* Re: [PATCH v4 4/5] remoteproc: qcom: Add support for mss remoteproc on SDM845
From: Bjorn Andersson @ 2018-05-18 21:31 UTC (permalink / raw)
To: Sibi Sankar
Cc: p.zabel, robh+dt, linux-remoteproc, linux-kernel, devicetree,
georgi.djakov, jassisinghbrar, ohad, mark.rutland, kyan,
sricharan, akdwived, linux-arm-msm, tsoni
In-Reply-To: <20180425150843.26657-5-sibis@codeaurora.org>
On Wed 25 Apr 08:08 PDT 2018, Sibi Sankar wrote:
> From SDM845, the Q6SS reset sequence on software side has been
> simplified with the introduction of boot FSM which assists in
> bringing the Q6 out of reset
>
> Add GLINK subdevice to allow definition of GLINK edge as a
> child of modem-pil
>
Please split this in two patches; one adding sdm845 and one adding the
glink subdev. You can squash in the addition of the compatible in the dt
binding into the sdm845 code patch, you wish as well.
Apart from that this looks good!
Regards,
Bjorn
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> drivers/remoteproc/qcom_q6v5_pil.c | 65 +++++++++++++++++++++++++++++-
> 1 file changed, 64 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/remoteproc/qcom_q6v5_pil.c b/drivers/remoteproc/qcom_q6v5_pil.c
> index 7e2d04d4f2f0..4d9504e8bf8e 100644
> --- a/drivers/remoteproc/qcom_q6v5_pil.c
> +++ b/drivers/remoteproc/qcom_q6v5_pil.c
> @@ -57,6 +57,8 @@
> #define RMB_PMI_META_DATA_REG 0x10
> #define RMB_PMI_CODE_START_REG 0x14
> #define RMB_PMI_CODE_LENGTH_REG 0x18
> +#define RMB_MBA_MSS_STATUS 0x40
> +#define RMB_MBA_ALT_RESET 0x44
>
> #define RMB_CMD_META_DATA_READY 0x1
> #define RMB_CMD_LOAD_READY 0x2
> @@ -104,6 +106,13 @@
> #define QDSP6SS_XO_CBCR 0x0038
> #define QDSP6SS_ACC_OVERRIDE_VAL 0x20
>
> +/* QDSP6v65 parameters */
> +#define QDSP6SS_SLEEP 0x3C
> +#define QDSP6SS_BOOT_CORE_START 0x400
> +#define QDSP6SS_BOOT_CMD 0x404
> +#define SLEEP_CHECK_MAX_LOOPS 200
> +#define BOOT_FSM_TIMEOUT 10000
> +
> struct reg_info {
> struct regulator *reg;
> int uV;
> @@ -170,6 +179,7 @@ struct q6v5 {
> void *mpss_region;
> size_t mpss_size;
>
> + struct qcom_rproc_glink glink_subdev;
> struct qcom_rproc_subdev smd_subdev;
> struct qcom_rproc_ssr ssr_subdev;
> struct qcom_sysmon *sysmon;
> @@ -184,6 +194,7 @@ enum {
> MSS_MSM8916,
> MSS_MSM8974,
> MSS_MSM8996,
> + MSS_SDM845,
> };
>
> static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
> @@ -390,8 +401,35 @@ static int q6v5proc_reset(struct q6v5 *qproc)
> int ret;
> int i;
>
> + if (qproc->version == MSS_SDM845) {
>
> - if (qproc->version == MSS_MSM8996) {
> + val = readl(qproc->reg_base + QDSP6SS_SLEEP);
> + val |= 0x1;
> + writel(val, qproc->reg_base + QDSP6SS_SLEEP);
> +
> + ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
> + val, !(val & BIT(31)), 1,
> + SLEEP_CHECK_MAX_LOOPS);
> + if (ret) {
> + dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
> + return -ETIMEDOUT;
> + }
> +
> + /* De-assert QDSP6 stop core */
> + writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
> + /* Trigger boot FSM */
> + writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
> +
> + ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
> + val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
> + if (ret) {
> + dev_err(qproc->dev, "Boot FSM failed to complete.\n");
> + return ret;
> + }
> +
> + goto pbl_wait;
> +
> + } else if (qproc->version == MSS_MSM8996) {
> /* Override the ACC value if required */
> writel(QDSP6SS_ACC_OVERRIDE_VAL,
> qproc->reg_base + QDSP6SS_STRAP_ACC);
> @@ -499,6 +537,7 @@ static int q6v5proc_reset(struct q6v5 *qproc)
> val &= ~Q6SS_STOP_CORE;
> writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
>
> +pbl_wait:
> /* Wait for PBL status */
> ret = q6v5_rmb_pbl_wait(qproc, 1000);
> if (ret == -ETIMEDOUT) {
> @@ -1256,6 +1295,7 @@ static int q6v5_probe(struct platform_device *pdev)
> }
> qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
> qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
> + qcom_add_glink_subdev(rproc, &qproc->glink_subdev);
> qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
> qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
> qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
> @@ -1279,6 +1319,7 @@ static int q6v5_remove(struct platform_device *pdev)
> rproc_del(qproc->rproc);
>
> qcom_remove_sysmon_subdev(qproc->sysmon);
> + qcom_remove_glink_subdev(qproc->rproc, &qproc->glink_subdev);
> qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev);
> qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev);
> rproc_free(qproc->rproc);
> @@ -1286,6 +1327,27 @@ static int q6v5_remove(struct platform_device *pdev)
> return 0;
> }
>
> +static const struct rproc_hexagon_res sdm845_mss = {
> + .hexagon_mba_image = "mba.mbn",
> + .proxy_clk_names = (char*[]){
> + "xo",
> + "axis2",
> + "prng",
> + NULL
> + },
> + .active_clk_names = (char*[]){
> + "iface",
> + "bus",
> + "mem",
> + "gpll0_mss",
> + "snoc_axi",
> + "mnoc_axi",
> + NULL
> + },
> + .need_mem_protection = true,
> + .version = MSS_SDM845,
> +};
> +
> static const struct rproc_hexagon_res msm8996_mss = {
> .hexagon_mba_image = "mba.mbn",
> .proxy_clk_names = (char*[]){
> @@ -1379,6 +1441,7 @@ static const struct of_device_id q6v5_of_match[] = {
> { .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
> { .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
> { .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
> + { .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
> { },
> };
> MODULE_DEVICE_TABLE(of, q6v5_of_match);
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
^ permalink raw reply
* Re: [PATCH v3 1/2] dt-bindings: add MediaTek XS-PHY binding
From: Rob Herring @ 2018-05-18 21:29 UTC (permalink / raw)
To: Chunfeng Yun
Cc: Kishon Vijay Abraham I, Matthias Brugger, Mark Rutland,
Ian Campbell, Ryder Lee, linux-kernel, linux-arm-kernel,
linux-usb, linux-mediatek, devicetree
In-Reply-To: <1525932629-10603-2-git-send-email-chunfeng.yun@mediatek.com>
On Thu, May 10, 2018 at 02:10:28PM +0800, Chunfeng Yun wrote:
> Add a DT binding documentation of XS-PHY for MediaTek SoCs
> with USB3.1 GEN2 controller
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> .../devicetree/bindings/phy/phy-mtk-xsphy.txt | 110 ++++++++++++++++++++
> 1 file changed, 110 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [v4 3/6] dt-bindings: fsl-qdma: Add NXP Layerscpae qDMA controller bindings
From: Rob Herring @ 2018-05-18 21:26 UTC (permalink / raw)
To: Wen He
Cc: vinod.koul, dmaengine, devicetree, leoyang.li, jiafei.pan,
jiaheng.fan
In-Reply-To: <20180514120307.15592-3-wen.he_1@nxp.com>
On Mon, May 14, 2018 at 08:03:04PM +0800, Wen He wrote:
> Document the devicetree bindings for NXP Layerscape qDMA controller
> which could be found on NXP QorIQ Layerscape SoCs.
>
> Signed-off-by: Wen He <wen.he_1@nxp.com>
> ---
> change in v4:
> - Rewrite the bindings document that follows generic DMA bindings file
>
> change in v3:
> - no change
>
> change in v2:
> - Remove indentation
> - Add "Should be" before 'fsl,ls1021a-qdma'
> - Replace 'channels' by 'dma-channels'
> - Replace 'qdma@8390000' by 'dma-controller@8390000'
>
> Documentation/devicetree/bindings/dma/fsl-qdma.txt | 41 ++++++++++++++++++++
> 1 files changed, 41 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/dma/fsl-qdma.txt
>
> diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
> new file mode 100644
> index 0000000..368c4e7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt
> @@ -0,0 +1,41 @@
> +NXP Layerscape SoC qDMA Controller
> +==================================
> +
> +This device follows the generic DMA bindings defined in dma/dma.txt.
> +
> +Required properties:
> +
> +- compatible: Must be one of
> + "fsl,ls1021a-qdma": for LS1021A Board
> + "fsl,ls1043a-qdma": for ls1043A Board
> + "fsl,ls1046a-qdma": for ls1046A Board
> +- reg: Should contain the register's base address and length.
> +- interrupts: Should contain a reference to the interrupt used by this
> + device.
> +- interrupt-names: Should contain interrupt names:
> + "qdma-error": the error interrupt
> + "qdma-queue": the queue interrupt
> +- queues: Should contain number of queues supported.
Needs a vendor prefix.
> +
> +Optional properties:
> +
> +- dma-channels: Number of DMA channels supported by the controller.
> +- big-endian: If present registers and hardware scatter/gather descriptors
> + of the qDMA are implemented in big endian mode, otherwise in little
> + mode.
> +
> +Examples:
> +
> + qdma: dma-controller@8390000 {
> + compatible = "fsl,ls1021a-qdma";
> + reg = <0x0 0x8398000 0x0 0x2000 /* Controller registers */
> + 0x0 0x839a000 0x0 0x2000>; /* Block registers */
> + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "qdma-error", "qdma-queue";
> + dma-channels = <8>;
> + queues = <2>;
> + big-endian;
> + };
> +
> +DMA clients must use the format described in dma/dma.txt file.
> --
> 1.7.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* RE: [PATCH 1/2] dt-bindings: power: Add ZynqMP power domain bindings
From: Jolly Shah @ 2018-05-18 21:18 UTC (permalink / raw)
To: Marek Szyprowski
Cc: Matthias Brugger, Andy Gross, Shawn Guo, Geert Uytterhoeven,
Björn Andersson, sean.wang@mediatek.com, Michal Simek,
Mark Rutland, Rajan Vaja,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux ARM, Linux Kernel Mailing List, Geert Uytterhoeven,
Rob Herring
In-Reply-To: <be5cecb2-3d0d-22f8-48a2-f94ed9546e04@samsung.com>
Hi Marek,
> -----Original Message-----
> From: Marek Szyprowski [mailto:m.szyprowski@samsung.com]
> Sent: Thursday, May 17, 2018 11:31 PM
> To: Jolly Shah <JOLLYS@xilinx.com>; Geert Uytterhoeven <geert@linux-
> m68k.org>; Rob Herring <robh@kernel.org>
> Cc: Matthias Brugger <matthias.bgg@gmail.com>; Andy Gross
> <andy.gross@linaro.org>; Shawn Guo <shawnguo@kernel.org>; Geert
> Uytterhoeven <geert+renesas@glider.be>; Björn Andersson
> <bjorn.andersson@linaro.org>; sean.wang@mediatek.com; Michal Simek
> <michal.simek@xilinx.com>; Mark Rutland <mark.rutland@arm.com>; Rajan
> Vaja <RAJANV@xilinx.com>; open list:OPEN FIRMWARE AND FLATTENED
> DEVICE TREE BINDINGS <devicetree@vger.kernel.org>; Linux ARM <linux-arm-
> kernel@lists.infradead.org>; Linux Kernel Mailing List <linux-
> kernel@vger.kernel.org>
> Subject: Re: [PATCH 1/2] dt-bindings: power: Add ZynqMP power domain
> bindings
>
> Hi Jolly,
>
> On 2018-05-17 23:10, Jolly Shah wrote:
>
> >>>>>> +Example:
> >>>>>> + zynqmp-genpd {
> >>>>>> + compatible = "xlnx,zynqmp-genpd";
> >>>>> What's the control interface for controlling the domains?
> >>>>>> +
> >>>>>> + pd_usb0: pd-usb0 {
> >>>>>> + pd-id = <22>;
> >>>>>> + #power-domain-cells = <0>;
> >>>>> There's no need for all these sub nodes. Make #power-domain-cells
> >>>>> 1 and put the id in the cell value.
> >>>> That was my first reaction, too...
> >>>>>> + };
> >>>>>> +
> >>>>>> + pd_sata: pd-sata {
> >>>>>> + pd-id = <28>;
> >>>>>> + #power-domain-cells = <0>;
> >>>>>> + };
> >>>>>> +
> >>>>>> + pd_gpu: pd-gpu {
> >>>>>> + pd-id = <58 20 21>;
> >>>> ... until I saw the above.
> >>>> Controlling the GPU power area requires controlling 3 physical areas?
> >>>>
> >>>> However, doing it this way may bite you in the future, if a need
> >>>> arises to control a subset. And what about power up/down order?
> >>> What about defining 3 separate domains and arranging them in
> >>> parent-child relationship? generic power domains already supports
> >>> that and this allows to nicely define the power on/off order.
> >>>
> >>>>>> + #power-domain-cells = <0x0>;
> >>>>>> + };
> >>>>>> + };
> >> I agree it should be arranged in as parent child order to control
> >> subset or control order. Will incorporate those changes in next version.
> >
> > As suggested, I tried out parent, child approach. However what I found is
> Genpd core takes care of parent child dependencies for power on off routines
> only. In our case, We need them in attach-detach routines too. In that case, we
> need to handle dependencies manually for those routines. Please suggest better
> approach, if any.
>
> What do you mean to handle attach-detach?
>
> Best regards
> --
> Marek Szyprowski, PhD
> Samsung R&D Institute Poland
For our power domain driver, we request usage of these nodes in attach routines and power them on in power on routine. So for below specific case, when attach_dev is called, all 3 nodes need to be requested.
> >>>>>> + pd_gpu: pd-gpu {
> >>>>>> + pd-id = <58 20 21>;
Thanks,
Jolly Shah
^ permalink raw reply
* Re: [PATCH v7 2/2] drivers: soc: Add LLCC driver
From: Andy Shevchenko @ 2018-05-18 21:01 UTC (permalink / raw)
To: Rishabh Bhatnagar
Cc: linux-arm Mailing List, linux-arm-msm, devicetree,
Linux Kernel Mailing List, linux-arm, tsoni, ckadabi, evgreen,
Rob Herring
In-Reply-To: <1526492623-20527-3-git-send-email-rishabhb@codeaurora.org>
On Wed, May 16, 2018 at 8:43 PM, Rishabh Bhatnagar
<rishabhb@codeaurora.org> wrote:
> LLCC (Last Level Cache Controller) provides additional cache memory
> in the system. LLCC is partitioned into multiple slices and each
> slice gets its own priority, size, ID and other config parameters.
> LLCC driver programs these parameters for each slice. Clients that
> are assigned to use LLCC need to get information such size & ID of the
> slice they get and activate or deactivate the slice as needed. LLCC driver
> provides API for the clients to perform these operations.
> +static const struct of_device_id sdm845_qcom_llcc_of_match[] = {
> + { .compatible = "qcom,sdm845-llcc", },
> + { },
Slightly better w/o comma
> +};
> +static struct platform_driver sdm845_qcom_llcc_driver = {
> + .driver = {
> + .name = "sdm845-llcc",
> + .owner = THIS_MODULE,
No need. See below.
> + .of_match_table = sdm845_qcom_llcc_of_match,
> + },
> + .probe = sdm845_qcom_llcc_probe,
> +};
> +
> +static int __init sdm845_init_qcom_llcc_init(void)
> +{
> + return platform_driver_register(&sdm845_qcom_llcc_driver);
> +}
> +module_init(sdm845_init_qcom_llcc_init);
> +
> +static void __exit sdm845_exit_qcom_llcc_exit(void)
> +{
> + platform_driver_unregister(&sdm845_qcom_llcc_driver);
> +}
> +module_exit(sdm845_exit_qcom_llcc_exit);
Why not to use module_platform_driver() macro?
> +#define ACTIVATE 0x1
> +#define DEACTIVATE 0x2
> +#define ACT_CTRL_OPCODE_ACTIVATE 0x1
> +#define ACT_CTRL_OPCODE_DEACTIVATE 0x2
> +#define ACT_CTRL_ACT_TRIG 0x1
Are these bits? Perhaps BIT() ?
> +#define ACT_CTRL_OPCODE_SHIFT 0x1
> +#define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x2
> +#define ATTR1_FIXED_SIZE_SHIFT 0x3
> +#define ATTR1_PRIORITY_SHIFT 0x4
> +#define ATTR1_MAX_CAP_SHIFT 0x10
Better to use fixed size pattern, i.e. 0x01, 0x02, 0x03, 0x04, 0x10.
> +#define ATTR0_RES_WAYS_MASK 0x00000fff
> +#define ATTR0_BONUS_WAYS_MASK 0x0fff0000
GENMASK()
> +#define LLCC_LB_CNT_MASK 0xf0000000
Ditto.
> +#define MAX_CAP_TO_BYTES(n) (n * 1024)
(n * SZ_1K) ?
> +#define LLCC_TRP_ACT_CTRLn(n) (n * 0x1000)
SZ_4K ?
> +#define LLCC_TRP_STATUSn(n) (4 + n * 0x1000)
Ditto.
> +struct llcc_slice_desc *llcc_slice_getd(u32 uid)
> +{
> + const struct llcc_slice_config *cfg;
> + struct llcc_slice_desc *desc;
> + u32 sz, count = 0;
> +
> + cfg = drv_data->cfg;
> + sz = drv_data->cfg_size;
> +
> + while (cfg && count < sz) {
> + if (cfg->usecase_id == uid)
> + break;
> + cfg++;
> + count++;
> + }
> + if (cfg == NULL || count == sz)
> + return ERR_PTR(-ENODEV);
if (!cfg)
return ERR_PTR(-ENODEV);
while (cfg->... != uid) {
cfg++;
count++;
}
if (count == sz)
return ...
Though I would rather put it to for () loop.
> +static int llcc_update_act_ctrl(u32 sid,
> + u32 act_ctrl_reg_val, u32 status)
> +{
> + u32 act_ctrl_reg;
> + u32 status_reg;
> + u32 slice_status;
> + int ret = 0;
Useless assignment. Check entire patch series for a such.
> + ret = regmap_read_poll_timeout(drv_data->regmap, status_reg,
> + slice_status, !(slice_status & status), 0, LLCC_STATUS_READ_DELAY);
Wrong indentation.
> + return ret;
> +}
> + ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
> + DEACTIVATE);
Perhaps one line (~83 characters here is OK) ?
> + ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
> + ACTIVATE);
Ditto.
> + attr1_cfg = bcast_off +
> + LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id);
> + attr0_cfg = bcast_off +
> + LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id);
Ditto.
> + attr1_val |= llcc_table[i].probe_target_ways <<
> + ATTR1_PROBE_TARGET_WAYS_SHIFT;
> + attr1_val |= llcc_table[i].fixed_size <<
> + ATTR1_FIXED_SIZE_SHIFT;
> + attr1_val |= llcc_table[i].priority << ATTR1_PRIORITY_SHIFT;
foo |=
bar << SHIFT;
would look slightly better.
> +int qcom_llcc_probe(struct platform_device *pdev,
> + const struct llcc_slice_config *llcc_cfg, u32 sz)
> +{
> + drv_data->offsets = devm_kzalloc(dev, num_banks * sizeof(u32),
> + GFP_KERNEL);
> + if (!drv_data->offsets)
> + return -ENOMEM;
devm_kcalloc() ?
> +
> + for (i = 0; i < num_banks; i++)
> + drv_data->offsets[i] = (i * BANK_OFFSET_STRIDE);
Pointless parens.
> + drv_data->bitmap = devm_kcalloc(dev,
> + BITS_TO_LONGS(drv_data->max_slices), sizeof(unsigned long),
> + GFP_KERNEL);
> + if (!drv_data->bitmap)
> + return -ENOMEM;
Perhaps at some point someone will add
bitmap_alloc()
devm_bitmap_alloc()
> + bitmap_zero(drv_data->bitmap, drv_data->max_slices);
Pointless
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH 1/2] slimbus: ngd: dt-bindings: Add slim ngd dt bindings
From: Trilok Soni @ 2018-05-18 20:47 UTC (permalink / raw)
To: Srinivas Kandagatla, gregkh, robh+dt
Cc: kramasub, sdharia, girishm, linux-kernel, mark.rutland, bgoswami,
devicetree, broonie, linux-arm-msm, alsa-devel
In-Reply-To: <20180516165118.16551-2-srinivas.kandagatla@linaro.org>
Hi Srinivas
On 5/16/2018 9:51 AM, Srinivas Kandagatla wrote:
> This patch adds bindings for Qualcomm SLIMBus NGD controller found in
> all new SoCs starting from B family.
"X/Y/Z family" has no meaning here in upstream and just put the
processor name from which you are adding the support or tested to start
with.
--
---Trilok Soni
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a
Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH] ARM: dts: da850-evm: Enable SATA port
From: Adam Ford @ 2018-05-18 20:43 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Adam Ford, devicetree, nsekhar, adam.ford, khilman
The DA850-EVM from Logic PD has a SATA port and the module that went
with the kit support it as well. This patch will enable the SATA
controller.
Signed-off-by: Adam Ford <aford173@gmail.com>
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index a76c2ddfd23e..afccbe7681e7 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -160,6 +160,10 @@
};
};
+&sata {
+ status = "okay";
+};
+
&serial0 {
status = "okay";
};
--
2.17.0
^ permalink raw reply related
* [PATCH V7] ARM: dts: da850-evm: Enable LCD and Backlight
From: Adam Ford @ 2018-05-18 20:33 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Adam Ford, devicetree, nsekhar, khilman
When using the board files the LCD works, but not with the DT.
This adds enables the original da850-evm to work with the same
LCD in device tree mode.
The EVM has a gpio for the regulator and a PWM for dimming the
backlight. The LCD and the vpif display pins are mutually
exclusive, so if using the LCD, do not load the vpif driver.
Signed-off-by: Adam Ford <aford173@gmail.com>
---
V7: Missed one reference to backlight_reg->backlight_lcd
V6: Fix some whitespace and comment formatting. Rename backlight_reg to
backlight_lcd
V5: Resync against v4.18/dt
V4: Move the backlight to PWM, so the driver can control the regulator allowing the
regulator to power down and enabling the ability to change the brightness of the
backlight
V3: Fix errant GPIO, label GPIO pins, and rename the regulator to be more explict to
backlight which better matches the schematic. Updated the description to explain
that it cannot be used at the same time as the vpif driver.
V2: Add regulator and GPIO enable pins. Remove PWM backlight and replace with GPIO
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index 0e82bb988fde..a76c2ddfd23e 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -27,6 +27,60 @@
spi0 = &spi1;
};
+ backlight: backlight-pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ecap2_pins>;
+ power-supply = <&backlight_lcd>;
+ compatible = "pwm-backlight";
+ pwms = <&ecap2 0 50000 0>;
+ brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
+ default-brightness-level = <7>;
+ };
+
+ panel {
+ compatible = "ti,tilcdc,panel";
+ pinctrl-names = "default";
+ pinctrl-0 = <&lcd_pins>;
+ /*
+ * The vpif and the LCD are mutually exclusive.
+ * To enable VPIF, change the status below to 'disabled' then
+ * then change the status of the vpif below to 'okay'
+ */
+ status = "okay";
+ enable-gpios = <&gpio 40 GPIO_ACTIVE_HIGH>; /* lcd_panel_pwr */
+
+ panel-info {
+ ac-bias = <255>;
+ ac-bias-intrpt = <0>;
+ dma-burst-sz = <16>;
+ bpp = <16>;
+ fdd = <0x80>;
+ sync-edge = <0>;
+ sync-ctrl = <1>;
+ raster-order = <0>;
+ fifo-th = <0>;
+ };
+
+ display-timings {
+ native-mode = <&timing0>;
+ timing0: 480x272 {
+ clock-frequency = <9000000>;
+ hactive = <480>;
+ vactive = <272>;
+ hfront-porch = <3>;
+ hback-porch = <2>;
+ hsync-len = <42>;
+ vback-porch = <3>;
+ vfront-porch = <4>;
+ vsync-len = <11>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ de-active = <1>;
+ pixelclk-active = <1>;
+ };
+ };
+ };
+
vbat: fixedregulator0 {
compatible = "regulator-fixed";
regulator-name = "vbat";
@@ -35,6 +89,15 @@
regulator-boot-on;
};
+ backlight_lcd: backlight-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "lcd_backlight_pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio 47 GPIO_ACTIVE_HIGH>; /* lcd_backlight_pwr */
+ enable-active-high;
+ };
+
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "DA850/OMAP-L138 EVM";
@@ -63,6 +126,10 @@
};
};
+&ecap2 {
+ status = "okay";
+};
+
&pmx_core {
status = "okay";
@@ -109,6 +176,10 @@
status = "okay";
};
+&lcdc {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
clock-frequency = <100000>;
@@ -336,5 +407,10 @@
&vpif {
pinctrl-names = "default";
pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>;
- status = "okay";
+ /*
+ * The vpif and the LCD are mutually exclusive.
+ * To enable VPIF, disable the ti,tilcdc,panel then
+ * changed the status below to 'okay'
+ */
+ status = "disabled";
};
--
2.17.0
^ permalink raw reply related
* Re: [PATCH v7 2/2] PCI: mediatek: Using chained IRQ to setup IRQ handle
From: Bjorn Helgaas @ 2018-05-18 19:51 UTC (permalink / raw)
To: honghui.zhang
Cc: lorenzo.pieralisi, marc.zyngier, bhelgaas, matthias.bgg,
linux-arm-kernel, linux-mediatek, linux-pci, linux-kernel,
devicetree, yingjoe.chen, eddie.huang, ryder.lee, hongkun.cao,
youlin.pei, yong.wu, yt.shen, sean.wang, xinping.qian
In-Reply-To: <1525412853-24367-3-git-send-email-honghui.zhang@mediatek.com>
On Fri, May 04, 2018 at 01:47:33PM +0800, honghui.zhang@mediatek.com wrote:
> From: Honghui Zhang <honghui.zhang@mediatek.com>
>
> Using irq_chip solution to setup IRQs in order to consist
> with IRQ framework.
>
> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
> Acked-by: Ryder Lee <ryder.lee@mediatek.com>
> ---
> drivers/pci/host/pcie-mediatek.c | 206 ++++++++++++++++++++++-----------------
> 1 file changed, 115 insertions(+), 91 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c
> index c3dc549..dabf1086 100644
> --- a/drivers/pci/host/pcie-mediatek.c
> +++ b/drivers/pci/host/pcie-mediatek.c
> ...
> -static int mtk_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
> - irq_hw_number_t hwirq)
> +static struct msi_domain_info mtk_msi_domain_info = {
I think this patch should be amended to include this:
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 0d0177ce436c..368b70d9371b 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -193,7 +193,7 @@ config PCIE_MEDIATEK
bool "MediaTek PCIe controller"
depends on (ARM || ARM64) && (ARCH_MEDIATEK || COMPILE_TEST)
depends on OF
- depends on PCI
+ depends on PCI_MSI_IRQ_DOMAIN
select PCIEPORTBUS
help
Say Y here if you want to enable PCIe controller support on
Lorenzo, if you want to fold that in and update your branch, I can pull it.
If not, I can add a patch on top, which should only break compile-testing
bisection.
^ permalink raw reply related
* [PATCH 2/2] arm64: dts: renesas: v3hsk: add GEther support
From: Sergei Shtylyov @ 2018-05-18 19:46 UTC (permalink / raw)
To: Rob Herring, Catalin Marinas, Will Deacon, Simon Horman,
devicetree, linux-renesas-soc
Cc: Mark Rutland, Magnus Damm, linux-arm-kernel
In-Reply-To: <a4230699-e46f-0782-e3b1-22d58b9033c8@cogentembedded.com>
Define the V3H Starter Kit board dependent part of the GEther device node.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
@@ -15,6 +15,7 @@
aliases {
serial0 = &scif0;
+ ethernet0 = &gether;
};
chosen {
@@ -36,7 +37,27 @@
clock-frequency = <32768>;
};
+&gether {
+ pinctrl-0 = <&gether_pins>;
+ pinctrl-names = "default";
+
+ phy-mode = "rgmii";
+ phy-handle = <&phy0>;
+ renesas,no-ether-link;
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
&pfc {
+ gether_pins: gether {
+ groups = "gether_mdio_a", "gether_rgmii",
+ "gether_txcrefclk", "gether_txcrefclk_mega";
+ function = "gether";
+ };
+
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
^ permalink raw reply
* [PATCH 1/2] arm64: dts: renesas: r8a77980: add GEther support
From: Sergei Shtylyov @ 2018-05-18 19:45 UTC (permalink / raw)
To: Rob Herring, Catalin Marinas, Will Deacon, Simon Horman,
devicetree, linux-renesas-soc
Cc: Mark Rutland, Magnus Damm, linux-arm-kernel
In-Reply-To: <a4230699-e46f-0782-e3b1-22d58b9033c8@cogentembedded.com>
Define the generic R8A77980 part of the GEther device node.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -417,6 +417,17 @@
dma-channels = <16>;
};
+ gether: ethernet@e7400000 {
+ compatible = "renesas,gether-r8a77980";
+ reg = <0 0xe7400000 0 0x1000>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
mmc0: mmc@ee140000 {
compatible = "renesas,sdhi-r8a77980",
"renesas,rcar-gen3-sdhi";
^ permalink raw reply
* [PATCH 0/2] Add R8A77980/V3HSK GEther support
From: Sergei Shtylyov @ 2018-05-18 19:37 UTC (permalink / raw)
To: Rob Herring, Catalin Marinas, Will Deacon, Simon Horman,
devicetree, linux-renesas-soc
Cc: Mark Rutland, Magnus Damm, linux-arm-kernel
Hello!
Here's the set of 2 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-20180518-v4.17-rc5' tag plus the R8A77980 SMP support patch.
I'm adding the device tree support for mounting the NFS root on the R8A77980-
based V3H Starter Kit board. The 'sh_eth' driver patches adding R8A77980
GEther support patches needed for these 2 patches to work have been posted
and are close to be merged...
[1/2] arm64: dts: renesas: r8a77980: add GEther support
[2/2] arm64: dts: renesas: v3hsk: add GEther support
WBR, Sergei
^ permalink raw reply
* [PATCH] arm64: dts: stingray: use NUM_SATA to configure number of sata ports
From: Scott Branden @ 2018-05-18 18:34 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon, Ray Jui
Cc: BCM Kernel Feedback, devicetree, linux-arm-kernel, linux-kernel,
Scott Branden
Move remaining sata configuration to stingray-sata.dtsi and enable
ports based on NUM_SATA defined.
Now, all that needs to be done is define NUM_SATA per board.
Signed-off-by: Scott Branden <scott.branden@broadcom.com>
---
.../boot/dts/broadcom/stingray/bcm958742-base.dtsi | 64 --------------------
.../boot/dts/broadcom/stingray/bcm958742k.dts | 2 +
.../boot/dts/broadcom/stingray/bcm958742t.dts | 2 +
.../boot/dts/broadcom/stingray/stingray-sata.dtsi | 68 ++++++++++++++++++++++
4 files changed, 72 insertions(+), 64 deletions(-)
diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
index 8862ec9..cacc25e 100644
--- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
+++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742-base.dtsi
@@ -72,70 +72,6 @@
<0x00000008 0x80000000 0x1 0x80000000>; /* 6G @ 34G */
};
-&sata0 {
- status = "okay";
-};
-
-&sata_phy0{
- status = "okay";
-};
-
-&sata1 {
- status = "okay";
-};
-
-&sata_phy1{
- status = "okay";
-};
-
-&sata2 {
- status = "okay";
-};
-
-&sata_phy2{
- status = "okay";
-};
-
-&sata3 {
- status = "okay";
-};
-
-&sata_phy3{
- status = "okay";
-};
-
-&sata4 {
- status = "okay";
-};
-
-&sata_phy4{
- status = "okay";
-};
-
-&sata5 {
- status = "okay";
-};
-
-&sata_phy5{
- status = "okay";
-};
-
-&sata6 {
- status = "okay";
-};
-
-&sata_phy6{
- status = "okay";
-};
-
-&sata7 {
- status = "okay";
-};
-
-&sata_phy7{
- status = "okay";
-};
-
&mdio_mux_iproc {
mdio@10 {
gphy0: eth-phy@10 {
diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts
index 77efa28..a515346 100644
--- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts
+++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742k.dts
@@ -32,6 +32,8 @@
/dts-v1/;
+#define NUM_SATA 8
+
#include "bcm958742-base.dtsi"
/ {
diff --git a/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts b/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts
index 5084b03..6a4d19e 100644
--- a/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts
+++ b/arch/arm64/boot/dts/broadcom/stingray/bcm958742t.dts
@@ -32,6 +32,8 @@
/dts-v1/;
+#define NUM_SATA 8
+
#include "bcm958742-base.dtsi"
/ {
diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi
index 8c68e0c..7f6d176 100644
--- a/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi
+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray-sata.dtsi
@@ -43,7 +43,11 @@
interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+#if (NUM_SATA > 0)
+ status = "okay";
+#else
status = "disabled";
+#endif
sata0_port0: sata-port@0 {
reg = <0>;
@@ -58,7 +62,11 @@
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
+#if (NUM_SATA > 0)
+ status = "okay";
+#else
status = "disabled";
+#endif
sata0_phy0: sata-phy@0 {
reg = <0>;
@@ -73,7 +81,11 @@
interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+#if (NUM_SATA > 1)
+ status = "okay";
+#else
status = "disabled";
+#endif
sata1_port0: sata-port@0 {
reg = <0>;
@@ -88,7 +100,11 @@
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
+#if (NUM_SATA > 1)
+ status = "okay";
+#else
status = "disabled";
+#endif
sata1_phy0: sata-phy@0 {
reg = <0>;
@@ -103,7 +119,11 @@
interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+#if (NUM_SATA > 2)
+ status = "okay";
+#else
status = "disabled";
+#endif
sata2_port0: sata-port@0 {
reg = <0>;
@@ -118,7 +138,11 @@
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
+#if (NUM_SATA > 2)
+ status = "okay";
+#else
status = "disabled";
+#endif
sata2_phy0: sata-phy@0 {
reg = <0>;
@@ -133,7 +157,11 @@
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+#if (NUM_SATA > 3)
+ status = "okay";
+#else
status = "disabled";
+#endif
sata3_port0: sata-port@0 {
reg = <0>;
@@ -148,7 +176,11 @@
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
+#if (NUM_SATA > 3)
+ status = "okay";
+#else
status = "disabled";
+#endif
sata3_phy0: sata-phy@0 {
reg = <0>;
@@ -163,7 +195,11 @@
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+#if (NUM_SATA > 4)
+ status = "okay";
+#else
status = "disabled";
+#endif
sata4_port0: sata-port@0 {
reg = <0>;
@@ -178,7 +214,11 @@
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
+#if (NUM_SATA > 4)
+ status = "okay";
+#else
status = "disabled";
+#endif
sata4_phy0: sata-phy@0 {
reg = <0>;
@@ -193,7 +233,11 @@
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+#if (NUM_SATA > 5)
+ status = "okay";
+#else
status = "disabled";
+#endif
sata5_port0: sata-port@0 {
reg = <0>;
@@ -208,7 +252,11 @@
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
+#if (NUM_SATA > 5)
+ status = "okay";
+#else
status = "disabled";
+#endif
sata5_phy0: sata-phy@0 {
reg = <0>;
@@ -223,7 +271,11 @@
interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+#if (NUM_SATA > 6)
+ status = "okay";
+#else
status = "disabled";
+#endif
sata6_port0: sata-port@0 {
reg = <0>;
@@ -238,7 +290,11 @@
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
+#if (NUM_SATA > 6)
+ status = "okay";
+#else
status = "disabled";
+#endif
sata6_phy0: sata-phy@0 {
reg = <0>;
@@ -253,7 +309,11 @@
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+#if (NUM_SATA > 7)
+ status = "okay";
+#else
status = "disabled";
+#endif
sata7_port0: sata-port@0 {
reg = <0>;
@@ -268,11 +328,19 @@
reg-names = "phy";
#address-cells = <1>;
#size-cells = <0>;
+#if (NUM_SATA > 7)
+ status = "okay";
+#else
status = "disabled";
+#endif
sata7_phy0: sata-phy@0 {
reg = <0>;
#phy-cells = <0>;
};
};
+
+#if (NUM_SATA > 8)
+#error "NUM_SATA > 8"
+#endif
};
--
2.5.0
^ permalink raw reply related
* [PATCH v2 3/3] sh_eth: add R8A77980 support
From: Sergei Shtylyov @ 2018-05-18 18:32 UTC (permalink / raw)
To: netdev, devicetree, David S. Miller, Rob Herring
Cc: Mark Rutland, linux-renesas-soc
In-Reply-To: <f30c98ff-f6da-9e7f-c637-49076a428885@cogentembedded.com>
Finally, add support for the DT probing of the R-Car V3H (AKA R8A77980) --
it's the only R-Car gen3 SoC having the GEther controller -- others have
only EtherAVB...
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
---
Changes in version 2:
- added Simon's tag.
Documentation/devicetree/bindings/net/sh_eth.txt | 1
drivers/net/ethernet/renesas/sh_eth.c | 44 +++++++++++++++++++++++
2 files changed, 45 insertions(+)
Index: net-next/Documentation/devicetree/bindings/net/sh_eth.txt
===================================================================
--- net-next.orig/Documentation/devicetree/bindings/net/sh_eth.txt
+++ net-next/Documentation/devicetree/bindings/net/sh_eth.txt
@@ -14,6 +14,7 @@ Required properties:
"renesas,ether-r8a7791" if the device is a part of R8A7791 SoC.
"renesas,ether-r8a7793" if the device is a part of R8A7793 SoC.
"renesas,ether-r8a7794" if the device is a part of R8A7794 SoC.
+ "renesas,gether-r8a77980" if the device is a part of R8A77980 SoC.
"renesas,ether-r7s72100" if the device is a part of R7S72100 SoC.
"renesas,rcar-gen1-ether" for a generic R-Car Gen1 device.
"renesas,rcar-gen2-ether" for a generic R-Car Gen2 or RZ/G1
Index: net-next/drivers/net/ethernet/renesas/sh_eth.c
===================================================================
--- net-next.orig/drivers/net/ethernet/renesas/sh_eth.c
+++ net-next/drivers/net/ethernet/renesas/sh_eth.c
@@ -753,6 +753,49 @@ static struct sh_eth_cpu_data rcar_gen2_
.rmiimode = 1,
.magic = 1,
};
+
+/* R8A77980 */
+static struct sh_eth_cpu_data r8a77980_data = {
+ .soft_reset = sh_eth_soft_reset_gether,
+
+ .set_duplex = sh_eth_set_duplex,
+ .set_rate = sh_eth_set_rate_gether,
+
+ .register_type = SH_ETH_REG_GIGABIT,
+
+ .edtrr_trns = EDTRR_TRNS_GETHER,
+ .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
+ .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
+ ECSIPR_MPDIP,
+ .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
+ EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
+ EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
+ EESIPR_RMAFIP | EESIPR_RRFIP |
+ EESIPR_RTLFIP | EESIPR_RTSFIP |
+ EESIPR_PREIP | EESIPR_CERFIP,
+
+ .tx_check = EESR_FTC | EESR_CD | EESR_RTO,
+ .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
+ EESR_RFE | EESR_RDE | EESR_RFRMER |
+ EESR_TFE | EESR_TDE | EESR_ECI,
+ .fdr_value = 0x0000070f,
+
+ .apr = 1,
+ .mpr = 1,
+ .tpauser = 1,
+ .bculr = 1,
+ .hw_swap = 1,
+ .nbst = 1,
+ .rpadir = 1,
+ .rpadir_value = 2 << 16,
+ .no_trimd = 1,
+ .no_ade = 1,
+ .xdfar_rw = 1,
+ .hw_checksum = 1,
+ .select_mii = 1,
+ .magic = 1,
+ .cexcr = 1,
+};
#endif /* CONFIG_OF */
static void sh_eth_set_rate_sh7724(struct net_device *ndev)
@@ -3134,6 +3177,7 @@ static const struct of_device_id sh_eth_
{ .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data },
{ .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },
{ .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },
+ { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data },
{ .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
{ .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data },
{ .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data },
^ permalink raw reply
* [PATCH v2 2/3] sh_eth: add EDMR.NBST support
From: Sergei Shtylyov @ 2018-05-18 18:31 UTC (permalink / raw)
To: netdev, devicetree, David S. Miller, Rob Herring
Cc: Mark Rutland, linux-renesas-soc
In-Reply-To: <f30c98ff-f6da-9e7f-c637-49076a428885@cogentembedded.com>
The R-Car V3H (AKA R8A77980) GEther controller adds the DMA burst mode bit
(NBST) in EDMR and the manual tells to always set it before doing any DMA.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
---
Changes in version 2:
- added Simon's tag.
drivers/net/ethernet/renesas/sh_eth.c | 4 ++++
drivers/net/ethernet/renesas/sh_eth.h | 2 ++
2 files changed, 6 insertions(+)
Index: net-next/drivers/net/ethernet/renesas/sh_eth.c
===================================================================
--- net-next.orig/drivers/net/ethernet/renesas/sh_eth.c
+++ net-next/drivers/net/ethernet/renesas/sh_eth.c
@@ -1434,6 +1434,10 @@ static int sh_eth_dev_init(struct net_de
sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
+ /* DMA transfer burst mode */
+ if (mdp->cd->nbst)
+ sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST);
+
if (mdp->cd->bculr)
sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
Index: net-next/drivers/net/ethernet/renesas/sh_eth.h
===================================================================
--- net-next.orig/drivers/net/ethernet/renesas/sh_eth.h
+++ net-next/drivers/net/ethernet/renesas/sh_eth.h
@@ -184,6 +184,7 @@ enum GECMR_BIT {
/* EDMR */
enum DMAC_M_BIT {
+ EDMR_NBST = 0x80,
EDMR_EL = 0x40, /* Litte endian */
EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
EDMR_SRST_GETHER = 0x03,
@@ -505,6 +506,7 @@ struct sh_eth_cpu_data {
unsigned bculr:1; /* EtherC have BCULR */
unsigned tsu:1; /* EtherC have TSU */
unsigned hw_swap:1; /* E-DMAC have DE bit in EDMR */
+ unsigned nbst:1; /* E-DMAC has NBST bit in EDMR */
unsigned rpadir:1; /* E-DMAC have RPADIR */
unsigned no_trimd:1; /* E-DMAC DO NOT have TRIMD */
unsigned no_ade:1; /* E-DMAC DO NOT have ADE bit in EESR */
^ permalink raw reply
* [PATCH v2 0/3] Add Renesas R8A77980 GEther support
From: Sergei Shtylyov @ 2018-05-18 18:28 UTC (permalink / raw)
To: netdev, devicetree, David S. Miller, Rob Herring
Cc: Mark Rutland, linux-renesas-soc
Hello!
Here's a set of 3 patches against DaveM's 'net-next.git' repo. They (gradually)
add R8A77980 GEther support to the 'sh_eth' driver, starting with couple new
register bits/values introduced with this chip, and ending with adding a new
'struct sh_eth_cpu_data' instance connected to the new DT "compatible" prop
value...
[1/1] sh_eth: add RGMII support
[2/3] sh_eth: add EDMR.NBST support
[3/3] sh_eth: add R8A77980 support
MBR, Sergei
^ permalink raw reply
* [PATCH v4 12/12] staging: iio: ad2s1200: Move driver out of staging
From: David Veenstra @ 2018-05-18 18:23 UTC (permalink / raw)
To: jic23, lars, pmeerw, robh+dt
Cc: linux-iio, devel, devicetree, Michael.Hennerich, knaack.h
In-Reply-To: <cover.1526667118.git.davidjulianveenstra@gmail.com>
Move the iio driver for the ad2s1200 and ad2s1205 resolver-to-digital
converter out of staging, into mainline iio subsystems.
Signed-off-by: David Veenstra <davidjulianveenstra@gmail.com>
---
drivers/iio/Kconfig | 1 +
drivers/iio/Makefile | 1 +
drivers/iio/resolver/Kconfig | 17 ++
drivers/iio/resolver/Makefile | 5 +
drivers/iio/resolver/ad2s1200.c | 210 ++++++++++++++++++++++++
drivers/staging/iio/resolver/Kconfig | 12 --
drivers/staging/iio/resolver/Makefile | 1 -
drivers/staging/iio/resolver/ad2s1200.c | 210 ------------------------
8 files changed, 234 insertions(+), 223 deletions(-)
create mode 100644 drivers/iio/resolver/Kconfig
create mode 100644 drivers/iio/resolver/Makefile
create mode 100644 drivers/iio/resolver/ad2s1200.c
delete mode 100644 drivers/staging/iio/resolver/ad2s1200.c
diff --git a/drivers/iio/Kconfig b/drivers/iio/Kconfig
index d69e85a8bdc3..d08aeb41cd07 100644
--- a/drivers/iio/Kconfig
+++ b/drivers/iio/Kconfig
@@ -93,6 +93,7 @@ source "drivers/iio/potentiometer/Kconfig"
source "drivers/iio/potentiostat/Kconfig"
source "drivers/iio/pressure/Kconfig"
source "drivers/iio/proximity/Kconfig"
+source "drivers/iio/resolver/Kconfig"
source "drivers/iio/temperature/Kconfig"
endif # IIO
diff --git a/drivers/iio/Makefile b/drivers/iio/Makefile
index d8cba9c229c0..cb5993251381 100644
--- a/drivers/iio/Makefile
+++ b/drivers/iio/Makefile
@@ -36,5 +36,6 @@ obj-y += potentiometer/
obj-y += potentiostat/
obj-y += pressure/
obj-y += proximity/
+obj-y += resolver/
obj-y += temperature/
obj-y += trigger/
diff --git a/drivers/iio/resolver/Kconfig b/drivers/iio/resolver/Kconfig
new file mode 100644
index 000000000000..2ced9f22aa70
--- /dev/null
+++ b/drivers/iio/resolver/Kconfig
@@ -0,0 +1,17 @@
+#
+# Resolver/Synchro drivers
+#
+menu "Resolver to digital converters"
+
+config AD2S1200
+ tristate "Analog Devices ad2s1200/ad2s1205 driver"
+ depends on SPI
+ depends on GPIOLIB || COMPILE_TEST
+ help
+ Say yes here to build support for Analog Devices spi resolver
+ to digital converters, ad2s1200 and ad2s1205, provides direct access
+ via sysfs.
+
+ To compile this driver as a module, choose M here: the
+ module will be called ad2s1200.
+endmenu
diff --git a/drivers/iio/resolver/Makefile b/drivers/iio/resolver/Makefile
new file mode 100644
index 000000000000..4e1dccae07e7
--- /dev/null
+++ b/drivers/iio/resolver/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for Resolver/Synchro drivers
+#
+
+obj-$(CONFIG_AD2S1200) += ad2s1200.o
diff --git a/drivers/iio/resolver/ad2s1200.c b/drivers/iio/resolver/ad2s1200.c
new file mode 100644
index 000000000000..28e618af9939
--- /dev/null
+++ b/drivers/iio/resolver/ad2s1200.c
@@ -0,0 +1,210 @@
+/*
+ * ad2s1200.c simple support for the ADI Resolver to Digital Converters:
+ * AD2S1200/1205
+ *
+ * Copyright (c) 2018-2018 David Veenstra <davidjulianveenstra@gmail.com>
+ * Copyright (c) 2010-2010 Analog Devices Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/spi/spi.h>
+#include <linux/sysfs.h>
+#include <linux/types.h>
+
+#include <linux/iio/iio.h>
+#include <linux/iio/sysfs.h>
+
+#define DRV_NAME "ad2s1200"
+
+/* input clock on serial interface */
+#define AD2S1200_HZ 8192000
+/* clock period in nano second */
+#define AD2S1200_TSCLK (1000000000 / AD2S1200_HZ)
+
+/**
+ * struct ad2s1200_state - driver instance specific data.
+ * @lock: protects both the GPIO pins and the rx buffer.
+ * @sdev: spi device.
+ * @sample: GPIO pin SAMPLE.
+ * @rdvel: GPIO pin RDVEL.
+ * @rx: buffer for spi transfers.
+ */
+struct ad2s1200_state {
+ struct mutex lock;
+ struct spi_device *sdev;
+ struct gpio_desc *sample;
+ struct gpio_desc *rdvel;
+ __be16 rx ____cacheline_aligned;
+};
+
+static int ad2s1200_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val,
+ int *val2,
+ long m)
+{
+ struct ad2s1200_state *st = iio_priv(indio_dev);
+ int ret;
+
+ switch (m) {
+ case IIO_CHAN_INFO_SCALE:
+ switch (chan->type) {
+ case IIO_ANGL:
+ /* 2 * Pi / (2^12 - 1) ~= 0.001534355 */
+ *val = 0;
+ *val2 = 1534355;
+ return IIO_VAL_INT_PLUS_NANO;
+ case IIO_ANGL_VEL:
+ /* 2 * Pi ~= 6.283185 */
+ *val = 6;
+ *val2 = 283185;
+ return IIO_VAL_INT_PLUS_MICRO;
+ default:
+ return -EINVAL;
+ }
+ break;
+ case IIO_CHAN_INFO_RAW:
+ mutex_lock(&st->lock);
+ gpiod_set_value(st->sample, 0);
+
+ /* delay (6 * AD2S1200_TSCLK + 20) nano seconds */
+ udelay(1);
+ gpiod_set_value(st->sample, 1);
+ gpiod_set_value(st->rdvel, !!(chan->type == IIO_ANGL));
+
+ ret = spi_read(st->sdev, &st->rx, 2);
+ if (ret < 0) {
+ mutex_unlock(&st->lock);
+ return ret;
+ }
+
+ switch (chan->type) {
+ case IIO_ANGL:
+ *val = be16_to_cpup(&st->rx) >> 4;
+ break;
+ case IIO_ANGL_VEL:
+ *val = sign_extend32(be16_to_cpup(&st->rx) >> 4, 11);
+ break;
+ default:
+ mutex_unlock(&st->lock);
+ return -EINVAL;
+ }
+
+ /* delay (2 * AD2S1200_TSCLK + 20) ns for sample pulse */
+ udelay(1);
+ mutex_unlock(&st->lock);
+
+ return IIO_VAL_INT;
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static const struct iio_chan_spec ad2s1200_channels[] = {
+ {
+ .type = IIO_ANGL,
+ .indexed = 1,
+ .channel = 0,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
+ }, {
+ .type = IIO_ANGL_VEL,
+ .indexed = 1,
+ .channel = 0,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
+ }
+};
+
+static const struct iio_info ad2s1200_info = {
+ .read_raw = ad2s1200_read_raw,
+};
+
+static int ad2s1200_probe(struct spi_device *spi)
+{
+ struct ad2s1200_state *st;
+ struct iio_dev *indio_dev;
+ int ret;
+
+ indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
+ if (!indio_dev)
+ return -ENOMEM;
+
+ spi_set_drvdata(spi, indio_dev);
+ st = iio_priv(indio_dev);
+ mutex_init(&st->lock);
+ st->sdev = spi;
+
+ st->sample = devm_gpiod_get(&spi->dev, "adi,sample", GPIOD_OUT_LOW);
+ if (IS_ERR(st->sample)) {
+ dev_err(&spi->dev, "Failed to claim SAMPLE gpio: err=%ld\n",
+ PTR_ERR(st->sample));
+ return PTR_ERR(st->sample);
+ }
+
+ st->rdvel = devm_gpiod_get(&spi->dev, "adi,rdvel", GPIOD_OUT_LOW);
+ if (IS_ERR(st->rdvel)) {
+ dev_err(&spi->dev, "Failed to claim RDVEL gpio: err=%ld\n",
+ PTR_ERR(st->rdvel));
+ return PTR_ERR(st->rdvel);
+ }
+
+ indio_dev->dev.parent = &spi->dev;
+ indio_dev->info = &ad2s1200_info;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->channels = ad2s1200_channels;
+ indio_dev->num_channels = ARRAY_SIZE(ad2s1200_channels);
+ indio_dev->name = spi_get_device_id(spi)->name;
+
+ spi->max_speed_hz = AD2S1200_HZ;
+ spi->mode = SPI_MODE_3;
+ ret = spi_setup(spi);
+
+ if (ret < 0) {
+ dev_err(&spi->dev, "spi_setup failed!\n");
+ return ret;
+ }
+
+ return devm_iio_device_register(&spi->dev, indio_dev);
+}
+
+static const struct of_device_id ad2s1200_of_match[] = {
+ { .compatible = "adi,ad2s1200", },
+ { .compatible = "adi,ad2s1205", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, ad2s1200_of_match);
+
+static const struct spi_device_id ad2s1200_id[] = {
+ { "ad2s1200" },
+ { "ad2s1205" },
+ {}
+};
+MODULE_DEVICE_TABLE(spi, ad2s1200_id);
+
+static struct spi_driver ad2s1200_driver = {
+ .driver = {
+ .name = DRV_NAME,
+ .of_match_table = of_match_ptr(ad2s1200_of_match),
+ },
+ .probe = ad2s1200_probe,
+ .id_table = ad2s1200_id,
+};
+module_spi_driver(ad2s1200_driver);
+
+MODULE_AUTHOR("David Veenstra <davidjulianveenstra@gmail.com>");
+MODULE_AUTHOR("Graff Yang <graff.yang@gmail.com>");
+MODULE_DESCRIPTION("Analog Devices AD2S1200/1205 Resolver to Digital SPI driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/staging/iio/resolver/Kconfig b/drivers/staging/iio/resolver/Kconfig
index 1c7e2860d6b7..6a469ee6101f 100644
--- a/drivers/staging/iio/resolver/Kconfig
+++ b/drivers/staging/iio/resolver/Kconfig
@@ -13,18 +13,6 @@ config AD2S90
To compile this driver as a module, choose M here: the
module will be called ad2s90.
-config AD2S1200
- tristate "Analog Devices ad2s1200/ad2s1205 driver"
- depends on SPI
- depends on GPIOLIB || COMPILE_TEST
- help
- Say yes here to build support for Analog Devices spi resolver
- to digital converters, ad2s1200 and ad2s1205, provides direct access
- via sysfs.
-
- To compile this driver as a module, choose M here: the
- module will be called ad2s1200.
-
config AD2S1210
tristate "Analog Devices ad2s1210 driver"
depends on SPI
diff --git a/drivers/staging/iio/resolver/Makefile b/drivers/staging/iio/resolver/Makefile
index 14375e444ebf..8d901dc7500b 100644
--- a/drivers/staging/iio/resolver/Makefile
+++ b/drivers/staging/iio/resolver/Makefile
@@ -3,5 +3,4 @@
#
obj-$(CONFIG_AD2S90) += ad2s90.o
-obj-$(CONFIG_AD2S1200) += ad2s1200.o
obj-$(CONFIG_AD2S1210) += ad2s1210.o
diff --git a/drivers/staging/iio/resolver/ad2s1200.c b/drivers/staging/iio/resolver/ad2s1200.c
deleted file mode 100644
index 28e618af9939..000000000000
--- a/drivers/staging/iio/resolver/ad2s1200.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * ad2s1200.c simple support for the ADI Resolver to Digital Converters:
- * AD2S1200/1205
- *
- * Copyright (c) 2018-2018 David Veenstra <davidjulianveenstra@gmail.com>
- * Copyright (c) 2010-2010 Analog Devices Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/bitops.h>
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/gpio.h>
-#include <linux/gpio/consumer.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/spi/spi.h>
-#include <linux/sysfs.h>
-#include <linux/types.h>
-
-#include <linux/iio/iio.h>
-#include <linux/iio/sysfs.h>
-
-#define DRV_NAME "ad2s1200"
-
-/* input clock on serial interface */
-#define AD2S1200_HZ 8192000
-/* clock period in nano second */
-#define AD2S1200_TSCLK (1000000000 / AD2S1200_HZ)
-
-/**
- * struct ad2s1200_state - driver instance specific data.
- * @lock: protects both the GPIO pins and the rx buffer.
- * @sdev: spi device.
- * @sample: GPIO pin SAMPLE.
- * @rdvel: GPIO pin RDVEL.
- * @rx: buffer for spi transfers.
- */
-struct ad2s1200_state {
- struct mutex lock;
- struct spi_device *sdev;
- struct gpio_desc *sample;
- struct gpio_desc *rdvel;
- __be16 rx ____cacheline_aligned;
-};
-
-static int ad2s1200_read_raw(struct iio_dev *indio_dev,
- struct iio_chan_spec const *chan,
- int *val,
- int *val2,
- long m)
-{
- struct ad2s1200_state *st = iio_priv(indio_dev);
- int ret;
-
- switch (m) {
- case IIO_CHAN_INFO_SCALE:
- switch (chan->type) {
- case IIO_ANGL:
- /* 2 * Pi / (2^12 - 1) ~= 0.001534355 */
- *val = 0;
- *val2 = 1534355;
- return IIO_VAL_INT_PLUS_NANO;
- case IIO_ANGL_VEL:
- /* 2 * Pi ~= 6.283185 */
- *val = 6;
- *val2 = 283185;
- return IIO_VAL_INT_PLUS_MICRO;
- default:
- return -EINVAL;
- }
- break;
- case IIO_CHAN_INFO_RAW:
- mutex_lock(&st->lock);
- gpiod_set_value(st->sample, 0);
-
- /* delay (6 * AD2S1200_TSCLK + 20) nano seconds */
- udelay(1);
- gpiod_set_value(st->sample, 1);
- gpiod_set_value(st->rdvel, !!(chan->type == IIO_ANGL));
-
- ret = spi_read(st->sdev, &st->rx, 2);
- if (ret < 0) {
- mutex_unlock(&st->lock);
- return ret;
- }
-
- switch (chan->type) {
- case IIO_ANGL:
- *val = be16_to_cpup(&st->rx) >> 4;
- break;
- case IIO_ANGL_VEL:
- *val = sign_extend32(be16_to_cpup(&st->rx) >> 4, 11);
- break;
- default:
- mutex_unlock(&st->lock);
- return -EINVAL;
- }
-
- /* delay (2 * AD2S1200_TSCLK + 20) ns for sample pulse */
- udelay(1);
- mutex_unlock(&st->lock);
-
- return IIO_VAL_INT;
- default:
- break;
- }
-
- return -EINVAL;
-}
-
-static const struct iio_chan_spec ad2s1200_channels[] = {
- {
- .type = IIO_ANGL,
- .indexed = 1,
- .channel = 0,
- .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
- .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
- }, {
- .type = IIO_ANGL_VEL,
- .indexed = 1,
- .channel = 0,
- .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
- .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
- }
-};
-
-static const struct iio_info ad2s1200_info = {
- .read_raw = ad2s1200_read_raw,
-};
-
-static int ad2s1200_probe(struct spi_device *spi)
-{
- struct ad2s1200_state *st;
- struct iio_dev *indio_dev;
- int ret;
-
- indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
- if (!indio_dev)
- return -ENOMEM;
-
- spi_set_drvdata(spi, indio_dev);
- st = iio_priv(indio_dev);
- mutex_init(&st->lock);
- st->sdev = spi;
-
- st->sample = devm_gpiod_get(&spi->dev, "adi,sample", GPIOD_OUT_LOW);
- if (IS_ERR(st->sample)) {
- dev_err(&spi->dev, "Failed to claim SAMPLE gpio: err=%ld\n",
- PTR_ERR(st->sample));
- return PTR_ERR(st->sample);
- }
-
- st->rdvel = devm_gpiod_get(&spi->dev, "adi,rdvel", GPIOD_OUT_LOW);
- if (IS_ERR(st->rdvel)) {
- dev_err(&spi->dev, "Failed to claim RDVEL gpio: err=%ld\n",
- PTR_ERR(st->rdvel));
- return PTR_ERR(st->rdvel);
- }
-
- indio_dev->dev.parent = &spi->dev;
- indio_dev->info = &ad2s1200_info;
- indio_dev->modes = INDIO_DIRECT_MODE;
- indio_dev->channels = ad2s1200_channels;
- indio_dev->num_channels = ARRAY_SIZE(ad2s1200_channels);
- indio_dev->name = spi_get_device_id(spi)->name;
-
- spi->max_speed_hz = AD2S1200_HZ;
- spi->mode = SPI_MODE_3;
- ret = spi_setup(spi);
-
- if (ret < 0) {
- dev_err(&spi->dev, "spi_setup failed!\n");
- return ret;
- }
-
- return devm_iio_device_register(&spi->dev, indio_dev);
-}
-
-static const struct of_device_id ad2s1200_of_match[] = {
- { .compatible = "adi,ad2s1200", },
- { .compatible = "adi,ad2s1205", },
- { }
-};
-MODULE_DEVICE_TABLE(of, ad2s1200_of_match);
-
-static const struct spi_device_id ad2s1200_id[] = {
- { "ad2s1200" },
- { "ad2s1205" },
- {}
-};
-MODULE_DEVICE_TABLE(spi, ad2s1200_id);
-
-static struct spi_driver ad2s1200_driver = {
- .driver = {
- .name = DRV_NAME,
- .of_match_table = of_match_ptr(ad2s1200_of_match),
- },
- .probe = ad2s1200_probe,
- .id_table = ad2s1200_id,
-};
-module_spi_driver(ad2s1200_driver);
-
-MODULE_AUTHOR("David Veenstra <davidjulianveenstra@gmail.com>");
-MODULE_AUTHOR("Graff Yang <graff.yang@gmail.com>");
-MODULE_DESCRIPTION("Analog Devices AD2S1200/1205 Resolver to Digital SPI driver");
-MODULE_LICENSE("GPL v2");
--
2.17.0
^ permalink raw reply related
* [PATCH v4 11/12] staging: iio: ad2s1200: Add copyright
From: David Veenstra @ 2018-05-18 18:23 UTC (permalink / raw)
To: jic23, lars, pmeerw, robh+dt
Cc: linux-iio, devel, devicetree, Michael.Hennerich, knaack.h
In-Reply-To: <cover.1526667118.git.davidjulianveenstra@gmail.com>
Add David Veenstra as a copyright holders and as an author,
for all of the staging clean ups of the ad2s1200 driver.
Signed-off-by: David Veenstra <davidjulianveenstra@gmail.com>
---
Changes in v4:
- Introduced in this version.
drivers/staging/iio/resolver/ad2s1200.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/staging/iio/resolver/ad2s1200.c b/drivers/staging/iio/resolver/ad2s1200.c
index 10d6d79dce79..28e618af9939 100644
--- a/drivers/staging/iio/resolver/ad2s1200.c
+++ b/drivers/staging/iio/resolver/ad2s1200.c
@@ -2,6 +2,7 @@
* ad2s1200.c simple support for the ADI Resolver to Digital Converters:
* AD2S1200/1205
*
+ * Copyright (c) 2018-2018 David Veenstra <davidjulianveenstra@gmail.com>
* Copyright (c) 2010-2010 Analog Devices Inc.
*
* This program is free software; you can redistribute it and/or modify
@@ -203,6 +204,7 @@ static struct spi_driver ad2s1200_driver = {
};
module_spi_driver(ad2s1200_driver);
+MODULE_AUTHOR("David Veenstra <davidjulianveenstra@gmail.com>");
MODULE_AUTHOR("Graff Yang <graff.yang@gmail.com>");
MODULE_DESCRIPTION("Analog Devices AD2S1200/1205 Resolver to Digital SPI driver");
MODULE_LICENSE("GPL v2");
--
2.17.0
^ permalink raw reply related
* [PATCH v4 10/12] staging: iio: ad2s1200: Add scaling factor for angle channel
From: David Veenstra @ 2018-05-18 18:23 UTC (permalink / raw)
To: jic23, lars, pmeerw, robh+dt
Cc: linux-iio, devel, devicetree, Michael.Hennerich, knaack.h
In-Reply-To: <cover.1526667118.git.davidjulianveenstra@gmail.com>
A scaling factor of approximately 2 * Pi / (2^12 -1) is added,
to scale the 12-bits angular position to radians.
A return type of IIO_VAL_INT_PLUS_NANO is used, so that the scale of
both the angle channel and angular velocity channel has 7 significant
digits.
Signed-off-by: David Veenstra <davidjulianveenstra@gmail.com>
---
drivers/staging/iio/resolver/ad2s1200.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/staging/iio/resolver/ad2s1200.c b/drivers/staging/iio/resolver/ad2s1200.c
index 7b8af558e921..10d6d79dce79 100644
--- a/drivers/staging/iio/resolver/ad2s1200.c
+++ b/drivers/staging/iio/resolver/ad2s1200.c
@@ -58,6 +58,11 @@ static int ad2s1200_read_raw(struct iio_dev *indio_dev,
switch (m) {
case IIO_CHAN_INFO_SCALE:
switch (chan->type) {
+ case IIO_ANGL:
+ /* 2 * Pi / (2^12 - 1) ~= 0.001534355 */
+ *val = 0;
+ *val2 = 1534355;
+ return IIO_VAL_INT_PLUS_NANO;
case IIO_ANGL_VEL:
/* 2 * Pi ~= 6.283185 */
*val = 6;
@@ -112,6 +117,7 @@ static const struct iio_chan_spec ad2s1200_channels[] = {
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
}, {
.type = IIO_ANGL_VEL,
.indexed = 1,
--
2.17.0
^ permalink raw reply related
* [PATCH v4 09/12] staging: iio: ad2s1200: Add scaling factor for angular velocity channel
From: David Veenstra @ 2018-05-18 18:23 UTC (permalink / raw)
To: jic23, lars, pmeerw, robh+dt
Cc: linux-iio, devel, devicetree, Michael.Hennerich, knaack.h
In-Reply-To: <cover.1526667118.git.davidjulianveenstra@gmail.com>
The sysfs iio ABI states radians per second is expected as the unit for
angular velocity, but the 12-bit angular velocity register has
revolution per seconds as its unit. So a scaling factor of approximately
2 * Pi is added to the angular velocity channel.
Signed-off-by: David Veenstra <davidjulianveenstra@gmail.com>
---
Changes in v4:
- Changed rps to revolutions per second in commit message
to prevent confusion.
drivers/staging/iio/resolver/ad2s1200.c | 71 ++++++++++++++++---------
1 file changed, 45 insertions(+), 26 deletions(-)
diff --git a/drivers/staging/iio/resolver/ad2s1200.c b/drivers/staging/iio/resolver/ad2s1200.c
index 67d9747f88a6..7b8af558e921 100644
--- a/drivers/staging/iio/resolver/ad2s1200.c
+++ b/drivers/staging/iio/resolver/ad2s1200.c
@@ -55,37 +55,55 @@ static int ad2s1200_read_raw(struct iio_dev *indio_dev,
struct ad2s1200_state *st = iio_priv(indio_dev);
int ret;
- mutex_lock(&st->lock);
- gpiod_set_value(st->sample, 0);
-
- /* delay (6 * AD2S1200_TSCLK + 20) nano seconds */
- udelay(1);
- gpiod_set_value(st->sample, 1);
- gpiod_set_value(st->rdvel, !!(chan->type == IIO_ANGL));
-
- ret = spi_read(st->sdev, &st->rx, 2);
- if (ret < 0) {
+ switch (m) {
+ case IIO_CHAN_INFO_SCALE:
+ switch (chan->type) {
+ case IIO_ANGL_VEL:
+ /* 2 * Pi ~= 6.283185 */
+ *val = 6;
+ *val2 = 283185;
+ return IIO_VAL_INT_PLUS_MICRO;
+ default:
+ return -EINVAL;
+ }
+ break;
+ case IIO_CHAN_INFO_RAW:
+ mutex_lock(&st->lock);
+ gpiod_set_value(st->sample, 0);
+
+ /* delay (6 * AD2S1200_TSCLK + 20) nano seconds */
+ udelay(1);
+ gpiod_set_value(st->sample, 1);
+ gpiod_set_value(st->rdvel, !!(chan->type == IIO_ANGL));
+
+ ret = spi_read(st->sdev, &st->rx, 2);
+ if (ret < 0) {
+ mutex_unlock(&st->lock);
+ return ret;
+ }
+
+ switch (chan->type) {
+ case IIO_ANGL:
+ *val = be16_to_cpup(&st->rx) >> 4;
+ break;
+ case IIO_ANGL_VEL:
+ *val = sign_extend32(be16_to_cpup(&st->rx) >> 4, 11);
+ break;
+ default:
+ mutex_unlock(&st->lock);
+ return -EINVAL;
+ }
+
+ /* delay (2 * AD2S1200_TSCLK + 20) ns for sample pulse */
+ udelay(1);
mutex_unlock(&st->lock);
- return ret;
- }
- switch (chan->type) {
- case IIO_ANGL:
- *val = be16_to_cpup(&st->rx) >> 4;
- break;
- case IIO_ANGL_VEL:
- *val = sign_extend32(be16_to_cpup(&st->rx) >> 4, 11);
- break;
+ return IIO_VAL_INT;
default:
- mutex_unlock(&st->lock);
- return -EINVAL;
+ break;
}
- /* delay (2 * AD2S1200_TSCLK + 20) ns for sample pulse */
- udelay(1);
- mutex_unlock(&st->lock);
-
- return IIO_VAL_INT;
+ return -EINVAL;
}
static const struct iio_chan_spec ad2s1200_channels[] = {
@@ -99,6 +117,7 @@ static const struct iio_chan_spec ad2s1200_channels[] = {
.indexed = 1,
.channel = 0,
.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
}
};
--
2.17.0
^ permalink raw reply related
* [PATCH v4 08/12] dt-bindings: iio: resolver: Document AD2S1200 bindings
From: David Veenstra @ 2018-05-18 18:22 UTC (permalink / raw)
To: jic23, lars, pmeerw, robh+dt
Cc: linux-iio, devel, devicetree, Michael.Hennerich, knaack.h
In-Reply-To: <cover.1526667118.git.davidjulianveenstra@gmail.com>
Add documentation for the device tree bindings of the AD2S1200 resolver.
Signed-off-by: David Veenstra <davidjulianveenstra@gmail.com>
---
Changes in v4:
- Added vendor prefix to gpio function name.
- Added unit address.
- Changed commit subject to be more inline with other dt-bindings
commit .
.../bindings/iio/resolver/ad2s1200.txt | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/resolver/ad2s1200.txt
diff --git a/Documentation/devicetree/bindings/iio/resolver/ad2s1200.txt b/Documentation/devicetree/bindings/iio/resolver/ad2s1200.txt
new file mode 100644
index 000000000000..bbf54260c911
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/resolver/ad2s1200.txt
@@ -0,0 +1,16 @@
+Analog Devices AD2S1200 and AD2S1205 Resolver-to-Digital Converter
+
+Required properties:
+ - compatible : should be "adi,ad2s1200" or "adi,ad2s1205"
+ - reg : the SPI chip select number of the device
+ - adi,sample-gpios : The GPIO pin connected to the SAMPLE line of the AD2S1200
+ - adi,rdvel-gpios : The GPIO pin connected to the RDVEL line of the AD2S1200
+
+Example:
+
+ resolver@0 {
+ compatible = "adi,ad2s1200";
+ reg = <4>;
+ adi,sample-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+ adi,rdvel-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
+ };
--
2.17.0
^ permalink raw reply related
* [PATCH v4 07/12] staging: iio: ad2s1200: Add dt table
From: David Veenstra @ 2018-05-18 18:22 UTC (permalink / raw)
To: jic23, lars, pmeerw, robh+dt
Cc: linux-iio, devel, devicetree, Michael.Hennerich, knaack.h
In-Reply-To: <cover.1526667118.git.davidjulianveenstra@gmail.com>
Add device tree table for matching with the vendor ID.
Signed-off-by: David Veenstra <davidjulianveenstra@gmail.com>
---
Changes in v4:
- Introduced in this version.
drivers/staging/iio/resolver/ad2s1200.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/staging/iio/resolver/ad2s1200.c b/drivers/staging/iio/resolver/ad2s1200.c
index 9a8aa2448897..67d9747f88a6 100644
--- a/drivers/staging/iio/resolver/ad2s1200.c
+++ b/drivers/staging/iio/resolver/ad2s1200.c
@@ -154,6 +154,13 @@ static int ad2s1200_probe(struct spi_device *spi)
return devm_iio_device_register(&spi->dev, indio_dev);
}
+static const struct of_device_id ad2s1200_of_match[] = {
+ { .compatible = "adi,ad2s1200", },
+ { .compatible = "adi,ad2s1205", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, ad2s1200_of_match);
+
static const struct spi_device_id ad2s1200_id[] = {
{ "ad2s1200" },
{ "ad2s1205" },
@@ -164,6 +171,7 @@ MODULE_DEVICE_TABLE(spi, ad2s1200_id);
static struct spi_driver ad2s1200_driver = {
.driver = {
.name = DRV_NAME,
+ .of_match_table = of_match_ptr(ad2s1200_of_match),
},
.probe = ad2s1200_probe,
.id_table = ad2s1200_id,
--
2.17.0
^ permalink raw reply related
* [PATCH v4 06/12] staging: iio: ad2s1200: Replace platform data with dt bindings
From: David Veenstra @ 2018-05-18 18:22 UTC (permalink / raw)
To: jic23, lars, pmeerw, robh+dt
Cc: linux-iio, devel, devicetree, Michael.Hennerich, knaack.h
In-Reply-To: <cover.1526667118.git.davidjulianveenstra@gmail.com>
Remove usage of platform data, and replace it with device tree
facilities.
Signed-off-by: David Veenstra <davidjulianveenstra@gmail.com>
---
Changes in v4:
- Added vendor prefix to gpio function names.
drivers/staging/iio/resolver/ad2s1200.c | 32 ++++++++++++-------------
1 file changed, 15 insertions(+), 17 deletions(-)
diff --git a/drivers/staging/iio/resolver/ad2s1200.c b/drivers/staging/iio/resolver/ad2s1200.c
index b2c46a8c6b77..9a8aa2448897 100644
--- a/drivers/staging/iio/resolver/ad2s1200.c
+++ b/drivers/staging/iio/resolver/ad2s1200.c
@@ -25,9 +25,6 @@
#define DRV_NAME "ad2s1200"
-/* input pin sample and rdvel is controlled by driver */
-#define AD2S1200_PN 2
-
/* input clock on serial interface */
#define AD2S1200_HZ 8192000
/* clock period in nano second */
@@ -111,20 +108,9 @@ static const struct iio_info ad2s1200_info = {
static int ad2s1200_probe(struct spi_device *spi)
{
- unsigned short *pins = spi->dev.platform_data;
struct ad2s1200_state *st;
struct iio_dev *indio_dev;
- int pn, ret;
-
- for (pn = 0; pn < AD2S1200_PN; pn++) {
- ret = devm_gpio_request_one(&spi->dev, pins[pn], GPIOF_DIR_OUT,
- DRV_NAME);
- if (ret) {
- dev_err(&spi->dev, "request gpio pin %d failed\n",
- pins[pn]);
- return ret;
- }
- }
+ int ret;
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
if (!indio_dev)
@@ -134,8 +120,20 @@ static int ad2s1200_probe(struct spi_device *spi)
st = iio_priv(indio_dev);
mutex_init(&st->lock);
st->sdev = spi;
- st->sample = gpio_to_desc(pins[0]);
- st->rdvel = gpio_to_desc(pins[1]);
+
+ st->sample = devm_gpiod_get(&spi->dev, "adi,sample", GPIOD_OUT_LOW);
+ if (IS_ERR(st->sample)) {
+ dev_err(&spi->dev, "Failed to claim SAMPLE gpio: err=%ld\n",
+ PTR_ERR(st->sample));
+ return PTR_ERR(st->sample);
+ }
+
+ st->rdvel = devm_gpiod_get(&spi->dev, "adi,rdvel", GPIOD_OUT_LOW);
+ if (IS_ERR(st->rdvel)) {
+ dev_err(&spi->dev, "Failed to claim RDVEL gpio: err=%ld\n",
+ PTR_ERR(st->rdvel));
+ return PTR_ERR(st->rdvel);
+ }
indio_dev->dev.parent = &spi->dev;
indio_dev->info = &ad2s1200_info;
--
2.17.0
^ permalink raw reply related
* [PATCH v4 05/12] staging: iio: ad2s1200: Replace legacy gpio API with modern API
From: David Veenstra @ 2018-05-18 18:21 UTC (permalink / raw)
To: jic23, lars, pmeerw, robh+dt
Cc: linux-iio, devel, devicetree, Michael.Hennerich, knaack.h
In-Reply-To: <cover.1526667118.git.davidjulianveenstra@gmail.com>
The legacy, integer based gpio API is replaced with the modern
descriptor based API.
Signed-off-by: David Veenstra <davidjulianveenstra@gmail.com>
---
drivers/staging/iio/resolver/ad2s1200.c | 15 ++++++++-------
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/staging/iio/resolver/ad2s1200.c b/drivers/staging/iio/resolver/ad2s1200.c
index 430cc62591fe..b2c46a8c6b77 100644
--- a/drivers/staging/iio/resolver/ad2s1200.c
+++ b/drivers/staging/iio/resolver/ad2s1200.c
@@ -13,6 +13,7 @@
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
#include <linux/module.h>
#include <linux/mutex.h>
#include <linux/spi/spi.h>
@@ -43,8 +44,8 @@
struct ad2s1200_state {
struct mutex lock;
struct spi_device *sdev;
- int sample;
- int rdvel;
+ struct gpio_desc *sample;
+ struct gpio_desc *rdvel;
__be16 rx ____cacheline_aligned;
};
@@ -58,12 +59,12 @@ static int ad2s1200_read_raw(struct iio_dev *indio_dev,
int ret;
mutex_lock(&st->lock);
- gpio_set_value(st->sample, 0);
+ gpiod_set_value(st->sample, 0);
/* delay (6 * AD2S1200_TSCLK + 20) nano seconds */
udelay(1);
- gpio_set_value(st->sample, 1);
- gpio_set_value(st->rdvel, !!(chan->type == IIO_ANGL));
+ gpiod_set_value(st->sample, 1);
+ gpiod_set_value(st->rdvel, !!(chan->type == IIO_ANGL));
ret = spi_read(st->sdev, &st->rx, 2);
if (ret < 0) {
@@ -133,8 +134,8 @@ static int ad2s1200_probe(struct spi_device *spi)
st = iio_priv(indio_dev);
mutex_init(&st->lock);
st->sdev = spi;
- st->sample = pins[0];
- st->rdvel = pins[1];
+ st->sample = gpio_to_desc(pins[0]);
+ st->rdvel = gpio_to_desc(pins[1]);
indio_dev->dev.parent = &spi->dev;
indio_dev->info = &ad2s1200_info;
--
2.17.0
^ permalink raw reply related
* [PATCH v4 04/12] staging: iio: ad2s1200: Setup spi before iio device register
From: David Veenstra @ 2018-05-18 18:21 UTC (permalink / raw)
To: jic23, lars, pmeerw, robh+dt
Cc: linux-iio, devel, devicetree, Michael.Hennerich, knaack.h
In-Reply-To: <cover.1526667118.git.davidjulianveenstra@gmail.com>
The spi should be set up before the device is registered as an iio
device.
This patch moves the setup to before the device registration.
Signed-off-by: David Veenstra <davidjulianveenstra@gmail.com>
---
Changes in v4:
- Introduced in this version.
drivers/staging/iio/resolver/ad2s1200.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/iio/resolver/ad2s1200.c b/drivers/staging/iio/resolver/ad2s1200.c
index 068aa86e9c11..430cc62591fe 100644
--- a/drivers/staging/iio/resolver/ad2s1200.c
+++ b/drivers/staging/iio/resolver/ad2s1200.c
@@ -143,15 +143,16 @@ static int ad2s1200_probe(struct spi_device *spi)
indio_dev->num_channels = ARRAY_SIZE(ad2s1200_channels);
indio_dev->name = spi_get_device_id(spi)->name;
- ret = devm_iio_device_register(&spi->dev, indio_dev);
- if (ret)
- return ret;
-
spi->max_speed_hz = AD2S1200_HZ;
spi->mode = SPI_MODE_3;
- spi_setup(spi);
+ ret = spi_setup(spi);
+
+ if (ret < 0) {
+ dev_err(&spi->dev, "spi_setup failed!\n");
+ return ret;
+ }
- return 0;
+ return devm_iio_device_register(&spi->dev, indio_dev);
}
static const struct spi_device_id ad2s1200_id[] = {
--
2.17.0
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox