* [PATCH v2 16/16] arm64: dts: marvell: add CP110 ICU SEI subnode
From: Miquel Raynal @ 2018-05-22 9:40 UTC (permalink / raw)
To: Thomas Gleixner, Jason Cooper, Marc Zyngier, Catalin Marinas,
Will Deacon, Andrew Lunn, Gregory Clement, Sebastian Hesselbarth
Cc: Rob Herring, Mark Rutland, devicetree, linux-arm-kernel,
Thomas Petazzoni, Antoine Tenart, Maxime Chevallier, Nadav Haklai,
Haim Boot, Hanna Hawa, linux-kernel, Miquel Raynal
In-Reply-To: <20180522094042.24770-1-miquel.raynal@bootlin.com>
The ICU handles several interrupt groups, each of them being a subpart
of the ICU node.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index 5637ff2601c9..0038a922e7db 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -154,6 +154,13 @@
interrupt-controller;
msi-parent = <&gicp>;
};
+
+ CP110_LABEL(icu_sei): icu-sei {
+ compatible = "marvell,cp110-icu-sei";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ msi-parent = <&sei>;
+ };
};
CP110_LABEL(rtc): rtc@284000 {
--
2.14.1
^ permalink raw reply related
* [RESEND PATCH v2 0/2] gpu: drm/panel: Add DLC DLC0700YZG-1 support
From: Marco Felsch @ 2018-05-22 9:48 UTC (permalink / raw)
To: thierry.reding, robh+dt, mark.rutland; +Cc: devicetree, kernel, dri-devel
This serie adds support for the DLC Display Co. DLC0700YZG-1 7.0" WSVGA
TFT LCD panel. The customer isn't listed as vendor so we have to add the
vendor prefix too.
Philipp Zabel (2):
dt-bindings: Add vendor prefix for DLC Display Co., Ltd.
gpu: drm/panel: Add DLC DLC0700YZG-1 panel
.../display/panel/dlc,dlc0700yzg-1.txt | 7 ++++
.../devicetree/bindings/vendor-prefixes.txt | 1 +
drivers/gpu/drm/panel/panel-simple.c | 32 +++++++++++++++++++
3 files changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.txt
--
2.17.0
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* [RESEND PATCH v2 1/2] dt-bindings: Add vendor prefix for DLC Display Co., Ltd.
From: Marco Felsch @ 2018-05-22 9:48 UTC (permalink / raw)
To: thierry.reding, robh+dt, mark.rutland; +Cc: devicetree, kernel, dri-devel
In-Reply-To: <20180522094812.31608-1-m.felsch@pengutronix.de>
From: Philipp Zabel <p.zabel@pengutronix.de>
DLC provides a wide range of display solutions.
Website: http://www.dlcdisplay.com/
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index b5f978a4cac6..52de5eed11bf 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -89,6 +89,7 @@ dh DH electronics GmbH
digi Digi International Inc.
digilent Diglent, Inc.
dioo Dioo Microcircuit Co., Ltd
+dlc DLC Display Co., Ltd.
dlg Dialog Semiconductor
dlink D-Link Corporation
dmo Data Modul AG
--
2.17.0
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* [RESEND PATCH v2 2/2] gpu: drm/panel: Add DLC DLC0700YZG-1 panel
From: Marco Felsch @ 2018-05-22 9:48 UTC (permalink / raw)
To: thierry.reding, robh+dt, mark.rutland; +Cc: devicetree, kernel, dri-devel
In-Reply-To: <20180522094812.31608-1-m.felsch@pengutronix.de>
From: Philipp Zabel <p.zabel@pengutronix.de>
This patch adds support for DLC DLC0700YZG-1 1024x600 LVDS panels
to the simple-panel driver.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
[m.felsch@pengutronix.de: fix typo in compatible dt-binding]
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
.../display/panel/dlc,dlc0700yzg-1.txt | 7 ++++
drivers/gpu/drm/panel/panel-simple.c | 32 +++++++++++++++++++
2 files changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.txt
diff --git a/Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.txt b/Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.txt
new file mode 100644
index 000000000000..3cfafe26eb35
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/dlc,dlc0700yzg-1.txt
@@ -0,0 +1,7 @@
+DLC Display Co. DLC0700YZG-1 7.0" WSVGA TFT LCD panel
+
+Required properties:
+- compatible: should be "dlc,dlc0700yzg-1"
+
+This binding is compatible with the simple-panel binding, which is specified
+in simple-panel.txt in this directory.
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index 964c261cfb78..7274ae7b9c57 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -856,6 +856,35 @@ static const struct panel_desc chunghwa_claa101wb01 = {
},
};
+static const struct display_timing dlc_dlc0700yzg_1_timing = {
+ .pixelclock = { 45000000, 51200000, 57000000 },
+ .hactive = { 1024, 1024, 1024 },
+ .hfront_porch = { 100, 106, 113 },
+ .hback_porch = { 100, 106, 113 },
+ .hsync_len = { 100, 108, 114 },
+ .vactive = { 600, 600, 600 },
+ .vfront_porch = { 8, 11, 15 },
+ .vback_porch = { 8, 11, 15 },
+ .vsync_len = { 9, 13, 15 },
+ .flags = DISPLAY_FLAGS_DE_HIGH,
+};
+
+static const struct panel_desc dlc_dlc0700yzg_1 = {
+ .timings = &dlc_dlc0700yzg_1_timing,
+ .num_timings = 1,
+ .bpc = 6,
+ .size = {
+ .width = 154,
+ .height = 86,
+ },
+ .delay = {
+ .prepare = 30,
+ .enable = 200,
+ .disable = 200,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
+};
+
static const struct drm_display_mode edt_et057090dhu_mode = {
.clock = 25175,
.hdisplay = 640,
@@ -2147,6 +2176,9 @@ static const struct of_device_id platform_of_match[] = {
}, {
.compatible = "chunghwa,claa101wb01",
.data = &chunghwa_claa101wb01
+ }, {
+ .compatible = "dlc,dlc0700yzg-1",
+ .data = &dlc_dlc0700yzg_1,
}, {
.compatible = "edt,et057090dhu",
.data = &edt_et057090dhu,
--
2.17.0
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* Re: [PATCH] arm64: dts: renesas: r8a77980: add SMP support
From: Geert Uytterhoeven @ 2018-05-22 9:49 UTC (permalink / raw)
To: Simon Horman
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Sergei Shtylyov, Catalin Marinas, Will Deacon,
Linux-Renesas, Rob Herring, Linux ARM
In-Reply-To: <20180522085430.eqhan4njajnp5hkk@verge.net.au>
On Tue, May 22, 2018 at 10:54 AM, Simon Horman <horms@verge.net.au> wrote:
> On Sat, May 19, 2018 at 08:38:13PM +0300, Sergei Shtylyov wrote:
>> On 05/17/2018 11:23 PM, Geert Uytterhoeven wrote:
>>
>> >> Add the device nodes for 3 more Cortex-A53 CPU cores; adjust the interrupt
>> >> delivery masks for the ARM GIC and Architectured Timer.
>> >>
>> >> Based on the original (and large) patch by Vladimir Barinov.
>> >>
>> >> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>> >
>> > Thanks for your patch!
>> >
>> >> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> >> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> >> @@ -30,6 +30,36 @@
>> >> enable-method = "psci";
>> >> };
>> >>
>> >> + a53_1: cpu@1 {
>> >> + device_type = "cpu";
>> >> + compatible = "arm,cortex-a53","arm,armv8";
>> >
>> > Please stop copying spaceless lists ;-)
>>
>> Oops! Simon, do I need to re-post?
>
> No, but Geert, are you otherwise ok with this patch?
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH v6 0/6] arm: Base support for Renesas RZN1D-DB Board
From: Michel Pollet @ 2018-05-22 10:01 UTC (permalink / raw)
To: linux-renesas-soc, Simon Horman
Cc: phil.edworthy, Michel Pollet, Michel Pollet, Magnus Damm,
Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, devicetree, linux-kernel, linux-clk
This series adds the plain basic support for booting a bare
kernel on the RZ/N1D-DB Board. It's been trimmed to the strict
minimum as a 'base', further patches that will add the
rest of the support.
Special note on the clock driver: Current usage of the clocks on Linux
involves Linux 'claiming' all of them, disabling the one it doesn't
need and so on.
On *this* architecture it can't be done, there is at least one other
OS running on the CM3 core that claims it's own clock; Linux can claim
some others but definitely not start disabling stuff it isn't supposed to.
Thanks for the comments on the previous versions!
v6:
+ Fix for suggestion by Geert Uytterhoeven
+ Removed "renesas,rzn1" from the board bindings
+ Removed patches already merged.
+ Removed reboot driver
+ Added a whole clock infrastructure.
+ Rebased on next-20180517
v5:
+ Given the problems I have with getting in some structure around the
sysctrl block, I've removed the MFD, I've now attached the reboot
driver on it's own pair of registers.
+ Rebased on next-20180417
v4:
+ Fixes for suggestions by Simon Horman
+ Fixes for suggestions by Jacopo Mondi
+ Fixes for suggestions by Geert Uytterhoeven
+ Renamed the r9a06g0xx.dtsi file, given up on trying to get a family
common file in, so dropped potential RZ/N1S support and now only
focus on RZ/N1D for this patchset.
+ Added 'always-on' to the architected timer node, because it is.
+ Added ARCH_R9A06G032, to match others patterns like RCAR
+ Sorted the .dts files, added empty lines as required.
+ Fixed patch prefixes to match git-log for bindings&dts
+ Merged board .dts & Makefile changes together
+ Rebased on next-20180410
v3:
+ Fixes for suggestions by Geert Uytterhoeven
+ Removed SoC Specific renesas,r9a06g032-xxx, as it's not needed for now.
+ Kept renesas,rzn1 as a family/generic for this family.
+ Fixed a couple of the commit messages.
+ Added Geert's Reviewed-By where appropriate.
v2:
+ Fixes for suggestions by Simon Horman
+ Fixes for suggestions by Rob Herring
+ Fixes for suggestions by Geert Uytterhoeven
+ Removed the mach file
+ Added a MFD base for the sysctrl block
+ Added a regmap based sub driver for the reboot handler
+ Renamed the files to match shmobile conventions
+ Adapted the compatible= strings to reflect 'family' vs 'part'
distinction.
+ Removed the sysctrl.h file entirelly.
+ Fixed every warnings from the DTC compiler on W=12 mode.
+ Split the device-tree patches from the code.
Michel Pollet (6):
dt-bindings: arm: Document the RZN1D-DB board
dt-bindings: Add the rzn1-clocks.h file
dt-bindings: clock: renesas,rzn1-clocks: document RZ/N1 clock driver
ARM: dts: Renesas RZ/N1 SoC base device tree file
ARM: dts: Renesas RZN1D-DB Board base file
clk: renesas: Renesas RZ/N1 clock driver
Documentation/devicetree/bindings/arm/shmobile.txt | 5 +-
.../bindings/clock/renesas,rzn1-clocks.txt | 44 ++
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 29 +
arch/arm/boot/dts/r9a06g032.dtsi | 86 +++
drivers/clk/renesas/Kconfig | 6 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/rzn1-clocks.c | 814 +++++++++++++++++++++
include/dt-bindings/clock/rzn1-clocks.h | 187 +++++
9 files changed, 1172 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt
create mode 100644 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
create mode 100644 arch/arm/boot/dts/r9a06g032.dtsi
create mode 100644 drivers/clk/renesas/rzn1-clocks.c
create mode 100644 include/dt-bindings/clock/rzn1-clocks.h
--
2.7.4
^ permalink raw reply
* [PATCH v6 1/6] dt-bindings: arm: Document the RZN1D-DB board
From: Michel Pollet @ 2018-05-22 10:01 UTC (permalink / raw)
To: linux-renesas-soc, Simon Horman
Cc: phil.edworthy, Michel Pollet, Michel Pollet, Magnus Damm,
Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, devicetree, linux-kernel, linux-clk
In-Reply-To: <1526983321-41949-1-git-send-email-michel.pollet@bp.renesas.com>
This documents the RZ/N1 bindings for the RZN1D-DB board.
Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/arm/shmobile.txt | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index d8cf740..89b4a38 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -51,7 +51,8 @@ SoCs:
compatible = "renesas,r8a77990"
- R-Car D3 (R8A77995)
compatible = "renesas,r8a77995"
-
+ - RZ/N1D (R9A06G032)
+ compatible = "renesas,r9a06g032"
Boards:
@@ -112,6 +113,8 @@ Boards:
compatible = "renesas,porter", "renesas,r8a7791"
- RSKRZA1 (YR0K77210C000BE)
compatible = "renesas,rskrza1", "renesas,r7s72100"
+ - RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package)
+ compatible = "renesas,rzn1d400-db", "renesas,r9a06g032"
- Salvator-X (RTP0RC7795SIPB0010S)
compatible = "renesas,salvator-x", "renesas,r8a7795"
- Salvator-X (RTP0RC7796SIPB0011S)
--
2.7.4
^ permalink raw reply related
* [PATCH v6 2/6] dt-bindings: Add the rzn1-clocks.h file
From: Michel Pollet @ 2018-05-22 10:01 UTC (permalink / raw)
To: linux-renesas-soc, Simon Horman
Cc: phil.edworthy, Michel Pollet, Michel Pollet, Magnus Damm,
Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, devicetree, linux-kernel, linux-clk
In-Reply-To: <1526983321-41949-1-git-send-email-michel.pollet@bp.renesas.com>
This adds the constants necessary to use the renesas,rzn1-clocks driver.
Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
include/dt-bindings/clock/rzn1-clocks.h | 187 ++++++++++++++++++++++++++++++++
1 file changed, 187 insertions(+)
create mode 100644 include/dt-bindings/clock/rzn1-clocks.h
diff --git a/include/dt-bindings/clock/rzn1-clocks.h b/include/dt-bindings/clock/rzn1-clocks.h
new file mode 100644
index 0000000..8a73db2
--- /dev/null
+++ b/include/dt-bindings/clock/rzn1-clocks.h
@@ -0,0 +1,187 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * RZ/N1 clock IDs
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
+ * Derived from zx-reboot.c
+ */
+
+#ifndef __DT_BINDINGS_RZN1_CLOCK_H__
+#define __DT_BINDINGS_RZN1_CLOCK_H__
+
+#define RZN1_CLKOUT 0
+#define RZN1_CLK_PLL_USB 1
+#define RZN1_CLK_48 1 /* AKA CLK_PLL_USB */
+#define RZN1_CLKOUT_D10 2
+#define RZN1_CLKOUT_D16 3
+#define RZN1_MSEBIS_CLK 3 /* AKA CLKOUT_D16 */
+#define RZN1_MSEBIM_CLK 3 /* AKA CLKOUT_D16 */
+#define RZN1_CLKOUT_D160 4
+#define RZN1_CLKOUT_D1OR2 5
+#define RZN1_CLK_DDRPHY_PLLCLK 5 /* AKA CLKOUT_D1OR2 */
+#define RZN1_CLKOUT_D20 6
+#define RZN1_CLK50 6 /* AKA CLKOUT_D20 */
+#define RZN1_CLKOUT_D40 7
+#define RZN1_CLK25 7 /* AKA CLKOUT_D40 */
+#define RZN1_CLKOUT_D5 8
+#define RZN1_CLKOUT_D8 9
+#define RZN1_CLK125 9 /* AKA CLKOUT_D8 */
+#define RZN1_DIV_ADC 10
+#define RZN1_DIV_I2C 11
+#define RZN1_DIV_NAND 12
+#define RZN1_DIV_P1_PG 13
+#define RZN1_DIV_P2_PG 14
+#define RZN1_DIV_P3_PG 15
+#define RZN1_DIV_P4_PG 16
+#define RZN1_DIV_P5_PG 17
+#define RZN1_CLK_P5_PG1 17 /* AKA DIV_P5_PG */
+#define RZN1_DIV_P6_PG 18
+#define RZN1_DIV_QSPI0 19
+#define RZN1_DIV_QSPI1 20
+#define RZN1_DIV_REF_SYNC 21
+#define RZN1_CLK_REF_SYNC 21 /* AKA DIV_REF_SYNC */
+#define RZN1_DIV_SDIO0 22
+#define RZN1_DIV_SDIO1 23
+#define RZN1_DIV_SWITCH 24
+#define RZN1_DIV_UART 25
+#define RZN1_CLK_25_PG4 26
+#define RZN1_CLK_25_PG5 27
+#define RZN1_CLK_25_PG6 28
+#define RZN1_CLK_25_PG7 29
+#define RZN1_CLK_25_PG8 30
+#define RZN1_CLK_ADC 31
+#define RZN1_CLK_ECAT100 32
+#define RZN1_CLK_HSR100 33
+#define RZN1_CLK_I2C0 34
+#define RZN1_CLK_I2C1 35
+#define RZN1_CLK_MII_REF 36
+#define RZN1_CLK_NAND 37
+#define RZN1_CLK_NOUSBP2_PG6 38
+#define RZN1_CLK_P1_PG2 39
+#define RZN1_CLK_P1_PG3 40
+#define RZN1_CLK_P1_PG4 41
+#define RZN1_CLK_P4_PG3 42
+#define RZN1_CLK_P4_PG4 43
+#define RZN1_CLK_P6_PG1 44
+#define RZN1_CLK_P6_PG2 45
+#define RZN1_CLK_P6_PG3 46
+#define RZN1_CLK_P6_PG4 47
+#define RZN1_CLK_PCI_USB 48
+#define RZN1_CLK_QSPI0 49
+#define RZN1_CLK_QSPI1 50
+#define RZN1_CLK_RGMII_REF 51
+#define RZN1_CLK_RMII_REF 52
+#define RZN1_CLK_SDIO0 53
+#define RZN1_CLK_SDIO1 54
+#define RZN1_CLK_SERCOS100 55
+#define RZN1_CLK_SLCD 56
+#define RZN1_CLK_SPI0 57
+#define RZN1_CLK_SPI1 58
+#define RZN1_CLK_SPI2 59
+#define RZN1_CLK_SPI3 60
+#define RZN1_CLK_SPI4 61
+#define RZN1_CLK_SPI5 62
+#define RZN1_CLK_SWITCH 63
+#define RZN1_DIV_MOTOR 64
+#define RZN1_HCLK_ECAT125 65
+#define RZN1_HCLK_PINCONFIG 66
+#define RZN1_HCLK_SERCOS 67
+#define RZN1_HCLK_SGPIO2 68
+#define RZN1_HCLK_SGPIO3 69
+#define RZN1_HCLK_SGPIO4 70
+#define RZN1_HCLK_TIMER0 71
+#define RZN1_HCLK_TIMER1 72
+#define RZN1_HCLK_USBF 73
+#define RZN1_HCLK_USBH 74
+#define RZN1_HCLK_USBPM 75
+#define RZN1_CLK_48_PG_F 76
+#define RZN1_CLK_48_PG4 77
+#define RZN1_CLK_DDRPHY_PLLCLK_D4 78
+#define RZN1_CLK_ECAT100_D4 79
+#define RZN1_CLK_HSR100_D2 80
+#define RZN1_CLK_REF_SYNC_D4 81
+#define RZN1_CLK_DDRPHY_PCLK 81 /* AKA CLK_REF_SYNC_D4 */
+#define RZN1_CLK_FW 81 /* AKA CLK_REF_SYNC_D4 */
+#define RZN1_CLK_CRYPTO 81 /* AKA CLK_REF_SYNC_D4 */
+#define RZN1_CLK_REF_SYNC_D8 82
+#define RZN1_CLK_SERCOS100_D2 83
+#define RZN1_DIV_CA7 84
+#define RZN1_CLK_A7MP 84 /* AKA DIV_CA7 */
+#define RZN1_HCLK_CAN0 85
+#define RZN1_HCLK_CAN1 86
+#define RZN1_HCLK_DELTASIGMA 87
+#define RZN1_HCLK_PWMPTO 88
+#define RZN1_HCLK_RSV 89
+#define RZN1_HCLK_SGPIO0 90
+#define RZN1_HCLK_SGPIO1 91
+#define RZN1_RTOS_MDC 92
+#define RZN1_CLK_CM3 93
+#define RZN1_CLK_DDRC 94
+#define RZN1_CLK_ECAT25 95
+#define RZN1_CLK_HSR50 96
+#define RZN1_CLK_HW_RTOS 97
+#define RZN1_CLK_SERCOS50 98
+#define RZN1_HCLK_ADC 99
+#define RZN1_HCLK_CM3 100
+#define RZN1_HCLK_CRYPTO_EIP150 101
+#define RZN1_HCLK_CRYPTO_EIP93 102
+#define RZN1_HCLK_DDRC 103
+#define RZN1_HCLK_DMA0 104
+#define RZN1_HCLK_DMA1 105
+#define RZN1_HCLK_GMAC0 106
+#define RZN1_HCLK_GMAC1 107
+#define RZN1_HCLK_GPIO0 108
+#define RZN1_HCLK_GPIO1 109
+#define RZN1_HCLK_GPIO2 110
+#define RZN1_HCLK_HSR 111
+#define RZN1_HCLK_I2C0 112
+#define RZN1_HCLK_I2C1 113
+#define RZN1_HCLK_LCD 114
+#define RZN1_HCLK_MSEBI_M 115
+#define RZN1_HCLK_MSEBI_S 116
+#define RZN1_HCLK_NAND 117
+#define RZN1_HCLK_PG_I 118
+#define RZN1_HCLK_PG19 119
+#define RZN1_HCLK_PG20 120
+#define RZN1_HCLK_PG3 121
+#define RZN1_HCLK_PG4 122
+#define RZN1_HCLK_QSPI0 123
+#define RZN1_HCLK_QSPI1 124
+#define RZN1_HCLK_ROM 125
+#define RZN1_HCLK_RTC 126
+#define RZN1_HCLK_SDIO0 127
+#define RZN1_HCLK_SDIO1 128
+#define RZN1_HCLK_SEMAP 129
+#define RZN1_HCLK_SPI0 130
+#define RZN1_HCLK_SPI1 131
+#define RZN1_HCLK_SPI2 132
+#define RZN1_HCLK_SPI3 133
+#define RZN1_HCLK_SPI4 134
+#define RZN1_HCLK_SPI5 135
+#define RZN1_HCLK_SWITCH 136
+#define RZN1_HCLK_SWITCH_RG 137
+#define RZN1_HCLK_UART0 138
+#define RZN1_HCLK_UART1 139
+#define RZN1_HCLK_UART2 140
+#define RZN1_HCLK_UART3 141
+#define RZN1_HCLK_UART4 142
+#define RZN1_HCLK_UART5 143
+#define RZN1_HCLK_UART6 144
+#define RZN1_HCLK_UART7 145
+#define RZN1_CLK_UART0 146
+#define RZN1_CLK_UART1 147
+#define RZN1_CLK_UART2 148
+#define RZN1_CLK_UART3 149
+#define RZN1_CLK_UART4 150
+#define RZN1_CLK_UART5 151
+#define RZN1_CLK_UART6 152
+#define RZN1_CLK_UART7 153
+
+#define RZN1_UART_GROUP_012 154
+#define RZN1_UART_GROUP_34567 155
+
+#define RZN1_CLOCK_COUNT (RZN1_UART_GROUP_34567 + 1)
+
+#endif /* __DT_BINDINGS_RZN1_CLOCK_H__ */
--
2.7.4
^ permalink raw reply related
* [PATCH v6 3/6] dt-bindings: clock: renesas,rzn1-clocks: document RZ/N1 clock driver
From: Michel Pollet @ 2018-05-22 10:01 UTC (permalink / raw)
To: linux-renesas-soc, Simon Horman
Cc: phil.edworthy, Michel Pollet, Michel Pollet, Magnus Damm,
Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, devicetree, linux-kernel, linux-clk
In-Reply-To: <1526983321-41949-1-git-send-email-michel.pollet@bp.renesas.com>
The Renesas RZ/N1 Family (Part #R9A06G0xx) requires a driver
to provide the SoC clock infrastructure for Linux.
This documents the driver bindings.
Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
.../bindings/clock/renesas,rzn1-clocks.txt | 44 ++++++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt
diff --git a/Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt
new file mode 100644
index 0000000..0c41137
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,rzn1-clocks.txt
@@ -0,0 +1,44 @@
+* Renesas RZ/N1 Clock Driver
+
+This driver provides the clock infrastructure used by all the other drivers.
+
+One of the 'special' feature of this infrastructure is that Linux doesn't
+necessary 'own' all the clocks on the SoC, some other OS runs on
+the Cortex-M3 core and that OS can access and claim it's own clocks.
+
+Required Properties:
+
+ - compatible: Must be
+ - "renesas,r9a06g032-clocks" for the RZ/N1D
+ and "renesas,rzn1-clocks" as a fallback.
+ - reg: Base address and length of the memory resource used by the driver
+ - #clock-cells: Must be 1
+
+Examples
+--------
+
+ - Clock driver device node:
+
+ clock: clocks@4000c000 {
+ compatible = "renesas,r9a06g032-clocks",
+ "renesas,rzn1-clocks";
+ reg = <0x4000c000 0x1000>;
+ status = "okay";
+ #clock-cells = <1>;
+ };
+
+
+ - Other drivers can use the clocks as in:
+
+ uart0: serial@40060000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x40060000 0x400>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&clock RZN1_CLK_UART0>;
+ clock-names = "baudclk";
+ };
+ Note the use of RZN1_CLK_UART0 -- these constants are declared in
+ the rzn1-clocks.h header file. These are not hardware based constants
+ and are Linux specific.
--
2.7.4
^ permalink raw reply related
* [PATCH v6 4/6] ARM: dts: Renesas RZ/N1 SoC base device tree file
From: Michel Pollet @ 2018-05-22 10:01 UTC (permalink / raw)
To: linux-renesas-soc, Simon Horman
Cc: phil.edworthy, Michel Pollet, Michel Pollet, Magnus Damm,
Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, devicetree, linux-kernel, linux-clk
In-Reply-To: <1526983321-41949-1-git-send-email-michel.pollet@bp.renesas.com>
This adds the Renesas RZ/N1D (Part #R9A06G032) SoC bare
bone support.
This currently only handles generic parts (gic, architected timer)
and a UART.
For simplicity sake, this also relies on the bootloader to set the
pinctrl and clocks.
Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
arch/arm/boot/dts/r9a06g032.dtsi | 86 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 86 insertions(+)
create mode 100644 arch/arm/boot/dts/r9a06g032.dtsi
diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi
new file mode 100644
index 0000000..c7764c7
--- /dev/null
+++ b/arch/arm/boot/dts/r9a06g032.dtsi
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/rzn1-clock.h>
+
+/ {
+ compatible = "renesas,r9a06g032", "renesas,rzn1";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clock RZN1_DIV_CA7>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <1>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+ ranges;
+
+ clock: clocks@4000c000 {
+ compatible = "renesas,r9a06g032-clocks",
+ "renesas,rzn1-clocks";
+ reg = <0x4000c000 0x1000>;
+ status = "okay";
+ #clock-cells = <1>;
+ };
+
+ uart0: serial@40060000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x40060000 0x400>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clocks = <&clock RZN1_CLK_UART0>;
+ clock-names = "baudclk";
+ status = "disabled";
+ };
+
+ gic: gic@44101000 {
+ compatible = "arm,cortex-a7-gic", "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x44101000 0x1000>, /* Distributer */
+ <0x44102000 0x2000>, /* CPU interface */
+ <0x44104000 0x2000>, /* Virt interface control */
+ <0x44106000 0x2000>; /* Virt CPU interface */
+ interrupts =
+ <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+ };
+
+ timer {
+ compatible = "arm,cortex-a7-timer",
+ "arm,armv7-timer";
+ interrupt-parent = <&gic>;
+ arm,cpu-registers-not-fw-configured;
+ always-on;
+ interrupts =
+ <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH v6 5/6] ARM: dts: Renesas RZN1D-DB Board base file
From: Michel Pollet @ 2018-05-22 10:01 UTC (permalink / raw)
To: linux-renesas-soc, Simon Horman
Cc: phil.edworthy, Michel Pollet, Michel Pollet, Magnus Damm,
Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, devicetree, linux-kernel, linux-clk
In-Reply-To: <1526983321-41949-1-git-send-email-michel.pollet@bp.renesas.com>
This adds a base device tree file for the RZN1-DB board, with only the
basic support allowing the system to boot to a prompt. Only one UART is
used, with only a single CPU running.
Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts | 29 +++++++++++++++++++++++++++++
2 files changed, 30 insertions(+)
create mode 100644 arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f4753b0..6157897 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -814,6 +814,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a7793-gose.dtb \
r8a7794-alt.dtb \
r8a7794-silk.dtb \
+ r9a06g032-rzn1d400-db.dtb \
sh73a0-kzm9g.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rv1108-evb.dtb \
diff --git a/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
new file mode 100644
index 0000000..5fc2c40
--- /dev/null
+++ b/arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the RZN1D-DB Board
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ */
+
+/dts-v1/;
+
+#include "r9a06g032.dtsi"
+
+/ {
+ model = "RZN1D-DB Board";
+ compatible = "renesas,rzn1d400-db",
+ "renesas,r9a06g032", "renesas,rzn1";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
--
2.7.4
^ permalink raw reply related
* [PATCH v6 6/6] clk: renesas: Renesas RZ/N1 clock driver
From: Michel Pollet @ 2018-05-22 10:01 UTC (permalink / raw)
To: linux-renesas-soc, Simon Horman
Cc: phil.edworthy, Michel Pollet, Michel Pollet, Magnus Damm,
Rob Herring, Mark Rutland, Michael Turquette, Stephen Boyd,
Geert Uytterhoeven, devicetree, linux-kernel, linux-clk
In-Reply-To: <1526983321-41949-1-git-send-email-michel.pollet@bp.renesas.com>
This provides a clock driver for the Renesas RZ/N1 parts (#R09A06G0xx).
This uses a structure derived from both the RCAR gen2 driver as well as
the renesas-cpg-mssr driver.
Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
---
drivers/clk/renesas/Kconfig | 6 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/rzn1-clocks.c | 814 ++++++++++++++++++++++++++++++++++++++
3 files changed, 821 insertions(+)
create mode 100644 drivers/clk/renesas/rzn1-clocks.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index f9ba71311..bdb8129 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -21,6 +21,7 @@ config CLK_RENESAS
select CLK_R8A77980 if ARCH_R8A77980
select CLK_R8A77990 if ARCH_R8A77990
select CLK_R8A77995 if ARCH_R8A77995
+ select CLK_RZN1 if ARCH_RZN1
select CLK_SH73A0 if ARCH_SH73A0
if CLK_RENESAS
@@ -151,6 +152,11 @@ config CLK_RCAR_USB2_CLOCK_SEL
help
This is a driver for R-Car USB2 clock selector
+config CLK_RZN1
+ bool "Renesas RZ/N1 clock driver"
+ help
+ This is a driver for RZ/N1 clocks
+
# Generic
config CLK_RENESAS_CPG_MSSR
bool "CPG/MSSR clock support" if COMPILE_TEST
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index fe5bac9..754281c 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o
obj-$(CONFIG_CLK_RCAR_GEN2_CPG) += rcar-gen2-cpg.o
obj-$(CONFIG_CLK_RCAR_GEN3_CPG) += rcar-gen3-cpg.o
obj-$(CONFIG_CLK_RCAR_USB2_CLOCK_SEL) += rcar-usb2-clock-sel.o
+obj-$(CONFIG_CLK_RZN1) += rzn1-clocks.o
# Generic
obj-$(CONFIG_CLK_RENESAS_CPG_MSSR) += renesas-cpg-mssr.o
diff --git a/drivers/clk/renesas/rzn1-clocks.c b/drivers/clk/renesas/rzn1-clocks.c
new file mode 100644
index 0000000..06c176b
--- /dev/null
+++ b/drivers/clk/renesas/rzn1-clocks.c
@@ -0,0 +1,814 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RZ/N1 clock driver
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ * Michel Pollet <michel.pollet@bp.renesas.com>, <buserror@gmail.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/math64.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <dt-bindings/clock/rzn1-clocks.h>
+
+struct rzn1_gate {
+ uint16_t gate, reset, ready, midle,
+ scon, mirack, mistat;
+};
+
+/* This is used to describe a clock for instantiation */
+struct rzn1_clkdesc {
+ const char *name;
+ uint32_t type: 3;
+ uint32_t index: 8;
+ uint32_t source : 8; /* source index + 1 (0 == none) */
+ /* these are used to populate the bitsel struct */
+ union {
+ struct rzn1_gate gate;
+ /* for dividers */
+ struct {
+ unsigned int div_min : 10, div_max : 10, reg: 10;
+ uint16_t div_table[4];
+ };
+ /* For fixed-factor ones */
+ uint16_t div;
+ unsigned int factor;
+ unsigned int frequency;
+ /* for dual gate */
+ struct {
+ uint16_t group : 1, index: 3;
+ uint16_t sel, g1, r1, g2, r2;
+ } dual;
+ };
+} __packed;
+
+#define I_GATE(_clk, _rst, _rdy, _midle, _scon, _mirack, _mistat) \
+ { .gate = _clk, .reset = _rst, \
+ .ready = _rdy, .midle = _midle, \
+ .scon = _scon, .mirack = _mirack, .mistat = _mistat }
+#define D_GATE(_idx, _n, _src, ...) \
+ { .type = K_GATE, .index = RZN1_##_idx, \
+ .source = 1 + RZN1_##_src, .name = _n, \
+ .gate = I_GATE(__VA_ARGS__), }
+#define D_FC(_idx, _n, _freq) \
+ { .type = K_FC, .index = RZN1_##_idx, .name = _n, .frequency = _freq, }
+#define D_FFC(_idx, _n, _src, _div) \
+ { .type = K_FFC, .index = RZN1_##_idx, \
+ .source = 1 + RZN1_##_src, .name = _n, \
+ .div = _div, }
+#define D_DIV(_idx, _n, _src, _reg, _min, _max, ...) \
+ { .type = K_DIV, .index = RZN1_##_idx, \
+ .source = 1 + RZN1_##_src, .name = _n, \
+ .reg = _reg, .div_min = _min, .div_max = _max, \
+ .div_table = { __VA_ARGS__ } }
+#define D_UGATE(_idx, _n, _src, _g, _gi, _g1, _r1, _g2, _r2) \
+ { .type = K_DUALGATE, .index = RZN1_##_idx, \
+ .source = 1 + RZN1_##_src, .name = _n, \
+ .dual = { .group = _g, .index = _gi, \
+ .g1 = _g1, .r1 = _r1, .g2 = _g2, .r2 = _r2 }, }
+
+enum { K_GATE = 0, K_FFC, K_FC, K_DIV, K_BITSEL, K_DUALGATE };
+
+static const struct rzn1_clkdesc rzn1_clocks[] __initconst = {
+ D_FC(CLKOUT, "clkout", 1000000000),
+ D_FC(CLK_PLL_USB, "clk_pll_usb", 48000000),
+ D_FFC(CLKOUT_D10, "clkout_d10", CLKOUT, 10),
+ D_FFC(CLKOUT_D16, "clkout_d16", CLKOUT, 16),
+ D_FFC(CLKOUT_D160, "clkout_d160", CLKOUT, 160),
+ D_DIV(CLKOUT_D1OR2, "clkout_d1or2", CLKOUT, 0, 1, 2),
+ D_FFC(CLKOUT_D20, "clkout_d20", CLKOUT, 20),
+ D_FFC(CLKOUT_D40, "clkout_d40", CLKOUT, 40),
+ D_FFC(CLKOUT_D5, "clkout_d5", CLKOUT, 5),
+ D_FFC(CLKOUT_D8, "clkout_d8", CLKOUT, 8),
+ D_DIV(DIV_ADC, "div_adc", CLKOUT, 77, 50, 250),
+ D_DIV(DIV_I2C, "div_i2c", CLKOUT, 78, 12, 16),
+ D_DIV(DIV_NAND, "div_nand", CLKOUT, 82, 12, 32),
+ D_DIV(DIV_P1_PG, "div_p1_pg", CLKOUT, 68, 12, 200),
+ D_DIV(DIV_P2_PG, "div_p2_pg", CLKOUT, 62, 12, 128),
+ D_DIV(DIV_P3_PG, "div_p3_pg", CLKOUT, 64, 8, 128),
+ D_DIV(DIV_P4_PG, "div_p4_pg", CLKOUT, 66, 8, 128),
+ D_DIV(DIV_P5_PG, "div_p5_pg", CLKOUT, 71, 10, 40),
+ D_DIV(DIV_P6_PG, "div_p6_pg", CLKOUT, 18, 12, 64),
+ D_DIV(DIV_QSPI0, "div_qspi0", CLKOUT, 73, 3, 7),
+ D_DIV(DIV_QSPI1, "div_qspi1", CLKOUT, 25, 3, 7),
+ D_DIV(DIV_REF_SYNC, "div_ref_sync", CLKOUT, 56, 2, 16, 2, 4, 8, 16),
+ D_DIV(DIV_SDIO0, "div_sdio0", CLKOUT, 74, 20, 128),
+ D_DIV(DIV_SDIO1, "div_sdio1", CLKOUT, 75, 20, 128),
+ D_DIV(DIV_SWITCH, "div_switch", CLKOUT, 37, 5, 40),
+ D_DIV(DIV_UART, "div_uart", CLKOUT, 79, 12, 128),
+ D_GATE(CLK_25_PG4, "clk_25_pg4", CLKOUT_D40, 0x749, 0x74a, 0x74b, 0, 0xae3, 0, 0),
+ D_GATE(CLK_25_PG5, "clk_25_pg5", CLKOUT_D40, 0x74c, 0x74d, 0x74e, 0, 0xae4, 0, 0),
+ D_GATE(CLK_25_PG6, "clk_25_pg6", CLKOUT_D40, 0x74f, 0x750, 0x751, 0, 0xae5, 0, 0),
+ D_GATE(CLK_25_PG7, "clk_25_pg7", CLKOUT_D40, 0x752, 0x753, 0x754, 0, 0xae6, 0, 0),
+ D_GATE(CLK_25_PG8, "clk_25_pg8", CLKOUT_D40, 0x755, 0x756, 0x757, 0, 0xae7, 0, 0),
+ D_GATE(CLK_ADC, "clk_adc", DIV_ADC, 0x1ea, 0x1eb, 0, 0, 0, 0, 0),
+ D_GATE(CLK_ECAT100, "clk_ecat100", CLKOUT_D10, 0x405, 0, 0, 0, 0, 0, 0),
+ D_GATE(CLK_HSR100, "clk_hsr100", CLKOUT_D10, 0x483, 0, 0, 0, 0, 0, 0),
+ D_GATE(CLK_I2C0, "clk_i2c0", DIV_I2C, 0x1e6, 0x1e7, 0, 0, 0, 0, 0),
+ D_GATE(CLK_I2C1, "clk_i2c1", DIV_I2C, 0x1e8, 0x1e9, 0, 0, 0, 0, 0),
+ D_GATE(CLK_MII_REF, "clk_mii_ref", CLKOUT_D40, 0x342, 0, 0, 0, 0, 0, 0),
+ D_GATE(CLK_NAND, "clk_nand", DIV_NAND, 0x284, 0x285, 0, 0, 0, 0, 0),
+ D_GATE(CLK_NOUSBP2_PG6, "clk_nousbp2_pg6", DIV_P2_PG, 0x774, 0x775, 0, 0, 0, 0, 0),
+ D_GATE(CLK_P1_PG2, "clk_p1_pg2", DIV_P1_PG, 0x862, 0x863, 0, 0, 0, 0, 0),
+ D_GATE(CLK_P1_PG3, "clk_p1_pg3", DIV_P1_PG, 0x864, 0x865, 0, 0, 0, 0, 0),
+ D_GATE(CLK_P1_PG4, "clk_p1_pg4", DIV_P1_PG, 0x866, 0x867, 0, 0, 0, 0, 0),
+ D_GATE(CLK_P4_PG3, "clk_p4_pg3", DIV_P4_PG, 0x824, 0x825, 0, 0, 0, 0, 0),
+ D_GATE(CLK_P4_PG4, "clk_p4_pg4", DIV_P4_PG, 0x826, 0x827, 0, 0, 0, 0, 0),
+ D_GATE(CLK_P6_PG1, "clk_p6_pg1", DIV_P6_PG, 0x8a0, 0x8a1, 0x8a2, 0, 0xb60, 0, 0),
+ D_GATE(CLK_P6_PG2, "clk_p6_pg2", DIV_P6_PG, 0x8a3, 0x8a4, 0x8a5, 0, 0xb61, 0, 0),
+ D_GATE(CLK_P6_PG3, "clk_p6_pg3", DIV_P6_PG, 0x8a6, 0x8a7, 0x8a8, 0, 0xb62, 0, 0),
+ D_GATE(CLK_P6_PG4, "clk_p6_pg4", DIV_P6_PG, 0x8a9, 0x8aa, 0x8ab, 0, 0xb63, 0, 0),
+ D_GATE(CLK_QSPI0, "clk_qspi0", DIV_QSPI0, 0x2a4, 0x2a5, 0, 0, 0, 0, 0),
+ D_GATE(CLK_QSPI1, "clk_qspi1", DIV_QSPI1, 0x484, 0x485, 0, 0, 0, 0, 0),
+ D_GATE(CLK_RGMII_REF, "clk_rgmii_ref", CLKOUT_D8, 0x340, 0, 0, 0, 0, 0, 0),
+ D_GATE(CLK_RMII_REF, "clk_rmii_ref", CLKOUT_D20, 0x341, 0, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SDIO0, "clk_sdio0", DIV_SDIO0, 0x64, 0, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SDIO1, "clk_sdio1", DIV_SDIO1, 0x644, 0, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SERCOS100, "clk_sercos100", CLKOUT_D10, 0x425, 0, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SLCD, "clk_slcd", DIV_P1_PG, 0x860, 0x861, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SPI0, "clk_spi0", DIV_P3_PG, 0x7e0, 0x7e1, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SPI1, "clk_spi1", DIV_P3_PG, 0x7e2, 0x7e3, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SPI2, "clk_spi2", DIV_P3_PG, 0x7e4, 0x7e5, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SPI3, "clk_spi3", DIV_P3_PG, 0x7e6, 0x7e7, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SPI4, "clk_spi4", DIV_P4_PG, 0x820, 0x821, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SPI5, "clk_spi5", DIV_P4_PG, 0x822, 0x823, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SWITCH, "clk_switch", DIV_SWITCH, 0x982, 0x983, 0, 0, 0, 0, 0),
+ D_DIV(DIV_MOTOR, "div_motor", CLKOUT_D5, 84, 2, 8),
+ D_GATE(HCLK_ECAT125, "hclk_ecat125", CLKOUT_D8, 0x400, 0x401, 0, 0x402, 0, 0x440, 0x441),
+ D_GATE(HCLK_PINCONFIG, "hclk_pinconfig", CLKOUT_D40, 0x740, 0x741, 0x742, 0, 0xae0, 0, 0),
+ D_GATE(HCLK_SERCOS, "hclk_sercos", CLKOUT_D10, 0x420, 0x422, 0, 0x421, 0, 0x460, 0x461),
+ D_GATE(HCLK_SGPIO2, "hclk_sgpio2", DIV_P5_PG, 0x8c3, 0x8c4, 0x8c5, 0, 0xb41, 0, 0),
+ D_GATE(HCLK_SGPIO3, "hclk_sgpio3", DIV_P5_PG, 0x8c6, 0x8c7, 0x8c8, 0, 0xb42, 0, 0),
+ D_GATE(HCLK_SGPIO4, "hclk_sgpio4", DIV_P5_PG, 0x8c9, 0x8ca, 0x8cb, 0, 0xb43, 0, 0),
+ D_GATE(HCLK_TIMER0, "hclk_timer0", CLKOUT_D40, 0x743, 0x744, 0x745, 0, 0xae1, 0, 0),
+ D_GATE(HCLK_TIMER1, "hclk_timer1", CLKOUT_D40, 0x746, 0x747, 0x748, 0, 0xae2, 0, 0),
+ D_GATE(HCLK_USBF, "hclk_usbf", CLKOUT_D8, 0xe3, 0, 0, 0xe4, 0, 0x102, 0x103),
+ D_GATE(HCLK_USBH, "hclk_usbh", CLKOUT_D8, 0xe0, 0xe1, 0, 0xe2, 0, 0x100, 0x101),
+ D_GATE(HCLK_USBPM, "hclk_usbpm", CLKOUT_D8, 0xe5, 0, 0, 0, 0, 0, 0),
+ D_GATE(CLK_48_PG_F, "clk_48_pg_f", CLK_48, 0x78c, 0x78d, 0, 0x78e, 0, 0xb04, 0xb05),
+ D_GATE(CLK_48_PG4, "clk_48_pg4", CLK_48, 0x789, 0x78a, 0x78b, 0, 0xb03, 0, 0),
+ D_FFC(CLK_DDRPHY_PLLCLK_D4, "clk_ddrphy_pllclk_d4", CLK_DDRPHY_PLLCLK, 4),
+ D_FFC(CLK_ECAT100_D4, "clk_ecat100_d4", CLK_ECAT100, 4),
+ D_FFC(CLK_HSR100_D2, "clk_hsr100_d2", CLK_HSR100, 2),
+ D_FFC(CLK_REF_SYNC_D4, "clk_ref_sync_d4", CLK_REF_SYNC, 4),
+ D_FFC(CLK_REF_SYNC_D8, "clk_ref_sync_d8", CLK_REF_SYNC, 8),
+ D_FFC(CLK_SERCOS100_D2, "clk_sercos100_d2", CLK_SERCOS100, 2),
+ D_DIV(DIV_CA7, "div_ca7", CLK_REF_SYNC, 57, 1, 4, 1, 2, 4),
+ D_GATE(HCLK_CAN0, "hclk_can0", CLK_48, 0x783, 0x784, 0x785, 0, 0xb01, 0, 0),
+ D_GATE(HCLK_CAN1, "hclk_can1", CLK_48, 0x786, 0x787, 0x788, 0, 0xb02, 0, 0),
+ D_GATE(HCLK_DELTASIGMA, "hclk_deltasigma", DIV_MOTOR, 0x1ef, 0x1f0, 0x1f1, 0, 0, 0, 0),
+ D_GATE(HCLK_PWMPTO, "hclk_pwmpto", DIV_MOTOR, 0x1ec, 0x1ed, 0x1ee, 0, 0, 0, 0),
+ D_GATE(HCLK_RSV, "hclk_rsv", CLK_48, 0x780, 0x781, 0x782, 0, 0xb00, 0, 0),
+ D_GATE(HCLK_SGPIO0, "hclk_sgpio0", DIV_MOTOR, 0x1e0, 0x1e1, 0x1e2, 0, 0, 0, 0),
+ D_GATE(HCLK_SGPIO1, "hclk_sgpio1", DIV_MOTOR, 0x1e3, 0x1e4, 0x1e5, 0, 0, 0, 0),
+ D_DIV(RTOS_MDC, "rtos_mdc", CLK_REF_SYNC, 100, 80, 640, 80, 160, 320, 640),
+ D_GATE(CLK_CM3, "clk_cm3", CLK_REF_SYNC_D4, 0xba0, 0xba1, 0, 0xba2, 0, 0xbc0, 0xbc1),
+ D_GATE(CLK_DDRC, "clk_ddrc", CLK_DDRPHY_PLLCLK_D4, 0x323, 0x324, 0, 0, 0, 0, 0),
+ D_GATE(CLK_ECAT25, "clk_ecat25", CLK_ECAT100_D4, 0x403, 0x404, 0, 0, 0, 0, 0),
+ D_GATE(CLK_HSR50, "clk_hsr50", CLK_HSR100_D2, 0x484, 0x485, 0, 0, 0, 0, 0),
+ D_GATE(CLK_HW_RTOS, "clk_hw_rtos", CLK_REF_SYNC_D4, 0xc60, 0xc61, 0, 0, 0, 0, 0),
+ D_GATE(CLK_SERCOS50, "clk_sercos50", CLK_SERCOS100_D2, 0x424, 0x423, 0, 0, 0, 0, 0),
+ D_GATE(HCLK_ADC, "hclk_adc", CLK_REF_SYNC_D8, 0x1af, 0x1b0, 0x1b1, 0, 0, 0, 0),
+ D_GATE(HCLK_CM3, "hclk_cm3", CLK_REF_SYNC_D4, 0xc20, 0xc21, 0xc22, 0, 0, 0, 0),
+ D_GATE(HCLK_CRYPTO_EIP150, "hclk_crypto_eip150", CLK_REF_SYNC_D4, 0x123, 0x124, 0x125, 0, 0x142, 0, 0),
+ D_GATE(HCLK_CRYPTO_EIP93, "hclk_crypto_eip93", CLK_REF_SYNC_D4, 0x120, 0x121, 0, 0x122, 0, 0x140, 0x141),
+ D_GATE(HCLK_DDRC, "hclk_ddrc", CLK_REF_SYNC_D4, 0x320, 0x322, 0, 0x321, 0, 0x3a0, 0x3a1),
+ D_GATE(HCLK_DMA0, "hclk_dma0", CLK_REF_SYNC_D4, 0x260, 0x261, 0x262, 0x263, 0x2c0, 0x2c1, 0x2c2),
+ D_GATE(HCLK_DMA1, "hclk_dma1", CLK_REF_SYNC_D4, 0x264, 0x265, 0x266, 0x267, 0x2c3, 0x2c4, 0x2c5),
+ D_GATE(HCLK_GMAC0, "hclk_gmac0", CLK_REF_SYNC_D4, 0x360, 0x361, 0x362, 0x363, 0x3c0, 0x3c1, 0x3c2),
+ D_GATE(HCLK_GMAC1, "hclk_gmac1", CLK_REF_SYNC_D4, 0x380, 0x381, 0x382, 0x383, 0x3e0, 0x3e1, 0x3e2),
+ D_GATE(HCLK_GPIO0, "hclk_gpio0", CLK_REF_SYNC_D4, 0x212, 0x213, 0x214, 0, 0, 0, 0),
+ D_GATE(HCLK_GPIO1, "hclk_gpio1", CLK_REF_SYNC_D4, 0x215, 0x216, 0x217, 0, 0, 0, 0),
+ D_GATE(HCLK_GPIO2, "hclk_gpio2", CLK_REF_SYNC_D4, 0x229, 0x22a, 0x22b, 0, 0, 0, 0),
+ D_GATE(HCLK_HSR, "hclk_hsr", CLK_HSR100_D2, 0x480, 0x482, 0, 0x481, 0, 0x4c0, 0x4c1),
+ D_GATE(HCLK_I2C0, "hclk_i2c0", CLK_REF_SYNC_D8, 0x1a9, 0x1aa, 0x1ab, 0, 0, 0, 0),
+ D_GATE(HCLK_I2C1, "hclk_i2c1", CLK_REF_SYNC_D8, 0x1ac, 0x1ad, 0x1ae, 0, 0, 0, 0),
+ D_GATE(HCLK_LCD, "hclk_lcd", CLK_REF_SYNC_D4, 0x7a0, 0x7a1, 0x7a2, 0, 0xb20, 0, 0),
+ D_GATE(HCLK_MSEBI_M, "hclk_msebi_m", CLK_REF_SYNC_D4, 0x164, 0x165, 0x166, 0, 0x183, 0, 0),
+ D_GATE(HCLK_MSEBI_S, "hclk_msebi_s", CLK_REF_SYNC_D4, 0x160, 0x161, 0x162, 0x163, 0x180, 0x181, 0x182),
+ D_GATE(HCLK_NAND, "hclk_nand", CLK_REF_SYNC_D4, 0x280, 0x281, 0x282, 0x283, 0x2e0, 0x2e1, 0x2e2),
+ D_GATE(HCLK_PG_I, "hclk_pg_i", CLK_REF_SYNC_D4, 0x7ac, 0x7ad, 0, 0x7ae, 0, 0xb24, 0xb25),
+ D_GATE(HCLK_PG19, "hclk_pg19", CLK_REF_SYNC_D4, 0x22c, 0x22d, 0x22e, 0, 0, 0, 0),
+ D_GATE(HCLK_PG20, "hclk_pg20", CLK_REF_SYNC_D4, 0x22f, 0x230, 0x231, 0, 0, 0, 0),
+ D_GATE(HCLK_PG3, "hclk_pg3", CLK_REF_SYNC_D4, 0x7a6, 0x7a7, 0x7a8, 0, 0xb22, 0, 0),
+ D_GATE(HCLK_PG4, "hclk_pg4", CLK_REF_SYNC_D4, 0x7a9, 0x7aa, 0x7ab, 0, 0xb23, 0, 0),
+ D_GATE(HCLK_QSPI0, "hclk_qspi0", CLK_REF_SYNC_D4, 0x2a0, 0x2a1, 0x2a2, 0x2a3, 0x300, 0x301, 0x302),
+ D_GATE(HCLK_QSPI1, "hclk_qspi1", CLK_REF_SYNC_D4, 0x480, 0x481, 0x482, 0x483, 0x4c0, 0x4c1, 0x4c2),
+ D_GATE(HCLK_ROM, "hclk_rom", CLK_REF_SYNC_D4, 0xaa0, 0xaa1, 0xaa2, 0, 0xb80, 0, 0),
+ D_GATE(HCLK_RTC, "hclk_rtc", CLK_REF_SYNC_D8, 0xa00, 0, 0, 0, 0, 0, 0),
+ D_GATE(HCLK_SDIO0, "hclk_sdio0", CLK_REF_SYNC_D4, 0x60, 0x61, 0x62, 0x63, 0x80, 0x81, 0x82),
+ D_GATE(HCLK_SDIO1, "hclk_sdio1", CLK_REF_SYNC_D4, 0x640, 0x641, 0x642, 0x643, 0x660, 0x661, 0x662),
+ D_GATE(HCLK_SEMAP, "hclk_semap", CLK_REF_SYNC_D4, 0x7a3, 0x7a4, 0x7a5, 0, 0xb21, 0, 0),
+ D_GATE(HCLK_SPI0, "hclk_spi0", CLK_REF_SYNC_D4, 0x200, 0x201, 0x202, 0, 0, 0, 0),
+ D_GATE(HCLK_SPI1, "hclk_spi1", CLK_REF_SYNC_D4, 0x203, 0x204, 0x205, 0, 0, 0, 0),
+ D_GATE(HCLK_SPI2, "hclk_spi2", CLK_REF_SYNC_D4, 0x206, 0x207, 0x208, 0, 0, 0, 0),
+ D_GATE(HCLK_SPI3, "hclk_spi3", CLK_REF_SYNC_D4, 0x209, 0x20a, 0x20b, 0, 0, 0, 0),
+ D_GATE(HCLK_SPI4, "hclk_spi4", CLK_REF_SYNC_D4, 0x20c, 0x20d, 0x20e, 0, 0, 0, 0),
+ D_GATE(HCLK_SPI5, "hclk_spi5", CLK_REF_SYNC_D4, 0x20f, 0x210, 0x211, 0, 0, 0, 0),
+ D_GATE(HCLK_SWITCH, "hclk_switch", CLK_REF_SYNC_D4, 0x980, 0, 0x981, 0, 0, 0, 0),
+ D_GATE(HCLK_SWITCH_RG, "hclk_switch_rg", CLK_REF_SYNC_D4, 0xc40, 0xc41, 0xc42, 0, 0, 0, 0),
+ D_GATE(HCLK_UART0, "hclk_uart0", CLK_REF_SYNC_D8, 0x1a0, 0x1a1, 0x1a2, 0, 0, 0, 0),
+ D_GATE(HCLK_UART1, "hclk_uart1", CLK_REF_SYNC_D8, 0x1a3, 0x1a4, 0x1a5, 0, 0, 0, 0),
+ D_GATE(HCLK_UART2, "hclk_uart2", CLK_REF_SYNC_D8, 0x1a6, 0x1a7, 0x1a8, 0, 0, 0, 0),
+ D_GATE(HCLK_UART3, "hclk_uart3", CLK_REF_SYNC_D4, 0x218, 0x219, 0x21a, 0, 0, 0, 0),
+ D_GATE(HCLK_UART4, "hclk_uart4", CLK_REF_SYNC_D4, 0x21b, 0x21c, 0x21d, 0, 0, 0, 0),
+ D_GATE(HCLK_UART5, "hclk_uart5", CLK_REF_SYNC_D4, 0x220, 0x221, 0x222, 0, 0, 0, 0),
+ D_GATE(HCLK_UART6, "hclk_uart6", CLK_REF_SYNC_D4, 0x223, 0x224, 0x225, 0, 0, 0, 0),
+ D_GATE(HCLK_UART7, "hclk_uart7", CLK_REF_SYNC_D4, 0x226, 0x227, 0x228, 0, 0, 0, 0),
+ /*
+ * These are not hardware clocks, but are needed to handle the special
+ * case where we have a 'selector bit' that doesn't just change the
+ * parent for a clock, but also the gate it's suposed to use.
+ */
+ {
+ .index = RZN1_UART_GROUP_012,
+ .name = "uart_group_012",
+ .type = K_BITSEL,
+ .source = 1 + RZN1_DIV_UART,
+ /* RZN1_SYSCTRL_REG_PWRCTRL_PG1_PR2 */
+ .dual.sel = ((0xec / 4) << 5) | 24,
+ .dual.group = 0,
+ },
+ {
+ .index = RZN1_UART_GROUP_34567,
+ .name = "uart_group_34567",
+ .type = K_BITSEL,
+ .source = 1 + RZN1_DIV_P2_PG,
+ /* RZN1_SYSCTRL_REG_PWRCTRL_PG0_0 */
+ .dual.sel = ((0x34 / 4) << 5) | 30,
+ .dual.group = 1,
+ },
+ D_UGATE(CLK_UART0, "clk_uart0", UART_GROUP_012, 0, 0, 0x1b2, 0x1b3, 0x1b4, 0x1b5),
+ D_UGATE(CLK_UART1, "clk_uart1", UART_GROUP_012, 0, 1, 0x1b6, 0x1b7, 0x1b8, 0x1b9),
+ D_UGATE(CLK_UART2, "clk_uart2", UART_GROUP_012, 0, 2, 0x1ba, 0x1bb, 0x1bc, 0x1bd),
+ D_UGATE(CLK_UART3, "clk_uart3", UART_GROUP_34567, 1, 0, 0x760, 0x761, 0x762, 0x763),
+ D_UGATE(CLK_UART4, "clk_uart4", UART_GROUP_34567, 1, 1, 0x764, 0x765, 0x766, 0x767),
+ D_UGATE(CLK_UART5, "clk_uart5", UART_GROUP_34567, 1, 2, 0x768, 0x769, 0x76a, 0x76b),
+ D_UGATE(CLK_UART6, "clk_uart6", UART_GROUP_34567, 1, 3, 0x76c, 0x76d, 0x76e, 0x76f),
+ D_UGATE(CLK_UART7, "clk_uart7", UART_GROUP_34567, 1, 4, 0x770, 0x771, 0x772, 0x773),
+};
+
+struct rzn1_priv {
+ struct clk_onecell_data data;
+ spinlock_t lock;
+ void __iomem *reg;
+};
+
+/* register/bit pairs are encoded as an uint16_t */
+static void clk_rdesc_set(
+ struct rzn1_priv *clocks,
+ uint16_t one, unsigned int on)
+{
+ u32 *reg = ((u32 *)clocks->reg) + (one >> 5);
+ u32 val = clk_readl(reg);
+
+ val = (val & ~(1U << (one & 0x1f))) | ((!!on) << (one & 0x1f));
+ clk_writel(val, reg);
+}
+
+static int clk_rdesc_get(
+ struct rzn1_priv *clocks,
+ uint16_t one)
+{
+ u32 *reg = ((u32 *)clocks->reg) + (one >> 5);
+ u32 val = clk_readl(reg);
+
+ return !!(val & (1U << (one & 0x1f)));
+}
+
+/*
+ * This implements the RZ/N1 clock gate 'driver'. We cannot use the system's
+ * clock gate framework as the gates on the RZ/N1 have a special enabling
+ * sequence, therefore we use this little proxy to call into the general
+ * clock gate API in rznr-clock.c that implements what is needed.
+ */
+struct rzn1_clk_gate {
+ struct clk_hw hw;
+ struct rzn1_priv *clocks;
+ u16 index;
+ unsigned read_only : 1;
+
+ struct rzn1_gate gate;
+};
+
+#define to_rzn1_gate(_hw) container_of(_hw, struct rzn1_clk_gate, hw)
+
+static void rzn1_clk_gate_set(
+ struct rzn1_priv *clocks,
+ struct rzn1_gate *g, int on)
+{
+ unsigned long flags;
+
+ WARN_ON(!g->gate);
+
+ spin_lock_irqsave(&clocks->lock, flags);
+ clk_rdesc_set(clocks, g->gate, on);
+ /* De-assert reset */
+ if (g->reset)
+ clk_rdesc_set(clocks, g->reset, 1);
+ spin_unlock_irqrestore(&clocks->lock, flags);
+
+ /* Hardware manual recommends 5us delay after enabling clock & reset */
+ udelay(5);
+
+ /* If the peripheral is memory mapped (i.e. an AXI slave), there is an
+ * associated SLVRDY bit in the System Controller that needs to be set
+ * so that the FlexWAY bus fabric passes on the read/write requests.
+ */
+ if (g->ready || g->midle) {
+ spin_lock_irqsave(&clocks->lock, flags);
+ if (g->ready)
+ clk_rdesc_set(clocks, g->ready, on);
+ /* Clear 'Master Idle Request' bit */
+ if (g->midle)
+ clk_rdesc_set(clocks, g->midle, !on);
+ spin_unlock_irqrestore(&clocks->lock, flags);
+ }
+ /* Note: We don't wait for FlexWAY Socket Connection signal */
+}
+
+static int rzn1_clk_gate_enable(struct clk_hw *hw)
+{
+ struct rzn1_clk_gate *g = to_rzn1_gate(hw);
+
+ rzn1_clk_gate_set(g->clocks, &g->gate, 1);
+ return 0;
+}
+
+static void rzn1_clk_gate_disable(struct clk_hw *hw)
+{
+ struct rzn1_clk_gate *g = to_rzn1_gate(hw);
+
+ if (!g->read_only)
+ rzn1_clk_gate_set(g->clocks, &g->gate, 0);
+ else
+ pr_debug("%s %s: disallowed\n", __func__,
+ __clk_get_name(hw->clk));
+}
+
+static int rzn1_clk_gate_is_enabled(struct clk_hw *hw)
+{
+ struct rzn1_clk_gate *g = to_rzn1_gate(hw);
+
+ return clk_rdesc_get(g->clocks, g->gate.gate);
+}
+
+static const struct clk_ops rzn1_clk_gate_ops = {
+ .enable = rzn1_clk_gate_enable,
+ .disable = rzn1_clk_gate_disable,
+ .is_enabled = rzn1_clk_gate_is_enabled,
+};
+
+static struct clk *rzn1_register_gate(
+ struct rzn1_priv *clocks,
+ const char *parent_name,
+ const struct rzn1_clkdesc *desc)
+{
+ struct clk *clk;
+ struct rzn1_clk_gate *g;
+ struct clk_init_data init;
+
+ g = kzalloc(sizeof(struct rzn1_clk_gate), GFP_KERNEL);
+ if (!g)
+ return NULL;
+
+ init.name = desc->name;
+ init.ops = &rzn1_clk_gate_ops;
+ init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+
+ g->clocks = clocks;
+ g->index = desc->index;
+ g->gate = desc->gate;
+ g->hw.init = &init;
+ g->read_only = 0;
+
+ clk = clk_register(NULL, &g->hw);
+ if (IS_ERR(clk)) {
+ kfree(g);
+ return NULL;
+ }
+ /*
+ * important here, some clocks are already in use by the CM3, we
+ * have to assume they are not Linux's to play with and try to disable
+ * at the end of the boot!
+ * Therefore we increase the clock usage count by arbitrarily enabling
+ * the clock, allowing it to stay untouched at the end of the boot.
+ */
+ g->read_only = rzn1_clk_gate_is_enabled(&g->hw);
+ if (g->read_only)
+ pr_debug("%s was enabled, making read-only\n", desc->name);
+ return clk;
+}
+
+struct rzn1_clk_div {
+ struct clk_hw hw;
+ struct rzn1_priv *clocks;
+ u16 index;
+ u16 reg;
+ u16 min, max;
+ uint8_t table_size;
+ u16 table[8]; /* we know there are no more than 8 */
+};
+
+#define to_rzn1_divider(_hw) container_of(_hw, struct rzn1_clk_div, hw)
+
+static unsigned long rzn1_divider_recalc_rate(
+ struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct rzn1_clk_div *clk = to_rzn1_divider(hw);
+ u32 *reg = ((u32 *)clk->clocks->reg) + clk->reg;
+ long div = clk_readl(reg);
+
+ if (div < clk->min)
+ div = clk->min;
+ else if (div > clk->max)
+ div = clk->max;
+ return DIV_ROUND_UP(parent_rate, div);
+}
+
+/*
+ * Attempts to find a value that is in range of min,max,
+ * and if a table of set dividers was specified for this
+ * register, try to find the fixed divider that is the closest
+ * to the target frequency
+ */
+static long rzn1_divider_clamp_div(
+ struct rzn1_clk_div *clk,
+ unsigned long rate, unsigned long prate)
+{
+ /* + 1 to cope with rates that have the remainder dropped */
+ long div = DIV_ROUND_UP(prate, rate + 1);
+ int i;
+
+ if (div <= clk->min)
+ return clk->min;
+ if (div >= clk->max)
+ return clk->max;
+
+ for (i = 0; clk->table_size && i < clk->table_size - 1; i++) {
+ if (div >= clk->table[i] && div <= clk->table[i+1]) {
+ unsigned long m = rate -
+ DIV_ROUND_UP(prate, clk->table[i]);
+ unsigned long p =
+ DIV_ROUND_UP(prate, clk->table[i + 1]) -
+ rate;
+ /*
+ * select the divider that generates
+ * the value closest to the ideal frequency
+ */
+ div = p >= m ? clk->table[i] : clk->table[i + 1];
+ return div;
+ }
+ }
+ return div;
+}
+
+static long rzn1_divider_round_rate(
+ struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct rzn1_clk_div *clk = to_rzn1_divider(hw);
+ long div = DIV_ROUND_UP(*prate, rate);
+
+ pr_devel("%s %pC %ld (prate %ld) (wanted div %ld)\n", __func__,
+ hw->clk, rate, *prate, div);
+ pr_devel(" min %d (%ld) max %d (%ld)\n",
+ clk->min, DIV_ROUND_UP(*prate, clk->min),
+ clk->max, DIV_ROUND_UP(*prate, clk->max));
+
+ div = rzn1_divider_clamp_div(clk, rate, *prate);
+ /*
+ * this is a hack. Currently the serial driver asks for a clock rate
+ * that is 16 times the baud rate -- and that is wildly outside the
+ * range of the UART divider, somehow there is no provision for that
+ * case of 'let the divider as is if outside range'.
+ * The serial driver *shouldn't* play with these clocks anyway, there's
+ * several uarts attached to this divider, and changing this impacts
+ * everyone.
+ */
+ if (clk->index == RZN1_DIV_UART) {
+ pr_devel("%s div uart hack!\n", __func__);
+ return clk_get_rate(hw->clk);
+ }
+ pr_devel("%s %pC %ld / %ld = %ld\n", __func__, hw->clk,
+ *prate, div, DIV_ROUND_UP(*prate, div));
+ return DIV_ROUND_UP(*prate, div);
+}
+
+static int rzn1_divider_set_rate(
+ struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct rzn1_clk_div *clk = to_rzn1_divider(hw);
+ /* + 1 to cope with rates that have the remainder dropped */
+ u32 div = DIV_ROUND_UP(parent_rate, rate + 1);
+ u32 *reg = ((u32 *)clk->clocks->reg) + clk->reg;
+
+ pr_devel("%s %pC rate %ld parent %ld div %d\n", __func__, hw->clk,
+ rate, parent_rate, div);
+
+ /*
+ * Need to write the bit 31 with the divider value to
+ * latch it. Technically we should wait until it has been
+ * cleared too.
+ * TODO: Find whether this callback is sleepable, in case
+ * the hardware /does/ require some sort of spinloop here.
+ */
+ clk_writel(div | (1U << 31), reg);
+
+ return 0;
+}
+
+static const struct clk_ops rzn1_clk_div_ops = {
+ .recalc_rate = rzn1_divider_recalc_rate,
+ .round_rate = rzn1_divider_round_rate,
+ .set_rate = rzn1_divider_set_rate,
+};
+
+static struct clk *rzn1_register_divider(
+ struct rzn1_priv *clocks,
+ const char *parent_name,
+ const struct rzn1_clkdesc *desc)
+{
+ struct rzn1_clk_div *div;
+ struct clk *clk;
+ struct clk_init_data init;
+ int i;
+
+ if (desc->index == RZN1_CLKOUT_D1OR2) {
+ /*
+ * TODO: handle bizare case of the divider that is set by an
+ * external pin, for the DDR2/3 switch
+ */
+ }
+
+ div = kzalloc(sizeof(struct rzn1_clk_div), GFP_KERNEL);
+ if (!div)
+ return NULL;
+
+ init.name = desc->name;
+ init.ops = &rzn1_clk_div_ops;
+ init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
+ init.parent_names = parent_name ? &parent_name : NULL;
+ init.num_parents = parent_name ? 1 : 0;
+
+ div->clocks = clocks;
+ div->index = desc->index;
+ div->reg = desc->reg;
+ div->hw.init = &init;
+ div->min = desc->div_min;
+ div->max = desc->div_max;
+ /* populate (optional) divider table fixed values */
+ for (i = 0; i < ARRAY_SIZE(div->table) &&
+ i < ARRAY_SIZE(desc->div_table) &&
+ desc->div_table[i]; i++) {
+ div->table[div->table_size++] = desc->div_table[i];
+ }
+
+ clk = clk_register(NULL, &div->hw);
+ if (IS_ERR(clk)) {
+ kfree(div);
+ return NULL;
+ }
+ return clk;
+}
+
+/*
+ * This clock provider handles the case of the RZN1 where you have peripherals
+ * that have two potential clock source and two gates, one for each of the
+ * clock source - the used clock source (for all sub clocks) is selected by a
+ * single bit.
+ * That single bit affects all sub-clocks, and therefore needs to change the
+ * active gate (and turn the others off) and force a recalculation of the rates.
+ *
+ * This implements two clock providers, one 'bitselect' that
+ * handles the switch between both parents, and another 'dualgate'
+ * that knows which gate to poke at, depending on the parent's bit position.
+ */
+struct rzn1_clk_bitsel {
+ struct clk_hw hw;
+ struct rzn1_priv *clocks;
+ u16 index;
+ u16 selector; /* selector register + bit */
+};
+
+#define to_clk_bitselect(_hw) container_of(_hw, struct rzn1_clk_bitsel, hw)
+
+static u8 rzn1_clk_mux_get_parent(struct clk_hw *hw)
+{
+ struct rzn1_clk_bitsel *set = to_clk_bitselect(hw);
+
+ return clk_rdesc_get(set->clocks, set->selector);
+}
+
+static int rzn1_clk_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct rzn1_clk_bitsel *set = to_clk_bitselect(hw);
+
+ /* a single bit in the register selects one of two parent clocks */
+ clk_rdesc_set(set->clocks, set->selector, !!index);
+
+ return 0;
+}
+
+static const struct clk_ops clk_bitselect_ops = {
+ .get_parent = rzn1_clk_mux_get_parent,
+ .set_parent = rzn1_clk_mux_set_parent,
+};
+
+static struct clk *rzn1_register_bitsel(
+ struct rzn1_priv *clocks,
+ const char *parent_name,
+ const struct rzn1_clkdesc *desc)
+{
+ struct clk *clk;
+ struct rzn1_clk_bitsel *g;
+ struct clk_init_data init;
+ const char *names[2];
+
+ /* allocate the gate */
+ g = kzalloc(sizeof(struct rzn1_clk_bitsel), GFP_KERNEL);
+ if (!g)
+ return NULL;
+
+ names[0] = parent_name;
+ names[1] = "clk_pll_usb";
+
+ init.name = desc->name;
+ init.ops = &clk_bitselect_ops;
+ init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
+ init.parent_names = names;
+ init.num_parents = 2;
+
+ g->clocks = clocks;
+ g->index = desc->index;
+ g->selector = desc->dual.sel;
+ g->hw.init = &init;
+
+ clk = clk_register(NULL, &g->hw);
+ if (IS_ERR(clk)) {
+ kfree(g);
+ return NULL;
+ }
+ return clk;
+}
+
+struct rzn1_clk_dualgate {
+ struct clk_hw hw;
+ struct rzn1_priv *clocks;
+ u16 index;
+ u16 selector; /* selector register + bit */
+ struct rzn1_gate gate[2];
+};
+#define to_clk_dualgate(_hw) container_of(_hw, struct rzn1_clk_dualgate, hw)
+
+static int rzn1_clk_dualgate_setenable(struct rzn1_clk_dualgate *g, int enable)
+{
+ uint8_t sel_bit = clk_rdesc_get(g->clocks, g->selector);
+
+ /* we always turn off the 'other' gate, regardless */
+ rzn1_clk_gate_set(g->clocks, &g->gate[!sel_bit], 0);
+ rzn1_clk_gate_set(g->clocks, &g->gate[sel_bit], enable);
+
+ return 0;
+}
+
+static int rzn1_clk_dualgate_enable(struct clk_hw *hw)
+{
+ struct rzn1_clk_dualgate *gate = to_clk_dualgate(hw);
+
+ rzn1_clk_dualgate_setenable(gate, 1);
+
+ return 0;
+}
+
+static void rzn1_clk_dualgate_disable(struct clk_hw *hw)
+{
+ struct rzn1_clk_dualgate *gate = to_clk_dualgate(hw);
+
+ rzn1_clk_dualgate_setenable(gate, 0);
+}
+
+static int rzn1_clk_dualgate_is_enabled(struct clk_hw *hw)
+{
+ struct rzn1_clk_dualgate *g = to_clk_dualgate(hw);
+ uint8_t sel_bit = clk_rdesc_get(g->clocks, g->selector);
+
+ return clk_rdesc_get(g->clocks, g->gate[sel_bit].gate);
+}
+
+static const struct clk_ops rzn1_clk_dualgate_ops = {
+ .enable = rzn1_clk_dualgate_enable,
+ .disable = rzn1_clk_dualgate_disable,
+ .is_enabled = rzn1_clk_dualgate_is_enabled,
+};
+
+static struct clk *rzn1_register_dualgate(
+ struct rzn1_priv *clocks,
+ const char *parent_name,
+ const struct rzn1_clkdesc *desc,
+ uint16_t sel)
+{
+ struct rzn1_clk_dualgate *g;
+ struct clk *clk;
+ struct clk_init_data init;
+
+ /* allocate the gate */
+ g = kzalloc(sizeof(struct rzn1_clk_dualgate), GFP_KERNEL);
+ if (!g)
+ return NULL;
+ g->clocks = clocks;
+ g->index = desc->index;
+ g->selector = sel;
+ g->gate[0].gate = desc->dual.g1;
+ g->gate[0].reset = desc->dual.r1;
+ g->gate[1].gate = desc->dual.g2;
+ g->gate[1].reset = desc->dual.r2;
+
+ init.name = desc->name;
+ init.ops = &rzn1_clk_dualgate_ops;
+ init.flags = CLK_IS_BASIC | CLK_SET_RATE_PARENT;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ g->hw.init = &init;
+
+ clk = clk_register(NULL, &g->hw);
+ if (IS_ERR(clk)) {
+ kfree(g);
+ return NULL;
+ }
+ return clk;
+}
+
+static void __init rzn1_clocks_init(struct device_node *np)
+{
+ struct rzn1_priv *clocks;
+ struct clk **clks;
+ unsigned int i;
+ uint16_t uart_group_sel[2];
+
+ clocks = kzalloc(sizeof(*clocks), GFP_KERNEL);
+ clks = kzalloc(RZN1_CLOCK_COUNT * sizeof(struct clk *), GFP_KERNEL);
+ if (clocks == NULL || clks == NULL) {
+ /* We're leaking memory on purpose, there's no point in cleaning
+ * up as the system won't boot anyway.
+ */
+ return;
+ }
+ spin_lock_init(&clocks->lock);
+
+ clocks->data.clks = clks;
+ clocks->data.clk_num = RZN1_CLOCK_COUNT;
+
+ clocks->reg = of_iomap(np, 0);
+ if (WARN_ON(clocks->reg == NULL))
+ return;
+ for (i = 0; i < ARRAY_SIZE(rzn1_clocks); ++i) {
+ const struct rzn1_clkdesc *d = &rzn1_clocks[i];
+ const char *parent_name = d->source ?
+ __clk_get_name(clocks->data.clks[d->source - 1]) : NULL;
+ struct clk *clk = NULL;
+
+ switch (d->type) {
+ case K_FC:
+ clk = clk_register_fixed_rate(NULL, d->name,
+ parent_name, 0, d->frequency);
+ break;
+ case K_FFC:
+ clk = clk_register_fixed_factor(NULL, d->name,
+ parent_name, 0, 1, d->div);
+ break;
+ case K_GATE:
+ clk = rzn1_register_gate(clocks, parent_name, d);
+ break;
+ case K_DIV:
+ clk = rzn1_register_divider(clocks, parent_name, d);
+ break;
+ case K_BITSEL:
+ /* keep that selector register around */
+ uart_group_sel[d->dual.group] = d->dual.sel;
+ clk = rzn1_register_bitsel(clocks, parent_name, d);
+ break;
+ case K_DUALGATE:
+ clk = rzn1_register_dualgate(clocks, parent_name, d,
+ uart_group_sel[d->dual.group]);
+ break;
+ }
+ clocks->data.clks[d->index] = clk;
+ }
+ of_clk_add_provider(np, of_clk_src_onecell_get, &clocks->data);
+}
+CLK_OF_DECLARE(rzn1_clks, "renesas,rzn1-clocks",
+ rzn1_clocks_init);
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v2 2/2] cpufreq: qcom-fw: Add support for QCOM cpufreq FW driver
From: Taniya Das @ 2018-05-22 10:43 UTC (permalink / raw)
To: skannan, Viresh Kumar
Cc: Rafael J. Wysocki, linux-kernel, linux-pm, Stephen Boyd, robh,
Rajendra Nayak, Amit Nischal, devicetree, amit.kucheria
In-Reply-To: <0fccdc1880c912102548a85008482fa0@codeaurora.org>
Hello Viresh,
Thanks for your comments.
On 5/22/2018 12:36 AM, skannan@codeaurora.org wrote:
> On 2018-05-21 02:01, Viresh Kumar wrote:
>> On 19-05-18, 23:04, Taniya Das wrote:
>>> The CPUfreq FW present in some QCOM chipsets offloads the steps
>>> necessary
>>> for changing the frequency of CPUs. The driver implements the cpufreq
>>> driver interface for this firmware.
>>>
>>> Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
>>> Signed-off-by: Taniya Das <tdas@codeaurora.org>
>>> ---
>>> drivers/cpufreq/Kconfig.arm | 9 ++
>>> drivers/cpufreq/Makefile | 1 +
>>> drivers/cpufreq/qcom-cpufreq-fw.c | 317
>>> ++++++++++++++++++++++++++++++++++++++
>>> 3 files changed, 327 insertions(+)
>>> create mode 100644 drivers/cpufreq/qcom-cpufreq-fw.c
>>>
>>> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
>>> index 96b35b8..571f6b4 100644
>>> --- a/drivers/cpufreq/Kconfig.arm
>>> +++ b/drivers/cpufreq/Kconfig.arm
>>> @@ -301,3 +301,12 @@ config ARM_PXA2xx_CPUFREQ
>>> This add the CPUFreq driver support for Intel PXA2xx SOCs.
>>>
>>> If in doubt, say N.
>>> +
>>> +config ARM_QCOM_CPUFREQ_FW
>>> + bool "QCOM CPUFreq FW driver"
>>
>> During last review I didn't say that this driver shouldn't be a
>> module, but that you need to fix things to make it a module. I am fine
>> though if you don't want this to be a module ever.
>>
>>> + help
>>> + Support for the CPUFreq FW driver.
>>> + The CPUfreq FW preset in some QCOM chipsets offloads the steps
>>> + necessary for changing the frequency of CPUs. The driver
>>> + implements the cpufreq driver interface for this firmware.
>>> + Say Y if you want to support CPUFreq FW.
>>> diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
>>> index 8d24ade..a3edbce 100644
>>> --- a/drivers/cpufreq/Makefile
>>> +++ b/drivers/cpufreq/Makefile
>>> @@ -85,6 +85,7 @@ obj-$(CONFIG_ARM_TEGRA124_CPUFREQ) +=
>>> tegra124-cpufreq.o
>>> obj-$(CONFIG_ARM_TEGRA186_CPUFREQ) += tegra186-cpufreq.o
>>> obj-$(CONFIG_ARM_TI_CPUFREQ) += ti-cpufreq.o
>>> obj-$(CONFIG_ARM_VEXPRESS_SPC_CPUFREQ) += vexpress-spc-cpufreq.o
>>> +obj-$(CONFIG_ARM_QCOM_CPUFREQ_FW) += qcom-cpufreq-fw.o
>>>
>>>
>>>
>>> ##################################################################################
>>>
>>> diff --git a/drivers/cpufreq/qcom-cpufreq-fw.c
>>> b/drivers/cpufreq/qcom-cpufreq-fw.c
>>> new file mode 100644
>>> index 0000000..0e66de0
>>> --- /dev/null
>>> +++ b/drivers/cpufreq/qcom-cpufreq-fw.c
>>> @@ -0,0 +1,317 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
>>> + */
>>> +
>>> +#include <linux/cpufreq.h>
>>> +#include <linux/init.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of_address.h>
>>> +#include <linux/of_platform.h>
>>> +
>>> +#define INIT_RATE 300000000UL
>>> +#define XO_RATE 19200000UL
>>> +#define LUT_MAX_ENTRIES 40U
>>> +#define CORE_COUNT_VAL(val) ((val & GENMASK(18, 16)) >> 16)
>>> +#define LUT_ROW_SIZE 32
>>> +
>>> +struct cpufreq_qcom {
>>> + struct cpufreq_frequency_table *table;
>>> + struct device *dev;
>>> + void __iomem *perf_base;
>>> + void __iomem *lut_base;
>>> + cpumask_t related_cpus;
>>> + unsigned int max_cores;
>>> +};
>>> +
>>> +static struct cpufreq_qcom *qcom_freq_domain_map[NR_CPUS];
>>> +
>>> +static int
>>> +qcom_cpufreq_fw_target_index(struct cpufreq_policy *policy, unsigned
>>> int index)
>>> +{
>>> + struct cpufreq_qcom *c = policy->driver_data;
>>> +
>>> + if (index >= LUT_MAX_ENTRIES) {
>>> + dev_err(c->dev,
>>> + "Passing an index (%u) that's greater than max (%d)\n",
>>> + index, LUT_MAX_ENTRIES - 1);
>>> + return -EINVAL;
>>> + }
>>
>> This is never going to happen unless there is a bug in cpufreq core.
>> You are allocating only 40 entries for the cpufreq table and this will
>> always be 0-39. None of the other drivers is checking this I believe
>> and neither should you. This is the only routine which will get call
>> very frequently and we better not add unnecessary stuff here.
>>
Yes, I would remove this in the next series.
>>> + writel_relaxed(index, c->perf_base);
>>> +
>>> + /* Make sure the write goes through before proceeding */
>>> + mb();
>>
>> Btw what happens right after this is done ? Are we guaranteed that the
>> frequency is updated in the hardware after this ? What about enabling
>> fast-switch for your platform ? Look at drivers/cpufreq/scmi-cpufreq.c
>> to see how that is done.
>
> Yeah, I don't think this is needed really.
>
Just want to make sure it doesn't really sit in the write buffer before
return.
>>
>>> + return 0;
>>> +}
>>> +
>>> +static unsigned int qcom_cpufreq_fw_get(unsigned int cpu)
>>> +{
>>> + struct cpufreq_qcom *c;
>>> + unsigned int index;
>>> +
>>> + c = qcom_freq_domain_map[cpu];
>>> + if (!c)
>>> + return -ENODEV;
>>
>> Return 0 on error here.
>>
Would update this in the next patch.
>>> +
>>> + index = readl_relaxed(c->perf_base);
>>> + index = min(index, LUT_MAX_ENTRIES - 1);
>>
>> Will the hardware ever read a value over 39 here ?
>
> The register could be initialized to whatever before the kernel is
> brought up. Don't want to depend on it being correct to avoid out of
> bounds access that could leak data.
>
>
>>> +
>>> + return c->table[index].frequency;
>>> +}
>>> +
>>> +static int qcom_cpufreq_fw_cpu_init(struct cpufreq_policy *policy)
>>> +{
>>> + struct cpufreq_qcom *c;
>>> +
>>> + c = qcom_freq_domain_map[policy->cpu];
>>> + if (!c) {
>>> + pr_err("No scaling support for CPU%d\n", policy->cpu);
>>> + return -ENODEV;
>>> + }
>>> +
>>> + cpumask_copy(policy->cpus, &c->related_cpus);
>>> + policy->freq_table = c->table;
>>> + policy->driver_data = c;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static struct freq_attr *qcom_cpufreq_fw_attr[] = {
>>> + &cpufreq_freq_attr_scaling_available_freqs,
>>> + &cpufreq_freq_attr_scaling_boost_freqs,
>>> + NULL
>>> +};
>>> +
>>> +static struct cpufreq_driver cpufreq_qcom_fw_driver = {
>>> + .flags = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK |
>>> + CPUFREQ_HAVE_GOVERNOR_PER_POLICY,
>>> + .verify = cpufreq_generic_frequency_table_verify,
>>> + .target_index = qcom_cpufreq_fw_target_index,
>>> + .get = qcom_cpufreq_fw_get,
>>> + .init = qcom_cpufreq_fw_cpu_init,
>>> + .name = "qcom-cpufreq-fw",
>>> + .attr = qcom_cpufreq_fw_attr,
>>> + .boost_enabled = true,
>>> +};
>>> +
>>> +static int qcom_read_lut(struct platform_device *pdev,
>>> + struct cpufreq_qcom *c)
>>> +{
>>> + struct device *dev = &pdev->dev;
>>> + u32 data, src, lval, i, core_count, prev_cc;
>>> +
>>> + c->table = devm_kcalloc(dev, LUT_MAX_ENTRIES + 1,
>>> + sizeof(*c->table), GFP_KERNEL);
>>> + if (!c->table)
>>> + return -ENOMEM;
>>> +
>>> + for (i = 0; i < LUT_MAX_ENTRIES; i++) {
>>> + data = readl_relaxed(c->lut_base + i * LUT_ROW_SIZE);
>>> + src = ((data & GENMASK(31, 30)) >> 30);
>>> + lval = (data & GENMASK(7, 0));
>>> + core_count = CORE_COUNT_VAL(data);
>>> +
>>> + if (!src)
>>> + c->table[i].frequency = INIT_RATE / 1000;
>>> + else
>>> + c->table[i].frequency = XO_RATE * lval / 1000;
>>> +
>>> + c->table[i].driver_data = c->table[i].frequency;
>>
>> Why do you need to use driver_data here? Why can't you simple use
>> frequency field in the below conditional expressions ?
>>
The frequency field would be marked INVALID in case the core count does
not match and the frequency data would be lost.
>>> +
>>> + dev_dbg(dev, "index=%d freq=%d, core_count %d\n",
>>> + i, c->table[i].frequency, core_count);
>>> +
>>> + if (core_count != c->max_cores)
>>> + c->table[i].frequency = CPUFREQ_ENTRY_INVALID;
>>> +
>>> + /*
>>> + * Two of the same frequencies with the same core counts means
>>> + * end of table.
>>> + */
>>> + if (i > 0 && c->table[i - 1].driver_data ==
>>> + c->table[i].driver_data && prev_cc == core_count) {
>>> + struct cpufreq_frequency_table *prev = &c->table[i - 1];
>>> +
>>> + if (prev->frequency == CPUFREQ_ENTRY_INVALID) {
>>
>> There can only be a single boost frequency at max ?
>
> As of now, yes. If that changes, we'll change this code later.
>
>>> + prev->flags = CPUFREQ_BOOST_FREQ;
>>> + prev->frequency = prev->driver_data;
>>
>> Okay you are using driver_data as a local variable to keep this value
>> safe which you might have overwritten. Maybe use a simple variable
>> prev_freq for this. It would be much more readable in that case and
>> you wouldn't end up abusing the driver_data field.
>>
Please correct me, currently the driver_data is not used by cpufreq core
and that was the reason to use it. In case you still think it is not a
good way to handle it, I would try to handle it differently.
>>> + }
>>> +
>>> + break;
>>> + }
>>> + prev_cc = core_count;
>>> + }
>>> + c->table[i].frequency = CPUFREQ_TABLE_END;
>>
>> Wouldn't you end up writing on c->table[40].frequency here if there
>> are 40 frequency value present ?
>
> Yeah, the loop condition needs to be fixed.
>
The table allocation is done for 'LUT_MAX_ENTRIES + 1'.
Yes in case we have all [0-39] (i.e 40 entries) read from the hardware,
would store the same and mark the 40th index as table end. Please
correct if I missed something in your comment.
> -Saravana
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation.
--
^ permalink raw reply
* Re: [PATCH v6 9/9] iio: counter: Remove IIO counter subdirectory
From: Jonathan Cameron @ 2018-05-22 10:44 UTC (permalink / raw)
To: William Breathitt Gray
Cc: Jonathan Cameron, benjamin.gaignard, fabrice.gasnier, linux-iio,
linux-kernel, devicetree, linux-arm-kernel
In-Reply-To: <20180521135828.GD5723@sophia>
On Mon, 21 May 2018 09:58:28 -0400
William Breathitt Gray <vilhelm.gray@gmail.com> wrote:
> On Sun, May 20, 2018 at 04:53:02PM +0100, Jonathan Cameron wrote:
> >On Wed, 16 May 2018 13:52:39 -0400
> >William Breathitt Gray <vilhelm.gray@gmail.com> wrote:
> >
> >> This patch removes the IIO counter subdirectory which is now superceded
> >> by the Counter subsystem. Deprecation warnings are added to the
> >> documentation of the relevant IIO counter sysfs attributes.
> >>
> >> Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
> >
> >Please drop the directory when it becomes empty rather than in a later
> >patch. IIRC there are some issues with empty Makefiles that will
> >make building inbetween tricky.
> >
> >For the deprecated markings.
> >
> >Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> I'll have the directory removal occur with the removal of the last
> module then when the directory becomes empty.
>
> Regarding the deprecation markings, should I select a specific kernel
> version to date the removal of these attributes, or leave the future
> date open as this patch is now?
Leave it open. The ultimate test is whether it is actually enough of a burden
to make us want to clean up the deprecated interface.
This burden may be that it is a pain to implement something new, or to test
or to maintain the code (or something I haven't thought of).
If it's not it may stay there for ever.
Jonathan
>
> William Breathitt Gray
>
> >
> >> ---
> >> Documentation/ABI/testing/sysfs-bus-iio | 8 ++++++++
> >> .../ABI/testing/sysfs-bus-iio-counter-104-quad-8 | 16 ++++++++++++++++
> >> drivers/iio/Kconfig | 1 -
> >> drivers/iio/Makefile | 1 -
> >> drivers/iio/counter/Kconfig | 8 --------
> >> drivers/iio/counter/Makefile | 5 -----
> >> 6 files changed, 24 insertions(+), 15 deletions(-)
> >> delete mode 100644 drivers/iio/counter/Kconfig
> >> delete mode 100644 drivers/iio/counter/Makefile
> >>
> >> diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/testing/sysfs-bus-iio
> >> index 731146c3b138..6115d97b075e 100644
> >> --- a/Documentation/ABI/testing/sysfs-bus-iio
> >> +++ b/Documentation/ABI/testing/sysfs-bus-iio
> >> @@ -1637,6 +1637,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_countY_raw
> >> KernelVersion: 4.10
> >> Contact: linux-iio@vger.kernel.org
> >> Description:
> >> + This interface is deprecated; please use the Counter subsystem.
> >> +
> >> Raw counter device counts from channel Y. For quadrature
> >> counters, multiplication by an available [Y]_scale results in
> >> the counts of a single quadrature signal phase from channel Y.
> >> @@ -1645,6 +1647,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_indexY_raw
> >> KernelVersion: 4.10
> >> Contact: linux-iio@vger.kernel.org
> >> Description:
> >> + This interface is deprecated; please use the Counter subsystem.
> >> +
> >> Raw counter device index value from channel Y. This attribute
> >> provides an absolute positional reference (e.g. a pulse once per
> >> revolution) which may be used to home positional systems as
> >> @@ -1654,6 +1658,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_count_count_direction_available
> >> KernelVersion: 4.12
> >> Contact: linux-iio@vger.kernel.org
> >> Description:
> >> + This interface is deprecated; please use the Counter subsystem.
> >> +
> >> A list of possible counting directions which are:
> >> - "up" : counter device is increasing.
> >> - "down": counter device is decreasing.
> >> @@ -1662,4 +1668,6 @@ What: /sys/bus/iio/devices/iio:deviceX/in_countY_count_direction
> >> KernelVersion: 4.12
> >> Contact: linux-iio@vger.kernel.org
> >> Description:
> >> + This interface is deprecated; please use the Counter subsystem.
> >> +
> >> Raw counter device counters direction for channel Y.
> >> diff --git a/Documentation/ABI/testing/sysfs-bus-iio-counter-104-quad-8 b/Documentation/ABI/testing/sysfs-bus-iio-counter-104-quad-8
> >> index 7fac2c268d9a..bac3d0d48b7b 100644
> >> --- a/Documentation/ABI/testing/sysfs-bus-iio-counter-104-quad-8
> >> +++ b/Documentation/ABI/testing/sysfs-bus-iio-counter-104-quad-8
> >> @@ -6,6 +6,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_index_synchronous_mode_available
> >> KernelVersion: 4.10
> >> Contact: linux-iio@vger.kernel.org
> >> Description:
> >> + This interface is deprecated; please use the Counter subsystem.
> >> +
> >> Discrete set of available values for the respective counter
> >> configuration are listed in this file.
> >>
> >> @@ -13,6 +15,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_countY_count_mode
> >> KernelVersion: 4.10
> >> Contact: linux-iio@vger.kernel.org
> >> Description:
> >> + This interface is deprecated; please use the Counter subsystem.
> >> +
> >> Count mode for channel Y. Four count modes are available:
> >> normal, range limit, non-recycle, and modulo-n. The preset value
> >> for channel Y is used by the count mode where required.
> >> @@ -47,6 +51,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_countY_noise_error
> >> KernelVersion: 4.10
> >> Contact: linux-iio@vger.kernel.org
> >> Description:
> >> + This interface is deprecated; please use the Counter subsystem.
> >> +
> >> Read-only attribute that indicates whether excessive noise is
> >> present at the channel Y count inputs in quadrature clock mode;
> >> irrelevant in non-quadrature clock mode.
> >> @@ -55,6 +61,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_countY_preset
> >> KernelVersion: 4.10
> >> Contact: linux-iio@vger.kernel.org
> >> Description:
> >> + This interface is deprecated; please use the Counter subsystem.
> >> +
> >> If the counter device supports preset registers, the preset
> >> count for channel Y is provided by this attribute.
> >>
> >> @@ -62,6 +70,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_countY_quadrature_mode
> >> KernelVersion: 4.10
> >> Contact: linux-iio@vger.kernel.org
> >> Description:
> >> + This interface is deprecated; please use the Counter subsystem.
> >> +
> >> Configure channel Y counter for non-quadrature or quadrature
> >> clock mode. Selecting non-quadrature clock mode will disable
> >> synchronous load mode. In quadrature clock mode, the channel Y
> >> @@ -83,6 +93,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_countY_set_to_preset_on_index
> >> KernelVersion: 4.10
> >> Contact: linux-iio@vger.kernel.org
> >> Description:
> >> + This interface is deprecated; please use the Counter subsystem.
> >> +
> >> Whether to set channel Y counter with channel Y preset value
> >> when channel Y index input is active, or continuously count.
> >> Valid attribute values are boolean.
> >> @@ -91,6 +103,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_indexY_index_polarity
> >> KernelVersion: 4.10
> >> Contact: linux-iio@vger.kernel.org
> >> Description:
> >> + This interface is deprecated; please use the Counter subsystem.
> >> +
> >> Active level of channel Y index input; irrelevant in
> >> non-synchronous load mode.
> >>
> >> @@ -98,6 +112,8 @@ What: /sys/bus/iio/devices/iio:deviceX/in_indexY_synchronous_mode
> >> KernelVersion: 4.10
> >> Contact: linux-iio@vger.kernel.org
> >> Description:
> >> + This interface is deprecated; please use the Counter subsystem.
> >> +
> >> Configure channel Y counter for non-synchronous or synchronous
> >> load mode. Synchronous load mode cannot be selected in
> >> non-quadrature clock mode.
> >> diff --git a/drivers/iio/Kconfig b/drivers/iio/Kconfig
> >> index d69e85a8bdc3..1152efad91a1 100644
> >> --- a/drivers/iio/Kconfig
> >> +++ b/drivers/iio/Kconfig
> >> @@ -74,7 +74,6 @@ source "drivers/iio/afe/Kconfig"
> >> source "drivers/iio/amplifiers/Kconfig"
> >> source "drivers/iio/chemical/Kconfig"
> >> source "drivers/iio/common/Kconfig"
> >> -source "drivers/iio/counter/Kconfig"
> >> source "drivers/iio/dac/Kconfig"
> >> source "drivers/iio/dummy/Kconfig"
> >> source "drivers/iio/frequency/Kconfig"
> >> diff --git a/drivers/iio/Makefile b/drivers/iio/Makefile
> >> index d8cba9c229c0..7bdd31f1b88f 100644
> >> --- a/drivers/iio/Makefile
> >> +++ b/drivers/iio/Makefile
> >> @@ -20,7 +20,6 @@ obj-y += amplifiers/
> >> obj-y += buffer/
> >> obj-y += chemical/
> >> obj-y += common/
> >> -obj-y += counter/
> >> obj-y += dac/
> >> obj-y += dummy/
> >> obj-y += gyro/
> >> diff --git a/drivers/iio/counter/Kconfig b/drivers/iio/counter/Kconfig
> >> deleted file mode 100644
> >> index 95a7a0df6cac..000000000000
> >> --- a/drivers/iio/counter/Kconfig
> >> +++ /dev/null
> >> @@ -1,8 +0,0 @@
> >> -#
> >> -# Counter devices
> >> -#
> >> -# When adding new entries keep the list in alphabetical order
> >> -
> >> -menu "Counters"
> >> -
> >> -endmenu
> >> diff --git a/drivers/iio/counter/Makefile b/drivers/iio/counter/Makefile
> >> deleted file mode 100644
> >> index 8fd3d954775a..000000000000
> >> --- a/drivers/iio/counter/Makefile
> >> +++ /dev/null
> >> @@ -1,5 +0,0 @@
> >> -#
> >> -# Makefile for IIO counter devices
> >> -#
> >> -
> >> -# When adding new entries keep the list in alphabetical order
> >
> --
> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Applied "ASoC: codec: realtek: Make the node name generic" to the asoc tree
From: Mark Brown @ 2018-05-22 10:58 UTC (permalink / raw)
To: Fabio Estevam; +Cc: devicetree, alsa-devel, broonie, robh+dt
In-Reply-To: <1526829768-15001-1-git-send-email-festevam@gmail.com>
The patch
ASoC: codec: realtek: Make the node name generic
has been applied to the asoc tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
>From 520a76f855e570c11fd042dd2ab4712ce33fb3a0 Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Sun, 20 May 2018 12:22:48 -0300
Subject: [PATCH] ASoC: codec: realtek: Make the node name generic
"The name of a node should be somewhat generic, reflecting the function
of the device and not its precise programming model."
Do as suggested in the bindings examples.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/devicetree/bindings/sound/rt274.txt | 2 +-
Documentation/devicetree/bindings/sound/rt5514.txt | 2 +-
Documentation/devicetree/bindings/sound/rt5616.txt | 2 +-
Documentation/devicetree/bindings/sound/rt5645.txt | 2 +-
Documentation/devicetree/bindings/sound/rt5651.txt | 2 +-
Documentation/devicetree/bindings/sound/rt5663.txt | 2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/rt274.txt b/Documentation/devicetree/bindings/sound/rt274.txt
index e9a6178c78cf..791a1bd767b9 100644
--- a/Documentation/devicetree/bindings/sound/rt274.txt
+++ b/Documentation/devicetree/bindings/sound/rt274.txt
@@ -26,7 +26,7 @@ Pins on the device (for linking into audio routes) for RT274:
Example:
-codec: rt274@1c {
+rt274: codec@1c {
compatible = "realtek,rt274";
reg = <0x1c>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
diff --git a/Documentation/devicetree/bindings/sound/rt5514.txt b/Documentation/devicetree/bindings/sound/rt5514.txt
index 4f33b0d96afe..b25ed08c7a5a 100644
--- a/Documentation/devicetree/bindings/sound/rt5514.txt
+++ b/Documentation/devicetree/bindings/sound/rt5514.txt
@@ -32,7 +32,7 @@ Pins on the device (for linking into audio routes) for I2C:
Example:
-codec: rt5514@57 {
+rt5514: codec@57 {
compatible = "realtek,rt5514";
reg = <0x57>;
};
diff --git a/Documentation/devicetree/bindings/sound/rt5616.txt b/Documentation/devicetree/bindings/sound/rt5616.txt
index e41085818559..540a4bf252e4 100644
--- a/Documentation/devicetree/bindings/sound/rt5616.txt
+++ b/Documentation/devicetree/bindings/sound/rt5616.txt
@@ -26,7 +26,7 @@ Pins on the device (for linking into audio routes) for RT5616:
Example:
-codec: rt5616@1b {
+rt5616: codec@1b {
compatible = "realtek,rt5616";
reg = <0x1b>;
};
diff --git a/Documentation/devicetree/bindings/sound/rt5645.txt b/Documentation/devicetree/bindings/sound/rt5645.txt
index 7cee1f518f59..a03f9a872a71 100644
--- a/Documentation/devicetree/bindings/sound/rt5645.txt
+++ b/Documentation/devicetree/bindings/sound/rt5645.txt
@@ -69,4 +69,4 @@ codec: rt5650@1a {
realtek,dmic-en = "true";
realtek,en-jd-func = "true";
realtek,jd-mode = <3>;
-};
\ No newline at end of file
+};
diff --git a/Documentation/devicetree/bindings/sound/rt5651.txt b/Documentation/devicetree/bindings/sound/rt5651.txt
index b85221864cec..a41199a5cd79 100644
--- a/Documentation/devicetree/bindings/sound/rt5651.txt
+++ b/Documentation/devicetree/bindings/sound/rt5651.txt
@@ -50,7 +50,7 @@ Pins on the device (for linking into audio routes) for RT5651:
Example:
-codec: rt5651@1a {
+rt5651: codec@1a {
compatible = "realtek,rt5651";
reg = <0x1a>;
realtek,dmic-en = "true";
diff --git a/Documentation/devicetree/bindings/sound/rt5663.txt b/Documentation/devicetree/bindings/sound/rt5663.txt
index 497bcfc58b71..23386446c63d 100644
--- a/Documentation/devicetree/bindings/sound/rt5663.txt
+++ b/Documentation/devicetree/bindings/sound/rt5663.txt
@@ -47,7 +47,7 @@ Pins on the device (for linking into audio routes) for RT5663:
Example:
-codec: rt5663@12 {
+rt5663: codec@12 {
compatible = "realtek,rt5663";
reg = <0x12>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
--
2.17.0
^ permalink raw reply related
* Re: [PATCH] ASoC: codec: wolfson: Make the node name generic
From: Mark Brown @ 2018-05-22 10:58 UTC (permalink / raw)
To: Fabio Estevam; +Cc: Fabio Estevam, devicetree, alsa-devel, robh+dt
In-Reply-To: <1526820821-12106-1-git-send-email-festevam@gmail.com>
[-- Attachment #1.1: Type: text/plain, Size: 397 bytes --]
On Sun, May 20, 2018 at 09:53:41AM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@nxp.com>
>
> According to Devicetree Specification v0.2 document:
>
> "The name of a node should be somewhat generic, reflecting the function
> of the device and not its precise programming model."
>
> Do as suggested in the bindings examples.
Not that this has any real meaning :(
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 0 bytes --]
^ permalink raw reply
* Re: [PATCH V7] ARM: dts: da850-evm: Enable LCD and Backlight
From: Sekhar Nori @ 2018-05-22 10:58 UTC (permalink / raw)
To: Adam Ford, linux-arm-kernel; +Cc: devicetree, khilman
In-Reply-To: <2d52e1f8-d321-4465-fdfa-fd0d718c67cf@ti.com>
On Monday 21 May 2018 08:21 PM, Sekhar Nori wrote:
> On Saturday 19 May 2018 02:03 AM, Adam Ford wrote:
>> When using the board files the LCD works, but not with the DT.
>> This adds enables the original da850-evm to work with the same
>> LCD in device tree mode.
>>
>> The EVM has a gpio for the regulator and a PWM for dimming the
>> backlight. The LCD and the vpif display pins are mutually
>> exclusive, so if using the LCD, do not load the vpif driver.
>>
>> Signed-off-by: Adam Ford <aford173@gmail.com>
>
>> diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
>> index 0e82bb988fde..a76c2ddfd23e 100644
>> --- a/arch/arm/boot/dts/da850-evm.dts
>> +++ b/arch/arm/boot/dts/da850-evm.dts
>> @@ -27,6 +27,60 @@
>> spi0 = &spi1;
>> };
>>
>> + backlight: backlight-pwm {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&ecap2_pins>;
>> + power-supply = <&backlight_lcd>;
>> + compatible = "pwm-backlight";
>> + pwms = <&ecap2 0 50000 0>;
>
> It will be nice to add a comment here: "The PWM here corresponds to
> production hardware. The schematic needs to be 1015171 (15 March 2010),
> Rev A or newer."
>
>> + brightness-levels = <0 10 20 30 40 50 60 70 80 90 99>;
>> + default-brightness-level = <7>;
>> + };
>> +
>> + panel {
>> + compatible = "ti,tilcdc,panel";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&lcd_pins>;
>> + /*
>> + * The vpif and the LCD are mutually exclusive.
>> + * To enable VPIF, change the status below to 'disabled' then
>> + * then change the status of the vpif below to 'okay'
>> + */
>
> This results in checkpatch warning:
>
> [PATCH V7] ARM: dts: da850-evm: Enable LCD and Backlight.eml:153: WARNING: Block comments should align the * on each line
> [PATCH V7] ARM: dts: da850-evm: Enable LCD and Backlight.eml:239: WARNING: Block comments should align the * on each line
>
>> &vpif {
>> pinctrl-names = "default";
>> pinctrl-0 = <&vpif_capture_pins>, <&vpif_display_pins>;
>> - status = "okay";
>> + /*
>> + * The vpif and the LCD are mutually exclusive.
>> + * To enable VPIF, disable the ti,tilcdc,panel then
>> + * changed the status below to 'okay'
>> + */
>> + status = "disabled";
>
> Are you able to see VPIF is disabled after this? Trying your patch, I
> still see VPIF probing[1]. Also, only VPIF display has a conflict with
> LCD, correct (capture should be fine)?
To answer myself, I forgot that VPIF is bit special because it is
registered through pdata-quirks. As such the parent vpif node is used
only for pinmux setting. I do think the platform devices for capture and
display should not be registered if the vpif parent node is disabled in
DT. But thats a subject of another patch.
With that, I fixed up my comments above locally and added this in queue
for v4.19
Thanks,
Sekhar
^ permalink raw reply
* Applied "ASoC: codec: wolfson: Make the node name generic" to the asoc tree
From: Mark Brown @ 2018-05-22 10:58 UTC (permalink / raw)
To: Fabio Estevam; +Cc: devicetree, alsa-devel, broonie, robh+dt
In-Reply-To: <1526820821-12106-1-git-send-email-festevam@gmail.com>
The patch
ASoC: codec: wolfson: Make the node name generic
has been applied to the asoc tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
>From 34f5897c59d19ac1b97fd4030b430ac4658c722c Mon Sep 17 00:00:00 2001
From: Fabio Estevam <fabio.estevam@nxp.com>
Date: Sun, 20 May 2018 09:53:41 -0300
Subject: [PATCH] ASoC: codec: wolfson: Make the node name generic
According to Devicetree Specification v0.2 document:
"The name of a node should be somewhat generic, reflecting the function
of the device and not its precise programming model."
Do as suggested in the bindings examples.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
---
Documentation/devicetree/bindings/sound/wm8510.txt | 2 +-
Documentation/devicetree/bindings/sound/wm8523.txt | 2 +-
Documentation/devicetree/bindings/sound/wm8524.txt | 2 +-
Documentation/devicetree/bindings/sound/wm8580.txt | 2 +-
Documentation/devicetree/bindings/sound/wm8711.txt | 2 +-
Documentation/devicetree/bindings/sound/wm8728.txt | 2 +-
Documentation/devicetree/bindings/sound/wm8731.txt | 2 +-
Documentation/devicetree/bindings/sound/wm8737.txt | 2 +-
Documentation/devicetree/bindings/sound/wm8741.txt | 2 +-
Documentation/devicetree/bindings/sound/wm8750.txt | 2 +-
Documentation/devicetree/bindings/sound/wm8753.txt | 2 +-
Documentation/devicetree/bindings/sound/wm8770.txt | 2 +-
Documentation/devicetree/bindings/sound/wm8776.txt | 2 +-
Documentation/devicetree/bindings/sound/wm8804.txt | 2 +-
Documentation/devicetree/bindings/sound/wm8903.txt | 2 +-
Documentation/devicetree/bindings/sound/wm8994.txt | 2 +-
16 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/wm8510.txt b/Documentation/devicetree/bindings/sound/wm8510.txt
index fa1a32b85577..e6b6cc041f89 100644
--- a/Documentation/devicetree/bindings/sound/wm8510.txt
+++ b/Documentation/devicetree/bindings/sound/wm8510.txt
@@ -12,7 +12,7 @@ Required properties:
Example:
-codec: wm8510@1a {
+wm8510: codec@1a {
compatible = "wlf,wm8510";
reg = <0x1a>;
};
diff --git a/Documentation/devicetree/bindings/sound/wm8523.txt b/Documentation/devicetree/bindings/sound/wm8523.txt
index 04746186b283..f3a6485f4b8a 100644
--- a/Documentation/devicetree/bindings/sound/wm8523.txt
+++ b/Documentation/devicetree/bindings/sound/wm8523.txt
@@ -10,7 +10,7 @@ Required properties:
Example:
-codec: wm8523@1a {
+wm8523: codec@1a {
compatible = "wlf,wm8523";
reg = <0x1a>;
};
diff --git a/Documentation/devicetree/bindings/sound/wm8524.txt b/Documentation/devicetree/bindings/sound/wm8524.txt
index 0f0553563fc1..f6c0c263b135 100644
--- a/Documentation/devicetree/bindings/sound/wm8524.txt
+++ b/Documentation/devicetree/bindings/sound/wm8524.txt
@@ -10,7 +10,7 @@ Required properties:
Example:
-codec: wm8524 {
+wm8524: codec {
compatible = "wlf,wm8524";
wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
};
diff --git a/Documentation/devicetree/bindings/sound/wm8580.txt b/Documentation/devicetree/bindings/sound/wm8580.txt
index 78fce9b14954..ff3f9f5f2111 100644
--- a/Documentation/devicetree/bindings/sound/wm8580.txt
+++ b/Documentation/devicetree/bindings/sound/wm8580.txt
@@ -10,7 +10,7 @@ Required properties:
Example:
-codec: wm8580@1a {
+wm8580: codec@1a {
compatible = "wlf,wm8580";
reg = <0x1a>;
};
diff --git a/Documentation/devicetree/bindings/sound/wm8711.txt b/Documentation/devicetree/bindings/sound/wm8711.txt
index 8ed9998cd23c..c30a1387c4bf 100644
--- a/Documentation/devicetree/bindings/sound/wm8711.txt
+++ b/Documentation/devicetree/bindings/sound/wm8711.txt
@@ -12,7 +12,7 @@ Required properties:
Example:
-codec: wm8711@1a {
+wm8711: codec@1a {
compatible = "wlf,wm8711";
reg = <0x1a>;
};
diff --git a/Documentation/devicetree/bindings/sound/wm8728.txt b/Documentation/devicetree/bindings/sound/wm8728.txt
index a8b5c3668e60..a3608b4c78b9 100644
--- a/Documentation/devicetree/bindings/sound/wm8728.txt
+++ b/Documentation/devicetree/bindings/sound/wm8728.txt
@@ -12,7 +12,7 @@ Required properties:
Example:
-codec: wm8728@1a {
+wm8728: codec@1a {
compatible = "wlf,wm8728";
reg = <0x1a>;
};
diff --git a/Documentation/devicetree/bindings/sound/wm8731.txt b/Documentation/devicetree/bindings/sound/wm8731.txt
index 236690e99b87..f660d9bb0e69 100644
--- a/Documentation/devicetree/bindings/sound/wm8731.txt
+++ b/Documentation/devicetree/bindings/sound/wm8731.txt
@@ -12,7 +12,7 @@ Required properties:
Example:
-codec: wm8731@1a {
+wm8731: codec@1a {
compatible = "wlf,wm8731";
reg = <0x1a>;
};
diff --git a/Documentation/devicetree/bindings/sound/wm8737.txt b/Documentation/devicetree/bindings/sound/wm8737.txt
index 4bc2cea3b140..eda1ec6a7563 100644
--- a/Documentation/devicetree/bindings/sound/wm8737.txt
+++ b/Documentation/devicetree/bindings/sound/wm8737.txt
@@ -12,7 +12,7 @@ Required properties:
Example:
-codec: wm8737@1a {
+wm8737: codec@1a {
compatible = "wlf,wm8737";
reg = <0x1a>;
};
diff --git a/Documentation/devicetree/bindings/sound/wm8741.txt b/Documentation/devicetree/bindings/sound/wm8741.txt
index a13315408719..b69e196c741c 100644
--- a/Documentation/devicetree/bindings/sound/wm8741.txt
+++ b/Documentation/devicetree/bindings/sound/wm8741.txt
@@ -21,7 +21,7 @@ Optional properties:
Example:
-codec: wm8741@1a {
+wm8741: codec@1a {
compatible = "wlf,wm8741";
reg = <0x1a>;
diff --git a/Documentation/devicetree/bindings/sound/wm8750.txt b/Documentation/devicetree/bindings/sound/wm8750.txt
index 8db239fd5ecd..682f221f6f38 100644
--- a/Documentation/devicetree/bindings/sound/wm8750.txt
+++ b/Documentation/devicetree/bindings/sound/wm8750.txt
@@ -12,7 +12,7 @@ Required properties:
Example:
-codec: wm8750@1a {
+wm8750: codec@1a {
compatible = "wlf,wm8750";
reg = <0x1a>;
};
diff --git a/Documentation/devicetree/bindings/sound/wm8753.txt b/Documentation/devicetree/bindings/sound/wm8753.txt
index 8eee61282105..eca9e5a825a9 100644
--- a/Documentation/devicetree/bindings/sound/wm8753.txt
+++ b/Documentation/devicetree/bindings/sound/wm8753.txt
@@ -34,7 +34,7 @@ Pins on the device (for linking into audio routes):
Example:
-codec: wm8753@1a {
+wm8753: codec@1a {
compatible = "wlf,wm8753";
reg = <0x1a>;
};
diff --git a/Documentation/devicetree/bindings/sound/wm8770.txt b/Documentation/devicetree/bindings/sound/wm8770.txt
index 866e00ca150b..cac762a1105d 100644
--- a/Documentation/devicetree/bindings/sound/wm8770.txt
+++ b/Documentation/devicetree/bindings/sound/wm8770.txt
@@ -10,7 +10,7 @@ Required properties:
Example:
-codec: wm8770@1 {
+wm8770: codec@1 {
compatible = "wlf,wm8770";
reg = <1>;
};
diff --git a/Documentation/devicetree/bindings/sound/wm8776.txt b/Documentation/devicetree/bindings/sound/wm8776.txt
index 3b9ca49abc2b..01173369c3ed 100644
--- a/Documentation/devicetree/bindings/sound/wm8776.txt
+++ b/Documentation/devicetree/bindings/sound/wm8776.txt
@@ -12,7 +12,7 @@ Required properties:
Example:
-codec: wm8776@1a {
+wm8776: codec@1a {
compatible = "wlf,wm8776";
reg = <0x1a>;
};
diff --git a/Documentation/devicetree/bindings/sound/wm8804.txt b/Documentation/devicetree/bindings/sound/wm8804.txt
index 6fd124b16496..2c1641c17a91 100644
--- a/Documentation/devicetree/bindings/sound/wm8804.txt
+++ b/Documentation/devicetree/bindings/sound/wm8804.txt
@@ -19,7 +19,7 @@ Optional properties:
Example:
-codec: wm8804@1a {
+wm8804: codec@1a {
compatible = "wlf,wm8804";
reg = <0x1a>;
};
diff --git a/Documentation/devicetree/bindings/sound/wm8903.txt b/Documentation/devicetree/bindings/sound/wm8903.txt
index afc51caf1137..6371c2434afe 100644
--- a/Documentation/devicetree/bindings/sound/wm8903.txt
+++ b/Documentation/devicetree/bindings/sound/wm8903.txt
@@ -57,7 +57,7 @@ Pins on the device (for linking into audio routes):
Example:
-codec: wm8903@1a {
+wm8903: codec@1a {
compatible = "wlf,wm8903";
reg = <0x1a>;
interrupts = < 347 >;
diff --git a/Documentation/devicetree/bindings/sound/wm8994.txt b/Documentation/devicetree/bindings/sound/wm8994.txt
index 68c4e8d96bed..4a9dead1b7d3 100644
--- a/Documentation/devicetree/bindings/sound/wm8994.txt
+++ b/Documentation/devicetree/bindings/sound/wm8994.txt
@@ -59,7 +59,7 @@ Optional properties:
Example:
-codec: wm8994@1a {
+wm8994: codec@1a {
compatible = "wlf,wm8994";
reg = <0x1a>;
--
2.17.0
^ permalink raw reply related
* Re: [PATCH 3/4] dt-bindings: PCI: cadence: Add DT bindings for optional PHYs
From: Lorenzo Pieralisi @ 2018-05-22 11:02 UTC (permalink / raw)
To: Alan Douglas
Cc: bhelgaas@google.com, kishon@ti.com, linux-pci@vger.kernel.org,
cyrille.pitchen@free-electrons.com, devicetree@vger.kernel.org,
nsekhar@ti.com
In-Reply-To: <SN6PR07MB451213F202165D9733877828D8940@SN6PR07MB4512.namprd07.prod.outlook.com>
On Tue, May 22, 2018 at 09:08:01AM +0000, Alan Douglas wrote:
> From: Alan Douglas <adouglas@cadence.com>
>
> Update DT documentation to include optional PHYs for cadence PCIe
> host and endpoint controllers.
>
> Signed-off-by: Alan Douglas <adouglas@cadence.com>
> ---
> Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt | 4 ++++
> Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt | 2 ++
> 2 files changed, 6 insertions(+)
It looks like v2 of patches [3-4] did not make it to the linux-pci list.
I do not know why you sent two versions and what happened, I suggest you
avoid adding linux-pci@vger.kernel.org in both to: and cc: for no reason
to start with.
Anyway, I can't apply patches that aren't on the PCI mailing list.
Can you please generate the series with:
git format-patch
and send it with
git send-email
to make sure headers, etc. are in order ? You can resend a v2 by
sticking a "RESEND" at the beginning of (every) patch subject:
[RESEND PATCH v2...]
Please send patches to yourself first to make sure everything is OK,
email threading inclusive.
Thanks,
Lorenzo
>
> diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
> index 9a305237..e40c635 100644
> --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
> +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt
> @@ -9,6 +9,8 @@ Required properties:
>
> Optional properties:
> - max-functions: Maximum number of functions that can be configured (default 1).
> +- phys: From PHY bindings: List of Generic PHY phandles.
> +- phy-names: List of names to identify the PHY.
>
> Example:
>
> @@ -19,4 +21,6 @@ pcie@fc000000 {
> reg-names = "reg", "mem";
> cdns,max-outbound-regions = <16>;
> max-functions = /bits/ 8 <8>;
> + phys = <&ep_phy0 &ep_phy1>;
> + phy-names = "pcie-lane0","pcie-lane1";
> };
> diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
> index 20a33f3..c0ca4c1 100644
> --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
> +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.txt
> @@ -24,6 +24,8 @@ Optional properties:
> translations (default 32)
> - vendor-id: The PCI vendor ID (16 bits, default is design dependent)
> - device-id: The PCI device ID (16 bits, default is design dependent)
> +- phys: From PHY bindings: List of Generic PHY phandles.
> +- phy-names: List of names to identify the PHY.
>
> Example:
>
> --
> 2.2.2
>
^ permalink raw reply
* [PATCH net-next v2 0/7] Add support for QCA8334 switch
From: Michal Vokáč @ 2018-05-22 11:16 UTC (permalink / raw)
To: netdev
Cc: linux-kernel, devicetree, f.fainelli, vivien.didelot, andrew,
mark.rutland, robh+dt, davem, michal.vokac
This series basically adds support for a QCA8334 ethernet switch to the
qca8k driver. It is a four-port variant of the already supported seven
port QCA8337. Register map is the same for the whole familly and all chips
have the same device ID.
Major part of this series enhances the CPU port setting. Currently the CPU
port is not set to any sensible defaults compatible with the xGMII
interface. This series forces the CPU port to its maximum bandwidth and
also allows to adjust the new defaults using fixed-link device tree
sub-node.
Alongside these changes I fixed two checkpatch warnings regarding SPDX and
redundant parentheses.
Michal Vokáč (7):
net: dsa: qca8k: Add QCA8334 binding documentation
net: dsa: qca8k: Add support for QCA8334 switch
net: dsa: qca8k: Enable RXMAC when bringing up a port
net: dsa: qca8k: Force CPU port to its highest bandwidth
net: dsa: qca8k: Allow overwriting CPU port setting
net: dsa: qca8k: Replace GPL boilerplate by SPDX
net: dsa: qca8k: Remove redundant parentheses
.../devicetree/bindings/net/dsa/qca8k.txt | 23 +++++++-
drivers/net/dsa/qca8k.c | 64 ++++++++++++++++++----
drivers/net/dsa/qca8k.h | 7 ++-
3 files changed, 79 insertions(+), 15 deletions(-)
--
2.1.4
^ permalink raw reply
* [PATCH net-next v2 1/7] net: dsa: qca8k: Add QCA8334 binding documentation
From: Michal Vokáč @ 2018-05-22 11:16 UTC (permalink / raw)
To: netdev
Cc: linux-kernel, devicetree, f.fainelli, vivien.didelot, andrew,
mark.rutland, robh+dt, davem, michal.vokac
In-Reply-To: <1526987792-56861-1-git-send-email-michal.vokac@ysoft.com>
Add support for the four-port variant of the Qualcomm QCA833x switch.
The CPU port default link settings can be reconfigured using
a fixed-link sub-node.
Signed-off-by: Michal Vokáč <michal.vokac@ysoft.com>
---
Changes in v2:
- Add commit message and document fixed-link binding.
.../devicetree/bindings/net/dsa/qca8k.txt | 23 +++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
index 9c67ee4..15b9057 100644
--- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt
+++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
@@ -2,7 +2,10 @@
Required properties:
-- compatible: should be "qca,qca8337"
+- compatible: should be one of:
+ "qca,qca8334"
+ "qca,qca8337"
+
- #size-cells: must be 0
- #address-cells: must be 1
@@ -14,6 +17,20 @@ port and PHY id, each subnode describing a port needs to have a valid phandle
referencing the internal PHY connected to it. The CPU port of this switch is
always port 0.
+A CPU port node has the following optional property:
+
+- fixed-link : Fixed-link subnode describing a link to a non-MDIO
+ managed entity. See
+ Documentation/devicetree/bindings/net/fixed-link.txt
+ for details.
+
+For QCA8K the 'fixed-link' sub-node supports only the following properties:
+
+- 'speed' (integer, mandatory), to indicate the link speed. Accepted
+ values are 10, 100 and 1000
+- 'full-duplex' (boolean, optional), to indicate that full duplex is
+ used. When absent, half duplex is assumed.
+
Example:
@@ -53,6 +70,10 @@ Example:
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "rgmii";
+ fixed-link {
+ speed = 1000;
+ full-duplex;
+ };
};
port@1 {
--
2.1.4
^ permalink raw reply related
* [PATCH net-next v2 2/7] net: dsa: qca8k: Add support for QCA8334 switch
From: Michal Vokáč @ 2018-05-22 11:16 UTC (permalink / raw)
To: netdev
Cc: linux-kernel, devicetree, f.fainelli, vivien.didelot, andrew,
mark.rutland, robh+dt, davem, michal.vokac
In-Reply-To: <1526987792-56861-1-git-send-email-michal.vokac@ysoft.com>
Add support for the four-port variant of the Qualcomm QCA833x switch.
Signed-off-by: Michal Vokáč <michal.vokac@ysoft.com>
---
Changes in v2:
- Add commit message.
drivers/net/dsa/qca8k.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index 3684e56..6a3ffb2 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -1010,6 +1010,7 @@ static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
qca8k_suspend, qca8k_resume);
static const struct of_device_id qca8k_of_match[] = {
+ { .compatible = "qca,qca8334" },
{ .compatible = "qca,qca8337" },
{ /* sentinel */ },
};
--
2.1.4
^ permalink raw reply related
* [PATCH net-next v2 3/7] net: dsa: qca8k: Enable RXMAC when bringing up a port
From: Michal Vokáč @ 2018-05-22 11:16 UTC (permalink / raw)
To: netdev
Cc: linux-kernel, devicetree, f.fainelli, vivien.didelot, andrew,
mark.rutland, robh+dt, davem, michal.vokac
In-Reply-To: <1526987792-56861-1-git-send-email-michal.vokac@ysoft.com>
When a port is brought up/down do not enable/disable only the TXMAC
but the RXMAC as well. This is essential for the CPU port to work.
Fixes: 6b93fb46480a ("net-next: dsa: add new driver for qca8xxx family")
Signed-off-by: Michal Vokáč <michal.vokac@ysoft.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
---
Changes in v2:
- Add "Fixes" tag as pointed out by Florian.
- Add "Reviewed-by" tags from Andrew and Florian.
drivers/net/dsa/qca8k.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index 6a3ffb2..0d224f3 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -516,7 +516,7 @@ qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
static void
qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
{
- u32 mask = QCA8K_PORT_STATUS_TXMAC;
+ u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
pr_debug("qca: port %i set status %i\n", port, enable);
--
2.1.4
^ permalink raw reply related
* [PATCH net-next v2 4/7] net: dsa: qca8k: Force CPU port to its highest bandwidth
From: Michal Vokáč @ 2018-05-22 11:16 UTC (permalink / raw)
To: netdev
Cc: linux-kernel, devicetree, f.fainelli, vivien.didelot, andrew,
mark.rutland, robh+dt, davem, michal.vokac
In-Reply-To: <1526987792-56861-1-git-send-email-michal.vokac@ysoft.com>
By default autonegotiation is enabled to configure MAC on all ports.
For the CPU port autonegotiation can not be used so we need to set
some sensible defaults manually.
This patch forces the default setting of the CPU port to 1000Mbps/full
duplex which is the chip maximum capability.
Also correct size of the bit field used to configure link speed.
Fixes: 6b93fb46480a ("net-next: dsa: add new driver for qca8xxx family")
Signed-off-by: Michal Vokáč <michal.vokac@ysoft.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
---
Changes in v2:
- Add "Fixes" tag as pointed out by Florian.
- Add "Reviewed-by" tags from Andrew and Florian.
drivers/net/dsa/qca8k.c | 6 +++++-
drivers/net/dsa/qca8k.h | 6 ++++--
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index 0d224f3..14a108b38 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -537,6 +537,7 @@ qca8k_setup(struct dsa_switch *ds)
{
struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
int ret, i, phy_mode = -1;
+ u32 mask;
pr_debug("qca: setup\n");
@@ -564,7 +565,10 @@ qca8k_setup(struct dsa_switch *ds)
if (ret < 0)
return ret;
- /* Enable CPU Port */
+ /* Enable CPU Port, force it to maximum bandwidth and full-duplex */
+ mask = QCA8K_PORT_STATUS_SPEED_1000 | QCA8K_PORT_STATUS_TXFLOW |
+ QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_DUPLEX;
+ qca8k_write(priv, QCA8K_REG_PORT_STATUS(QCA8K_CPU_PORT), mask);
qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
qca8k_port_set_status(priv, QCA8K_CPU_PORT, 1);
diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index 1cf8a92..5bda165 100644
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -51,8 +51,10 @@
#define QCA8K_GOL_MAC_ADDR0 0x60
#define QCA8K_GOL_MAC_ADDR1 0x64
#define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
-#define QCA8K_PORT_STATUS_SPEED GENMASK(2, 0)
-#define QCA8K_PORT_STATUS_SPEED_S 0
+#define QCA8K_PORT_STATUS_SPEED GENMASK(1, 0)
+#define QCA8K_PORT_STATUS_SPEED_10 0
+#define QCA8K_PORT_STATUS_SPEED_100 0x1
+#define QCA8K_PORT_STATUS_SPEED_1000 0x2
#define QCA8K_PORT_STATUS_TXMAC BIT(2)
#define QCA8K_PORT_STATUS_RXMAC BIT(3)
#define QCA8K_PORT_STATUS_TXFLOW BIT(4)
--
2.1.4
^ permalink raw reply related
* [PATCH net-next v2 5/7] net: dsa: qca8k: Allow overwriting CPU port setting
From: Michal Vokáč @ 2018-05-22 11:16 UTC (permalink / raw)
To: netdev
Cc: linux-kernel, devicetree, f.fainelli, vivien.didelot, andrew,
mark.rutland, robh+dt, davem, michal.vokac
In-Reply-To: <1526987792-56861-1-git-send-email-michal.vokac@ysoft.com>
Implement adjust_link function that allows to overwrite default CPU port
setting using fixed-link device tree subnode.
Signed-off-by: Michal Vokáč <michal.vokac@ysoft.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
---
Changes in v2:
- Add "Reviewed-by" tags from Andrew and Florian.
drivers/net/dsa/qca8k.c | 43 +++++++++++++++++++++++++++++++++++++++++++
drivers/net/dsa/qca8k.h | 1 +
2 files changed, 44 insertions(+)
diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
index 14a108b38..7eba987 100644
--- a/drivers/net/dsa/qca8k.c
+++ b/drivers/net/dsa/qca8k.c
@@ -636,6 +636,47 @@ qca8k_setup(struct dsa_switch *ds)
return 0;
}
+static void
+qca8k_adjust_link(struct dsa_switch *ds, int port, struct phy_device *phy)
+{
+ struct qca8k_priv *priv = ds->priv;
+ u32 reg;
+
+ /* Force fixed-link setting for CPU port, skip others. */
+ if (!phy_is_pseudo_fixed_link(phy))
+ return;
+
+ /* Set port speed */
+ switch (phy->speed) {
+ case 10:
+ reg = QCA8K_PORT_STATUS_SPEED_10;
+ break;
+ case 100:
+ reg = QCA8K_PORT_STATUS_SPEED_100;
+ break;
+ case 1000:
+ reg = QCA8K_PORT_STATUS_SPEED_1000;
+ break;
+ default:
+ dev_dbg(priv->dev, "port%d link speed %dMbps not supported.\n",
+ port, phy->speed);
+ return;
+ }
+
+ /* Set duplex mode */
+ if (phy->duplex == DUPLEX_FULL)
+ reg |= QCA8K_PORT_STATUS_DUPLEX;
+
+ /* Force flow control */
+ if (dsa_is_cpu_port(ds, port))
+ reg |= QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_TXFLOW;
+
+ /* Force link down before changing MAC options */
+ qca8k_port_set_status(priv, port, 0);
+ qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
+ qca8k_port_set_status(priv, port, 1);
+}
+
static int
qca8k_phy_read(struct dsa_switch *ds, int phy, int regnum)
{
@@ -909,6 +950,7 @@ qca8k_get_tag_protocol(struct dsa_switch *ds, int port)
static const struct dsa_switch_ops qca8k_switch_ops = {
.get_tag_protocol = qca8k_get_tag_protocol,
.setup = qca8k_setup,
+ .adjust_link = qca8k_adjust_link,
.get_strings = qca8k_get_strings,
.phy_read = qca8k_phy_read,
.phy_write = qca8k_phy_write,
@@ -942,6 +984,7 @@ qca8k_sw_probe(struct mdio_device *mdiodev)
return -ENOMEM;
priv->bus = mdiodev->bus;
+ priv->dev = &mdiodev->dev;
/* read the switches ID register */
id = qca8k_read(priv, QCA8K_REG_MASK_CTRL);
diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
index 5bda165..613fe5c5 100644
--- a/drivers/net/dsa/qca8k.h
+++ b/drivers/net/dsa/qca8k.h
@@ -167,6 +167,7 @@ struct qca8k_priv {
struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];
struct dsa_switch *ds;
struct mutex reg_mutex;
+ struct device *dev;
};
struct qca8k_mib_desc {
--
2.1.4
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