* Re: [PATCH v3] arm64: allwinner: a64: Add Amarula A64-Relic initial support
From: Maxime Ripard @ 2018-05-23 8:18 UTC (permalink / raw)
To: Jagan Teki
Cc: Chen-Yu Tsai, Michael Trimarchi, Icenowy Zheng, devicetree,
linux-arm-kernel, linux-kernel, linux-sunxi
In-Reply-To: <CAMty3ZD3JT-ToGAUHN_uj7uVK-jkyAwfEdTBCmJSj34bACFpYQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
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On Wed, May 23, 2018 at 11:44:56AM +0530, Jagan Teki wrote:
> On Tue, May 22, 2018 at 8:00 PM, Maxime Ripard
> <maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org> wrote:
> > On Tue, May 22, 2018 at 06:52:28PM +0530, Jagan Teki wrote:
> >> Amarula A64-Relic is Allwinner A64 based IoT device, which support
> >> - Allwinner A64 Cortex-A53
> >> - Mali-400MP2 GPU
> >> - AXP803 PMIC
> >> - 1GB DDR3 RAM
> >> - 8GB eMMC
> >> - AP6330 Wifi/BLE
> >> - MIPI-DSI
> >> - CSI: OV5640 sensor
> >> - USB OTG
> >
> > You claim that this is doing OTG...
> >
> > [..]
> >
> >> +&usb_otg {
> >> + dr_mode = "peripheral";
> >> + status = "okay";
> >> +};
> >
> > ... and yet you're setting it as peripheral...
>
> Though it claims OTG, board doesn't have any USB ports to operate(not
> even Mini-AB) the only way to use the board as peripheral to transfer
> images from host.
I'm not sure what you mean here. If there's no USB connector, why do
you even enable it?
maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH v5 1/3] ARM: dts: tegra: Remove skeleton.dtsi and fix DTC warnings for /memory
From: Stefan Agner @ 2018-05-23 8:22 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Mark Rutland, Thierry Reding, Jonathan Hunter,
devicetree, linux-tegra, linux-kernel, Marcel Ziswiler,
Lucas Stach
In-Reply-To: <CAJKOXPeOg7Xjx0qr2qZ0dLs56HFD=1=gbGh8VPeS+PgQm6QQZg@mail.gmail.com>
On 23.05.2018 09:05, Krzysztof Kozlowski wrote:
> On Thu, May 17, 2018 at 1:39 PM, Stefan Agner <stefan@agner.ch> wrote:
>> On 17.05.2018 09:45, Krzysztof Kozlowski wrote:
>>> Remove the usage of skeleton.dtsi and add necessary properties to /memory
>>> node to fix the DTC warnings:
>>>
>>> arch/arm/boot/dts/tegra20-harmony.dtb: Warning (unit_address_vs_reg):
>>> /memory: node has a reg or ranges property, but no unit name
>>>
>>> The DTB after the change is the same as before except adding
>>> unit-address to /memory node.
>>>
>>> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
>>>
>>> ---
>>>
>>> Changes since v4:
>>> 1. None
>>> ---
>>> arch/arm/boot/dts/tegra114-dalmore.dts | 3 ++-
>>> arch/arm/boot/dts/tegra114-roth.dts | 3 ++-
>>> arch/arm/boot/dts/tegra114-tn7.dts | 3 ++-
>>> arch/arm/boot/dts/tegra114.dtsi | 4 ++--
>>> arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi | 3 ++-
>>> arch/arm/boot/dts/tegra124-apalis.dtsi | 3 ++-
>>> arch/arm/boot/dts/tegra124-jetson-tk1.dts | 3 ++-
>>> arch/arm/boot/dts/tegra124-nyan.dtsi | 3 ++-
>>> arch/arm/boot/dts/tegra124-venice2.dts | 3 ++-
>>> arch/arm/boot/dts/tegra124.dtsi | 2 --
>>> arch/arm/boot/dts/tegra20-colibri-512.dtsi | 3 ++-
>>> arch/arm/boot/dts/tegra20-harmony.dts | 3 ++-
>>> arch/arm/boot/dts/tegra20-paz00.dts | 3 ++-
>>> arch/arm/boot/dts/tegra20-seaboard.dts | 3 ++-
>>> arch/arm/boot/dts/tegra20-tamonten.dtsi | 3 ++-
>>> arch/arm/boot/dts/tegra20-trimslice.dts | 3 ++-
>>> arch/arm/boot/dts/tegra20-ventana.dts | 3 ++-
>>> arch/arm/boot/dts/tegra20.dtsi | 7 +++++--
>>> arch/arm/boot/dts/tegra30-apalis.dtsi | 5 +++++
>>> arch/arm/boot/dts/tegra30-beaver.dts | 3 ++-
>>> arch/arm/boot/dts/tegra30-cardhu.dtsi | 3 ++-
>>> arch/arm/boot/dts/tegra30-colibri.dtsi | 3 ++-
>>> arch/arm/boot/dts/tegra30.dtsi | 7 +++++--
>>> 23 files changed, 53 insertions(+), 26 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts
>>> b/arch/arm/boot/dts/tegra114-dalmore.dts
>>> index eafff16765b4..5cdcedfc19cb 100644
>>> --- a/arch/arm/boot/dts/tegra114-dalmore.dts
>>> +++ b/arch/arm/boot/dts/tegra114-dalmore.dts
>>> @@ -23,7 +23,8 @@
>>> stdout-path = "serial0:115200n8";
>>> };
>>>
>>> - memory {
>>> + memory@80000000 {
>>> + device_type = "memory";
>>> reg = <0x80000000 0x40000000>;
>>> };
>>>
>>> diff --git a/arch/arm/boot/dts/tegra114-roth.dts
>>> b/arch/arm/boot/dts/tegra114-roth.dts
>>> index 7ed7370ee67a..b4f329a07c60 100644
>>> --- a/arch/arm/boot/dts/tegra114-roth.dts
>>> +++ b/arch/arm/boot/dts/tegra114-roth.dts
>>> @@ -28,7 +28,8 @@
>>> };
>>> };
>>>
>>> - memory {
>>> + memory@80000000 {
>>> + device_type = "memory";
>>> /* memory >= 0x79600000 is reserved for firmware usage */
>>> reg = <0x80000000 0x79600000>;
>>> };
>>> diff --git a/arch/arm/boot/dts/tegra114-tn7.dts
>>> b/arch/arm/boot/dts/tegra114-tn7.dts
>>> index 7fc4a8b31e45..12092d344ce8 100644
>>> --- a/arch/arm/boot/dts/tegra114-tn7.dts
>>> +++ b/arch/arm/boot/dts/tegra114-tn7.dts
>>> @@ -28,7 +28,8 @@
>>> };
>>> };
>>>
>>> - memory {
>>> + memory@80000000 {
>>> + device_type = "memory";
>>> /* memory >= 0x37e00000 is reserved for firmware usage */
>>> reg = <0x80000000 0x37e00000>;
>>> };
>>> diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
>>> index 0e4a13295d8a..b917784d3f97 100644
>>> --- a/arch/arm/boot/dts/tegra114.dtsi
>>> +++ b/arch/arm/boot/dts/tegra114.dtsi
>>> @@ -5,11 +5,11 @@
>>> #include <dt-bindings/pinctrl/pinctrl-tegra.h>
>>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>
>>> -#include "skeleton.dtsi"
>>> -
>>> / {
>>> compatible = "nvidia,tegra114";
>>> interrupt-parent = <&lic>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>>
>>> host1x@50000000 {
>>> compatible = "nvidia,tegra114-host1x", "simple-bus";
>>> diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
>>> b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
>>> index bb67edb016c5..80b52c612891 100644
>>> --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
>>> +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi
>>> @@ -15,7 +15,8 @@
>>> compatible = "toradex,apalis-tk1-v1.2", "toradex,apalis-tk1",
>>> "nvidia,tegra124";
>>>
>>> - memory {
>>> + memory@0 {
>>> + device_type = "memory";
>>> reg = <0x0 0x80000000 0x0 0x80000000>;
>>> };
>>>
>>> diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi
>>> b/arch/arm/boot/dts/tegra124-apalis.dtsi
>>> index 65a2161b9b8e..3ca7601cafe9 100644
>>> --- a/arch/arm/boot/dts/tegra124-apalis.dtsi
>>> +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
>>> @@ -50,7 +50,8 @@
>>> model = "Toradex Apalis TK1";
>>> compatible = "toradex,apalis-tk1", "nvidia,tegra124";
>>>
>>> - memory {
>>> + memory@0 {
>>> + device_type = "memory";
>>> reg = <0x0 0x80000000 0x0 0x80000000>;
>>> };
>>>
>>> diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>>> b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>>> index 6dbcf84dafbc..8d9e6ee6c6a7 100644
>>> --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>>> +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
>>> @@ -24,7 +24,8 @@
>>> stdout-path = "serial0:115200n8";
>>> };
>>>
>>> - memory {
>>> + memory@0 {
>>> + device_type = "memory";
>>> reg = <0x0 0x80000000 0x0 0x80000000>;
>>> };
>>>
>>> diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi
>>> b/arch/arm/boot/dts/tegra124-nyan.dtsi
>>> index 3609367037a6..15a2b0e3237e 100644
>>> --- a/arch/arm/boot/dts/tegra124-nyan.dtsi
>>> +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
>>> @@ -13,7 +13,8 @@
>>> stdout-path = "serial0:115200n8";
>>> };
>>>
>>> - memory {
>>> + memory@0 {
>>> + device_type = "memory";
>>> reg = <0x0 0x80000000 0x0 0x80000000>;
>>> };
>>>
>>> diff --git a/arch/arm/boot/dts/tegra124-venice2.dts
>>> b/arch/arm/boot/dts/tegra124-venice2.dts
>>> index 89bcc178994d..241cdc4b6600 100644
>>> --- a/arch/arm/boot/dts/tegra124-venice2.dts
>>> +++ b/arch/arm/boot/dts/tegra124-venice2.dts
>>> @@ -18,7 +18,8 @@
>>> stdout-path = "serial0:115200n8";
>>> };
>>>
>>> - memory {
>>> + memory@0 {
>>> + device_type = "memory";
>>> reg = <0x0 0x80000000 0x0 0x80000000>;
>>> };
>>>
>>> diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
>>> index 174092bfac90..df1642876a4c 100644
>>> --- a/arch/arm/boot/dts/tegra124.dtsi
>>> +++ b/arch/arm/boot/dts/tegra124.dtsi
>>> @@ -7,8 +7,6 @@
>>> #include <dt-bindings/reset/tegra124-car.h>
>>> #include <dt-bindings/thermal/tegra124-soctherm.h>
>>>
>>> -#include "skeleton.dtsi"
>>> -
>>> / {
>>> compatible = "nvidia,tegra124";
>>> interrupt-parent = <&lic>;
>>> diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
>>> b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
>>> index 5c202b3e3bb1..305efb275b48 100644
>>> --- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
>>> +++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
>>> @@ -10,7 +10,8 @@
>>> rtc1 = "/rtc@7000e000";
>>> };
>>>
>>> - memory {
>>> + memory@0 {
>>> + device_type = "memory";
>>> reg = <0x00000000 0x20000000>;
>>> };
>>>
>>> diff --git a/arch/arm/boot/dts/tegra20-harmony.dts
>>> b/arch/arm/boot/dts/tegra20-harmony.dts
>>> index 628a55a9318b..5009a55ae15c 100644
>>> --- a/arch/arm/boot/dts/tegra20-harmony.dts
>>> +++ b/arch/arm/boot/dts/tegra20-harmony.dts
>>> @@ -18,7 +18,8 @@
>>> stdout-path = "serial0:115200n8";
>>> };
>>>
>>> - memory {
>>> + memory@0 {
>>> + device_type = "memory";
>>> reg = <0x00000000 0x40000000>;
>>> };
>>>
>>> diff --git a/arch/arm/boot/dts/tegra20-paz00.dts
>>> b/arch/arm/boot/dts/tegra20-paz00.dts
>>> index 30436969adc0..e794ac5442ef 100644
>>> --- a/arch/arm/boot/dts/tegra20-paz00.dts
>>> +++ b/arch/arm/boot/dts/tegra20-paz00.dts
>>> @@ -19,7 +19,8 @@
>>> stdout-path = "serial0:115200n8";
>>> };
>>>
>>> - memory {
>>> + memory@0 {
>>> + device_type = "memory";
>>> reg = <0x00000000 0x20000000>;
>>> };
>>>
>>> diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts
>>> b/arch/arm/boot/dts/tegra20-seaboard.dts
>>> index 284aae351ff2..6cb832cfa4f3 100644
>>> --- a/arch/arm/boot/dts/tegra20-seaboard.dts
>>> +++ b/arch/arm/boot/dts/tegra20-seaboard.dts
>>> @@ -18,7 +18,8 @@
>>> stdout-path = "serial0:115200n8";
>>> };
>>>
>>> - memory {
>>> + memory@0 {
>>> + device_type = "memory";
>>> reg = <0x00000000 0x40000000>;
>>> };
>>>
>>> diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi
>>> b/arch/arm/boot/dts/tegra20-tamonten.dtsi
>>> index 872046d48709..6ceb1228fed3 100644
>>> --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
>>> +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
>>> @@ -15,7 +15,8 @@
>>> stdout-path = "serial0:115200n8";
>>> };
>>>
>>> - memory {
>>> + memory@0 {
>>> + device_type = "memory";
>>> reg = <0x00000000 0x20000000>;
>>> };
>>>
>>> diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts
>>> b/arch/arm/boot/dts/tegra20-trimslice.dts
>>> index d55c6b240a30..3f94be3da9e5 100644
>>> --- a/arch/arm/boot/dts/tegra20-trimslice.dts
>>> +++ b/arch/arm/boot/dts/tegra20-trimslice.dts
>>> @@ -18,7 +18,8 @@
>>> stdout-path = "serial0:115200n8";
>>> };
>>>
>>> - memory {
>>> + memory@0 {
>>> + device_type = "memory";
>>> reg = <0x00000000 0x40000000>;
>>> };
>>>
>>> diff --git a/arch/arm/boot/dts/tegra20-ventana.dts
>>> b/arch/arm/boot/dts/tegra20-ventana.dts
>>> index ee3fbf941e79..c897a90289bc 100644
>>> --- a/arch/arm/boot/dts/tegra20-ventana.dts
>>> +++ b/arch/arm/boot/dts/tegra20-ventana.dts
>>> @@ -18,7 +18,8 @@
>>> stdout-path = "serial0:115200n8";
>>> };
>>>
>>> - memory {
>>> + memory@0 {
>>> + device_type = "memory";
>>> reg = <0x00000000 0x40000000>;
>>> };
>>>
>>> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
>>> index 0a7136462a1a..290ebbeb210f 100644
>>> --- a/arch/arm/boot/dts/tegra20.dtsi
>>> +++ b/arch/arm/boot/dts/tegra20.dtsi
>>> @@ -4,11 +4,14 @@
>>> #include <dt-bindings/pinctrl/pinctrl-tegra.h>
>>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>
>>> -#include "skeleton.dtsi"
>>> -
>>> / {
>>> compatible = "nvidia,tegra20";
>>> interrupt-parent = <&lic>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> +
>>> + chosen { };
>>> + aliases { };
>>>
>>> iram@40000000 {
>>> compatible = "mmio-sram";
>>> diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi
>>> b/arch/arm/boot/dts/tegra30-apalis.dtsi
>>> index d1d21ec2a844..184f60c720fa 100644
>>> --- a/arch/arm/boot/dts/tegra30-apalis.dtsi
>>> +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
>>> @@ -10,6 +10,11 @@
>>> model = "Toradex Apalis T30";
>>> compatible = "toradex,apalis_t30", "nvidia,tegra30";
>>>
>>> + memory@0 {
>>> + device_type = "memory";
>>> + reg = <0 0>;
>>> + };
>>> +
>>> pcie@3000 {
>>> avdd-pexa-supply = <&vdd2_reg>;
>>> vdd-pexa-supply = <&vdd2_reg>;
>>> diff --git a/arch/arm/boot/dts/tegra30-beaver.dts
>>> b/arch/arm/boot/dts/tegra30-beaver.dts
>>> index ae52a5039506..72369877d284 100644
>>> --- a/arch/arm/boot/dts/tegra30-beaver.dts
>>> +++ b/arch/arm/boot/dts/tegra30-beaver.dts
>>> @@ -17,7 +17,8 @@
>>> stdout-path = "serial0:115200n8";
>>> };
>>>
>>> - memory {
>>> + memory@80000000 {
>>> + device_type = "memory";
>>> reg = <0x80000000 0x7ff00000>;
>>> };
>>>
>>> diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi
>>> b/arch/arm/boot/dts/tegra30-cardhu.dtsi
>>> index 92a9740c533f..24c04d4c335d 100644
>>> --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
>>> +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
>>> @@ -40,7 +40,8 @@
>>> stdout-path = "serial0:115200n8";
>>> };
>>>
>>> - memory {
>>> + memory@80000000 {
>>> + device_type = "memory";
>>> reg = <0x80000000 0x40000000>;
>>> };
>>>
>>> diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi
>>> b/arch/arm/boot/dts/tegra30-colibri.dtsi
>>> index c44d8c40c410..cc46cedf80b9 100644
>>> --- a/arch/arm/boot/dts/tegra30-colibri.dtsi
>>> +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi
>>> @@ -10,7 +10,8 @@
>>> model = "Toradex Colibri T30";
>>> compatible = "toradex,colibri_t30", "nvidia,tegra30";
>>>
>>> - memory {
>>> + memory@80000000 {
>>> + device_type = "memory";
>>> reg = <0x80000000 0x40000000>;
>>> };
>>>
>>> diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
>>> index a110cf84d85f..4383f0fd789d 100644
>>> --- a/arch/arm/boot/dts/tegra30.dtsi
>>> +++ b/arch/arm/boot/dts/tegra30.dtsi
>>> @@ -5,11 +5,14 @@
>>> #include <dt-bindings/pinctrl/pinctrl-tegra.h>
>>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>
>>> -#include "skeleton.dtsi"
>>> -
>>> / {
>>> compatible = "nvidia,tegra30";
>>> interrupt-parent = <&lic>;
>>> + #address-cells = <1>;
>>> + #size-cells = <1>;
>>> +
>>> + chosen { };
>>> + aliases { };
>>
>> Could we not add
>>
>> memory { device_type = "memory"; };
>>
>> in the SoC level device trees?
>>
>> This would save device_type in all other instances.
>>
>> That is also how it is done in other places, e.g.
>> arch/arm/boot/dts/imx6qdl.dtsi
>
> Not really because the unit address will not match between different
> boards. The imx6qdl, as I see, has the same issue:
> - imx6qdl.dtsi defines "memory" node
> - imx6dl-apf6dev.dts includes the previous and defines "memory@10000000"
>
> This is wrong - two memory nodes.
>
Hm I see. We could add
memory@0 { device_type = "memory"; };
Since the reg property is specified in the board level device tree it
would be still fine?
Or probably better to provide a complete spec with length zero:
memory@0 {
device_type = "memory";
reg = <0x0 0x0>;
};
Even some boards do that and assume that boot loader will fill it
correctly, so that should be fine.
--
Stefan
>> Also, could we maybe split this in two?
>>
>> ARM: dts: tegra: Remove skeleton.dtsi
>> ARM: dts: tegra: fix DTC warnings for /memory
>
> It is possible to split it but this really won't bring any benefit
> because the removal of skeleton.dtsi is the way to fix the errors. Or
> saying it differently - the warnings are the reason to remove the
> skeleton.dtsi. If you split them, what is the reason to remove the
> skeleton.dtsi? (Theoretically it was deprecated so this could be
> explanation).
>
> If you wish, I can prepare something like:
> 1. Remove skeleton.dtsi and add everywhere 'device_type = "memory"'.
> All the warnings will stay but the end DTB should be equal between
> changes.
> 2. Fix warnings.
>
>> The first would only touch SoC level dts.
>
> No, because device_type has to be added everywhere. And because of
> warnings (explained before) it cannot be added to SoC DTSI.
>
> Best regards,
> Krzysztof
>
>>
>> The second then would fix DTC warnings by adding the address to the
>> memory nodes in all board files.
>>
>> --
>> Stefan
>>
>>>
>>> pcie@3000 {
>>> compatible = "nvidia,tegra30-pcie";
^ permalink raw reply
* Re: [PATCH v2 3/3] ARM: dts: imx28/imx53: enable edt-ft5x06 wakeup source
From: Daniel Mack @ 2018-05-23 8:26 UTC (permalink / raw)
To: Dmitry Torokhov, Shawn Guo
Cc: mark.rutland, devicetree, robh+dt, kernel, linux-input,
fabio.estevam, linux-arm-kernel
In-Reply-To: <20180522182043.GA123708@dtor-ws>
On Tuesday, May 22, 2018 08:20 PM, Dmitry Torokhov wrote:
> On Sun, May 20, 2018 at 09:05:30PM +0800, Shawn Guo wrote:
>> On Thu, May 17, 2018 at 11:05:52AM +0200, Daniel Mack wrote:
>>> The touchscreen driver no longer configures the device as wakeup source by
>>> default. A "wakeup-source" property is needed.
>>>
>>> To avoid regressions, this patch changes the DTS files for the only two
>>> users of this driver that didn't have this property yet.
>>>
>>> Signed-off-by: Daniel Mack <daniel@zonque.org>
>>> Cc: Shawn Guo <shawnguo@kernel.org>
>>> Cc: Sascha Hauer <kernel@pengutronix.de>
>>> Cc: Fabio Estevam <fabio.estevam@nxp.com>
>>> Cc: Rob Herring <robh+dt@kernel.org>
>>
>> Applied this one, thanks.
>
> I think there are few more that need "wakeup-source" added:
>
> arch/arm/boot/dts/am437x-sk-evm.dts
> arch/arm/boot/dts/imx6q-var-dt6customboard.dts
> arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
> arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
> arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
> arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
Oh, sorry for having missed them. Will send patches.
Thanks,
Daniel
^ permalink raw reply
* Re: [PATCH v2 1/3] input: touchscreen: edt-ft5x06: don't make device a wakeup source by default
From: Daniel Mack @ 2018-05-23 8:27 UTC (permalink / raw)
To: Rob Herring
Cc: mark.rutland, devicetree, dmitry.torokhov, kernel, linux-input,
fabio.estevam, shawnguo, linux-arm-kernel
In-Reply-To: <20180522175413.GA24850@rob-hp-laptop>
On Tuesday, May 22, 2018 07:54 PM, Rob Herring wrote:
> On Thu, May 17, 2018 at 11:05:50AM +0200, Daniel Mack wrote:
>> Allow configuring the device as wakeup source through device properties, as
>> not all platforms want to wake up on touch screen activity.
>>
>> The I2C core automatically reads the "wakeup-source" DT property to
>> configure a device's wakeup capability, and board supports files can set
>> I2C_CLIENT_WAKE in the flags.
>
> This will break wake-up on working systems. Looks like mostly i.MX, but
> there's one AM437x board. If that board doesn't care, then it is up to
> Shawn.
I added the property to the dts files, but as Dmitry pointed out, I
missed some. Sorry for that.
Thanks,
Daniel
^ permalink raw reply
* Re: [PATCH v3 1/2] regulator: dt-bindings: add QCOM RPMh regulator bindings
From: Mark Brown @ 2018-05-23 8:29 UTC (permalink / raw)
To: Doug Anderson
Cc: David Collins, Liam Girdwood, Rob Herring, Mark Rutland,
linux-arm-msm, Linux ARM, devicetree, LKML, Rajendra Nayak,
Stephen Boyd
In-Reply-To: <CAD=FV=W=BquL5ojORz4HNP889s=-uNJ-QEzUfAxwXj2Oa3cGew@mail.gmail.com>
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On Tue, May 22, 2018 at 05:08:45PM -0700, Doug Anderson wrote:
> So one client's vote for a voltage continues to be in effect even if
> that client votes to have the regulator disabled? That seems
> fundamentally broken in RPMh. I guess my take would be to work around
It's arguable either way - you could say that the client gets to specify
a safe range at all times or you could say that the machine constraints
should cover all cases where the hardware is idling. Of course RPMh
is missing anything like the machine constraints (as we can see from all
the fixing up of undesirable hard coding we have to do) so it's kind of
pushed towards the first case.
> >> A) Turn off VMMC and VQMMC
> >> B) Program VMMC and VQMMC to defaults
> >> C) Turn on VMMC and VQMMC
> >> ...right now we bootup and pretend to Linux that VMMC and VQMMC start
> >> off, so step A) will be no-op. Sigh.
> > Step A) would not work because the regulator's use_count would be 0 and
> > regulator_disable() can only be called successfully if use_count > 0. The
> > call would have no impact and it would return an error.
> Are you sure regulator_force_disable() won't do the trick on most
> boards (which will report the regulator being enabled at bootup)? I
> haven't tried it, but it seems like it might.
It does mean that things will go wrong if the regulator is shared.
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^ permalink raw reply
* Re: [PATCH v6] gpio: dwapb: Add support for 1 interrupt per port A GPIO
From: Linus Walleij @ 2018-05-23 8:29 UTC (permalink / raw)
To: Phil Edworthy
Cc: Andy Shevchenko, Hoan Tran, Mark Rutland, Rob Herring, Lee Jones,
Michel Pollet, open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas, linux-kernel@vger.kernel.org
In-Reply-To: <1526027497-32556-1-git-send-email-phil.edworthy@renesas.com>
On Fri, May 11, 2018 at 10:31 AM, Phil Edworthy
<phil.edworthy@renesas.com> wrote:
> The DesignWare GPIO IP can be configured for either 1 interrupt or 1
> per GPIO in port A, but the driver currently only supports 1 interrupt.
> See the DesignWare DW_apb_gpio Databook description of the
> 'GPIO_INTR_IO' parameter.
>
> This change allows the driver to work with up to 32 interrupts, it will
> get as many interrupts as specified in the DT 'interrupts' property.
> It doesn't do anything clever with the different interrupts, it just calls
> the same handler used for single interrupt hardware.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Acked-by: Lee Jones <lee.jones@linaro.org>
> ---
> One point to mention is that I have made it possible for users to have
> unconnected interrupts by specifying holes in the list of interrupts. This is
> done by supporting the interrupts-extended DT prop.
> However, I have no use for this and had to hack some test case for this.
> Perhaps the driver should support 1 interrupt or all GPIOa as interrupts?
>
> v6:
> - Treat DT and ACPI the same as much as possible. Note that we can't use
> platform_get_irq() to get the DT interrupts as they are in the port
> sub-node and hence do not have an associated platform device.
I already applied this patch in some version, can you check what is
in my devel branch and send incremental patches on top if
something needs changing?
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio.git/commit/?h=devel&id=e6ca26abd37606ba4864f20c85d3fe4a2173b93f
Sorry for not knowing by heart what was applied or when, it's
just too much for me sometimes.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 1/2] ARM: dts: imx6: make edt-ft5x06 a wakeup source for imx6 boards
From: Daniel Mack @ 2018-05-23 8:30 UTC (permalink / raw)
To: dmitry.torokhov, robh+dt, mark.rutland, shawnguo, kernel,
fabio.estevam
Cc: devicetree, Daniel Mack, linux-arm-kernel, linux-input
The touchscreen driver no longer configures the device as wakeup source by
default. A "wakeup-source" property is needed.
Signed-off-by: Daniel Mack <daniel@zonque.org>
---
arch/arm/boot/dts/imx6q-var-dt6customboard.dts | 1 +
arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi | 1 +
arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 1 +
arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi | 1 +
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 1 +
5 files changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts
index e0728d475f6f..7537d77b3415 100644
--- a/arch/arm/boot/dts/imx6q-var-dt6customboard.dts
+++ b/arch/arm/boot/dts/imx6q-var-dt6customboard.dts
@@ -179,6 +179,7 @@
touchscreen-size-y = <480>;
touchscreen-inverted-x;
touchscreen-inverted-y;
+ wakeup-source;
};
rtc@68 {
diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
index aab088f318e8..aef4a756ca81 100644
--- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
@@ -292,6 +292,7 @@
reg = <0x38>;
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
};
rtc@6f {
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
index 87ca6ead4098..9cb464b65be1 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
@@ -442,6 +442,7 @@
reg = <0x38>;
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
};
};
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
index f5b763d39285..5e4da6d6fcff 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
@@ -360,6 +360,7 @@
reg = <0x38>;
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
};
};
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index 596866b0a0d2..a14872436c5e 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -370,6 +370,7 @@
reg = <0x38>;
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-source;
};
};
--
2.14.3
^ permalink raw reply related
* [PATCH 2/2] ARM: dts: am437x: make edt-ft5x06 a wakeup source for imx6 boards
From: Daniel Mack @ 2018-05-23 8:30 UTC (permalink / raw)
To: dmitry.torokhov, robh+dt, mark.rutland, shawnguo, kernel,
fabio.estevam
Cc: devicetree, Daniel Mack, linux-arm-kernel, linux-input
In-Reply-To: <20180523083013.7570-1-daniel@zonque.org>
The touchscreen driver no longer configures the device as wakeup source by
default. A "wakeup-source" property is needed.
Signed-off-by: Daniel Mack <daniel@zonque.org>
---
arch/arm/boot/dts/am437x-sk-evm.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts
index 4118802b7fea..f17ed89da06b 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -537,6 +537,8 @@
touchscreen-size-x = <480>;
touchscreen-size-y = <272>;
+
+ wakeup-source;
};
tlv320aic3106: tlv320aic3106@1b {
--
2.14.3
^ permalink raw reply related
* Re: [PATCH v3 5/6] spi: at91-usart: add driver for at91-usart as spi
From: Mark Brown @ 2018-05-23 8:30 UTC (permalink / raw)
To: Radu Pirea
Cc: devicetree, linux-serial, linux-kernel, linux-arm-kernel,
linux-spi, mark.rutland, robh+dt, lee.jones, gregkh, jslaby,
richard.genoud, alexandre.belloni, nicolas.ferre
In-Reply-To: <6a59e071-3159-4939-8535-6c7a9d491379@microchip.com>
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On Wed, May 23, 2018 at 11:10:28AM +0300, Radu Pirea wrote:
> On 05/17/2018 08:04 AM, Mark Brown wrote:
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * Driver for AT91 USART Controllers as SPI
> > > + *
> > > + * Copyright (C) 2018 Microchip Technology Inc.
> > Make the entire block a C++ comment so it looks more intentional rather
> > tha mixing C and C++.
> I know it's ugly, but SPDX license identifier must be in a separate comment
> block.
No, it doesn't - it just needs to be the first line of the file.
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^ permalink raw reply
* Re: [PATCH] arm64: dts: renesas: r8a77980: add SMP support
From: Simon Horman @ 2018-05-23 8:30 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Sergei Shtylyov, Catalin Marinas, Will Deacon,
Linux-Renesas, Rob Herring, Linux ARM
In-Reply-To: <CAMuHMdWepA=YbjtVN2iw7uXrWu62LRx1ymix_AUgp6NrOTUgpw@mail.gmail.com>
On Tue, May 22, 2018 at 11:49:36AM +0200, Geert Uytterhoeven wrote:
> On Tue, May 22, 2018 at 10:54 AM, Simon Horman <horms@verge.net.au> wrote:
> > On Sat, May 19, 2018 at 08:38:13PM +0300, Sergei Shtylyov wrote:
> >> On 05/17/2018 11:23 PM, Geert Uytterhoeven wrote:
> >>
> >> >> Add the device nodes for 3 more Cortex-A53 CPU cores; adjust the interrupt
> >> >> delivery masks for the ARM GIC and Architectured Timer.
> >> >>
> >> >> Based on the original (and large) patch by Vladimir Barinov.
> >> >>
> >> >> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> >> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >> >
> >> > Thanks for your patch!
> >> >
> >> >> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >> >> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >> >> @@ -30,6 +30,36 @@
> >> >> enable-method = "psci";
> >> >> };
> >> >>
> >> >> + a53_1: cpu@1 {
> >> >> + device_type = "cpu";
> >> >> + compatible = "arm,cortex-a53","arm,armv8";
> >> >
> >> > Please stop copying spaceless lists ;-)
> >>
> >> Oops! Simon, do I need to re-post?
> >
> > No, but Geert, are you otherwise ok with this patch?
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, I have applied the following:
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Subject: [PATCH] arm64: dts: renesas: r8a77980: add SMP support
Add the device nodes for 3 more Cortex-A53 CPU cores; adjust the interrupt
delivery masks for the ARM GIC and Architectured Timer.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
[simon: corrected whitespace]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 40 +++++++++++++++++++++++++++----
1 file changed, 35 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index 4c40f9f0ebc9..6d2b61d83caf 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -30,6 +30,36 @@
enable-method = "psci";
};
+ a53_1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <1>;
+ clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
+ power-domains = <&sysc R8A77980_PD_CA53_CPU1>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ a53_2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <2>;
+ clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
+ power-domains = <&sysc R8A77980_PD_CA53_CPU2>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
+ a53_3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <3>;
+ clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
+ power-domains = <&sysc R8A77980_PD_CA53_CPU3>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
L2_CA53: cache-controller {
compatible = "cache";
power-domains = <&sysc R8A77980_PD_CA53_SCU>;
@@ -408,7 +438,7 @@
<0x0 0xf1020000 0 0x20000>,
<0x0 0xf1040000 0 0x20000>,
<0x0 0xf1060000 0 0x20000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
@@ -424,13 +454,13 @@
timer {
compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>;
};
};
--
2.11.0
^ permalink raw reply related
* Re: [PATCH v2 1/5] dt-bindings: pinctrl: Add gpio bindings for Actions S900 SoC
From: Linus Walleij @ 2018-05-23 8:33 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Rob Herring, Andreas Färber, liuwei, mp-cs, 96boards,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andy Shevchenko, Daniel Thompson, Amit Kucheria, Linux ARM,
open list:GPIO SUBSYSTEM, linux-kernel@vger.kernel.org, hzhang,
bdong, Mani Sadhasivam
In-Reply-To: <20180520051736.4842-2-manivannan.sadhasivam@linaro.org>
On Sun, May 20, 2018 at 7:17 AM, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
> Add gpio bindings for Actions Semi S900 SoC.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Patch applied with Rob's review tag.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v2 2/5] arm64: dts: actions: Add gpio properties to pinctrl node for S900
From: Linus Walleij @ 2018-05-23 8:34 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Rob Herring, Andreas Färber, liuwei, mp-cs, 96boards,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andy Shevchenko, Daniel Thompson, Amit Kucheria, Linux ARM,
open list:GPIO SUBSYSTEM, linux-kernel@vger.kernel.org, hzhang,
bdong, Mani Sadhasivam
In-Reply-To: <20180520051736.4842-3-manivannan.sadhasivam@linaro.org>
On Sun, May 20, 2018 at 7:17 AM, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
> Add gpio properties to pinctrl node for Actions Semi S900 SoC.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v5 1/3] ARM: dts: tegra: Remove skeleton.dtsi and fix DTC warnings for /memory
From: Krzysztof Kozlowski @ 2018-05-23 8:34 UTC (permalink / raw)
To: Stefan Agner
Cc: Rob Herring, Mark Rutland, Thierry Reding, Jonathan Hunter,
devicetree, linux-tegra, linux-kernel, Marcel Ziswiler,
Lucas Stach
In-Reply-To: <f762464c796fa1976c1ec6fde6869add@agner.ch>
On Wed, May 23, 2018 at 10:22 AM, Stefan Agner <stefan@agner.ch> wrote:
> On 23.05.2018 09:05, Krzysztof Kozlowski wrote:
>> On Thu, May 17, 2018 at 1:39 PM, Stefan Agner <stefan@agner.ch> wrote:
>>> On 17.05.2018 09:45, Krzysztof Kozlowski wrote:
>>> Could we not add
>>>
>>> memory { device_type = "memory"; };
>>>
>>> in the SoC level device trees?
>>>
>>> This would save device_type in all other instances.
>>>
>>> That is also how it is done in other places, e.g.
>>> arch/arm/boot/dts/imx6qdl.dtsi
>>
>> Not really because the unit address will not match between different
>> boards. The imx6qdl, as I see, has the same issue:
>> - imx6qdl.dtsi defines "memory" node
>> - imx6dl-apf6dev.dts includes the previous and defines "memory@10000000"
>>
>> This is wrong - two memory nodes.
>>
>
> Hm I see. We could add
>
> memory@0 { device_type = "memory"; };
>
> Since the reg property is specified in the board level device tree it
> would be still fine?
>
> Or probably better to provide a complete spec with length zero:
>
> memory@0 {
> device_type = "memory";
> reg = <0x0 0x0>;
> };
>
> Even some boards do that and assume that boot loader will fill it
> correctly, so that should be fine.
That could be the solution although tegra30-apalis.dtsi is a problem
here. For Tegra 114, 124 and 20 it would work fine - all boards from
given SoC have the same address of memory (0x0 or 0x80000000). However
for Tegra30 the Apalis did not have any memory reg before so I am not
sure what should be used. I added 0x0. The other Tegra30 boards have
memory@80000000.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 3/5] arm64: dts: actions: Add gpio line names to Bubblegum-96 board
From: Linus Walleij @ 2018-05-23 8:34 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Rob Herring, Andreas Färber, liuwei, mp-cs, 96boards,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andy Shevchenko, Daniel Thompson, Amit Kucheria, Linux ARM,
open list:GPIO SUBSYSTEM, linux-kernel@vger.kernel.org, hzhang,
bdong, Mani Sadhasivam
In-Reply-To: <20180520051736.4842-4-manivannan.sadhasivam@linaro.org>
On Sun, May 20, 2018 at 7:17 AM, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
> Add gpio line names to Actions Semi S900 based Bubblegum-96 board.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v2 4/5] pinctrl: actions: Add gpio support for Actions S900 SoC
From: Linus Walleij @ 2018-05-23 8:36 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Rob Herring, Andreas Färber, liuwei, mp-cs, 96boards,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andy Shevchenko, Daniel Thompson, Amit Kucheria, Linux ARM,
open list:GPIO SUBSYSTEM, linux-kernel@vger.kernel.org, hzhang,
bdong, Mani Sadhasivam
In-Reply-To: <20180520051736.4842-5-manivannan.sadhasivam@linaro.org>
On Sun, May 20, 2018 at 7:17 AM, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
> Add gpio support to pinctrl driver for Actions Semi S900 SoC.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Patch applied for v4.18 so we get some rotation in linux-next!
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH/RFC] ARM: dts: r8a7791: Move enable-method to CPU nodes
From: Simon Horman @ 2018-05-23 8:37 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Mark Rutland, devicetree, Lorenzo Pieralisi, Stephen Boyd,
Magnus Damm, linux-kernel, linux-renesas-soc, Rob Herring,
linux-arm-kernel
In-Reply-To: <1526995765-29693-1-git-send-email-geert+renesas@glider.be>
On Tue, May 22, 2018 at 03:29:25PM +0200, Geert Uytterhoeven wrote:
> According to Documentation/devicetree/bindings/arm/cpus.txt, the
> "enable-method" property should be a property of the individual CPU
> nodes, not of the parent "cpus" node. However, on R-Car M2-W (and on
> several other arm32 SoCs), the property is tied to the "cpus" node
> instead.
>
> Secondary CPU bringup and CPU hot (un)plug work regardless, as
> arm_dt_init_cpu_maps() falls back to looking in the "cpus" node.
>
> The cpuidle code does not have such a fallback, so it does not detect
> the enable-method. Note that cpuidle does not support the
> "renesas,apmu" enable-method yet, so for now this does not make any
> difference.
Is the implication that if we keep the current binding for cpu nodes
then at some point we will need to update the cpuidle binding?
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> Arm64 and powerpc do not have such a fallback, but SH has, like arm32.
>
> This is marked RFC, as the alternative is to update the DT bindings to
> keep the status quo.
> ---
> arch/arm/boot/dts/r8a7791.dtsi | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
> index d568bd22d6cbd855..b214cb8f52e47109 100644
> --- a/arch/arm/boot/dts/r8a7791.dtsi
> +++ b/arch/arm/boot/dts/r8a7791.dtsi
> @@ -71,7 +71,6 @@
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> - enable-method = "renesas,apmu";
>
> cpu0: cpu@0 {
> device_type = "cpu";
> @@ -83,6 +82,7 @@
> clock-latency = <300000>; /* 300 us */
> power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
> next-level-cache = <&L2_CA15>;
> + enable-method = "renesas,apmu";
>
> /* kHz - uV - OPPs unknown yet */
> operating-points = <1500000 1000000>,
> @@ -101,6 +101,7 @@
> clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
> power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
> next-level-cache = <&L2_CA15>;
> + enable-method = "renesas,apmu";
> };
>
> L2_CA15: cache-controller-0 {
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH v2 5/5] MAINTAINERS: Add Actions Semi S900 pinctrl entries
From: Linus Walleij @ 2018-05-23 8:40 UTC (permalink / raw)
To: Manivannan Sadhasivam, Andreas Färber
Cc: Rob Herring, liuwei, mp-cs, 96boards,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Andy Shevchenko, Daniel Thompson, Amit Kucheria, Linux ARM,
open list:GPIO SUBSYSTEM, linux-kernel@vger.kernel.org, hzhang,
bdong, Mani Sadhasivam
In-Reply-To: <20180520051736.4842-6-manivannan.sadhasivam@linaro.org>
On Sun, May 20, 2018 at 7:17 AM, Manivannan Sadhasivam
<manivannan.sadhasivam@linaro.org> wrote:
> Add S900 pinctrl entries under ARCH_ACTIONS
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Patch applied tentatively so we have some maintenance entry for this.
Andreas expressed concerns about the driver earlier, so he might want it
split from the platform parts and have a separate entry for the pinctrl+GPIO
so Manivannan can maintain that part, also it makes sense to list
Manivannan as comaintainer of ARCH_ACTIONS with this in.
Andreas: how would you like to proceed?
I understand that I was a bit pushy or even rude in my last message
about the maintenance of this platform and the code structure of
the pin control driver. I am sorry if it caused any bad feelings on your
side :( social conflicts give me the creeps, I just try my best. Maybe
my best isn't always what it should be.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 1/2] arm64: dts: renesas: r8a77980: add GEther support
From: Simon Horman @ 2018-05-23 8:41 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Catalin Marinas, Will Deacon, Linux-Renesas,
Rob Herring, Geert Uytterhoeven, Linux ARM
In-Reply-To: <bdbfd13e-cf0c-e19a-b76f-5e8e024dca26@cogentembedded.com>
On Tue, May 22, 2018 at 06:44:59PM +0300, Sergei Shtylyov wrote:
> On 05/22/2018 02:48 PM, Geert Uytterhoeven wrote:
>
> >> Define the generic R8A77980 part of the GEther device node.
> >>
> >> Based on the original (and large) patch by Vladimir Barinov.
> >>
> >> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >
> > Thanks for your patch!
> >
> > With the below addressed:
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Thanks!
>
> >> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >> @@ -417,6 +417,17 @@
> >> dma-channels = <16>;
> >> };
> >>
> >> + gether: ethernet@e7400000 {
> >> + compatible = "renesas,gether-r8a77980";
> >> + reg = <0 0xe7400000 0 0x1000>;
> >> + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&cpg CPG_MOD 813>;
> >> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> >
> > resets = <&cpg 813>;
>
> As usual...
>
> >
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> + status = "disabled";
> >
> > Any default phy-mode needed?
>
> A default "phy-mode" IMO make sense when the MAC supports a single
> PHY interface mode. In this case, both RMII and RGMII are supported, so
> I coulsn't choose a default...
I would think making an arbitrary choice is better than no choice.
How does the driver behave in the absence of a default?
>
> >> + };
> >> +
> >> mmc0: mmc@ee140000 {
> >> compatible = "renesas,sdhi-r8a77980",
> >> "renesas,rcar-gen3-sdhi";
> >
> >
> > Gr{oetje,eeting}s,
> >
> > Geert
> >
>
^ permalink raw reply
* Re: [PATCH v4 2/3] dt-bindings: thermal: rcar-thermal: add R8A77995 support
From: Simon Horman @ 2018-05-23 8:42 UTC (permalink / raw)
To: Yoshihiro Kaneko
Cc: linux-renesas-soc, Zhang Rui, Eduardo Valentin, Rob Herring,
Magnus Damm, linux-pm, devicetree
In-Reply-To: <1526808379-3850-3-git-send-email-ykaneko0929@gmail.com>
On Sun, May 20, 2018 at 06:26:18PM +0900, Yoshihiro Kaneko wrote:
> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> Documentation/devicetree/bindings/thermal/rcar-thermal.txt | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
> index 349e635..67c563f 100644
> --- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
> @@ -3,7 +3,8 @@
> Required properties:
> - compatible : "renesas,thermal-<soctype>",
> "renesas,rcar-gen2-thermal" (with thermal-zone) or
> - "renesas,rcar-thermal" (without thermal-zone) as fallback.
> + "renesas,rcar-thermal" (without thermal-zone) as
> + fallback except R-Car D3.
> Examples with soctypes are:
> - "renesas,thermal-r8a73a4" (R-Mobile APE6)
> - "renesas,thermal-r8a7743" (RZ/G1M)
> @@ -12,13 +13,15 @@ Required properties:
> - "renesas,thermal-r8a7791" (R-Car M2-W)
> - "renesas,thermal-r8a7792" (R-Car V2H)
> - "renesas,thermal-r8a7793" (R-Car M2-N)
> + - "renesas,thermal-r8a77995" (R-Car D3)
> - reg : Address range of the thermal registers.
> The 1st reg will be recognized as common register
> if it has "interrupts".
>
> Option properties:
>
> -- interrupts : use interrupt
> +- interrupts : If present should contain 3 interrupts for
> + R-Car D3 or 1 interrupt otherwise.
>
> Example (non interrupt support):
>
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH v4 1/3] thermal: rcar_thermal: add r8a77995 support
From: Simon Horman @ 2018-05-23 8:43 UTC (permalink / raw)
To: Yoshihiro Kaneko
Cc: linux-renesas-soc, Zhang Rui, Eduardo Valentin, Rob Herring,
Magnus Damm, linux-pm, devicetree
In-Reply-To: <1526808379-3850-2-git-send-email-ykaneko0929@gmail.com>
On Sun, May 20, 2018 at 06:26:17PM +0900, Yoshihiro Kaneko wrote:
> Add support for R-Car D3 (r8a77995) thermal sensor.
>
> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
> Tested-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply
* Re: [PATCH v4 3/3] arm64: dts: renesas: r8a77995: add thermal device support
From: Simon Horman @ 2018-05-23 8:44 UTC (permalink / raw)
To: Yoshihiro Kaneko
Cc: linux-renesas-soc, Zhang Rui, Eduardo Valentin, Rob Herring,
Magnus Damm, linux-pm, devicetree
In-Reply-To: <1526808379-3850-4-git-send-email-ykaneko0929@gmail.com>
On Sun, May 20, 2018 at 06:26:19PM +0900, Yoshihiro Kaneko wrote:
> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied.
^ permalink raw reply
* RE: [PATCH v6] gpio: dwapb: Add support for 1 interrupt per port A GPIO
From: Phil Edworthy @ 2018-05-23 8:45 UTC (permalink / raw)
To: Linus Walleij
Cc: Andy Shevchenko, Hoan Tran, Mark Rutland, Rob Herring, Lee Jones,
Michel Pollet, open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas, linux-kernel@vger.kernel.org
In-Reply-To: <CACRpkdZAdhAn97iWPsym_K+A8iVwa3tRacpeEu=J6C=b+xAO6g@mail.gmail.com>
Hi Linus,
On 23 May 2018 09:29, Linus Walleij wrote:
> On Fri, May 11, 2018 at 10:31 AM, Phil Edworthy wrote:
>
> > The DesignWare GPIO IP can be configured for either 1 interrupt or 1
> > per GPIO in port A, but the driver currently only supports 1 interrupt.
> > See the DesignWare DW_apb_gpio Databook description of the
> > 'GPIO_INTR_IO' parameter.
> >
> > This change allows the driver to work with up to 32 interrupts, it
> > will get as many interrupts as specified in the DT 'interrupts' property.
> > It doesn't do anything clever with the different interrupts, it just
> > calls the same handler used for single interrupt hardware.
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > Acked-by: Lee Jones <lee.jones@linaro.org>
> > ---
> > One point to mention is that I have made it possible for users to have
> > unconnected interrupts by specifying holes in the list of interrupts.
> > This is done by supporting the interrupts-extended DT prop.
> > However, I have no use for this and had to hack some test case for this.
> > Perhaps the driver should support 1 interrupt or all GPIOa as interrupts?
> >
> > v6:
> > - Treat DT and ACPI the same as much as possible. Note that we can't use
> > platform_get_irq() to get the DT interrupts as they are in the port
> > sub-node and hence do not have an associated platform device.
>
> I already applied this patch in some version, can you check what is in my
> devel branch and send incremental patches on top if something needs
> changing?
> https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-
> gpio.git/commit/?h=devel&id=e6ca26abd37606ba4864f20c85d3fe4a2173b93f
>
> Sorry for not knowing by heart what was applied or when, it's just too much
> for me sometimes.
No problem, I'll send a patch with the incremental changes.
Thanks
Phil
^ permalink raw reply
* Re: [PATCH v7 3/5] soc: rockchip: split rockchip_typec_phy struct to separate header
From: Enric Balletbo Serra @ 2018-05-23 8:48 UTC (permalink / raw)
To: Lin Huang
Cc: devicetree@vger.kernel.org, David Airlie, linux-kernel,
Brian Norris, Doug Anderson, dri-devel, Kishon Vijay Abraham I,
open list:ARM/Rockchip SoC..., Rob Herring, Chris Zhong,
daniel.vetter, Linux ARM
In-Reply-To: <1527061353-16902-3-git-send-email-hl@rock-chips.com>
2018-05-23 9:42 GMT+02:00 Lin Huang <hl@rock-chips.com>:
> we may use rockchip_phy_typec struct in other driver, so split
> it to separate header.
>
> Signed-off-by: Lin Huang <hl@rock-chips.com>
> ---
> Changes in v2:
> - None
> Changes in v3:
> - None
> Changes in v4:
> - None
> Changes in v5:
> - None
> Changes in v6:
> - new patch here
> Changes in v7:
> - move new element to next patch
>
> drivers/phy/rockchip/phy-rockchip-typec.c | 47 +-------------------------
> include/soc/rockchip/rockchip_phy_typec.h | 55 +++++++++++++++++++++++++++++++
> 2 files changed, 56 insertions(+), 46 deletions(-)
> create mode 100644 include/soc/rockchip/rockchip_phy_typec.h
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c
> index 76a4b58..795055f 100644
> --- a/drivers/phy/rockchip/phy-rockchip-typec.c
> +++ b/drivers/phy/rockchip/phy-rockchip-typec.c
> @@ -63,6 +63,7 @@
>
> #include <linux/mfd/syscon.h>
> #include <linux/phy/phy.h>
> +#include <soc/rockchip/rockchip_phy_typec.h>
>
> #define CMN_SSM_BANDGAP (0x21 << 2)
> #define CMN_SSM_BIAS (0x22 << 2)
> @@ -349,52 +350,6 @@
> #define MODE_DFP_USB BIT(1)
> #define MODE_DFP_DP BIT(2)
>
> -struct usb3phy_reg {
> - u32 offset;
> - u32 enable_bit;
> - u32 write_enable;
> -};
> -
> -/**
> - * struct rockchip_usb3phy_port_cfg: usb3-phy port configuration.
> - * @reg: the base address for usb3-phy config.
> - * @typec_conn_dir: the register of type-c connector direction.
> - * @usb3tousb2_en: the register of type-c force usb2 to usb2 enable.
> - * @external_psm: the register of type-c phy external psm clock.
> - * @pipe_status: the register of type-c phy pipe status.
> - * @usb3_host_disable: the register of type-c usb3 host disable.
> - * @usb3_host_port: the register of type-c usb3 host port.
> - * @uphy_dp_sel: the register of type-c phy DP select control.
> - */
> -struct rockchip_usb3phy_port_cfg {
> - unsigned int reg;
> - struct usb3phy_reg typec_conn_dir;
> - struct usb3phy_reg usb3tousb2_en;
> - struct usb3phy_reg external_psm;
> - struct usb3phy_reg pipe_status;
> - struct usb3phy_reg usb3_host_disable;
> - struct usb3phy_reg usb3_host_port;
> - struct usb3phy_reg uphy_dp_sel;
> -};
> -
> -struct rockchip_typec_phy {
> - struct device *dev;
> - void __iomem *base;
> - struct extcon_dev *extcon;
> - struct regmap *grf_regs;
> - struct clk *clk_core;
> - struct clk *clk_ref;
> - struct reset_control *uphy_rst;
> - struct reset_control *pipe_rst;
> - struct reset_control *tcphy_rst;
> - const struct rockchip_usb3phy_port_cfg *port_cfgs;
> - /* mutex to protect access to individual PHYs */
> - struct mutex lock;
> -
> - bool flip;
> - u8 mode;
> -};
> -
> struct phy_reg {
> u16 value;
> u32 addr;
> diff --git a/include/soc/rockchip/rockchip_phy_typec.h b/include/soc/rockchip/rockchip_phy_typec.h
> new file mode 100644
> index 0000000..4afe039
> --- /dev/null
> +++ b/include/soc/rockchip/rockchip_phy_typec.h
> @@ -0,0 +1,55 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
> + * Author: Lin Huang <hl@rock-chips.com>
> + */
> +
> +#ifndef __SOC_ROCKCHIP_PHY_TYPEC_H
> +#define __SOC_ROCKCHIP_PHY_TYPEC_H
> +
> +struct usb3phy_reg {
> + u32 offset;
> + u32 enable_bit;
> + u32 write_enable;
> +};
> +
> +/**
> + * struct rockchip_usb3phy_port_cfg: usb3-phy port configuration.
> + * @reg: the base address for usb3-phy config.
> + * @typec_conn_dir: the register of type-c connector direction.
> + * @usb3tousb2_en: the register of type-c force usb2 to usb2 enable.
> + * @external_psm: the register of type-c phy external psm clock.
> + * @pipe_status: the register of type-c phy pipe status.
> + * @usb3_host_disable: the register of type-c usb3 host disable.
> + * @usb3_host_port: the register of type-c usb3 host port.
> + * @uphy_dp_sel: the register of type-c phy DP select control.
> + */
> +struct rockchip_usb3phy_port_cfg {
> + unsigned int reg;
> + struct usb3phy_reg typec_conn_dir;
> + struct usb3phy_reg usb3tousb2_en;
> + struct usb3phy_reg external_psm;
> + struct usb3phy_reg pipe_status;
> + struct usb3phy_reg usb3_host_disable;
> + struct usb3phy_reg usb3_host_port;
> + struct usb3phy_reg uphy_dp_sel;
> +};
> +
> +struct rockchip_typec_phy {
> + struct device *dev;
> + void __iomem *base;
> + struct extcon_dev *extcon;
> + struct regmap *grf_regs;
> + struct clk *clk_core;
> + struct clk *clk_ref;
> + struct reset_control *uphy_rst;
> + struct reset_control *pipe_rst;
> + struct reset_control *tcphy_rst;
> + const struct rockchip_usb3phy_port_cfg *port_cfgs;
> + /* mutex to protect access to individual PHYs */
> + struct mutex lock;
> + bool flip;
> + u8 mode;
> +};
> +
> +#endif
> --
> 2.7.4
>
Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCH v7 4/5] phy: rockchip-typec: support variable phy config value
From: Enric Balletbo Serra @ 2018-05-23 8:50 UTC (permalink / raw)
To: Lin Huang
Cc: devicetree@vger.kernel.org, David Airlie, linux-kernel,
Brian Norris, Doug Anderson, dri-devel, Kishon Vijay Abraham I,
open list:ARM/Rockchip SoC..., Rob Herring, Chris Zhong,
daniel.vetter, Linux ARM
In-Reply-To: <1527061353-16902-4-git-send-email-hl@rock-chips.com>
2018-05-23 9:42 GMT+02:00 Lin Huang <hl@rock-chips.com>:
> the phy config values used to fix in dp firmware, but some boards
> need change these values to do training and get the better eye diagram
> result. So support that in phy driver.
>
> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
> Signed-off-by: Lin Huang <hl@rock-chips.com>
> ---
> Changes in v2:
> - update patch following Enric suggest
> Changes in v3:
> - delete need_software_training variable
> - add default phy config value, if dts do not define phy config value, use these value
> Changes in v4:
> - rename variable config to tcphy_default_config
> Changes in v5:
> - None
> Changes in v6:
> - split the header file to new patch
> Changes in v7:
> - add default case when check link rate
> - move struct rockchip_typec_phy new element to this patch
>
> drivers/phy/rockchip/phy-rockchip-typec.c | 263 ++++++++++++++++++++++++------
> include/soc/rockchip/rockchip_phy_typec.h | 8 +
> 2 files changed, 218 insertions(+), 53 deletions(-)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c
> index 795055f..69af90e 100644
> --- a/drivers/phy/rockchip/phy-rockchip-typec.c
> +++ b/drivers/phy/rockchip/phy-rockchip-typec.c
> @@ -324,21 +324,29 @@
> * clock 0: PLL 0 div 1
> * clock 1: PLL 1 div 2
> */
> -#define CLK_PLL_CONFIG 0X30
> +#define CLK_PLL1_DIV1 0x20
> +#define CLK_PLL1_DIV2 0x30
> #define CLK_PLL_MASK 0x33
>
> #define CMN_READY BIT(0)
>
> +#define DP_PLL_CLOCK_ENABLE_ACK BIT(3)
> #define DP_PLL_CLOCK_ENABLE BIT(2)
> +#define DP_PLL_ENABLE_ACK BIT(1)
> #define DP_PLL_ENABLE BIT(0)
> #define DP_PLL_DATA_RATE_RBR ((2 << 12) | (4 << 8))
> #define DP_PLL_DATA_RATE_HBR ((2 << 12) | (4 << 8))
> #define DP_PLL_DATA_RATE_HBR2 ((1 << 12) | (2 << 8))
> +#define DP_PLL_DATA_RATE_MASK 0xff00
>
> -#define DP_MODE_A0 BIT(4)
> -#define DP_MODE_A2 BIT(6)
> -#define DP_MODE_ENTER_A0 0xc101
> -#define DP_MODE_ENTER_A2 0xc104
> +#define DP_MODE_MASK 0xf
> +#define DP_MODE_ENTER_A0 BIT(0)
> +#define DP_MODE_ENTER_A2 BIT(2)
> +#define DP_MODE_ENTER_A3 BIT(3)
> +#define DP_MODE_A0_ACK BIT(4)
> +#define DP_MODE_A2_ACK BIT(6)
> +#define DP_MODE_A3_ACK BIT(7)
> +#define DP_LINK_RESET_DEASSERTED BIT(8)
>
> #define PHY_MODE_SET_TIMEOUT 100000
>
> @@ -350,6 +358,8 @@
> #define MODE_DFP_USB BIT(1)
> #define MODE_DFP_DP BIT(2)
>
> +#define DP_DEFAULT_RATE 162000
> +
> struct phy_reg {
> u16 value;
> u32 addr;
> @@ -372,15 +382,15 @@ struct phy_reg usb3_pll_cfg[] = {
> { 0x8, CMN_DIAG_PLL0_LF_PROG },
> };
>
> -struct phy_reg dp_pll_cfg[] = {
> +struct phy_reg dp_pll_rbr_cfg[] = {
> { 0xf0, CMN_PLL1_VCOCAL_INIT },
> { 0x18, CMN_PLL1_VCOCAL_ITER },
> { 0x30b9, CMN_PLL1_VCOCAL_START },
> - { 0x21c, CMN_PLL1_INTDIV },
> + { 0x87, CMN_PLL1_INTDIV },
> { 0, CMN_PLL1_FRACDIV },
> - { 0x5, CMN_PLL1_HIGH_THR },
> - { 0x35, CMN_PLL1_SS_CTRL1 },
> - { 0x7f1e, CMN_PLL1_SS_CTRL2 },
> + { 0x22, CMN_PLL1_HIGH_THR },
> + { 0x8000, CMN_PLL1_SS_CTRL1 },
> + { 0, CMN_PLL1_SS_CTRL2 },
> { 0x20, CMN_PLL1_DSM_DIAG },
> { 0, CMN_PLLSM1_USER_DEF_CTRL },
> { 0, CMN_DIAG_PLL1_OVRD },
> @@ -391,9 +401,52 @@ struct phy_reg dp_pll_cfg[] = {
> { 0x8, CMN_DIAG_PLL1_LF_PROG },
> { 0x100, CMN_DIAG_PLL1_PTATIS_TUNE1 },
> { 0x7, CMN_DIAG_PLL1_PTATIS_TUNE2 },
> - { 0x4, CMN_DIAG_PLL1_INCLK_CTRL },
> + { 0x1, CMN_DIAG_PLL1_INCLK_CTRL },
> };
>
> +struct phy_reg dp_pll_hbr_cfg[] = {
> + { 0xf0, CMN_PLL1_VCOCAL_INIT },
> + { 0x18, CMN_PLL1_VCOCAL_ITER },
> + { 0x30b4, CMN_PLL1_VCOCAL_START },
> + { 0xe1, CMN_PLL1_INTDIV },
> + { 0, CMN_PLL1_FRACDIV },
> + { 0x5, CMN_PLL1_HIGH_THR },
> + { 0x8000, CMN_PLL1_SS_CTRL1 },
> + { 0, CMN_PLL1_SS_CTRL2 },
> + { 0x20, CMN_PLL1_DSM_DIAG },
> + { 0x1000, CMN_PLLSM1_USER_DEF_CTRL },
> + { 0, CMN_DIAG_PLL1_OVRD },
> + { 0, CMN_DIAG_PLL1_FBH_OVRD },
> + { 0, CMN_DIAG_PLL1_FBL_OVRD },
> + { 0x7, CMN_DIAG_PLL1_V2I_TUNE },
> + { 0x45, CMN_DIAG_PLL1_CP_TUNE },
> + { 0x8, CMN_DIAG_PLL1_LF_PROG },
> + { 0x1, CMN_DIAG_PLL1_PTATIS_TUNE1 },
> + { 0x1, CMN_DIAG_PLL1_PTATIS_TUNE2 },
> + { 0x1, CMN_DIAG_PLL1_INCLK_CTRL },
> +};
> +
> +struct phy_reg dp_pll_hbr2_cfg[] = {
> + { 0xf0, CMN_PLL1_VCOCAL_INIT },
> + { 0x18, CMN_PLL1_VCOCAL_ITER },
> + { 0x30b4, CMN_PLL1_VCOCAL_START },
> + { 0xe1, CMN_PLL1_INTDIV },
> + { 0, CMN_PLL1_FRACDIV },
> + { 0x5, CMN_PLL1_HIGH_THR },
> + { 0x8000, CMN_PLL1_SS_CTRL1 },
> + { 0, CMN_PLL1_SS_CTRL2 },
> + { 0x20, CMN_PLL1_DSM_DIAG },
> + { 0x1000, CMN_PLLSM1_USER_DEF_CTRL },
> + { 0, CMN_DIAG_PLL1_OVRD },
> + { 0, CMN_DIAG_PLL1_FBH_OVRD },
> + { 0, CMN_DIAG_PLL1_FBL_OVRD },
> + { 0x7, CMN_DIAG_PLL1_V2I_TUNE },
> + { 0x45, CMN_DIAG_PLL1_CP_TUNE },
> + { 0x8, CMN_DIAG_PLL1_LF_PROG },
> + { 0x1, CMN_DIAG_PLL1_PTATIS_TUNE1 },
> + { 0x1, CMN_DIAG_PLL1_PTATIS_TUNE2 },
> + { 0x1, CMN_DIAG_PLL1_INCLK_CTRL },
> +};
> static const struct rockchip_usb3phy_port_cfg rk3399_usb3phy_port_cfgs[] = {
> {
> .reg = 0xff7c0000,
> @@ -418,6 +471,24 @@ static const struct rockchip_usb3phy_port_cfg rk3399_usb3phy_port_cfgs[] = {
> { /* sentinel */ }
> };
>
> +/* default phy config */
> +static const struct phy_config tcphy_default_config[3][4] = {
> + {{ .swing = 0x2a, .pe = 0x00 },
> + { .swing = 0x1f, .pe = 0x15 },
> + { .swing = 0x14, .pe = 0x22 },
> + { .swing = 0x02, .pe = 0x2b } },
> +
> + {{ .swing = 0x21, .pe = 0x00 },
> + { .swing = 0x12, .pe = 0x15 },
> + { .swing = 0x02, .pe = 0x22 },
> + { .swing = 0, .pe = 0 } },
> +
> + {{ .swing = 0x15, .pe = 0x00 },
> + { .swing = 0x00, .pe = 0x15 },
> + { .swing = 0, .pe = 0 },
> + { .swing = 0, .pe = 0 } },
> +};
> +
> static void tcphy_cfg_24m(struct rockchip_typec_phy *tcphy)
> {
> u32 i, rdata;
> @@ -439,7 +510,7 @@ static void tcphy_cfg_24m(struct rockchip_typec_phy *tcphy)
>
> rdata = readl(tcphy->base + CMN_DIAG_HSCLK_SEL);
> rdata &= ~CLK_PLL_MASK;
> - rdata |= CLK_PLL_CONFIG;
> + rdata |= CLK_PLL1_DIV2;
> writel(rdata, tcphy->base + CMN_DIAG_HSCLK_SEL);
> }
>
> @@ -453,17 +524,45 @@ static void tcphy_cfg_usb3_pll(struct rockchip_typec_phy *tcphy)
> tcphy->base + usb3_pll_cfg[i].addr);
> }
>
> -static void tcphy_cfg_dp_pll(struct rockchip_typec_phy *tcphy)
> +static void tcphy_cfg_dp_pll(struct rockchip_typec_phy *tcphy, int link_rate)
> {
> - u32 i;
> + struct phy_reg *phy_cfg;
> + u32 clk_ctrl;
> + u32 i, cfg_size, hsclk_sel;
> +
> + hsclk_sel = readl(tcphy->base + CMN_DIAG_HSCLK_SEL);
> + hsclk_sel &= ~CLK_PLL_MASK;
> +
> + switch (link_rate) {
> + case 540000:
> + clk_ctrl = DP_PLL_DATA_RATE_HBR2;
> + hsclk_sel |= CLK_PLL1_DIV1;
> + phy_cfg = dp_pll_hbr2_cfg;
> + cfg_size = ARRAY_SIZE(dp_pll_hbr2_cfg);
> + break;
> + case 270000:
> + clk_ctrl = DP_PLL_DATA_RATE_HBR;
> + hsclk_sel |= CLK_PLL1_DIV2;
> + phy_cfg = dp_pll_hbr_cfg;
> + cfg_size = ARRAY_SIZE(dp_pll_hbr_cfg);
> + break;
> + case 162000:
> + default:
> + clk_ctrl = DP_PLL_DATA_RATE_RBR;
> + hsclk_sel |= CLK_PLL1_DIV2;
> + phy_cfg = dp_pll_rbr_cfg;
> + cfg_size = ARRAY_SIZE(dp_pll_rbr_cfg);
> + break;
> + }
>
> - /* set the default mode to RBR */
> - writel(DP_PLL_CLOCK_ENABLE | DP_PLL_ENABLE | DP_PLL_DATA_RATE_RBR,
> - tcphy->base + DP_CLK_CTL);
> + clk_ctrl |= DP_PLL_CLOCK_ENABLE | DP_PLL_ENABLE;
> + writel(clk_ctrl, tcphy->base + DP_CLK_CTL);
> +
> + writel(hsclk_sel, tcphy->base + CMN_DIAG_HSCLK_SEL);
>
> /* load the configuration of PLL1 */
> - for (i = 0; i < ARRAY_SIZE(dp_pll_cfg); i++)
> - writel(dp_pll_cfg[i].value, tcphy->base + dp_pll_cfg[i].addr);
> + for (i = 0; i < cfg_size; i++)
> + writel(phy_cfg[i].value, tcphy->base + phy_cfg[i].addr);
> }
>
> static void tcphy_tx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane)
> @@ -490,9 +589,10 @@ static void tcphy_rx_usb3_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane)
> writel(0xfb, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane));
> }
>
> -static void tcphy_dp_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane)
> +static void tcphy_dp_cfg_lane(struct rockchip_typec_phy *tcphy, int link_rate,
> + u8 swing, u8 pre_emp, u32 lane)
> {
> - u16 rdata;
> + u16 val;
>
> writel(0xbefc, tcphy->base + XCVR_PSM_RCTRL(lane));
> writel(0x6799, tcphy->base + TX_PSC_A0(lane));
> @@ -500,25 +600,32 @@ static void tcphy_dp_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane)
> writel(0x98, tcphy->base + TX_PSC_A2(lane));
> writel(0x98, tcphy->base + TX_PSC_A3(lane));
>
> - writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_000(lane));
> - writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_001(lane));
> - writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_010(lane));
> - writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_011(lane));
> - writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_100(lane));
> - writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_101(lane));
> - writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_110(lane));
> - writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_111(lane));
> - writel(0, tcphy->base + TX_TXCC_CPOST_MULT_10(lane));
> - writel(0, tcphy->base + TX_TXCC_CPOST_MULT_01(lane));
> - writel(0, tcphy->base + TX_TXCC_CPOST_MULT_00(lane));
> - writel(0, tcphy->base + TX_TXCC_CPOST_MULT_11(lane));
> -
> - writel(0x128, tcphy->base + TX_TXCC_CAL_SCLR_MULT(lane));
> - writel(0x400, tcphy->base + TX_DIAG_TX_DRV(lane));
> -
> - rdata = readl(tcphy->base + XCVR_DIAG_PLLDRC_CTRL(lane));
> - rdata = (rdata & 0x8fff) | 0x6000;
> - writel(rdata, tcphy->base + XCVR_DIAG_PLLDRC_CTRL(lane));
> + writel(tcphy->config[swing][pre_emp].swing,
> + tcphy->base + TX_TXCC_MGNFS_MULT_000(lane));
> + writel(tcphy->config[swing][pre_emp].pe,
> + tcphy->base + TX_TXCC_CPOST_MULT_00(lane));
> +
> + if (swing == 2 && pre_emp == 0 && link_rate != 540000) {
> + writel(0x700, tcphy->base + TX_DIAG_TX_DRV(lane));
> + writel(0x13c, tcphy->base + TX_TXCC_CAL_SCLR_MULT(lane));
> + } else {
> + writel(0x128, tcphy->base + TX_TXCC_CAL_SCLR_MULT(lane));
> + writel(0x0400, tcphy->base + TX_DIAG_TX_DRV(lane));
> + }
> +
> + val = readl(tcphy->base + XCVR_DIAG_PLLDRC_CTRL(lane));
> + val = val & 0x8fff;
> + switch (link_rate) {
> + case 540000:
> + val |= (4 << 12);
> + break;
> + case 162000:
> + case 270000:
> + default:
> + val |= (6 << 12);
> + break;
> + }
> + writel(val, tcphy->base + XCVR_DIAG_PLLDRC_CTRL(lane));
> }
>
> static inline int property_enable(struct rockchip_typec_phy *tcphy,
> @@ -709,30 +816,33 @@ static int tcphy_phy_init(struct rockchip_typec_phy *tcphy, u8 mode)
> tcphy_cfg_24m(tcphy);
>
> if (mode == MODE_DFP_DP) {
> - tcphy_cfg_dp_pll(tcphy);
> + tcphy_cfg_dp_pll(tcphy, DP_DEFAULT_RATE);
> for (i = 0; i < 4; i++)
> - tcphy_dp_cfg_lane(tcphy, i);
> + tcphy_dp_cfg_lane(tcphy, DP_DEFAULT_RATE, 0, 0, i);
>
> writel(PIN_ASSIGN_C_E, tcphy->base + PMA_LANE_CFG);
> } else {
> tcphy_cfg_usb3_pll(tcphy);
> - tcphy_cfg_dp_pll(tcphy);
> + tcphy_cfg_dp_pll(tcphy, DP_DEFAULT_RATE);
> if (tcphy->flip) {
> tcphy_tx_usb3_cfg_lane(tcphy, 3);
> tcphy_rx_usb3_cfg_lane(tcphy, 2);
> - tcphy_dp_cfg_lane(tcphy, 0);
> - tcphy_dp_cfg_lane(tcphy, 1);
> + tcphy_dp_cfg_lane(tcphy, DP_DEFAULT_RATE, 0, 0, 0);
> + tcphy_dp_cfg_lane(tcphy, DP_DEFAULT_RATE, 0, 0, 1);
> } else {
> tcphy_tx_usb3_cfg_lane(tcphy, 0);
> tcphy_rx_usb3_cfg_lane(tcphy, 1);
> - tcphy_dp_cfg_lane(tcphy, 2);
> - tcphy_dp_cfg_lane(tcphy, 3);
> + tcphy_dp_cfg_lane(tcphy, DP_DEFAULT_RATE, 0, 0, 2);
> + tcphy_dp_cfg_lane(tcphy, DP_DEFAULT_RATE, 0, 0, 3);
> }
>
> writel(PIN_ASSIGN_D_F, tcphy->base + PMA_LANE_CFG);
> }
>
> - writel(DP_MODE_ENTER_A2, tcphy->base + DP_MODE_CTL);
> + val = readl(tcphy->base + DP_MODE_CTL);
> + val &= ~DP_MODE_MASK;
> + val |= DP_MODE_ENTER_A2 | DP_LINK_RESET_DEASSERTED;
> + writel(val, tcphy->base + DP_MODE_CTL);
>
> reset_control_deassert(tcphy->uphy_rst);
>
> @@ -945,7 +1055,7 @@ static int rockchip_dp_phy_power_on(struct phy *phy)
> property_enable(tcphy, &cfg->uphy_dp_sel, 1);
>
> ret = readx_poll_timeout(readl, tcphy->base + DP_MODE_CTL,
> - val, val & DP_MODE_A2, 1000,
> + val, val & DP_MODE_A2_ACK, 1000,
> PHY_MODE_SET_TIMEOUT);
> if (ret < 0) {
> dev_err(tcphy->dev, "failed to wait TCPHY enter A2\n");
> @@ -954,13 +1064,19 @@ static int rockchip_dp_phy_power_on(struct phy *phy)
>
> tcphy_dp_aux_calibration(tcphy);
>
> - writel(DP_MODE_ENTER_A0, tcphy->base + DP_MODE_CTL);
> + /* enter A0 mode */
> + val = readl(tcphy->base + DP_MODE_CTL);
> + val &= ~DP_MODE_MASK;
> + val |= DP_MODE_ENTER_A0;
> + writel(val, tcphy->base + DP_MODE_CTL);
>
> ret = readx_poll_timeout(readl, tcphy->base + DP_MODE_CTL,
> - val, val & DP_MODE_A0, 1000,
> + val, val & DP_MODE_A0_ACK, 1000,
> PHY_MODE_SET_TIMEOUT);
> if (ret < 0) {
> - writel(DP_MODE_ENTER_A2, tcphy->base + DP_MODE_CTL);
> + val &= ~DP_MODE_MASK;
> + val |= DP_MODE_ENTER_A2;
> + writel(val, tcphy->base + DP_MODE_CTL);
> dev_err(tcphy->dev, "failed to wait TCPHY enter A0\n");
> goto power_on_finish;
> }
> @@ -978,6 +1094,7 @@ static int rockchip_dp_phy_power_on(struct phy *phy)
> static int rockchip_dp_phy_power_off(struct phy *phy)
> {
> struct rockchip_typec_phy *tcphy = phy_get_drvdata(phy);
> + u32 val;
>
> mutex_lock(&tcphy->lock);
>
> @@ -986,7 +1103,10 @@ static int rockchip_dp_phy_power_off(struct phy *phy)
>
> tcphy->mode &= ~MODE_DFP_DP;
>
> - writel(DP_MODE_ENTER_A2, tcphy->base + DP_MODE_CTL);
> + val = readl(tcphy->base + DP_MODE_CTL);
> + val &= ~DP_MODE_MASK;
> + val |= DP_MODE_ENTER_A2;
> + writel(val, tcphy->base + DP_MODE_CTL);
>
> if (tcphy->mode == MODE_DISCONNECT)
> tcphy_phy_deinit(tcphy);
> @@ -1002,9 +1122,35 @@ static const struct phy_ops rockchip_dp_phy_ops = {
> .owner = THIS_MODULE,
> };
>
> +static int typec_dp_phy_config(struct phy *phy, int link_rate,
> + int lanes, u8 swing, u8 pre_emp)
> +{
> + struct rockchip_typec_phy *tcphy = phy_get_drvdata(phy);
> + u8 i;
> +
> + tcphy_cfg_dp_pll(tcphy, link_rate);
> +
> + if (tcphy->mode == MODE_DFP_DP) {
> + for (i = 0; i < 4; i++)
> + tcphy_dp_cfg_lane(tcphy, link_rate, swing, pre_emp, i);
> + } else {
> + if (tcphy->flip) {
> + tcphy_dp_cfg_lane(tcphy, link_rate, swing, pre_emp, 0);
> + tcphy_dp_cfg_lane(tcphy, link_rate, swing, pre_emp, 1);
> + } else {
> + tcphy_dp_cfg_lane(tcphy, link_rate, swing, pre_emp, 2);
> + tcphy_dp_cfg_lane(tcphy, link_rate, swing, pre_emp, 3);
> + }
> + }
> +
> + return 0;
> +}
> +
> static int tcphy_parse_dt(struct rockchip_typec_phy *tcphy,
> struct device *dev)
> {
> + int ret;
> +
> tcphy->grf_regs = syscon_regmap_lookup_by_phandle(dev->of_node,
> "rockchip,grf");
> if (IS_ERR(tcphy->grf_regs)) {
> @@ -1042,6 +1188,16 @@ static int tcphy_parse_dt(struct rockchip_typec_phy *tcphy,
> return PTR_ERR(tcphy->tcphy_rst);
> }
>
> + /*
> + * check if phy_config pass from dts, if no,
> + * use default phy config value.
> + */
> + ret = of_property_read_u32_array(dev->of_node, "rockchip,phy-config",
> + (u32 *)tcphy->config, sizeof(tcphy->config) / sizeof(u32));
> + if (ret)
> + memcpy(tcphy->config, tcphy_default_config,
> + sizeof(tcphy->config));
> +
> return 0;
> }
>
> @@ -1126,6 +1282,7 @@ static int rockchip_typec_phy_probe(struct platform_device *pdev)
> }
> }
>
> + tcphy->typec_phy_config = typec_dp_phy_config;
> pm_runtime_enable(dev);
>
> for_each_available_child_of_node(np, child_np) {
> diff --git a/include/soc/rockchip/rockchip_phy_typec.h b/include/soc/rockchip/rockchip_phy_typec.h
> index 4afe039..8e45c4d 100644
> --- a/include/soc/rockchip/rockchip_phy_typec.h
> +++ b/include/soc/rockchip/rockchip_phy_typec.h
> @@ -35,6 +35,11 @@ struct rockchip_usb3phy_port_cfg {
> struct usb3phy_reg uphy_dp_sel;
> };
>
> +struct phy_config {
> + int swing;
> + int pe;
> +};
> +
> struct rockchip_typec_phy {
> struct device *dev;
> void __iomem *base;
> @@ -50,6 +55,9 @@ struct rockchip_typec_phy {
> struct mutex lock;
> bool flip;
> u8 mode;
> + struct phy_config config[3][4];
> + int (*typec_phy_config)(struct phy *phy, int link_rate,
> + int lanes, u8 swing, u8 pre_emp);
> };
>
> #endif
> --
> 2.7.4
>
Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCH/RFC] ARM: dts: r8a7791: Move enable-method to CPU nodes
From: Geert Uytterhoeven @ 2018-05-23 8:50 UTC (permalink / raw)
To: Simon Horman
Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, Mark Rutland,
Lorenzo Pieralisi, Stephen Boyd, Linux-Renesas, Linux ARM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List
In-Reply-To: <20180523083746.f4nkz4uhjwfgw7yz@verge.net.au>
Hi Simon,
On Wed, May 23, 2018 at 10:37 AM, Simon Horman <horms@verge.net.au> wrote:
> On Tue, May 22, 2018 at 03:29:25PM +0200, Geert Uytterhoeven wrote:
>> According to Documentation/devicetree/bindings/arm/cpus.txt, the
>> "enable-method" property should be a property of the individual CPU
>> nodes, not of the parent "cpus" node. However, on R-Car M2-W (and on
>> several other arm32 SoCs), the property is tied to the "cpus" node
>> instead.
>>
>> Secondary CPU bringup and CPU hot (un)plug work regardless, as
>> arm_dt_init_cpu_maps() falls back to looking in the "cpus" node.
>>
>> The cpuidle code does not have such a fallback, so it does not detect
>> the enable-method. Note that cpuidle does not support the
>> "renesas,apmu" enable-method yet, so for now this does not make any
>> difference.
>
> Is the implication that if we keep the current binding for cpu nodes
> then at some point we will need to update the cpuidle binding?
If we keep the current binding for cpu nodes, we indeed have to update
(common) Documentation/devicetree/bindings/arm/cpus.txt.
In addition, if we want to add renesas,apmu-based cpuidle support later,
we will have to update the common cpuidle code to look in /cpus, too.
>> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>> ---
>> Arm64 and powerpc do not have such a fallback, but SH has, like arm32.
>>
>> This is marked RFC, as the alternative is to update the DT bindings to
>> keep the status quo.
>> ---
>> arch/arm/boot/dts/r8a7791.dtsi | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
>> index d568bd22d6cbd855..b214cb8f52e47109 100644
>> --- a/arch/arm/boot/dts/r8a7791.dtsi
>> +++ b/arch/arm/boot/dts/r8a7791.dtsi
>> @@ -71,7 +71,6 @@
>> cpus {
>> #address-cells = <1>;
>> #size-cells = <0>;
>> - enable-method = "renesas,apmu";
>>
>> cpu0: cpu@0 {
>> device_type = "cpu";
>> @@ -83,6 +82,7 @@
>> clock-latency = <300000>; /* 300 us */
>> power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
>> next-level-cache = <&L2_CA15>;
>> + enable-method = "renesas,apmu";
>>
>> /* kHz - uV - OPPs unknown yet */
>> operating-points = <1500000 1000000>,
>> @@ -101,6 +101,7 @@
>> clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
>> power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
>> next-level-cache = <&L2_CA15>;
>> + enable-method = "renesas,apmu";
>> };
>>
>> L2_CA15: cache-controller-0 {
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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