* Re: [PATCH RFC 12/24] drm/lima: add GP related functions
From: Qiang Yu @ 2018-05-24 0:38 UTC (permalink / raw)
To: Marek Vasut
Cc: Simon Shields, devicetree, Connor Abbott, Neil Armstrong,
Andrei Paulau, dri-devel, Vasily Khoruzhick, Erico Nunes
In-Reply-To: <7b42a0c2-3737-327c-3829-0c322497b317@denx.de>
On Thu, May 24, 2018 at 1:12 AM, Marek Vasut <marex@denx.de> wrote:
> On 05/18/2018 11:28 AM, Qiang Yu wrote:
>> GP is a processor for OpenGL vertex shader
>> processing.
>>
>> Signed-off-by: Qiang Yu <yuq825@gmail.com>
>
> [...]
>
>> +int lima_gp_init(struct lima_ip *ip)
>> +{
>> + struct lima_device *dev = ip->dev;
>> + int err;
>> +
>> + lima_gp_print_version(ip);
>> +
>> + ip->data.async_reset = false;
>> + lima_gp_soft_reset_async(ip);
>> + err = lima_gp_soft_reset_async_wait(ip);
>> + if (err)
>> + return err;
>> +
>> + err = devm_request_irq(dev->dev, ip->irq, lima_gp_irq_handler, 0,
>> + lima_ip_name(ip), ip);
>
> IRQF_SHARED, since there are designs (like zynqmp) where there is only
> one IRQ line for the entire GPU.
Right, will add this flag.
Regards,
Qiang
>
>> + if (err) {
>> + dev_err(dev->dev, "gp %s fail to request irq\n",
>> + lima_ip_name(ip));
>> + return err;
>> + }
>> +
>> + return 0;
>> +}
>
>
> [...]
>
> --
> Best regards,
> Marek Vasut
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* [PATCH v8 2/2] drivers: soc: Add LLCC driver
From: Rishabh Bhatnagar @ 2018-05-24 0:35 UTC (permalink / raw)
To: linux-arm-kernel, linux-arm-msm, devicetree
Cc: linux-kernel, linux-arm, tsoni, ckadabi, evgreen, robh,
andy.shevchenko, Rishabh Bhatnagar
In-Reply-To: <1527122121-31452-1-git-send-email-rishabhb@codeaurora.org>
LLCC (Last Level Cache Controller) provides additional cache memory
in the system. LLCC is partitioned into multiple slices and each
slice gets its own priority, size, ID and other config parameters.
LLCC driver programs these parameters for each slice. Clients that
are assigned to use LLCC need to get information such size & ID of the
slice they get and activate or deactivate the slice as needed. LLCC driver
provides API for the clients to perform these operations.
Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
drivers/soc/qcom/Kconfig | 17 ++
drivers/soc/qcom/Makefile | 2 +
drivers/soc/qcom/llcc-sdm845.c | 94 +++++++++++
drivers/soc/qcom/llcc-slice.c | 335 +++++++++++++++++++++++++++++++++++++
include/linux/soc/qcom/llcc-qcom.h | 180 ++++++++++++++++++++
5 files changed, 628 insertions(+)
create mode 100644 drivers/soc/qcom/llcc-sdm845.c
create mode 100644 drivers/soc/qcom/llcc-slice.c
create mode 100644 include/linux/soc/qcom/llcc-qcom.h
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index e050eb8..0b550f9 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -21,6 +21,23 @@ config QCOM_GSBI
functions for connecting the underlying serial UART, SPI, and I2C
devices to the output pins.
+config QCOM_LLCC
+ tristate "Qualcomm Technologies, Inc. LLCC driver"
+ depends on ARCH_QCOM
+ help
+ Qualcomm Technologies, Inc. platform specific
+ Last Level Cache Controller(LLCC) driver. This provides interfaces
+ to clients that use the LLCC. Say yes here to enable LLCC slice
+ driver.
+
+config QCOM_SDM845_LLCC
+ tristate "Qualcomm Technologies, Inc. SDM845 LLCC driver"
+ depends on QCOM_LLCC
+ help
+ Say yes here to enable the LLCC driver for SDM845. This provides
+ data required to configure LLCC so that clients can start using the
+ LLCC slices.
+
config QCOM_MDT_LOADER
tristate
select QCOM_SCM
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index dcebf28..e16d6a2 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -12,3 +12,5 @@ obj-$(CONFIG_QCOM_SMEM_STATE) += smem_state.o
obj-$(CONFIG_QCOM_SMP2P) += smp2p.o
obj-$(CONFIG_QCOM_SMSM) += smsm.o
obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
+obj-$(CONFIG_QCOM_LLCC) += llcc-slice.o
+obj-$(CONFIG_QCOM_SDM845_LLCC) += llcc-sdm845.o
diff --git a/drivers/soc/qcom/llcc-sdm845.c b/drivers/soc/qcom/llcc-sdm845.c
new file mode 100644
index 0000000..2e1e4f0
--- /dev/null
+++ b/drivers/soc/qcom/llcc-sdm845.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/soc/qcom/llcc-qcom.h>
+
+/*
+ * SCT(System Cache Table) entry contains of the following members:
+ * usecase_id: Unique id for the client's use case
+ * slice_id: llcc slice id for each client
+ * max_cap: The maximum capacity of the cache slice provided in KB
+ * priority: Priority of the client used to select victim line for replacement
+ * fixed_size: Boolean indicating if the slice has a fixed capacity
+ * bonus_ways: Bonus ways are additional ways to be used for any slice,
+ * if client ends up using more than reserved cache ways. Bonus
+ * ways are allocated only if they are not reserved for some
+ * other client.
+ * res_ways: Reserved ways for the cache slice, the reserved ways cannot
+ * be used by any other client than the one its assigned to.
+ * cache_mode: Each slice operates as a cache, this controls the mode of the
+ * slice: normal or TCM(Tightly Coupled Memory)
+ * probe_target_ways: Determines what ways to probe for access hit. When
+ * configured to 1 only bonus and reserved ways are probed.
+ * When configured to 0 all ways in llcc are probed.
+ * dis_cap_alloc: Disable capacity based allocation for a client
+ * retain_on_pc: If this bit is set and client has maintained active vote
+ * then the ways assigned to this client are not flushed on power
+ * collapse.
+ * activate_on_init: Activate the slice immediately after the SCT is programmed
+ */
+#define SCT_ENTRY(uid, sid, mc, p, fs, bway, rway, cmod, ptw, dca, rp, a) \
+ { \
+ .usecase_id = uid, \
+ .slice_id = sid, \
+ .max_cap = mc, \
+ .priority = p, \
+ .fixed_size = fs, \
+ .bonus_ways = bway, \
+ .res_ways = rway, \
+ .cache_mode = cmod, \
+ .probe_target_ways = ptw, \
+ .dis_cap_alloc = dca, \
+ .retain_on_pc = rp, \
+ .activate_on_init = a, \
+ }
+
+static struct llcc_slice_config sdm845_data[] = {
+ SCT_ENTRY(LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1),
+ SCT_ENTRY(LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0),
+ SCT_ENTRY(LLCC_VIDSC1, 3, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0),
+ SCT_ENTRY(LLCC_ROTATOR, 4, 563, 2, 1, 0x0, 0x00e, 2, 0, 1, 1, 0),
+ SCT_ENTRY(LLCC_VOICE, 5, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
+ SCT_ENTRY(LLCC_AUDIO, 6, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
+ SCT_ENTRY(LLCC_MDMHPGRW, 7, 1024, 2, 0, 0xfc, 0xf00, 0, 0, 1, 1, 0),
+ SCT_ENTRY(LLCC_MDM, 8, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
+ SCT_ENTRY(LLCC_CMPT, 10, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
+ SCT_ENTRY(LLCC_GPUHTW, 11, 512, 1, 1, 0xc, 0x0, 0, 0, 1, 1, 0),
+ SCT_ENTRY(LLCC_GPU, 12, 2304, 1, 0, 0xff0, 0x2, 0, 0, 1, 1, 0),
+ SCT_ENTRY(LLCC_MMUHWT, 13, 256, 2, 0, 0x0, 0x1, 0, 0, 1, 0, 1),
+ SCT_ENTRY(LLCC_CMPTDMA, 15, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
+ SCT_ENTRY(LLCC_DISP, 16, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
+ SCT_ENTRY(LLCC_VIDFW, 17, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0),
+ SCT_ENTRY(LLCC_MDMHPFX, 20, 1024, 2, 1, 0x0, 0xf00, 0, 0, 1, 1, 0),
+ SCT_ENTRY(LLCC_MDMPNG, 21, 1024, 0, 1, 0x1e, 0x0, 0, 0, 1, 1, 0),
+ SCT_ENTRY(LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0),
+};
+
+static int sdm845_qcom_llcc_probe(struct platform_device *pdev)
+{
+ return qcom_llcc_probe(pdev, sdm845_data, ARRAY_SIZE(sdm845_data));
+}
+
+static const struct of_device_id sdm845_qcom_llcc_of_match[] = {
+ { .compatible = "qcom,sdm845-llcc", },
+ { }
+};
+
+static struct platform_driver sdm845_qcom_llcc_driver = {
+ .driver = {
+ .name = "sdm845-llcc",
+ .of_match_table = sdm845_qcom_llcc_of_match,
+ },
+ .probe = sdm845_qcom_llcc_probe,
+};
+module_platform_driver(sdm845_qcom_llcc_driver);
+
+MODULE_DESCRIPTION("QCOM sdm845 LLCC driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/soc/qcom/llcc-slice.c b/drivers/soc/qcom/llcc-slice.c
new file mode 100644
index 0000000..fcaad1a
--- /dev/null
+++ b/drivers/soc/qcom/llcc-slice.c
@@ -0,0 +1,335 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ *
+ */
+
+#include <linux/bitmap.h>
+#include <linux/bitops.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mutex.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/soc/qcom/llcc-qcom.h>
+
+#define ACTIVATE BIT(0)
+#define DEACTIVATE BIT(1)
+#define ACT_CTRL_OPCODE_ACTIVATE BIT(0)
+#define ACT_CTRL_OPCODE_DEACTIVATE BIT(1)
+#define ACT_CTRL_ACT_TRIG BIT(0)
+#define ACT_CTRL_OPCODE_SHIFT 0x01
+#define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02
+#define ATTR1_FIXED_SIZE_SHIFT 0x03
+#define ATTR1_PRIORITY_SHIFT 0x04
+#define ATTR1_MAX_CAP_SHIFT 0x10
+#define ATTR0_RES_WAYS_MASK GENMASK(11, 0)
+#define ATTR0_BONUS_WAYS_MASK GENMASK(27, 16)
+#define ATTR0_BONUS_WAYS_SHIFT 0x10
+#define LLCC_STATUS_READ_DELAY 100
+
+#define CACHE_LINE_SIZE_SHIFT 6
+
+#define LLCC_COMMON_STATUS0 0x0003000c
+#define LLCC_LB_CNT_MASK GENMASK(31, 28)
+#define LLCC_LB_CNT_SHIFT 28
+
+#define MAX_CAP_TO_BYTES(n) (n * SZ_1K)
+#define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K)
+#define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K)
+#define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n)
+#define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n)
+
+#define BANK_OFFSET_STRIDE 0x80000
+
+static struct llcc_drv_data *drv_data;
+
+static const struct regmap_config llcc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+ .fast_io = true,
+};
+
+/**
+ * llcc_slice_getd - get llcc slice descriptor
+ * @uid: usecase_id for the client
+ *
+ * A pointer to llcc slice descriptor will be returned on success and
+ * and error pointer is returned on failure
+ */
+struct llcc_slice_desc *llcc_slice_getd(u32 uid)
+{
+ const struct llcc_slice_config *cfg;
+ struct llcc_slice_desc *desc;
+ u32 sz, count;
+
+ cfg = drv_data->cfg;
+ sz = drv_data->cfg_size;
+
+ for (count = 0; cfg && count < sz; count++, cfg++)
+ if (cfg->usecase_id == uid)
+ break;
+
+ if (count == sz || !cfg)
+ return ERR_PTR(-ENODEV);
+
+ desc = kzalloc(sizeof(*desc), GFP_KERNEL);
+ if (!desc)
+ return ERR_PTR(-ENOMEM);
+
+ desc->slice_id = cfg->slice_id;
+ desc->slice_size = cfg->max_cap;
+
+ return desc;
+}
+EXPORT_SYMBOL_GPL(llcc_slice_getd);
+
+/**
+ * llcc_slice_putd - llcc slice descritpor
+ * @desc: Pointer to llcc slice descriptor
+ */
+void llcc_slice_putd(struct llcc_slice_desc *desc)
+{
+ kfree(desc);
+}
+EXPORT_SYMBOL_GPL(llcc_slice_putd);
+
+static int llcc_update_act_ctrl(u32 sid,
+ u32 act_ctrl_reg_val, u32 status)
+{
+ u32 act_ctrl_reg;
+ u32 status_reg;
+ u32 slice_status;
+ int ret;
+
+ act_ctrl_reg = drv_data->bcast_off + LLCC_TRP_ACT_CTRLn(sid);
+ status_reg = drv_data->bcast_off + LLCC_TRP_STATUSn(sid);
+
+ /* Set the ACTIVE trigger */
+ act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG;
+ ret = regmap_write(drv_data->regmap, act_ctrl_reg, act_ctrl_reg_val);
+ if (ret)
+ return ret;
+
+ /* Clear the ACTIVE trigger */
+ act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG;
+ ret = regmap_write(drv_data->regmap, act_ctrl_reg, act_ctrl_reg_val);
+ if (ret)
+ return ret;
+
+ ret = regmap_read_poll_timeout(drv_data->regmap, status_reg,
+ slice_status, !(slice_status & status),
+ 0, LLCC_STATUS_READ_DELAY);
+ return ret;
+}
+
+/**
+ * llcc_slice_activate - Activate the llcc slice
+ * @desc: Pointer to llcc slice descriptor
+ *
+ * A value of zero will be returned on success and a negative errno will
+ * be returned in error cases
+ */
+int llcc_slice_activate(struct llcc_slice_desc *desc)
+{
+ int ret;
+ u32 act_ctrl_val;
+
+ mutex_lock(&drv_data->lock);
+ if (test_bit(desc->slice_id, drv_data->bitmap)) {
+ mutex_unlock(&drv_data->lock);
+ return 0;
+ }
+
+ act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT;
+
+ ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
+ DEACTIVATE);
+ if (ret) {
+ mutex_unlock(&drv_data->lock);
+ return ret;
+ }
+
+ __set_bit(desc->slice_id, drv_data->bitmap);
+ mutex_unlock(&drv_data->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(llcc_slice_activate);
+
+/**
+ * llcc_slice_deactivate - Deactivate the llcc slice
+ * @desc: Pointer to llcc slice descriptor
+ *
+ * A value of zero will be returned on success and a negative errno will
+ * be returned in error cases
+ */
+int llcc_slice_deactivate(struct llcc_slice_desc *desc)
+{
+ u32 act_ctrl_val;
+ int ret;
+
+ mutex_lock(&drv_data->lock);
+ if (!test_bit(desc->slice_id, drv_data->bitmap)) {
+ mutex_unlock(&drv_data->lock);
+ return 0;
+ }
+ act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT;
+
+ ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val,
+ ACTIVATE);
+ if (ret) {
+ mutex_unlock(&drv_data->lock);
+ return ret;
+ }
+
+ __clear_bit(desc->slice_id, drv_data->bitmap);
+ mutex_unlock(&drv_data->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(llcc_slice_deactivate);
+
+/**
+ * llcc_get_slice_id - return the slice id
+ * @desc: Pointer to llcc slice descriptor
+ */
+int llcc_get_slice_id(struct llcc_slice_desc *desc)
+{
+ return desc->slice_id;
+}
+EXPORT_SYMBOL_GPL(llcc_get_slice_id);
+
+/**
+ * llcc_get_slice_size - return the slice id
+ * @desc: Pointer to llcc slice descriptor
+ */
+size_t llcc_get_slice_size(struct llcc_slice_desc *desc)
+{
+ return desc->slice_size;
+}
+EXPORT_SYMBOL_GPL(llcc_get_slice_size);
+
+static int qcom_llcc_cfg_program(struct platform_device *pdev)
+{
+ int i;
+ u32 attr1_cfg;
+ u32 attr0_cfg;
+ u32 attr1_val;
+ u32 attr0_val;
+ u32 max_cap_cacheline;
+ u32 sz;
+ int ret;
+ const struct llcc_slice_config *llcc_table;
+ struct llcc_slice_desc desc;
+ u32 bcast_off = drv_data->bcast_off;
+
+ sz = drv_data->cfg_size;
+ llcc_table = drv_data->cfg;
+
+ for (i = 0; i < sz; i++) {
+ attr1_cfg = bcast_off +
+ LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id);
+ attr0_cfg = bcast_off +
+ LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id);
+
+ attr1_val = llcc_table[i].cache_mode;
+ attr1_val |= llcc_table[i].probe_target_ways <<
+ ATTR1_PROBE_TARGET_WAYS_SHIFT;
+ attr1_val |= llcc_table[i].fixed_size <<
+ ATTR1_FIXED_SIZE_SHIFT;
+ attr1_val |= llcc_table[i].priority <<
+ ATTR1_PRIORITY_SHIFT;
+
+ max_cap_cacheline = MAX_CAP_TO_BYTES(llcc_table[i].max_cap);
+
+ /* LLCC instances can vary for each target.
+ * The SW writes to broadcast register which gets propagated
+ * to each llcc instace (llcc0,.. llccN).
+ * Since the size of the memory is divided equally amongst the
+ * llcc instances, we need to configure the max cap accordingly.
+ */
+ max_cap_cacheline = max_cap_cacheline / drv_data->num_banks;
+ max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT;
+ attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT;
+
+ attr0_val = llcc_table[i].res_ways & ATTR0_RES_WAYS_MASK;
+ attr0_val |= llcc_table[i].bonus_ways << ATTR0_BONUS_WAYS_SHIFT;
+
+ ret = regmap_write(drv_data->regmap, attr1_cfg, attr1_val);
+ if (ret)
+ return ret;
+ ret = regmap_write(drv_data->regmap, attr0_cfg, attr0_val);
+ if (ret)
+ return ret;
+ if (llcc_table[i].activate_on_init) {
+ desc.slice_id = llcc_table[i].slice_id;
+ ret = llcc_slice_activate(&desc);
+ }
+ }
+ return ret;
+}
+
+int qcom_llcc_probe(struct platform_device *pdev,
+ const struct llcc_slice_config *llcc_cfg, u32 sz)
+{
+ u32 num_banks;
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ void __iomem *base;
+ int ret, i;
+
+ drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
+ if (!drv_data)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ drv_data->regmap = devm_regmap_init_mmio(dev, base,
+ &llcc_regmap_config);
+ if (IS_ERR(drv_data->regmap))
+ return PTR_ERR(drv_data->regmap);
+
+ ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0,
+ &num_banks);
+ if (ret)
+ return ret;
+
+ num_banks &= LLCC_LB_CNT_MASK;
+ num_banks >>= LLCC_LB_CNT_SHIFT;
+ drv_data->num_banks = num_banks;
+
+ for (i = 0; i < sz; i++)
+ if (llcc_cfg[i].slice_id > drv_data->max_slices)
+ drv_data->max_slices = llcc_cfg[i].slice_id;
+
+ drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32),
+ GFP_KERNEL);
+ if (!drv_data->offsets)
+ return -ENOMEM;
+
+ for (i = 0; i < num_banks; i++)
+ drv_data->offsets[i] = i * BANK_OFFSET_STRIDE;
+
+ drv_data->bcast_off = num_banks * BANK_OFFSET_STRIDE;
+
+ drv_data->bitmap = devm_kcalloc(dev,
+ BITS_TO_LONGS(drv_data->max_slices), sizeof(unsigned long),
+ GFP_KERNEL);
+ if (!drv_data->bitmap)
+ return -ENOMEM;
+
+ drv_data->cfg = llcc_cfg;
+ drv_data->cfg_size = sz;
+ mutex_init(&drv_data->lock);
+ platform_set_drvdata(pdev, drv_data);
+
+ return qcom_llcc_cfg_program(pdev);
+}
+EXPORT_SYMBOL_GPL(qcom_llcc_probe);
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
new file mode 100644
index 0000000..7e3b9c6
--- /dev/null
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -0,0 +1,180 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
+ *
+ */
+
+#include <linux/platform_device.h>
+#ifndef __LLCC_QCOM__
+#define __LLCC_QCOM__
+
+#define LLCC_CPUSS 1
+#define LLCC_VIDSC0 2
+#define LLCC_VIDSC1 3
+#define LLCC_ROTATOR 4
+#define LLCC_VOICE 5
+#define LLCC_AUDIO 6
+#define LLCC_MDMHPGRW 7
+#define LLCC_MDM 8
+#define LLCC_CMPT 10
+#define LLCC_GPUHTW 11
+#define LLCC_GPU 12
+#define LLCC_MMUHWT 13
+#define LLCC_CMPTDMA 15
+#define LLCC_DISP 16
+#define LLCC_VIDFW 17
+#define LLCC_MDMHPFX 20
+#define LLCC_MDMPNG 21
+#define LLCC_AUDHW 22
+
+/**
+ * llcc_slice_desc - Cache slice descriptor
+ * @slice_id: llcc slice id
+ * @slice_size: Size allocated for the llcc slice
+ */
+struct llcc_slice_desc {
+ u32 slice_id;
+ size_t slice_size;
+};
+
+/**
+ * llcc_slice_config - Data associated with the llcc slice
+ * @usecase_id: usecase id for which the llcc slice is used
+ * @slice_id: llcc slice id assigned to each slice
+ * @max_cap: maximum capacity of the llcc slice
+ * @priority: priority of the llcc slice
+ * @fixed_size: whether the llcc slice can grow beyond its size
+ * @bonus_ways: bonus ways associated with llcc slice
+ * @res_ways: reserved ways associated with llcc slice
+ * @cache_mode: mode of the llcc slice
+ * @probe_target_ways: Probe only reserved and bonus ways on a cache miss
+ * @dis_cap_alloc: Disable capacity based allocation
+ * @retain_on_pc: Retain through power collapse
+ * @activate_on_init: activate the slice on init
+ */
+struct llcc_slice_config {
+ u32 usecase_id;
+ u32 slice_id;
+ u32 max_cap;
+ u32 priority;
+ bool fixed_size;
+ u32 bonus_ways;
+ u32 res_ways;
+ u32 cache_mode;
+ u32 probe_target_ways;
+ bool dis_cap_alloc;
+ bool retain_on_pc;
+ bool activate_on_init;
+};
+
+/**
+ * llcc_drv_data - Data associated with the llcc driver
+ * @regmap: regmap associated with the llcc device
+ * @cfg: pointer to the data structure for slice configuration
+ * @lock: mutex associated with each slice
+ * @cfg_size: size of the config data table
+ * @max_slices: max slices as read from device tree
+ * @bcast_off: Offset of the broadcast bank
+ * @num_banks: Number of llcc banks
+ * @bitmap: Bit map to track the active slice ids
+ * @offsets: Pointer to the bank offsets array
+ */
+struct llcc_drv_data {
+ struct regmap *regmap;
+ const struct llcc_slice_config *cfg;
+ struct mutex lock;
+ u32 cfg_size;
+ u32 max_slices;
+ u32 bcast_off;
+ u32 num_banks;
+ unsigned long *bitmap;
+ u32 *offsets;
+};
+
+#if IS_ENABLED(CONFIG_QCOM_LLCC)
+/**
+ * llcc_slice_getd - get llcc slice descriptor
+ * @uid: usecase_id of the client
+ */
+struct llcc_slice_desc *llcc_slice_getd(u32 uid);
+
+/**
+ * llcc_slice_putd - llcc slice descritpor
+ * @desc: Pointer to llcc slice descriptor
+ */
+void llcc_slice_putd(struct llcc_slice_desc *desc);
+
+/**
+ * llcc_get_slice_id - get slice id
+ * @desc: Pointer to llcc slice descriptor
+ */
+int llcc_get_slice_id(struct llcc_slice_desc *desc);
+
+/**
+ * llcc_get_slice_size - llcc slice size
+ * @desc: Pointer to llcc slice descriptor
+ */
+size_t llcc_get_slice_size(struct llcc_slice_desc *desc);
+
+/**
+ * llcc_slice_activate - Activate the llcc slice
+ * @desc: Pointer to llcc slice descriptor
+ */
+int llcc_slice_activate(struct llcc_slice_desc *desc);
+
+/**
+ * llcc_slice_deactivate - Deactivate the llcc slice
+ * @desc: Pointer to llcc slice descriptor
+ */
+int llcc_slice_deactivate(struct llcc_slice_desc *desc);
+
+/**
+ * qcom_llcc_probe - program the sct table
+ * @pdev: platform device pointer
+ * @table: soc sct table
+ * @sz: Size of the config table
+ */
+int qcom_llcc_probe(struct platform_device *pdev,
+ const struct llcc_slice_config *table, u32 sz);
+#else
+static inline struct llcc_slice_desc *llcc_slice_getd(u32 uid)
+{
+ return NULL;
+}
+
+static inline void llcc_slice_putd(struct llcc_slice_desc *desc)
+{
+
+};
+
+static inline int llcc_get_slice_id(struct llcc_slice_desc *desc)
+{
+ return -EINVAL;
+}
+
+static inline size_t llcc_get_slice_size(struct llcc_slice_desc *desc)
+{
+ return 0;
+}
+static inline int llcc_slice_activate(struct llcc_slice_desc *desc)
+{
+ return -EINVAL;
+}
+
+static inline int llcc_slice_deactivate(struct llcc_slice_desc *desc)
+{
+ return -EINVAL;
+}
+static inline int qcom_llcc_probe(struct platform_device *pdev,
+ const struct llcc_slice_config *table, u32 sz)
+{
+ return -ENODEV;
+}
+
+static inline int qcom_llcc_remove(struct platform_device *pdev)
+{
+ return -ENODEV;
+}
+#endif
+
+#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH v8 1/2] dt-bindings: Documentation for qcom, llcc
From: Rishabh Bhatnagar @ 2018-05-24 0:35 UTC (permalink / raw)
To: linux-arm-kernel, linux-arm-msm, devicetree
Cc: linux-kernel, linux-arm, tsoni, ckadabi, evgreen, robh,
andy.shevchenko, Rishabh Bhatnagar
In-Reply-To: <1527122121-31452-1-git-send-email-rishabhb@codeaurora.org>
Documentation for last level cache controller device tree bindings,
client bindings usage examples.
Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
Signed-off-by: Rishabh Bhatnagar <rishabhb@codeaurora.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/arm/msm/qcom,llcc.txt | 26 ++++++++++++++++++++++
1 file changed, 26 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
new file mode 100644
index 0000000..5e85749
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
@@ -0,0 +1,26 @@
+== Introduction==
+
+LLCC (Last Level Cache Controller) provides last level of cache memory in SOC,
+that can be shared by multiple clients. Clients here are different cores in the
+SOC, the idea is to minimize the local caches at the clients and migrate to
+common pool of memory. Cache memory is divided into partitions called slices
+which are assigned to clients. Clients can query the slice details, activate
+and deactivate them.
+
+Properties:
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be "qcom,sdm845-llcc"
+
+- reg:
+ Usage: required
+ Value Type: <prop-encoded-array>
+ Definition: Start address and the the size of the register region.
+
+Example:
+
+ cache-controller@1100000 {
+ compatible = "qcom,sdm845-llcc";
+ reg = <0x1100000 0x250000>;
+ };
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH v8 0/2] SDM845 System Cache Driver
From: Rishabh Bhatnagar @ 2018-05-24 0:35 UTC (permalink / raw)
To: linux-arm-kernel, linux-arm-msm, devicetree
Cc: linux-kernel, linux-arm, tsoni, ckadabi, evgreen, robh,
andy.shevchenko, Rishabh Bhatnagar
This series implements system cache or LLCC(Last Level Cache Controller)
driver for SDM845 SOC. The purpose of the driver is to partition the
system cache and program the settings such as priortiy, lines to probe
while doing a look up in the system cache, low power related settings etc.
The partitions are called cache slices. Each cache slice is associated
with size and SCID(System Cache ID). The driver also provides API for
clients to query the cache slice details,activate and deactivate them.
The driver can be broadly classified into:
* SOC specific driver: llcc-sdm845.c: Cache partitioning and cache slice
properties for usecases on sdm845 that need to use system cache.
* API : llcc-slice.c: Exports APIs to clients to query cache slice details,
activate and deactivate cache slices.
Changes since v7:
* Change the DT node name to cache-controller.
* Use the module_platform_driver_macro
* Use GENMASK and SZ_* macros
* Correct indentation, and remove unnecessary assignemnts.
* Addresed all comments by Andy Schevchenko except the comment to ignore some
lines of code going over 80 characters.
Changes since v6:
* Remove the max-slices property from DT.
* Make client's slice_ids as macros.
* Unlock mutex while returning from function in case of error.
Changes since v5:
* Remove client information from DT.
* Make the llcc driver data as global.
* Check return value of llcc_update_act_ctrl function
* Change error returned from -EFAULT to -EINVAL
Changes since v4:
* Remove null pointer checks as per comments.
* Remove extra blank lines.
Changes since v3:
* Use the regmap_read_poll_timeout function
* Check for regmap read/write errors.
* Remove memory barrier after regmap write
* Derive memory bank offsets using stride macro variable
* Remove debug statements from code
* Remove the qcom_llcc_remove function
* Use if IS_ENABLED in place of ifdef for built-in module
* Change EXPORT_SYMBOL to EXPORT_SYMBOL_GPL
* Remove unnecessary free functions
* Change the variable names as per review comments
Changes since v2:
* Corrected the Makefile to fix compilation.
Changes since v1:
* Added Makefile and Kconfig.
Changes since v0:
* Removed the syscon and simple-mfd approach
* Updated the device tree nodes to mention LLCC as a single HW block
* Moved llcc bank offsets from device tree and handled the offset
in the driver.
ckadabi@codeaurora.org (2):
dt-bindings: Documentation for qcom, llcc
drivers: soc: Add LLCC driver
.../devicetree/bindings/arm/msm/qcom,llcc.txt | 26 ++
drivers/soc/qcom/Kconfig | 17 ++
drivers/soc/qcom/Makefile | 2 +
drivers/soc/qcom/llcc-sdm845.c | 94 ++++++
drivers/soc/qcom/llcc-slice.c | 335 +++++++++++++++++++++
include/linux/soc/qcom/llcc-qcom.h | 180 +++++++++++
6 files changed, 654 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
create mode 100644 drivers/soc/qcom/llcc-sdm845.c
create mode 100644 drivers/soc/qcom/llcc-slice.c
create mode 100644 include/linux/soc/qcom/llcc-qcom.h
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [PATCH RFC 00/24] Lima DRM driver
From: Qiang Yu @ 2018-05-24 0:31 UTC (permalink / raw)
To: Daniel Vetter
Cc: Simon Shields, devicetree, Connor Abbott, Marek Vasut,
Neil Armstrong, Andrei Paulau, dri-devel, Vasily Khoruzhick,
Christian König, Erico Nunes
In-Reply-To: <CAKMK7uFfnSLpcQ_MAbqkLfs8DyZS8BfiG5uuxgvynYc_Z7To_g@mail.gmail.com>
On Wed, May 23, 2018 at 11:44 PM, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Wed, May 23, 2018 at 3:52 PM, Qiang Yu <yuq825@gmail.com> wrote:
>> On Wed, May 23, 2018 at 5:29 PM, Christian König
>> <ckoenig.leichtzumerken@gmail.com> wrote:
>>> Am 18.05.2018 um 11:27 schrieb Qiang Yu:
>>>>
>>>> Kernel DRM driver for ARM Mali 400/450 GPUs.
>>>>
>>>> This implementation mainly take amdgpu DRM driver as reference.
>>>>
>>>> - Mali 4xx GPUs have two kinds of processors GP and PP. GP is for
>>>> OpenGL vertex shader processing and PP is for fragment shader
>>>> processing. Each processor has its own MMU so prcessors work in
>>>> virtual address space.
>>>> - There's only one GP but multiple PP (max 4 for mali 400 and 8
>>>> for mali 450) in the same mali 4xx GPU. All PPs are grouped
>>>> togather to handle a single fragment shader task divided by
>>>> FB output tiled pixels. Mali 400 user space driver is
>>>> responsible for assign target tiled pixels to each PP, but mali
>>>> 450 has a HW module called DLBU to dynamically balance each
>>>> PP's load.
>>>> - User space driver allocate buffer object and map into GPU
>>>> virtual address space, upload command stream and draw data with
>>>> CPU mmap of the buffer object, then submit task to GP/PP with
>>>> a register frame indicating where is the command stream and misc
>>>> settings.
>>>> - There's no command stream validation/relocation due to each user
>>>> process has its own GPU virtual address space. GP/PP's MMU switch
>>>> virtual address space before running two tasks from different
>>>> user process. Error or evil user space code just get MMU fault
>>>> or GP/PP error IRQ, then the HW/SW will be recovered.
>>>> - Use TTM as MM. TTM_PL_TT type memory is used as the content of
>>>> lima buffer object which is allocated from TTM page pool. all
>>>> lima buffer object gets pinned with TTM_PL_FLAG_NO_EVICT when
>>>> allocation, so there's no buffer eviction and swap for now. We
>>>> need reverse engineering to see if and how GP/PP support MMU
>>>> fault recovery (continue execution). Otherwise we have to
>>>> pin/unpin each envolved buffer when task creation/deletion.
>>>
>>>
>>> Well pinning all memory is usually a no-go for upstreaming. But since you
>>> are already using the drm_sched for GPU task scheduling why are you actually
>>> needing this?
>>>
>>> The scheduler should take care of signaling all fences when the hardware is
>>> done with it's magic and that is enough for TTM to note that a buffer object
>>> is movable again (e.g. unpin them).
>>
>> Please correct me if I'm wrong.
>>
>> One way to implement eviction/swap is like this:
>> call validation on each buffers involved in a task, but this won't
>> prevent it from
>> eviction/swap when executing, so a GPU MMU fault may happen and in the
>> handler we need to recover the buffer evicted/swapped.
>>
>> Another way is pin/unpin buffers evolved when task create/free.
>>
>> First way is better when memory load is low and second way is better when
>> memory load is high. First way also need less memory.
>>
>> So I'd prefer first way but due to the GPU MMU fault
>> HW op need reverse engineering, I have to pin all buffers now. After
>> the HW op is clear, I can choose one way to implement.
>
> All the drivers using ttm have something that looks like vram, or a
> requirement to move buffers around. Afaiui that includes virtio drm
> driver.
Does virtio drm driver need to move buffers around? amdgpu also
has no vram when APU.
> From your description you don't have such a requirement, and
> then doing what etnaviv has done would be a lot simpler. Everything
> that's not related to buffer movement handling is also available
> outside of ttm already.
Yeah, I could do like etnaviv, but it's not simpler than using ttm
directly especially want some optimization (like ttm page pool,
ttm_eu_reserve_buffers, ttm_bo_mmap). If I have/want to implement
them, why not just use TTM directly with all those helper functions.
Regards,
Qiang
> -Daniel
>
>> Regards,
>> Qiang
>>
>>>
>>> Christian.
>>>
>>>
>>>> - Use drm_sched for GPU task schedule. Each OpenGL context should
>>>> have a lima context object in the kernel to distinguish tasks
>>>> from different user. drm_sched gets task from each lima context
>>>> in a fair way.
>>>>
>>>> Not implemented:
>>>> - Dump buffer support
>>>> - Power management
>>>> - Performance counter
>>>>
>>>> This patch serial just pack a pair of .c/.h files in each patch.
>>>> For whole history of this driver's development, see:
>>>> https://github.com/yuq/linux-lima/commits/lima-4.17-rc4
>>>>
>>>> Mesa driver is still in development and not ready for daily usage,
>>>> but can run some simple tests like kmscube and glamrk2, see:
>>>> https://github.com/yuq/mesa-lima
>>>>
>>>> Andrei Paulau (1):
>>>> arm64/dts: add switch-delay for meson mali
>>>>
>>>> Lima Project Developers (10):
>>>> drm/lima: add mali 4xx GPU hardware regs
>>>> drm/lima: add lima core driver
>>>> drm/lima: add GPU device functions
>>>> drm/lima: add PMU related functions
>>>> drm/lima: add PP related functions
>>>> drm/lima: add MMU related functions
>>>> drm/lima: add GPU virtual memory space handing
>>>> drm/lima: add GEM related functions
>>>> drm/lima: add GEM Prime related functions
>>>> drm/lima: add makefile and kconfig
>>>>
>>>> Qiang Yu (12):
>>>> dt-bindings: add switch-delay property for mali-utgard
>>>> arm64/dts: add switch-delay for meson mali
>>>> Revert "drm: Nerf the preclose callback for modern drivers"
>>>> drm/lima: add lima uapi header
>>>> drm/lima: add L2 cache functions
>>>> drm/lima: add GP related functions
>>>> drm/lima: add BCAST related function
>>>> drm/lima: add DLBU related functions
>>>> drm/lima: add TTM subsystem functions
>>>> drm/lima: add buffer object functions
>>>> drm/lima: add GPU schedule using DRM_SCHED
>>>> drm/lima: add context related functions
>>>>
>>>> Simon Shields (1):
>>>> ARM: dts: add gpu node to exynos4
>>>>
>>>> .../bindings/gpu/arm,mali-utgard.txt | 4 +
>>>> arch/arm/boot/dts/exynos4.dtsi | 33 ++
>>>> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 1 +
>>>> .../boot/dts/amlogic/meson-gxl-mali.dtsi | 1 +
>>>> drivers/gpu/drm/Kconfig | 2 +
>>>> drivers/gpu/drm/Makefile | 1 +
>>>> drivers/gpu/drm/drm_file.c | 8 +-
>>>> drivers/gpu/drm/lima/Kconfig | 9 +
>>>> drivers/gpu/drm/lima/Makefile | 19 +
>>>> drivers/gpu/drm/lima/lima_bcast.c | 65 +++
>>>> drivers/gpu/drm/lima/lima_bcast.h | 34 ++
>>>> drivers/gpu/drm/lima/lima_ctx.c | 143 +++++
>>>> drivers/gpu/drm/lima/lima_ctx.h | 51 ++
>>>> drivers/gpu/drm/lima/lima_device.c | 407 ++++++++++++++
>>>> drivers/gpu/drm/lima/lima_device.h | 136 +++++
>>>> drivers/gpu/drm/lima/lima_dlbu.c | 75 +++
>>>> drivers/gpu/drm/lima/lima_dlbu.h | 37 ++
>>>> drivers/gpu/drm/lima/lima_drv.c | 466 ++++++++++++++++
>>>> drivers/gpu/drm/lima/lima_drv.h | 77 +++
>>>> drivers/gpu/drm/lima/lima_gem.c | 459 ++++++++++++++++
>>>> drivers/gpu/drm/lima/lima_gem.h | 41 ++
>>>> drivers/gpu/drm/lima/lima_gem_prime.c | 66 +++
>>>> drivers/gpu/drm/lima/lima_gem_prime.h | 31 ++
>>>> drivers/gpu/drm/lima/lima_gp.c | 293 +++++++++++
>>>> drivers/gpu/drm/lima/lima_gp.h | 34 ++
>>>> drivers/gpu/drm/lima/lima_l2_cache.c | 98 ++++
>>>> drivers/gpu/drm/lima/lima_l2_cache.h | 32 ++
>>>> drivers/gpu/drm/lima/lima_mmu.c | 154 ++++++
>>>> drivers/gpu/drm/lima/lima_mmu.h | 34 ++
>>>> drivers/gpu/drm/lima/lima_object.c | 120 +++++
>>>> drivers/gpu/drm/lima/lima_object.h | 87 +++
>>>> drivers/gpu/drm/lima/lima_pmu.c | 85 +++
>>>> drivers/gpu/drm/lima/lima_pmu.h | 30 ++
>>>> drivers/gpu/drm/lima/lima_pp.c | 418 +++++++++++++++
>>>> drivers/gpu/drm/lima/lima_pp.h | 37 ++
>>>> drivers/gpu/drm/lima/lima_regs.h | 304 +++++++++++
>>>> drivers/gpu/drm/lima/lima_sched.c | 497 ++++++++++++++++++
>>>> drivers/gpu/drm/lima/lima_sched.h | 126 +++++
>>>> drivers/gpu/drm/lima/lima_ttm.c | 409 ++++++++++++++
>>>> drivers/gpu/drm/lima/lima_ttm.h | 44 ++
>>>> drivers/gpu/drm/lima/lima_vm.c | 312 +++++++++++
>>>> drivers/gpu/drm/lima/lima_vm.h | 73 +++
>>>> include/drm/drm_drv.h | 23 +-
>>>> include/uapi/drm/lima_drm.h | 195 +++++++
>>>> 44 files changed, 5565 insertions(+), 6 deletions(-)
>>>> create mode 100644 drivers/gpu/drm/lima/Kconfig
>>>> create mode 100644 drivers/gpu/drm/lima/Makefile
>>>> create mode 100644 drivers/gpu/drm/lima/lima_bcast.c
>>>> create mode 100644 drivers/gpu/drm/lima/lima_bcast.h
>>>> create mode 100644 drivers/gpu/drm/lima/lima_ctx.c
>>>> create mode 100644 drivers/gpu/drm/lima/lima_ctx.h
>>>> create mode 100644 drivers/gpu/drm/lima/lima_device.c
>>>> create mode 100644 drivers/gpu/drm/lima/lima_device.h
>>>> create mode 100644 drivers/gpu/drm/lima/lima_dlbu.c
>>>> create mode 100644 drivers/gpu/drm/lima/lima_dlbu.h
>>>> create mode 100644 drivers/gpu/drm/lima/lima_drv.c
>>>> create mode 100644 drivers/gpu/drm/lima/lima_drv.h
>>>> create mode 100644 drivers/gpu/drm/lima/lima_gem.c
>>>> create mode 100644 drivers/gpu/drm/lima/lima_gem.h
>>>> create mode 100644 drivers/gpu/drm/lima/lima_gem_prime.c
>>>> create mode 100644 drivers/gpu/drm/lima/lima_gem_prime.h
>>>> create mode 100644 drivers/gpu/drm/lima/lima_gp.c
>>>> create mode 100644 drivers/gpu/drm/lima/lima_gp.h
>>>> create mode 100644 drivers/gpu/drm/lima/lima_l2_cache.c
>>>> create mode 100644 drivers/gpu/drm/lima/lima_l2_cache.h
>>>> create mode 100644 drivers/gpu/drm/lima/lima_mmu.c
>>>> create mode 100644 drivers/gpu/drm/lima/lima_mmu.h
>>>> create mode 100644 drivers/gpu/drm/lima/lima_object.c
>>>> create mode 100644 drivers/gpu/drm/lima/lima_object.h
>>>> create mode 100644 drivers/gpu/drm/lima/lima_pmu.c
>>>> create mode 100644 drivers/gpu/drm/lima/lima_pmu.h
>>>> create mode 100644 drivers/gpu/drm/lima/lima_pp.c
>>>> create mode 100644 drivers/gpu/drm/lima/lima_pp.h
>>>> create mode 100644 drivers/gpu/drm/lima/lima_regs.h
>>>> create mode 100644 drivers/gpu/drm/lima/lima_sched.c
>>>> create mode 100644 drivers/gpu/drm/lima/lima_sched.h
>>>> create mode 100644 drivers/gpu/drm/lima/lima_ttm.c
>>>> create mode 100644 drivers/gpu/drm/lima/lima_ttm.h
>>>> create mode 100644 drivers/gpu/drm/lima/lima_vm.c
>>>> create mode 100644 drivers/gpu/drm/lima/lima_vm.h
>>>> create mode 100644 include/uapi/drm/lima_drm.h
>>>>
>>>
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
>
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCH v6 6/6] clk: renesas: Renesas RZ/N1 clock driver
From: kbuild test robot @ 2018-05-24 0:17 UTC (permalink / raw)
Cc: kbuild-all, linux-renesas-soc, Simon Horman, phil.edworthy,
Michel Pollet, Michel Pollet, Magnus Damm, Rob Herring,
Mark Rutland, Michael Turquette, Stephen Boyd, Geert Uytterhoeven,
devicetree, linux-kernel, linux-clk
In-Reply-To: <1526983321-41949-7-git-send-email-michel.pollet@bp.renesas.com>
Hi Michel,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on next-20180517]
[also build test WARNING on v4.17-rc6]
[cannot apply to robh/for-next renesas-drivers/clk-renesas renesas/devel v4.17-rc6 v4.17-rc5 v4.17-rc4]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Michel-Pollet/arm-Base-support-for-Renesas-RZN1D-DB-Board/20180524-052042
reproduce:
# apt-get install sparse
make ARCH=x86_64 allmodconfig
make C=1 CF=-D__CHECK_ENDIAN__
sparse warnings: (new ones prefixed by >>)
>> drivers/clk/renesas/rzn1-clocks.c:270:22: sparse: cast removes address space of expression
>> drivers/clk/renesas/rzn1-clocks.c:271:29: sparse: incorrect type in argument 1 (different address spaces) @@ expected unsigned int [noderef] [usertype] <asn:2>*reg @@ got eref] [usertype] <asn:2>*reg @@
drivers/clk/renesas/rzn1-clocks.c:271:29: expected unsigned int [noderef] [usertype] <asn:2>*reg
drivers/clk/renesas/rzn1-clocks.c:271:29: got unsigned int [usertype] *reg
drivers/clk/renesas/rzn1-clocks.c:274:25: sparse: incorrect type in argument 2 (different address spaces) @@ expected unsigned int [noderef] [usertype] <asn:2>*reg @@ got eref] [usertype] <asn:2>*reg @@
drivers/clk/renesas/rzn1-clocks.c:274:25: expected unsigned int [noderef] [usertype] <asn:2>*reg
drivers/clk/renesas/rzn1-clocks.c:274:25: got unsigned int [usertype] *reg
drivers/clk/renesas/rzn1-clocks.c:281:22: sparse: cast removes address space of expression
drivers/clk/renesas/rzn1-clocks.c:282:29: sparse: incorrect type in argument 1 (different address spaces) @@ expected unsigned int [noderef] [usertype] <asn:2>*reg @@ got eref] [usertype] <asn:2>*reg @@
drivers/clk/renesas/rzn1-clocks.c:282:29: expected unsigned int [noderef] [usertype] <asn:2>*reg
drivers/clk/renesas/rzn1-clocks.c:282:29: got unsigned int [usertype] *reg
drivers/clk/renesas/rzn1-clocks.c:430:22: sparse: cast removes address space of expression
drivers/clk/renesas/rzn1-clocks.c:431:30: sparse: incorrect type in argument 1 (different address spaces) @@ expected unsigned int [noderef] [usertype] <asn:2>*reg @@ got eref] [usertype] <asn:2>*reg @@
drivers/clk/renesas/rzn1-clocks.c:431:30: expected unsigned int [noderef] [usertype] <asn:2>*reg
drivers/clk/renesas/rzn1-clocks.c:431:30: got unsigned int [usertype] *reg
drivers/clk/renesas/rzn1-clocks.c:516:22: sparse: cast removes address space of expression
drivers/clk/renesas/rzn1-clocks.c:528:38: sparse: incorrect type in argument 2 (different address spaces) @@ expected unsigned int [noderef] [usertype] <asn:2>*reg @@ got eref] [usertype] <asn:2>*reg @@
drivers/clk/renesas/rzn1-clocks.c:528:38: expected unsigned int [noderef] [usertype] <asn:2>*reg
drivers/clk/renesas/rzn1-clocks.c:528:38: got unsigned int [usertype] *reg
vim +270 drivers/clk/renesas/rzn1-clocks.c
264
265 /* register/bit pairs are encoded as an uint16_t */
266 static void clk_rdesc_set(
267 struct rzn1_priv *clocks,
268 uint16_t one, unsigned int on)
269 {
> 270 u32 *reg = ((u32 *)clocks->reg) + (one >> 5);
> 271 u32 val = clk_readl(reg);
272
273 val = (val & ~(1U << (one & 0x1f))) | ((!!on) << (one & 0x1f));
274 clk_writel(val, reg);
275 }
276
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
^ permalink raw reply
* [PATCH v3 6/6] arm64: defconfig: add CONFIG_ARM_SP805_WATCHDOG
From: Ray Jui @ 2018-05-24 0:15 UTC (permalink / raw)
To: Wim Van Sebroeck, Guenter Roeck, Rob Herring, Mark Rutland,
Frank Rowand, Catalin Marinas, Will Deacon, Robin Murphy
Cc: linux-watchdog, devicetree, linux-arm-kernel, linux-kernel,
bcm-kernel-feedback-list, Ray Jui
In-Reply-To: <1527120924-12131-1-git-send-email-ray.jui@broadcom.com>
Enable the SP805 watchdog timer
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index ecf6137..3fe5eb5 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -351,6 +351,7 @@ CONFIG_ROCKCHIP_THERMAL=m
CONFIG_TEGRA_BPMP_THERMAL=m
CONFIG_UNIPHIER_THERMAL=y
CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
CONFIG_S3C2410_WATCHDOG=y
CONFIG_MESON_GXBB_WATCHDOG=m
CONFIG_MESON_WATCHDOG=m
--
2.1.4
^ permalink raw reply related
* [PATCH v3 5/6] arm64: dt: set initial SR watchdog timeout to 60 seconds
From: Ray Jui @ 2018-05-24 0:15 UTC (permalink / raw)
To: Wim Van Sebroeck, Guenter Roeck, Rob Herring, Mark Rutland,
Frank Rowand, Catalin Marinas, Will Deacon, Robin Murphy
Cc: linux-watchdog, devicetree, linux-arm-kernel, linux-kernel,
bcm-kernel-feedback-list, Ray Jui
In-Reply-To: <1527120924-12131-1-git-send-email-ray.jui@broadcom.com>
Set initial Stingray watchdog timeout to 60 seconds
By the time when the userspace watchdog daemon is ready and taking
control over, the watchdog timeout will then be reset to what's
configured in the daemon
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
---
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
index 99aaff0..1e1cf49 100644
--- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
@@ -420,6 +420,7 @@
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
clock-names = "wdogclk", "apb_pclk";
+ timeout-sec = <60>;
};
gpio_hsls: gpio@d0000 {
--
2.1.4
^ permalink raw reply related
* [PATCH v3 4/6] watchdog: sp805: set WDOG_HW_RUNNING when appropriate
From: Ray Jui @ 2018-05-24 0:15 UTC (permalink / raw)
To: Wim Van Sebroeck, Guenter Roeck, Rob Herring, Mark Rutland,
Frank Rowand, Catalin Marinas, Will Deacon, Robin Murphy
Cc: linux-watchdog, devicetree, linux-arm-kernel, linux-kernel,
bcm-kernel-feedback-list, Ray Jui
In-Reply-To: <1527120924-12131-1-git-send-email-ray.jui@broadcom.com>
If the watchdog hardware is already enabled during the boot process,
when the Linux watchdog driver loads, it should reset the watchdog and
tell the watchdog framework. As a result, ping can be generated from
the watchdog framework, until the userspace watchdog daemon takes over
control
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
---
drivers/watchdog/sp805_wdt.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
index 1484609..d662a6f 100644
--- a/drivers/watchdog/sp805_wdt.c
+++ b/drivers/watchdog/sp805_wdt.c
@@ -42,6 +42,7 @@
/* control register masks */
#define INT_ENABLE (1 << 0)
#define RESET_ENABLE (1 << 1)
+ #define ENABLE_MASK (INT_ENABLE | RESET_ENABLE)
#define WDTINTCLR 0x00C
#define WDTRIS 0x010
#define WDTMIS 0x014
@@ -74,6 +75,15 @@ module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Set to 1 to keep watchdog running after device release");
+/* returns true if wdt is running; otherwise returns false */
+static bool wdt_is_running(struct watchdog_device *wdd)
+{
+ struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
+ u32 wdtcontrol = readl_relaxed(wdt->base + WDTCONTROL);
+
+ return (wdtcontrol & ENABLE_MASK) == ENABLE_MASK;
+}
+
/* This routine finds load value that will reset system in required timout */
static int wdt_setload(struct watchdog_device *wdd, unsigned int timeout)
{
@@ -239,6 +249,15 @@ sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
watchdog_init_timeout(&wdt->wdd, 0, &adev->dev);
wdt_setload(&wdt->wdd, wdt->wdd.timeout);
+ /*
+ * If HW is already running, enable/reset the wdt and set the running
+ * bit to tell the wdt subsystem
+ */
+ if (wdt_is_running(&wdt->wdd)) {
+ wdt_enable(&wdt->wdd);
+ set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
+ }
+
ret = watchdog_register_device(&wdt->wdd);
if (ret) {
dev_err(&adev->dev, "watchdog_register_device() failed: %d\n",
--
2.1.4
^ permalink raw reply related
* [PATCH v3 3/6] watchdog: sp805: add 'timeout-sec' DT property support
From: Ray Jui @ 2018-05-24 0:15 UTC (permalink / raw)
To: Wim Van Sebroeck, Guenter Roeck, Rob Herring, Mark Rutland,
Frank Rowand, Catalin Marinas, Will Deacon, Robin Murphy
Cc: linux-watchdog, devicetree, linux-arm-kernel, linux-kernel,
bcm-kernel-feedback-list, Ray Jui
In-Reply-To: <1527120924-12131-1-git-send-email-ray.jui@broadcom.com>
Add support for optional devicetree property 'timeout-sec'.
'timeout-sec' is used in the driver if specified in devicetree.
Otherwise, fall back to driver default, i.e., 60 seconds
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
---
drivers/watchdog/sp805_wdt.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
index 03805bc..1484609 100644
--- a/drivers/watchdog/sp805_wdt.c
+++ b/drivers/watchdog/sp805_wdt.c
@@ -230,7 +230,14 @@ sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
spin_lock_init(&wdt->lock);
watchdog_set_nowayout(&wdt->wdd, nowayout);
watchdog_set_drvdata(&wdt->wdd, wdt);
- wdt_setload(&wdt->wdd, DEFAULT_TIMEOUT);
+
+ /*
+ * If 'timeout-sec' devicetree property is specified, use that.
+ * Otherwise, use DEFAULT_TIMEOUT
+ */
+ wdt->wdd.timeout = DEFAULT_TIMEOUT;
+ watchdog_init_timeout(&wdt->wdd, 0, &adev->dev);
+ wdt_setload(&wdt->wdd, wdt->wdd.timeout);
ret = watchdog_register_device(&wdt->wdd);
if (ret) {
--
2.1.4
^ permalink raw reply related
* [PATCH v3 2/6] Documentation: DT: Add optional 'timeout-sec' property for sp805
From: Ray Jui @ 2018-05-24 0:15 UTC (permalink / raw)
To: Wim Van Sebroeck, Guenter Roeck, Rob Herring, Mark Rutland,
Frank Rowand, Catalin Marinas, Will Deacon, Robin Murphy
Cc: linux-watchdog, devicetree, linux-arm-kernel, linux-kernel,
bcm-kernel-feedback-list, Ray Jui
In-Reply-To: <1527120924-12131-1-git-send-email-ray.jui@broadcom.com>
Update the SP805 binding document to add optional 'timeout-sec'
devicetree property
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
---
Documentation/devicetree/bindings/watchdog/arm,sp805.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/watchdog/arm,sp805.txt b/Documentation/devicetree/bindings/watchdog/arm,sp805.txt
index 0fa3629..1debea3 100644
--- a/Documentation/devicetree/bindings/watchdog/arm,sp805.txt
+++ b/Documentation/devicetree/bindings/watchdog/arm,sp805.txt
@@ -19,6 +19,8 @@ Required properties:
Optional properties:
- interrupts: Should specify WDT interrupt number
+- timeout-sec: Should specify default WDT timeout in seconds. If unset, the
+ default timeout in the driver is 30 seconds
Example:
watchdog@66090000 {
--
2.1.4
^ permalink raw reply related
* [PATCH v3 1/6] Documentation: DT: Consolidate SP805 binding docs
From: Ray Jui @ 2018-05-24 0:15 UTC (permalink / raw)
To: Wim Van Sebroeck, Guenter Roeck, Rob Herring, Mark Rutland,
Frank Rowand, Catalin Marinas, Will Deacon, Robin Murphy
Cc: linux-watchdog, devicetree, linux-arm-kernel, linux-kernel,
bcm-kernel-feedback-list, Ray Jui
In-Reply-To: <1527120924-12131-1-git-send-email-ray.jui@broadcom.com>
Consolidate two SP805 binding documents "arm,sp805.txt" and
"sp805-wdt.txt" into "arm,sp805.txt" that matches the naming of the
desired compatible string to be used
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
---
.../devicetree/bindings/watchdog/arm,sp805.txt | 27 ++++++++++++++-----
.../devicetree/bindings/watchdog/sp805-wdt.txt | 31 ----------------------
2 files changed, 20 insertions(+), 38 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/watchdog/sp805-wdt.txt
diff --git a/Documentation/devicetree/bindings/watchdog/arm,sp805.txt b/Documentation/devicetree/bindings/watchdog/arm,sp805.txt
index ca99d64..0fa3629 100644
--- a/Documentation/devicetree/bindings/watchdog/arm,sp805.txt
+++ b/Documentation/devicetree/bindings/watchdog/arm,sp805.txt
@@ -1,17 +1,30 @@
ARM AMBA Primecell SP805 Watchdog
+SP805 WDT is a ARM Primecell Peripheral and has a standard-id register that
+can be used to identify the peripheral type, vendor, and revision.
+This value can be used for driver matching.
+
+As SP805 WDT is a primecell IP, it follows the base bindings specified in
+'arm/primecell.txt'
+
Required properties:
-- compatible: Should be "arm,sp805" & "arm,primecell"
-- reg: Should contain location and length for watchdog timer register.
-- interrupts: Should contain the list of watchdog timer interrupts.
-- clocks: clocks driving the watchdog timer hardware. This list should be 2
- clocks. With 2 clocks, the order is wdogclk clock, apb_pclk.
+- compatible: Should be "arm,sp805" & "arm,primecell"
+- reg: Should contain location and length for watchdog timer register
+- clocks: Clocks driving the watchdog timer hardware. This list should be
+ 2 clocks. With 2 clocks, the order is wdog_clk, apb_pclk
+ wdog_clk can be equal to or be a sub-multiple of the apb_pclk
+ frequency
+- clock-names: Shall be "wdog_clk" for first clock and "apb_pclk" for the
+ second one
+
+Optional properties:
+- interrupts: Should specify WDT interrupt number
Example:
watchdog@66090000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x66090000 0x1000>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb_pclk>,<&apb_pclk>;
- clock-names = "wdogclk", "apb_pclk";
+ clocks = <&wdt_clk>, <&apb_pclk>;
+ clock-names = "wdog_clk", "apb_pclk";
};
diff --git a/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt b/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt
deleted file mode 100644
index edc4f0e..0000000
--- a/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-* ARM SP805 Watchdog Timer (WDT) Controller
-
-SP805 WDT is a ARM Primecell Peripheral and has a standard-id register that
-can be used to identify the peripheral type, vendor, and revision.
-This value can be used for driver matching.
-
-As SP805 WDT is a primecell IP, it follows the base bindings specified in
-'arm/primecell.txt'
-
-Required properties:
-- compatible : Should be "arm,sp805-wdt", "arm,primecell"
-- reg : Base address and size of the watchdog timer registers.
-- clocks : From common clock binding.
- First clock is PCLK and the second is WDOGCLK.
- WDOGCLK can be equal to or be a sub-multiple of the PCLK frequency.
-- clock-names : From common clock binding.
- Shall be "apb_pclk" for first clock and "wdog_clk" for the
- second one.
-
-Optional properties:
-- interrupts : Should specify WDT interrupt number.
-
-Examples:
-
- cluster1_core0_watchdog: wdt@c000000 {
- compatible = "arm,sp805-wdt", "arm,primecell";
- reg = <0x0 0xc000000 0x0 0x1000>;
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
- clock-names = "apb_pclk", "wdog_clk";
- };
-
--
2.1.4
^ permalink raw reply related
* [PATCH v3 0/6] Enhance support for the SP805 WDT
From: Ray Jui @ 2018-05-24 0:15 UTC (permalink / raw)
To: Wim Van Sebroeck, Guenter Roeck, Rob Herring, Mark Rutland,
Frank Rowand, Catalin Marinas, Will Deacon, Robin Murphy
Cc: linux-watchdog, devicetree, linux-arm-kernel, linux-kernel,
bcm-kernel-feedback-list, Ray Jui
This patch series enhances the support for the SP805 watchdog timer.
First of all, 'timeout-sec' devicetree property is added. In addition,
support is also added to allow the driver to reset the watchdog if it
has been detected that watchdot has been started in the bootloader. In
this case, the driver will initiate the ping service from the kernel
watchdog subsystem, before a user mode daemon takes over. This series
also enables SP805 in the default ARM64 defconfig
This patch series is based off v4.17-rc5 and is available on GIHUB:
repo: https://github.com/Broadcom/arm64-linux.git
branch: sp805-wdt-v3
Changes since v2:
- Fix indent and format to make them consistent within arm,sp805.txt
Changes since v1:
- Consolidate two duplicated SP805 binding documents into one
- Slight change of the wdt_is_running implementation per discussion
Ray Jui (6):
Documentation: DT: Consolidate SP805 binding docs
Documentation: DT: Add optional 'timeout-sec' property for sp805
watchdog: sp805: add 'timeout-sec' DT property support
watchdog: sp805: set WDOG_HW_RUNNING when appropriate
arm64: dt: set initial SR watchdog timeout to 60 seconds
arm64: defconfig: add CONFIG_ARM_SP805_WATCHDOG
.../devicetree/bindings/watchdog/arm,sp805.txt | 29 +++++++++++++++-----
.../devicetree/bindings/watchdog/sp805-wdt.txt | 31 ----------------------
.../arm64/boot/dts/broadcom/stingray/stingray.dtsi | 1 +
arch/arm64/configs/defconfig | 1 +
drivers/watchdog/sp805_wdt.c | 28 ++++++++++++++++++-
5 files changed, 51 insertions(+), 39 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/watchdog/sp805-wdt.txt
--
2.1.4
^ permalink raw reply
* Re: [PATCH v6 5/6] ARM: dts: Renesas RZN1D-DB Board base file
From: kbuild test robot @ 2018-05-24 0:03 UTC (permalink / raw)
Cc: kbuild-all, linux-renesas-soc, Simon Horman, phil.edworthy,
Michel Pollet, Michel Pollet, Magnus Damm, Rob Herring,
Mark Rutland, Michael Turquette, Stephen Boyd, Geert Uytterhoeven,
devicetree, linux-kernel, linux-clk
In-Reply-To: <1526983321-41949-6-git-send-email-michel.pollet@bp.renesas.com>
[-- Attachment #1: Type: text/plain, Size: 1738 bytes --]
Hi Michel,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on next-20180517]
[also build test ERROR on v4.17-rc6]
[cannot apply to robh/for-next renesas-drivers/clk-renesas renesas/devel v4.17-rc6 v4.17-rc5 v4.17-rc4]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Michel-Pollet/arm-Base-support-for-Renesas-RZN1D-DB-Board/20180524-052042
config: arm-at91_dt_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm
All errors (new ones prefixed by >>):
In file included from arch/arm/boot/dts/r9a06g032-rzn1d400-db.dts:11:0:
>> arch/arm/boot/dts/r9a06g032.dtsi:10:10: fatal error: dt-bindings/clock/rzn1-clock.h: No such file or directory
#include <dt-bindings/clock/rzn1-clock.h>
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
vim +10 arch/arm/boot/dts/r9a06g032.dtsi
f9ea3b52 Michel Pollet 2018-05-22 @10 #include <dt-bindings/clock/rzn1-clock.h>
f9ea3b52 Michel Pollet 2018-05-22 11
:::::: The code at line 10 was first introduced by commit
:::::: f9ea3b52d31219bb2ad77f919417ed61fc779fcb ARM: dts: Renesas RZ/N1 SoC base device tree file
:::::: TO: Michel Pollet <michel.pollet@bp.renesas.com>
:::::: CC: 0day robot <lkp@intel.com>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 23300 bytes --]
^ permalink raw reply
* Re: [PATCH v2 2/6] Documentation: DT: Add optional 'timeout-sec' property for sp805
From: Ray Jui @ 2018-05-23 23:51 UTC (permalink / raw)
To: Guenter Roeck
Cc: Wim Van Sebroeck, Rob Herring, Mark Rutland, Frank Rowand,
Catalin Marinas, Will Deacon, Robin Murphy, linux-watchdog,
devicetree, linux-arm-kernel, linux-kernel,
bcm-kernel-feedback-list
In-Reply-To: <20180523222915.GA16779@roeck-us.net>
On 5/23/2018 3:29 PM, Guenter Roeck wrote:
> On Wed, May 23, 2018 at 01:32:03PM -0700, Ray Jui wrote:
>> Update the SP805 binding document to add optional 'timeout-sec'
>> devicetree property
>>
>> Signed-off-by: Ray Jui <ray.jui@broadcom.com>
>> Reviewed-by: Scott Branden <scott.branden@broadcom.com>
>> Reviewed-by: Guenter Roeck <linux@roeck-us.net>
>> ---
>> Documentation/devicetree/bindings/watchdog/arm,sp805.txt | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/watchdog/arm,sp805.txt b/Documentation/devicetree/bindings/watchdog/arm,sp805.txt
>> index de93a4d..9cd7470 100644
>> --- a/Documentation/devicetree/bindings/watchdog/arm,sp805.txt
>> +++ b/Documentation/devicetree/bindings/watchdog/arm,sp805.txt
>> @@ -18,6 +18,8 @@ Required properties:
>>
>> Optional properties:
>> - interrupts : Should specify WDT interrupt number.
>> +timeout-sec : Should specify default WDT timeout in seconds. If unset, the
>> + default timeout in the driver is 30 seconds
>
> That looks odd, with the changed indentation and the missing '-'
> in front of 'timeout-sec' >
My bad. Will fix this in v3. Thanks.
> Guenter
>
^ permalink raw reply
* Re: [PATCH v2 2/6] Documentation: DT: Add optional 'timeout-sec' property for sp805
From: Guenter Roeck @ 2018-05-23 22:29 UTC (permalink / raw)
To: Ray Jui
Cc: Wim Van Sebroeck, Rob Herring, Mark Rutland, Frank Rowand,
Catalin Marinas, Will Deacon, Robin Murphy, linux-watchdog,
devicetree, linux-arm-kernel, linux-kernel,
bcm-kernel-feedback-list
In-Reply-To: <1527107527-8093-3-git-send-email-ray.jui@broadcom.com>
On Wed, May 23, 2018 at 01:32:03PM -0700, Ray Jui wrote:
> Update the SP805 binding document to add optional 'timeout-sec'
> devicetree property
>
> Signed-off-by: Ray Jui <ray.jui@broadcom.com>
> Reviewed-by: Scott Branden <scott.branden@broadcom.com>
> Reviewed-by: Guenter Roeck <linux@roeck-us.net>
> ---
> Documentation/devicetree/bindings/watchdog/arm,sp805.txt | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/watchdog/arm,sp805.txt b/Documentation/devicetree/bindings/watchdog/arm,sp805.txt
> index de93a4d..9cd7470 100644
> --- a/Documentation/devicetree/bindings/watchdog/arm,sp805.txt
> +++ b/Documentation/devicetree/bindings/watchdog/arm,sp805.txt
> @@ -18,6 +18,8 @@ Required properties:
>
> Optional properties:
> - interrupts : Should specify WDT interrupt number.
> +timeout-sec : Should specify default WDT timeout in seconds. If unset, the
> + default timeout in the driver is 30 seconds
That looks odd, with the changed indentation and the missing '-'
in front of 'timeout-sec'.
Guenter
^ permalink raw reply
* Re: [PATCH] ARM: DTS: imx53: Add support for imx53 HSC/DDC boards from K+P
From: Lukasz Majewski @ 2018-05-23 22:18 UTC (permalink / raw)
To: Fabio Estevam
Cc: Rob Herring, Mark Rutland, Russell King, Shawn Guo, Sascha Hauer,
Fabio Estevam, linux-kernel,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <CAOMZO5DoLwEmQz5BQHDLk8sBq7mDH_UxBjRA0RGKb+PunMYu-Q@mail.gmail.com>
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Hi Fabio,
> Hi Lukasz,
>
> On Sat, May 19, 2018 at 9:02 AM, Lukasz Majewski <lukma@denx.de>
> wrote:
>
> > After removing imx53-kp-ddc and imx53-kp-common iomux subnodes I do
> > see following errors in the dmesg (v4.17-rc5):
> >
> > imx53-pinctrl 53fa8000.iomuxc: function 'iomuxc' not supported
> > imx53-pinctrl 53fa8000.iomuxc: invalid function iomuxc in map
> > table
>
> Could you please investigate this error?
>
Ok.
> I have just tried the following change on a imx53-qsb:
> http://code.bulix.org/ik01yu-339697
I've noticed that this is the "common" dtsi file:
imx53-qsb-common.dtsi
Is there any board inheriting it? Is it extending the iomux node with
its own code ?
>
> and it works as expected:
> # dmesg | grep iomux
> [ 0.100046] imx53-pinctrl 53fa8000.iomuxc: initialized IMX pinctrl
> driver
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
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^ permalink raw reply
* Re: [PATCH 2/4] arcnet: com20020: bindings for smsc com20020
From: Andrea Greco @ 2018-05-23 22:17 UTC (permalink / raw)
To: Rob Herring
Cc: Tobin C. Harding, Andrea Greco, Mark Rutland, netdev, devicetree,
linux-kernel
In-Reply-To: <20180523164931.GA3635@rob-hp-laptop>
On 05/23/2018 06:49 PM, Rob Herring wrote:
> One typo, otherwise:
>
> Reviewed-by: Rob Herring <robh@kernel.org>
Yes typo, Fixed over my branch, sorry for that...
I expect a comment about bps, Bit per Second, used in `bus-speed-bps`
You will add it by your self in property-units.txt, or required my patch?
If your confirm that, ready for: Reviewed-by
Regards, Andrea
^ permalink raw reply
* Re: [v4 07/11] dt-bindings: hwmon: Add documents for PECI hwmon client drivers
From: Jae Hyun Yoo @ 2018-05-23 21:56 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland, Haiyue Wang, Vernon Mauery, James Feist, devicetree,
linux-kernel@vger.kernel.org, Andrew Jeffery, Arnd Bergmann,
Jason M Biils, Joel Stanley
In-Reply-To: <22bd0e23-69ad-5858-656e-16c77007913c@linux.intel.com>
On 5/23/2018 1:03 PM, Jae Hyun Yoo wrote:
> On 5/23/2018 12:33 PM, Rob Herring wrote:
>> On Wed, May 23, 2018 at 11:37 AM, Jae Hyun Yoo
>> <jae.hyun.yoo@linux.intel.com> wrote:
>>> On 5/23/2018 8:11 AM, Rob Herring wrote:
>>>>
>>>> On Tue, May 22, 2018 at 12:18 PM, Jae Hyun Yoo
>>>> <jae.hyun.yoo@linux.intel.com> wrote:
>>>>>
>>>>> On 5/22/2018 9:42 AM, Rob Herring wrote:
>>>>>>
>>>>>>
>>>>>> On Mon, May 21, 2018 at 12:59:05PM -0700, Jae Hyun Yoo wrote:
>>>>>>>
>>>>>>>
>>>>>>> This commit adds dt-bindings documents for PECI hwmon client
>>>>>>> drivers.
>>>>>>>
>>>>>>> Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
>>>>>>> Reviewed-by: Haiyue Wang <haiyue.wang@linux.intel.com>
>>>>>>> Reviewed-by: James Feist <james.feist@linux.intel.com>
>>>>>>> Reviewed-by: Vernon Mauery <vernon.mauery@linux.intel.com>
>>>>>>> Cc: Andrew Jeffery <andrew@aj.id.au>
>>>>>>> Cc: Arnd Bergmann <arnd@arndb.de>
>>>>>>> Cc: Jason M Biils <jason.m.bills@linux.intel.com>
>>>>>>> Cc: Joel Stanley <joel@jms.id.au>
>>>>>>> ---
>>>>>>> .../bindings/hwmon/peci-cputemp.txt | 23
>>>>>>> ++++++++++++++++++
>>>>>>> .../bindings/hwmon/peci-dimmtemp.txt | 24
>>>>>>> +++++++++++++++++++
>>>>>>> 2 files changed, 47 insertions(+)
>>>>>>> create mode 100644
>>>>>>> Documentation/devicetree/bindings/hwmon/peci-cputemp.txt
>>>>>>> create mode 100644
>>>>>>> Documentation/devicetree/bindings/hwmon/peci-dimmtemp.txt
>>>>>>>
>>>>>>> diff --git
>>>>>>> a/Documentation/devicetree/bindings/hwmon/peci-cputemp.txt
>>>>>>> b/Documentation/devicetree/bindings/hwmon/peci-cputemp.txt
>>>>>>> new file mode 100644
>>>>>>> index 000000000000..2f59aee12d9e
>>>>>>> --- /dev/null
>>>>>>> +++ b/Documentation/devicetree/bindings/hwmon/peci-cputemp.txt
>>>>>>> @@ -0,0 +1,23 @@
>>>>>>> +Bindings for Intel PECI (Platform Environment Control Interface)
>>>>>>> cputemp
>>>>>>> driver.
>>>>>>> +
>>>>>>> +Required properties:
>>>>>>> +- compatible : Should be "intel,peci-cputemp".
>>>>>>> +- reg : Should contain address of a client CPU. Address
>>>>>>> range
>>>>>>> of
>>>>>>> CPU
>>>>>>> + clients is starting from 0x30 based on PECI
>>>>>>> specification.
>>>>>>> +
>>>>>>> +Example:
>>>>>>> + peci-bus@0 {
>>>>>>> + #address-cells = <1>;
>>>>>>> + #size-cells = <0>;
>>>>>>> + < more properties >
>>>>>>> +
>>>>>>> + peci-cputemp@30 {
>>>>>>> + compatible = "intel,peci-cputemp";
>>>>>>> + reg = <0x30>;
>>>>>>> + };
>>>>>>
>>>>>>
>>>>>>
>>>>>> [...]
>>>>>>
>>>>>>> + peci-dimmtemp@30 {
>>>>>>> + compatible = "intel,peci-dimmtemp";
>>>>>>> + reg = <0x30>;
>>>>>>> + };
>>>>>>
>>>>>>
>>>>>>
>>>>>> As I said in the prior version, 2 nodes at the same address is wrong.
>>>>>>
>>>>>> Rob
>>>>>>
>>>>>
>>>>> In PECI bus, there is one and only bus host (adapter) and multiple
>>>>> clients on a PECI bus, and PECI spec doesn't allow multiple
>>>>> originators
>>>>> so only the host device can originate message.
>>>>
>>>>
>>>> Yes, I get that. A single host still has to address slave devices.
>>>>
>>>>> In this implementation,
>>>>> all message transactions on a bus from client driver modules and user
>>>>> space will be serialized well in the PECI core bus driver so bus
>>>>> occupation and traffic arbitration will be managed well in the PECI
>>>>> core
>>>>> bus driver even in case of a bus has 2 client drivers at the same
>>>>> address. I'm sure that this implementation doesn't make that kind of
>>>>> problem to OS.
>>>>
>>>>
>>>> Multiple clients to a single device is common, but that is a software
>>>> problem and doesn't belong in DT.
>>>>
>>>> I don't think there is a single other case in the kernel where
>>>> multiple drivers can bind to the same device at a given bus address.
>>>> That is why we have things like MFD. Though in this case, why can't
>>>> one hwmon driver register multiple hwmon devices (cpu and dimm temps)?
>>>>
>>>
>>> It was implemented as a single driver until v2 but dimm temps need
>>> delayed creation unlikely the cpu temps on hwmon subsystem because of
>>> memory training behavior of remote x86 cpus. Since hwmon doesn't allow
>>> incremental creation, I had to divide it into two, cputemp and dimmtemp,
>>> so that cputemp can be registered immediately when the remote x86 cpu
>>> turns on and dimmtemp can be registered by delayed creation. It is the
>>> reason why I had to make the two hwmon driver modules that sharing a
>>> single device address.
>>
>> That all sounds like kernel problems to me. Stop designing your DT
>> binding around what the kernel can or can't *currently* support.
>>
>>> Additionally, PECI isn't limited for temperature
>>> monitoring feature but it can be used for other functions such as
>>> platform management, cpu interface tuning and diagnostics and failure
>>> analysis, so in case of adding a new driver for the functions, we should
>>> add an another DT node which is sharing the same cpu address.
>>
>> No, the driver should add support for those additional functions.
>> Perhaps you will need to use MFD.
>>
>
> Do you mean that the device address sharing is acceptable if I make
> these nodes under "simple-mfd"?
>
> Thanks,
>
> -Jae
Hi Rob,
I'm planning to change the whole PECI node like below:
peci: peci@1e78b000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x1e78b000 0x60>;
peci0: peci-bus@0 {
compatible = "aspeed,ast2500-peci";
reg = <0x0 0x60>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <15>;
clocks = <&syscon ASPEED_CLK_GATE_REFCLK>;
resets = <&syscon ASPEED_RESET_PECI>;
clock-frequency = <24000000>;
msg-timing = <1>;
addr-timing = <1>;
rd-sampling-point = <8>;
cmd-timeout-ms = <1000>;
status = "disabled";
peci-client@30 {
compatible = "simple-mfd", "syscon";
reg = <0x30>;
cputemp: cputemp {
compatible = "intel,peci-cputemp";
};
dimmtemp: dimmtemp {
compatible = "intel,peci-dimmtemp";
};
};
peci-client@31 {
compatible = "simple-mfd", "syscon";
reg = <0x31>;
cputemp: cputemp {
compatible = "intel,peci-cputemp";
};
dimmtemp: dimmtemp {
compatible = "intel,peci-dimmtemp";
};
};
};
};
Can you please check whether it is acceptable or not?
Thanks,
-Jae
^ permalink raw reply
* [PATCH v2 6/6] arm64: defconfig: add CONFIG_ARM_SP805_WATCHDOG
From: Ray Jui @ 2018-05-23 20:32 UTC (permalink / raw)
To: Wim Van Sebroeck, Guenter Roeck, Rob Herring, Mark Rutland,
Frank Rowand, Catalin Marinas, Will Deacon, Robin Murphy
Cc: linux-watchdog, devicetree, linux-arm-kernel, linux-kernel,
bcm-kernel-feedback-list, Ray Jui
In-Reply-To: <1527107527-8093-1-git-send-email-ray.jui@broadcom.com>
Enable the SP805 watchdog timer
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index ecf6137..3fe5eb5 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -351,6 +351,7 @@ CONFIG_ROCKCHIP_THERMAL=m
CONFIG_TEGRA_BPMP_THERMAL=m
CONFIG_UNIPHIER_THERMAL=y
CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
CONFIG_S3C2410_WATCHDOG=y
CONFIG_MESON_GXBB_WATCHDOG=m
CONFIG_MESON_WATCHDOG=m
--
2.1.4
^ permalink raw reply related
* [PATCH v2 5/6] arm64: dt: set initial SR watchdog timeout to 60 seconds
From: Ray Jui @ 2018-05-23 20:32 UTC (permalink / raw)
To: Wim Van Sebroeck, Guenter Roeck, Rob Herring, Mark Rutland,
Frank Rowand, Catalin Marinas, Will Deacon, Robin Murphy
Cc: linux-watchdog, devicetree, linux-arm-kernel, linux-kernel,
bcm-kernel-feedback-list, Ray Jui
In-Reply-To: <1527107527-8093-1-git-send-email-ray.jui@broadcom.com>
Set initial Stingray watchdog timeout to 60 seconds
By the time when the userspace watchdog daemon is ready and taking
control over, the watchdog timeout will then be reset to what's
configured in the daemon
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
---
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
index 99aaff0..1e1cf49 100644
--- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
@@ -420,6 +420,7 @@
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&hsls_25m_div2_clk>, <&hsls_div4_clk>;
clock-names = "wdogclk", "apb_pclk";
+ timeout-sec = <60>;
};
gpio_hsls: gpio@d0000 {
--
2.1.4
^ permalink raw reply related
* [PATCH v2 4/6] watchdog: sp805: set WDOG_HW_RUNNING when appropriate
From: Ray Jui @ 2018-05-23 20:32 UTC (permalink / raw)
To: Wim Van Sebroeck, Guenter Roeck, Rob Herring, Mark Rutland,
Frank Rowand, Catalin Marinas, Will Deacon, Robin Murphy
Cc: linux-watchdog, devicetree, linux-arm-kernel, linux-kernel,
bcm-kernel-feedback-list, Ray Jui
In-Reply-To: <1527107527-8093-1-git-send-email-ray.jui@broadcom.com>
If the watchdog hardware is already enabled during the boot process,
when the Linux watchdog driver loads, it should reset the watchdog and
tell the watchdog framework. As a result, ping can be generated from
the watchdog framework, until the userspace watchdog daemon takes over
control
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
---
drivers/watchdog/sp805_wdt.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
index 1484609..d662a6f 100644
--- a/drivers/watchdog/sp805_wdt.c
+++ b/drivers/watchdog/sp805_wdt.c
@@ -42,6 +42,7 @@
/* control register masks */
#define INT_ENABLE (1 << 0)
#define RESET_ENABLE (1 << 1)
+ #define ENABLE_MASK (INT_ENABLE | RESET_ENABLE)
#define WDTINTCLR 0x00C
#define WDTRIS 0x010
#define WDTMIS 0x014
@@ -74,6 +75,15 @@ module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
"Set to 1 to keep watchdog running after device release");
+/* returns true if wdt is running; otherwise returns false */
+static bool wdt_is_running(struct watchdog_device *wdd)
+{
+ struct sp805_wdt *wdt = watchdog_get_drvdata(wdd);
+ u32 wdtcontrol = readl_relaxed(wdt->base + WDTCONTROL);
+
+ return (wdtcontrol & ENABLE_MASK) == ENABLE_MASK;
+}
+
/* This routine finds load value that will reset system in required timout */
static int wdt_setload(struct watchdog_device *wdd, unsigned int timeout)
{
@@ -239,6 +249,15 @@ sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
watchdog_init_timeout(&wdt->wdd, 0, &adev->dev);
wdt_setload(&wdt->wdd, wdt->wdd.timeout);
+ /*
+ * If HW is already running, enable/reset the wdt and set the running
+ * bit to tell the wdt subsystem
+ */
+ if (wdt_is_running(&wdt->wdd)) {
+ wdt_enable(&wdt->wdd);
+ set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
+ }
+
ret = watchdog_register_device(&wdt->wdd);
if (ret) {
dev_err(&adev->dev, "watchdog_register_device() failed: %d\n",
--
2.1.4
^ permalink raw reply related
* [PATCH v2 3/6] watchdog: sp805: add 'timeout-sec' DT property support
From: Ray Jui @ 2018-05-23 20:32 UTC (permalink / raw)
To: Wim Van Sebroeck, Guenter Roeck, Rob Herring, Mark Rutland,
Frank Rowand, Catalin Marinas, Will Deacon, Robin Murphy
Cc: linux-watchdog, devicetree, linux-arm-kernel, linux-kernel,
bcm-kernel-feedback-list, Ray Jui
In-Reply-To: <1527107527-8093-1-git-send-email-ray.jui@broadcom.com>
Add support for optional devicetree property 'timeout-sec'.
'timeout-sec' is used in the driver if specified in devicetree.
Otherwise, fall back to driver default, i.e., 60 seconds
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
---
drivers/watchdog/sp805_wdt.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
index 03805bc..1484609 100644
--- a/drivers/watchdog/sp805_wdt.c
+++ b/drivers/watchdog/sp805_wdt.c
@@ -230,7 +230,14 @@ sp805_wdt_probe(struct amba_device *adev, const struct amba_id *id)
spin_lock_init(&wdt->lock);
watchdog_set_nowayout(&wdt->wdd, nowayout);
watchdog_set_drvdata(&wdt->wdd, wdt);
- wdt_setload(&wdt->wdd, DEFAULT_TIMEOUT);
+
+ /*
+ * If 'timeout-sec' devicetree property is specified, use that.
+ * Otherwise, use DEFAULT_TIMEOUT
+ */
+ wdt->wdd.timeout = DEFAULT_TIMEOUT;
+ watchdog_init_timeout(&wdt->wdd, 0, &adev->dev);
+ wdt_setload(&wdt->wdd, wdt->wdd.timeout);
ret = watchdog_register_device(&wdt->wdd);
if (ret) {
--
2.1.4
^ permalink raw reply related
* [PATCH v2 2/6] Documentation: DT: Add optional 'timeout-sec' property for sp805
From: Ray Jui @ 2018-05-23 20:32 UTC (permalink / raw)
To: Wim Van Sebroeck, Guenter Roeck, Rob Herring, Mark Rutland,
Frank Rowand, Catalin Marinas, Will Deacon, Robin Murphy
Cc: linux-watchdog, devicetree, linux-arm-kernel, linux-kernel,
bcm-kernel-feedback-list, Ray Jui
In-Reply-To: <1527107527-8093-1-git-send-email-ray.jui@broadcom.com>
Update the SP805 binding document to add optional 'timeout-sec'
devicetree property
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
---
Documentation/devicetree/bindings/watchdog/arm,sp805.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/watchdog/arm,sp805.txt b/Documentation/devicetree/bindings/watchdog/arm,sp805.txt
index de93a4d..9cd7470 100644
--- a/Documentation/devicetree/bindings/watchdog/arm,sp805.txt
+++ b/Documentation/devicetree/bindings/watchdog/arm,sp805.txt
@@ -18,6 +18,8 @@ Required properties:
Optional properties:
- interrupts : Should specify WDT interrupt number.
+timeout-sec : Should specify default WDT timeout in seconds. If unset, the
+ default timeout in the driver is 30 seconds
Example:
watchdog@66090000 {
--
2.1.4
^ permalink raw reply related
* [PATCH v2 1/6] Documentation: DT: Consolidate SP805 binding docs
From: Ray Jui @ 2018-05-23 20:32 UTC (permalink / raw)
To: Wim Van Sebroeck, Guenter Roeck, Rob Herring, Mark Rutland,
Frank Rowand, Catalin Marinas, Will Deacon, Robin Murphy
Cc: linux-watchdog, devicetree, linux-arm-kernel, linux-kernel,
bcm-kernel-feedback-list, Ray Jui
In-Reply-To: <1527107527-8093-1-git-send-email-ray.jui@broadcom.com>
Consolidate two SP805 binding documents "arm,sp805.txt" and
"sp805-wdt.txt" into "arm,sp805.txt" that matches the naming of the
desired compatible string to be used
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
---
.../devicetree/bindings/watchdog/arm,sp805.txt | 20 +++++++++++---
.../devicetree/bindings/watchdog/sp805-wdt.txt | 31 ----------------------
2 files changed, 16 insertions(+), 35 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/watchdog/sp805-wdt.txt
diff --git a/Documentation/devicetree/bindings/watchdog/arm,sp805.txt b/Documentation/devicetree/bindings/watchdog/arm,sp805.txt
index ca99d64..de93a4d 100644
--- a/Documentation/devicetree/bindings/watchdog/arm,sp805.txt
+++ b/Documentation/devicetree/bindings/watchdog/arm,sp805.txt
@@ -1,17 +1,29 @@
ARM AMBA Primecell SP805 Watchdog
+SP805 WDT is a ARM Primecell Peripheral and has a standard-id register that
+can be used to identify the peripheral type, vendor, and revision.
+This value can be used for driver matching.
+
+As SP805 WDT is a primecell IP, it follows the base bindings specified in
+'arm/primecell.txt'
+
Required properties:
- compatible: Should be "arm,sp805" & "arm,primecell"
- reg: Should contain location and length for watchdog timer register.
-- interrupts: Should contain the list of watchdog timer interrupts.
- clocks: clocks driving the watchdog timer hardware. This list should be 2
- clocks. With 2 clocks, the order is wdogclk clock, apb_pclk.
+ clocks. With 2 clocks, the order is wdog_clk, apb_pclk.
+ wdog_clk can be equal to or be a sub-multiple of the apb_pclk frequency
+- clock-names : Shall be "wdog_clk" for first clock and "apb_pclk" for the
+ second one.
+
+Optional properties:
+- interrupts : Should specify WDT interrupt number.
Example:
watchdog@66090000 {
compatible = "arm,sp805", "arm,primecell";
reg = <0x66090000 0x1000>;
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&apb_pclk>,<&apb_pclk>;
- clock-names = "wdogclk", "apb_pclk";
+ clocks = <&wdt_clk>, <&apb_pclk>;
+ clock-names = "wdog_clk", "apb_pclk";
};
diff --git a/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt b/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt
deleted file mode 100644
index edc4f0e..0000000
--- a/Documentation/devicetree/bindings/watchdog/sp805-wdt.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-* ARM SP805 Watchdog Timer (WDT) Controller
-
-SP805 WDT is a ARM Primecell Peripheral and has a standard-id register that
-can be used to identify the peripheral type, vendor, and revision.
-This value can be used for driver matching.
-
-As SP805 WDT is a primecell IP, it follows the base bindings specified in
-'arm/primecell.txt'
-
-Required properties:
-- compatible : Should be "arm,sp805-wdt", "arm,primecell"
-- reg : Base address and size of the watchdog timer registers.
-- clocks : From common clock binding.
- First clock is PCLK and the second is WDOGCLK.
- WDOGCLK can be equal to or be a sub-multiple of the PCLK frequency.
-- clock-names : From common clock binding.
- Shall be "apb_pclk" for first clock and "wdog_clk" for the
- second one.
-
-Optional properties:
-- interrupts : Should specify WDT interrupt number.
-
-Examples:
-
- cluster1_core0_watchdog: wdt@c000000 {
- compatible = "arm,sp805-wdt", "arm,primecell";
- reg = <0x0 0xc000000 0x0 0x1000>;
- clocks = <&clockgen 4 3>, <&clockgen 4 3>;
- clock-names = "apb_pclk", "wdog_clk";
- };
-
--
2.1.4
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