* [PATCH 2/5] ptp_qoriq: move some definitions to header file
From: Yangbo Lu @ 2018-05-25 4:40 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel, Richard Cochran, claudiu.manoil,
Rob Herring
Cc: Yangbo Lu
In-Reply-To: <20180525044038.37756-1-yangbo.lu@nxp.com>
This patch is to move some definitions in ptp_qoriq.c
to the header file.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
drivers/ptp/ptp_qoriq.c | 132 +--------------------------------------
include/linux/fsl/ptp_qoriq.h | 141 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 142 insertions(+), 131 deletions(-)
create mode 100644 include/linux/fsl/ptp_qoriq.h
diff --git a/drivers/ptp/ptp_qoriq.c b/drivers/ptp/ptp_qoriq.c
index 5110cce..1468a16 100644
--- a/drivers/ptp/ptp_qoriq.c
+++ b/drivers/ptp/ptp_qoriq.c
@@ -28,139 +28,9 @@
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/timex.h>
-#include <linux/io.h>
#include <linux/slab.h>
-#include <linux/ptp_clock_kernel.h>
-
-/*
- * qoriq ptp registers
- * Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010
- */
-struct qoriq_ptp_registers {
- u32 tmr_ctrl; /* Timer control register */
- u32 tmr_tevent; /* Timestamp event register */
- u32 tmr_temask; /* Timer event mask register */
- u32 tmr_pevent; /* Timestamp event register */
- u32 tmr_pemask; /* Timer event mask register */
- u32 tmr_stat; /* Timestamp status register */
- u32 tmr_cnt_h; /* Timer counter high register */
- u32 tmr_cnt_l; /* Timer counter low register */
- u32 tmr_add; /* Timer drift compensation addend register */
- u32 tmr_acc; /* Timer accumulator register */
- u32 tmr_prsc; /* Timer prescale */
- u8 res1[4];
- u32 tmroff_h; /* Timer offset high */
- u32 tmroff_l; /* Timer offset low */
- u8 res2[8];
- u32 tmr_alarm1_h; /* Timer alarm 1 high register */
- u32 tmr_alarm1_l; /* Timer alarm 1 high register */
- u32 tmr_alarm2_h; /* Timer alarm 2 high register */
- u32 tmr_alarm2_l; /* Timer alarm 2 high register */
- u8 res3[48];
- u32 tmr_fiper1; /* Timer fixed period interval */
- u32 tmr_fiper2; /* Timer fixed period interval */
- u32 tmr_fiper3; /* Timer fixed period interval */
- u8 res4[20];
- u32 tmr_etts1_h; /* Timestamp of general purpose external trigger */
- u32 tmr_etts1_l; /* Timestamp of general purpose external trigger */
- u32 tmr_etts2_h; /* Timestamp of general purpose external trigger */
- u32 tmr_etts2_l; /* Timestamp of general purpose external trigger */
-};
-
-/* Bit definitions for the TMR_CTRL register */
-#define ALM1P (1<<31) /* Alarm1 output polarity */
-#define ALM2P (1<<30) /* Alarm2 output polarity */
-#define FIPERST (1<<28) /* FIPER start indication */
-#define PP1L (1<<27) /* Fiper1 pulse loopback mode enabled. */
-#define PP2L (1<<26) /* Fiper2 pulse loopback mode enabled. */
-#define TCLK_PERIOD_SHIFT (16) /* 1588 timer reference clock period. */
-#define TCLK_PERIOD_MASK (0x3ff)
-#define RTPE (1<<15) /* Record Tx Timestamp to PAL Enable. */
-#define FRD (1<<14) /* FIPER Realignment Disable */
-#define ESFDP (1<<11) /* External Tx/Rx SFD Polarity. */
-#define ESFDE (1<<10) /* External Tx/Rx SFD Enable. */
-#define ETEP2 (1<<9) /* External trigger 2 edge polarity */
-#define ETEP1 (1<<8) /* External trigger 1 edge polarity */
-#define COPH (1<<7) /* Generated clock output phase. */
-#define CIPH (1<<6) /* External oscillator input clock phase */
-#define TMSR (1<<5) /* Timer soft reset. */
-#define BYP (1<<3) /* Bypass drift compensated clock */
-#define TE (1<<2) /* 1588 timer enable. */
-#define CKSEL_SHIFT (0) /* 1588 Timer reference clock source */
-#define CKSEL_MASK (0x3)
-
-/* Bit definitions for the TMR_TEVENT register */
-#define ETS2 (1<<25) /* External trigger 2 timestamp sampled */
-#define ETS1 (1<<24) /* External trigger 1 timestamp sampled */
-#define ALM2 (1<<17) /* Current time = alarm time register 2 */
-#define ALM1 (1<<16) /* Current time = alarm time register 1 */
-#define PP1 (1<<7) /* periodic pulse generated on FIPER1 */
-#define PP2 (1<<6) /* periodic pulse generated on FIPER2 */
-#define PP3 (1<<5) /* periodic pulse generated on FIPER3 */
-
-/* Bit definitions for the TMR_TEMASK register */
-#define ETS2EN (1<<25) /* External trigger 2 timestamp enable */
-#define ETS1EN (1<<24) /* External trigger 1 timestamp enable */
-#define ALM2EN (1<<17) /* Timer ALM2 event enable */
-#define ALM1EN (1<<16) /* Timer ALM1 event enable */
-#define PP1EN (1<<7) /* Periodic pulse event 1 enable */
-#define PP2EN (1<<6) /* Periodic pulse event 2 enable */
-
-/* Bit definitions for the TMR_PEVENT register */
-#define TXP2 (1<<9) /* PTP transmitted timestamp im TXTS2 */
-#define TXP1 (1<<8) /* PTP transmitted timestamp in TXTS1 */
-#define RXP (1<<0) /* PTP frame has been received */
-
-/* Bit definitions for the TMR_PEMASK register */
-#define TXP2EN (1<<9) /* Transmit PTP packet event 2 enable */
-#define TXP1EN (1<<8) /* Transmit PTP packet event 1 enable */
-#define RXPEN (1<<0) /* Receive PTP packet event enable */
-
-/* Bit definitions for the TMR_STAT register */
-#define STAT_VEC_SHIFT (0) /* Timer general purpose status vector */
-#define STAT_VEC_MASK (0x3f)
-
-/* Bit definitions for the TMR_PRSC register */
-#define PRSC_OCK_SHIFT (0) /* Output clock division/prescale factor. */
-#define PRSC_OCK_MASK (0xffff)
-
-
-#define DRIVER "ptp_qoriq"
-#define DEFAULT_CKSEL 1
-#define N_EXT_TS 2
-#define REG_SIZE sizeof(struct qoriq_ptp_registers)
-
-struct qoriq_ptp {
- struct qoriq_ptp_registers __iomem *regs;
- spinlock_t lock; /* protects regs */
- struct ptp_clock *clock;
- struct ptp_clock_info caps;
- struct resource *rsrc;
- int irq;
- int phc_index;
- u64 alarm_interval; /* for periodic alarm */
- u64 alarm_value;
- u32 tclk_period; /* nanoseconds */
- u32 tmr_prsc;
- u32 tmr_add;
- u32 cksel;
- u32 tmr_fiper1;
- u32 tmr_fiper2;
-};
-
-static inline u32 qoriq_read(unsigned __iomem *addr)
-{
- u32 val;
-
- val = ioread32be(addr);
- return val;
-}
-
-static inline void qoriq_write(unsigned __iomem *addr, u32 val)
-{
- iowrite32be(val, addr);
-}
+#include <linux/fsl/ptp_qoriq.h>
/*
* Register access functions
diff --git a/include/linux/fsl/ptp_qoriq.h b/include/linux/fsl/ptp_qoriq.h
new file mode 100644
index 0000000..b462d9e
--- /dev/null
+++ b/include/linux/fsl/ptp_qoriq.h
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ * Copyright 2018 NXP
+ */
+#ifndef __PTP_QORIQ_H__
+#define __PTP_QORIQ_H__
+
+#include <linux/io.h>
+#include <linux/ptp_clock_kernel.h>
+
+/*
+ * qoriq ptp registers
+ * Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010
+ */
+struct qoriq_ptp_registers {
+ u32 tmr_ctrl; /* Timer control register */
+ u32 tmr_tevent; /* Timestamp event register */
+ u32 tmr_temask; /* Timer event mask register */
+ u32 tmr_pevent; /* Timestamp event register */
+ u32 tmr_pemask; /* Timer event mask register */
+ u32 tmr_stat; /* Timestamp status register */
+ u32 tmr_cnt_h; /* Timer counter high register */
+ u32 tmr_cnt_l; /* Timer counter low register */
+ u32 tmr_add; /* Timer drift compensation addend register */
+ u32 tmr_acc; /* Timer accumulator register */
+ u32 tmr_prsc; /* Timer prescale */
+ u8 res1[4];
+ u32 tmroff_h; /* Timer offset high */
+ u32 tmroff_l; /* Timer offset low */
+ u8 res2[8];
+ u32 tmr_alarm1_h; /* Timer alarm 1 high register */
+ u32 tmr_alarm1_l; /* Timer alarm 1 high register */
+ u32 tmr_alarm2_h; /* Timer alarm 2 high register */
+ u32 tmr_alarm2_l; /* Timer alarm 2 high register */
+ u8 res3[48];
+ u32 tmr_fiper1; /* Timer fixed period interval */
+ u32 tmr_fiper2; /* Timer fixed period interval */
+ u32 tmr_fiper3; /* Timer fixed period interval */
+ u8 res4[20];
+ u32 tmr_etts1_h; /* Timestamp of general purpose external trigger */
+ u32 tmr_etts1_l; /* Timestamp of general purpose external trigger */
+ u32 tmr_etts2_h; /* Timestamp of general purpose external trigger */
+ u32 tmr_etts2_l; /* Timestamp of general purpose external trigger */
+};
+
+/* Bit definitions for the TMR_CTRL register */
+#define ALM1P (1<<31) /* Alarm1 output polarity */
+#define ALM2P (1<<30) /* Alarm2 output polarity */
+#define FIPERST (1<<28) /* FIPER start indication */
+#define PP1L (1<<27) /* Fiper1 pulse loopback mode enabled. */
+#define PP2L (1<<26) /* Fiper2 pulse loopback mode enabled. */
+#define TCLK_PERIOD_SHIFT (16) /* 1588 timer reference clock period. */
+#define TCLK_PERIOD_MASK (0x3ff)
+#define RTPE (1<<15) /* Record Tx Timestamp to PAL Enable. */
+#define FRD (1<<14) /* FIPER Realignment Disable */
+#define ESFDP (1<<11) /* External Tx/Rx SFD Polarity. */
+#define ESFDE (1<<10) /* External Tx/Rx SFD Enable. */
+#define ETEP2 (1<<9) /* External trigger 2 edge polarity */
+#define ETEP1 (1<<8) /* External trigger 1 edge polarity */
+#define COPH (1<<7) /* Generated clock output phase. */
+#define CIPH (1<<6) /* External oscillator input clock phase */
+#define TMSR (1<<5) /* Timer soft reset. */
+#define BYP (1<<3) /* Bypass drift compensated clock */
+#define TE (1<<2) /* 1588 timer enable. */
+#define CKSEL_SHIFT (0) /* 1588 Timer reference clock source */
+#define CKSEL_MASK (0x3)
+
+/* Bit definitions for the TMR_TEVENT register */
+#define ETS2 (1<<25) /* External trigger 2 timestamp sampled */
+#define ETS1 (1<<24) /* External trigger 1 timestamp sampled */
+#define ALM2 (1<<17) /* Current time = alarm time register 2 */
+#define ALM1 (1<<16) /* Current time = alarm time register 1 */
+#define PP1 (1<<7) /* periodic pulse generated on FIPER1 */
+#define PP2 (1<<6) /* periodic pulse generated on FIPER2 */
+#define PP3 (1<<5) /* periodic pulse generated on FIPER3 */
+
+/* Bit definitions for the TMR_TEMASK register */
+#define ETS2EN (1<<25) /* External trigger 2 timestamp enable */
+#define ETS1EN (1<<24) /* External trigger 1 timestamp enable */
+#define ALM2EN (1<<17) /* Timer ALM2 event enable */
+#define ALM1EN (1<<16) /* Timer ALM1 event enable */
+#define PP1EN (1<<7) /* Periodic pulse event 1 enable */
+#define PP2EN (1<<6) /* Periodic pulse event 2 enable */
+
+/* Bit definitions for the TMR_PEVENT register */
+#define TXP2 (1<<9) /* PTP transmitted timestamp im TXTS2 */
+#define TXP1 (1<<8) /* PTP transmitted timestamp in TXTS1 */
+#define RXP (1<<0) /* PTP frame has been received */
+
+/* Bit definitions for the TMR_PEMASK register */
+#define TXP2EN (1<<9) /* Transmit PTP packet event 2 enable */
+#define TXP1EN (1<<8) /* Transmit PTP packet event 1 enable */
+#define RXPEN (1<<0) /* Receive PTP packet event enable */
+
+/* Bit definitions for the TMR_STAT register */
+#define STAT_VEC_SHIFT (0) /* Timer general purpose status vector */
+#define STAT_VEC_MASK (0x3f)
+
+/* Bit definitions for the TMR_PRSC register */
+#define PRSC_OCK_SHIFT (0) /* Output clock division/prescale factor. */
+#define PRSC_OCK_MASK (0xffff)
+
+
+#define DRIVER "ptp_qoriq"
+#define DEFAULT_CKSEL 1
+#define N_EXT_TS 2
+#define REG_SIZE sizeof(struct qoriq_ptp_registers)
+
+struct qoriq_ptp {
+ struct qoriq_ptp_registers __iomem *regs;
+ spinlock_t lock; /* protects regs */
+ struct ptp_clock *clock;
+ struct ptp_clock_info caps;
+ struct resource *rsrc;
+ int irq;
+ int phc_index;
+ u64 alarm_interval; /* for periodic alarm */
+ u64 alarm_value;
+ u32 tclk_period; /* nanoseconds */
+ u32 tmr_prsc;
+ u32 tmr_add;
+ u32 cksel;
+ u32 tmr_fiper1;
+ u32 tmr_fiper2;
+};
+
+static inline u32 qoriq_read(unsigned __iomem *addr)
+{
+ u32 val;
+
+ val = ioread32be(addr);
+ return val;
+}
+
+static inline void qoriq_write(unsigned __iomem *addr, u32 val)
+{
+ iowrite32be(val, addr);
+}
+
+#endif
--
1.7.1
^ permalink raw reply related
* [PATCH 1/5] ptp: rework gianfar_ptp as QorIQ common PTP driver
From: Yangbo Lu @ 2018-05-25 4:40 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel, Richard Cochran, claudiu.manoil,
Rob Herring
Cc: Yangbo Lu
gianfar_ptp was the PTP clock driver for 1588 timer
module of Freescale QorIQ eTSEC (Enhanced Three-Speed
Ethernet Controllers) platforms. Actually QorIQ DPAA
(Data Path Acceleration Architecture) platforms is
also using the same 1588 timer module in hardware.
This patch is to rework gianfar_ptp as QorIQ common
PTP driver to support both DPAA and eTSEC. Moved
gianfar_ptp.c to drivers/ptp/, renamed it as
ptp_qoriq.c, and renamed many variables. There were
not any function changes.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
drivers/net/ethernet/freescale/Makefile | 1 -
drivers/ptp/Kconfig | 14 +-
drivers/ptp/Makefile | 1 +
.../freescale/gianfar_ptp.c => ptp/ptp_qoriq.c} | 320 ++++++++++----------
4 files changed, 174 insertions(+), 162 deletions(-)
rename drivers/{net/ethernet/freescale/gianfar_ptp.c => ptp/ptp_qoriq.c} (58%)
diff --git a/drivers/net/ethernet/freescale/Makefile b/drivers/net/ethernet/freescale/Makefile
index ed8ad0f..0914a3e 100644
--- a/drivers/net/ethernet/freescale/Makefile
+++ b/drivers/net/ethernet/freescale/Makefile
@@ -14,7 +14,6 @@ obj-$(CONFIG_FS_ENET) += fs_enet/
obj-$(CONFIG_FSL_PQ_MDIO) += fsl_pq_mdio.o
obj-$(CONFIG_FSL_XGMAC_MDIO) += xgmac_mdio.o
obj-$(CONFIG_GIANFAR) += gianfar_driver.o
-obj-$(CONFIG_PTP_1588_CLOCK_GIANFAR) += gianfar_ptp.o
gianfar_driver-objs := gianfar.o \
gianfar_ethtool.o
obj-$(CONFIG_UCC_GETH) += ucc_geth_driver.o
diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
index a21ad10..474c988 100644
--- a/drivers/ptp/Kconfig
+++ b/drivers/ptp/Kconfig
@@ -41,19 +41,19 @@ config PTP_1588_CLOCK_DTE
To compile this driver as a module, choose M here: the module
will be called ptp_dte.
-config PTP_1588_CLOCK_GIANFAR
- tristate "Freescale eTSEC as PTP clock"
+config PTP_1588_CLOCK_QORIQ
+ tristate "Freescale QorIQ 1588 timer as PTP clock"
depends on GIANFAR
depends on PTP_1588_CLOCK
default y
help
- This driver adds support for using the eTSEC as a PTP
- clock. This clock is only useful if your PTP programs are
- getting hardware time stamps on the PTP Ethernet packets
- using the SO_TIMESTAMPING API.
+ This driver adds support for using the Freescale QorIQ 1588
+ timer as a PTP clock. This clock is only useful if your PTP
+ programs are getting hardware time stamps on the PTP Ethernet
+ packets using the SO_TIMESTAMPING API.
To compile this driver as a module, choose M here: the module
- will be called gianfar_ptp.
+ will be called ptp_qoriq.
config PTP_1588_CLOCK_IXP46X
tristate "Intel IXP46x as PTP clock"
diff --git a/drivers/ptp/Makefile b/drivers/ptp/Makefile
index fd28207..19efa9c 100644
--- a/drivers/ptp/Makefile
+++ b/drivers/ptp/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_PTP_1588_CLOCK_DTE) += ptp_dte.o
obj-$(CONFIG_PTP_1588_CLOCK_IXP46X) += ptp_ixp46x.o
obj-$(CONFIG_PTP_1588_CLOCK_PCH) += ptp_pch.o
obj-$(CONFIG_PTP_1588_CLOCK_KVM) += ptp_kvm.o
+obj-$(CONFIG_PTP_1588_CLOCK_QORIQ) += ptp_qoriq.o
diff --git a/drivers/net/ethernet/freescale/gianfar_ptp.c b/drivers/ptp/ptp_qoriq.c
similarity index 58%
rename from drivers/net/ethernet/freescale/gianfar_ptp.c
rename to drivers/ptp/ptp_qoriq.c
index 9f8d4f8..5110cce 100644
--- a/drivers/net/ethernet/freescale/gianfar_ptp.c
+++ b/drivers/ptp/ptp_qoriq.c
@@ -1,5 +1,5 @@
/*
- * PTP 1588 clock using the eTSEC
+ * PTP 1588 clock for Freescale QorIQ 1588 timer
*
* Copyright (C) 2010 OMICRON electronics GmbH
*
@@ -29,16 +29,15 @@
#include <linux/of_platform.h>
#include <linux/timex.h>
#include <linux/io.h>
+#include <linux/slab.h>
#include <linux/ptp_clock_kernel.h>
-#include "gianfar.h"
-
/*
- * gianfar ptp registers
+ * qoriq ptp registers
* Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010
*/
-struct gianfar_ptp_registers {
+struct qoriq_ptp_registers {
u32 tmr_ctrl; /* Timer control register */
u32 tmr_tevent; /* Timestamp event register */
u32 tmr_temask; /* Timer event mask register */
@@ -127,18 +126,19 @@ struct gianfar_ptp_registers {
#define PRSC_OCK_MASK (0xffff)
-#define DRIVER "gianfar_ptp"
+#define DRIVER "ptp_qoriq"
#define DEFAULT_CKSEL 1
#define N_EXT_TS 2
-#define REG_SIZE sizeof(struct gianfar_ptp_registers)
+#define REG_SIZE sizeof(struct qoriq_ptp_registers)
-struct etsects {
- struct gianfar_ptp_registers __iomem *regs;
+struct qoriq_ptp {
+ struct qoriq_ptp_registers __iomem *regs;
spinlock_t lock; /* protects regs */
struct ptp_clock *clock;
struct ptp_clock_info caps;
struct resource *rsrc;
int irq;
+ int phc_index;
u64 alarm_interval; /* for periodic alarm */
u64 alarm_value;
u32 tclk_period; /* nanoseconds */
@@ -149,54 +149,67 @@ struct etsects {
u32 tmr_fiper2;
};
+static inline u32 qoriq_read(unsigned __iomem *addr)
+{
+ u32 val;
+
+ val = ioread32be(addr);
+ return val;
+}
+
+static inline void qoriq_write(unsigned __iomem *addr, u32 val)
+{
+ iowrite32be(val, addr);
+}
+
/*
* Register access functions
*/
-/* Caller must hold etsects->lock. */
-static u64 tmr_cnt_read(struct etsects *etsects)
+/* Caller must hold qoriq_ptp->lock. */
+static u64 tmr_cnt_read(struct qoriq_ptp *qoriq_ptp)
{
u64 ns;
u32 lo, hi;
- lo = gfar_read(&etsects->regs->tmr_cnt_l);
- hi = gfar_read(&etsects->regs->tmr_cnt_h);
+ lo = qoriq_read(&qoriq_ptp->regs->tmr_cnt_l);
+ hi = qoriq_read(&qoriq_ptp->regs->tmr_cnt_h);
ns = ((u64) hi) << 32;
ns |= lo;
return ns;
}
-/* Caller must hold etsects->lock. */
-static void tmr_cnt_write(struct etsects *etsects, u64 ns)
+/* Caller must hold qoriq_ptp->lock. */
+static void tmr_cnt_write(struct qoriq_ptp *qoriq_ptp, u64 ns)
{
u32 hi = ns >> 32;
u32 lo = ns & 0xffffffff;
- gfar_write(&etsects->regs->tmr_cnt_l, lo);
- gfar_write(&etsects->regs->tmr_cnt_h, hi);
+ qoriq_write(&qoriq_ptp->regs->tmr_cnt_l, lo);
+ qoriq_write(&qoriq_ptp->regs->tmr_cnt_h, hi);
}
-/* Caller must hold etsects->lock. */
-static void set_alarm(struct etsects *etsects)
+/* Caller must hold qoriq_ptp->lock. */
+static void set_alarm(struct qoriq_ptp *qoriq_ptp)
{
u64 ns;
u32 lo, hi;
- ns = tmr_cnt_read(etsects) + 1500000000ULL;
+ ns = tmr_cnt_read(qoriq_ptp) + 1500000000ULL;
ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
- ns -= etsects->tclk_period;
+ ns -= qoriq_ptp->tclk_period;
hi = ns >> 32;
lo = ns & 0xffffffff;
- gfar_write(&etsects->regs->tmr_alarm1_l, lo);
- gfar_write(&etsects->regs->tmr_alarm1_h, hi);
+ qoriq_write(&qoriq_ptp->regs->tmr_alarm1_l, lo);
+ qoriq_write(&qoriq_ptp->regs->tmr_alarm1_h, hi);
}
-/* Caller must hold etsects->lock. */
-static void set_fipers(struct etsects *etsects)
+/* Caller must hold qoriq_ptp->lock. */
+static void set_fipers(struct qoriq_ptp *qoriq_ptp)
{
- set_alarm(etsects);
- gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
- gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
+ set_alarm(qoriq_ptp);
+ qoriq_write(&qoriq_ptp->regs->tmr_fiper1, qoriq_ptp->tmr_fiper1);
+ qoriq_write(&qoriq_ptp->regs->tmr_fiper2, qoriq_ptp->tmr_fiper2);
}
/*
@@ -205,72 +218,72 @@ static void set_fipers(struct etsects *etsects)
static irqreturn_t isr(int irq, void *priv)
{
- struct etsects *etsects = priv;
+ struct qoriq_ptp *qoriq_ptp = priv;
struct ptp_clock_event event;
u64 ns;
u32 ack = 0, lo, hi, mask, val;
- val = gfar_read(&etsects->regs->tmr_tevent);
+ val = qoriq_read(&qoriq_ptp->regs->tmr_tevent);
if (val & ETS1) {
ack |= ETS1;
- hi = gfar_read(&etsects->regs->tmr_etts1_h);
- lo = gfar_read(&etsects->regs->tmr_etts1_l);
+ hi = qoriq_read(&qoriq_ptp->regs->tmr_etts1_h);
+ lo = qoriq_read(&qoriq_ptp->regs->tmr_etts1_l);
event.type = PTP_CLOCK_EXTTS;
event.index = 0;
event.timestamp = ((u64) hi) << 32;
event.timestamp |= lo;
- ptp_clock_event(etsects->clock, &event);
+ ptp_clock_event(qoriq_ptp->clock, &event);
}
if (val & ETS2) {
ack |= ETS2;
- hi = gfar_read(&etsects->regs->tmr_etts2_h);
- lo = gfar_read(&etsects->regs->tmr_etts2_l);
+ hi = qoriq_read(&qoriq_ptp->regs->tmr_etts2_h);
+ lo = qoriq_read(&qoriq_ptp->regs->tmr_etts2_l);
event.type = PTP_CLOCK_EXTTS;
event.index = 1;
event.timestamp = ((u64) hi) << 32;
event.timestamp |= lo;
- ptp_clock_event(etsects->clock, &event);
+ ptp_clock_event(qoriq_ptp->clock, &event);
}
if (val & ALM2) {
ack |= ALM2;
- if (etsects->alarm_value) {
+ if (qoriq_ptp->alarm_value) {
event.type = PTP_CLOCK_ALARM;
event.index = 0;
- event.timestamp = etsects->alarm_value;
- ptp_clock_event(etsects->clock, &event);
+ event.timestamp = qoriq_ptp->alarm_value;
+ ptp_clock_event(qoriq_ptp->clock, &event);
}
- if (etsects->alarm_interval) {
- ns = etsects->alarm_value + etsects->alarm_interval;
+ if (qoriq_ptp->alarm_interval) {
+ ns = qoriq_ptp->alarm_value + qoriq_ptp->alarm_interval;
hi = ns >> 32;
lo = ns & 0xffffffff;
- spin_lock(&etsects->lock);
- gfar_write(&etsects->regs->tmr_alarm2_l, lo);
- gfar_write(&etsects->regs->tmr_alarm2_h, hi);
- spin_unlock(&etsects->lock);
- etsects->alarm_value = ns;
+ spin_lock(&qoriq_ptp->lock);
+ qoriq_write(&qoriq_ptp->regs->tmr_alarm2_l, lo);
+ qoriq_write(&qoriq_ptp->regs->tmr_alarm2_h, hi);
+ spin_unlock(&qoriq_ptp->lock);
+ qoriq_ptp->alarm_value = ns;
} else {
- gfar_write(&etsects->regs->tmr_tevent, ALM2);
- spin_lock(&etsects->lock);
- mask = gfar_read(&etsects->regs->tmr_temask);
+ qoriq_write(&qoriq_ptp->regs->tmr_tevent, ALM2);
+ spin_lock(&qoriq_ptp->lock);
+ mask = qoriq_read(&qoriq_ptp->regs->tmr_temask);
mask &= ~ALM2EN;
- gfar_write(&etsects->regs->tmr_temask, mask);
- spin_unlock(&etsects->lock);
- etsects->alarm_value = 0;
- etsects->alarm_interval = 0;
+ qoriq_write(&qoriq_ptp->regs->tmr_temask, mask);
+ spin_unlock(&qoriq_ptp->lock);
+ qoriq_ptp->alarm_value = 0;
+ qoriq_ptp->alarm_interval = 0;
}
}
if (val & PP1) {
ack |= PP1;
event.type = PTP_CLOCK_PPS;
- ptp_clock_event(etsects->clock, &event);
+ ptp_clock_event(qoriq_ptp->clock, &event);
}
if (ack) {
- gfar_write(&etsects->regs->tmr_tevent, ack);
+ qoriq_write(&qoriq_ptp->regs->tmr_tevent, ack);
return IRQ_HANDLED;
} else
return IRQ_NONE;
@@ -280,18 +293,18 @@ static irqreturn_t isr(int irq, void *priv)
* PTP clock operations
*/
-static int ptp_gianfar_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
+static int ptp_qoriq_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
{
u64 adj, diff;
u32 tmr_add;
int neg_adj = 0;
- struct etsects *etsects = container_of(ptp, struct etsects, caps);
+ struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
if (scaled_ppm < 0) {
neg_adj = 1;
scaled_ppm = -scaled_ppm;
}
- tmr_add = etsects->tmr_add;
+ tmr_add = qoriq_ptp->tmr_add;
adj = tmr_add;
/* calculate diff as adj*(scaled_ppm/65536)/1000000
@@ -303,70 +316,70 @@ static int ptp_gianfar_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
- gfar_write(&etsects->regs->tmr_add, tmr_add);
+ qoriq_write(&qoriq_ptp->regs->tmr_add, tmr_add);
return 0;
}
-static int ptp_gianfar_adjtime(struct ptp_clock_info *ptp, s64 delta)
+static int ptp_qoriq_adjtime(struct ptp_clock_info *ptp, s64 delta)
{
s64 now;
unsigned long flags;
- struct etsects *etsects = container_of(ptp, struct etsects, caps);
+ struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
- spin_lock_irqsave(&etsects->lock, flags);
+ spin_lock_irqsave(&qoriq_ptp->lock, flags);
- now = tmr_cnt_read(etsects);
+ now = tmr_cnt_read(qoriq_ptp);
now += delta;
- tmr_cnt_write(etsects, now);
- set_fipers(etsects);
+ tmr_cnt_write(qoriq_ptp, now);
+ set_fipers(qoriq_ptp);
- spin_unlock_irqrestore(&etsects->lock, flags);
+ spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
return 0;
}
-static int ptp_gianfar_gettime(struct ptp_clock_info *ptp,
+static int ptp_qoriq_gettime(struct ptp_clock_info *ptp,
struct timespec64 *ts)
{
u64 ns;
unsigned long flags;
- struct etsects *etsects = container_of(ptp, struct etsects, caps);
+ struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
- spin_lock_irqsave(&etsects->lock, flags);
+ spin_lock_irqsave(&qoriq_ptp->lock, flags);
- ns = tmr_cnt_read(etsects);
+ ns = tmr_cnt_read(qoriq_ptp);
- spin_unlock_irqrestore(&etsects->lock, flags);
+ spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
*ts = ns_to_timespec64(ns);
return 0;
}
-static int ptp_gianfar_settime(struct ptp_clock_info *ptp,
+static int ptp_qoriq_settime(struct ptp_clock_info *ptp,
const struct timespec64 *ts)
{
u64 ns;
unsigned long flags;
- struct etsects *etsects = container_of(ptp, struct etsects, caps);
+ struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
ns = timespec64_to_ns(ts);
- spin_lock_irqsave(&etsects->lock, flags);
+ spin_lock_irqsave(&qoriq_ptp->lock, flags);
- tmr_cnt_write(etsects, ns);
- set_fipers(etsects);
+ tmr_cnt_write(qoriq_ptp, ns);
+ set_fipers(qoriq_ptp);
- spin_unlock_irqrestore(&etsects->lock, flags);
+ spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
return 0;
}
-static int ptp_gianfar_enable(struct ptp_clock_info *ptp,
+static int ptp_qoriq_enable(struct ptp_clock_info *ptp,
struct ptp_clock_request *rq, int on)
{
- struct etsects *etsects = container_of(ptp, struct etsects, caps);
+ struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
unsigned long flags;
u32 bit, mask;
@@ -382,25 +395,25 @@ static int ptp_gianfar_enable(struct ptp_clock_info *ptp,
default:
return -EINVAL;
}
- spin_lock_irqsave(&etsects->lock, flags);
- mask = gfar_read(&etsects->regs->tmr_temask);
+ spin_lock_irqsave(&qoriq_ptp->lock, flags);
+ mask = qoriq_read(&qoriq_ptp->regs->tmr_temask);
if (on)
mask |= bit;
else
mask &= ~bit;
- gfar_write(&etsects->regs->tmr_temask, mask);
- spin_unlock_irqrestore(&etsects->lock, flags);
+ qoriq_write(&qoriq_ptp->regs->tmr_temask, mask);
+ spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
return 0;
case PTP_CLK_REQ_PPS:
- spin_lock_irqsave(&etsects->lock, flags);
- mask = gfar_read(&etsects->regs->tmr_temask);
+ spin_lock_irqsave(&qoriq_ptp->lock, flags);
+ mask = qoriq_read(&qoriq_ptp->regs->tmr_temask);
if (on)
mask |= PP1EN;
else
mask &= ~PP1EN;
- gfar_write(&etsects->regs->tmr_temask, mask);
- spin_unlock_irqrestore(&etsects->lock, flags);
+ qoriq_write(&qoriq_ptp->regs->tmr_temask, mask);
+ spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
return 0;
default:
@@ -410,142 +423,141 @@ static int ptp_gianfar_enable(struct ptp_clock_info *ptp,
return -EOPNOTSUPP;
}
-static const struct ptp_clock_info ptp_gianfar_caps = {
+static const struct ptp_clock_info ptp_qoriq_caps = {
.owner = THIS_MODULE,
- .name = "gianfar clock",
+ .name = "qoriq ptp clock",
.max_adj = 512000,
.n_alarm = 0,
.n_ext_ts = N_EXT_TS,
.n_per_out = 0,
.n_pins = 0,
.pps = 1,
- .adjfine = ptp_gianfar_adjfine,
- .adjtime = ptp_gianfar_adjtime,
- .gettime64 = ptp_gianfar_gettime,
- .settime64 = ptp_gianfar_settime,
- .enable = ptp_gianfar_enable,
+ .adjfine = ptp_qoriq_adjfine,
+ .adjtime = ptp_qoriq_adjtime,
+ .gettime64 = ptp_qoriq_gettime,
+ .settime64 = ptp_qoriq_settime,
+ .enable = ptp_qoriq_enable,
};
-static int gianfar_ptp_probe(struct platform_device *dev)
+static int qoriq_ptp_probe(struct platform_device *dev)
{
struct device_node *node = dev->dev.of_node;
- struct etsects *etsects;
+ struct qoriq_ptp *qoriq_ptp;
struct timespec64 now;
int err = -ENOMEM;
u32 tmr_ctrl;
unsigned long flags;
- etsects = kzalloc(sizeof(*etsects), GFP_KERNEL);
- if (!etsects)
+ qoriq_ptp = kzalloc(sizeof(*qoriq_ptp), GFP_KERNEL);
+ if (!qoriq_ptp)
goto no_memory;
err = -ENODEV;
- etsects->caps = ptp_gianfar_caps;
+ qoriq_ptp->caps = ptp_qoriq_caps;
- if (of_property_read_u32(node, "fsl,cksel", &etsects->cksel))
- etsects->cksel = DEFAULT_CKSEL;
+ if (of_property_read_u32(node, "fsl,cksel", &qoriq_ptp->cksel))
+ qoriq_ptp->cksel = DEFAULT_CKSEL;
if (of_property_read_u32(node,
- "fsl,tclk-period", &etsects->tclk_period) ||
+ "fsl,tclk-period", &qoriq_ptp->tclk_period) ||
of_property_read_u32(node,
- "fsl,tmr-prsc", &etsects->tmr_prsc) ||
+ "fsl,tmr-prsc", &qoriq_ptp->tmr_prsc) ||
of_property_read_u32(node,
- "fsl,tmr-add", &etsects->tmr_add) ||
+ "fsl,tmr-add", &qoriq_ptp->tmr_add) ||
of_property_read_u32(node,
- "fsl,tmr-fiper1", &etsects->tmr_fiper1) ||
+ "fsl,tmr-fiper1", &qoriq_ptp->tmr_fiper1) ||
of_property_read_u32(node,
- "fsl,tmr-fiper2", &etsects->tmr_fiper2) ||
+ "fsl,tmr-fiper2", &qoriq_ptp->tmr_fiper2) ||
of_property_read_u32(node,
- "fsl,max-adj", &etsects->caps.max_adj)) {
+ "fsl,max-adj", &qoriq_ptp->caps.max_adj)) {
pr_err("device tree node missing required elements\n");
goto no_node;
}
- etsects->irq = platform_get_irq(dev, 0);
+ qoriq_ptp->irq = platform_get_irq(dev, 0);
- if (etsects->irq < 0) {
+ if (qoriq_ptp->irq < 0) {
pr_err("irq not in device tree\n");
goto no_node;
}
- if (request_irq(etsects->irq, isr, 0, DRIVER, etsects)) {
+ if (request_irq(qoriq_ptp->irq, isr, 0, DRIVER, qoriq_ptp)) {
pr_err("request_irq failed\n");
goto no_node;
}
- etsects->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0);
- if (!etsects->rsrc) {
+ qoriq_ptp->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0);
+ if (!qoriq_ptp->rsrc) {
pr_err("no resource\n");
goto no_resource;
}
- if (request_resource(&iomem_resource, etsects->rsrc)) {
+ if (request_resource(&iomem_resource, qoriq_ptp->rsrc)) {
pr_err("resource busy\n");
goto no_resource;
}
- spin_lock_init(&etsects->lock);
+ spin_lock_init(&qoriq_ptp->lock);
- etsects->regs = ioremap(etsects->rsrc->start,
- resource_size(etsects->rsrc));
- if (!etsects->regs) {
+ qoriq_ptp->regs = ioremap(qoriq_ptp->rsrc->start,
+ resource_size(qoriq_ptp->rsrc));
+ if (!qoriq_ptp->regs) {
pr_err("ioremap ptp registers failed\n");
goto no_ioremap;
}
getnstimeofday64(&now);
- ptp_gianfar_settime(&etsects->caps, &now);
+ ptp_qoriq_settime(&qoriq_ptp->caps, &now);
tmr_ctrl =
- (etsects->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
- (etsects->cksel & CKSEL_MASK) << CKSEL_SHIFT;
+ (qoriq_ptp->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
+ (qoriq_ptp->cksel & CKSEL_MASK) << CKSEL_SHIFT;
- spin_lock_irqsave(&etsects->lock, flags);
+ spin_lock_irqsave(&qoriq_ptp->lock, flags);
- gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl);
- gfar_write(&etsects->regs->tmr_add, etsects->tmr_add);
- gfar_write(&etsects->regs->tmr_prsc, etsects->tmr_prsc);
- gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
- gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
- set_alarm(etsects);
- gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl|FIPERST|RTPE|TE|FRD);
+ qoriq_write(&qoriq_ptp->regs->tmr_ctrl, tmr_ctrl);
+ qoriq_write(&qoriq_ptp->regs->tmr_add, qoriq_ptp->tmr_add);
+ qoriq_write(&qoriq_ptp->regs->tmr_prsc, qoriq_ptp->tmr_prsc);
+ qoriq_write(&qoriq_ptp->regs->tmr_fiper1, qoriq_ptp->tmr_fiper1);
+ qoriq_write(&qoriq_ptp->regs->tmr_fiper2, qoriq_ptp->tmr_fiper2);
+ set_alarm(qoriq_ptp);
+ qoriq_write(&qoriq_ptp->regs->tmr_ctrl, tmr_ctrl|FIPERST|RTPE|TE|FRD);
- spin_unlock_irqrestore(&etsects->lock, flags);
+ spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
- etsects->clock = ptp_clock_register(&etsects->caps, &dev->dev);
- if (IS_ERR(etsects->clock)) {
- err = PTR_ERR(etsects->clock);
+ qoriq_ptp->clock = ptp_clock_register(&qoriq_ptp->caps, &dev->dev);
+ if (IS_ERR(qoriq_ptp->clock)) {
+ err = PTR_ERR(qoriq_ptp->clock);
goto no_clock;
}
- gfar_phc_index = ptp_clock_index(etsects->clock);
+ qoriq_ptp->phc_index = ptp_clock_index(qoriq_ptp->clock);
- platform_set_drvdata(dev, etsects);
+ platform_set_drvdata(dev, qoriq_ptp);
return 0;
no_clock:
- iounmap(etsects->regs);
+ iounmap(qoriq_ptp->regs);
no_ioremap:
- release_resource(etsects->rsrc);
+ release_resource(qoriq_ptp->rsrc);
no_resource:
- free_irq(etsects->irq, etsects);
+ free_irq(qoriq_ptp->irq, qoriq_ptp);
no_node:
- kfree(etsects);
+ kfree(qoriq_ptp);
no_memory:
return err;
}
-static int gianfar_ptp_remove(struct platform_device *dev)
+static int qoriq_ptp_remove(struct platform_device *dev)
{
- struct etsects *etsects = platform_get_drvdata(dev);
+ struct qoriq_ptp *qoriq_ptp = platform_get_drvdata(dev);
- gfar_write(&etsects->regs->tmr_temask, 0);
- gfar_write(&etsects->regs->tmr_ctrl, 0);
+ qoriq_write(&qoriq_ptp->regs->tmr_temask, 0);
+ qoriq_write(&qoriq_ptp->regs->tmr_ctrl, 0);
- gfar_phc_index = -1;
- ptp_clock_unregister(etsects->clock);
- iounmap(etsects->regs);
- release_resource(etsects->rsrc);
- free_irq(etsects->irq, etsects);
- kfree(etsects);
+ ptp_clock_unregister(qoriq_ptp->clock);
+ iounmap(qoriq_ptp->regs);
+ release_resource(qoriq_ptp->rsrc);
+ free_irq(qoriq_ptp->irq, qoriq_ptp);
+ kfree(qoriq_ptp);
return 0;
}
@@ -556,17 +568,17 @@ static int gianfar_ptp_remove(struct platform_device *dev)
};
MODULE_DEVICE_TABLE(of, match_table);
-static struct platform_driver gianfar_ptp_driver = {
+static struct platform_driver qoriq_ptp_driver = {
.driver = {
- .name = "gianfar_ptp",
+ .name = "ptp_qoriq",
.of_match_table = match_table,
},
- .probe = gianfar_ptp_probe,
- .remove = gianfar_ptp_remove,
+ .probe = qoriq_ptp_probe,
+ .remove = qoriq_ptp_remove,
};
-module_platform_driver(gianfar_ptp_driver);
+module_platform_driver(qoriq_ptp_driver);
MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
-MODULE_DESCRIPTION("PTP clock using the eTSEC");
+MODULE_DESCRIPTION("PTP clock for Freescale QorIQ 1588 timer");
MODULE_LICENSE("GPL");
--
1.7.1
^ permalink raw reply related
* Re: [PATCH v6 05/17] media: rkisp1: add Rockchip ISP1 subdev driver
From: Tomasz Figa @ 2018-05-25 4:35 UTC (permalink / raw)
To: baruch-NswTu9S1W3P6gbPvEgmw2w
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Eddie Cai, 陈城,
Heiko Stübner, Jeffy, 钟以崇,
Linux Kernel Mailing List, open list:ARM/Rockchip SoC...,
open list:IOMMU DRIVERS, Jacob Chen, Hans Verkuil,
Laurent Pinchart, Allon Huang, Mauro Carvalho Chehab,
Shunqian Zheng,
list-Y9sIeH5OGRo@public.gmane.org:IOMMU DRIVERS <iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org>, Joerg Roedel <joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org>, ,
Linux Media Mailing List
In-Reply-To: <20180524113012.mt5b2f2vrhfrn3d7@tarshish>
On Thu, May 24, 2018 at 8:30 PM Baruch Siach <baruch-NswTu9S1W3P6gbPvEgmw2w@public.gmane.org> wrote:
> Hi Tomasz,
> On Mon, May 07, 2018 at 06:41:50AM +0000, Tomasz Figa wrote:
> > On Mon, May 7, 2018 at 3:38 PM Baruch Siach <baruch-NswTu9S1W3P6gbPvEgmw2w@public.gmane.org> wrote:
> > > On Mon, May 07, 2018 at 06:13:27AM +0000, Tomasz Figa wrote:
> > > > On Thu, May 3, 2018 at 6:09 PM Baruch Siach <baruch-NswTu9S1W3P6gbPvEgmw2w@public.gmane.org>
wrote:
> > > > > On Thu, Mar 08, 2018 at 05:47:55PM +0800, Jacob Chen wrote:
> > > > > > +static int rkisp1_isp_sd_s_power(struct v4l2_subdev *sd, int
on)
> > > > > > +{
> > > > > > + struct rkisp1_device *isp_dev = sd_to_isp_dev(sd);
> > > > > > + int ret;
> > > > > > +
> > > > > > + v4l2_dbg(1, rkisp1_debug, &isp_dev->v4l2_dev, "s_power:
%d\n",
> > > > on);
> > > > > > +
> > > > > > + if (on) {
> > > > > > + ret = pm_runtime_get_sync(isp_dev->dev);
> > > > > > + if (ret < 0)
> > > > > > + return ret;
> > > > > > +
> > > > > > + rkisp1_config_clk(isp_dev);
> > > > > > + } else {
> > > > > > + ret = pm_runtime_put(isp_dev->dev);
> > > >
> > > > > I commented this line out to make more than one STREAMON work.
> > Otherwise,
> > > > > the second STREAMON hangs. I guess the bug is not this driver.
> > Probably
> > > > > something in drivers/soc/rockchip/pm_domains.c. Just noting that
in
> > case
> > > > > you or someone on Cc would like to investigate it further.
> > > > >
> > > > > I tested v4.16-rc4 on the Tinkerboard.
> > > >
> > > > Looks like that version doesn't include the IOMMU PM and clock
handling
> > > > rework [1], which should fix a lot of runtime PM issues. FWIW,
> > linux-next
> > > > seems to already include it.
> > > >
> > > > [1] https://lkml.org/lkml/2018/3/23/44
> >
> > > Thanks for the reference.
> >
> > > It looks like the iommu driver part is in Linus' tree already. The DT
> > part is
> > > in the v4.18-armsoc/dts32 branch of Heiko's tree. Am I missing
anything?
> >
> > You're right, most of the series made it in time for 4.17. However, the
DT
> > part (precisely, the clocks properties added to IOMMU nodes) is crucial
for
> > the fixes to be effective.
> >
> > > Anyway, I'll take a look.
> >
> > Thanks for testing. :) (Forgot to mention in my previous email...)
> I finally got around to testing. Unfortunately, kernel v4.17-rc6 with
> cherry-pick of commit c78751f91c0b (ARM: dts: rockchip: add clocks in
iommu
> nodes) from Heiko's tree still exhibit the same problem. STREAMON hangs on
> second try. The same workaround "fixes" it.
Thanks for testing. I'm out of ideas, since the same code seems to work
fine for us in Chrome OS 4.4 kernel. Maybe we could have someone from RK
take a look.
Best regards,
Tomasz
^ permalink raw reply
* Re: [PATCH v3 4/8] drm/mediatek: add ddp component AAL1
From: CK Hu @ 2018-05-25 4:23 UTC (permalink / raw)
To: stu.hsieh
Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Matthias Brugger, linux-arm-kernel
In-Reply-To: <1527215665-11937-5-git-send-email-stu.hsieh@mediatek.com>
Hi, Stu:
On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote:
> From: Stu Hsieh <stu.hsieh@mediatek.com>
>
> This patch add component AAL1 and
> rename AAL to AAL0
>
> Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 0828cf8bf85c..eee3c0cc2632 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -41,7 +41,8 @@ enum mtk_ddp_comp_type {
> };
>
> enum mtk_ddp_comp_id {
> - DDP_COMPONENT_AAL,
> + DDP_COMPONENT_AAL0,
> + DDP_COMPONENT_AAL1,
Be sure compiling is success when you apply each patch of a series. I
think when you apply to this patch, it would cause compiling error
because some related modification is in the patch 'Add support for
mediatek SOC MT2712'. So move the modification from that patch to this
patch.
Regards,
CK
> DDP_COMPONENT_BLS,
> DDP_COMPONENT_COLOR0,
> DDP_COMPONENT_COLOR1,
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCH v2 5/5] MAINTAINERS: Add Actions Semi S900 pinctrl entries
From: Andreas Färber @ 2018-05-25 4:12 UTC (permalink / raw)
To: Linus Walleij
Cc: Manivannan Sadhasivam, Rob Herring, liuwei, 96boards,
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Andy Shevchenko,
Daniel Thompson, Amit Kucheria, Linux ARM, GPIO SUBSYSTEM,
linux-kernel@vger.kernel.org, hzhang, bdong, Mani Sadhasivam,
Thomas C. Liau, Jeff Chen
In-Reply-To: <CACRpkdYF7a-uwye0uwn-pT9Bprj74q1-Pcbq4WLyiE+kYY4j7w@mail.gmail.com>
Am 23.05.2018 um 10:40 schrieb Linus Walleij:
> On Sun, May 20, 2018 at 7:17 AM, Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org> wrote:
>
>> Add S900 pinctrl entries under ARCH_ACTIONS
>>
>> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>
> Patch applied tentatively so we have some maintenance entry for this.
>
> Andreas expressed concerns about the driver earlier, so he might want it
> split from the platform parts and have a separate entry for the pinctrl+GPIO
> so Manivannan can maintain that part, also it makes sense to list
> Manivannan as comaintainer of ARCH_ACTIONS with this in.
>
> Andreas: how would you like to proceed?
>
> I understand that I was a bit pushy or even rude in my last message
> about the maintenance of this platform and the code structure of
> the pin control driver. I am sorry if it caused any bad feelings on your
> side :( social conflicts give me the creeps, I just try my best. Maybe
> my best isn't always what it should be.
I fail to understand how splitting the MAINTAINERS section is going to
help with the pinctrl conflict at hand? The problem is that instead of
refactoring my S500 pinctrl driver to his liking, Mani has submitted a
competing S900 pinctrl driver that you went on to merge. The human
aspect is that merging his driver took the credit away from me having
written the earlier pinctrl driver (based on my rtd1295 pinctrl driver).
The practical aspect is that I can't drop my pinctrl driver from my work
branch until there is equivalent functionality in the merged driver. I
am lacking the time to rewrite S500 pin definitions on top of Mani's
myself at this time, and I haven't seen S500 patches from him yet.
Also I had been investing efforts in explaining the upstreaming process
to Actions, last in November. I see Thomas Liau and Jeff Chen missing in
CC and I have not seen any Reviewed-by or Acked-by from anyone at
Actions on this and the preceding series. There are more chips than the
one on Linaro's 96board, so I would prefer to assure that the design
works for all. Thus I am very critical of you applying the patches
without waiting for review by Actions.
Other aspects are: The reason I wrote the pinctrl driver is that I
experienced a UART TX issue on the Sparky board and was hoping a pinctrl
driver might resolve that, but it didn't. So I still have a mix of
boards where some are working and some are pretty unusable, without any
clues on why.
That said, I don't object to having a separate MAINTAINERS section for
the pinctrl driver(s) as long as I still get CC'ed on changes. We have
wanted to add Mani as R for Actions overall, so that would probably mean
adding me as R to an Actions pinctrl section, to avoid syncing the paths
between two sections. I had previously felt that it does not make sense
to list Mani as co-maintainer (M) for Actions overall since he can't tag
and submit from my repo. And for the record I have offered him to take
over which he didn't want to. I still hope to find some more time to
review and queue his SPS patches, a driver that I have designed and thus
understand and am much happier about the incremental additions there.
A further side note is that I had reached out about setting up an
infradead mailing list linux-actions, but there was no response from
David or anyone. Having an L on the section(s) would avoid messing with
R and hand-maintained CC lists. Any help with that appreciated.
Regards,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
^ permalink raw reply
* Re: [PATCH v13 1/2] cpufreq: Add Kryo CPU scaling driver
From: Viresh Kumar @ 2018-05-25 4:05 UTC (permalink / raw)
To: Ilia Lin
Cc: vireshk, nm, sboyd, robh, mark.rutland, rjw, linux-pm, devicetree,
linux-kernel
In-Reply-To: <DF878CBB-304A-4116-83D5-DF6BCEB7C131@codeaurora.org>
On 25-05-18, 07:00, Ilia Lin wrote:
>
>
> On May 25, 2018 6:54:12 AM GMT+03:00, Viresh Kumar <viresh.kumar@linaro.org> wrote:
> >On 24-05-18, 18:03, Ilia Lin wrote:
> >> +static int __init qcom_cpufreq_kryo_init(void)
> >> +{
> >> + struct device_node *np;
> >> + struct device *cpu_dev;
> >> + int ret;
> >> +
> >> + cpu_dev = get_cpu_device(0);
> >> + if (NULL == cpu_dev)
> >> + ret = -ENODEV;
> >> +
> >> + np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
> >> + if (IS_ERR(np))
> >> + return PTR_ERR(np);
> >> +
> >> + ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
> >> + of_node_put(np);
> >> + if (!ret)
> >> + return -ENOENT;
> >> +
> >
> >I hate the fact that it is taking so long to get done with this. But
> >can't you
> >just check machine compatibility instead of this complicated setup to
> >check OPP
> >node ? Like:
> >
> > if (!of_device_is_compatible("qcom,apq8096") &&
> > !of_device_is_compatible("qcom,msm8996"))
> > return;
>
> I have to check the "operating-points-v2-kryo-cpu" anyway, so I moved it from probe to the init.
Okay, leave it as is then. Don't send anything yet and wait for Sudeep to
respond.
> >
> >And please see if you can add an entry in MAINTAINERS and add your
> >working email
> >id there.
>
> Sure. Should this be part of the patch itself?
If you need to send another version of this series, then add it to this patch
itself. Else send it separately and don't resend this stuff.
--
viresh
^ permalink raw reply
* Re: [PATCH v13 1/2] cpufreq: Add Kryo CPU scaling driver
From: Ilia Lin @ 2018-05-25 4:00 UTC (permalink / raw)
To: Viresh Kumar
Cc: vireshk, nm, sboyd, robh, mark.rutland, rjw, linux-pm, devicetree,
linux-kernel
In-Reply-To: <20180525035412.3jjocp7ccmv5u2il@vireshk-i7>
[-- Attachment #1: Type: text/plain, Size: 1186 bytes --]
On May 25, 2018 6:54:12 AM GMT+03:00, Viresh Kumar <viresh.kumar@linaro.org> wrote:
>On 24-05-18, 18:03, Ilia Lin wrote:
>> +static int __init qcom_cpufreq_kryo_init(void)
>> +{
>> + struct device_node *np;
>> + struct device *cpu_dev;
>> + int ret;
>> +
>> + cpu_dev = get_cpu_device(0);
>> + if (NULL == cpu_dev)
>> + ret = -ENODEV;
>> +
>> + np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
>> + if (IS_ERR(np))
>> + return PTR_ERR(np);
>> +
>> + ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
>> + of_node_put(np);
>> + if (!ret)
>> + return -ENOENT;
>> +
>
>I hate the fact that it is taking so long to get done with this. But
>can't you
>just check machine compatibility instead of this complicated setup to
>check OPP
>node ? Like:
>
> if (!of_device_is_compatible("qcom,apq8096") &&
> !of_device_is_compatible("qcom,msm8996"))
> return;
I have to check the "operating-points-v2-kryo-cpu" anyway, so I moved it from probe to the init.
>
>And please see if you can add an entry in MAINTAINERS and add your
>working email
>id there.
Sure. Should this be part of the patch itself?
[-- Attachment #2: Type: text/html, Size: 1571 bytes --]
^ permalink raw reply
* Re: [PATCH v13 1/2] cpufreq: Add Kryo CPU scaling driver
From: Viresh Kumar @ 2018-05-25 3:54 UTC (permalink / raw)
To: Ilia Lin
Cc: vireshk, nm, sboyd, robh, mark.rutland, rjw, linux-pm, devicetree,
linux-kernel
In-Reply-To: <1527174220-13244-2-git-send-email-ilialin@codeaurora.org>
On 24-05-18, 18:03, Ilia Lin wrote:
> +static int __init qcom_cpufreq_kryo_init(void)
> +{
> + struct device_node *np;
> + struct device *cpu_dev;
> + int ret;
> +
> + cpu_dev = get_cpu_device(0);
> + if (NULL == cpu_dev)
> + ret = -ENODEV;
> +
> + np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
> + if (IS_ERR(np))
> + return PTR_ERR(np);
> +
> + ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu");
> + of_node_put(np);
> + if (!ret)
> + return -ENOENT;
> +
I hate the fact that it is taking so long to get done with this. But can't you
just check machine compatibility instead of this complicated setup to check OPP
node ? Like:
if (!of_device_is_compatible("qcom,apq8096") &&
!of_device_is_compatible("qcom,msm8996"))
return;
And please see if you can add an entry in MAINTAINERS and add your working email
id there.
--
viresh
^ permalink raw reply
* RE: [PATCH v6 2/2] ARM: dts: imx: Add basic dts support for imx6sll EVK board
From: A.s. Dong @ 2018-05-25 3:35 UTC (permalink / raw)
To: Jacky Bai, shawnguo@kernel.org, robh+dt@kernel.org,
kernel@pengutronix.de
Cc: Fabio Estevam, devicetree@vger.kernel.org, dl-linux-imx,
linux-arm-kernel@lists.infradead.org, jacky.baip@gmail.com
In-Reply-To: <1526899612-22856-2-git-send-email-ping.bai@nxp.com>
> -----Original Message-----
> From: Jacky Bai
> Sent: Monday, May 21, 2018 6:47 PM
> To: shawnguo@kernel.org; robh+dt@kernel.org; kernel@pengutronix.de
> Cc: Fabio Estevam <fabio.estevam@nxp.com>; devicetree@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; dl-linux-imx <linux-imx@nxp.com>;
> A.s. Dong <aisheng.dong@nxp.com>; jacky.baip@gmail.com
> Subject: [PATCH v6 2/2] ARM: dts: imx: Add basic dts support for imx6sll EVK
> board
>
> Add dts file support for imx6sll EVK board.
>
> Signed-off-by: Bai Ping <ping.bai@nxp.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> change v3->v4
> - update the license indentifier
> - remove leading zero of node
> - remove unused pin from hog group
> change v4->v5
> - use generic name for device node
> - remove unnecessary hog pin group
> change v5->v6
> - no
> ---
> Documentation/devicetree/bindings/arm/fsl.txt | 4 +
> arch/arm/boot/dts/Makefile | 2 +
> arch/arm/boot/dts/imx6sll-evk.dts | 315
> ++++++++++++++++++++++++++
> 3 files changed, 321 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6sll-evk.dts
>
> diff --git a/Documentation/devicetree/bindings/arm/fsl.txt
> b/Documentation/devicetree/bindings/arm/fsl.txt
> index cdb9dd7..8a1baa2 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.txt
> +++ b/Documentation/devicetree/bindings/arm/fsl.txt
> @@ -53,6 +53,10 @@ i.MX6 Quad SABRE Automotive Board Required root
> node properties:
> - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
>
> +i.MX6SLL EVK board
> +Required root node properties:
> + - compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
> +
> Generic i.MX boards
> -------------------
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index f4753b0..f3fb85f 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -521,6 +521,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
> dtb-$(CONFIG_SOC_IMX6SL) += \
> imx6sl-evk.dtb \
> imx6sl-warp.dtb
> +dtb-$(CONFIG_SOC_IMX6SLL) += \
> + imx6sll-evk.dtb
> dtb-$(CONFIG_SOC_IMX6SX) += \
> imx6sx-nitrogen6sx.dtb \
> imx6sx-sabreauto.dtb \
> diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-
> evk.dts
> new file mode 100644
> index 0000000..0cfa4a2
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6sll-evk.dts
> @@ -0,0 +1,315 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright 2016 Freescale Semiconductor, Inc.
> + * Copyright 2017-2018 NXP.
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include "imx6sll.dtsi"
> +
> +/ {
> + model = "Freescale i.MX6SLL EVK Board";
> + compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
> +
> + memory@80000000 {
> + reg = <0x80000000 0x80000000>;
> + };
> +
> + backlight {
> + compatible = "pwm-backlight";
> + pwms = <&pwm1 0 5000000>;
> + brightness-levels = <0 4 8 16 32 64 128 255>;
> + default-brightness-level = <6>;
> + status = "okay";
> + };
> +
> + reg_usb_otg1_vbus: regulator-otg1-vbus {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usb_otg1_vbus>;
> + regulator-name = "usb_otg1_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_usb_otg2_vbus: regulator-otg2-vbus {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usb_otg2_vbus>;
> + regulator-name = "usb_otg2_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_aud3v: regulator-aud3v {
> + compatible = "regulator-fixed";
> + regulator-name = "wm8962-supply-3v15";
> + regulator-min-microvolt = <3150000>;
> + regulator-max-microvolt = <3150000>;
> + regulator-boot-on;
> + };
> +
> + reg_aud4v: regulator-aud4v {
> + compatible = "regulator-fixed";
> + regulator-name = "wm8962-supply-4v2";
> + regulator-min-microvolt = <4325000>;
> + regulator-max-microvolt = <4325000>;
> + regulator-boot-on;
> + };
> +
> + reg_lcd: regulator-lcd {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reg_lcd>;
> + regulator-name = "lcd-pwr";
> + gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_sd1_vmmc: regulator-sd1-vmmc {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reg_sd1_vmmc>;
> + regulator-name = "SD1_SPWR";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +};
> +
> +&cpu0 {
> + arm-supply = <&sw1a_reg>;
> + soc-supply = <&sw1c_reg>;
> +};
> +
> +&i2c1 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +
> + pfuze100: pmic@8 {
> + compatible = "fsl,pfuze100";
> + reg = <0x08>;
> +
> + regulators {
> + sw1a_reg: sw1ab {
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1875000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <6250>;
> + };
> +
> + sw1c_reg: sw1c {
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1875000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <6250>;
> + };
> +
> + sw2_reg: sw2 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + sw3a_reg: sw3a {
> + regulator-min-microvolt = <400000>;
> + regulator-max-microvolt = <1975000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + sw3b_reg: sw3b {
> + regulator-min-microvolt = <400000>;
> + regulator-max-microvolt = <1975000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + sw4_reg: sw4 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + swbst_reg: swbst {
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5150000>;
> + };
> +
> + snvs_reg: vsnvs {
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vref_reg: vrefddr {
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vgen1_reg: vgen1 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1550000>;
> + regulator-always-on;
> + };
> +
> + vgen2_reg: vgen2 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1550000>;
> + };
> +
> + vgen3_reg: vgen3 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + vgen4_reg: vgen4 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + vgen5_reg: vgen5 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + vgen6_reg: vgen6 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> + };
> + };
> +};
> +
> +&iomuxc {
> + pinctrl_usb_otg1_vbus: vbus1grp {
> + fsl,pins = <
> + MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059
> + >;
> + };
> +
> + pinctrl_usb_otg2_vbus: vbus2grp {
> + fsl,pins = <
> + MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059
> + >;
> + };
> +
> + pinctrl_reg_lcd: reglcdgrp {
> + fsl,pins = <
> + MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x17059
> + >;
> + };
> +
> + pinctrl_reg_sd1_vmmc: sd1vmmcgrp {
> + fsl,pins = <
> + MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX6SLL_PAD_UART1_TXD__UART1_DCE_TX
> 0x1b0b1
> + MX6SLL_PAD_UART1_RXD__UART1_DCE_RX
> 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059
> + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13059
> + MX6SLL_PAD_SD1_DATA0__SD1_DATA0
> 0x17059
> + MX6SLL_PAD_SD1_DATA1__SD1_DATA1
> 0x17059
> + MX6SLL_PAD_SD1_DATA2__SD1_DATA2
> 0x17059
> + MX6SLL_PAD_SD1_DATA3__SD1_DATA3
> 0x17059
> + >;
> + };
> +
> + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
> + fsl,pins = <
> + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9
> + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130b9
> + MX6SLL_PAD_SD1_DATA0__SD1_DATA0
> 0x170b9
> + MX6SLL_PAD_SD1_DATA1__SD1_DATA1
> 0x170b9
> + MX6SLL_PAD_SD1_DATA2__SD1_DATA2
> 0x170b9
> + MX6SLL_PAD_SD1_DATA3__SD1_DATA3
> 0x170b9
> + >;
> + };
> +
> + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
> + fsl,pins = <
> + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9
> + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9
> + MX6SLL_PAD_SD1_DATA0__SD1_DATA0
> 0x170f9
> + MX6SLL_PAD_SD1_DATA1__SD1_DATA1
> 0x170f9
> + MX6SLL_PAD_SD1_DATA2__SD1_DATA2
> 0x170f9
> + MX6SLL_PAD_SD1_DATA3__SD1_DATA3
> 0x170f9
> + >;
> + };
> +
> + pinctrl_usbotg1: usbotg1grp {
> + fsl,pins = <
> + MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID
> 0x17059
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
> + MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
> + >;
> + };
> +};
Due to iomux node usually may expend largely, we choose better to put iomux node
at the end of this file to make other nodes easily looking.
Acked-by: Dong Aisheng <Aisheng.dong@nxp.com>
Regards
Dong Aisheng
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + status = "okay";
> +};
> +
> +&usdhc1 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> + cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
> + wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
> + keep-power-in-suspend;
> + wakeup-source;
> + vmmc-supply = <®_sd1_vmmc>;
> + status = "okay";
> +};
> +
> +&usbotg1 {
> + vbus-supply = <®_usb_otg1_vbus>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbotg1>;
> + disable-over-current;
> + srp-disable;
> + hnp-disable;
> + adp-disable;
> + status = "okay";
> +};
> +
> +&usbotg2 {
> + vbus-supply = <®_usb_otg2_vbus>;
> + dr_mode = "host";
> + disable-over-current;
> + status = "okay";
> +};
> --
> 1.9.1
^ permalink raw reply
* Re: [PATCH v3 3/8] drm/mediatek: add connection from OD1 to RDMA1
From: CK Hu @ 2018-05-25 3:26 UTC (permalink / raw)
To: stu.hsieh
Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Matthias Brugger, linux-arm-kernel
In-Reply-To: <1527215665-11937-4-git-send-email-stu.hsieh@mediatek.com>
Hi, Stu:
On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote:
> From: Stu Hsieh <stu.hsieh@mediatek.com>
>
> This patch add the connection from OD1 to RDMA1 for ext path.
>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index 47ffa240bd25..0f568dd853d8 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -151,6 +151,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
> } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> value = GAMMA_MOUT_EN_RDMA1;
> + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> + value = OD1_MOUT_EN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN;
> value = RDMA1_MOUT_DPI0;
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* RE: [PATCH v6 1/2] ARM: dts: imx: Add basic dtsi file for imx6sll
From: A.s. Dong @ 2018-05-25 3:24 UTC (permalink / raw)
To: Jacky Bai, shawnguo@kernel.org, robh+dt@kernel.org,
kernel@pengutronix.de
Cc: Fabio Estevam, devicetree@vger.kernel.org, dl-linux-imx,
linux-arm-kernel@lists.infradead.org, jacky.baip@gmail.com
In-Reply-To: <1526899612-22856-1-git-send-email-ping.bai@nxp.com>
> -----Original Message-----
> From: Jacky Bai
> Sent: Monday, May 21, 2018 6:47 PM
> To: shawnguo@kernel.org; robh+dt@kernel.org; kernel@pengutronix.de
> Cc: Fabio Estevam <fabio.estevam@nxp.com>; devicetree@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; dl-linux-imx <linux-imx@nxp.com>;
> A.s. Dong <aisheng.dong@nxp.com>; jacky.baip@gmail.com
> Subject: [PATCH v6 1/2] ARM: dts: imx: Add basic dtsi file for imx6sll
>
[...]
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "arm,cortex-a9";
> + device_type = "cpu";
> + reg = <0>;
> + next-level-cache = <&L2>;
> + operating-points = <
> + /* kHz uV */
> + 996000 1275000
> + 792000 1175000
> + 396000 1075000
> + 198000 975000
> + >;
> + fsl,soc-operating-points = <
> + /* ARM kHz SOC-PU uV */
> + 996000 1175000
> + 792000 1175000
> + 396000 1175000
> + 198000 1175000
> + >;
> + clock-latency = <61036>; /* two CLK32 periods */
> + clocks = <&clks IMX6SLL_CLK_ARM>,
> + <&clks IMX6SLL_CLK_PLL2_PFD2>,
> + <&clks IMX6SLL_CLK_STEP>,
> + <&clks IMX6SLL_CLK_PLL1_SW>,
> + <&clks IMX6SLL_CLK_PLL1_SYS>,
> + <&clks IMX6SLL_CLK_PLL1>,
> + <&clks IMX6SLL_PLL1_BYPASS>,
> + <&clks IMX6SLL_PLL1_BYPASS_SRC>;
> + clock-names = "arm", "pll2_pfd2_396m", "step",
> + "pll1_sw", "pll1_sys", "pll1",
> + "pll1_bypass", "pll1_bypass_src";
> + };
Please remove the unused pll1, pll1_bypass and pll1_bypass_src clocks.
> + };
> +
> + intc: interrupt-controller@a01000 {
> + compatible = "arm,cortex-a9-gic";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x00a01000 0x1000>,
> + <0x00a00100 0x100>;
> + interrupt-parent = <&intc>;
> + };
> +
> + ckil: clock-ckil {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + clock-output-names = "ckil";
> + };
> +
> + osc: clock-osc-24m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24000000>;
> + clock-output-names = "osc";
> + };
> +
[...]
> +
> + gpt1: timer@2098000 {
> + compatible = "fsl,imx6dl-gpt";
This looks strange as mx6sll is derived from mx6sl.
How about change to "fsl,imx6sl-gpt" which is already supported?
> + reg = <0x02098000 0x4000>;
> + interrupts = <GIC_SPI 55
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_GPT_BUS>,
> + <&clks IMX6SLL_CLK_GPT_SERIAL>;
> + clock-names = "ipg", "per";
> + };
> +
[...]
> +
> + tempmon: temperature-sensor {
> + compatible = "fsl,imx6sll-tempmon",
> "fsl,imx6sx-tempmon";
> + interrupts = <GIC_SPI 49
> IRQ_TYPE_LEVEL_HIGH>;
> + fsl,tempmon = <&anatop>;
> + fsl,tempmon-data = <&ocotp>;
> + clocks = <&clks
> IMX6SLL_CLK_PLL3_USB_OTG>;
> + status = "disabled";
> + };
> +
Pls move it out of SoC node to root node.
See:
commit 225fa59fddfa7 ("ARM: dts: imx7: Move tempmon node out of bus")
And probably we need switch to the new way?
See:
commit de25b9bb4a4 ("ARM: dts: imx7s: add temperature monitor support")
Otherwise:
Acked-by: Dong Aisheng <Aisheng.dong@nxp.com>
Regards
Dong Aisheng
> + usbphy1: usb-phy@20c9000 {
> + compatible = "fsl,imx6sll-usbphy",
> "fsl,imx6ul-usbphy",
> + "fsl,imx23-usbphy";
> + reg = <0x020c9000 0x1000>;
> + interrupts = <GIC_SPI 40
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_USBPHY1>;
> + phy-3p0-supply = <®_3p0>;
> + fsl,anatop = <&anatop>;
> + };
> +
> + usbphy2: usb-phy@20ca000 {
> + compatible = "fsl,imx6sll-usbphy",
> "fsl,imx6ul-usbphy",
> + "fsl,imx23-usbphy";
> + reg = <0x020ca000 0x1000>;
> + interrupts = <GIC_SPI 41
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_USBPHY2>;
> + phy-reg_3p0-supply = <®_3p0>;
> + fsl,anatop = <&anatop>;
> + };
> +
> + snvs: snvs@20cc000 {
> + compatible = "fsl,sec-v4.0-mon", "syscon",
> "simple-mfd";
> + reg = <0x020cc000 0x4000>;
> +
> + snvs_rtc: snvs-rtc-lp {
> + compatible = "fsl,sec-v4.0-mon-rtc-
> lp";
> + regmap = <&snvs>;
> + offset = <0x34>;
> + interrupts = <GIC_SPI 19
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 20
> IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + snvs_poweroff: snvs-poweroff {
> + compatible = "syscon-poweroff";
> + regmap = <&snvs>;
> + offset = <0x38>;
> + mask = <0x61>;
> + };
> +
> + snvs_pwrkey: snvs-powerkey {
> + compatible = "fsl,sec-v4.0-pwrkey";
> + regmap = <&snvs>;
> + interrupts = <GIC_SPI 4
> IRQ_TYPE_LEVEL_HIGH>;
> + linux,keycode = <KEY_POWER>;
> + wakeup-source;
> + };
> + };
> +
> + src: reset-controller@20d8000 {
> + compatible = "fsl,imx6sll-src";
> + reg = <0x020d8000 0x4000>;
> + interrupts = <GIC_SPI 91
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 96
> IRQ_TYPE_LEVEL_HIGH>;
> + #reset-cells = <1>;
> + };
> +
> + gpc: interrupt-controller@20dc000 {
> + compatible = "fsl,imx6sll-gpc", "fsl,imx6q-
> gpc";
> + reg = <0x020dc000 0x4000>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupts = <GIC_SPI 89
> IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&intc>;
> + fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00
> 0x0 0x1400640>;
> + };
> +
> + iomuxc: pinctrl@20e0000 {
> + compatible = "fsl,imx6sll-iomuxc";
> + reg = <0x020e0000 0x4000>;
> + };
> +
> + gpr: iomuxc-gpr@20e4000 {
> + compatible = "fsl,imx6sll-iomuxc-gpr",
> + "fsl,imx6q-iomuxc-gpr", "syscon";
> + reg = <0x020e4000 0x4000>;
> + };
> +
> + csi: csi@20e8000 {
> + compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
> + reg = <0x020e8000 0x4000>;
> + interrupts = <GIC_SPI 7
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_DUMMY>,
> + <&clks IMX6SLL_CLK_CSI>,
> + <&clks IMX6SLL_CLK_DUMMY>;
> + clock-names = "disp-axi", "csi_mclk",
> "disp_dcic";
> + status = "disabled";
> + };
> +
> + sdma: dma-controller@20ec000 {
> + compatible = "fsl,imx6sll-sdma", "fsl,imx35-
> sdma";
> + reg = <0x020ec000 0x4000>;
> + interrupts = <GIC_SPI 2
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_SDMA>,
> + <&clks IMX6SLL_CLK_SDMA>;
> + clock-names = "ipg", "ahb";
> + #dma-cells = <3>;
> + iram = <&ocram>;
> + fsl,sdma-ram-script-name =
> "imx/sdma/sdma-imx6q.bin";
> + };
> +
> + lcdif: lcd-controller@20f8000 {
> + compatible = "fsl,imx6sll-lcdif", "fsl,imx28-
> lcdif";
> + reg = <0x020f8000 0x4000>;
> + interrupts = <GIC_SPI 39
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>,
> + <&clks IMX6SLL_CLK_LCDIF_APB>,
> + <&clks IMX6SLL_CLK_DUMMY>;
> + clock-names = "pix", "axi", "disp_axi";
> + status = "disabled";
> + };
> +
> + dcp: dcp@20fc000 {
> + compatible = "fsl,imx28-dcp";
> + reg = <0x020fc000 0x4000>;
> + interrupts = <GIC_SPI 99
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 100
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 101
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_DCP>;
> + clock-names = "dcp";
> + };
> + };
> +
> + aips2: aips-bus@2100000 {
> + compatible = "fsl,aips-bus", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x02100000 0x100000>;
> + ranges;
> +
> + usbotg1: usb@2184000 {
> + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-
> usb",
> + "fsl,imx27-usb";
> + reg = <0x02184000 0x200>;
> + interrupts = <GIC_SPI 43
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_USBOH3>;
> + fsl,usbphy = <&usbphy1>;
> + fsl,usbmisc = <&usbmisc 0>;
> + fsl,anatop = <&anatop>;
> + ahb-burst-config = <0x0>;
> + tx-burst-size-dword = <0x10>;
> + rx-burst-size-dword = <0x10>;
> + status = "disabled";
> + };
> +
> + usbotg2: usb@2184200 {
> + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-
> usb",
> + "fsl,imx27-usb";
> + reg = <0x02184200 0x200>;
> + interrupts = <GIC_SPI 42
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_USBOH3>;
> + fsl,usbphy = <&usbphy2>;
> + fsl,usbmisc = <&usbmisc 1>;
> + ahb-burst-config = <0x0>;
> + tx-burst-size-dword = <0x10>;
> + rx-burst-size-dword = <0x10>;
> + status = "disabled";
> + };
> +
> + usbmisc: usbmisc@2184800 {
> + #index-cells = <1>;
> + compatible = "fsl,imx6sll-usbmisc",
> "fsl,imx6ul-usbmisc",
> + "fsl,imx6q-usbmisc";
> + reg = <0x02184800 0x200>;
> + };
> +
> + usdhc1: mmc@2190000 {
> + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-
> usdhc";
> + reg = <0x02190000 0x4000>;
> + interrupts = <GIC_SPI 22
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_USDHC1>,
> + <&clks IMX6SLL_CLK_USDHC1>,
> + <&clks IMX6SLL_CLK_USDHC1>;
> + clock-names = "ipg", "ahb", "per";
> + bus-width = <4>;
> + fsl,tuning-step = <2>;
> + fsl,tuning-start-tap = <20>;
> + status = "disabled";
> + };
> +
> + usdhc2: mmc@2194000 {
> + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-
> usdhc";
> + reg = <0x02194000 0x4000>;
> + interrupts = <GIC_SPI 23
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_USDHC2>,
> + <&clks IMX6SLL_CLK_USDHC2>,
> + <&clks IMX6SLL_CLK_USDHC2>;
> + clock-names = "ipg", "ahb", "per";
> + bus-width = <4>;
> + fsl,tuning-step = <2>;
> + fsl,tuning-start-tap = <20>;
> + status = "disabled";
> + };
> +
> + usdhc3: mmc@2198000 {
> + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-
> usdhc";
> + reg = <0x02198000 0x4000>;
> + interrupts = <GIC_SPI 24
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_USDHC3>,
> + <&clks IMX6SLL_CLK_USDHC3>,
> + <&clks IMX6SLL_CLK_USDHC3>;
> + clock-names = "ipg", "ahb", "per";
> + bus-width = <4>;
> + fsl,tuning-step = <2>;
> + fsl,tuning-start-tap = <20>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c@21a0000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fs,imx6sll-i2c", "fsl,imx21-i2c";
> + reg = <0x021a0000 0x4000>;
> + interrupts = <GIC_SPI 36
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_I2C1>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c@21a4000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
> + reg = <0x021a4000 0x4000>;
> + interrupts = <GIC_SPI 37
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_I2C2>;
> + status = "disabled";
> + };
> +
> + i2c3: i2c@21a8000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
> + reg = <0x021a8000 0x4000>;
> + interrupts = <GIC_SPI 38
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_I2C3>;
> + status = "disabled";
> + };
> +
> + mmdc: memory-controller@21b0000 {
> + compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-
> mmdc";
> + reg = <0x021b0000 0x4000>;
> + };
> +
> + ocotp: ocotp-ctrl@21bc000 {
> + compatible = "fsl,imx6sll-ocotp", "syscon";
> + reg = <0x021bc000 0x4000>;
> + clocks = <&clks IMX6SLL_CLK_OCOTP>;
> + };
> +
> + audmux: audmux@21d8000 {
> + compatible = "fsl,imx6sll-audmux",
> "fsl,imx31-audmux";
> + reg = <0x021d8000 0x4000>;
> + status = "disabled";
> + };
> +
> + uart5: serial@21f4000 {
> + compatible = "fsl,imx6sll-uart", "fsl,imx6q-
> uart",
> + "fsl,imx21-uart";
> + reg = <0x021f4000 0x4000>;
> + interrupts =<GIC_SPI 30
> IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
> + dma-names = "rx", "tx";
> + clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
> + <&clks
> IMX6SLL_CLK_UART5_SERIAL>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> + };
> + };
> +};
> --
> 1.9.1
^ permalink raw reply
* Re: [PATCH v3 2/8] drm/mediatek: support maximum 64 mutex mod
From: CK Hu @ 2018-05-25 3:24 UTC (permalink / raw)
To: stu.hsieh
Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Matthias Brugger, linux-arm-kernel
In-Reply-To: <1527215665-11937-3-git-send-email-stu.hsieh@mediatek.com>
Hi, Stu:
On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote:
> From: Stu Hsieh <stu.hsieh@mediatek.com>
>
> This patch support that if modules more than 32,
> add index more than 31 when using DISP_REG_MUTEX_MOD2 bit
>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 75 +++++++++++++++++++++-------------
> 1 file changed, 47 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index 8130f3dab661..47ffa240bd25 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -41,31 +41,32 @@
> #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
> #define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
> #define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n))
> +#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
>
> #define INT_MUTEX BIT(1)
>
> -#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
> -#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
> -#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
> -#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
> -#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
> -#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
> -#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
> -#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
> -#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
> -#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
> -#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
> -#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
> -#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
> -#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
> -#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
> -
> -#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
> -#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
> -#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7)
> -#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
> -#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10)
> -#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12)
> +#define MT8173_MUTEX_MOD_DISP_OVL0 11
> +#define MT8173_MUTEX_MOD_DISP_OVL1 12
> +#define MT8173_MUTEX_MOD_DISP_RDMA0 13
> +#define MT8173_MUTEX_MOD_DISP_RDMA1 14
> +#define MT8173_MUTEX_MOD_DISP_RDMA2 15
> +#define MT8173_MUTEX_MOD_DISP_WDMA0 16
> +#define MT8173_MUTEX_MOD_DISP_WDMA1 17
> +#define MT8173_MUTEX_MOD_DISP_COLOR0 18
> +#define MT8173_MUTEX_MOD_DISP_COLOR1 19
> +#define MT8173_MUTEX_MOD_DISP_AAL 20
> +#define MT8173_MUTEX_MOD_DISP_GAMMA 21
> +#define MT8173_MUTEX_MOD_DISP_UFOE 22
> +#define MT8173_MUTEX_MOD_DISP_PWM0 23
> +#define MT8173_MUTEX_MOD_DISP_PWM1 24
> +#define MT8173_MUTEX_MOD_DISP_OD 25
> +
> +#define MT2701_MUTEX_MOD_DISP_OVL 3
> +#define MT2701_MUTEX_MOD_DISP_WDMA 6
> +#define MT2701_MUTEX_MOD_DISP_COLOR 7
> +#define MT2701_MUTEX_MOD_DISP_BLS 9
> +#define MT2701_MUTEX_MOD_DISP_RDMA0 10
> +#define MT2701_MUTEX_MOD_DISP_RDMA1 12
>
> #define MUTEX_SOF_SINGLE_MODE 0
> #define MUTEX_SOF_DSI0 1
> @@ -278,6 +279,7 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
> struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
> mutex[mutex->id]);
> unsigned int reg;
> + unsigned int offset;
>
> WARN_ON(&ddp->mutex[mutex->id] != mutex);
>
> @@ -292,9 +294,17 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
> reg = MUTEX_SOF_DPI0;
> break;
> default:
> - reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
> - reg |= ddp->mutex_mod[id];
> - writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
> + if (ddp->mutex_mod[id] < 32) {
> + offset = DISP_REG_MUTEX_MOD(mutex->id);
> + reg = readl_relaxed(ddp->regs + offset);
> + reg |= 1 << ddp->mutex_mod[id];
> + writel_relaxed(reg, ddp->regs + offset);
> + } else {
> + offset = DISP_REG_MUTEX_MOD2(mutex->id);
> + reg = readl_relaxed(ddp->regs + offset);
> + reg |= 1 << (ddp->mutex_mod[id] - 32);
> + writel_relaxed(reg, ddp->regs + offset);
> + }
> return;
> }
>
> @@ -307,6 +317,7 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex,
> struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
> mutex[mutex->id]);
> unsigned int reg;
> + unsigned int offset;
>
> WARN_ON(&ddp->mutex[mutex->id] != mutex);
>
> @@ -318,9 +329,17 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex,
> ddp->regs + DISP_REG_MUTEX_SOF(mutex->id));
> break;
> default:
> - reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
> - reg &= ~(ddp->mutex_mod[id]);
> - writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
> + if (ddp->mutex_mod[id] < 32) {
> + offset = DISP_REG_MUTEX_MOD(mutex->id);
> + reg = readl_relaxed(ddp->regs + offset);
> + reg &= ~(1 << ddp->mutex_mod[id]);
> + writel_relaxed(reg, ddp->regs + offset);
> + } else {
> + offset = DISP_REG_MUTEX_MOD2(mutex->id);
> + reg = readl_relaxed(ddp->regs + offset);
> + reg &= ~(1 << (ddp->mutex_mod[id] - 32));
> + writel_relaxed(reg, ddp->regs + offset);
> + }
> break;
> }
> }
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^ permalink raw reply
* Re: [PATCH v3 1/8] drm/mediatek: update dt-bindings for mt2712
From: CK Hu @ 2018-05-25 3:18 UTC (permalink / raw)
To: stu.hsieh
Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek,
Matthias Brugger, linux-arm-kernel
In-Reply-To: <1527215665-11937-2-git-send-email-stu.hsieh@mediatek.com>
Hi, Stu:
On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh@mediatek.com wrote:
> From: Stu Hsieh <stu.hsieh@mediatek.com>
>
> Update device tree binding documentation for the display subsystem for
> Mediatek MT2712 SoCs.
>
I've acked v2 of this patch and v3 is the same as v2, so you should keep
my ack in commit message.
Regards,
CK
> Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> ---
> Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> index 383183a89164..8469de510001 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> @@ -40,7 +40,7 @@ Required properties (all function blocks):
> "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
> "mediatek,<chip>-disp-mutex" - display mutex
> "mediatek,<chip>-disp-od" - overdrive
> - the supported chips are mt2701 and mt8173.
> + the supported chips are mt2701, mt2712 and mt8173.
> - reg: Physical base address and length of the function block register space
> - interrupts: The interrupt signal from the function block (required, except for
> merge and split function blocks).
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^ permalink raw reply
* [PATCH] ARM: dts: imx51-zii-rdu1: Make sure SD1_WP is low
From: Andrey Smirnov @ 2018-05-25 3:01 UTC (permalink / raw)
To: Shawn Guo
Cc: Andrey Smirnov, Nikita Yushchenko, Fabio Estevam, Lucas Stach,
Chris Healy, Rob Herring, linux-arm-kernel, devicetree,
linux-kernel
Make sure that MX51_PAD_GPIO1_1 does not remain configure as
ALT0/SD1_WP (it is out of reset). This is needed because of external
pull-up resistor attached to that pad that, when left unchanged, will
drive SD1_WP high preventing eSDHC1/eMMC from working correctly.
To fix that add a pinmux configuration line configureing the pad to
function as a GPIO. While we are at it, add a corresponding input GPIO
hog in an effort to minimize current consumption.
Cc: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/boot/dts/imx51-zii-rdu1.dts | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts
index df9eca94d812..d484e7e46b27 100644
--- a/arch/arm/boot/dts/imx51-zii-rdu1.dts
+++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts
@@ -476,6 +476,17 @@
status = "okay";
};
+&gpio1 {
+ unused-sd3-wp-gpio {
+ /*
+ * See pinctrl_esdhc1 below for more details on this
+ */
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_HIGH>;
+ input;
+ };
+};
+
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
@@ -660,6 +671,23 @@
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
+ /*
+ * GPIO1_1 is not directly used by eSDHC1 in
+ * any capacity, but earlier versions of RDU1
+ * used that pin as WP GPIO for eSDHC3 and
+ * because of that that pad has an external
+ * pull-up resistor. This is problematic
+ * because out of reset the pad is configured
+ * as ALT0 which serves as SD1_WP, which, when
+ * pulled high by and external pull-up, will
+ * inhibit execution of any write request to
+ * attached eMMC device.
+ *
+ * To avoid this problem we configure the pad
+ * to ALT1/GPIO and avoid driving SD1_WP
+ * signal high.
+ */
+ MX51_PAD_GPIO1_1__GPIO1_1 0x0000
>;
};
--
2.17.0
^ permalink raw reply related
* RE: [PATCH/RFC v4 2/4] usb: gadget: udc: renesas_usb3: Add register of usb role switch
From: Yoshihiro Shimoda @ 2018-05-25 2:50 UTC (permalink / raw)
To: Geert Uytterhoeven, Rob Herring
Cc: gregkh@linuxfoundation.org, mark.rutland@arm.com,
heikki.krogerus@linux.intel.com, hdegoede@redhat.com,
andy.shevchenko@gmail.com, linux-usb@vger.kernel.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org
In-Reply-To: <CAMuHMdWzORSs1_HeObaK0A1sYb_O8XTORA4EEk_riTKMWhWWAQ@mail.gmail.com>
Hi Rob, Geert-san,
> From: Geert Uytterhoeven, Sent: Thursday, May 24, 2018 5:18 PM
>
> Hi Rob,
>
> On Wed, May 23, 2018 at 5:00 PM, Rob Herring <robh@kernel.org> wrote:
<snip>
> >>> > Optional properties:
> >>> > - phys: phandle + phy specifier pair
> >>> > - phy-names: must be "usb"
> >>> > + - The connection to a usb3.0 host node needs by using OF graph bindings for
> >>> > + usb role switch.
> >>> > + - port@0 = USB3.0 host port.
> >>>
> >>> On the host side, this might conflict with the USB connector binding.
> >>>
> >>> I would either make sure this can work with the connector binding by
> >>> having 2 endpoints on the HS or SS port or just use the 'companion'
> >>> property defined in usb-generic.txt.
> >>
> >> I don't understand the first one now... This means the renesas_usb3 should follow
> >> USB connector binding and have 2 endpoints for the usb role switch to avoid
> >> the conflict like below?
> >> - port1@0: Super Speed (SS), present in SS capable connectors (from usb-connector.txt).
> >> - port1@1: USB3.0 host port.
> >
> > I'm confused, SS and USB3.0 are the same essentially. It would be:
> >
> > port@1/endpoint@0: SS host port
> > port@1/endpoint@1: SS device port
Thank you for the comment. It's better than my description.
> >> About the 'companion' in usb-generic.txt, the property intends to be used for EHCI or host side
> >> like the commit log [1]. If there is accept to use 'companion' for this patch, I think it will
> >> be simple to achieve this role switch feature. However, in last month, I submitted a similar patch [2]
> >> that has "renesas,host" property, but I got reply from Andy [3] and Heikki [4]. So, I'm
> >> trying to improve the device connection framework [5] now.
> >
> > I think this case is rare enough that we don't need a general solution
> > using OF graph, so I'm fine with a simple, single property to link the
> > 2 nodes. Either reusing "companion" or "renesas,host" is fine by me.
>
> I'd go for the standard "companion" over "renesas,host"[*].
>
> [*] Doh, we have another one ("renesas,bonding"), invented when I wasn't
> aware of the existence of "companion" yet...
Thank you for the comments. So, I'll reuse "companion" for it.
Best regards,
Yoshihiro Shimoda
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v2 13/40] vfio: Add support for Shared Virtual Addressing
From: Xu Zaibo @ 2018-05-25 2:39 UTC (permalink / raw)
To: Jean-Philippe Brucker,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org,
kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-mm-Bw31MaZKKs3YtjvyW6yDsg@public.gmane.org
Cc: bharatku-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org,
ashok.raj-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org,
dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org,
ilias.apalodimas-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
Will Deacon, okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
rgummal-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org,
rfranz-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org,
liguozhu-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org,
christian.koenig-5C7GfCeVMHo@public.gmane.org
In-Reply-To: <205c1729-8026-3efe-c363-d37d7150d622-5wv7dgnIgG8@public.gmane.org>
Hi,
On 2018/5/24 23:04, Jean-Philippe Brucker wrote:
> On 24/05/18 13:35, Xu Zaibo wrote:
>>> Right, sva_init() must be called once for any device that intends to use
>>> bind(). For the second process though, group->sva_enabled will be true
>>> so we won't call sva_init() again, only bind().
>> Well, while I create mediated devices based on one parent device to support multiple
>> processes(a new process will create a new 'vfio_group' for the corresponding mediated device,
>> and 'sva_enabled' cannot work any more), in fact, *sva_init and *sva_shutdown are basically
>> working on parent device, so, as a result, I just only need sva initiation and shutdown on the
>> parent device only once. So I change the two as following:
>>
>> @@ -551,8 +565,18 @@ int iommu_sva_device_init(struct device *dev, unsigned long features,
>> if (features & ~IOMMU_SVA_FEAT_IOPF)
>> return -EINVAL;
>>
>> + /* If already exists, do nothing */
>> + mutex_lock(&dev->iommu_param->lock);
>> + if (dev->iommu_param->sva_param) {
>> + mutex_unlock(&dev->iommu_param->lock);
>> + return 0;
>> + }
>> + mutex_unlock(&dev->iommu_param->lock);
>>
>> if (features & IOMMU_SVA_FEAT_IOPF) {
>> ret = iommu_register_device_fault_handler(dev, iommu_queue_iopf,
>>
>>
>> @@ -621,6 +646,14 @@ int iommu_sva_device_shutdown(struct device *dev)
>> if (!domain)
>> return -ENODEV;
>>
>> + /* If any other process is working on the device, shut down does nothing. */
>> + mutex_lock(&dev->iommu_param->lock);
>> + if (!list_empty(&dev->iommu_param->sva_param->mm_list)) {
>> + mutex_unlock(&dev->iommu_param->lock);
>> + return 0;
>> + }
>> + mutex_unlock(&dev->iommu_param->lock);
> I don't think iommu-sva.c is the best place for this, it's probably
> better to implement an intermediate layer (the mediating driver), that
> calls iommu_sva_device_init() and iommu_sva_device_shutdown() once. Then
> vfio-pci would still call these functions itself, but for mdev the
> mediating driver keeps a refcount of groups, and calls device_shutdown()
> only when freeing the last mdev.
>
> A device driver (non mdev in this example) expects to be able to free
> all its resources after sva_device_shutdown() returns. Imagine the
> mm_list isn't empty (mm_exit() is running late), and instead of waiting
> in unbind_dev_all() below, we return 0 immediately. Then the calling
> driver frees its resources, and the mm_exit callback along with private
> data passed to bind() disappear. If a mm_exit() is still running in
> parallel, then it will try to access freed data and corrupt memory. So
> in this function if mm_list isn't empty, the only thing we can do is wait.
>
I still don't understand why we should 'unbind_dev_all', is it possible
to do a 'unbind_dev_pasid'?
Then we can do other things instead of waiting that user may not like. :)
Thanks
Zaibo
>
>> +
>> __iommu_sva_unbind_dev_all(dev);
>>
>> mutex_lock(&dev->iommu_param->lock);
>>
>> I add the above two checkings in both *sva_init and *sva_shutdown, it is working now,
>> but i don't know if it will cause any new problems. What's more, i doubt if it is
>> reasonable to check this to avoid repeating operation in VFIO, maybe it is better to check
>> in IOMMU. :)
>
>
>
> .
>
^ permalink raw reply
* Re: [PATCH] arm64: dts: sprd: fix typo in 'remote-endpoint'
From: Chunyan Zhang @ 2018-05-25 2:36 UTC (permalink / raw)
To: Rob Herring, arm@kernel.org; +Cc: Orson Zhai, DTML, Linux ARM, Baolin Wang
In-Reply-To: <CAL_JsqKrsTpgnLfxhcxeucpoh9NkyGwwZq82QUBgJZrdjGYQzg@mail.gmail.com>
Hi Arnd, Olof
Could you please take this patch through arm-soc git?
Thanks,
Chunyan
On 24 May 2018 at 04:30, Rob Herring <robh@kernel.org> wrote:
> On Tue, May 8, 2018 at 8:58 PM, Chunyan Zhang <zhang.lyra@gmail.com> wrote:
>> Hi Rob,
>>
>> On 8 May 2018 at 23:09, Rob Herring <robh@kernel.org> wrote:
>>> dtc now warns on incomplete OF graph endpoint connections:
>>>
>>> arch/arm64/boot/dts/sprd/sp9860g-1h10.dtb: Warning (graph_endpoint): /soc/stm@10006000/port/endpoint: graph connection to node '/soc/funnel@10001000/ports/port@2/endpoint' is not bidirectional
>>>
>>> The cause is a typo in 'remote-endpoint'.
>>
>> Thanks for fixing this and,
>>
>> Acked-by: Chunyan Zhang <zhang.lyra@gmail.com>
>
> Is someone going to apply this? Still seeing warnings in linux-next.
>
> Rob
^ permalink raw reply
* [PATCH v3 8/8] drm/mediatek: add third ddp path
From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw)
To: CK Hu, Philipp Zabel
Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek, Stu Hsieh,
Matthias Brugger, linux-arm-kernel
In-Reply-To: <1527215665-11937-1-git-send-email-stu.hsieh@mediatek.com>
From: Stu Hsieh <stu.hsieh@mediatek.com>
This patch create third crtc by third ddp path
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index b32c4cc8d051..3a866e1d6af4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -267,6 +267,11 @@ static int mtk_drm_kms_init(struct drm_device *drm)
if (ret < 0)
goto err_component_unbind;
+ ret = mtk_drm_crtc_create(drm, private->data->third_path,
+ private->data->third_len);
+ if (ret < 0)
+ goto err_component_unbind;
+
/* Use OVL device for all DMA memory allocations */
np = private->comp_node[private->data->main_path[0]] ?:
private->comp_node[private->data->ext_path[0]];
--
2.12.5
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^ permalink raw reply related
* [PATCH v3 7/8] drm/mediatek: Add support for mediatek SOC MT2712
From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw)
To: CK Hu, Philipp Zabel
Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek, Stu Hsieh,
Matthias Brugger, linux-arm-kernel
In-Reply-To: <1527215665-11937-1-git-send-email-stu.hsieh@mediatek.com>
From: Stu Hsieh <stu.hsieh@mediatek.com>
This patch add support for the Mediatek MT2712 DISP subsystem.
There are two OVL engine and three disp output in MT2712.
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 46 +++++++++++++++++++++++++++--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++--
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 ++++++++++++++++++++++++--
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +++--
4 files changed, 94 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 0f568dd853d8..676726249ae0 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -61,6 +61,24 @@
#define MT8173_MUTEX_MOD_DISP_PWM1 24
#define MT8173_MUTEX_MOD_DISP_OD 25
+#define MT2712_MUTEX_MOD_DISP_OVL0 11
+#define MT2712_MUTEX_MOD_DISP_OVL1 12
+#define MT2712_MUTEX_MOD_DISP_RDMA0 13
+#define MT2712_MUTEX_MOD_DISP_RDMA1 14
+#define MT2712_MUTEX_MOD_DISP_RDMA2 15
+#define MT2712_MUTEX_MOD_DISP_WDMA0 16
+#define MT2712_MUTEX_MOD_DISP_WDMA1 17
+#define MT2712_MUTEX_MOD_DISP_COLOR0 18
+#define MT2712_MUTEX_MOD_DISP_COLOR1 19
+#define MT2712_MUTEX_MOD_DISP_AAL0 20
+#define MT2712_MUTEX_MOD_DISP_UFOE 22
+#define MT2712_MUTEX_MOD_DISP_PWM0 23
+#define MT2712_MUTEX_MOD_DISP_PWM1 24
+#define MT2712_MUTEX_MOD_DISP_PWM2 10
+#define MT2712_MUTEX_MOD_DISP_OD0 25
+#define MT2712_MUTEX_MOD2_DISP_AAL1 33
+#define MT2712_MUTEX_MOD2_DISP_OD1 34
+
#define MT2701_MUTEX_MOD_DISP_OVL 3
#define MT2701_MUTEX_MOD_DISP_WDMA 6
#define MT2701_MUTEX_MOD_DISP_COLOR 7
@@ -75,6 +93,7 @@
#define OVL0_MOUT_EN_COLOR0 0x1
#define OD_MOUT_EN_RDMA0 0x1
+#define OD1_MOUT_EN_RDMA1 BIT(16)
#define UFOE_MOUT_EN_DSI0 0x1
#define COLOR0_SEL_IN_OVL0 0x1
#define OVL1_MOUT_EN_COLOR1 0x1
@@ -109,12 +128,32 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
};
+static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
+ [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
+ [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
+ [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1,
+ [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0,
+ [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1,
+ [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1,
+ [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0,
+ [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1,
+ [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2,
+ [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1,
+ [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2,
+ [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE,
+ [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0,
+ [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
+};
+
static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
- [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL,
+ [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
[DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA,
- [DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD,
+ [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD,
[DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1,
[DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0,
@@ -139,7 +178,7 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
value = OVL_MOUT_EN_RDMA;
- } else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) {
+ } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD_MOUT_EN_RDMA0;
} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
@@ -429,6 +468,7 @@ static int mtk_ddp_remove(struct platform_device *pdev)
static const struct of_device_id ddp_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod},
+ { .compatible = "mediatek,mt2712-disp-mutex", .data = mt2712_mutex_mod},
{ .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod},
{},
};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 4672317e3ad1..86e8c9e5df41 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -218,7 +218,8 @@ struct mtk_ddp_comp_match {
};
static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
- [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, &ddp_aal },
+ [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
+ [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
[DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
[DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL },
[DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL },
@@ -226,10 +227,13 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL },
[DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL },
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
- [DDP_COMPONENT_OD] = { MTK_DISP_OD, 0, &ddp_od },
+ [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
+ [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
[DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL },
[DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL },
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
+ [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
+ [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
[DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL },
[DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL },
[DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index a2ca90fc403c..b32c4cc8d051 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -146,11 +146,37 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
DDP_COMPONENT_DPI0,
};
+static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_OD0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_DPI0,
+ DDP_COMPONENT_PWM0,
+};
+
+static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = {
+ DDP_COMPONENT_OVL1,
+ DDP_COMPONENT_COLOR1,
+ DDP_COMPONENT_AAL1,
+ DDP_COMPONENT_OD1,
+ DDP_COMPONENT_RDMA1,
+ DDP_COMPONENT_DPI1,
+ DDP_COMPONENT_PWM1,
+};
+
+static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
+ DDP_COMPONENT_RDMA2,
+ DDP_COMPONENT_DSI2,
+ DDP_COMPONENT_PWM2,
+};
+
static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_COLOR0,
- DDP_COMPONENT_AAL,
- DDP_COMPONENT_OD,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_OD0,
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_UFOE,
DDP_COMPONENT_DSI0,
@@ -173,6 +199,15 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.shadow_register = true,
};
+static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
+ .main_path = mt2712_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
+ .ext_path = mt2712_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
+ .third_path = mt2712_mtk_ddp_third,
+ .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
+};
+
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.main_path = mt8173_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
@@ -374,6 +409,7 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
{ .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI },
{ .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS },
{ .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM },
@@ -552,6 +588,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
static const struct of_device_id mtk_drm_of_ids[] = {
{ .compatible = "mediatek,mt2701-mmsys",
.data = &mt2701_mmsys_driver_data},
+ { .compatible = "mediatek,mt2712-mmsys",
+ .data = &mt2712_mmsys_driver_data},
{ .compatible = "mediatek,mt8173-mmsys",
.data = &mt8173_mmsys_driver_data},
{ }
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index c3378c452c0a..e821342bc2d3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -17,8 +17,8 @@
#include <linux/io.h>
#include "mtk_drm_ddp_comp.h"
-#define MAX_CRTC 2
-#define MAX_CONNECTOR 2
+#define MAX_CRTC 3
+#define MAX_CONNECTOR 3
struct device;
struct device_node;
@@ -33,6 +33,9 @@ struct mtk_mmsys_driver_data {
unsigned int main_len;
const enum mtk_ddp_comp_id *ext_path;
unsigned int ext_len;
+ enum mtk_ddp_comp_id *third_path;
+ unsigned int third_len;
+
bool shadow_register;
};
--
2.12.5
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* [PATCH v3 6/8] drm/mediatek: add ddp component PWM2
From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw)
To: CK Hu, Philipp Zabel
Cc: David Airlie, Rob Herring, Mark Rutland, Matthias Brugger,
dri-devel, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, srv_heupstream, Stu Hsieh
In-Reply-To: <1527215665-11937-1-git-send-email-stu.hsieh@mediatek.com>
From: Stu Hsieh <stu.hsieh@mediatek.com>
This patch add component PWM2
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 9b19fc4423f1..e00c2e798abd 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -56,6 +56,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL1,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
+ DDP_COMPONENT_PWM2,
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_RDMA1,
DDP_COMPONENT_RDMA2,
--
2.12.5
^ permalink raw reply related
* [PATCH v3 5/8] drm/mediatek: add ddp component OD1
From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw)
To: CK Hu, Philipp Zabel
Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek, Stu Hsieh,
Matthias Brugger, linux-arm-kernel
In-Reply-To: <1527215665-11937-1-git-send-email-stu.hsieh@mediatek.com>
From: Stu Hsieh <stu.hsieh@mediatek.com>
This patch add the component OD1 and
rename the OD to OD1
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index eee3c0cc2632..9b19fc4423f1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -50,7 +50,8 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_DSI0,
DDP_COMPONENT_DSI1,
DDP_COMPONENT_GAMMA,
- DDP_COMPONENT_OD,
+ DDP_COMPONENT_OD0,
+ DDP_COMPONENT_OD1,
DDP_COMPONENT_OVL0,
DDP_COMPONENT_OVL1,
DDP_COMPONENT_PWM0,
--
2.12.5
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* [PATCH v3 4/8] drm/mediatek: add ddp component AAL1
From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw)
To: CK Hu, Philipp Zabel
Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek, Stu Hsieh,
Matthias Brugger, linux-arm-kernel
In-Reply-To: <1527215665-11937-1-git-send-email-stu.hsieh@mediatek.com>
From: Stu Hsieh <stu.hsieh@mediatek.com>
This patch add component AAL1 and
rename AAL to AAL0
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 0828cf8bf85c..eee3c0cc2632 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -41,7 +41,8 @@ enum mtk_ddp_comp_type {
};
enum mtk_ddp_comp_id {
- DDP_COMPONENT_AAL,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_AAL1,
DDP_COMPONENT_BLS,
DDP_COMPONENT_COLOR0,
DDP_COMPONENT_COLOR1,
--
2.12.5
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^ permalink raw reply related
* [PATCH v3 3/8] drm/mediatek: add connection from OD1 to RDMA1
From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw)
To: CK Hu, Philipp Zabel
Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek, Stu Hsieh,
Matthias Brugger, linux-arm-kernel
In-Reply-To: <1527215665-11937-1-git-send-email-stu.hsieh@mediatek.com>
From: Stu Hsieh <stu.hsieh@mediatek.com>
This patch add the connection from OD1 to RDMA1 for ext path.
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 47ffa240bd25..0f568dd853d8 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -151,6 +151,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
value = GAMMA_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
+ *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ value = OD1_MOUT_EN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
*addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN;
value = RDMA1_MOUT_DPI0;
--
2.12.5
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* [PATCH v3 2/8] drm/mediatek: support maximum 64 mutex mod
From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw)
To: CK Hu, Philipp Zabel
Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek, Stu Hsieh,
Matthias Brugger, linux-arm-kernel
In-Reply-To: <1527215665-11937-1-git-send-email-stu.hsieh@mediatek.com>
From: Stu Hsieh <stu.hsieh@mediatek.com>
This patch support that if modules more than 32,
add index more than 31 when using DISP_REG_MUTEX_MOD2 bit
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 75 +++++++++++++++++++++-------------
1 file changed, 47 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 8130f3dab661..47ffa240bd25 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -41,31 +41,32 @@
#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
#define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
#define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n))
+#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
#define INT_MUTEX BIT(1)
-#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
-#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
-#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
-#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
-#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
-#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
-#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
-#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
-#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
-#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
-#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
-#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
-#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
-#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
-#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
-
-#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
-#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
-#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7)
-#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
-#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10)
-#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12)
+#define MT8173_MUTEX_MOD_DISP_OVL0 11
+#define MT8173_MUTEX_MOD_DISP_OVL1 12
+#define MT8173_MUTEX_MOD_DISP_RDMA0 13
+#define MT8173_MUTEX_MOD_DISP_RDMA1 14
+#define MT8173_MUTEX_MOD_DISP_RDMA2 15
+#define MT8173_MUTEX_MOD_DISP_WDMA0 16
+#define MT8173_MUTEX_MOD_DISP_WDMA1 17
+#define MT8173_MUTEX_MOD_DISP_COLOR0 18
+#define MT8173_MUTEX_MOD_DISP_COLOR1 19
+#define MT8173_MUTEX_MOD_DISP_AAL 20
+#define MT8173_MUTEX_MOD_DISP_GAMMA 21
+#define MT8173_MUTEX_MOD_DISP_UFOE 22
+#define MT8173_MUTEX_MOD_DISP_PWM0 23
+#define MT8173_MUTEX_MOD_DISP_PWM1 24
+#define MT8173_MUTEX_MOD_DISP_OD 25
+
+#define MT2701_MUTEX_MOD_DISP_OVL 3
+#define MT2701_MUTEX_MOD_DISP_WDMA 6
+#define MT2701_MUTEX_MOD_DISP_COLOR 7
+#define MT2701_MUTEX_MOD_DISP_BLS 9
+#define MT2701_MUTEX_MOD_DISP_RDMA0 10
+#define MT2701_MUTEX_MOD_DISP_RDMA1 12
#define MUTEX_SOF_SINGLE_MODE 0
#define MUTEX_SOF_DSI0 1
@@ -278,6 +279,7 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
mutex[mutex->id]);
unsigned int reg;
+ unsigned int offset;
WARN_ON(&ddp->mutex[mutex->id] != mutex);
@@ -292,9 +294,17 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
reg = MUTEX_SOF_DPI0;
break;
default:
- reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
- reg |= ddp->mutex_mod[id];
- writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
+ if (ddp->mutex_mod[id] < 32) {
+ offset = DISP_REG_MUTEX_MOD(mutex->id);
+ reg = readl_relaxed(ddp->regs + offset);
+ reg |= 1 << ddp->mutex_mod[id];
+ writel_relaxed(reg, ddp->regs + offset);
+ } else {
+ offset = DISP_REG_MUTEX_MOD2(mutex->id);
+ reg = readl_relaxed(ddp->regs + offset);
+ reg |= 1 << (ddp->mutex_mod[id] - 32);
+ writel_relaxed(reg, ddp->regs + offset);
+ }
return;
}
@@ -307,6 +317,7 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex,
struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
mutex[mutex->id]);
unsigned int reg;
+ unsigned int offset;
WARN_ON(&ddp->mutex[mutex->id] != mutex);
@@ -318,9 +329,17 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex,
ddp->regs + DISP_REG_MUTEX_SOF(mutex->id));
break;
default:
- reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
- reg &= ~(ddp->mutex_mod[id]);
- writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
+ if (ddp->mutex_mod[id] < 32) {
+ offset = DISP_REG_MUTEX_MOD(mutex->id);
+ reg = readl_relaxed(ddp->regs + offset);
+ reg &= ~(1 << ddp->mutex_mod[id]);
+ writel_relaxed(reg, ddp->regs + offset);
+ } else {
+ offset = DISP_REG_MUTEX_MOD2(mutex->id);
+ reg = readl_relaxed(ddp->regs + offset);
+ reg &= ~(1 << (ddp->mutex_mod[id] - 32));
+ writel_relaxed(reg, ddp->regs + offset);
+ }
break;
}
}
--
2.12.5
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^ permalink raw reply related
* [PATCH v3 1/8] drm/mediatek: update dt-bindings for mt2712
From: stu.hsieh @ 2018-05-25 2:34 UTC (permalink / raw)
To: CK Hu, Philipp Zabel
Cc: Mark Rutland, devicetree, srv_heupstream, David Airlie,
linux-kernel, dri-devel, Rob Herring, linux-mediatek, Stu Hsieh,
Matthias Brugger, linux-arm-kernel
In-Reply-To: <1527215665-11937-1-git-send-email-stu.hsieh@mediatek.com>
From: Stu Hsieh <stu.hsieh@mediatek.com>
Update device tree binding documentation for the display subsystem for
Mediatek MT2712 SoCs.
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
index 383183a89164..8469de510001 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
@@ -40,7 +40,7 @@ Required properties (all function blocks):
"mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
"mediatek,<chip>-disp-mutex" - display mutex
"mediatek,<chip>-disp-od" - overdrive
- the supported chips are mt2701 and mt8173.
+ the supported chips are mt2701, mt2712 and mt8173.
- reg: Physical base address and length of the function block register space
- interrupts: The interrupt signal from the function block (required, except for
merge and split function blocks).
--
2.12.5
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