* [PATCH v4 0/6] Enhance support for the SP805 WDT
From: Ray Jui @ 2018-05-28 18:01 UTC (permalink / raw)
To: Wim Van Sebroeck, Guenter Roeck, Rob Herring, Mark Rutland,
Frank Rowand, Catalin Marinas, Will Deacon, Robin Murphy
Cc: linux-watchdog, devicetree, linux-arm-kernel, linux-kernel,
bcm-kernel-feedback-list, Ray Jui
This patch series enhances the support for the SP805 watchdog timer.
First of all, 'timeout-sec' devicetree property is added. In addition,
support is also added to allow the driver to reset the watchdog if it
has been detected that watchdot has been started in the bootloader. In
this case, the driver will initiate the ping service from the kernel
watchdog subsystem, before a user mode daemon takes over. This series
also enables SP805 in the default ARM64 defconfig
This patch series is based off v4.17-rc5 and is available on GIHUB:
repo: https://github.com/Broadcom/arm64-linux.git
branch: sp805-wdt-v4
Changes since v3:
- Improve description of 'timeout-sec' in the binding document, per
recommendation from Guenter Roeck
Changes since v2:
- Fix indent and format to make them consistent within arm,sp805.txt
Changes since v1:
- Consolidate two duplicated SP805 binding documents into one
- Slight change of the wdt_is_running implementation per discussion
Ray Jui (6):
Documentation: DT: Consolidate SP805 binding docs
Documentation: DT: Add optional 'timeout-sec' property for sp805
watchdog: sp805: add 'timeout-sec' DT property support
watchdog: sp805: set WDOG_HW_RUNNING when appropriate
arm64: dt: set initial SR watchdog timeout to 60 seconds
arm64: defconfig: add CONFIG_ARM_SP805_WATCHDOG
.../devicetree/bindings/watchdog/arm,sp805.txt | 29 +++++++++++++++-----
.../devicetree/bindings/watchdog/sp805-wdt.txt | 31 ----------------------
.../arm64/boot/dts/broadcom/stingray/stingray.dtsi | 1 +
arch/arm64/configs/defconfig | 1 +
drivers/watchdog/sp805_wdt.c | 28 ++++++++++++++++++-
5 files changed, 51 insertions(+), 39 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/watchdog/sp805-wdt.txt
--
2.1.4
^ permalink raw reply
* [PATCH 2/4 RFCv2] net: dsa: Add bindings for Realtek SMI DSAs
From: Linus Walleij @ 2018-05-28 17:47 UTC (permalink / raw)
To: Andrew Lunn, Vivien Didelot, Florian Fainelli
Cc: netdev, openwrt-devel, LEDE Development List, Linus Walleij,
Antti Seppälä, Roman Yeryomin, Colin Leitner,
Gabor Juhos, devicetree
In-Reply-To: <20180528174752.6806-1-linus.walleij@linaro.org>
The Realtek SMI family is a set of DSA chips that provide
switching in routers. This binding just follows the pattern
set by other switches but with the introduction of an embedded
irqchip to demux and handle the interrupts fired by the single
line from the chip.
This interrupt construction is similar to how we handle
interrupt controllers inside PCI bridges etc.
Cc: Antti Seppälä <a.seppala@gmail.com>
Cc: Roman Yeryomin <roman@advem.lv>
Cc: Colin Leitner <colin.leitner@googlemail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog RFCv1->RFCv2:
- Switch to Andrew's suggestion to have a local MDIO bus
definition inside of the DSA device node
- Add realtek,disabled-leds
- Correct WAN IRQ to 12 in the example
---
.../bindings/net/dsa/realtek-smi.txt | 153 ++++++++++++++++++
1 file changed, 153 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/dsa/realtek-smi.txt
diff --git a/Documentation/devicetree/bindings/net/dsa/realtek-smi.txt b/Documentation/devicetree/bindings/net/dsa/realtek-smi.txt
new file mode 100644
index 000000000000..b6ae8541bd55
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dsa/realtek-smi.txt
@@ -0,0 +1,153 @@
+Realtek SMI-based Switches
+==========================
+
+The SMI "Simple Management Interface" is a two-wire protocol using
+bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
+not use the MDIO protocol. This binding defines how to specify the
+SMI-based Realtek devices.
+
+Required properties:
+
+- compatible: must be exactly one of:
+ "realtek,rtl8366"
+ "realtek,rtl8366rb" (4+1 ports)
+ "realtek,rtl8366s" (4+1 ports)
+ "realtek,rtl8367"
+ "realtek,rtl8367b"
+ "realtek,rtl8368s" (8 port)
+ "realtek,rtl8369"
+ "realtek,rtl8370" (8 port)
+
+Required properties:
+- mdc-gpios: GPIO line for the MDC clock line.
+- mdio-gpios: GPIO line for the MDIO data line.
+- reset-gpios: GPIO line for the reset signal.
+
+Optional properties:
+- realtek,disable-leds: if the LED drivers are not used in the
+ hardware design this will disable them so they are not turned on
+ and wasting power.
+
+Required subnodes:
+
+- interrupt-controller
+
+ This defines an interrupt controller with an IRQ line (typically
+ a GPIO) that will demultiplex and handle the interrupt from the single
+ interrupt line coming out of one of the SMI-based chips. It most
+ importantly provides link up/down interrupts to the PHY blocks inside
+ the ASIC.
+
+Required properties of interrupt-controller:
+
+- interrupt: parent interrupt, see interrupt-controller/interrupts.txt
+- interrupt-controller: see interrupt-controller/interrupts.txt
+- #address-cells: should be <0>
+- #interrupt-cells: should be <1>
+
+- mdio
+
+ This defines the internal MDIO bus of the SMI device, mostly for the
+ purpose of being able to hook the interrupts to the right PHY and
+ the right PHY to the corresponding port.
+
+Required properties of mdio:
+
+- compatible: should be set to "realtek,smi-mdio" for all SMI devices
+
+See net/mdio.txt for additional MDIO bus properties.
+
+See net/dsa/dsa.txt for a list of additional required and optional properties
+and subnodes of DSA switches.
+
+Examples:
+
+switch {
+ compatible = "realtek,rtl8366rb";
+ /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
+ mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
+ mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+
+ switch_intc: interrupt-controller {
+ /* GPIO 15 provides the interrupt */
+ interrupt-parent = <&gpio0>;
+ interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ port@0 {
+ reg = <0>;
+ label = "lan0";
+ phy-handle = <&phy0>;
+ };
+ port@1 {
+ reg = <1>;
+ label = "lan1";
+ phy-handle = <&phy1>;
+ };
+ port@2 {
+ reg = <2>;
+ label = "lan2";
+ phy-handle = <&phy2>;
+ };
+ port@3 {
+ reg = <3>;
+ label = "lan3";
+ phy-handle = <&phy3>;
+ };
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ phy-handle = <&phy4>;
+ };
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "rgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+
+ mdio {
+ compatible = "realtek,smi-mdio", "dsa-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy0: phy@0 {
+ reg = <0>;
+ interrupt-parent = <&switch_intc>;
+ interrupts = <0>;
+ };
+ phy1: phy@1 {
+ reg = <1>;
+ interrupt-parent = <&switch_intc>;
+ interrupts = <1>;
+ };
+ phy2: phy@2 {
+ reg = <2>;
+ interrupt-parent = <&switch_intc>;
+ interrupts = <2>;
+ };
+ phy3: phy@3 {
+ reg = <3>;
+ interrupt-parent = <&switch_intc>;
+ interrupts = <3>;
+ };
+ phy4: phy@4 {
+ reg = <4>;
+ interrupt-parent = <&switch_intc>;
+ interrupts = <12>;
+ };
+ };
+};
--
2.17.0
^ permalink raw reply related
* Re: [PATCH v2 3/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver
From: Boris Brezillon @ 2018-05-28 16:57 UTC (permalink / raw)
To: Benjamin Lindqvist
Cc: Stefan Agner, Dmitry Osipenko, David Woodhouse, Brian Norris,
Marek Vašut, robh+dt, mark.rutland, Thierry Reding,
Michael Turquette, sboyd, Lucas Stach, Miquel Raynal, richard,
Marcel Ziswiler, krzk, jonathanh, pdeschrijver, Prashant Gaikwad,
Mirza Krak, linux-mtd, linux-tegra, devicetree, linux-kernel,
linux-clk
In-Reply-To: <CAGefG56pyKd=rCjArVtvO1mnXzacrD+BW4_AkJSDRtw-2Gf3Nw@mail.gmail.com>
On Mon, 28 May 2018 18:41:26 +0200
Benjamin Lindqvist <benjamin.lindqvist@endian.se> wrote:
> Note that it's certainly possible to encode U-Boot and kernel with
> RS[4] and still use RS[8] for the rootfs even if the boot rom doesn't
> support it.
Not if you want to read/write from/to the uboot partition from Linux.
Per-partition ECC setup is not supported, so the only solutions we have
right now are:
1/ use the same ECC config as the one use by the bootrom
2/ only access uboot partition in raw mode from Linux (that implies
generating images containing the ECC bytes so that they can be
flashed to the device in raw mode)
3/ never access uboot partitions from Linux (not sure we want that)
> This whole 'use-bootable-ecc-only' business seems a bit
> overengineered.
>
Hm, I don't find it over-engineered.
^ permalink raw reply
* Re: [PATCH 12/12] ARM: dts: exynos5250-arndale: add dsi and panel nodes
From: Krzysztof Kozlowski @ 2018-05-28 16:41 UTC (permalink / raw)
To: Maciej Purski
Cc: Mark Rutland, devicetree, linux-samsung-soc@vger.kernel.org,
Bartlomiej Zolnierkiewicz, David Airlie, Seung-Woo Kim,
linux-kernel, dri-devel, Kyungmin Park, Rob Herring,
Thierry Reding, Kukjin Kim, Marek Szyprowski, linux-arm-kernel,
Laurent Pinchart
In-Reply-To: <1527501347-16521-1-git-send-email-m.purski@samsung.com>
On Mon, May 28, 2018 at 11:55 AM, Maciej Purski <m.purski@samsung.com> wrote:
> The patch adds bridge and panel nodes.
> It adds also DSI properties specific for arndale board.
>
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> Signed-off-by: Maciej Purski <m.purski@samsung.com>
> ---
> arch/arm/boot/dts/exynos5250-arndale.dts | 39 ++++++++++++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
> index 80221fa..6f0b1c4 100644
> --- a/arch/arm/boot/dts/exynos5250-arndale.dts
> +++ b/arch/arm/boot/dts/exynos5250-arndale.dts
> @@ -71,6 +71,17 @@
> };
> };
>
> + panel: panel {
> + compatible = "boe,hv070wsa-100";
> + power-supply = <&vcc_3v3_reg>;
> + enable-gpios = <&gpd1 3 GPIO_ACTIVE_HIGH>;
> + port {
> + panel_ep: endpoint {
> + remote-endpoint = <&bridge_out_ep>;
> + };
> + };
> + };
> +
> regulators {
> compatible = "simple-bus";
> #address-cells = <1>;
> @@ -476,6 +487,34 @@
> };
> };
>
> +&dsi_0 {
Please put the node alphabetically, so before &dp.
Also this patch should be squashed with previous one (regulators),
because adding non-controllable fixed regulators on its own does not
bring benefits. Linux will not disable them. You added these
regulators for the bridge below. Without the bridge, their existence
does not have much sense.
Best regards,
Krzysztof
> + vddcore-supply = <&ldo8_reg>;
> + vddio-supply = <&ldo10_reg>;
> + samsung,pll-clock-frequency = <24000000>;
> + samsung,burst-clock-frequency = <320000000>;
> + samsung,esc-clock-frequency = <10000000>;
> + status = "okay";
> +
> + bridge@0 {
> + reg = <0>;
> + compatible = "toshiba,tc358764";
> + vddc-supply = <&vcc_1v2_reg>;
> + vddio-supply = <&vcc_1v8_reg>;
> + vddmipi-supply = <&vcc_1v2_reg>;
> + vddlvds133-supply = <&vcc_3v3_reg>;
> + vddlvds112-supply = <&vcc_1v2_reg>;
> + reset-gpios = <&gpd1 6 GPIO_ACTIVE_LOW>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port@1 {
> + reg = <1>;
> + bridge_out_ep: endpoint {
> + remote-endpoint = <&panel_ep>;
> + };
> + };
> + };
> +};
> +
> &i2c_2 {
> status = "okay";
> /* used by HDMI DDC */
> --
> 2.7.4
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCH v2 3/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver
From: Benjamin Lindqvist @ 2018-05-28 16:41 UTC (permalink / raw)
To: Stefan Agner
Cc: Dmitry Osipenko, Boris Brezillon, David Woodhouse, Brian Norris,
Marek Vašut, robh+dt, mark.rutland, Thierry Reding,
Michael Turquette, sboyd, Lucas Stach, Miquel Raynal, richard,
Marcel Ziswiler, krzk, jonathanh, pdeschrijver, Prashant Gaikwad,
Mirza Krak, linux-mtd, linux-tegra, devicetree, linux-kernel,
linux-clk
In-Reply-To: <c4df253d318e7c268e8999d5f3bfcd0f@agner.ch>
Note that it's certainly possible to encode U-Boot and kernel with
RS[4] and still use RS[8] for the rootfs even if the boot rom doesn't
support it. This whole 'use-bootable-ecc-only' business seems a bit
overengineered.
2018-05-28 14:43 GMT+02:00 Stefan Agner <stefan@agner.ch>:
> On 28.05.2018 13:57, Dmitry Osipenko wrote:
>> On 28.05.2018 00:54, Stefan Agner wrote:
>>> Add support for the NAND flash controller found on NVIDIA
>>> Tegra 2 SoCs. This implementation does not make use of the
>>> command queue feature. Regular operations/data transfers are
>>> done in PIO mode. Page read/writes with hardware ECC make
>>> use of the DMA for data transfer.
>>>
>>> Signed-off-by: Lucas Stach <dev@lynxeye.de>
>>> Signed-off-by: Stefan Agner <stefan@agner.ch>
>>> ---
>>> MAINTAINERS | 7 +
>>> drivers/mtd/nand/raw/Kconfig | 6 +
>>> drivers/mtd/nand/raw/Makefile | 1 +
>>> drivers/mtd/nand/raw/tegra_nand.c | 999 ++++++++++++++++++++++++++++++
>>> 4 files changed, 1013 insertions(+)
>>> create mode 100644 drivers/mtd/nand/raw/tegra_nand.c
>>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index 58b9861ccf99..8cbbb7111742 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -13844,6 +13844,13 @@ M: Laxman Dewangan <ldewangan@nvidia.com>
>>> S: Supported
>>> F: drivers/input/keyboard/tegra-kbc.c
>>>
>>> +TEGRA NAND DRIVER
>>> +M: Stefan Agner <stefan@agner.ch>
>>> +M: Lucas Stach <dev@lynxeye.de>
>>> +S: Maintained
>>> +F: Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt
>>> +F: drivers/mtd/nand/raw/tegra_nand.c
>>> +
>>> TEGRA PWM DRIVER
>>> M: Thierry Reding <thierry.reding@gmail.com>
>>> S: Supported
>>> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
>>> index 19a2b283fbbe..012c63c6ab47 100644
>>> --- a/drivers/mtd/nand/raw/Kconfig
>>> +++ b/drivers/mtd/nand/raw/Kconfig
>>> @@ -534,4 +534,10 @@ config MTD_NAND_MTK
>>> Enables support for NAND controller on MTK SoCs.
>>> This controller is found on mt27xx, mt81xx, mt65xx SoCs.
>>>
>>> +config MTD_NAND_TEGRA
>>> + tristate "Support for NAND on NVIDIA Tegra"
>>> + depends on ARCH_TEGRA || COMPILE_TEST
>>> + help
>>> + Enables support for NAND flash on NVIDIA Tegra SoC based boards.
>>> +
>>> endif # MTD_NAND
>>> diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
>>> index 165b7ef9e9a1..d5a5f9832b88 100644
>>> --- a/drivers/mtd/nand/raw/Makefile
>>> +++ b/drivers/mtd/nand/raw/Makefile
>>> @@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
>>> obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
>>> obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
>>> obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o
>>> +obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o
>>>
>>> nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
>>> nand-objs += nand_amd.o
>>> diff --git a/drivers/mtd/nand/raw/tegra_nand.c b/drivers/mtd/nand/raw/tegra_nand.c
>>> new file mode 100644
>>> index 000000000000..1a0833d97472
>>> --- /dev/null
>>> +++ b/drivers/mtd/nand/raw/tegra_nand.c
>>> @@ -0,0 +1,999 @@
>>> +// SPDX-License-Identifier: GPL-2.0
>>> +/*
>>> + * Copyright (C) 2018 Stefan Agner <stefan@agner.ch>
>>> + * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
>>> + * Copyright (C) 2012 Avionic Design GmbH
>>> + */
>>> +
>>> +#include <linux/clk.h>
>>> +#include <linux/completion.h>
>>> +#include <linux/delay.h>
>>> +#include <linux/dma-mapping.h>
>>> +#include <linux/err.h>
>>> +#include <linux/gpio/consumer.h>
>>> +#include <linux/interrupt.h>
>>> +#include <linux/io.h>
>>> +#include <linux/module.h>
>>> +#include <linux/mtd/partitions.h>
>>> +#include <linux/mtd/rawnand.h>
>>> +#include <linux/of.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/reset.h>
>>> +
>>> +#define CMD 0x00
>>> +#define CMD_GO (1 << 31)
>>> +#define CMD_CLE (1 << 30)
>>> +#define CMD_ALE (1 << 29)
>>> +#define CMD_PIO (1 << 28)
>>> +#define CMD_TX (1 << 27)
>>> +#define CMD_RX (1 << 26)
>>> +#define CMD_SEC_CMD (1 << 25)
>>> +#define CMD_AFT_DAT (1 << 24)
>>> +#define CMD_TRANS_SIZE(x) (((x - 1) & 0xf) << 20)
>>> +#define CMD_A_VALID (1 << 19)
>>> +#define CMD_B_VALID (1 << 18)
>>> +#define CMD_RD_STATUS_CHK (1 << 17)
>>> +#define CMD_RBSY_CHK (1 << 16)
>>> +#define CMD_CE(x) (1 << (8 + ((x) & 0x7)))
>>> +#define CMD_CLE_SIZE(x) (((x - 1) & 0x3) << 4)
>>> +#define CMD_ALE_SIZE(x) (((x - 1) & 0xf) << 0)
>>> +
>>> +#define STATUS 0x04
>>> +
>>> +#define ISR 0x08
>>> +#define ISR_CORRFAIL_ERR (1 << 24)
>>> +#define ISR_UND (1 << 7)
>>> +#define ISR_OVR (1 << 6)
>>> +#define ISR_CMD_DONE (1 << 5)
>>> +#define ISR_ECC_ERR (1 << 4)
>>> +
>>> +#define IER 0x0c
>>> +#define IER_ERR_TRIG_VAL(x) (((x) & 0xf) << 16)
>>> +#define IER_UND (1 << 7)
>>> +#define IER_OVR (1 << 6)
>>> +#define IER_CMD_DONE (1 << 5)
>>> +#define IER_ECC_ERR (1 << 4)
>>> +#define IER_GIE (1 << 0)
>>> +
>>> +#define CFG 0x10
>>> +#define CFG_HW_ECC (1 << 31)
>>> +#define CFG_ECC_SEL (1 << 30)
>>> +#define CFG_ERR_COR (1 << 29)
>>> +#define CFG_PIPE_EN (1 << 28)
>>> +#define CFG_TVAL_4 (0 << 24)
>>> +#define CFG_TVAL_6 (1 << 24)
>>> +#define CFG_TVAL_8 (2 << 24)
>>> +#define CFG_SKIP_SPARE (1 << 23)
>>> +#define CFG_BUS_WIDTH_8 (0 << 21)
>>> +#define CFG_BUS_WIDTH_16 (1 << 21)
>>> +#define CFG_COM_BSY (1 << 20)
>>> +#define CFG_PS_256 (0 << 16)
>>> +#define CFG_PS_512 (1 << 16)
>>> +#define CFG_PS_1024 (2 << 16)
>>> +#define CFG_PS_2048 (3 << 16)
>>> +#define CFG_PS_4096 (4 << 16)
>>> +#define CFG_SKIP_SPARE_SIZE_4 (0 << 14)
>>> +#define CFG_SKIP_SPARE_SIZE_8 (1 << 14)
>>> +#define CFG_SKIP_SPARE_SIZE_12 (2 << 14)
>>> +#define CFG_SKIP_SPARE_SIZE_16 (3 << 14)
>>> +#define CFG_TAG_BYTE_SIZE(x) ((x) & 0xff)
>>> +
>>> +#define TIMING_1 0x14
>>> +#define TIMING_TRP_RESP(x) (((x) & 0xf) << 28)
>>> +#define TIMING_TWB(x) (((x) & 0xf) << 24)
>>> +#define TIMING_TCR_TAR_TRR(x) (((x) & 0xf) << 20)
>>> +#define TIMING_TWHR(x) (((x) & 0xf) << 16)
>>> +#define TIMING_TCS(x) (((x) & 0x3) << 14)
>>> +#define TIMING_TWH(x) (((x) & 0x3) << 12)
>>> +#define TIMING_TWP(x) (((x) & 0xf) << 8)
>>> +#define TIMING_TRH(x) (((x) & 0xf) << 4)
>>> +#define TIMING_TRP(x) (((x) & 0xf) << 0)
>>> +
>>> +#define RESP 0x18
>>> +
>>> +#define TIMING_2 0x1c
>>> +#define TIMING_TADL(x) ((x) & 0xf)
>>> +
>>> +#define CMD_1 0x20
>>> +#define CMD_2 0x24
>>> +#define ADDR_1 0x28
>>> +#define ADDR_2 0x2c
>>> +
>>> +#define DMA_CTRL 0x30
>>> +#define DMA_CTRL_GO (1 << 31)
>>> +#define DMA_CTRL_IN (0 << 30)
>>> +#define DMA_CTRL_OUT (1 << 30)
>>> +#define DMA_CTRL_PERF_EN (1 << 29)
>>> +#define DMA_CTRL_IE_DONE (1 << 28)
>>> +#define DMA_CTRL_REUSE (1 << 27)
>>> +#define DMA_CTRL_BURST_1 (2 << 24)
>>> +#define DMA_CTRL_BURST_4 (3 << 24)
>>> +#define DMA_CTRL_BURST_8 (4 << 24)
>>> +#define DMA_CTRL_BURST_16 (5 << 24)
>>> +#define DMA_CTRL_IS_DONE (1 << 20)
>>> +#define DMA_CTRL_EN_A (1 << 2)
>>> +#define DMA_CTRL_EN_B (1 << 1)
>>> +
>>> +#define DMA_CFG_A 0x34
>>> +#define DMA_CFG_B 0x38
>>> +
>>> +#define FIFO_CTRL 0x3c
>>> +#define FIFO_CTRL_CLR_ALL (1 << 3)
>>> +
>>> +#define DATA_PTR 0x40
>>> +#define TAG_PTR 0x44
>>> +#define ECC_PTR 0x48
>>> +
>>> +#define DEC_STATUS 0x4c
>>> +#define DEC_STATUS_A_ECC_FAIL (1 << 1)
>>> +#define DEC_STATUS_ERR_COUNT_MASK 0x00ff0000
>>> +#define DEC_STATUS_ERR_COUNT_SHIFT 16
>>> +
>>> +#define HWSTATUS_CMD 0x50
>>> +#define HWSTATUS_MASK 0x54
>>> +#define HWSTATUS_RDSTATUS_MASK(x) (((x) & 0xff) << 24)
>>> +#define HWSTATUS_RDSTATUS_VALUE(x) (((x) & 0xff) << 16)
>>> +#define HWSTATUS_RBSY_MASK(x) (((x) & 0xff) << 8)
>>> +#define HWSTATUS_RBSY_VALUE(x) (((x) & 0xff) << 0)
>>> +
>>> +#define BCH_CONFIG 0xcc
>>> +#define BCH_ENABLE (1 << 0)
>>> +#define BCH_TVAL_4 (0 << 4)
>>> +#define BCH_TVAL_8 (1 << 4)
>>> +#define BCH_TVAL_14 (2 << 4)
>>> +#define BCH_TVAL_16 (3 << 4)
>>> +
>>> +#define DEC_STAT_RESULT 0xd0
>>> +#define DEC_STAT_BUF 0xd4
>>> +#define DEC_STAT_BUF_FAIL_SEC_FLAG_MASK 0xff000000
>>> +#define DEC_STAT_BUF_FAIL_SEC_FLAG_SHIFT 24
>>> +#define DEC_STAT_BUF_CORR_SEC_FLAG_MASK 0x00ff0000
>>> +#define DEC_STAT_BUF_CORR_SEC_FLAG_SHIFT 16
>>> +#define DEC_STAT_BUF_MAX_CORR_CNT_MASK 0x00001f00
>>> +#define DEC_STAT_BUF_MAX_CORR_CNT_SHIFT 8
>>> +
>>> +#define SKIP_SPARE_BYTES 4
>>> +#define BITS_PER_STEP_RS 18
>>> +#define BITS_PER_STEP_BCH 13
>>> +
>>> +struct tegra_nand_controller {
>>> + struct nand_hw_control controller;
>>> + void __iomem *regs;
>>> + struct clk *clk;
>>> + struct device *dev;
>>> + struct completion command_complete;
>>> + struct completion dma_complete;
>>> + bool last_read_error;
>>> + int cur_chip;
>>> + struct nand_chip *chip;
>>> +};
>>> +
>>> +struct tegra_nand_chip {
>>> + struct nand_chip chip;
>>> + struct gpio_desc *wp_gpio;
>>> +};
>>> +
>>> +static inline struct tegra_nand_controller *to_tegra_ctrl(
>>> + struct nand_hw_control *hw_ctrl)
>>> +{
>>> + return container_of(hw_ctrl, struct tegra_nand_controller, controller);
>>> +}
>>> +
>>> +static int tegra_nand_ooblayout_rs_ecc(struct mtd_info *mtd, int section,
>>> + struct mtd_oob_region *oobregion)
>>> +{
>>> + struct nand_chip *chip = mtd_to_nand(mtd);
>>> + int bytes_per_step = (BITS_PER_STEP_RS * chip->ecc.strength) / 8;
>>> +
>>> + if (section > 0)
>>> + return -ERANGE;
>>> +
>>> + oobregion->offset = SKIP_SPARE_BYTES;
>>> + oobregion->length = round_up(bytes_per_step * chip->ecc.steps, 4);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int tegra_nand_ooblayout_rs_free(struct mtd_info *mtd, int section,
>>> + struct mtd_oob_region *oobregion)
>>> +{
>>> + struct nand_chip *chip = mtd_to_nand(mtd);
>>> + int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, 8);
>>> +
>>> + if (section > 0)
>>> + return -ERANGE;
>>> +
>>> + oobregion->offset = SKIP_SPARE_BYTES +
>>> + round_up(bytes_per_step * chip->ecc.steps, 4);
>>> + oobregion->length = mtd->oobsize - oobregion->offset;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static const struct mtd_ooblayout_ops tegra_nand_oob_rs_ops = {
>>> + .ecc = tegra_nand_ooblayout_rs_ecc,
>>> + .free = tegra_nand_ooblayout_rs_free,
>>> +};
>>> +
>>> +static int tegra_nand_ooblayout_bch_ecc(struct mtd_info *mtd, int section,
>>> + struct mtd_oob_region *oobregion)
>>> +{
>>> + struct nand_chip *chip = mtd_to_nand(mtd);
>>> + int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_BCH * chip->ecc.strength, 8);
>>> +
>>> + if (section > 0)
>>> + return -ERANGE;
>>> +
>>> + oobregion->offset = SKIP_SPARE_BYTES;
>>> + oobregion->length = round_up(bytes_per_step * chip->ecc.steps, 4);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int tegra_nand_ooblayout_bch_free(struct mtd_info *mtd, int section,
>>> + struct mtd_oob_region *oobregion)
>>> +{
>>> + struct nand_chip *chip = mtd_to_nand(mtd);
>>> + int bytes_per_step = (BITS_PER_STEP_BCH * chip->ecc.strength) / 8;
>>> +
>>> + if (section > 0)
>>> + return -ERANGE;
>>> +
>>> + oobregion->offset = SKIP_SPARE_BYTES +
>>> + round_up(bytes_per_step * chip->ecc.steps, 4);
>>> + oobregion->length = mtd->oobsize - oobregion->offset;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +/*
>>> + * Layout with tag bytes is
>>> + *
>>> + * --------------------------------------------------------------------------
>>> + * | main area | skip bytes | tag bytes | parity | .. |
>>> + * --------------------------------------------------------------------------
>>> + *
>>> + * If not tag bytes are written, parity moves right after skip bytes!
>>> + */
>>> +static const struct mtd_ooblayout_ops tegra_nand_oob_bch_ops = {
>>> + .ecc = tegra_nand_ooblayout_bch_ecc,
>>> + .free = tegra_nand_ooblayout_bch_free,
>>> +};
>>> +
>>> +static irqreturn_t tegra_nand_irq(int irq, void *data)
>>> +{
>>> + struct tegra_nand_controller *ctrl = data;
>>> + u32 isr, dma;
>>> +
>>> + isr = readl_relaxed(ctrl->regs + ISR);
>>> + dma = readl_relaxed(ctrl->regs + DMA_CTRL);
>>> + dev_dbg(ctrl->dev, "isr %08x\n", isr);
>>> +
>>> + if (!isr && !(dma & DMA_CTRL_IS_DONE))
>>> + return IRQ_NONE;
>>> +
>>> + if (isr & ISR_CORRFAIL_ERR)
>>> + ctrl->last_read_error = true;
>>> +
>>> + if (isr & ISR_CMD_DONE)
>>> + complete(&ctrl->command_complete);
>>> +
>>> + if (isr & ISR_UND)
>>> + dev_dbg(ctrl->dev, "FIFO underrun\n");
>>> +
>>> + if (isr & ISR_OVR)
>>> + dev_dbg(ctrl->dev, "FIFO overrun\n");
>>> +
>>> + /* handle DMA interrupts */
>>> + if (dma & DMA_CTRL_IS_DONE) {
>>> + writel(dma, ctrl->regs + DMA_CTRL);
>>> + complete(&ctrl->dma_complete);
>>> + }
>>> +
>>> + /* clear interrupts */
>>> + writel(isr, ctrl->regs + ISR);
>>> +
>>> + return IRQ_HANDLED;
>>> +}
>>> +
>>> +static int tegra_nand_cmd(struct nand_chip *chip,
>>> + const struct nand_subop *subop)
>>> +{
>>> + const struct nand_op_instr *instr;
>>> + const struct nand_op_instr *instr_data_in = NULL;
>>> + struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
>>> + unsigned int op_id = -1, trfr_in_sz = 0, trfr_out_sz = 0, offset = 0;
>>> + bool first_cmd = true;
>>> + u32 cmd = 0;
>>> + u32 value;
>>> +
>>> + for (op_id = 0; op_id < subop->ninstrs; op_id++) {
>>> + unsigned int naddrs, i;
>>> + const u8 *addrs;
>>> + u32 addr1 = 0, addr2 = 0;
>>> +
>>> + instr = &subop->instrs[op_id];
>>> +
>>> + switch (instr->type) {
>>> + case NAND_OP_CMD_INSTR:
>>> + if (first_cmd) {
>>> + cmd |= CMD_CLE;
>>> + writel(instr->ctx.cmd.opcode, ctrl->regs + CMD_1);
>>> + } else {
>>> + cmd |= CMD_SEC_CMD;
>>> + writel(instr->ctx.cmd.opcode, ctrl->regs + CMD_2);
>>> + }
>>> + first_cmd = false;
>>> + break;
>>> + case NAND_OP_ADDR_INSTR:
>>> + offset = nand_subop_get_addr_start_off(subop, op_id);
>>> + naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
>>> + addrs = &instr->ctx.addr.addrs[offset];
>>> +
>>> + cmd |= CMD_ALE | CMD_ALE_SIZE(naddrs);
>>> + for (i = 0; i < min_t(unsigned int, 4, naddrs); i++)
>>> + addr1 |= *addrs++ << (8 * i);
>>> + naddrs -= i;
>>> + for (i = 0; i < min_t(unsigned int, 4, naddrs); i++)
>>> + addr2 |= *addrs++ << (8 * i);
>>> + writel(addr1, ctrl->regs + ADDR_1);
>>> + writel(addr2, ctrl->regs + ADDR_2);
>>> + break;
>>> +
>>> + case NAND_OP_DATA_IN_INSTR:
>>> + trfr_in_sz = nand_subop_get_data_len(subop, op_id);
>>> + offset = nand_subop_get_data_start_off(subop, op_id);
>>> +
>>> + cmd |= CMD_TRANS_SIZE(trfr_in_sz) | CMD_PIO | CMD_RX | CMD_A_VALID;
>>> +
>>> + instr_data_in = instr;
>>> + break;
>>> +
>>> + case NAND_OP_DATA_OUT_INSTR:
>>> + trfr_out_sz = nand_subop_get_data_len(subop, op_id);
>>> + offset = nand_subop_get_data_start_off(subop, op_id);
>>> + trfr_out_sz = min_t(size_t, trfr_out_sz, 4);
>>> +
>>> + cmd |= CMD_TRANS_SIZE(trfr_out_sz) | CMD_PIO | CMD_TX | CMD_A_VALID;
>>> +
>>> + memcpy(&value, instr->ctx.data.buf.out + offset, trfr_out_sz);
>>> + writel(value, ctrl->regs + RESP);
>>> +
>>> + break;
>>> + case NAND_OP_WAITRDY_INSTR:
>>> + cmd |= CMD_RBSY_CHK;
>>> + break;
>>> +
>>> + }
>>> + }
>>> +
>>> +
>>> + cmd |= CMD_GO | CMD_CE(ctrl->cur_chip);
>>> + writel(cmd, ctrl->regs + CMD);
>>> + wait_for_completion(&ctrl->command_complete);
>>
>> Could this and other completions stuck forever? What about
>> wait_for_completion_timeout() + HW reset / re-init on timeout?
>>
>
> They actually get stuck forever when I try to use DMA without HW ECC...
> I haven't seen it with HW ECC.
>
> But yes, _timeout variant makes sense here. Not sure if re-init is
> necessary since we rewrite all the relevant settings.
>
>
>>> +
>>> + if (instr_data_in) {
>>> + u32 value;
>>> + size_t n = min_t(size_t, trfr_in_sz, 4);
>>> +
>>> + value = readl(ctrl->regs + RESP);
>>> + memcpy(instr_data_in->ctx.data.buf.in + offset, &value, n);
>>> + }
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static const struct nand_op_parser tegra_nand_op_parser = NAND_OP_PARSER(
>>> + NAND_OP_PARSER_PATTERN(tegra_nand_cmd,
>>> + NAND_OP_PARSER_PAT_CMD_ELEM(true),
>>> + NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8),
>>> + NAND_OP_PARSER_PAT_CMD_ELEM(true),
>>> + NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
>>> + NAND_OP_PARSER_PATTERN(tegra_nand_cmd,
>>> + NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, 4)),
>>> + NAND_OP_PARSER_PATTERN(tegra_nand_cmd,
>>> + NAND_OP_PARSER_PAT_CMD_ELEM(true),
>>> + NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8),
>>> + NAND_OP_PARSER_PAT_CMD_ELEM(true),
>>> + NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
>>> + NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, 4)),
>>> + );
>>> +
>>> +static int tegra_nand_exec_op(struct nand_chip *chip,
>>> + const struct nand_operation *op,
>>> + bool check_only)
>>> +{
>>> + return nand_op_parser_exec_op(chip, &tegra_nand_op_parser, op,
>>> + check_only);
>>> +}
>>> +static void tegra_nand_select_chip(struct mtd_info *mtd, int chip_nr)
>>> +{
>>> + struct nand_chip *chip = mtd_to_nand(mtd);
>>> + struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
>>> +
>>> + ctrl->cur_chip = chip_nr;
>>> +}
>>> +
>>> +static u32 tegra_nand_fill_address(struct tegra_nand_controller *ctrl,
>>> + struct nand_chip *chip, int page)
>>> +{
>>> + /* Lower 16-bits are column, always 0 */
>>> + writel(page << 16, ctrl->regs + ADDR_1);
>>> +
>>> + if (chip->options & NAND_ROW_ADDR_3) {
>>> + writel(page >> 16, ctrl->regs + ADDR_2);
>>> + return 5;
>>> + }
>>> +
>>> + return 4;
>>> +}
>>> +
>>> +static void tegra_nand_hw_ecc(struct tegra_nand_controller *ctrl,
>>> + struct nand_chip *chip, bool enable)
>>> +{
>>> + u32 value;
>>> +
>>> + switch (chip->ecc.algo) {
>>> + case NAND_ECC_RS:
>>> + value = readl(ctrl->regs + CFG);
>>> + if (enable)
>>> + value |= CFG_HW_ECC | CFG_ERR_COR;
>>> + else
>>> + value &= ~(CFG_HW_ECC | CFG_ERR_COR);
>>> + writel(value, ctrl->regs + CFG);
>>> + break;
>>> + case NAND_ECC_BCH:
>>> + value = readl(ctrl->regs + BCH_CONFIG);
>>> + if (enable)
>>> + value |= BCH_ENABLE;
>>> + else
>>> + value &= ~BCH_ENABLE;
>>> + writel(value, ctrl->regs + BCH_CONFIG);
>>> + break;
>>> + default:
>>> + dev_err(ctrl->dev, "Unsupported hardware ECC algorithm\n");
>>> + break;
>>> + }
>>> +}
>>> +
>>> +static int tegra_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
>>> + uint8_t *buf, int oob_required, int page)
>>> +{
>>> + struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
>>> + dma_addr_t dma_addr;
>>> + u32 value, addrs;
>>> + int ret, dma_len;
>>> +
>>> + writel(NAND_CMD_READ0, ctrl->regs + CMD_1);
>>> + writel(NAND_CMD_READSTART, ctrl->regs + CMD_2);
>>> +
>>> + addrs = tegra_nand_fill_address(ctrl, chip, page);
>>> +
>>> + dma_len = mtd->writesize + (oob_required ? mtd->oobsize : 0);
>>> + dma_addr = dma_map_single(ctrl->dev, buf, dma_len, DMA_FROM_DEVICE);
>>> + ret = dma_mapping_error(ctrl->dev, dma_addr);
>>> + if (ret) {
>>> + dev_err(ctrl->dev, "dma mapping error\n");
>>> + return -EINVAL;
>>> + }
>>> +
>>> + writel(mtd->writesize - 1, ctrl->regs + DMA_CFG_A);
>>> + writel(dma_addr, ctrl->regs + DATA_PTR);
>>> +
>>> + if (oob_required) {
>>> + struct mtd_oob_region oobregion;
>>> + dma_addr_t dma_addr_oob = dma_addr + mtd->writesize;
>>> +
>>> + mtd_ooblayout_free(mtd, 0, &oobregion);
>>> +
>>> + writel(oobregion.length - 1, ctrl->regs + DMA_CFG_B);
>>> + writel(dma_addr_oob + oobregion.offset, ctrl->regs + TAG_PTR);
>>> + } else {
>>> + writel(0, ctrl->regs + DMA_CFG_B);
>>> + writel(0, ctrl->regs + TAG_PTR);
>>> + }
>>> +
>>> + value = DMA_CTRL_GO | DMA_CTRL_IN | DMA_CTRL_PERF_EN |
>>> + DMA_CTRL_REUSE | DMA_CTRL_IE_DONE | DMA_CTRL_IS_DONE |
>>> + DMA_CTRL_BURST_16 | DMA_CTRL_EN_A;
>>> + if (oob_required)
>>> + value |= DMA_CTRL_EN_B;
>>> + writel(value, ctrl->regs + DMA_CTRL);
>>> +
>>> + value = CMD_CLE | CMD_ALE | CMD_ALE_SIZE(addrs) | CMD_SEC_CMD |
>>> + CMD_RBSY_CHK | CMD_GO | CMD_RX | CMD_TRANS_SIZE(9) |
>>> + CMD_A_VALID | CMD_CE(ctrl->cur_chip);
>>> + if (oob_required)
>>> + value |= CMD_B_VALID;
>>> + writel(value, ctrl->regs + CMD);
>>> +
>>> + wait_for_completion(&ctrl->command_complete);
>>> + wait_for_completion(&ctrl->dma_complete);
>>> +
>>> + dma_unmap_single(ctrl->dev, dma_addr, dma_len, DMA_FROM_DEVICE);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int tegra_nand_read_page_hwecc(struct mtd_info *mtd,
>>> + struct nand_chip *chip,
>>> + uint8_t *buf, int oob_required, int page)
>>> +{
>>> + struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
>>> + u32 value;
>>> + int ret;
>>> +
>>> + tegra_nand_hw_ecc(ctrl, chip, true);
>>> + ret = tegra_nand_read_page(mtd, chip, buf, oob_required, page);
>>> + tegra_nand_hw_ecc(ctrl, chip, false);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + /* If no correctable or un-correctable errors occured we can return 0 */
>>> + if (!ctrl->last_read_error)
>>> + return 0;
>>> +
>>> + /*
>>> + * Correctable or un-correctable errors did occure. NAND dec status
>>> + * contains information for all ECC selections
>>> + */
>>> + ctrl->last_read_error = false;
>>> + value = readl(ctrl->regs + DEC_STAT_BUF);
>>> +
>>> + if (value & DEC_STAT_BUF_FAIL_SEC_FLAG_MASK) {
>>> + /*
>>> + * The ECC isn't smart enough to figure out if a page is
>>> + * completely erased and flags an error in this case. So we
>>> + * check the read data here to figure out if it's a legitimate
>>> + * error or a false positive.
>>> + */
>>> + int i, ret;
>>> + int flips_threshold = chip->ecc.strength / 2;
>>> + int max_bitflips = 0;
>>> +
>>> + for (i = 0; i < chip->ecc.steps; i++) {
>>> + u8 *data = buf + (chip->ecc.size * i);
>>> +
>>> + ret = nand_check_erased_ecc_chunk(data, chip->ecc.size,
>>> + NULL, 0,
>>> + NULL, 0,
>>> + flips_threshold);
>>> + if (ret < 0)
>>> + mtd->ecc_stats.failed++;
>>> + else
>>> + max_bitflips = max(ret, max_bitflips);
>>> + }
>>> +
>>> + return max_bitflips;
>>> + } else {
>>> + int max_corr_cnt, corr_sec_flag;
>>> +
>>> + corr_sec_flag = (value & DEC_STAT_BUF_CORR_SEC_FLAG_MASK) >>
>>> + DEC_STAT_BUF_CORR_SEC_FLAG_SHIFT;
>>> + max_corr_cnt = (value & DEC_STAT_BUF_MAX_CORR_CNT_MASK) >>
>>> + DEC_STAT_BUF_MAX_CORR_CNT_SHIFT;
>>> +
>>> + /*
>>> + * The value returned in the register is the maximum of
>>> + * bitflips encountered in any of the ECC regions. As there is
>>> + * no way to get the number of bitflips in a specific regions
>>> + * we are not able to deliver correct stats but instead
>>> + * overestimate the number of corrected bitflips by assuming
>>> + * that all regions where errors have been corrected
>>> + * encountered the maximum number of bitflips.
>>> + */
>>> + mtd->ecc_stats.corrected += max_corr_cnt * hweight8(corr_sec_flag);
>>> +
>>> + return max_corr_cnt;
>>> + }
>>> +
>>> +}
>>> +
>>> +static int tegra_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
>>> + const uint8_t *buf, int oob_required, int page)
>>> +{
>>> + struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
>>> + dma_addr_t dma_addr;
>>> + u32 value, addrs;
>>> + int ret, dma_len;
>>> +
>>> + writel(NAND_CMD_SEQIN, ctrl->regs + CMD_1);
>>> + writel(NAND_CMD_PAGEPROG, ctrl->regs + CMD_2);
>>> +
>>> + addrs = tegra_nand_fill_address(ctrl, chip, page);
>>> +
>>> + dma_len = mtd->writesize + (oob_required ? mtd->oobsize : 0);
>>> + dma_addr = dma_map_single(ctrl->dev, (void *)buf, dma_len, DMA_TO_DEVICE);
>>> + ret = dma_mapping_error(ctrl->dev, dma_addr);
>>> + if (ret) {
>>> + dev_err(ctrl->dev, "dma mapping error\n");
>>> + return -EINVAL;
>>> + }
>>> +
>>> + writel(mtd->writesize - 1, ctrl->regs + DMA_CFG_A);
>>> + writel(dma_addr, ctrl->regs + DATA_PTR);
>>> +
>>> + if (oob_required) {
>>> + struct mtd_oob_region oobregion;
>>> + dma_addr_t dma_addr_oob = dma_addr + mtd->writesize;
>>> +
>>> + mtd_ooblayout_free(mtd, 0, &oobregion);
>>> +
>>> + writel(oobregion.length - 1, ctrl->regs + DMA_CFG_B);
>>> + writel(dma_addr_oob + oobregion.offset, ctrl->regs + TAG_PTR);
>>> + } else {
>>> + writel(0, ctrl->regs + DMA_CFG_B);
>>> + writel(0, ctrl->regs + TAG_PTR);
>>> + }
>>> +
>>> + value = DMA_CTRL_GO | DMA_CTRL_OUT | DMA_CTRL_PERF_EN |
>>> + DMA_CTRL_IE_DONE | DMA_CTRL_IS_DONE |
>>> + DMA_CTRL_BURST_16 | DMA_CTRL_EN_A;
>>> + if (oob_required)
>>> + value |= DMA_CTRL_EN_B;
>>> + writel(value, ctrl->regs + DMA_CTRL);
>>> +
>>> + value = CMD_CLE | CMD_ALE | CMD_ALE_SIZE(addrs) | CMD_SEC_CMD |
>>> + CMD_AFT_DAT | CMD_RBSY_CHK | CMD_GO | CMD_TX | CMD_A_VALID |
>>> + CMD_TRANS_SIZE(9) | CMD_CE(ctrl->cur_chip);
>>> + if (oob_required)
>>> + value |= CMD_B_VALID;
>>> + writel(value, ctrl->regs + CMD);
>>> +
>>> + wait_for_completion(&ctrl->command_complete);
>>> + wait_for_completion(&ctrl->dma_complete);
>>> +
>>> +
>>> + dma_unmap_single(ctrl->dev, dma_addr, dma_len, DMA_TO_DEVICE);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int tegra_nand_write_page_hwecc(struct mtd_info *mtd,
>>> + struct nand_chip *chip,
>>> + const uint8_t *buf, int oob_required,
>>> + int page)
>>> +{
>>> + struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
>>> + int ret;
>>> +
>>> + tegra_nand_hw_ecc(ctrl, chip, true);
>>> + ret = tegra_nand_write_page(mtd, chip, buf, oob_required, page);
>>> + tegra_nand_hw_ecc(ctrl, chip, false);
>>> +
>>> + return ret;
>>> +}
>>> +
>>> +static void tegra_nand_setup_timing(struct tegra_nand_controller *ctrl,
>>> + const struct nand_sdr_timings *timings)
>>> +{
>>> + /*
>>> + * The period (and all other timings in this function) is in ps,
>>> + * so need to take care here to avoid integer overflows.
>>> + */
>>> + unsigned int rate = clk_get_rate(ctrl->clk) / 1000000;
>>> + unsigned int period = DIV_ROUND_UP(1000000, rate);
>>> + u32 val, reg = 0;
>>> +
>>> + val = DIV_ROUND_UP(max3(timings->tAR_min, timings->tRR_min,
>>> + timings->tRC_min), period);
>>> + if (val > 2)
>>> + val -= 3;
>>> + reg |= TIMING_TCR_TAR_TRR(val);
>>> +
>>> + val = DIV_ROUND_UP(max(max(timings->tCS_min, timings->tCH_min),
>>> + max(timings->tALS_min, timings->tALH_min)),
>>> + period);
>>> + if (val > 1)
>>> + val -= 2;
>>> + reg |= TIMING_TCS(val);
>>> +
>>> + val = DIV_ROUND_UP(max(timings->tRP_min, timings->tREA_max) + 6000,
>>> + period);
>>> + reg |= TIMING_TRP(val) | TIMING_TRP_RESP(val);
>>> +
>>> + reg |= TIMING_TWB(DIV_ROUND_UP(timings->tWB_max, period));
>>> + reg |= TIMING_TWHR(DIV_ROUND_UP(timings->tWHR_min, period));
>>> + reg |= TIMING_TWH(DIV_ROUND_UP(timings->tWH_min, period));
>>> + reg |= TIMING_TWP(DIV_ROUND_UP(timings->tWP_min, period));
>>> + reg |= TIMING_TRH(DIV_ROUND_UP(timings->tRHW_min, period));
>>> +
>>> + writel(reg, ctrl->regs + TIMING_1);
>>> +
>>> + val = DIV_ROUND_UP(timings->tADL_min, period);
>>> + if (val > 2)
>>> + val -= 3;
>>> + reg = TIMING_TADL(val);
>>> +
>>> + writel(reg, ctrl->regs + TIMING_2);
>>> +}
>>> +
>>> +static int tegra_nand_setup_data_interface(struct mtd_info *mtd, int csline,
>>> + const struct nand_data_interface *conf)
>>> +{
>>> + struct nand_chip *chip = mtd_to_nand(mtd);
>>> + struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
>>> + const struct nand_sdr_timings *timings;
>>> +
>>> + timings = nand_get_sdr_timings(conf);
>>> + if (IS_ERR(timings))
>>> + return PTR_ERR(timings);
>>> +
>>> + if (csline == NAND_DATA_IFACE_CHECK_ONLY)
>>> + return 0;
>>> +
>>> + tegra_nand_setup_timing(ctrl, timings);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int tegra_nand_chips_init(struct device *dev,
>>> + struct tegra_nand_controller *ctrl)
>>> +{
>>> + struct device_node *np = dev->of_node;
>>> + struct device_node *np_nand;
>>> + int nchips = of_get_child_count(np);
>>> + struct tegra_nand_chip *nand;
>>> + struct mtd_info *mtd;
>>> + struct nand_chip *chip;
>>> + unsigned long config, bch_config = 0;
>>> + int bits_per_step;
>>> + int err;
>>> +
>>> + if (nchips != 1) {
>>> + dev_err(dev, "currently only one NAND chip supported\n");
>>> + return -EINVAL;
>>> + }
>>> +
>>> + np_nand = of_get_next_child(np, NULL);
>>> +
>>> + nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
>>> + if (!nand) {
>>> + dev_err(dev, "could not allocate chip structure\n");
>>> + return -ENOMEM;
>>> + }
>>> +
>>> + nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
>>> +
>>> + if (IS_ERR(nand->wp_gpio)) {
>>> + err = PTR_ERR(nand->wp_gpio);
>>> + dev_err(dev, "failed to request WP GPIO: %d\n", err);
>>> + return err;
>>> + }
>>> +
>>> + chip = &nand->chip;
>>> + chip->controller = &ctrl->controller;
>>> + ctrl->chip = chip;
>>> +
>>> + mtd = nand_to_mtd(chip);
>>> +
>>> + mtd->dev.parent = dev;
>>> + mtd->name = "tegra_nand";
>>> + mtd->owner = THIS_MODULE;
>>> +
>>> + nand_set_flash_node(chip, np_nand);
>>> +
>>> + chip->options = NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;
>>> + chip->exec_op = tegra_nand_exec_op;
>>> + chip->select_chip = tegra_nand_select_chip;
>>> + chip->setup_data_interface = tegra_nand_setup_data_interface;
>>> +
>>> + err = nand_scan_ident(mtd, 1, NULL);
>>> + if (err)
>>> + return err;
>>> +
>>> + if (chip->bbt_options & NAND_BBT_USE_FLASH)
>>> + chip->bbt_options |= NAND_BBT_NO_OOB;
>>> +
>>> + chip->ecc.mode = NAND_ECC_HW;
>>> + if (!chip->ecc.size)
>>> + chip->ecc.size = 512;
>>> + if (chip->ecc.size != 512)
>>> + return -EINVAL;
>>> +
>>> + chip->ecc.read_page = tegra_nand_read_page_hwecc;
>>> + chip->ecc.write_page = tegra_nand_write_page_hwecc;
>>> + /* Not functional for unknown reason...
>>> + chip->ecc.read_page_raw = tegra_nand_read_page;
>>> + chip->ecc.write_page_raw = tegra_nand_write_page;
>>> + */
>>> + config = readl(ctrl->regs + CFG);
>>> + config |= CFG_PIPE_EN | CFG_SKIP_SPARE | CFG_SKIP_SPARE_SIZE_4;
>>> +
>>> + if (chip->options & NAND_BUSWIDTH_16)
>>> + config |= CFG_BUS_WIDTH_16;
>>> +
>>> + switch (chip->ecc.algo) {
>>> + case NAND_ECC_RS:
>>> + bits_per_step = BITS_PER_STEP_RS * chip->ecc.strength;
>>> + mtd_set_ooblayout(mtd, &tegra_nand_oob_rs_ops);
>>> + switch (chip->ecc.strength) {
>>> + case 4:
>>> + config |= CFG_ECC_SEL | CFG_TVAL_4;
>>> + break;
>>> + case 6:
>>> + config |= CFG_ECC_SEL | CFG_TVAL_6;
>>> + break;
>>> + case 8:
>>> + config |= CFG_ECC_SEL | CFG_TVAL_8;
>>> + break;
>>> + default:
>>> + dev_err(dev, "ECC strength %d not supported\n",
>>> + chip->ecc.strength);
>>> + return -EINVAL;
>>> + }
>>> + break;
>>> + case NAND_ECC_BCH:
>>> + bits_per_step = BITS_PER_STEP_BCH * chip->ecc.strength;
>>> + mtd_set_ooblayout(mtd, &tegra_nand_oob_bch_ops);
>>> + switch (chip->ecc.strength) {
>>> + case 4:
>>> + bch_config = BCH_TVAL_4;
>>> + break;
>>> + case 8:
>>> + bch_config = BCH_TVAL_8;
>>> + break;
>>> + case 14:
>>> + bch_config = BCH_TVAL_14;
>>> + break;
>>> + case 16:
>>> + bch_config = BCH_TVAL_16;
>>> + break;
>>> + default:
>>> + dev_err(dev, "ECC strength %d not supported\n",
>>> + chip->ecc.strength);
>>> + return -EINVAL;
>>> + }
>>> + break;
>>> + default:
>>> + dev_err(dev, "ECC algorithm not supported\n");
>>> + return -EINVAL;
>>> + }
>>> +
>>> + chip->ecc.bytes = DIV_ROUND_UP(bits_per_step, 8);
>>> +
>>> + switch (mtd->writesize) {
>>> + case 256:
>>> + config |= CFG_PS_256;
>>> + break;
>>> + case 512:
>>> + config |= CFG_PS_512;
>>> + break;
>>> + case 1024:
>>> + config |= CFG_PS_1024;
>>> + break;
>>> + case 2048:
>>> + config |= CFG_PS_2048;
>>> + break;
>>> + case 4096:
>>> + config |= CFG_PS_4096;
>>> + break;
>>> + default:
>>> + dev_err(dev, "unhandled writesize %d\n", mtd->writesize);
>>> + return -ENODEV;
>>> + }
>>> +
>>> + writel(config, ctrl->regs + CFG);
>>> + writel(bch_config, ctrl->regs + BCH_CONFIG);
>>> +
>>> + err = nand_scan_tail(mtd);
>>> + if (err)
>>> + return err;
>>> +
>>> + config |= CFG_TAG_BYTE_SIZE(mtd_ooblayout_count_freebytes(mtd) - 1);
>>> + writel(config, ctrl->regs + CFG);
>>> +
>>> + err = mtd_device_register(mtd, NULL, 0);
>>> + if (err)
>>> + return err;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int tegra_nand_probe(struct platform_device *pdev)
>>> +{
>>> + struct reset_control *rst;
>>> + struct tegra_nand_controller *ctrl;
>>> + struct resource *res;
>>> + unsigned long value;
>>> + int irq, err = 0;
>>> +
>>> + ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
>>> + if (!ctrl)
>>> + return -ENOMEM;
>>> +
>>> + ctrl->dev = &pdev->dev;
>>> + nand_hw_control_init(&ctrl->controller);
>>> +
>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> + ctrl->regs = devm_ioremap_resource(&pdev->dev, res);
>>> + if (IS_ERR(ctrl->regs))
>>> + return PTR_ERR(ctrl->regs);
>>> +
>>> + rst = devm_reset_control_get(&pdev->dev, "nand");
>>> + if (IS_ERR(rst))
>>> + return PTR_ERR(rst);
>>> +
>>> + ctrl->clk = devm_clk_get(&pdev->dev, "nand");
>>> + if (IS_ERR(ctrl->clk))
>>> + return PTR_ERR(ctrl->clk);
>>> +
>>> + err = clk_prepare_enable(ctrl->clk);
>>> + if (err)
>>> + return err;
>>> +
>>> + reset_control_reset(rst);
>>
>> Technically reset_control_reset() could fail, so this should be:
>>
>> err = reset_control_reset(rst);
>> if (err)
>> goto err_disable_clk;
>>
>
> Ok.
>
> --
> Stefan
>
>>> +
>>> + value = HWSTATUS_RDSTATUS_MASK(1) | HWSTATUS_RDSTATUS_VALUE(0) |
>>> + HWSTATUS_RBSY_MASK(NAND_STATUS_READY) |
>>> + HWSTATUS_RBSY_VALUE(NAND_STATUS_READY);
>>> + writel(NAND_CMD_STATUS, ctrl->regs + HWSTATUS_CMD);
>>> + writel(value, ctrl->regs + HWSTATUS_MASK);
>>> +
>>> + init_completion(&ctrl->command_complete);
>>> + init_completion(&ctrl->dma_complete);
>>> +
>>> + /* clear interrupts */
>>> + value = readl(ctrl->regs + ISR);
>>> + writel(value, ctrl->regs + ISR);
>>> +
>>> + irq = platform_get_irq(pdev, 0);
>>> + err = devm_request_irq(&pdev->dev, irq, tegra_nand_irq, 0,
>>> + dev_name(&pdev->dev), ctrl);
>>> + if (err)
>>> + goto err_disable_clk;
>>> +
>>> + writel(DMA_CTRL_IS_DONE, ctrl->regs + DMA_CTRL);
>>> +
>>> + /* enable interrupts */
>>> + value = IER_UND | IER_OVR | IER_CMD_DONE | IER_ECC_ERR | IER_GIE;
>>> + writel(value, ctrl->regs + IER);
>>> +
>>> + /* reset config */
>>> + writel(0, ctrl->regs + CFG);
>>> +
>>> + err = tegra_nand_chips_init(ctrl->dev, ctrl);
>>> + if (err)
>>> + goto err_disable_clk;
>>> +
>>> + platform_set_drvdata(pdev, ctrl);
>>> +
>>> + return 0;
>>> +
>>> +err_disable_clk:
>>> + clk_disable_unprepare(ctrl->clk);
>>> + return err;
>>> +}
>>> +
>>> +static int tegra_nand_remove(struct platform_device *pdev)
>>> +{
>>> + struct tegra_nand_controller *ctrl = platform_get_drvdata(pdev);
>>> +
>>> + nand_release(nand_to_mtd(ctrl->chip));
>>> +
>>> + clk_disable_unprepare(ctrl->clk);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static const struct of_device_id tegra_nand_of_match[] = {
>>> + { .compatible = "nvidia,tegra20-nand" },
>>> + { /* sentinel */ }
>>> +};
>>> +
>>> +static struct platform_driver tegra_nand_driver = {
>>> + .driver = {
>>> + .name = "tegra-nand",
>>> + .of_match_table = tegra_nand_of_match,
>>> + },
>>> + .probe = tegra_nand_probe,
>>> + .remove = tegra_nand_remove,
>>> +};
>>> +module_platform_driver(tegra_nand_driver);
>>> +
>>> +MODULE_DESCRIPTION("NVIDIA Tegra NAND driver");
>>> +MODULE_AUTHOR("Thierry Reding <thierry.reding@nvidia.com>");
>>> +MODULE_AUTHOR("Lucas Stach <dev@lynxeye.de>");
>>> +MODULE_AUTHOR("Stefan Agner <stefan@agner.ch>");
>>> +MODULE_LICENSE("GPL v2");
>>> +MODULE_DEVICE_TABLE(of, tegra_nand_of_match);
>>>
^ permalink raw reply
* Re: [PATCH 10/12] ARM: dts: exynos5250: add DSI node
From: Krzysztof Kozlowski @ 2018-05-28 16:36 UTC (permalink / raw)
To: Maciej Purski
Cc: Mark Rutland, devicetree, linux-samsung-soc@vger.kernel.org,
Bartlomiej Zolnierkiewicz, David Airlie, Seung-Woo Kim,
linux-kernel, dri-devel, Kyungmin Park, Rob Herring,
Thierry Reding, Kukjin Kim, Marek Szyprowski, linux-arm-kernel,
Laurent Pinchart
In-Reply-To: <1527501272-16365-1-git-send-email-m.purski@samsung.com>
On Mon, May 28, 2018 at 11:54 AM, Maciej Purski <m.purski@samsung.com> wrote:
> The patch adds common part of DSI node for Exynos5250 platforms.
>
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> Signed-off-by: Maciej Purski <m.purski@samsung.com>
> ---
> arch/arm/boot/dts/exynos5250.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
This should be squashed with previous patch because it is logically
the same feature. The purpose of PHY is this DSI node so splitting it
is slightly too much.
Best regards,
Krzysztof
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCH 08/12] drm/bridge: tc358764: Add DSI to LVDS bridge driver
From: Randy Dunlap @ 2018-05-28 16:24 UTC (permalink / raw)
To: Maciej Purski, linux-kernel, linux-arm-kernel, linux-samsung-soc,
devicetree, dri-devel
Cc: David Airlie, Rob Herring, Mark Rutland, Thierry Reding,
Kukjin Kim, Krzysztof Kozlowski, Archit Taneja, Andrzej Hajda,
Laurent Pinchart, Inki Dae, Joonyoung Shim, Seung-Woo Kim,
Kyungmin Park, Marek Szyprowski, Bartlomiej Zolnierkiewicz
In-Reply-To: <1527500833-16005-9-git-send-email-m.purski@samsung.com>
On 05/28/2018 02:47 AM, Maciej Purski wrote:
> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> index fa2c799..58e19af 100644
> --- a/drivers/gpu/drm/bridge/Kconfig
> +++ b/drivers/gpu/drm/bridge/Kconfig
> @@ -110,6 +110,13 @@ config DRM_THINE_THC63LVD1024
> ---help---
> Thine THC63LVD1024 LVDS/parallel converter driver.
>
> +config DRM_TOSHIBA_TC358764
> + tristate "TC358764 DSI/LVDS bridge"
> + depends on DRM && DRM_PANEL
> + depends on OF
> + select DRM_MIPI_DSI
> + select VIDEOMODE_HELPERS
> +
Kconfig symbols with "prompt strings" should also have help text.
I expected checkpatch to catch that, but I tested it and there was no warning
from checkpatch about help text. OTOH, there was a warning that there are
2 lines in this patch that end with whitespace, so that should be fixed.
Did you use checkpatch (scripts/checkpatch.pl)?
> config DRM_TOSHIBA_TC358767
> tristate "Toshiba TC358767 eDP bridge"
> depends on OF
thanks,
--
~Randy
^ permalink raw reply
* Re: [PATCH 09/12] ARM: dts: exynos5250: add mipi-phy node
From: Krzysztof Kozlowski @ 2018-05-28 16:24 UTC (permalink / raw)
To: Maciej Purski
Cc: Mark Rutland, devicetree, linux-samsung-soc@vger.kernel.org,
Bartlomiej Zolnierkiewicz, David Airlie, Seung-Woo Kim,
linux-kernel, dri-devel, Kyungmin Park, Rob Herring,
Thierry Reding, Kukjin Kim, Marek Szyprowski, linux-arm-kernel,
Laurent Pinchart
In-Reply-To: <1527500833-16005-10-git-send-email-m.purski@samsung.com>
On Mon, May 28, 2018 at 11:47 AM, Maciej Purski <m.purski@samsung.com> wrote:
> The patch adds phy node, required by MIPI devices.
>
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> Signed-off-by: Maciej Purski <m.purski@samsung.com>
This have pretty small changes since original Andrzej's patch so
probably Andrzej's authorship should be preserved.
> ---
> arch/arm/boot/dts/exynos5250.dtsi | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index 2daf505..a63b655 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -733,6 +733,12 @@
> #phy-cells = <0>;
> };
>
> + mipi_phy: video-phy@10040710 {
> + compatible = "samsung,s5pv210-mipi-video-phy";
No DTC warnings (make dtbs W=1)? reg is missing so DTC should complain.
Best regards,
Krzysztof
> + #phy-cells = <1>;
> + syscon = <&pmu_system_controller>;
> + };
> +
> adc: adc@12d10000 {
> compatible = "samsung,exynos-adc-v1";
> reg = <0x12D10000 0x100>;
> --
> 2.7.4
>
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* RE: [patch v22 1/4] drivers: jtag: Add JTAG core driver
From: Oleksandr Shamray @ 2018-05-28 15:59 UTC (permalink / raw)
To: Greg KH
Cc: arnd@arndb.de, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
openbmc@lists.ozlabs.org, joel@jms.id.au, jiri@resnulli.us,
tklauser@distanz.ch, linux-serial@vger.kernel.org,
Vadim Pasternak, system-sw-low-level, robh+dt@kernel.org,
openocd-devel-owner@lists.sourceforge.net,
linux-api@vger.kernel.org, davem
In-Reply-To: <20180528123527.GA17613@kroah.com>
Hi Greg.
Thanks for your review.
Please see my comments inline.
Best Regards,
Oleksandr Shamray
> -----Original Message-----
> From: Greg KH [mailto:gregkh@linuxfoundation.org]
> Sent: 28 мая 2018 г. 15:35
> To: Oleksandr Shamray <oleksandrs@mellanox.com>
> Cc: arnd@arndb.de; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; devicetree@vger.kernel.org;
> openbmc@lists.ozlabs.org; joel@jms.id.au; jiri@resnulli.us;
> tklauser@distanz.ch; linux-serial@vger.kernel.org; Vadim Pasternak
> <vadimp@mellanox.com>; system-sw-low-level <system-sw-low-
> level@mellanox.com>; robh+dt@kernel.org; openocd-devel-
> owner@lists.sourceforge.net; linux-api@vger.kernel.org;
> davem@davemloft.net; mchehab@kernel.org
> Subject: Re: [patch v22 1/4] drivers: jtag: Add JTAG core driver
>
> On Mon, May 28, 2018 at 01:34:09PM +0300, Oleksandr Shamray wrote:
> > Initial patch for JTAG driver
> > JTAG class driver provide infrastructure to support hardware/software
> > JTAG platform drivers. It provide user layer API interface for
> > flashing and debugging external devices which equipped with JTAG
> > interface using standard transactions.
> >
> > Driver exposes set of IOCTL to user space for:
> > - XFER:
> > - SIR (Scan Instruction Register, IEEE 1149.1 Data Register scan);
> > - SDR (Scan Data Register, IEEE 1149.1 Instruction Register scan);
> > - RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
> > number of clocks).
> > - SIOCFREQ/GIOCFREQ for setting and reading JTAG frequency.
> >
> > Driver core provides set of internal APIs for allocation and
> > registration:
> > - jtag_register;
> > - jtag_unregister;
> > - jtag_alloc;
> > - jtag_free;
> >
> > Platform driver on registration with jtag-core creates the next entry
> > in dev folder:
> > /dev/jtagX
> >
> > Signed-off-by: Oleksandr Shamray <oleksandrs@mellanox.com>
> > Signed-off-by: Jiri Pirko <jiri@mellanox.com>
> > Acked-by: Philippe Ombredanne <pombredanne@nexb.com>
> > ---
> > v21->v22
>
> 22 versions, way to stick with this...
>
> Anyway, time to review it again. I feel it's really close, but I don't want to
> apply it yet as the api feels odd in places. If others have asked you to make
> these changes to look like this, I'm sorry, then please push back on me:
>
> > +/*
> > + * JTAG core driver supports up to 256 devices
> > + * JTAG device name will be in range jtag0-jtag255
> > + * Set maximum len of jtag id to 3
> > + */
> > +
> > +#define MAX_JTAG_DEVS 255
>
> Why have a max at all? You should be able to just dynamically allocate them.
> Anyway, if you do want a max, you need to be able to properly keep the max
> number, and right now you have a race when registering (you check the
> number, and then much later do you increment it, a pointless use of an
> atomic value if I've ever seen one...)
>
You are right. It's not good idea to have restriction of max dev number.
I will remove all regarding It.
> > +#define MAX_JTAG_NAME_LEN (sizeof("jtag") + 3)
> > +
> > +struct jtag {
> > + struct miscdevice miscdev;
>
> If you are a miscdev, why even have a max number? Just let the max
> number of miscdev devices rule things.
>
> > + const struct jtag_ops *ops;
> > + int id;
> > + bool opened;
>
> You shouldn't care about this, but ok...
Jtag HW not support to using with multiple requests from different users. So we prohibit this.
>
> > + struct mutex open_lock;
> > + unsigned long priv[0];
> > +};
> > +
> > +static DEFINE_IDA(jtag_ida);
> > +
> > +static atomic_t jtag_refcount = ATOMIC_INIT(0);
>
> Either use it as an atomic properly (test_and_set), or just leave it as an int, or
> better yet, don't use it at all.
It will be removed.
>
> > +void *jtag_priv(struct jtag *jtag)
> > +{
> > + return jtag->priv;
> > +}
> > +EXPORT_SYMBOL_GPL(jtag_priv);
>
> Api naming issue here. Traditionally this is a "get/set_drvdata" type function,
> as in dev_get_drvdata(), or dev_set_drvdata. But, you are right in that the
> network stack has a netdev_priv() call, where you probably copied this idea
> from.
>
> I don't know, I guess it's ok as-is, as it's the way networking does it, it's your
> call though.
>
Yes, I did as in networking.
> > +static long jtag_ioctl(struct file *file, unsigned int cmd, unsigned
> > +long arg) {
> > + struct jtag *jtag = file->private_data;
> > + struct jtag_run_test_idle idle;
> > + struct jtag_xfer xfer;
> > + u8 *xfer_data;
> > + u32 data_size;
> > + u32 value;
> > + int err;
> > +
> > + if (!arg)
> > + return -EINVAL;
> > +
> > + switch (cmd) {
> > + case JTAG_GIOCFREQ:
> > + if (!jtag->ops->freq_get)
> > + return -EOPNOTSUPP;
> > +
> > + err = jtag->ops->freq_get(jtag, &value);
> > + if (err)
> > + break;
> > +
> > + if (put_user(value, (__u32 __user *)arg))
> > + err = -EFAULT;
> > + break;
> > +
> > + case JTAG_SIOCFREQ:
> > + if (!jtag->ops->freq_set)
> > + return -EOPNOTSUPP;
> > +
> > + if (get_user(value, (__u32 __user *)arg))
> > + return -EFAULT;
> > + if (value == 0)
> > + return -EINVAL;
> > +
> > + err = jtag->ops->freq_set(jtag, value);
> > + break;
> > +
> > + case JTAG_IOCRUNTEST:
> > + if (copy_from_user(&idle, (const void __user *)arg,
> > + sizeof(struct jtag_run_test_idle)))
> > + return -EFAULT;
> > +
> > + if (idle.endstate > JTAG_STATE_PAUSEDR)
> > + return -EINVAL;
>
> No validation that idle contains sane values? Don't make every jtag driver
> have to do this type of validation please.
>
I have partially validation of idle structure (if (idle.endstate > JTAG_STATE_PAUSEDR)).
But I will add more validation.
>
> > +
> > + err = jtag->ops->idle(jtag, &idle);
> > + break;
> > +
> > + case JTAG_IOCXFER:
> > + if (copy_from_user(&xfer, (const void __user *)arg,
> > + sizeof(struct jtag_xfer)))
> > + return -EFAULT;
> > +
> > + if (xfer.length >= JTAG_MAX_XFER_DATA_LEN)
> > + return -EINVAL;
> > +
> > + if (xfer.type > JTAG_SDR_XFER)
> > + return -EINVAL;
> > +
> > + if (xfer.direction > JTAG_WRITE_XFER)
> > + return -EINVAL;
> > +
> > + if (xfer.endstate > JTAG_STATE_PAUSEDR)
> > + return -EINVAL;
> > +
>
> See, you do good error checking here, why not for the previous ioctl?
>
>
> > + data_size = DIV_ROUND_UP(xfer.length, BITS_PER_BYTE);
> > + xfer_data = memdup_user(u64_to_user_ptr(xfer.tdio),
> data_size);
> > +
>
> No blank line.
>
Will remove
> > + if (IS_ERR(xfer_data))
> > + return -EFAULT;
> > +
> > + err = jtag->ops->xfer(jtag, &xfer, xfer_data);
> > + if (err) {
> > + kfree(xfer_data);
> > + return -EFAULT;
>
> Why not return the error given to you? -EFAULT is only if there is a memory
> error in a copy_to/from_user() call.
>
Will change return code to err
> > + }
> > +
> > + err = copy_to_user(u64_to_user_ptr(xfer.tdio),
> > + (void *)xfer_data, data_size);
> > + kfree(xfer_data);
> > + if (err)
> > + return -EFAULT;
>
> Like here, that's correct.
>
> > +
> > + if (copy_to_user((void __user *)arg, (void *)&xfer,
> > + sizeof(struct jtag_xfer)))
> > + return -EFAULT;
> > + break;
> > +
> > + case JTAG_GIOCSTATUS:
> > + err = jtag->ops->status_get(jtag, &value);
> > + if (err)
> > + break;
> > +
> > + err = put_user(value, (__u32 __user *)arg);
> > + break;
> > + case JTAG_SIOCMODE:
> > + if (!jtag->ops->mode_set)
> > + return -EOPNOTSUPP;
> > +
> > + if (get_user(value, (__u32 __user *)arg))
> > + return -EFAULT;
> > + if (value == 0)
> > + return -EINVAL;
> > +
> > + err = jtag->ops->mode_set(jtag, value);
> > + break;
> > +
> > + default:
> > + return -EINVAL;
> > + }
> > + return err;
> > +}
> > +
> > +static int jtag_open(struct inode *inode, struct file *file) {
> > + struct jtag *jtag = container_of(file->private_data, struct jtag,
> > +miscdev);
> > +
> > + if (mutex_lock_interruptible(&jtag->open_lock))
> > + return -ERESTARTSYS;
>
> Why restart? Just grab the lock, you don't want to have to do restartable
> logic in userspace, right?
Will change like:
ret = mutex_lock_interruptible(&jtag->open_lock);
if (ret)
return ret;
>
> > +
> > + if (jtag->opened) {
> > + mutex_unlock(&jtag->open_lock);
> > + return -EBUSY;
>
> Why do you care about only 1 userspace open call? What does that buy you?
> Userspace can always pass around that file descriptor and use it in multiple
> places, so you are not really "protecting" yourself from anything.
>
Accessing to JTAG HW from multiple processes will make confusion in the work of the JTAG protocol.
And I want to prohibit this.
> And better yet, if you get rid of this, your open/release functions get very
> tiny and simple.
>
> > + }
> > + jtag->opened = true;
> > + mutex_unlock(&jtag->open_lock);
> > +
> > + nonseekable_open(inode, file);
>
> No error checking of the return value? Not good :(
Will add error handling
>
> > + file->private_data = jtag;
> > + return 0;
> > +}
> > +
> > +static int jtag_release(struct inode *inode, struct file *file) {
> > + struct jtag *jtag = file->private_data;
> > +
> > + mutex_lock(&jtag->open_lock);
> > + jtag->opened = false;
> > + mutex_unlock(&jtag->open_lock);
> > + return 0;
> > +}
> > +
> > +static const struct file_operations jtag_fops = {
> > + .owner = THIS_MODULE,
> > + .open = jtag_open,
> > + .release = jtag_release,
> > + .llseek = noop_llseek,
> > + .unlocked_ioctl = jtag_ioctl,
> > +};
> > +
> > +struct jtag *jtag_alloc(struct device *host, size_t priv_size,
> > + const struct jtag_ops *ops)
> > +{
> > + struct jtag *jtag;
> > +
> > + if (!host)
> > + return NULL;
> > +
> > + if (!ops)
> > + return NULL;
> > +
> > + if (!ops->idle || !ops->status_get || !ops->xfer)
> > + return NULL;
> > +
> > + jtag = kzalloc(sizeof(*jtag) + priv_size, GFP_KERNEL);
> > + if (!jtag)
> > + return NULL;
> > +
> > + jtag->ops = ops;
> > + jtag->miscdev.parent = host;
> > +
> > + return jtag;
> > +}
> > +EXPORT_SYMBOL_GPL(jtag_alloc);
> > +
> > +void jtag_free(struct jtag *jtag)
> > +{
> > + kfree(jtag);
> > +}
> > +EXPORT_SYMBOL_GPL(jtag_free);
> > +
> > +static int jtag_register(struct jtag *jtag) {
> > + struct device *dev = jtag->miscdev.parent;
> > + char *name;
> > + int err;
> > + int id;
> > +
> > + if (!dev)
> > + return -ENODEV;
> > +
> > + if (atomic_read(&jtag_refcount) >= MAX_JTAG_DEVS)
> > + return -ENOSPC;
>
> Here, you are reading the value, and then setting it a long ways away.
> What happens if two people call this at the same time. Not good.
> Either do it correctly, or better yet, don't do it at all.
>
Removed.
> > +
> > + id = ida_simple_get(&jtag_ida, 0, 0, GFP_KERNEL);
> > + if (id < 0)
> > + return id;
> > +
> > + jtag->id = id;
> > + jtag->opened = false;
> > +
> > + name = kzalloc(MAX_JTAG_NAME_LEN, GFP_KERNEL);
> > + if (!name) {
> > + err = -ENOMEM;
> > + goto err_jtag_alloc;
> > + }
> > +
> > + err = snprintf(name, MAX_JTAG_NAME_LEN, "jtag%d", id);
> > + if (err < 0)
> > + goto err_jtag_name;
> > +
> > + mutex_init(&jtag->open_lock);
> > + jtag->miscdev.fops = &jtag_fops;
> > + jtag->miscdev.minor = MISC_DYNAMIC_MINOR;
> > + jtag->miscdev.name = name;
> > +
> > + err = misc_register(&jtag->miscdev);
> > + if (err) {
> > + dev_err(jtag->miscdev.parent, "Unable to register
> device\n");
> > + goto err_jtag_name;
> > + }
> > + pr_info("%s %d\n", __func__, __LINE__);
> > + atomic_inc(&jtag_refcount);
> > + return 0;
> > +
> > +err_jtag_name:
> > + kfree(name);
> > +err_jtag_alloc:
> > + ida_simple_remove(&jtag_ida, id);
> > + return err;
> > +}
> > +
> > +static void jtag_unregister(struct jtag *jtag) {
> > + misc_deregister(&jtag->miscdev);
> > + kfree(jtag->miscdev.name);
> > + ida_simple_remove(&jtag_ida, jtag->id);
> > + atomic_dec(&jtag_refcount);
> > +}
> > +
> > +static void devm_jtag_unregister(struct device *dev, void *res) {
> > + jtag_unregister(*(struct jtag **)res); }
> > +
> > +int devm_jtag_register(struct device *dev, struct jtag *jtag) {
> > + struct jtag **ptr;
> > + int ret;
> > +
> > + ptr = devres_alloc(devm_jtag_unregister, sizeof(*ptr),
> GFP_KERNEL);
> > + if (!ptr)
> > + return -ENOMEM;
> > +
> > + ret = jtag_register(jtag);
> > + if (!ret) {
> > + *ptr = jtag;
> > + devres_add(dev, ptr);
> > + } else {
> > + devres_free(ptr);
> > + }
> > + return ret;
> > +}
> > +EXPORT_SYMBOL_GPL(devm_jtag_register);
> > +
> > +static void __exit jtag_exit(void)
> > +{
> > + ida_destroy(&jtag_ida);
> > +}
> > +
> > +module_exit(jtag_exit);
> > +
> > +MODULE_AUTHOR("Oleksandr Shamray <oleksandrs@mellanox.com>");
> > +MODULE_DESCRIPTION("Generic jtag support"); MODULE_LICENSE("GPL
> v2");
> > diff --git a/include/linux/jtag.h b/include/linux/jtag.h new file mode
> > 100644 index 0000000..56d784d
> > --- /dev/null
> > +++ b/include/linux/jtag.h
> > @@ -0,0 +1,43 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +// include/linux/jtag.h - JTAG class driver // // Copyright (c) 2018
> > +Mellanox Technologies. All rights reserved.
> > +// Copyright (c) 2018 Oleksandr Shamray <oleksandrs@mellanox.com>
> > +
> > +#ifndef __JTAG_H
> > +#define __JTAG_H
> > +
> > +#include <uapi/linux/jtag.h>
> > +
> > +#define jtag_u64_to_ptr(arg) ((void *)(uintptr_t)arg)
>
> Why do you need such a horrid cast? What is this for? And why use uintptr_t
> at all? It's not a "normal" kernel type.
>
Not needed - will be removed.
> > +
> > +#define JTAG_MAX_XFER_DATA_LEN 65535
> > +
> > +struct jtag;
> > +/**
> > + * struct jtag_ops - callbacks for JTAG control functions:
> > + *
> > + * @freq_get: get frequency function. Filled by dev driver
> > + * @freq_set: set frequency function. Filled by dev driver
> > + * @status_get: set status function. Mandatory func. Filled by dev
> > +driver
> > + * @idle: set JTAG to idle state function. Mandatory func. Filled by
> > +dev driver
> > + * @xfer: send JTAG xfer function. Mandatory func. Filled by dev
> > +driver
> > + * @mode_set: set specific work mode for JTAG. Filled by dev driver
> > +*/ struct jtag_ops {
> > + int (*freq_get)(struct jtag *jtag, u32 *freq);
> > + int (*freq_set)(struct jtag *jtag, u32 freq);
> > + int (*status_get)(struct jtag *jtag, u32 *state);
> > + int (*idle)(struct jtag *jtag, struct jtag_run_test_idle *idle);
> > + int (*xfer)(struct jtag *jtag, struct jtag_xfer *xfer, u8 *xfer_data);
> > + int (*mode_set)(struct jtag *jtag, u32 mode_mask); };
> > +
> > +void *jtag_priv(struct jtag *jtag);
> > +int devm_jtag_register(struct device *dev, struct jtag *jtag); void
> > +devm_jtag_unregister(struct device *dev, void *res); struct jtag
> > +*jtag_alloc(struct device *host, size_t priv_size,
> > + const struct jtag_ops *ops);
> > +void jtag_free(struct jtag *jtag);
> > +
> > +#endif /* __JTAG_H */
> > diff --git a/include/uapi/linux/jtag.h b/include/uapi/linux/jtag.h new
> > file mode 100644 index 0000000..8bbf1a7
> > --- /dev/null
> > +++ b/include/uapi/linux/jtag.h
> > @@ -0,0 +1,102 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +// include/uapi/linux/jtag.h - JTAG class driver uapi // // Copyright
> > +(c) 2018 Mellanox Technologies. All rights reserved.
> > +// Copyright (c) 2018 Oleksandr Shamray <oleksandrs@mellanox.com>
> > +
> > +#ifndef __UAPI_LINUX_JTAG_H
> > +#define __UAPI_LINUX_JTAG_H
> > +
> > +/*
> > + * JTAG_XFER_HW_MODE: JTAG hardware mode. Used to set HW drived
> or
> > +bitbang
> > + * mode. This is bitmask param of ioctl JTAG_SIOCMODE command */
> > +#define JTAG_XFER_HW_MODE 1
> > +
> > +/**
> > + * enum jtag_endstate:
> > + *
> > + * @JTAG_STATE_IDLE: JTAG state machine IDLE state
> > + * @JTAG_STATE_PAUSEIR: JTAG state machine PAUSE_IR state
> > + * @JTAG_STATE_PAUSEDR: JTAG state machine PAUSE_DR state */
> enum
> > +jtag_endstate {
> > + JTAG_STATE_IDLE,
> > + JTAG_STATE_PAUSEIR,
> > + JTAG_STATE_PAUSEDR,
> > +};
> > +
> > +/**
> > + * enum jtag_xfer_type:
> > + *
> > + * @JTAG_SIR_XFER: SIR transfer
> > + * @JTAG_SDR_XFER: SDR transfer
> > + */
> > +enum jtag_xfer_type {
> > + JTAG_SIR_XFER,
> > + JTAG_SDR_XFER,
> > +};
> > +
> > +/**
> > + * enum jtag_xfer_direction:
> > + *
> > + * @JTAG_READ_XFER: read transfer
> > + * @JTAG_WRITE_XFER: write transfer
> > + */
> > +enum jtag_xfer_direction {
> > + JTAG_READ_XFER,
> > + JTAG_WRITE_XFER,
> > +};
> > +
> > +/**
> > + * struct jtag_run_test_idle - forces JTAG state machine to
> > + * RUN_TEST/IDLE state
> > + *
> > + * @reset: 0 - run IDLE/PAUSE from current state
> > + * 1 - go through TEST_LOGIC/RESET state before IDLE/PAUSE
> > + * @end: completion flag
> > + * @tck: clock counter
> > + *
> > + * Structure provide interface to JTAG device for JTAG IDLE execution.
> > + */
> > +struct jtag_run_test_idle {
> > + __u8 reset;
> > + __u8 endstate;
> > + __u8 tck;
> > +};
> > +
> > +/**
> > + * struct jtag_xfer - jtag xfer:
> > + *
> > + * @type: transfer type
> > + * @direction: xfer direction
> > + * @length: xfer bits len
> > + * @tdio : xfer data array
> > + * @endir: xfer end state
> > + *
> > + * Structure provide interface to JTAG device for JTAG SDR/SIR xfer
> execution.
> > + */
> > +struct jtag_xfer {
> > + __u8 type;
> > + __u8 direction;
> > + __u8 endstate;
> > + __u8 padding;
> > + __u32 length;
> > + __u64 tdio;
> > +};
> > +
> > +/* ioctl interface */
> > +#define __JTAG_IOCTL_MAGIC 0xb2
> > +
> > +#define JTAG_IOCRUNTEST _IOW(__JTAG_IOCTL_MAGIC, 0,\
> > + struct jtag_run_test_idle)
>
> No need for 2 lines here, fits just fine on one.
Ok
>
> > +#define JTAG_SIOCFREQ _IOW(__JTAG_IOCTL_MAGIC, 1, unsigned
> int)
> > +#define JTAG_GIOCFREQ _IOR(__JTAG_IOCTL_MAGIC, 2, unsigned int)
> > +#define JTAG_IOCXFER _IOWR(__JTAG_IOCTL_MAGIC, 3, struct
> jtag_xfer)
> > +#define JTAG_GIOCSTATUS _IOWR(__JTAG_IOCTL_MAGIC, 4, enum
> jtag_endstate)
> > +#define JTAG_SIOCMODE _IOW(__JTAG_IOCTL_MAGIC, 5, unsigned
> int)
> > +
> > +#define JTAG_FIRST_MINOR 0
>
> Why is this in a uapi file?
Not needed - will be removed.
>
> > +#define JTAG_MAX_DEVICES 32
>
> This is never used, why is it in a uapi file?
>
Not needed - will be removed.
> So, almost there, with the above mentioned things, I think you can make the
> code even simpler, which is always better, right?
>
> thanks,
>
> greg k-h
Thanks.
BR,
Oleksandr Shamray
^ permalink raw reply
* Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate
From: Lucas Stach @ 2018-05-28 15:58 UTC (permalink / raw)
To: Stefan Agner, Peter De Schrijver
Cc: boris.brezillon, dwmw2, computersforpeace, marek.vasut, robh+dt,
mark.rutland, thierry.reding, mturquette, sboyd, miquel.raynal,
richard, marcel, krzk, digetx, benjamin.lindqvist, jonathanh,
pgaikwad, mirza.krak, linux-mtd, linux-tegra, devicetree,
linux-kernel, linux-clk
In-Reply-To: <5665b799f763daa82dced238fb494863@agner.ch>
Am Montag, den 28.05.2018, 17:53 +0200 schrieb Stefan Agner:
> On 28.05.2018 09:55, Peter De Schrijver wrote:
> > On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote:
> > > From: Lucas Stach <dev@lynxeye.de>
> > >
> > > Set up the NAND Flash controller clock to run at 150MHz
> > > instead of the rate set by the bootloader. This is a
> > > conservative rate which also yields good performance.
> > >
> > > Signed-off-by: Lucas Stach <dev@lynxeye.de>
> > > Signed-off-by: Stefan Agner <stefan@agner.ch>
> > > ---
> > > drivers/clk/tegra/clk-tegra20.c | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
> > > index 0ee56dd04cec..dff8c425cd28 100644
> > > --- a/drivers/clk/tegra/clk-tegra20.c
> > > +++ b/drivers/clk/tegra/clk-tegra20.c
> > > @@ -1049,6 +1049,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
> > > { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 },
> > > { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },
> > > { TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 300000000, 0 },
> > > + { TEGRA20_CLK_NDFLASH, TEGRA20_CLK_PLL_P, 150000000, 0 },
> > > /* must be the last entry */
> > > { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
> > > };
> > > --
> > > 2.17.0
> > >
> >
> > Maybe better to specify this in the Tegra20 dtsi? See
> > "Assigned clock parents and rates" in
> > Documentation/devicetree/bindings/clock/clock-bindings.txt
>
> assigned-clocks indeed works just fine for this case. Thanks for
> bringing this up, will drop this patch and add the device tree
> properties in v3.
>
> Hm, interesting that none of the Tegra device tree make use of the
> feature so far. I guess there would be other cases where this would be
> useful as well (the one just above, VDE?).
Most of the Tegra clock init stuff (including this patch) was written
before we had assigned-clocks as some common DT facility. But fully
agree on dropping this patch.
Regards,
Lucas
^ permalink raw reply
* Re: [PATCH v2 4/6] clk: tegra20: init NDFLASH clock to sensible rate
From: Stefan Agner @ 2018-05-28 15:53 UTC (permalink / raw)
To: Peter De Schrijver
Cc: boris.brezillon, dwmw2, computersforpeace, marek.vasut, robh+dt,
mark.rutland, thierry.reding, mturquette, sboyd, dev,
miquel.raynal, richard, marcel, krzk, digetx, benjamin.lindqvist,
jonathanh, pgaikwad, mirza.krak, linux-mtd, linux-tegra,
devicetree, linux-kernel, linux-clk
In-Reply-To: <20180528075510.GQ6835@tbergstrom-lnx.Nvidia.com>
On 28.05.2018 09:55, Peter De Schrijver wrote:
> On Sun, May 27, 2018 at 11:54:40PM +0200, Stefan Agner wrote:
>> From: Lucas Stach <dev@lynxeye.de>
>>
>> Set up the NAND Flash controller clock to run at 150MHz
>> instead of the rate set by the bootloader. This is a
>> conservative rate which also yields good performance.
>>
>> Signed-off-by: Lucas Stach <dev@lynxeye.de>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
>> ---
>> drivers/clk/tegra/clk-tegra20.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
>> index 0ee56dd04cec..dff8c425cd28 100644
>> --- a/drivers/clk/tegra/clk-tegra20.c
>> +++ b/drivers/clk/tegra/clk-tegra20.c
>> @@ -1049,6 +1049,7 @@ static struct tegra_clk_init_table init_table[] __initdata = {
>> { TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0 },
>> { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 },
>> { TEGRA20_CLK_VDE, TEGRA20_CLK_CLK_MAX, 300000000, 0 },
>> + { TEGRA20_CLK_NDFLASH, TEGRA20_CLK_PLL_P, 150000000, 0 },
>> /* must be the last entry */
>> { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 },
>> };
>> --
>> 2.17.0
>>
>
> Maybe better to specify this in the Tegra20 dtsi? See
> "Assigned clock parents and rates" in
> Documentation/devicetree/bindings/clock/clock-bindings.txt
assigned-clocks indeed works just fine for this case. Thanks for
bringing this up, will drop this patch and add the device tree
properties in v3.
Hm, interesting that none of the Tegra device tree make use of the
feature so far. I guess there would be other cases where this would be
useful as well (the one just above, VDE?).
--
Stefan
^ permalink raw reply
* Re: [PATCH 01/15] arm: dts: armada: Fix "#cooling-cells" property's name
From: Gregory CLEMENT @ 2018-05-28 14:53 UTC (permalink / raw)
To: Viresh Kumar
Cc: Mark Rutland, Andrew Lunn, Vincent Guittot, Jason Cooper,
devicetree, Daniel Lezcano, linux-kernel, Rob Herring, arm,
chris.redpath, ionela.voinescu, linux-arm-kernel,
Sebastian Hesselbarth
In-Reply-To: <26a0666368694db610414a85a08843435ea070a7.1527244201.git.viresh.kumar@linaro.org>
Hi Viresh,
On ven., mai 25 2018, Viresh Kumar <viresh.kumar@linaro.org> wrote:
> It should be "#cooling-cells" instead of "cooling-cells". Fix it.
>
> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Applied on mvebu/fixes
Thanks,
Gregory
> ---
> arch/arm/boot/dts/armada-385-synology-ds116.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/armada-385-synology-ds116.dts b/arch/arm/boot/dts/armada-385-synology-ds116.dts
> index 6782ce481ac9..d8769956cbfc 100644
> --- a/arch/arm/boot/dts/armada-385-synology-ds116.dts
> +++ b/arch/arm/boot/dts/armada-385-synology-ds116.dts
> @@ -139,7 +139,7 @@
> 3700 5
> 3900 6
> 4000 7>;
> - cooling-cells = <2>;
> + #cooling-cells = <2>;
> };
>
> gpio-leds {
> --
> 2.15.0.194.g9af6a3dea062
>
--
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply
* Re: [PATCH 1/5] ptp: rework gianfar_ptp as QorIQ common PTP driver
From: Richard Cochran @ 2018-05-28 14:29 UTC (permalink / raw)
To: Yangbo Lu; +Cc: netdev, devicetree, linux-kernel, claudiu.manoil, Rob Herring
In-Reply-To: <20180525044038.37756-1-yangbo.lu@nxp.com>
On Fri, May 25, 2018 at 12:40:34PM +0800, Yangbo Lu wrote:
> gianfar_ptp was the PTP clock driver for 1588 timer
> module of Freescale QorIQ eTSEC (Enhanced Three-Speed
> Ethernet Controllers) platforms. Actually QorIQ DPAA
> (Data Path Acceleration Architecture) platforms is
> also using the same 1588 timer module in hardware.
>
> This patch is to rework gianfar_ptp as QorIQ common
> PTP driver to support both DPAA and eTSEC. Moved
> gianfar_ptp.c to drivers/ptp/, renamed it as
> ptp_qoriq.c, and renamed many variables. There were
> not any function changes.
>
> Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
For the series:
Acked-by: Richard Cochran <richardcochran@gmail.com>
^ permalink raw reply
* [PATCH/RFC] arm64: dts: renesas: salvator-common: Add HSCIF1 device support
From: Geert Uytterhoeven @ 2018-05-28 13:28 UTC (permalink / raw)
To: Simon Horman, Magnus Damm, Rob Herring, Mark Rutland
Cc: Wolfram Sang, Laurent Pinchart, Ulrich Hecht, linux-renesas-soc,
devicetree, Hiromitsu Yamasaki, Takeshi Kihara,
Geert Uytterhoeven
From: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>
This patch adds the pin control for HSCIF1, and supports connection with
the Debug Serial-1 (CN26) on Salvator boards.
SCIF1 and HSCI1 are sharing the pin connected to the Debug Serial-1
(CN26) on Salvator boards, and it is necessary to use it by exclusion.
As for the default of this DeviceTree, SCIF1 is connected.
Signed-off-by: Hiromitsu Yamasaki <hiromitsu.yamasaki.ym@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Add missing "uart-has-rtscts"]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
This depends on "arm64: dts: renesas: r8a77965: Add all HSCIF nodes",
due to the &hscif1 reference.
This doesn't really change anything, but serves as an example and
documentation.
Questions:
1. Do we want to have such examples/documentation?
2. Should we make HSCIF1 the default? IMHO, HSCIF is superior to SCIF.
Both are served by the same driver, so increased kernel size is not
a counter-argument.
For comparison: r8a7790-lager.dts uses SCIFA1 instead of SCIF1 for
the debug serial (not for the serial console, due to earlycon and
U-Boot compatibility).
arch/arm64/boot/dts/renesas/salvator-common.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
index 9256fbaaab7f3297..976fda67e202f054 100644
--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
@@ -341,6 +341,15 @@
clock-frequency = <32768>;
};
+&hscif1 {
+ pinctrl-0 = <&hscif1_pins>;
+ pinctrl-names = "default";
+
+ uart-has-rtscts;
+ /* Please use exclusively to the scif1 node */
+ /* status = "okay"; */
+};
+
&hsusb {
dr_mode = "otg";
status = "okay";
@@ -546,6 +555,11 @@
function = "du";
};
+ hscif1_pins: hscif1 {
+ groups = "hscif1_data_a", "hscif1_ctrl_a";
+ function = "hscif1";
+ };
+
i2c2_pins: i2c2 {
groups = "i2c2_a";
function = "i2c2";
@@ -711,6 +725,7 @@
pinctrl-names = "default";
uart-has-rtscts;
+ /* Please use exclusively to the hscif1 node */
status = "okay";
};
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v5] usb: gadget: udc: renesas_usb3: Add register of usb role switch
From: Heikki Krogerus @ 2018-05-28 13:04 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: gregkh, robh+dt, mark.rutland, hdegoede, andy.shevchenko,
linux-usb, linux-renesas-soc, devicetree
In-Reply-To: <1527232376-5613-1-git-send-email-yoshihiro.shimoda.uh@renesas.com>
On Fri, May 25, 2018 at 04:12:56PM +0900, Yoshihiro Shimoda wrote:
> @@ -2573,6 +2635,12 @@ static void renesas_usb3_init_ram(struct renesas_usb3 *usb3, struct device *dev,
> EXTCON_NONE,
> };
>
> +static struct usb_role_switch_desc renesas_usb3_role_switch_desc = {
You can constify that.
> + .set = renesas_usb3_role_switch_set,
> + .get = renesas_usb3_role_switch_get,
> + .allow_userspace_control = true,
> +};
> +
> static int renesas_usb3_probe(struct platform_device *pdev)
> {
> struct renesas_usb3 *usb3;
Thanks,
--
heikki
^ permalink raw reply
* Re: [PATCH v5] usb: gadget: udc: renesas_usb3: Add register of usb role switch
From: Andy Shevchenko @ 2018-05-28 12:47 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: Greg Kroah-Hartman, Rob Herring, Mark Rutland, Krogerus, Heikki,
Hans de Goede, USB, Linux-Renesas, devicetree
In-Reply-To: <1527232376-5613-1-git-send-email-yoshihiro.shimoda.uh@renesas.com>
On Fri, May 25, 2018 at 10:12 AM, Yoshihiro Shimoda
<yoshihiro.shimoda.uh@renesas.com> wrote:
> -static void usb3_set_mode(struct renesas_usb3 *usb3, bool host)
Wouldn't be better to choose another name for a new function?
> + struct renesas_usb3 *usb3 = container_of(work, struct renesas_usb3,
> + role_work);
Matter of style, though I would rather put entire container_of() on
the next line (see for the existing style in the module and use it).
> + /* This device_attach() might sleep */
> + if (device_attach(host) < 0)
> + dev_err(dev, "device_attach(usb3_port) failed\n");
can't be "usb3_port" part derived from the host variable somehow and
to some extend?
> + usb3->role_sw = usb_role_switch_register(&pdev->dev,
> + &renesas_usb3_role_switch_desc);
> + if (!IS_ERR(usb3->role_sw)) {
> + usb3->host_dev = usb_of_get_companion_dev(&pdev->dev);
Hmm... Can it possible return -EPROBE_DEFER? If so, would it be better
to use other approach to handle it?
> + if (IS_ERR_OR_NULL(usb3->host_dev)) {
> + /* If not found, this driver will not use a role sw */
> + usb_role_switch_unregister(usb3->role_sw);
> + usb3->role_sw = NULL;
> + }
> + } else {
> + usb3->role_sw = NULL;
> + }
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v2 3/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver
From: Stefan Agner @ 2018-05-28 12:43 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: boris.brezillon, dwmw2, computersforpeace, marek.vasut, robh+dt,
mark.rutland, thierry.reding, mturquette, sboyd, dev,
miquel.raynal, richard, marcel, krzk, benjamin.lindqvist,
jonathanh, pdeschrijver, pgaikwad, mirza.krak, linux-mtd,
linux-tegra, devicetree, linux-kernel, linux-clk
In-Reply-To: <b9cfc23e-2434-fd90-ae2d-e51f28b16038@gmail.com>
On 28.05.2018 13:57, Dmitry Osipenko wrote:
> On 28.05.2018 00:54, Stefan Agner wrote:
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode. Page read/writes with hardware ECC make
>> use of the DMA for data transfer.
>>
>> Signed-off-by: Lucas Stach <dev@lynxeye.de>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
>> ---
>> MAINTAINERS | 7 +
>> drivers/mtd/nand/raw/Kconfig | 6 +
>> drivers/mtd/nand/raw/Makefile | 1 +
>> drivers/mtd/nand/raw/tegra_nand.c | 999 ++++++++++++++++++++++++++++++
>> 4 files changed, 1013 insertions(+)
>> create mode 100644 drivers/mtd/nand/raw/tegra_nand.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 58b9861ccf99..8cbbb7111742 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -13844,6 +13844,13 @@ M: Laxman Dewangan <ldewangan@nvidia.com>
>> S: Supported
>> F: drivers/input/keyboard/tegra-kbc.c
>>
>> +TEGRA NAND DRIVER
>> +M: Stefan Agner <stefan@agner.ch>
>> +M: Lucas Stach <dev@lynxeye.de>
>> +S: Maintained
>> +F: Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt
>> +F: drivers/mtd/nand/raw/tegra_nand.c
>> +
>> TEGRA PWM DRIVER
>> M: Thierry Reding <thierry.reding@gmail.com>
>> S: Supported
>> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
>> index 19a2b283fbbe..012c63c6ab47 100644
>> --- a/drivers/mtd/nand/raw/Kconfig
>> +++ b/drivers/mtd/nand/raw/Kconfig
>> @@ -534,4 +534,10 @@ config MTD_NAND_MTK
>> Enables support for NAND controller on MTK SoCs.
>> This controller is found on mt27xx, mt81xx, mt65xx SoCs.
>>
>> +config MTD_NAND_TEGRA
>> + tristate "Support for NAND on NVIDIA Tegra"
>> + depends on ARCH_TEGRA || COMPILE_TEST
>> + help
>> + Enables support for NAND flash on NVIDIA Tegra SoC based boards.
>> +
>> endif # MTD_NAND
>> diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
>> index 165b7ef9e9a1..d5a5f9832b88 100644
>> --- a/drivers/mtd/nand/raw/Makefile
>> +++ b/drivers/mtd/nand/raw/Makefile
>> @@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
>> obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
>> obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
>> obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o
>> +obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o
>>
>> nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
>> nand-objs += nand_amd.o
>> diff --git a/drivers/mtd/nand/raw/tegra_nand.c b/drivers/mtd/nand/raw/tegra_nand.c
>> new file mode 100644
>> index 000000000000..1a0833d97472
>> --- /dev/null
>> +++ b/drivers/mtd/nand/raw/tegra_nand.c
>> @@ -0,0 +1,999 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2018 Stefan Agner <stefan@agner.ch>
>> + * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
>> + * Copyright (C) 2012 Avionic Design GmbH
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/completion.h>
>> +#include <linux/delay.h>
>> +#include <linux/dma-mapping.h>
>> +#include <linux/err.h>
>> +#include <linux/gpio/consumer.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/io.h>
>> +#include <linux/module.h>
>> +#include <linux/mtd/partitions.h>
>> +#include <linux/mtd/rawnand.h>
>> +#include <linux/of.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/reset.h>
>> +
>> +#define CMD 0x00
>> +#define CMD_GO (1 << 31)
>> +#define CMD_CLE (1 << 30)
>> +#define CMD_ALE (1 << 29)
>> +#define CMD_PIO (1 << 28)
>> +#define CMD_TX (1 << 27)
>> +#define CMD_RX (1 << 26)
>> +#define CMD_SEC_CMD (1 << 25)
>> +#define CMD_AFT_DAT (1 << 24)
>> +#define CMD_TRANS_SIZE(x) (((x - 1) & 0xf) << 20)
>> +#define CMD_A_VALID (1 << 19)
>> +#define CMD_B_VALID (1 << 18)
>> +#define CMD_RD_STATUS_CHK (1 << 17)
>> +#define CMD_RBSY_CHK (1 << 16)
>> +#define CMD_CE(x) (1 << (8 + ((x) & 0x7)))
>> +#define CMD_CLE_SIZE(x) (((x - 1) & 0x3) << 4)
>> +#define CMD_ALE_SIZE(x) (((x - 1) & 0xf) << 0)
>> +
>> +#define STATUS 0x04
>> +
>> +#define ISR 0x08
>> +#define ISR_CORRFAIL_ERR (1 << 24)
>> +#define ISR_UND (1 << 7)
>> +#define ISR_OVR (1 << 6)
>> +#define ISR_CMD_DONE (1 << 5)
>> +#define ISR_ECC_ERR (1 << 4)
>> +
>> +#define IER 0x0c
>> +#define IER_ERR_TRIG_VAL(x) (((x) & 0xf) << 16)
>> +#define IER_UND (1 << 7)
>> +#define IER_OVR (1 << 6)
>> +#define IER_CMD_DONE (1 << 5)
>> +#define IER_ECC_ERR (1 << 4)
>> +#define IER_GIE (1 << 0)
>> +
>> +#define CFG 0x10
>> +#define CFG_HW_ECC (1 << 31)
>> +#define CFG_ECC_SEL (1 << 30)
>> +#define CFG_ERR_COR (1 << 29)
>> +#define CFG_PIPE_EN (1 << 28)
>> +#define CFG_TVAL_4 (0 << 24)
>> +#define CFG_TVAL_6 (1 << 24)
>> +#define CFG_TVAL_8 (2 << 24)
>> +#define CFG_SKIP_SPARE (1 << 23)
>> +#define CFG_BUS_WIDTH_8 (0 << 21)
>> +#define CFG_BUS_WIDTH_16 (1 << 21)
>> +#define CFG_COM_BSY (1 << 20)
>> +#define CFG_PS_256 (0 << 16)
>> +#define CFG_PS_512 (1 << 16)
>> +#define CFG_PS_1024 (2 << 16)
>> +#define CFG_PS_2048 (3 << 16)
>> +#define CFG_PS_4096 (4 << 16)
>> +#define CFG_SKIP_SPARE_SIZE_4 (0 << 14)
>> +#define CFG_SKIP_SPARE_SIZE_8 (1 << 14)
>> +#define CFG_SKIP_SPARE_SIZE_12 (2 << 14)
>> +#define CFG_SKIP_SPARE_SIZE_16 (3 << 14)
>> +#define CFG_TAG_BYTE_SIZE(x) ((x) & 0xff)
>> +
>> +#define TIMING_1 0x14
>> +#define TIMING_TRP_RESP(x) (((x) & 0xf) << 28)
>> +#define TIMING_TWB(x) (((x) & 0xf) << 24)
>> +#define TIMING_TCR_TAR_TRR(x) (((x) & 0xf) << 20)
>> +#define TIMING_TWHR(x) (((x) & 0xf) << 16)
>> +#define TIMING_TCS(x) (((x) & 0x3) << 14)
>> +#define TIMING_TWH(x) (((x) & 0x3) << 12)
>> +#define TIMING_TWP(x) (((x) & 0xf) << 8)
>> +#define TIMING_TRH(x) (((x) & 0xf) << 4)
>> +#define TIMING_TRP(x) (((x) & 0xf) << 0)
>> +
>> +#define RESP 0x18
>> +
>> +#define TIMING_2 0x1c
>> +#define TIMING_TADL(x) ((x) & 0xf)
>> +
>> +#define CMD_1 0x20
>> +#define CMD_2 0x24
>> +#define ADDR_1 0x28
>> +#define ADDR_2 0x2c
>> +
>> +#define DMA_CTRL 0x30
>> +#define DMA_CTRL_GO (1 << 31)
>> +#define DMA_CTRL_IN (0 << 30)
>> +#define DMA_CTRL_OUT (1 << 30)
>> +#define DMA_CTRL_PERF_EN (1 << 29)
>> +#define DMA_CTRL_IE_DONE (1 << 28)
>> +#define DMA_CTRL_REUSE (1 << 27)
>> +#define DMA_CTRL_BURST_1 (2 << 24)
>> +#define DMA_CTRL_BURST_4 (3 << 24)
>> +#define DMA_CTRL_BURST_8 (4 << 24)
>> +#define DMA_CTRL_BURST_16 (5 << 24)
>> +#define DMA_CTRL_IS_DONE (1 << 20)
>> +#define DMA_CTRL_EN_A (1 << 2)
>> +#define DMA_CTRL_EN_B (1 << 1)
>> +
>> +#define DMA_CFG_A 0x34
>> +#define DMA_CFG_B 0x38
>> +
>> +#define FIFO_CTRL 0x3c
>> +#define FIFO_CTRL_CLR_ALL (1 << 3)
>> +
>> +#define DATA_PTR 0x40
>> +#define TAG_PTR 0x44
>> +#define ECC_PTR 0x48
>> +
>> +#define DEC_STATUS 0x4c
>> +#define DEC_STATUS_A_ECC_FAIL (1 << 1)
>> +#define DEC_STATUS_ERR_COUNT_MASK 0x00ff0000
>> +#define DEC_STATUS_ERR_COUNT_SHIFT 16
>> +
>> +#define HWSTATUS_CMD 0x50
>> +#define HWSTATUS_MASK 0x54
>> +#define HWSTATUS_RDSTATUS_MASK(x) (((x) & 0xff) << 24)
>> +#define HWSTATUS_RDSTATUS_VALUE(x) (((x) & 0xff) << 16)
>> +#define HWSTATUS_RBSY_MASK(x) (((x) & 0xff) << 8)
>> +#define HWSTATUS_RBSY_VALUE(x) (((x) & 0xff) << 0)
>> +
>> +#define BCH_CONFIG 0xcc
>> +#define BCH_ENABLE (1 << 0)
>> +#define BCH_TVAL_4 (0 << 4)
>> +#define BCH_TVAL_8 (1 << 4)
>> +#define BCH_TVAL_14 (2 << 4)
>> +#define BCH_TVAL_16 (3 << 4)
>> +
>> +#define DEC_STAT_RESULT 0xd0
>> +#define DEC_STAT_BUF 0xd4
>> +#define DEC_STAT_BUF_FAIL_SEC_FLAG_MASK 0xff000000
>> +#define DEC_STAT_BUF_FAIL_SEC_FLAG_SHIFT 24
>> +#define DEC_STAT_BUF_CORR_SEC_FLAG_MASK 0x00ff0000
>> +#define DEC_STAT_BUF_CORR_SEC_FLAG_SHIFT 16
>> +#define DEC_STAT_BUF_MAX_CORR_CNT_MASK 0x00001f00
>> +#define DEC_STAT_BUF_MAX_CORR_CNT_SHIFT 8
>> +
>> +#define SKIP_SPARE_BYTES 4
>> +#define BITS_PER_STEP_RS 18
>> +#define BITS_PER_STEP_BCH 13
>> +
>> +struct tegra_nand_controller {
>> + struct nand_hw_control controller;
>> + void __iomem *regs;
>> + struct clk *clk;
>> + struct device *dev;
>> + struct completion command_complete;
>> + struct completion dma_complete;
>> + bool last_read_error;
>> + int cur_chip;
>> + struct nand_chip *chip;
>> +};
>> +
>> +struct tegra_nand_chip {
>> + struct nand_chip chip;
>> + struct gpio_desc *wp_gpio;
>> +};
>> +
>> +static inline struct tegra_nand_controller *to_tegra_ctrl(
>> + struct nand_hw_control *hw_ctrl)
>> +{
>> + return container_of(hw_ctrl, struct tegra_nand_controller, controller);
>> +}
>> +
>> +static int tegra_nand_ooblayout_rs_ecc(struct mtd_info *mtd, int section,
>> + struct mtd_oob_region *oobregion)
>> +{
>> + struct nand_chip *chip = mtd_to_nand(mtd);
>> + int bytes_per_step = (BITS_PER_STEP_RS * chip->ecc.strength) / 8;
>> +
>> + if (section > 0)
>> + return -ERANGE;
>> +
>> + oobregion->offset = SKIP_SPARE_BYTES;
>> + oobregion->length = round_up(bytes_per_step * chip->ecc.steps, 4);
>> +
>> + return 0;
>> +}
>> +
>> +static int tegra_nand_ooblayout_rs_free(struct mtd_info *mtd, int section,
>> + struct mtd_oob_region *oobregion)
>> +{
>> + struct nand_chip *chip = mtd_to_nand(mtd);
>> + int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength, 8);
>> +
>> + if (section > 0)
>> + return -ERANGE;
>> +
>> + oobregion->offset = SKIP_SPARE_BYTES +
>> + round_up(bytes_per_step * chip->ecc.steps, 4);
>> + oobregion->length = mtd->oobsize - oobregion->offset;
>> +
>> + return 0;
>> +}
>> +
>> +static const struct mtd_ooblayout_ops tegra_nand_oob_rs_ops = {
>> + .ecc = tegra_nand_ooblayout_rs_ecc,
>> + .free = tegra_nand_ooblayout_rs_free,
>> +};
>> +
>> +static int tegra_nand_ooblayout_bch_ecc(struct mtd_info *mtd, int section,
>> + struct mtd_oob_region *oobregion)
>> +{
>> + struct nand_chip *chip = mtd_to_nand(mtd);
>> + int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_BCH * chip->ecc.strength, 8);
>> +
>> + if (section > 0)
>> + return -ERANGE;
>> +
>> + oobregion->offset = SKIP_SPARE_BYTES;
>> + oobregion->length = round_up(bytes_per_step * chip->ecc.steps, 4);
>> +
>> + return 0;
>> +}
>> +
>> +static int tegra_nand_ooblayout_bch_free(struct mtd_info *mtd, int section,
>> + struct mtd_oob_region *oobregion)
>> +{
>> + struct nand_chip *chip = mtd_to_nand(mtd);
>> + int bytes_per_step = (BITS_PER_STEP_BCH * chip->ecc.strength) / 8;
>> +
>> + if (section > 0)
>> + return -ERANGE;
>> +
>> + oobregion->offset = SKIP_SPARE_BYTES +
>> + round_up(bytes_per_step * chip->ecc.steps, 4);
>> + oobregion->length = mtd->oobsize - oobregion->offset;
>> +
>> + return 0;
>> +}
>> +
>> +/*
>> + * Layout with tag bytes is
>> + *
>> + * --------------------------------------------------------------------------
>> + * | main area | skip bytes | tag bytes | parity | .. |
>> + * --------------------------------------------------------------------------
>> + *
>> + * If not tag bytes are written, parity moves right after skip bytes!
>> + */
>> +static const struct mtd_ooblayout_ops tegra_nand_oob_bch_ops = {
>> + .ecc = tegra_nand_ooblayout_bch_ecc,
>> + .free = tegra_nand_ooblayout_bch_free,
>> +};
>> +
>> +static irqreturn_t tegra_nand_irq(int irq, void *data)
>> +{
>> + struct tegra_nand_controller *ctrl = data;
>> + u32 isr, dma;
>> +
>> + isr = readl_relaxed(ctrl->regs + ISR);
>> + dma = readl_relaxed(ctrl->regs + DMA_CTRL);
>> + dev_dbg(ctrl->dev, "isr %08x\n", isr);
>> +
>> + if (!isr && !(dma & DMA_CTRL_IS_DONE))
>> + return IRQ_NONE;
>> +
>> + if (isr & ISR_CORRFAIL_ERR)
>> + ctrl->last_read_error = true;
>> +
>> + if (isr & ISR_CMD_DONE)
>> + complete(&ctrl->command_complete);
>> +
>> + if (isr & ISR_UND)
>> + dev_dbg(ctrl->dev, "FIFO underrun\n");
>> +
>> + if (isr & ISR_OVR)
>> + dev_dbg(ctrl->dev, "FIFO overrun\n");
>> +
>> + /* handle DMA interrupts */
>> + if (dma & DMA_CTRL_IS_DONE) {
>> + writel(dma, ctrl->regs + DMA_CTRL);
>> + complete(&ctrl->dma_complete);
>> + }
>> +
>> + /* clear interrupts */
>> + writel(isr, ctrl->regs + ISR);
>> +
>> + return IRQ_HANDLED;
>> +}
>> +
>> +static int tegra_nand_cmd(struct nand_chip *chip,
>> + const struct nand_subop *subop)
>> +{
>> + const struct nand_op_instr *instr;
>> + const struct nand_op_instr *instr_data_in = NULL;
>> + struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
>> + unsigned int op_id = -1, trfr_in_sz = 0, trfr_out_sz = 0, offset = 0;
>> + bool first_cmd = true;
>> + u32 cmd = 0;
>> + u32 value;
>> +
>> + for (op_id = 0; op_id < subop->ninstrs; op_id++) {
>> + unsigned int naddrs, i;
>> + const u8 *addrs;
>> + u32 addr1 = 0, addr2 = 0;
>> +
>> + instr = &subop->instrs[op_id];
>> +
>> + switch (instr->type) {
>> + case NAND_OP_CMD_INSTR:
>> + if (first_cmd) {
>> + cmd |= CMD_CLE;
>> + writel(instr->ctx.cmd.opcode, ctrl->regs + CMD_1);
>> + } else {
>> + cmd |= CMD_SEC_CMD;
>> + writel(instr->ctx.cmd.opcode, ctrl->regs + CMD_2);
>> + }
>> + first_cmd = false;
>> + break;
>> + case NAND_OP_ADDR_INSTR:
>> + offset = nand_subop_get_addr_start_off(subop, op_id);
>> + naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
>> + addrs = &instr->ctx.addr.addrs[offset];
>> +
>> + cmd |= CMD_ALE | CMD_ALE_SIZE(naddrs);
>> + for (i = 0; i < min_t(unsigned int, 4, naddrs); i++)
>> + addr1 |= *addrs++ << (8 * i);
>> + naddrs -= i;
>> + for (i = 0; i < min_t(unsigned int, 4, naddrs); i++)
>> + addr2 |= *addrs++ << (8 * i);
>> + writel(addr1, ctrl->regs + ADDR_1);
>> + writel(addr2, ctrl->regs + ADDR_2);
>> + break;
>> +
>> + case NAND_OP_DATA_IN_INSTR:
>> + trfr_in_sz = nand_subop_get_data_len(subop, op_id);
>> + offset = nand_subop_get_data_start_off(subop, op_id);
>> +
>> + cmd |= CMD_TRANS_SIZE(trfr_in_sz) | CMD_PIO | CMD_RX | CMD_A_VALID;
>> +
>> + instr_data_in = instr;
>> + break;
>> +
>> + case NAND_OP_DATA_OUT_INSTR:
>> + trfr_out_sz = nand_subop_get_data_len(subop, op_id);
>> + offset = nand_subop_get_data_start_off(subop, op_id);
>> + trfr_out_sz = min_t(size_t, trfr_out_sz, 4);
>> +
>> + cmd |= CMD_TRANS_SIZE(trfr_out_sz) | CMD_PIO | CMD_TX | CMD_A_VALID;
>> +
>> + memcpy(&value, instr->ctx.data.buf.out + offset, trfr_out_sz);
>> + writel(value, ctrl->regs + RESP);
>> +
>> + break;
>> + case NAND_OP_WAITRDY_INSTR:
>> + cmd |= CMD_RBSY_CHK;
>> + break;
>> +
>> + }
>> + }
>> +
>> +
>> + cmd |= CMD_GO | CMD_CE(ctrl->cur_chip);
>> + writel(cmd, ctrl->regs + CMD);
>> + wait_for_completion(&ctrl->command_complete);
>
> Could this and other completions stuck forever? What about
> wait_for_completion_timeout() + HW reset / re-init on timeout?
>
They actually get stuck forever when I try to use DMA without HW ECC...
I haven't seen it with HW ECC.
But yes, _timeout variant makes sense here. Not sure if re-init is
necessary since we rewrite all the relevant settings.
>> +
>> + if (instr_data_in) {
>> + u32 value;
>> + size_t n = min_t(size_t, trfr_in_sz, 4);
>> +
>> + value = readl(ctrl->regs + RESP);
>> + memcpy(instr_data_in->ctx.data.buf.in + offset, &value, n);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static const struct nand_op_parser tegra_nand_op_parser = NAND_OP_PARSER(
>> + NAND_OP_PARSER_PATTERN(tegra_nand_cmd,
>> + NAND_OP_PARSER_PAT_CMD_ELEM(true),
>> + NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8),
>> + NAND_OP_PARSER_PAT_CMD_ELEM(true),
>> + NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
>> + NAND_OP_PARSER_PATTERN(tegra_nand_cmd,
>> + NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, 4)),
>> + NAND_OP_PARSER_PATTERN(tegra_nand_cmd,
>> + NAND_OP_PARSER_PAT_CMD_ELEM(true),
>> + NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8),
>> + NAND_OP_PARSER_PAT_CMD_ELEM(true),
>> + NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
>> + NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, 4)),
>> + );
>> +
>> +static int tegra_nand_exec_op(struct nand_chip *chip,
>> + const struct nand_operation *op,
>> + bool check_only)
>> +{
>> + return nand_op_parser_exec_op(chip, &tegra_nand_op_parser, op,
>> + check_only);
>> +}
>> +static void tegra_nand_select_chip(struct mtd_info *mtd, int chip_nr)
>> +{
>> + struct nand_chip *chip = mtd_to_nand(mtd);
>> + struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
>> +
>> + ctrl->cur_chip = chip_nr;
>> +}
>> +
>> +static u32 tegra_nand_fill_address(struct tegra_nand_controller *ctrl,
>> + struct nand_chip *chip, int page)
>> +{
>> + /* Lower 16-bits are column, always 0 */
>> + writel(page << 16, ctrl->regs + ADDR_1);
>> +
>> + if (chip->options & NAND_ROW_ADDR_3) {
>> + writel(page >> 16, ctrl->regs + ADDR_2);
>> + return 5;
>> + }
>> +
>> + return 4;
>> +}
>> +
>> +static void tegra_nand_hw_ecc(struct tegra_nand_controller *ctrl,
>> + struct nand_chip *chip, bool enable)
>> +{
>> + u32 value;
>> +
>> + switch (chip->ecc.algo) {
>> + case NAND_ECC_RS:
>> + value = readl(ctrl->regs + CFG);
>> + if (enable)
>> + value |= CFG_HW_ECC | CFG_ERR_COR;
>> + else
>> + value &= ~(CFG_HW_ECC | CFG_ERR_COR);
>> + writel(value, ctrl->regs + CFG);
>> + break;
>> + case NAND_ECC_BCH:
>> + value = readl(ctrl->regs + BCH_CONFIG);
>> + if (enable)
>> + value |= BCH_ENABLE;
>> + else
>> + value &= ~BCH_ENABLE;
>> + writel(value, ctrl->regs + BCH_CONFIG);
>> + break;
>> + default:
>> + dev_err(ctrl->dev, "Unsupported hardware ECC algorithm\n");
>> + break;
>> + }
>> +}
>> +
>> +static int tegra_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
>> + uint8_t *buf, int oob_required, int page)
>> +{
>> + struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
>> + dma_addr_t dma_addr;
>> + u32 value, addrs;
>> + int ret, dma_len;
>> +
>> + writel(NAND_CMD_READ0, ctrl->regs + CMD_1);
>> + writel(NAND_CMD_READSTART, ctrl->regs + CMD_2);
>> +
>> + addrs = tegra_nand_fill_address(ctrl, chip, page);
>> +
>> + dma_len = mtd->writesize + (oob_required ? mtd->oobsize : 0);
>> + dma_addr = dma_map_single(ctrl->dev, buf, dma_len, DMA_FROM_DEVICE);
>> + ret = dma_mapping_error(ctrl->dev, dma_addr);
>> + if (ret) {
>> + dev_err(ctrl->dev, "dma mapping error\n");
>> + return -EINVAL;
>> + }
>> +
>> + writel(mtd->writesize - 1, ctrl->regs + DMA_CFG_A);
>> + writel(dma_addr, ctrl->regs + DATA_PTR);
>> +
>> + if (oob_required) {
>> + struct mtd_oob_region oobregion;
>> + dma_addr_t dma_addr_oob = dma_addr + mtd->writesize;
>> +
>> + mtd_ooblayout_free(mtd, 0, &oobregion);
>> +
>> + writel(oobregion.length - 1, ctrl->regs + DMA_CFG_B);
>> + writel(dma_addr_oob + oobregion.offset, ctrl->regs + TAG_PTR);
>> + } else {
>> + writel(0, ctrl->regs + DMA_CFG_B);
>> + writel(0, ctrl->regs + TAG_PTR);
>> + }
>> +
>> + value = DMA_CTRL_GO | DMA_CTRL_IN | DMA_CTRL_PERF_EN |
>> + DMA_CTRL_REUSE | DMA_CTRL_IE_DONE | DMA_CTRL_IS_DONE |
>> + DMA_CTRL_BURST_16 | DMA_CTRL_EN_A;
>> + if (oob_required)
>> + value |= DMA_CTRL_EN_B;
>> + writel(value, ctrl->regs + DMA_CTRL);
>> +
>> + value = CMD_CLE | CMD_ALE | CMD_ALE_SIZE(addrs) | CMD_SEC_CMD |
>> + CMD_RBSY_CHK | CMD_GO | CMD_RX | CMD_TRANS_SIZE(9) |
>> + CMD_A_VALID | CMD_CE(ctrl->cur_chip);
>> + if (oob_required)
>> + value |= CMD_B_VALID;
>> + writel(value, ctrl->regs + CMD);
>> +
>> + wait_for_completion(&ctrl->command_complete);
>> + wait_for_completion(&ctrl->dma_complete);
>> +
>> + dma_unmap_single(ctrl->dev, dma_addr, dma_len, DMA_FROM_DEVICE);
>> +
>> + return 0;
>> +}
>> +
>> +static int tegra_nand_read_page_hwecc(struct mtd_info *mtd,
>> + struct nand_chip *chip,
>> + uint8_t *buf, int oob_required, int page)
>> +{
>> + struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
>> + u32 value;
>> + int ret;
>> +
>> + tegra_nand_hw_ecc(ctrl, chip, true);
>> + ret = tegra_nand_read_page(mtd, chip, buf, oob_required, page);
>> + tegra_nand_hw_ecc(ctrl, chip, false);
>> + if (ret)
>> + return ret;
>> +
>> + /* If no correctable or un-correctable errors occured we can return 0 */
>> + if (!ctrl->last_read_error)
>> + return 0;
>> +
>> + /*
>> + * Correctable or un-correctable errors did occure. NAND dec status
>> + * contains information for all ECC selections
>> + */
>> + ctrl->last_read_error = false;
>> + value = readl(ctrl->regs + DEC_STAT_BUF);
>> +
>> + if (value & DEC_STAT_BUF_FAIL_SEC_FLAG_MASK) {
>> + /*
>> + * The ECC isn't smart enough to figure out if a page is
>> + * completely erased and flags an error in this case. So we
>> + * check the read data here to figure out if it's a legitimate
>> + * error or a false positive.
>> + */
>> + int i, ret;
>> + int flips_threshold = chip->ecc.strength / 2;
>> + int max_bitflips = 0;
>> +
>> + for (i = 0; i < chip->ecc.steps; i++) {
>> + u8 *data = buf + (chip->ecc.size * i);
>> +
>> + ret = nand_check_erased_ecc_chunk(data, chip->ecc.size,
>> + NULL, 0,
>> + NULL, 0,
>> + flips_threshold);
>> + if (ret < 0)
>> + mtd->ecc_stats.failed++;
>> + else
>> + max_bitflips = max(ret, max_bitflips);
>> + }
>> +
>> + return max_bitflips;
>> + } else {
>> + int max_corr_cnt, corr_sec_flag;
>> +
>> + corr_sec_flag = (value & DEC_STAT_BUF_CORR_SEC_FLAG_MASK) >>
>> + DEC_STAT_BUF_CORR_SEC_FLAG_SHIFT;
>> + max_corr_cnt = (value & DEC_STAT_BUF_MAX_CORR_CNT_MASK) >>
>> + DEC_STAT_BUF_MAX_CORR_CNT_SHIFT;
>> +
>> + /*
>> + * The value returned in the register is the maximum of
>> + * bitflips encountered in any of the ECC regions. As there is
>> + * no way to get the number of bitflips in a specific regions
>> + * we are not able to deliver correct stats but instead
>> + * overestimate the number of corrected bitflips by assuming
>> + * that all regions where errors have been corrected
>> + * encountered the maximum number of bitflips.
>> + */
>> + mtd->ecc_stats.corrected += max_corr_cnt * hweight8(corr_sec_flag);
>> +
>> + return max_corr_cnt;
>> + }
>> +
>> +}
>> +
>> +static int tegra_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
>> + const uint8_t *buf, int oob_required, int page)
>> +{
>> + struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
>> + dma_addr_t dma_addr;
>> + u32 value, addrs;
>> + int ret, dma_len;
>> +
>> + writel(NAND_CMD_SEQIN, ctrl->regs + CMD_1);
>> + writel(NAND_CMD_PAGEPROG, ctrl->regs + CMD_2);
>> +
>> + addrs = tegra_nand_fill_address(ctrl, chip, page);
>> +
>> + dma_len = mtd->writesize + (oob_required ? mtd->oobsize : 0);
>> + dma_addr = dma_map_single(ctrl->dev, (void *)buf, dma_len, DMA_TO_DEVICE);
>> + ret = dma_mapping_error(ctrl->dev, dma_addr);
>> + if (ret) {
>> + dev_err(ctrl->dev, "dma mapping error\n");
>> + return -EINVAL;
>> + }
>> +
>> + writel(mtd->writesize - 1, ctrl->regs + DMA_CFG_A);
>> + writel(dma_addr, ctrl->regs + DATA_PTR);
>> +
>> + if (oob_required) {
>> + struct mtd_oob_region oobregion;
>> + dma_addr_t dma_addr_oob = dma_addr + mtd->writesize;
>> +
>> + mtd_ooblayout_free(mtd, 0, &oobregion);
>> +
>> + writel(oobregion.length - 1, ctrl->regs + DMA_CFG_B);
>> + writel(dma_addr_oob + oobregion.offset, ctrl->regs + TAG_PTR);
>> + } else {
>> + writel(0, ctrl->regs + DMA_CFG_B);
>> + writel(0, ctrl->regs + TAG_PTR);
>> + }
>> +
>> + value = DMA_CTRL_GO | DMA_CTRL_OUT | DMA_CTRL_PERF_EN |
>> + DMA_CTRL_IE_DONE | DMA_CTRL_IS_DONE |
>> + DMA_CTRL_BURST_16 | DMA_CTRL_EN_A;
>> + if (oob_required)
>> + value |= DMA_CTRL_EN_B;
>> + writel(value, ctrl->regs + DMA_CTRL);
>> +
>> + value = CMD_CLE | CMD_ALE | CMD_ALE_SIZE(addrs) | CMD_SEC_CMD |
>> + CMD_AFT_DAT | CMD_RBSY_CHK | CMD_GO | CMD_TX | CMD_A_VALID |
>> + CMD_TRANS_SIZE(9) | CMD_CE(ctrl->cur_chip);
>> + if (oob_required)
>> + value |= CMD_B_VALID;
>> + writel(value, ctrl->regs + CMD);
>> +
>> + wait_for_completion(&ctrl->command_complete);
>> + wait_for_completion(&ctrl->dma_complete);
>> +
>> +
>> + dma_unmap_single(ctrl->dev, dma_addr, dma_len, DMA_TO_DEVICE);
>> +
>> + return 0;
>> +}
>> +
>> +static int tegra_nand_write_page_hwecc(struct mtd_info *mtd,
>> + struct nand_chip *chip,
>> + const uint8_t *buf, int oob_required,
>> + int page)
>> +{
>> + struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
>> + int ret;
>> +
>> + tegra_nand_hw_ecc(ctrl, chip, true);
>> + ret = tegra_nand_write_page(mtd, chip, buf, oob_required, page);
>> + tegra_nand_hw_ecc(ctrl, chip, false);
>> +
>> + return ret;
>> +}
>> +
>> +static void tegra_nand_setup_timing(struct tegra_nand_controller *ctrl,
>> + const struct nand_sdr_timings *timings)
>> +{
>> + /*
>> + * The period (and all other timings in this function) is in ps,
>> + * so need to take care here to avoid integer overflows.
>> + */
>> + unsigned int rate = clk_get_rate(ctrl->clk) / 1000000;
>> + unsigned int period = DIV_ROUND_UP(1000000, rate);
>> + u32 val, reg = 0;
>> +
>> + val = DIV_ROUND_UP(max3(timings->tAR_min, timings->tRR_min,
>> + timings->tRC_min), period);
>> + if (val > 2)
>> + val -= 3;
>> + reg |= TIMING_TCR_TAR_TRR(val);
>> +
>> + val = DIV_ROUND_UP(max(max(timings->tCS_min, timings->tCH_min),
>> + max(timings->tALS_min, timings->tALH_min)),
>> + period);
>> + if (val > 1)
>> + val -= 2;
>> + reg |= TIMING_TCS(val);
>> +
>> + val = DIV_ROUND_UP(max(timings->tRP_min, timings->tREA_max) + 6000,
>> + period);
>> + reg |= TIMING_TRP(val) | TIMING_TRP_RESP(val);
>> +
>> + reg |= TIMING_TWB(DIV_ROUND_UP(timings->tWB_max, period));
>> + reg |= TIMING_TWHR(DIV_ROUND_UP(timings->tWHR_min, period));
>> + reg |= TIMING_TWH(DIV_ROUND_UP(timings->tWH_min, period));
>> + reg |= TIMING_TWP(DIV_ROUND_UP(timings->tWP_min, period));
>> + reg |= TIMING_TRH(DIV_ROUND_UP(timings->tRHW_min, period));
>> +
>> + writel(reg, ctrl->regs + TIMING_1);
>> +
>> + val = DIV_ROUND_UP(timings->tADL_min, period);
>> + if (val > 2)
>> + val -= 3;
>> + reg = TIMING_TADL(val);
>> +
>> + writel(reg, ctrl->regs + TIMING_2);
>> +}
>> +
>> +static int tegra_nand_setup_data_interface(struct mtd_info *mtd, int csline,
>> + const struct nand_data_interface *conf)
>> +{
>> + struct nand_chip *chip = mtd_to_nand(mtd);
>> + struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
>> + const struct nand_sdr_timings *timings;
>> +
>> + timings = nand_get_sdr_timings(conf);
>> + if (IS_ERR(timings))
>> + return PTR_ERR(timings);
>> +
>> + if (csline == NAND_DATA_IFACE_CHECK_ONLY)
>> + return 0;
>> +
>> + tegra_nand_setup_timing(ctrl, timings);
>> +
>> + return 0;
>> +}
>> +
>> +static int tegra_nand_chips_init(struct device *dev,
>> + struct tegra_nand_controller *ctrl)
>> +{
>> + struct device_node *np = dev->of_node;
>> + struct device_node *np_nand;
>> + int nchips = of_get_child_count(np);
>> + struct tegra_nand_chip *nand;
>> + struct mtd_info *mtd;
>> + struct nand_chip *chip;
>> + unsigned long config, bch_config = 0;
>> + int bits_per_step;
>> + int err;
>> +
>> + if (nchips != 1) {
>> + dev_err(dev, "currently only one NAND chip supported\n");
>> + return -EINVAL;
>> + }
>> +
>> + np_nand = of_get_next_child(np, NULL);
>> +
>> + nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
>> + if (!nand) {
>> + dev_err(dev, "could not allocate chip structure\n");
>> + return -ENOMEM;
>> + }
>> +
>> + nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
>> +
>> + if (IS_ERR(nand->wp_gpio)) {
>> + err = PTR_ERR(nand->wp_gpio);
>> + dev_err(dev, "failed to request WP GPIO: %d\n", err);
>> + return err;
>> + }
>> +
>> + chip = &nand->chip;
>> + chip->controller = &ctrl->controller;
>> + ctrl->chip = chip;
>> +
>> + mtd = nand_to_mtd(chip);
>> +
>> + mtd->dev.parent = dev;
>> + mtd->name = "tegra_nand";
>> + mtd->owner = THIS_MODULE;
>> +
>> + nand_set_flash_node(chip, np_nand);
>> +
>> + chip->options = NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;
>> + chip->exec_op = tegra_nand_exec_op;
>> + chip->select_chip = tegra_nand_select_chip;
>> + chip->setup_data_interface = tegra_nand_setup_data_interface;
>> +
>> + err = nand_scan_ident(mtd, 1, NULL);
>> + if (err)
>> + return err;
>> +
>> + if (chip->bbt_options & NAND_BBT_USE_FLASH)
>> + chip->bbt_options |= NAND_BBT_NO_OOB;
>> +
>> + chip->ecc.mode = NAND_ECC_HW;
>> + if (!chip->ecc.size)
>> + chip->ecc.size = 512;
>> + if (chip->ecc.size != 512)
>> + return -EINVAL;
>> +
>> + chip->ecc.read_page = tegra_nand_read_page_hwecc;
>> + chip->ecc.write_page = tegra_nand_write_page_hwecc;
>> + /* Not functional for unknown reason...
>> + chip->ecc.read_page_raw = tegra_nand_read_page;
>> + chip->ecc.write_page_raw = tegra_nand_write_page;
>> + */
>> + config = readl(ctrl->regs + CFG);
>> + config |= CFG_PIPE_EN | CFG_SKIP_SPARE | CFG_SKIP_SPARE_SIZE_4;
>> +
>> + if (chip->options & NAND_BUSWIDTH_16)
>> + config |= CFG_BUS_WIDTH_16;
>> +
>> + switch (chip->ecc.algo) {
>> + case NAND_ECC_RS:
>> + bits_per_step = BITS_PER_STEP_RS * chip->ecc.strength;
>> + mtd_set_ooblayout(mtd, &tegra_nand_oob_rs_ops);
>> + switch (chip->ecc.strength) {
>> + case 4:
>> + config |= CFG_ECC_SEL | CFG_TVAL_4;
>> + break;
>> + case 6:
>> + config |= CFG_ECC_SEL | CFG_TVAL_6;
>> + break;
>> + case 8:
>> + config |= CFG_ECC_SEL | CFG_TVAL_8;
>> + break;
>> + default:
>> + dev_err(dev, "ECC strength %d not supported\n",
>> + chip->ecc.strength);
>> + return -EINVAL;
>> + }
>> + break;
>> + case NAND_ECC_BCH:
>> + bits_per_step = BITS_PER_STEP_BCH * chip->ecc.strength;
>> + mtd_set_ooblayout(mtd, &tegra_nand_oob_bch_ops);
>> + switch (chip->ecc.strength) {
>> + case 4:
>> + bch_config = BCH_TVAL_4;
>> + break;
>> + case 8:
>> + bch_config = BCH_TVAL_8;
>> + break;
>> + case 14:
>> + bch_config = BCH_TVAL_14;
>> + break;
>> + case 16:
>> + bch_config = BCH_TVAL_16;
>> + break;
>> + default:
>> + dev_err(dev, "ECC strength %d not supported\n",
>> + chip->ecc.strength);
>> + return -EINVAL;
>> + }
>> + break;
>> + default:
>> + dev_err(dev, "ECC algorithm not supported\n");
>> + return -EINVAL;
>> + }
>> +
>> + chip->ecc.bytes = DIV_ROUND_UP(bits_per_step, 8);
>> +
>> + switch (mtd->writesize) {
>> + case 256:
>> + config |= CFG_PS_256;
>> + break;
>> + case 512:
>> + config |= CFG_PS_512;
>> + break;
>> + case 1024:
>> + config |= CFG_PS_1024;
>> + break;
>> + case 2048:
>> + config |= CFG_PS_2048;
>> + break;
>> + case 4096:
>> + config |= CFG_PS_4096;
>> + break;
>> + default:
>> + dev_err(dev, "unhandled writesize %d\n", mtd->writesize);
>> + return -ENODEV;
>> + }
>> +
>> + writel(config, ctrl->regs + CFG);
>> + writel(bch_config, ctrl->regs + BCH_CONFIG);
>> +
>> + err = nand_scan_tail(mtd);
>> + if (err)
>> + return err;
>> +
>> + config |= CFG_TAG_BYTE_SIZE(mtd_ooblayout_count_freebytes(mtd) - 1);
>> + writel(config, ctrl->regs + CFG);
>> +
>> + err = mtd_device_register(mtd, NULL, 0);
>> + if (err)
>> + return err;
>> +
>> + return 0;
>> +}
>> +
>> +static int tegra_nand_probe(struct platform_device *pdev)
>> +{
>> + struct reset_control *rst;
>> + struct tegra_nand_controller *ctrl;
>> + struct resource *res;
>> + unsigned long value;
>> + int irq, err = 0;
>> +
>> + ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
>> + if (!ctrl)
>> + return -ENOMEM;
>> +
>> + ctrl->dev = &pdev->dev;
>> + nand_hw_control_init(&ctrl->controller);
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + ctrl->regs = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(ctrl->regs))
>> + return PTR_ERR(ctrl->regs);
>> +
>> + rst = devm_reset_control_get(&pdev->dev, "nand");
>> + if (IS_ERR(rst))
>> + return PTR_ERR(rst);
>> +
>> + ctrl->clk = devm_clk_get(&pdev->dev, "nand");
>> + if (IS_ERR(ctrl->clk))
>> + return PTR_ERR(ctrl->clk);
>> +
>> + err = clk_prepare_enable(ctrl->clk);
>> + if (err)
>> + return err;
>> +
>> + reset_control_reset(rst);
>
> Technically reset_control_reset() could fail, so this should be:
>
> err = reset_control_reset(rst);
> if (err)
> goto err_disable_clk;
>
Ok.
--
Stefan
>> +
>> + value = HWSTATUS_RDSTATUS_MASK(1) | HWSTATUS_RDSTATUS_VALUE(0) |
>> + HWSTATUS_RBSY_MASK(NAND_STATUS_READY) |
>> + HWSTATUS_RBSY_VALUE(NAND_STATUS_READY);
>> + writel(NAND_CMD_STATUS, ctrl->regs + HWSTATUS_CMD);
>> + writel(value, ctrl->regs + HWSTATUS_MASK);
>> +
>> + init_completion(&ctrl->command_complete);
>> + init_completion(&ctrl->dma_complete);
>> +
>> + /* clear interrupts */
>> + value = readl(ctrl->regs + ISR);
>> + writel(value, ctrl->regs + ISR);
>> +
>> + irq = platform_get_irq(pdev, 0);
>> + err = devm_request_irq(&pdev->dev, irq, tegra_nand_irq, 0,
>> + dev_name(&pdev->dev), ctrl);
>> + if (err)
>> + goto err_disable_clk;
>> +
>> + writel(DMA_CTRL_IS_DONE, ctrl->regs + DMA_CTRL);
>> +
>> + /* enable interrupts */
>> + value = IER_UND | IER_OVR | IER_CMD_DONE | IER_ECC_ERR | IER_GIE;
>> + writel(value, ctrl->regs + IER);
>> +
>> + /* reset config */
>> + writel(0, ctrl->regs + CFG);
>> +
>> + err = tegra_nand_chips_init(ctrl->dev, ctrl);
>> + if (err)
>> + goto err_disable_clk;
>> +
>> + platform_set_drvdata(pdev, ctrl);
>> +
>> + return 0;
>> +
>> +err_disable_clk:
>> + clk_disable_unprepare(ctrl->clk);
>> + return err;
>> +}
>> +
>> +static int tegra_nand_remove(struct platform_device *pdev)
>> +{
>> + struct tegra_nand_controller *ctrl = platform_get_drvdata(pdev);
>> +
>> + nand_release(nand_to_mtd(ctrl->chip));
>> +
>> + clk_disable_unprepare(ctrl->clk);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id tegra_nand_of_match[] = {
>> + { .compatible = "nvidia,tegra20-nand" },
>> + { /* sentinel */ }
>> +};
>> +
>> +static struct platform_driver tegra_nand_driver = {
>> + .driver = {
>> + .name = "tegra-nand",
>> + .of_match_table = tegra_nand_of_match,
>> + },
>> + .probe = tegra_nand_probe,
>> + .remove = tegra_nand_remove,
>> +};
>> +module_platform_driver(tegra_nand_driver);
>> +
>> +MODULE_DESCRIPTION("NVIDIA Tegra NAND driver");
>> +MODULE_AUTHOR("Thierry Reding <thierry.reding@nvidia.com>");
>> +MODULE_AUTHOR("Lucas Stach <dev@lynxeye.de>");
>> +MODULE_AUTHOR("Stefan Agner <stefan@agner.ch>");
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_DEVICE_TABLE(of, tegra_nand_of_match);
>>
^ permalink raw reply
* Re: [PATCH v2 3/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver
From: Stefan Agner @ 2018-05-28 12:41 UTC (permalink / raw)
To: Miquel Raynal
Cc: boris.brezillon, dwmw2, computersforpeace, marek.vasut, robh+dt,
mark.rutland, thierry.reding, mturquette, sboyd, dev, richard,
marcel, krzk, digetx, benjamin.lindqvist, jonathanh, pdeschrijver,
pgaikwad, mirza.krak, linux-mtd, linux-tegra, devicetree,
linux-kernel, linux-clk
In-Reply-To: <20180528001940.7f54caff@xps13>
On 28.05.2018 00:19, Miquel Raynal wrote:
> Hi Stefan,
>
> A few more comments here.
>
> On Sun, 27 May 2018 23:54:39 +0200, Stefan Agner <stefan@agner.ch>
> wrote:
>
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode. Page read/writes with hardware ECC make
>> use of the DMA for data transfer.
>>
>> Signed-off-by: Lucas Stach <dev@lynxeye.de>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
>> ---
>> MAINTAINERS | 7 +
>> drivers/mtd/nand/raw/Kconfig | 6 +
>> drivers/mtd/nand/raw/Makefile | 1 +
>> drivers/mtd/nand/raw/tegra_nand.c | 999 ++++++++++++++++++++++++++++++
>> 4 files changed, 1013 insertions(+)
>> create mode 100644 drivers/mtd/nand/raw/tegra_nand.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 58b9861ccf99..8cbbb7111742 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -13844,6 +13844,13 @@ M: Laxman Dewangan <ldewangan@nvidia.com>
>> S: Supported
>> F: drivers/input/keyboard/tegra-kbc.c
>>
>> +TEGRA NAND DRIVER
>> +M: Stefan Agner <stefan@agner.ch>
>> +M: Lucas Stach <dev@lynxeye.de>
>> +S: Maintained
>> +F: Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt
>
> I think most MTD bindings use '-' instead of ','. I don't have a
> preference, it's just for coherence.
>
Sure, will use a dash.
>> +F: drivers/mtd/nand/raw/tegra_nand.c
>> +
>> TEGRA PWM DRIVER
>> M: Thierry Reding <thierry.reding@gmail.com>
>> S: Supported
>> diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
>> index 19a2b283fbbe..012c63c6ab47 100644
>> --- a/drivers/mtd/nand/raw/Kconfig
>> +++ b/drivers/mtd/nand/raw/Kconfig
>> @@ -534,4 +534,10 @@ config MTD_NAND_MTK
>> Enables support for NAND controller on MTK SoCs.
>> This controller is found on mt27xx, mt81xx, mt65xx SoCs.
>>
>> +config MTD_NAND_TEGRA
>> + tristate "Support for NAND on NVIDIA Tegra"
>> + depends on ARCH_TEGRA || COMPILE_TEST
>> + help
>> + Enables support for NAND flash on NVIDIA Tegra SoC based boards.
>
> Please make the term "controller" appear because it's mostly a
> controller driver that you're adding.
>
Ok.
>> +
>> endif # MTD_NAND
>> diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
>> index 165b7ef9e9a1..d5a5f9832b88 100644
>> --- a/drivers/mtd/nand/raw/Makefile
>> +++ b/drivers/mtd/nand/raw/Makefile
>> @@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
>> obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
>> obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
>> obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o
>> +obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o
>>
>> nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
>> nand-objs += nand_amd.o
>
> [...]
>
>> +static int tegra_nand_setup_data_interface(struct mtd_info *mtd, int csline,
>> + const struct nand_data_interface *conf)
>> +{
>> + struct nand_chip *chip = mtd_to_nand(mtd);
>> + struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
>> + const struct nand_sdr_timings *timings;
>> +
>> + timings = nand_get_sdr_timings(conf);
>> + if (IS_ERR(timings))
>> + return PTR_ERR(timings);
>> +
>> + if (csline == NAND_DATA_IFACE_CHECK_ONLY)
>> + return 0;
>> +
>> + tegra_nand_setup_timing(ctrl, timings);
>
> Is this indirection really needed?
>
This evolved due to historic reasons, will get rid of it.
>> +
>> + return 0;
>> +}
>> +
>> +static int tegra_nand_chips_init(struct device *dev,
>> + struct tegra_nand_controller *ctrl)
>> +{
>> + struct device_node *np = dev->of_node;
>> + struct device_node *np_nand;
>> + int nchips = of_get_child_count(np);
>> + struct tegra_nand_chip *nand;
>> + struct mtd_info *mtd;
>> + struct nand_chip *chip;
>> + unsigned long config, bch_config = 0;
>> + int bits_per_step;
>> + int err;
>> +
>> + if (nchips != 1) {
>> + dev_err(dev, "currently only one NAND chip supported\n");
>> + return -EINVAL;
>> + }
>> +
>> + np_nand = of_get_next_child(np, NULL);
>> +
>> + nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
>> + if (!nand) {
>> + dev_err(dev, "could not allocate chip structure\n");
>> + return -ENOMEM;
>> + }
>> +
>> + nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
>> +
>> + if (IS_ERR(nand->wp_gpio)) {
>> + err = PTR_ERR(nand->wp_gpio);
>> + dev_err(dev, "failed to request WP GPIO: %d\n", err);
>> + return err;
>> + }
>> +
>> + chip = &nand->chip;
>> + chip->controller = &ctrl->controller;
>> + ctrl->chip = chip;
>> +
>> + mtd = nand_to_mtd(chip);
>> +
>> + mtd->dev.parent = dev;
>> + mtd->name = "tegra_nand";
>> + mtd->owner = THIS_MODULE;
>> +
>> + nand_set_flash_node(chip, np_nand);
>> +
>> + chip->options = NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;
>> + chip->exec_op = tegra_nand_exec_op;
>> + chip->select_chip = tegra_nand_select_chip;
>> + chip->setup_data_interface = tegra_nand_setup_data_interface;
>> +
>> + err = nand_scan_ident(mtd, 1, NULL);
>> + if (err)
>> + return err;
>> +
>> + if (chip->bbt_options & NAND_BBT_USE_FLASH)
>> + chip->bbt_options |= NAND_BBT_NO_OOB;
>> +
>> + chip->ecc.mode = NAND_ECC_HW;
>> + if (!chip->ecc.size)
>> + chip->ecc.size = 512;
>> + if (chip->ecc.size != 512)
>> + return -EINVAL;
>
> This is useless. You can force ecc.size to 512 and forget about the DT
> property (please update the DT bindings).
>
Ok.
>> +
>> + chip->ecc.read_page = tegra_nand_read_page_hwecc;
>> + chip->ecc.write_page = tegra_nand_write_page_hwecc;
>> + /* Not functional for unknown reason...
>> + chip->ecc.read_page_raw = tegra_nand_read_page;
>> + chip->ecc.write_page_raw = tegra_nand_write_page;
>
> Please add the _raw suffix to these helpers.
>
They are also used from tegra_nand_read_page_hwecc, that is why I was
hesitant to add _raw...
>> + */
>> + config = readl(ctrl->regs + CFG);
>> + config |= CFG_PIPE_EN | CFG_SKIP_SPARE | CFG_SKIP_SPARE_SIZE_4;
>> +
>> + if (chip->options & NAND_BUSWIDTH_16)
>> + config |= CFG_BUS_WIDTH_16;
>> +
>> + switch (chip->ecc.algo) {
>> + case NAND_ECC_RS:
>> + bits_per_step = BITS_PER_STEP_RS * chip->ecc.strength;
>> + mtd_set_ooblayout(mtd, &tegra_nand_oob_rs_ops);
>> + switch (chip->ecc.strength) {
>> + case 4:
>> + config |= CFG_ECC_SEL | CFG_TVAL_4;
>> + break;
>> + case 6:
>> + config |= CFG_ECC_SEL | CFG_TVAL_6;
>> + break;
>> + case 8:
>> + config |= CFG_ECC_SEL | CFG_TVAL_8;
>> + break;
>> + default:
>> + dev_err(dev, "ECC strength %d not supported\n",
>> + chip->ecc.strength);
>> + return -EINVAL;
>> + }
>> + break;
>> + case NAND_ECC_BCH:
>> + bits_per_step = BITS_PER_STEP_BCH * chip->ecc.strength;
>> + mtd_set_ooblayout(mtd, &tegra_nand_oob_bch_ops);
>> + switch (chip->ecc.strength) {
>> + case 4:
>> + bch_config = BCH_TVAL_4;
>> + break;
>> + case 8:
>> + bch_config = BCH_TVAL_8;
>> + break;
>> + case 14:
>> + bch_config = BCH_TVAL_14;
>> + break;
>> + case 16:
>> + bch_config = BCH_TVAL_16;
>> + break;
>> + default:
>> + dev_err(dev, "ECC strength %d not supported\n",
>> + chip->ecc.strength);
>> + return -EINVAL;
>> + }
>> + break;
>> + default:
>> + dev_err(dev, "ECC algorithm not supported\n");
>> + return -EINVAL;
>> + }
>> +
>> + chip->ecc.bytes = DIV_ROUND_UP(bits_per_step, 8);
>> +
>> + switch (mtd->writesize) {
>> + case 256:
>> + config |= CFG_PS_256;
>> + break;
>> + case 512:
>> + config |= CFG_PS_512;
>> + break;
>> + case 1024:
>> + config |= CFG_PS_1024;
>> + break;
>> + case 2048:
>> + config |= CFG_PS_2048;
>> + break;
>> + case 4096:
>> + config |= CFG_PS_4096;
>> + break;
>> + default:
>> + dev_err(dev, "unhandled writesize %d\n", mtd->writesize);
>> + return -ENODEV;
>> + }
>> +
>> + writel(config, ctrl->regs + CFG);
>> + writel(bch_config, ctrl->regs + BCH_CONFIG);
>> +
>> + err = nand_scan_tail(mtd);
>> + if (err)
>> + return err;
>> +
>> + config |= CFG_TAG_BYTE_SIZE(mtd_ooblayout_count_freebytes(mtd) - 1);
>> + writel(config, ctrl->regs + CFG);
>> +
>> + err = mtd_device_register(mtd, NULL, 0);
>> + if (err)
>
> Missing nand_cleanup() in the error path.
>
Ok.
--
Stefan
>> + return err;
>> +
>> + return 0;
>> +}
>> +
>
> [...]
^ permalink raw reply
* Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver
From: Stefan Agner @ 2018-05-28 12:39 UTC (permalink / raw)
To: Miquel Raynal
Cc: boris.brezillon, dwmw2, computersforpeace, marek.vasut, robh+dt,
mark.rutland, thierry.reding, mturquette, sboyd, dev, richard,
marcel, krzk, digetx, benjamin.lindqvist, jonathanh, pdeschrijver,
pgaikwad, mirza.krak, linux-mtd, linux-tegra, devicetree,
linux-kernel, linux-clk
In-Reply-To: <20180528000422.7f18dc5f@xps13>
On 28.05.2018 00:04, Miquel Raynal wrote:
> Hi Stefan,
>
> I just see your v2 while I'm sending my review on the driver, will
> probably wait for v4 then ;)
Hehe, yeah lets hope we do not race on v3 :-)
Some comments to things which are not addressed yet in v2:
>
> Thanks for the work though!
> Miquèl
>
> On Tue, 22 May 2018 14:07:06 +0200, Stefan Agner <stefan@agner.ch>
> wrote:
>
>> Add support for the NAND flash controller found on NVIDIA
>> Tegra 2 SoCs. This implementation does not make use of the
>> command queue feature. Regular operations/data transfers are
>> done in PIO mode. Page read/writes with hardware ECC make
>> use of the DMA for data transfer.
>>
>> Signed-off-by: Lucas Stach <dev@lynxeye.de>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
>> ---
>
> [...]
>
>> --- /dev/null
>> +++ b/drivers/mtd/nand/raw/tegra_nand.c
>> @@ -0,0 +1,915 @@
>> +/*
>> + * Copyright (C) 2018 Stefan Agner <stefan@agner.ch>
>> + * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
>> + * Copyright (C) 2012 Avionic Design GmbH
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>
> Please use SPDX tag.
>
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/completion.h>
>> +#include <linux/delay.h>
>> +#include <linux/dma-mapping.h>
>> +#include <linux/err.h>
>> +#include <linux/gpio/consumer.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/io.h>
>> +#include <linux/module.h>
>> +#include <linux/mtd/partitions.h>
>> +#include <linux/mtd/rawnand.h>
>> +#include <linux/of.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/reset.h>
>> +
>> +#define CMD 0x00
>> +#define CMD_GO (1 << 31)
>> +#define CMD_CLE (1 << 30)
>> +#define CMD_ALE (1 << 29)
>> +#define CMD_PIO (1 << 28)
>> +#define CMD_TX (1 << 27)
>> +#define CMD_RX (1 << 26)
>
> Please use the BIT(x) macro instead of (1 << x)
>
Ok.
>> +#define CMD_SEC_CMD (1 << 25)
>> +#define CMD_AFT_DAT (1 << 24)
>> +#define CMD_TRANS_SIZE(x) (((x - 1) & 0xf) << 20)
>> +#define CMD_A_VALID (1 << 19)
>> +#define CMD_B_VALID (1 << 18)
>> +#define CMD_RD_STATUS_CHK (1 << 17)
>> +#define CMD_RBSY_CHK (1 << 16)
>> +#define CMD_CE(x) (1 << (8 + ((x) & 0x7)))
>> +#define CMD_CLE_SIZE(x) (((x - 1) & 0x3) << 4)
>> +#define CMD_ALE_SIZE(x) (((x - 1) & 0xf) << 0)
>> +
>
> [...]
>
>> +static int tegra_nand_cmd(struct nand_chip *chip,
>> + const struct nand_subop *subop)
>> +{
>> + const struct nand_op_instr *instr;
>> + const struct nand_op_instr *instr_data_in = NULL;
>> + struct mtd_info *mtd = nand_to_mtd(chip);
>> + struct tegra_nand *nand = to_tegra_nand(mtd);
>> + unsigned int op_id = -1, trfr_in_sz = 0, trfr_out_sz = 0, offset = 0;
>> + bool first_cmd = true;
>> + bool force8bit;
>> + u32 cmd = 0;
>> + u32 value;
>> +
>> + for (op_id = 0; op_id < subop->ninstrs; op_id++) {
>> + unsigned int naddrs, i;
>> + const u8 *addrs;
>> + u32 addr1 = 0, addr2 = 0;
>> +
>> + instr = &subop->instrs[op_id];
>> +
>> + switch (instr->type) {
>> + case NAND_OP_CMD_INSTR:
>> + if (first_cmd) {
>> + cmd |= CMD_CLE;
>> + writel(instr->ctx.cmd.opcode, nand->regs + CMD_1);
>> + } else {
>> + cmd |= CMD_SEC_CMD;
>> + writel(instr->ctx.cmd.opcode, nand->regs + CMD_2);
>> + }
>> + first_cmd = false;
>> + break;
>> + case NAND_OP_ADDR_INSTR:
>> + offset = nand_subop_get_addr_start_off(subop, op_id);
>> + naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
>> + addrs = &instr->ctx.addr.addrs[offset];
>> +
>> + cmd |= CMD_ALE | CMD_ALE_SIZE(naddrs);
>> + for (i = 0; i < min_t(unsigned int, 4, naddrs); i++)
>> + addr1 |= *addrs++ << (8 * i);
>> + naddrs -= i;
>> + for (i = 0; i < min_t(unsigned int, 4, naddrs); i++)
>> + addr2 |= *addrs++ << (8 * i);
>> + writel(addr1, nand->regs + ADDR_1);
>> + writel(addr2, nand->regs + ADDR_2);
>> + break;
>> +
>> + case NAND_OP_DATA_IN_INSTR:
>> + trfr_in_sz = nand_subop_get_data_len(subop, op_id);
>> + offset = nand_subop_get_data_start_off(subop, op_id);
>> +
>> + cmd |= CMD_TRANS_SIZE(trfr_in_sz) | CMD_PIO | CMD_RX | CMD_A_VALID;
>> +
>> + instr_data_in = instr;
>> + break;
>> +
>> + case NAND_OP_DATA_OUT_INSTR:
>> + trfr_out_sz = nand_subop_get_data_len(subop, op_id);
>> + offset = nand_subop_get_data_start_off(subop, op_id);
>> + trfr_out_sz = min_t(size_t, trfr_out_sz, 4);
>> +
>> + cmd |= CMD_TRANS_SIZE(trfr_out_sz) | CMD_PIO | CMD_TX | CMD_A_VALID;
>> +
>> + memcpy(&value, instr->ctx.data.buf.out + offset, trfr_out_sz);
>> + writel(value, nand->regs + RESP);
>> +
>> + break;
>> + case NAND_OP_WAITRDY_INSTR:
>> + cmd |= CMD_RBSY_CHK;
>> + break;
>> +
>> + }
>> + }
>> +
>> +
>> + cmd |= CMD_GO | CMD_CE(nand->cur_chip);
>> + writel(cmd, nand->regs + CMD);
>> + wait_for_completion(&nand->command_complete);
>
> _timeout?
>
Yes, I definitely will do this. One half a second should be fine?
>> +
>> + if (instr_data_in) {
>> + u32 value;
>> + size_t n = min_t(size_t, trfr_in_sz, 4);
>> +
>> + value = readl(nand->regs + RESP);
>> + memcpy(instr_data_in->ctx.data.buf.in + offset, &value, n);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static const struct nand_op_parser tegra_nand_op_parser = NAND_OP_PARSER(
>> + NAND_OP_PARSER_PATTERN(tegra_nand_cmd,
>> + NAND_OP_PARSER_PAT_CMD_ELEM(true),
>> + NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8),
>> + NAND_OP_PARSER_PAT_CMD_ELEM(true),
>> + NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
>> + NAND_OP_PARSER_PATTERN(tegra_nand_cmd,
>> + NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, 4)),
>> + NAND_OP_PARSER_PATTERN(tegra_nand_cmd,
>> + NAND_OP_PARSER_PAT_CMD_ELEM(true),
>> + NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8),
>> + NAND_OP_PARSER_PAT_CMD_ELEM(true),
>> + NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
>> + NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, 4)),
>> + );
>> +
>> +static int tegra_nand_exec_op(struct nand_chip *chip,
>> + const struct nand_operation *op,
>> + bool check_only)
>> +{
>> + return nand_op_parser_exec_op(chip, &tegra_nand_op_parser, op,
>> + check_only);
>> +}
>> +static void tegra_nand_select_chip(struct mtd_info *mtd, int chip)
>> +{
>> + struct tegra_nand *nand = to_tegra_nand(mtd);
>> +
>> + nand->cur_chip = chip;
>
> You should probably save the timings configuration and apply them back
> here in case of using different chips.
>
So far multiple chips are not supported, but yes, would need to be done
in that case.
>> +}
>> +
>> +static u32 tegra_nand_fill_address(struct mtd_info *mtd, struct nand_chip *chip,
>> + int page)
>> +{
>> + struct tegra_nand *nand = to_tegra_nand(mtd);
>> +
>> + /* Lower 16-bits are column, always 0 */
>> + writel(page << 16, nand->regs + ADDR_1);
>> +
>> + if (chip->options & NAND_ROW_ADDR_3) {
>> + writel(page >> 16, nand->regs + ADDR_2);
>> + return 5;
>> + }
>> +
>> + return 4;
>> +}
>> +
>> +static int tegra_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
>> + uint8_t *buf, int oob_required, int page)
>> +{
>> + struct tegra_nand *nand = to_tegra_nand(mtd);
>> + u32 value, addrs;
>> +
>> + writel(NAND_CMD_READ0, nand->regs + CMD_1);
>> + writel(NAND_CMD_READSTART, nand->regs + CMD_2);
>> +
>> + addrs = tegra_nand_fill_address(mtd, chip, page);
>> +
>> + value = readl(nand->regs + CFG);
>> + value |= CFG_HW_ECC | CFG_ERR_COR;
>> + writel(value, nand->regs + CFG);
>> +
>> + writel(mtd->writesize - 1, nand->regs + DMA_CFG_A);
>> + writel(nand->data_dma, nand->regs + DATA_PTR);
>> +
>> + if (oob_required) {
>> + writel(mtd_ooblayout_count_freebytes(mtd) - 1,
>> + nand->regs + DMA_CFG_B);
>> + writel(nand->oob_dma, nand->regs + TAG_PTR);
>> + } else {
>> + writel(0, nand->regs + DMA_CFG_B);
>> + writel(0, nand->regs + TAG_PTR);
>> + }
>> +
>> + value = DMA_CTRL_GO | DMA_CTRL_IN | DMA_CTRL_PERF_EN |
>> + DMA_CTRL_REUSE | DMA_CTRL_IE_DONE | DMA_CTRL_IS_DONE |
>> + DMA_CTRL_BURST_8 | DMA_CTRL_EN_A;
>> + if (oob_required)
>> + value |= DMA_CTRL_EN_B;
>> + writel(value, nand->regs + DMA_CTRL);
>> +
>> + value = CMD_CLE | CMD_ALE | CMD_ALE_SIZE(addrs) | CMD_SEC_CMD |
>> + CMD_RBSY_CHK | CMD_GO | CMD_RX | CMD_TRANS_SIZE(9) |
>> + CMD_A_VALID | CMD_CE(nand->cur_chip);
>> + if (oob_required)
>> + value |= CMD_B_VALID;
>> + writel(value, nand->regs + CMD);
>> +
>> + wait_for_completion(&nand->command_complete);
>> + wait_for_completion(&nand->dma_complete);
>> +
>> + if (oob_required) {
>> + struct mtd_oob_region oobregion;
>> +
>> + mtd_ooblayout_free(mtd, 0, &oobregion);
>
> Don't you want to save the oobregion parameters once and then just
> refer to them?
>
I probably could just safe the size of the free OOB region.
Anyway have some open questions wrt OOB support with HW ECC, see cover
letter of v2.
>> + memcpy(chip->oob_poi, nand->oob_buf + oobregion.offset,
>> + mtd_ooblayout_count_freebytes(mtd));
>> + }
>> + memcpy(buf, nand->data_buf, mtd->writesize);
>> +
>> + value = readl(nand->regs + CFG);
>> + value &= ~(CFG_HW_ECC | CFG_ERR_COR);
>> + writel(value, nand->regs + CFG);
>> +
>> + value = readl(nand->regs + DEC_STATUS);
>> + if (value & DEC_STATUS_A_ECC_FAIL) {
>> + /*
>> + * The ECC isn't smart enough to figure out if a page is
>> + * completely erased and flags an error in this case. So we
>> + * check the read data here to figure out if it's a legitimate
>> + * error or a false positive.
>> + */
>> + int i, err;
>> + int flips_threshold = chip->ecc.strength / 2;
>> + int max_bitflips = 0;
>> +
>> + for (i = 0; i < chip->ecc.steps; i++) {
>> + u8 *data = buf + (chip->ecc.size * i);
>> + err = nand_check_erased_ecc_chunk(data, chip->ecc.size,
>
> Are you sure the data was uncorrected there? I bet you have corrected
> data in chip->ecc.size and should re-read the page with the raw
> helpers before using nand_check_erased_ecc_chunk().
>
Hm, quite likely. Will check that.
>> + NULL, 0,
>> + NULL, 0,
>> + flips_threshold);
>
> I think you should use chip->ecc.strength instead of flips_threshold
> (and remove it).
>
Hm, so higher level will check and relocate if we get closer to
correctable bits?
Probably wrong in drivers/mtd/nand/raw/vf610_nfc.c then too?
>> + if (err < 0)
>> + return err;
>
> In case of ECC failure you should increment ecc_stats.failed.
>
>> +
>> + max_bitflips += max_bitflips;
>
> max_bitflipts = max_t(unsigned int, max_bitflipts, err);
>
>> + }
>> +
>> + return max_bitflips;
>> + }
>> +
>> + if (nand->last_read_error) {
>> + int max_corr_cnt, corr_sec_flag;
>> +
>> + value = readl(nand->regs + DEC_STAT_BUF);
>> + corr_sec_flag = (value & DEC_STAT_BUF_CORR_SEC_FLAG_MASK) >>
>> + DEC_STAT_BUF_CORR_SEC_FLAG_SHIFT;
>> + max_corr_cnt = (value & DEC_STAT_BUF_MAX_CORR_CNT_MASK) >>
>> + DEC_STAT_BUF_MAX_CORR_CNT_SHIFT;
>> +
>> + /*
>> + * The value returned in the register is the maximum of
>> + * bitflips encountered in any of the ECC regions. As there is
>> + * no way to get the number of bitflips in a specific regions
>> + * we are not able to deliver correct stats but instead
>> + * overestimate the number of corrected bitflips by assuming
>> + * that all regions where errors have been corrected
>> + * encountered the maximum number of bitflips.
>> + */
>> + mtd->ecc_stats.corrected += max_corr_cnt * hweight8(corr_sec_flag);
>
> That's bad. But okay if we don't have the information.
>
>> + nand->last_read_error = false;
>> + return value;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int tegra_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
>> + const uint8_t *buf, int oob_required, int page)
>> +{
>> + struct tegra_nand *nand = to_tegra_nand(mtd);
>> + u32 value, addrs;
>> +
>> + writel(NAND_CMD_SEQIN, nand->regs + CMD_1);
>> + writel(NAND_CMD_PAGEPROG, nand->regs + CMD_2);
>> +
>> + addrs = tegra_nand_fill_address(mtd, chip, page);
>> +
>> + value = readl(nand->regs + CFG);
>> + value |= CFG_HW_ECC | CFG_ERR_COR;
>> + writel(value, nand->regs + CFG);
>
> You might want to test with the _relaxed() operators?
>
>> +
>> + memcpy(nand->data_buf, buf, mtd->writesize);
>> +
>> + writel(mtd->writesize - 1, nand->regs + DMA_CFG_A);
>> + writel(nand->data_dma, nand->regs + DATA_PTR);
>> +
>> + if (oob_required) {
>> + struct mtd_oob_region oobregion;
>> +
>> + mtd_ooblayout_free(mtd, 0, &oobregion);
>> + memcpy(nand->oob_buf, chip->oob_poi + oobregion.offset,
>> + mtd_ooblayout_count_freebytes(mtd));
>> + writel(mtd_ooblayout_count_freebytes(mtd) - 1,
>> + nand->regs + DMA_CFG_B);
>> + writel(nand->oob_dma, nand->regs + TAG_PTR);
>> + } else {
>> + writel(0, nand->regs + DMA_CFG_B);
>> + writel(0, nand->regs + TAG_PTR);
>> + }
>> +
>> + value = DMA_CTRL_GO | DMA_CTRL_OUT | DMA_CTRL_PERF_EN |
>> + DMA_CTRL_IE_DONE | DMA_CTRL_IS_DONE |
>> + DMA_CTRL_BURST_8 | DMA_CTRL_EN_A;
>> + if (oob_required)
>> + value |= DMA_CTRL_EN_B;
>
> Line here
>
>> + writel(value, nand->regs + DMA_CTRL);
>> +
>> + value = CMD_CLE | CMD_ALE | CMD_ALE_SIZE(addrs) | CMD_SEC_CMD |
>> + CMD_AFT_DAT | CMD_RBSY_CHK | CMD_GO | CMD_TX | CMD_A_VALID |
>> + CMD_TRANS_SIZE(9) | CMD_CE(nand->cur_chip);
>> + if (oob_required)
>> + value |= CMD_B_VALID;
>
> Line here
>
>> + writel(value, nand->regs + CMD);
>> +
>> + wait_for_completion(&nand->command_complete);
>> + wait_for_completion(&nand->dma_complete);
>> +
>> + value = readl(nand->regs + CFG);
>> + value &= ~(CFG_HW_ECC | CFG_ERR_COR);
>> + writel(value, nand->regs + CFG);
>> +
>> + return 0;
>> +}
>> +
>> +static void tegra_nand_setup_timing(struct tegra_nand *nand, int mode)
>> +{
>> + /*
>> + * The period (and all other timings in this function) is in ps,
>> + * so need to take care here to avoid integer overflows.
>
> You might wanna check __DIVIDE, PSEC_TO_NSEC and PSEC_TO_MSEC macros in
> rawnand.h. You could use them in the following derivations.
>
>> + */
>> + unsigned int rate = clk_get_rate(nand->clk) / 1000000;
>> + unsigned int period = DIV_ROUND_UP(1000000, rate);
>> + const struct nand_sdr_timings *timings;
>> + u32 val, reg = 0;
>> +
>> + timings = onfi_async_timing_mode_to_sdr_timings(mode);
>> +
>> + val = DIV_ROUND_UP(max3(timings->tAR_min, timings->tRR_min,
>> + timings->tRC_min), period);
>> + if (val > 2)
>> + val -= 3;
>> + reg |= TIMING_TCR_TAR_TRR(val);
>> +
>> + val = DIV_ROUND_UP(max(max(timings->tCS_min, timings->tCH_min),
>> + max(timings->tALS_min, timings->tALH_min)),
>
> Is the second line aligned correctly?
>
>> + period);
>> + if (val > 1)
>> + val -= 2;
>
> This is weird and I would recommend a comment.
>
>> + reg |= TIMING_TCS(val);
>> +
>> + val = DIV_ROUND_UP(max(timings->tRP_min, timings->tREA_max) + 6000,
>> + period);
>> + reg |= TIMING_TRP(val) | TIMING_TRP_RESP(val);
>> +
>> + reg |= TIMING_TWB(DIV_ROUND_UP(timings->tWB_max, period));
>> + reg |= TIMING_TWHR(DIV_ROUND_UP(timings->tWHR_min, period));
>> + reg |= TIMING_TWH(DIV_ROUND_UP(timings->tWH_min, period));
>> + reg |= TIMING_TWP(DIV_ROUND_UP(timings->tWP_min, period));
>> + reg |= TIMING_TRH(DIV_ROUND_UP(timings->tRHW_min, period));
>> +
>> + writel(reg, nand->regs + TIMING_1);
>> +
>> + val = DIV_ROUND_UP(timings->tADL_min, period);
>> + if (val > 2)
>> + val -= 3;
>
> Ditto
>
>> + reg = TIMING_TADL(val);
>> +
>> + writel(reg, nand->regs + TIMING_2);
>> +}
>> +
>> +static void tegra_nand_setup_chiptiming(struct tegra_nand *nand)
>> +{
>> + struct nand_chip *chip = &nand->chip;
>> + int mode;
>> +
>> + mode = onfi_get_async_timing_mode(chip);
>> + if (mode == ONFI_TIMING_MODE_UNKNOWN)
>> + mode = chip->onfi_timing_mode_default;
>> + else
>> + mode = fls(mode);
>> +
>> + tegra_nand_setup_timing(nand, mode);
>> +}
>
> You can drop this function and use tegra_nand_setup_timing directly as
> hook for ->setup_data_interface().
>
>> +
>> +static int tegra_nand_probe(struct platform_device *pdev)
>> +{
>> + struct reset_control *rst;
>> + struct tegra_nand *nand;
>
> Would you mind having another name for the tegra_nand structure than
> just 'nand'? I found it confusing as, following Boris comment, it won't
> be a 'NAND device' structure but rather more a controller structure.
>
>> + struct nand_chip *chip;
>> + struct mtd_info *mtd;
>> + struct resource *res;
>> + unsigned long value;
>
> s/value/reg/ ? or something more explicit?
>
>> + int irq, err = 0;
>> +
>> + nand = devm_kzalloc(&pdev->dev, sizeof(*nand), GFP_KERNEL);
>> + if (!nand)
>> + return -ENOMEM;
>> +
>> + nand->dev = &pdev->dev;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + nand->regs = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(nand->regs))
>> + return PTR_ERR(nand->regs);
>> +
>> + irq = platform_get_irq(pdev, 0);
>> + err = devm_request_irq(&pdev->dev, irq, tegra_nand_irq, 0,
>> + dev_name(&pdev->dev), nand);
>> + if (err)
>> + return err;
>> +
>> + rst = devm_reset_control_get(&pdev->dev, "nand");
>> + if (IS_ERR(rst))
>> + return PTR_ERR(rst);
>> +
>> + nand->clk = devm_clk_get(&pdev->dev, "nand");
>> + if (IS_ERR(nand->clk))
>> + return PTR_ERR(nand->clk);
>> +
>> + nand->wp_gpio = gpiod_get_optional(&pdev->dev, "wp-gpios",
>> + GPIOD_OUT_HIGH);
>> + if (IS_ERR(nand->wp_gpio))
>> + return PTR_ERR(nand->wp_gpio);
>> +
>> + err = clk_prepare_enable(nand->clk);
>> + if (err)
>> + return err;
>> +
>> + reset_control_assert(rst);
>> + udelay(2);
>> + reset_control_deassert(rst);
>> +
>> + value = HWSTATUS_RDSTATUS_MASK(1) | HWSTATUS_RDSTATUS_VALUE(0) |
>> + HWSTATUS_RBSY_MASK(NAND_STATUS_READY) |
>> + HWSTATUS_RBSY_VALUE(NAND_STATUS_READY);
>> + writel(NAND_CMD_STATUS, nand->regs + HWSTATUS_CMD);
>> + writel(value, nand->regs + HWSTATUS_MASK);
>> +
>> + init_completion(&nand->command_complete);
>> + init_completion(&nand->dma_complete);
>> +
>> + /* clear interrupts */
>> + value = readl(nand->regs + ISR);
>> + writel(value, nand->regs + ISR);
>> +
>> + writel(DMA_CTRL_IS_DONE, nand->regs + DMA_CTRL);
>> +
>> + /* enable interrupts */
>> + value = IER_UND | IER_OVR | IER_CMD_DONE | IER_ECC_ERR | IER_GIE;
>> + writel(value, nand->regs + IER);
>> +
>> + /* reset config */
>> + writel(0, nand->regs + CFG);
>> +
>> + chip = &nand->chip;
>> + mtd = nand_to_mtd(chip);
>> +
>> + mtd->dev.parent = &pdev->dev;
>> + mtd->name = "tegra_nand";
>
> I just figured it was undocumented (yet) but you could have a label
> string property in your nand DT node that tells you the name of the
> MTD device instead of something too generic like tegra_nand.
>
I think that was used back in the kernel parameter mtd partition time?
So maybe it should stay the same in case somebody uses it? But yeah, I
can use a label property with "tegra_nand" instead of hard coding it.
--
Stefan
>> + mtd->owner = THIS_MODULE;
>> +
>> + nand_set_flash_node(chip, pdev->dev.of_node);
>> + nand_set_controller_data(chip, nand);
>> +
>> + chip->options = NAND_NO_SUBPAGE_WRITE;
>> + chip->exec_op = tegra_nand_exec_op;
>> + chip->select_chip = tegra_nand_select_chip;
>> + tegra_nand_setup_timing(nand, 0);
>
> You really should implement ->setup_data_interface() and let the core
> handle the timings issue entirely (mind that chipnr is not the NAND
> chip id but more the CS id asserted for the pointed NAND chip).
>
>> +
>> + err = nand_scan_ident(mtd, 1, NULL);
>> + if (err)
>> + goto err_disable_clk;
>> +
>> + if (chip->bbt_options & NAND_BBT_USE_FLASH)
>> + chip->bbt_options |= NAND_BBT_NO_OOB;
>> +
>> + nand->data_buf = dmam_alloc_coherent(&pdev->dev, mtd->writesize,
>> + &nand->data_dma, GFP_KERNEL);
>
> Do you need these buffers before nand_scan_tail() or could you simply
> use the ones allocated by the core right after?
>
>> + if (!nand->data_buf) {
>> + err = -ENOMEM;
>> + goto err_disable_clk;
>> + }
>> +
>> + nand->oob_buf = dmam_alloc_coherent(&pdev->dev, mtd->oobsize,
>> + &nand->oob_dma, GFP_KERNEL);
>> + if (!nand->oob_buf) {
>> + err = -ENOMEM;
>> + goto err_disable_clk;
>> + }
>> +
>> + chip->ecc.mode = NAND_ECC_HW;
>> + chip->ecc.size = 512;
>> + chip->ecc.read_page = tegra_nand_read_page;
>> + chip->ecc.write_page = tegra_nand_write_page;
>> +
>> + value = readl(nand->regs + CFG);
>> + value |= CFG_PIPE_EN | CFG_SKIP_SPARE | CFG_SKIP_SPARE_SIZE_4 |
>> + CFG_TAG_BYTE_SIZE(mtd_ooblayout_count_freebytes(mtd) - 1);
>> +
>> + if (chip->options & NAND_BUSWIDTH_16)
>> + value |= CFG_BUS_WIDTH_16;
>> +
>> + switch (mtd->oobsize) {
>> + case 16:
>> + mtd_set_ooblayout(mtd, &tegra_nand_oob_16_ops);
>> + chip->ecc.strength = 1;
>> + chip->ecc.bytes = 4;
>> + break;
>> + case 64:
>> + mtd_set_ooblayout(mtd, &tegra_nand_oob_64_ops);
>> + chip->ecc.strength = 8;
>> + chip->ecc.bytes = 18;
>> + value |= CFG_ECC_SEL | CFG_TVAL_8;
>> + break;
>> + case 128:
>> + mtd_set_ooblayout(mtd, &tegra_nand_oob_128_ops);
>> + chip->ecc.strength = 8;
>> + chip->ecc.bytes = 18;
>> + value |= CFG_ECC_SEL | CFG_TVAL_8;
>> + break;
>> + case 224:
>> + mtd_set_ooblayout(mtd, &tegra_nand_oob_224_ops);
>> + chip->ecc.strength = 8;
>> + chip->ecc.bytes = 18;
>> + value |= CFG_ECC_SEL | CFG_TVAL_8;
>> + break;
>> + default:
>> + dev_err(&pdev->dev, "unhandled OOB size %d\n", mtd->oobsize);
>> + err = -ENODEV;
>> + goto err_disable_clk;
>> + }
>> +
>> + switch (mtd->writesize) {
>> + case 256:
>> + value |= CFG_PS_256;
>> + break;
>> + case 512:
>> + value |= CFG_PS_512;
>> + break;
>> + case 1024:
>> + value |= CFG_PS_1024;
>> + break;
>> + case 2048:
>> + value |= CFG_PS_2048;
>> + break;
>> + case 4096:
>> + value |= CFG_PS_4096;
>> + break;
>> + default:
>> + dev_err(&pdev->dev, "unhandled writesize %d\n", mtd->writesize);
>> + err = -ENODEV;
>> + goto err_disable_clk;
>> + }
>> +
>> + writel(value, nand->regs + CFG);
>> +
>> + tegra_nand_setup_chiptiming(nand);
>> +
>> + err = nand_scan_tail(mtd);
>> + if (err)
>> + goto err_disable_clk;
>> +
>> + err = mtd_device_register(mtd, NULL, 0);
>> + if (err)
>> + goto err_cleanup_nand;
>> +
>> + platform_set_drvdata(pdev, nand);
>> +
>> + return 0;
>> +
>> +err_cleanup_nand:
>> + nand_cleanup(chip);
>> +err_disable_clk:
>> + clk_disable_unprepare(nand->clk);
>> + return err;
>> +}
>> +
>> +static int tegra_nand_remove(struct platform_device *pdev)
>> +{
>> + struct tegra_nand *nand = platform_get_drvdata(pdev);
>> +
>> + nand_release(nand_to_mtd(&nand->chip));
>> +
>> + clk_disable_unprepare(nand->clk);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id tegra_nand_of_match[] = {
>> + { .compatible = "nvidia,tegra20-nand" },
>> + { /* sentinel */ }
>> +};
>> +
>> +static struct platform_driver tegra_nand_driver = {
>> + .driver = {
>> + .name = "tegra-nand",
>> + .of_match_table = tegra_nand_of_match,
>> + },
>> + .probe = tegra_nand_probe,
>> + .remove = tegra_nand_remove,
>> +};
>> +module_platform_driver(tegra_nand_driver);
>> +
>> +MODULE_DESCRIPTION("NVIDIA Tegra NAND driver");
>> +MODULE_AUTHOR("Thierry Reding <thierry.reding@nvidia.com>");
>> +MODULE_AUTHOR("Lucas Stach <dev@lynxeye.de>");
>> +MODULE_AUTHOR("Stefan Agner <stefan@agner.ch>");
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_DEVICE_TABLE(of, tegra_nand_of_match);
^ permalink raw reply
* Re: [patch v22 1/4] drivers: jtag: Add JTAG core driver
From: Greg KH @ 2018-05-28 12:35 UTC (permalink / raw)
To: Oleksandr Shamray
Cc: arnd, linux-kernel, linux-arm-kernel, devicetree, openbmc, joel,
jiri, tklauser, linux-serial, vadimp, system-sw-low-level,
robh+dt, openocd-devel-owner, linux-api, davem, mchehab
In-Reply-To: <1527503652-21975-2-git-send-email-oleksandrs@mellanox.com>
On Mon, May 28, 2018 at 01:34:09PM +0300, Oleksandr Shamray wrote:
> Initial patch for JTAG driver
> JTAG class driver provide infrastructure to support hardware/software
> JTAG platform drivers. It provide user layer API interface for flashing
> and debugging external devices which equipped with JTAG interface
> using standard transactions.
>
> Driver exposes set of IOCTL to user space for:
> - XFER:
> - SIR (Scan Instruction Register, IEEE 1149.1 Data Register scan);
> - SDR (Scan Data Register, IEEE 1149.1 Instruction Register scan);
> - RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
> number of clocks).
> - SIOCFREQ/GIOCFREQ for setting and reading JTAG frequency.
>
> Driver core provides set of internal APIs for allocation and
> registration:
> - jtag_register;
> - jtag_unregister;
> - jtag_alloc;
> - jtag_free;
>
> Platform driver on registration with jtag-core creates the next
> entry in dev folder:
> /dev/jtagX
>
> Signed-off-by: Oleksandr Shamray <oleksandrs@mellanox.com>
> Signed-off-by: Jiri Pirko <jiri@mellanox.com>
> Acked-by: Philippe Ombredanne <pombredanne@nexb.com>
> ---
> v21->v22
22 versions, way to stick with this...
Anyway, time to review it again. I feel it's really close, but I don't
want to apply it yet as the api feels odd in places. If others have
asked you to make these changes to look like this, I'm sorry, then
please push back on me:
> +/*
> + * JTAG core driver supports up to 256 devices
> + * JTAG device name will be in range jtag0-jtag255
> + * Set maximum len of jtag id to 3
> + */
> +
> +#define MAX_JTAG_DEVS 255
Why have a max at all? You should be able to just dynamically allocate
them. Anyway, if you do want a max, you need to be able to properly
keep the max number, and right now you have a race when registering (you
check the number, and then much later do you increment it, a pointless
use of an atomic value if I've ever seen one...)
> +#define MAX_JTAG_NAME_LEN (sizeof("jtag") + 3)
> +
> +struct jtag {
> + struct miscdevice miscdev;
If you are a miscdev, why even have a max number? Just let the max
number of miscdev devices rule things.
> + const struct jtag_ops *ops;
> + int id;
> + bool opened;
You shouldn't care about this, but ok...
> + struct mutex open_lock;
> + unsigned long priv[0];
> +};
> +
> +static DEFINE_IDA(jtag_ida);
> +
> +static atomic_t jtag_refcount = ATOMIC_INIT(0);
Either use it as an atomic properly (test_and_set), or just leave it as
an int, or better yet, don't use it at all.
> +void *jtag_priv(struct jtag *jtag)
> +{
> + return jtag->priv;
> +}
> +EXPORT_SYMBOL_GPL(jtag_priv);
Api naming issue here. Traditionally this is a "get/set_drvdata" type
function, as in dev_get_drvdata(), or dev_set_drvdata. But, you are
right in that the network stack has a netdev_priv() call, where you
probably copied this idea from.
I don't know, I guess it's ok as-is, as it's the way networking does it,
it's your call though.
> +static long jtag_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
> +{
> + struct jtag *jtag = file->private_data;
> + struct jtag_run_test_idle idle;
> + struct jtag_xfer xfer;
> + u8 *xfer_data;
> + u32 data_size;
> + u32 value;
> + int err;
> +
> + if (!arg)
> + return -EINVAL;
> +
> + switch (cmd) {
> + case JTAG_GIOCFREQ:
> + if (!jtag->ops->freq_get)
> + return -EOPNOTSUPP;
> +
> + err = jtag->ops->freq_get(jtag, &value);
> + if (err)
> + break;
> +
> + if (put_user(value, (__u32 __user *)arg))
> + err = -EFAULT;
> + break;
> +
> + case JTAG_SIOCFREQ:
> + if (!jtag->ops->freq_set)
> + return -EOPNOTSUPP;
> +
> + if (get_user(value, (__u32 __user *)arg))
> + return -EFAULT;
> + if (value == 0)
> + return -EINVAL;
> +
> + err = jtag->ops->freq_set(jtag, value);
> + break;
> +
> + case JTAG_IOCRUNTEST:
> + if (copy_from_user(&idle, (const void __user *)arg,
> + sizeof(struct jtag_run_test_idle)))
> + return -EFAULT;
> +
> + if (idle.endstate > JTAG_STATE_PAUSEDR)
> + return -EINVAL;
No validation that idle contains sane values? Don't make every jtag
driver have to do this type of validation please.
> +
> + err = jtag->ops->idle(jtag, &idle);
> + break;
> +
> + case JTAG_IOCXFER:
> + if (copy_from_user(&xfer, (const void __user *)arg,
> + sizeof(struct jtag_xfer)))
> + return -EFAULT;
> +
> + if (xfer.length >= JTAG_MAX_XFER_DATA_LEN)
> + return -EINVAL;
> +
> + if (xfer.type > JTAG_SDR_XFER)
> + return -EINVAL;
> +
> + if (xfer.direction > JTAG_WRITE_XFER)
> + return -EINVAL;
> +
> + if (xfer.endstate > JTAG_STATE_PAUSEDR)
> + return -EINVAL;
> +
See, you do good error checking here, why not for the previous ioctl?
> + data_size = DIV_ROUND_UP(xfer.length, BITS_PER_BYTE);
> + xfer_data = memdup_user(u64_to_user_ptr(xfer.tdio), data_size);
> +
No blank line.
> + if (IS_ERR(xfer_data))
> + return -EFAULT;
> +
> + err = jtag->ops->xfer(jtag, &xfer, xfer_data);
> + if (err) {
> + kfree(xfer_data);
> + return -EFAULT;
Why not return the error given to you? -EFAULT is only if there is a
memory error in a copy_to/from_user() call.
> + }
> +
> + err = copy_to_user(u64_to_user_ptr(xfer.tdio),
> + (void *)xfer_data, data_size);
> + kfree(xfer_data);
> + if (err)
> + return -EFAULT;
Like here, that's correct.
> +
> + if (copy_to_user((void __user *)arg, (void *)&xfer,
> + sizeof(struct jtag_xfer)))
> + return -EFAULT;
> + break;
> +
> + case JTAG_GIOCSTATUS:
> + err = jtag->ops->status_get(jtag, &value);
> + if (err)
> + break;
> +
> + err = put_user(value, (__u32 __user *)arg);
> + break;
> + case JTAG_SIOCMODE:
> + if (!jtag->ops->mode_set)
> + return -EOPNOTSUPP;
> +
> + if (get_user(value, (__u32 __user *)arg))
> + return -EFAULT;
> + if (value == 0)
> + return -EINVAL;
> +
> + err = jtag->ops->mode_set(jtag, value);
> + break;
> +
> + default:
> + return -EINVAL;
> + }
> + return err;
> +}
> +
> +static int jtag_open(struct inode *inode, struct file *file)
> +{
> + struct jtag *jtag = container_of(file->private_data, struct jtag, miscdev);
> +
> + if (mutex_lock_interruptible(&jtag->open_lock))
> + return -ERESTARTSYS;
Why restart? Just grab the lock, you don't want to have to do
restartable logic in userspace, right?
> +
> + if (jtag->opened) {
> + mutex_unlock(&jtag->open_lock);
> + return -EBUSY;
Why do you care about only 1 userspace open call? What does that buy
you? Userspace can always pass around that file descriptor and use it
in multiple places, so you are not really "protecting" yourself from
anything.
And better yet, if you get rid of this, your open/release functions get
very tiny and simple.
> + }
> + jtag->opened = true;
> + mutex_unlock(&jtag->open_lock);
> +
> + nonseekable_open(inode, file);
No error checking of the return value? Not good :(
> + file->private_data = jtag;
> + return 0;
> +}
> +
> +static int jtag_release(struct inode *inode, struct file *file)
> +{
> + struct jtag *jtag = file->private_data;
> +
> + mutex_lock(&jtag->open_lock);
> + jtag->opened = false;
> + mutex_unlock(&jtag->open_lock);
> + return 0;
> +}
> +
> +static const struct file_operations jtag_fops = {
> + .owner = THIS_MODULE,
> + .open = jtag_open,
> + .release = jtag_release,
> + .llseek = noop_llseek,
> + .unlocked_ioctl = jtag_ioctl,
> +};
> +
> +struct jtag *jtag_alloc(struct device *host, size_t priv_size,
> + const struct jtag_ops *ops)
> +{
> + struct jtag *jtag;
> +
> + if (!host)
> + return NULL;
> +
> + if (!ops)
> + return NULL;
> +
> + if (!ops->idle || !ops->status_get || !ops->xfer)
> + return NULL;
> +
> + jtag = kzalloc(sizeof(*jtag) + priv_size, GFP_KERNEL);
> + if (!jtag)
> + return NULL;
> +
> + jtag->ops = ops;
> + jtag->miscdev.parent = host;
> +
> + return jtag;
> +}
> +EXPORT_SYMBOL_GPL(jtag_alloc);
> +
> +void jtag_free(struct jtag *jtag)
> +{
> + kfree(jtag);
> +}
> +EXPORT_SYMBOL_GPL(jtag_free);
> +
> +static int jtag_register(struct jtag *jtag)
> +{
> + struct device *dev = jtag->miscdev.parent;
> + char *name;
> + int err;
> + int id;
> +
> + if (!dev)
> + return -ENODEV;
> +
> + if (atomic_read(&jtag_refcount) >= MAX_JTAG_DEVS)
> + return -ENOSPC;
Here, you are reading the value, and then setting it a long ways away.
What happens if two people call this at the same time. Not good.
Either do it correctly, or better yet, don't do it at all.
> +
> + id = ida_simple_get(&jtag_ida, 0, 0, GFP_KERNEL);
> + if (id < 0)
> + return id;
> +
> + jtag->id = id;
> + jtag->opened = false;
> +
> + name = kzalloc(MAX_JTAG_NAME_LEN, GFP_KERNEL);
> + if (!name) {
> + err = -ENOMEM;
> + goto err_jtag_alloc;
> + }
> +
> + err = snprintf(name, MAX_JTAG_NAME_LEN, "jtag%d", id);
> + if (err < 0)
> + goto err_jtag_name;
> +
> + mutex_init(&jtag->open_lock);
> + jtag->miscdev.fops = &jtag_fops;
> + jtag->miscdev.minor = MISC_DYNAMIC_MINOR;
> + jtag->miscdev.name = name;
> +
> + err = misc_register(&jtag->miscdev);
> + if (err) {
> + dev_err(jtag->miscdev.parent, "Unable to register device\n");
> + goto err_jtag_name;
> + }
> + pr_info("%s %d\n", __func__, __LINE__);
> + atomic_inc(&jtag_refcount);
> + return 0;
> +
> +err_jtag_name:
> + kfree(name);
> +err_jtag_alloc:
> + ida_simple_remove(&jtag_ida, id);
> + return err;
> +}
> +
> +static void jtag_unregister(struct jtag *jtag)
> +{
> + misc_deregister(&jtag->miscdev);
> + kfree(jtag->miscdev.name);
> + ida_simple_remove(&jtag_ida, jtag->id);
> + atomic_dec(&jtag_refcount);
> +}
> +
> +static void devm_jtag_unregister(struct device *dev, void *res)
> +{
> + jtag_unregister(*(struct jtag **)res);
> +}
> +
> +int devm_jtag_register(struct device *dev, struct jtag *jtag)
> +{
> + struct jtag **ptr;
> + int ret;
> +
> + ptr = devres_alloc(devm_jtag_unregister, sizeof(*ptr), GFP_KERNEL);
> + if (!ptr)
> + return -ENOMEM;
> +
> + ret = jtag_register(jtag);
> + if (!ret) {
> + *ptr = jtag;
> + devres_add(dev, ptr);
> + } else {
> + devres_free(ptr);
> + }
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(devm_jtag_register);
> +
> +static void __exit jtag_exit(void)
> +{
> + ida_destroy(&jtag_ida);
> +}
> +
> +module_exit(jtag_exit);
> +
> +MODULE_AUTHOR("Oleksandr Shamray <oleksandrs@mellanox.com>");
> +MODULE_DESCRIPTION("Generic jtag support");
> +MODULE_LICENSE("GPL v2");
> diff --git a/include/linux/jtag.h b/include/linux/jtag.h
> new file mode 100644
> index 0000000..56d784d
> --- /dev/null
> +++ b/include/linux/jtag.h
> @@ -0,0 +1,43 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// include/linux/jtag.h - JTAG class driver
> +//
> +// Copyright (c) 2018 Mellanox Technologies. All rights reserved.
> +// Copyright (c) 2018 Oleksandr Shamray <oleksandrs@mellanox.com>
> +
> +#ifndef __JTAG_H
> +#define __JTAG_H
> +
> +#include <uapi/linux/jtag.h>
> +
> +#define jtag_u64_to_ptr(arg) ((void *)(uintptr_t)arg)
Why do you need such a horrid cast? What is this for? And why use
uintptr_t at all? It's not a "normal" kernel type.
> +
> +#define JTAG_MAX_XFER_DATA_LEN 65535
> +
> +struct jtag;
> +/**
> + * struct jtag_ops - callbacks for JTAG control functions:
> + *
> + * @freq_get: get frequency function. Filled by dev driver
> + * @freq_set: set frequency function. Filled by dev driver
> + * @status_get: set status function. Mandatory func. Filled by dev driver
> + * @idle: set JTAG to idle state function. Mandatory func. Filled by dev driver
> + * @xfer: send JTAG xfer function. Mandatory func. Filled by dev driver
> + * @mode_set: set specific work mode for JTAG. Filled by dev driver
> + */
> +struct jtag_ops {
> + int (*freq_get)(struct jtag *jtag, u32 *freq);
> + int (*freq_set)(struct jtag *jtag, u32 freq);
> + int (*status_get)(struct jtag *jtag, u32 *state);
> + int (*idle)(struct jtag *jtag, struct jtag_run_test_idle *idle);
> + int (*xfer)(struct jtag *jtag, struct jtag_xfer *xfer, u8 *xfer_data);
> + int (*mode_set)(struct jtag *jtag, u32 mode_mask);
> +};
> +
> +void *jtag_priv(struct jtag *jtag);
> +int devm_jtag_register(struct device *dev, struct jtag *jtag);
> +void devm_jtag_unregister(struct device *dev, void *res);
> +struct jtag *jtag_alloc(struct device *host, size_t priv_size,
> + const struct jtag_ops *ops);
> +void jtag_free(struct jtag *jtag);
> +
> +#endif /* __JTAG_H */
> diff --git a/include/uapi/linux/jtag.h b/include/uapi/linux/jtag.h
> new file mode 100644
> index 0000000..8bbf1a7
> --- /dev/null
> +++ b/include/uapi/linux/jtag.h
> @@ -0,0 +1,102 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// include/uapi/linux/jtag.h - JTAG class driver uapi
> +//
> +// Copyright (c) 2018 Mellanox Technologies. All rights reserved.
> +// Copyright (c) 2018 Oleksandr Shamray <oleksandrs@mellanox.com>
> +
> +#ifndef __UAPI_LINUX_JTAG_H
> +#define __UAPI_LINUX_JTAG_H
> +
> +/*
> + * JTAG_XFER_HW_MODE: JTAG hardware mode. Used to set HW drived or bitbang
> + * mode. This is bitmask param of ioctl JTAG_SIOCMODE command
> + */
> +#define JTAG_XFER_HW_MODE 1
> +
> +/**
> + * enum jtag_endstate:
> + *
> + * @JTAG_STATE_IDLE: JTAG state machine IDLE state
> + * @JTAG_STATE_PAUSEIR: JTAG state machine PAUSE_IR state
> + * @JTAG_STATE_PAUSEDR: JTAG state machine PAUSE_DR state
> + */
> +enum jtag_endstate {
> + JTAG_STATE_IDLE,
> + JTAG_STATE_PAUSEIR,
> + JTAG_STATE_PAUSEDR,
> +};
> +
> +/**
> + * enum jtag_xfer_type:
> + *
> + * @JTAG_SIR_XFER: SIR transfer
> + * @JTAG_SDR_XFER: SDR transfer
> + */
> +enum jtag_xfer_type {
> + JTAG_SIR_XFER,
> + JTAG_SDR_XFER,
> +};
> +
> +/**
> + * enum jtag_xfer_direction:
> + *
> + * @JTAG_READ_XFER: read transfer
> + * @JTAG_WRITE_XFER: write transfer
> + */
> +enum jtag_xfer_direction {
> + JTAG_READ_XFER,
> + JTAG_WRITE_XFER,
> +};
> +
> +/**
> + * struct jtag_run_test_idle - forces JTAG state machine to
> + * RUN_TEST/IDLE state
> + *
> + * @reset: 0 - run IDLE/PAUSE from current state
> + * 1 - go through TEST_LOGIC/RESET state before IDLE/PAUSE
> + * @end: completion flag
> + * @tck: clock counter
> + *
> + * Structure provide interface to JTAG device for JTAG IDLE execution.
> + */
> +struct jtag_run_test_idle {
> + __u8 reset;
> + __u8 endstate;
> + __u8 tck;
> +};
> +
> +/**
> + * struct jtag_xfer - jtag xfer:
> + *
> + * @type: transfer type
> + * @direction: xfer direction
> + * @length: xfer bits len
> + * @tdio : xfer data array
> + * @endir: xfer end state
> + *
> + * Structure provide interface to JTAG device for JTAG SDR/SIR xfer execution.
> + */
> +struct jtag_xfer {
> + __u8 type;
> + __u8 direction;
> + __u8 endstate;
> + __u8 padding;
> + __u32 length;
> + __u64 tdio;
> +};
> +
> +/* ioctl interface */
> +#define __JTAG_IOCTL_MAGIC 0xb2
> +
> +#define JTAG_IOCRUNTEST _IOW(__JTAG_IOCTL_MAGIC, 0,\
> + struct jtag_run_test_idle)
No need for 2 lines here, fits just fine on one.
> +#define JTAG_SIOCFREQ _IOW(__JTAG_IOCTL_MAGIC, 1, unsigned int)
> +#define JTAG_GIOCFREQ _IOR(__JTAG_IOCTL_MAGIC, 2, unsigned int)
> +#define JTAG_IOCXFER _IOWR(__JTAG_IOCTL_MAGIC, 3, struct jtag_xfer)
> +#define JTAG_GIOCSTATUS _IOWR(__JTAG_IOCTL_MAGIC, 4, enum jtag_endstate)
> +#define JTAG_SIOCMODE _IOW(__JTAG_IOCTL_MAGIC, 5, unsigned int)
> +
> +#define JTAG_FIRST_MINOR 0
Why is this in a uapi file?
> +#define JTAG_MAX_DEVICES 32
This is never used, why is it in a uapi file?
So, almost there, with the above mentioned things, I think you can make
the code even simpler, which is always better, right?
thanks,
greg k-h
^ permalink raw reply
* [patch v22 4/4] Documentation: jtag: Add ABI documentation
From: Oleksandr Shamray @ 2018-05-28 12:00 UTC (permalink / raw)
To: gregkh, arnd
Cc: linux-kernel, linux-arm-kernel, devicetree, openbmc, joel, jiri,
tklauser, linux-serial, system-sw-low-level, robh+dt,
openocd-devel-owner, linux-api, davem, mchehab, Oleksandr Shamray
In-Reply-To: <1527508827-30724-1-git-send-email-oleksandrs@mellanox.com>
Added document that describe the ABI for JTAG class drivrer
Signed-off-by: Oleksandr Shamray <oleksandrs@mellanox.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
---
v21->v22
Comments pointed by Randy Dunlap <rdunlap@infradead.org>
- fix spell in ABI doccumentation
v20->v21
Comments pointed by Randy Dunlap <rdunlap@infradead.org>
- Fix JTAG dirver help in Kconfig
v19->v20
Comments pointed by Randy Dunlap <rdunlap@infradead.org>
- Fix JTAG doccumentation
v18->v19
Pavel Machek <pavel@ucw.cz>
- Added JTAG doccumentation to Documentation/jtag
v17->v18
v16->v17
v15->v16
v14->v15
v13->v14
v12->v13
v11->v12 Tobias Klauser <tklauser@distanz.ch>
Comments pointed by
- rename /Documentation/ABI/testing/jatg-dev -> jtag-dev
- Typo: s/interfase/interface
v10->v11
v9->v10
Fixes added by Oleksandr:
- change jtag-cdev to jtag-dev in documentation
- update KernelVersion and Date in jtag-dev documentation;
v8->v9
v7->v8
v6->v7
Comments pointed by Pavel Machek <pavel@ucw.cz>
- Added jtag-cdev documentation to Documentation/ABI/testing folder
---
Documentation/ABI/testing/jtag-dev | 27 +++++++++
Documentation/jtag/overview | 28 +++++++++
Documentation/jtag/transactions | 109 ++++++++++++++++++++++++++++++++++++
MAINTAINERS | 1 +
4 files changed, 165 insertions(+), 0 deletions(-)
create mode 100644 Documentation/ABI/testing/jtag-dev
create mode 100644 Documentation/jtag/overview
create mode 100644 Documentation/jtag/transactions
diff --git a/Documentation/ABI/testing/jtag-dev b/Documentation/ABI/testing/jtag-dev
new file mode 100644
index 0000000..4325316
--- /dev/null
+++ b/Documentation/ABI/testing/jtag-dev
@@ -0,0 +1,27 @@
+What: /dev/jtag[0-9]+
+Date: May 2018
+KernelVersion: 4.18
+Contact: oleksandrs@mellanox.com
+Description:
+ The misc device files /dev/jtag* are the interface
+ between JTAG master interface and userspace.
+
+ The ioctl(2)-based ABI is defined and documented in
+ [include/uapi]<linux/jtag.h>.
+
+ The following file operations are supported:
+
+ open(2)
+ The argument flag currently support only one access
+ mode O_RDWR.
+
+ ioctl(2)
+ Initiate various actions.
+ See the inline documentation in [include/uapi]<linux/jtag.h>
+ for descriptions of all ioctls.
+
+ close(2)
+ Stops and free up the I/O contexts that was associated
+ with the file descriptor.
+
+Users: TBD
diff --git a/Documentation/jtag/overview b/Documentation/jtag/overview
new file mode 100644
index 0000000..42b487a
--- /dev/null
+++ b/Documentation/jtag/overview
@@ -0,0 +1,28 @@
+Linux kernel JTAG support
+=========================
+
+The JTAG is an industry standard for verifying hardware.
+JTAG provides access to many logic signals of a complex integrated circuit,
+including the device pins.
+
+A JTAG interface is a special interface added to a chip.
+Depending on the version of JTAG, two, four, or five pins are added.
+
+The connector pins are:
+ TDI (Test Data In)
+ TDO (Test Data Out)
+ TCK (Test Clock)
+ TMS (Test Mode Select)
+ TRST (Test Reset) optional
+
+JTAG interface is designed to have two parts - basic core driver and
+hardware specific driver. The basic driver introduces a general interface
+which is not dependent of specific hardware. It provides communication
+between user space and hardware specific driver.
+Each JTAG device is represented as a char device from (jtag0, jtag1, ...).
+Access to a JTAG device is performed through IOCTL calls.
+
+Call flow example:
+User: open -> /dev/jatgX
+User: ioctl -> /dev/jtagX -> JTAG core driver -> JTAG hardware specific driver
+User: close -> /dev/jatgX
diff --git a/Documentation/jtag/transactions b/Documentation/jtag/transactions
new file mode 100644
index 0000000..2abf833
--- /dev/null
+++ b/Documentation/jtag/transactions
@@ -0,0 +1,109 @@
+The JTAG API
+=============
+
+JTAG master devices can be accessed through a character misc-device.
+Each JTAG master interface can be accessed by using /dev/jtagN.
+
+JTAG system calls set:
+- SIR (Scan Instruction Register, IEEE 1149.1 Instruction Register scan);
+- SDR (Scan Data Register, IEEE 1149.1 Data Register scan);
+- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
+number of clocks.
+
+open(), close()
+-------
+open() opens JTAG device. Only one open operation per JTAG device
+can be performed. Two or more open for one device will return error.
+
+Open/Close device:
+- jtag_fd = open("/dev/jtag0", O_RDWR);
+- close(jtag_fd);
+
+ioctl()
+-------
+All access operations to JTAG devices performed through ioctl interface.
+The IOCTL interface supports these requests:
+ JTAG_IOCRUNTEST - Force JTAG state machine to RUN_TEST/IDLE state
+ JTAG_SIOCFREQ - Set JTAG TCK frequency
+ JTAG_GIOCFREQ - Get JTAG TCK frequency
+ JTAG_IOCXFER - send JTAG data Xfer
+ JTAG_GIOCSTATUS - get current JTAG TAP status
+ JTAG_SIOCMODE - set JTAG mode flags.
+
+JTAG_SIOCFREQ, JTAG_GIOCFREQ
+------
+Set/Get JTAG clock speed:
+
+ unsigned int jtag_fd;
+ ioctl(jtag_fd, JTAG_SIOCFREQ, &frq);
+ ioctl(jtag_fd, JTAG_GIOCFREQ, &frq);
+
+JTAG_IOCRUNTEST
+------
+Force JTAG state machine to RUN_TEST/IDLE state
+
+struct jtag_run_test_idle {
+ __u8 reset;
+ __u8 endstate;
+ __u8 tck;
+};
+
+reset: 0 - run IDLE/PAUSE from current state
+ 1 - go through TEST_LOGIC/RESET state before IDLE/PAUSE
+endstate: completion flag
+tck: clock counter
+
+Example:
+ struct jtag_run_test_idle runtest;
+
+ runtest.endstate = JTAG_STATE_IDLE;
+ runtest.reset = 0;
+ runtest.tck = data_p->tck;
+ usleep(25 * 1000);
+ ioctl(jtag_fd, JTAG_IOCRUNTEST, &runtest);
+
+JTAG_IOCXFER
+------
+Send SDR/SIR transaction
+
+struct jtag_xfer {
+ __u8 type;
+ __u8 direction;
+ __u8 endstate;
+ __u8 padding;
+ __u32 length;
+ __u64 tdio;
+};
+
+type: transfer type - JTAG_SIR_XFER/JTAG_SDR_XFER
+direction: xfer direction - JTAG_SIR_XFER/JTAG_SDR_XFER,
+length: xfer data len in bits
+tdio : xfer data array
+endstate: xfer end state after transaction finish
+ can be: JTAG_STATE_IDLE/JTAG_STATE_PAUSEIR/JTAG_STATE_PAUSEDR
+
+Example:
+ struct jtag_xfer xfer;
+ static char buf[64];
+ static unsigned int buf_len = 0;
+ [...]
+ xfer.type = JTAG_SDR_XFER;
+ xfer.tdio = (__u64)buf;
+ xfer.length = buf_len;
+ xfer.endstate = JTAG_STATE_IDLE;
+
+ if (is_read)
+ xfer.direction = JTAG_READ_XFER;
+ else
+ xfer.direction = JTAG_WRITE_XFER;
+
+ ioctl(jtag_fd, JTAG_IOCXFER, &xfer);
+
+JTAG_SIOCMODE
+------
+If hardware driver can support different running modes you can change it.
+
+Example:
+ unsigned int mode;
+ mode = JTAG_XFER_HW_MODE;
+ ioctl(jtag_fd, JTAG_SIOCMODE, &mode);
diff --git a/MAINTAINERS b/MAINTAINERS
index a5e5f75..e067eda 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7618,6 +7618,7 @@ F: include/linux/jtag.h
F: include/uapi/linux/jtag.h
F: drivers/jtag/
F: Documentation/devicetree/bindings/jtag/
+F: Documentation/ABI/testing/jtag-dev
K10TEMP HARDWARE MONITORING DRIVER
M: Clemens Ladisch <clemens@ladisch.de>
--
1.7.1
^ permalink raw reply related
* [patch v22 3/4] Documentation: jtag: Add bindings for Aspeed SoC 24xx and 25xx families JTAG master driver
From: Oleksandr Shamray @ 2018-05-28 12:00 UTC (permalink / raw)
To: gregkh, arnd
Cc: linux-kernel, linux-arm-kernel, devicetree, openbmc, joel, jiri,
tklauser, linux-serial, system-sw-low-level, robh+dt,
openocd-devel-owner, linux-api, davem, mchehab, Oleksandr Shamray
In-Reply-To: <1527508827-30724-1-git-send-email-oleksandrs@mellanox.com>
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray <oleksandrs@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Acked-by: Rob Herring <robh@kernel.org>
---
v21->v22
v20->v21
v19->v20
v18->v19
v17->v18
v16->v17
v15->v16
Comments pointed by Joel Stanley <joel.stan@gmail.com>
- change clocks = <&clk_apb> to proper clocks = <&syscon ASPEED_CLK_APB>
- add reset descriptions in bndings file
v14->v15
v13->v14
v12->v13
v11->v12
v10->v11
v9->v10
v8->v9
v7->v8
Comments pointed by pointed by Joel Stanley <joel.stan@gmail.com>
- Change compatible string to ast2400 and ast2000
V6->v7
Comments pointed by Tobias Klauser <tklauser@distanz.ch>
- Fix spell "Doccumentation" -> "Documentation"
v5->v6
Comments pointed by Tobias Klauser <tklauser@distanz.ch>
- Small nit: s/documentation/Documentation/
v4->v5
V3->v4
Comments pointed by Rob Herring <robh@kernel.org>
- delete unnecessary "status" and "reg-shift" descriptions in
bndings file
v2->v3
Comments pointed by Rob Herring <robh@kernel.org>
- split Aspeed jtag driver and binding to sepatrate patches
- delete unnecessary "status" and "reg-shift" descriptions in
bndings file
---
.../devicetree/bindings/jtag/aspeed-jtag.txt | 22 ++++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 23 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/jtag/aspeed-jtag.txt
diff --git a/Documentation/devicetree/bindings/jtag/aspeed-jtag.txt b/Documentation/devicetree/bindings/jtag/aspeed-jtag.txt
new file mode 100644
index 0000000..7c36eb6
--- /dev/null
+++ b/Documentation/devicetree/bindings/jtag/aspeed-jtag.txt
@@ -0,0 +1,22 @@
+Aspeed JTAG driver for ast2400 and ast2500 SoC
+
+Required properties:
+- compatible: Should be one of
+ - "aspeed,ast2400-jtag"
+ - "aspeed,ast2500-jtag"
+- reg contains the offset and length of the JTAG memory
+ region
+- clocks root clock of bus, should reference the APB
+ clock in the second cell
+- resets phandle to reset controller with the reset number in
+ the second cell
+- interrupts should contain JTAG controller interrupt
+
+Example:
+jtag: jtag@1e6e4000 {
+ compatible = "aspeed,ast2500-jtag";
+ reg = <0x1e6e4000 0x1c>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_JTAG_MASTER>;
+ interrupts = <43>;
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index e7b8b2c..a5e5f75 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7617,6 +7617,7 @@ S: Maintained
F: include/linux/jtag.h
F: include/uapi/linux/jtag.h
F: drivers/jtag/
+F: Documentation/devicetree/bindings/jtag/
K10TEMP HARDWARE MONITORING DRIVER
M: Clemens Ladisch <clemens@ladisch.de>
--
1.7.1
^ permalink raw reply related
* [patch v22 2/4] drivers: jtag: Add Aspeed SoC 24xx and 25xx families JTAG master driver
From: Oleksandr Shamray @ 2018-05-28 12:00 UTC (permalink / raw)
To: gregkh, arnd
Cc: linux-kernel, linux-arm-kernel, devicetree, openbmc, joel, jiri,
tklauser, linux-serial, system-sw-low-level, robh+dt,
openocd-devel-owner, linux-api, davem, mchehab, Oleksandr Shamray
In-Reply-To: <1527508827-30724-1-git-send-email-oleksandrs@mellanox.com>
Driver adds support of Aspeed 2500/2400 series SOC JTAG master controller.
Driver implements the following jtag ops:
- freq_get;
- freq_set;
- status_get;
- idle;
- xfer;
It has been tested on Mellanox system with BMC equipped with
Aspeed 2520 SoC for programming CPLD devices.
Signed-off-by: Oleksandr Shamray <oleksandrs@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Philippe Ombredanne <pombredanne@nexb.com>
Acked-by: Joel Stanley <joel@jms.id.au>
---
v21->v22
Comments pointed by Andy Shevchenko <andy.shevchenko@gmail.com>
- rearrange ASPEED register defines
- simplified JTAG divider calculation formula
- change delay function in bit-bang operation
- add helper functions for TAP states switching
- remove unnecessary comments
- remove redundant debug messages
- make dines for repetative register bit sets
- fixed indentation
- change checks from negative to positive
- add error check for clk_prepare_enable
- rework driver alloc/register to devm_ variant
- Increasing line length up to 85 in order to improve readability
v20->v21
v19->v20
Notifications from kbuild test robot <lkp@intel.com>
- add static declaration to 'aspeed_jtag_init' and
'aspeed_jtag_deinit' functions
v18->v19
v17->v18
v16->v17
v15->v16
Comments pointed by Joel Stanley <joel.stan@gmail.com>
- Add reset_control on Jtag init/deinit
v14->v15
Comments pointed by Joel Stanley <joel.stan@gmail.com>
- Add ARCH_ASPEED || COMPILE_TEST to Kconfig
- remove unused offset variable
- remove "aspeed_jtag" from dev_err and dev_dbg messages
- change clk_prepare_enable initialisation order
v13->v14
Comments pointed by Philippe Ombredanne <pombredanne@nexb.com>
- Change style of head block comment from /**/ to //
v12->v13
Comments pointed by Philippe Ombredanne <pombredanne@nexb.com>
- Change jtag-aspeed.c licence type to
SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
and reorder line with license- add reset descriptions in bndings file
in description
Comments pointed by Kun Yi <kunyi@google.com>
- Changed capability check for aspeed,ast2400-jtag/ast200-jtag
v11->v12
Comments pointed by Chip Bilbrey <chip@bilbrey.org>
- Remove access mode from xfer and idle transactions
- Add new ioctl JTAG_SIOCMODE for set hw mode
v10->v11
v9->v10
V8->v9
Comments pointed by Arnd Bergmann <arnd@arndb.de>
- add *data parameter to xfer function prototype
v7->v8
Comments pointed by Joel Stanley <joel.stan@gmail.com>
- aspeed_jtag_init replace goto to return;
- change input variables type from __u32 to u32
in functios freq_get, freq_set, status_get
- change sm_ variables type from char to u8
- in jatg_init add disable clocks on error case
- remove release_mem_region on error case
- remove devm_free_irq on jtag_deinit
- Fix misspelling Disabe/Disable
- Change compatible string to ast2400 and ast2000
v6->v7
Notifications from kbuild test robot <lkp@intel.com>
- Add include <linux/types.h> to jtag-asapeed.c
v5->v6
v4->v5
Comments pointed by Arnd Bergmann <arnd@arndb.de>
- Added HAS_IOMEM dependence in Kconfig to avoid
"undefined reference to `devm_ioremap_resource'" error,
because in some arch this not supported
v3->v4
Comments pointed by Arnd Bergmann <arnd@arndb.de>
- change transaction pointer tdio type to __u64
- change internal status type from enum to __u32
v2->v3
v1->v2
Comments pointed by Greg KH <gregkh@linuxfoundation.org>
- change license type from GPLv2/BSD to GPLv2
Comments pointed by Neil Armstrong <narmstrong@baylibre.com>
- Add clk_prepare_enable/clk_disable_unprepare in clock init/deinit
- Change .compatible to soc-specific compatible names
aspeed,aspeed4000-jtag/aspeed5000-jtag
- Added dt-bindings
Comments pointed by Arnd Bergmann <arnd@arndb.de>
- Reorder functions and removed the forward declarations
- Add static const qualifier to state machine states transitions
- Change .compatible to soc-specific compatible names
aspeed,aspeed4000-jtag/aspeed5000-jtag
- Add dt-bindings
Comments pointed by Randy Dunlap <rdunlap@infradead.org>
- Change module name jtag-aspeed in description in Kconfig
Comments pointed by kbuild test robot <lkp@intel.com>
- Remove invalid include <asm/mach-types.h>
- add resource_size instead of calculation
---
drivers/jtag/Kconfig | 14 +
drivers/jtag/Makefile | 1 +
drivers/jtag/jtag-aspeed.c | 769 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 784 insertions(+), 0 deletions(-)
create mode 100644 drivers/jtag/jtag-aspeed.c
diff --git a/drivers/jtag/Kconfig b/drivers/jtag/Kconfig
index 47771fc..0cc163f 100644
--- a/drivers/jtag/Kconfig
+++ b/drivers/jtag/Kconfig
@@ -15,3 +15,17 @@ menuconfig JTAG
To compile this driver as a module, choose M here: the module will
be called jtag.
+
+menuconfig JTAG_ASPEED
+ tristate "Aspeed SoC JTAG controller support"
+ depends on JTAG && HAS_IOMEM
+ depends on ARCH_ASPEED || COMPILE_TEST
+ help
+ This provides a support for Aspeed JTAG device, equipped on
+ Aspeed SoC 24xx and 25xx families. Drivers allows programming
+ of hardware devices, connected to SoC through the JTAG interface.
+
+ If you want this support, you should say Y here.
+
+ To compile this driver as a module, choose M here: the module will
+ be called jtag-aspeed.
diff --git a/drivers/jtag/Makefile b/drivers/jtag/Makefile
index af37493..04a855e 100644
--- a/drivers/jtag/Makefile
+++ b/drivers/jtag/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_JTAG) += jtag.o
+obj-$(CONFIG_JTAG_ASPEED) += jtag-aspeed.o
diff --git a/drivers/jtag/jtag-aspeed.c b/drivers/jtag/jtag-aspeed.c
new file mode 100644
index 0000000..b3559f8
--- /dev/null
+++ b/drivers/jtag/jtag-aspeed.c
@@ -0,0 +1,769 @@
+// SPDX-License-Identifier: GPL-2.0
+// drivers/jtag/aspeed-jtag.c
+//
+// Copyright (c) 2018 Mellanox Technologies. All rights reserved.
+// Copyright (c) 2018 Oleksandr Shamray <oleksandrs@mellanox.com>
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/jtag.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <uapi/linux/jtag.h>
+
+#define ASPEED_JTAG_DATA 0x00
+#define ASPEED_JTAG_INST 0x04
+#define ASPEED_JTAG_CTRL 0x08
+#define ASPEED_JTAG_ISR 0x0C
+#define ASPEED_JTAG_SW 0x10
+#define ASPEED_JTAG_TCK 0x14
+#define ASPEED_JTAG_EC 0x18
+
+#define ASPEED_JTAG_DATA_MSB 0x01
+#define ASPEED_JTAG_DATA_CHUNK_SIZE 0x20
+
+/* ASPEED_JTAG_CTRL: Engine Control */
+#define ASPEED_JTAG_CTL_ENG_EN BIT(31)
+#define ASPEED_JTAG_CTL_ENG_OUT_EN BIT(30)
+#define ASPEED_JTAG_CTL_FORCE_TMS BIT(29)
+#define ASPEED_JTAG_CTL_INST_LEN(x) ((x) << 20)
+#define ASPEED_JTAG_CTL_LASPEED_INST BIT(17)
+#define ASPEED_JTAG_CTL_INST_EN BIT(16)
+#define ASPEED_JTAG_CTL_DR_UPDATE BIT(10)
+#define ASPEED_JTAG_CTL_DATA_LEN(x) ((x) << 4)
+#define ASPEED_JTAG_CTL_LASPEED_DATA BIT(1)
+#define ASPEED_JTAG_CTL_DATA_EN BIT(0)
+
+/* ASPEED_JTAG_ISR : Interrupt status and enable */
+#define ASPEED_JTAG_ISR_INST_PAUSE BIT(19)
+#define ASPEED_JTAG_ISR_INST_COMPLETE BIT(18)
+#define ASPEED_JTAG_ISR_DATA_PAUSE BIT(17)
+#define ASPEED_JTAG_ISR_DATA_COMPLETE BIT(16)
+#define ASPEED_JTAG_ISR_INST_PAUSE_EN BIT(3)
+#define ASPEED_JTAG_ISR_INST_COMPLETE_EN BIT(2)
+#define ASPEED_JTAG_ISR_DATA_PAUSE_EN BIT(1)
+#define ASPEED_JTAG_ISR_DATA_COMPLETE_EN BIT(0)
+#define ASPEED_JTAG_ISR_INT_EN_MASK GENMASK(3, 0)
+#define ASPEED_JTAG_ISR_INT_MASK GENMASK(19, 16)
+
+/* ASPEED_JTAG_SW : Software Mode and Status */
+#define ASPEED_JTAG_SW_MODE_EN BIT(19)
+#define ASPEED_JTAG_SW_MODE_TCK BIT(18)
+#define ASPEED_JTAG_SW_MODE_TMS BIT(17)
+#define ASPEED_JTAG_SW_MODE_TDIO BIT(16)
+
+/* ASPEED_JTAG_TCK : TCK Control */
+#define ASPEED_JTAG_TCK_DIVISOR_MASK GENMASK(10, 0)
+#define ASPEED_JTAG_TCK_GET_DIV(x) ((x) & ASPEED_JTAG_TCK_DIVISOR_MASK)
+
+/* ASPEED_JTAG_EC : Controller set for go to IDLE */
+#define ASPEED_JTAG_EC_GO_IDLE BIT(0)
+
+#define ASPEED_JTAG_IOUT_LEN(len) \
+ (ASPEED_JTAG_CTL_ENG_EN | \
+ ASPEED_JTAG_CTL_ENG_OUT_EN | \
+ ASPEED_JTAG_CTL_INST_LEN(len))
+
+#define ASPEED_JTAG_DOUT_LEN(len) \
+ (ASPEED_JTAG_CTL_ENG_EN | \
+ ASPEED_JTAG_CTL_ENG_OUT_EN | \
+ ASPEED_JTAG_CTL_DATA_LEN(len))
+
+#define ASPEED_JTAG_SW_TDIO (ASPEED_JTAG_SW_MODE_EN | ASPEED_JTAG_SW_MODE_TDIO)
+
+#define ASPEED_JTAG_GET_TDI(direction, byte) \
+ ((direction == JTAG_READ_XFER) ? UINT_MAX : byte)
+
+#define ASPEED_JTAG_TCK_WAIT 10
+#define ASPEED_JTAG_RESET_CNTR 10
+
+#define ASPEED_JTAG_NAME "jtag-aspeed"
+
+struct aspeed_jtag {
+ void __iomem *reg_base;
+ struct device *dev;
+ struct clk *pclk;
+ enum jtag_endstate status;
+ int irq;
+ struct reset_control *rst;
+ u32 flag;
+ wait_queue_head_t jtag_wq;
+ u32 mode;
+};
+
+static char *end_status_str[] = {"idle", "ir pause", "drpause"};
+
+static u32 aspeed_jtag_read(struct aspeed_jtag *aspeed_jtag, u32 reg)
+{
+ return readl(aspeed_jtag->reg_base + reg);
+}
+
+static void
+aspeed_jtag_write(struct aspeed_jtag *aspeed_jtag, u32 val, u32 reg)
+{
+ writel(val, aspeed_jtag->reg_base + reg);
+}
+
+static int aspeed_jtag_freq_set(struct jtag *jtag, u32 freq)
+{
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+ unsigned long apb_frq;
+ u32 tck_val;
+ u16 div;
+
+ apb_frq = clk_get_rate(aspeed_jtag->pclk);
+ if (!apb_frq)
+ return -ENOTSUPP;
+
+ div = (apb_frq - 1) / freq;
+ tck_val = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_TCK);
+ aspeed_jtag_write(aspeed_jtag,
+ (tck_val & ASPEED_JTAG_TCK_DIVISOR_MASK) | div,
+ ASPEED_JTAG_TCK);
+ return 0;
+}
+
+static int aspeed_jtag_freq_get(struct jtag *jtag, u32 *frq)
+{
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+ u32 pclk;
+ u32 tck;
+
+ pclk = clk_get_rate(aspeed_jtag->pclk);
+ tck = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_TCK);
+ *frq = pclk / (ASPEED_JTAG_TCK_GET_DIV(tck) + 1);
+
+ return 0;
+}
+
+static int aspeed_jtag_mode_set(struct jtag *jtag, u32 mode)
+{
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+
+ aspeed_jtag->mode = mode;
+ return 0;
+}
+
+static void aspeed_jtag_sw_delay(struct aspeed_jtag *aspeed_jtag, int cnt)
+{
+ int i;
+
+ for (i = 0; i < cnt; i++)
+ aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_SW);
+}
+
+static char aspeed_jtag_tck_cycle(struct aspeed_jtag *aspeed_jtag,
+ u8 tms, u8 tdi)
+{
+ char tdo = 0;
+
+ /* TCK = 0 */
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
+ (tms * ASPEED_JTAG_SW_MODE_TMS) |
+ (tdi * ASPEED_JTAG_SW_MODE_TDIO), ASPEED_JTAG_SW);
+
+ ndelay(ASPEED_JTAG_TCK_WAIT);
+ aspeed_jtag_sw_delay(aspeed_jtag, ASPEED_JTAG_TCK_WAIT);
+
+ /* TCK = 1 */
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
+ ASPEED_JTAG_SW_MODE_TCK |
+ (tms * ASPEED_JTAG_SW_MODE_TMS) |
+ (tdi * ASPEED_JTAG_SW_MODE_TDIO), ASPEED_JTAG_SW);
+
+ if (aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_SW) &
+ ASPEED_JTAG_SW_MODE_TDIO)
+ tdo = 1;
+
+ aspeed_jtag_sw_delay(aspeed_jtag, ASPEED_JTAG_TCK_WAIT);
+
+ /* TCK = 0 */
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_MODE_EN |
+ (tms * ASPEED_JTAG_SW_MODE_TMS) |
+ (tdi * ASPEED_JTAG_SW_MODE_TDIO), ASPEED_JTAG_SW);
+ return tdo;
+}
+
+static void aspeed_jtag_wait_instruction_pause(struct aspeed_jtag *aspeed_jtag)
+{
+ wait_event_interruptible(aspeed_jtag->jtag_wq,
+ aspeed_jtag->flag & ASPEED_JTAG_ISR_INST_PAUSE);
+ aspeed_jtag->flag &= ~ASPEED_JTAG_ISR_INST_PAUSE;
+}
+
+static void
+aspeed_jtag_wait_instruction_complete(struct aspeed_jtag *aspeed_jtag)
+{
+ wait_event_interruptible(aspeed_jtag->jtag_wq,
+ aspeed_jtag->flag & ASPEED_JTAG_ISR_INST_COMPLETE);
+ aspeed_jtag->flag &= ~ASPEED_JTAG_ISR_INST_COMPLETE;
+}
+
+static void
+aspeed_jtag_wait_data_pause_complete(struct aspeed_jtag *aspeed_jtag)
+{
+ wait_event_interruptible(aspeed_jtag->jtag_wq,
+ aspeed_jtag->flag & ASPEED_JTAG_ISR_DATA_PAUSE);
+ aspeed_jtag->flag &= ~ASPEED_JTAG_ISR_DATA_PAUSE;
+}
+
+static void aspeed_jtag_wait_data_complete(struct aspeed_jtag *aspeed_jtag)
+{
+ wait_event_interruptible(aspeed_jtag->jtag_wq,
+ aspeed_jtag->flag & ASPEED_JTAG_ISR_DATA_COMPLETE);
+ aspeed_jtag->flag &= ~ASPEED_JTAG_ISR_DATA_COMPLETE;
+}
+
+static void aspeed_jtag_sm_cycle(struct aspeed_jtag *aspeed_jtag,
+ const u8 *tms, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ aspeed_jtag_tck_cycle(aspeed_jtag, tms[i], 0);
+}
+
+static void aspeed_jtag_run_idle(struct aspeed_jtag *aspeed_jtag,
+ struct jtag_run_test_idle *runtest)
+{
+ static const u8 sm_idle_irpause[] = {1, 1, 0, 1, 0};
+ static const u8 sm_idle_drpause[] = {1, 0, 1, 0};
+
+ switch (runtest->endstate) {
+ case JTAG_STATE_PAUSEIR:
+ /* ->DRSCan->IRSCan->IRCap->IRExit1->PauseIR */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_idle_irpause,
+ sizeof(sm_idle_irpause));
+ aspeed_jtag->status = JTAG_STATE_PAUSEIR;
+ break;
+ case JTAG_STATE_PAUSEDR:
+ /* ->DRSCan->DRCap->DRExit1->PauseDR */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_idle_drpause,
+ sizeof(sm_idle_drpause));
+
+ aspeed_jtag->status = JTAG_STATE_PAUSEDR;
+ break;
+ case JTAG_STATE_IDLE:
+ /* IDLE */
+ aspeed_jtag_tck_cycle(aspeed_jtag, 0, 0);
+ aspeed_jtag->status = JTAG_STATE_IDLE;
+ break;
+ default:
+ break;
+ }
+}
+
+static void aspeed_jtag_run_pause(struct aspeed_jtag *aspeed_jtag,
+ struct jtag_run_test_idle *runtest)
+{
+ static const u8 sm_pause_irpause[] = {1, 1, 1, 1, 0, 1, 0};
+ static const u8 sm_pause_drpause[] = {1, 1, 1, 0, 1, 0};
+ static const u8 sm_pause_idle[] = {1, 1, 0};
+
+ /* From IR/DR Pa.use */
+ switch (runtest->endstate) {
+ case JTAG_STATE_PAUSEIR:
+ /*
+ * to Exit2 IR/DR->Updt IR/DR->DRSCan->IRSCan->IRCap->
+ * IRExit1->PauseIR
+ */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_pause_irpause,
+ sizeof(sm_pause_irpause));
+
+ aspeed_jtag->status = JTAG_STATE_PAUSEIR;
+ break;
+ case JTAG_STATE_PAUSEDR:
+ /*
+ * to Exit2 IR/DR->Updt IR/DR->DRSCan->DRCap->
+ * DRExit1->PauseDR
+ */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_pause_drpause,
+ sizeof(sm_pause_drpause));
+ aspeed_jtag->status = JTAG_STATE_PAUSEDR;
+ break;
+ case JTAG_STATE_IDLE:
+ /* to Exit2 IR/DR->Updt IR/DR->IDLE */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_pause_idle,
+ sizeof(sm_pause_idle));
+ aspeed_jtag->status = JTAG_STATE_IDLE;
+ break;
+ default:
+ break;
+ }
+}
+
+static void aspeed_jtag_run_test_idle_sw(struct aspeed_jtag *aspeed_jtag,
+ struct jtag_run_test_idle *runtest)
+{
+ int i;
+
+ /* SW mode from idle/pause-> to pause/idle */
+ if (runtest->reset) {
+ for (i = 0; i < ASPEED_JTAG_RESET_CNTR; i++)
+ aspeed_jtag_tck_cycle(aspeed_jtag, 1, 0);
+ }
+
+ switch (aspeed_jtag->status) {
+ case JTAG_STATE_IDLE:
+ aspeed_jtag_run_idle(aspeed_jtag, runtest);
+ break;
+
+ case JTAG_STATE_PAUSEIR:
+ /* Fall-through */
+ case JTAG_STATE_PAUSEDR:
+ aspeed_jtag_run_pause(aspeed_jtag, runtest);
+ break;
+
+ default:
+ dev_err(aspeed_jtag->dev, "aspeed_jtag_run_test_idle error\n");
+ break;
+ }
+
+ /* Stay on IDLE for at least TCK cycle */
+ for (i = 0; i < runtest->tck; i++)
+ aspeed_jtag_tck_cycle(aspeed_jtag, 0, 0);
+}
+
+static int aspeed_jtag_idle(struct jtag *jtag,
+ struct jtag_run_test_idle *runtest)
+{
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+
+ dev_dbg(aspeed_jtag->dev, "runtest, status:%d, mode:%s, state:%s, reset:%d, tck:%d\n",
+ aspeed_jtag->status,
+ aspeed_jtag->mode & JTAG_XFER_HW_MODE ? "HW" : "SW",
+ end_status_str[runtest->endstate], runtest->reset,
+ runtest->tck);
+
+ if (!(aspeed_jtag->mode & JTAG_XFER_HW_MODE)) {
+ aspeed_jtag_run_test_idle_sw(aspeed_jtag, runtest);
+ return 0;
+ }
+
+ /* Disable sw mode */
+ aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_SW);
+ /* x TMS high + 1 TMS low */
+ if (runtest->reset)
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_CTL_ENG_EN |
+ ASPEED_JTAG_CTL_ENG_OUT_EN |
+ ASPEED_JTAG_CTL_FORCE_TMS, ASPEED_JTAG_CTRL);
+ else
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_EC_GO_IDLE,
+ ASPEED_JTAG_EC);
+
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_TDIO, ASPEED_JTAG_SW);
+
+ aspeed_jtag->status = JTAG_STATE_IDLE;
+ return 0;
+}
+
+static void aspeed_jtag_xfer_sw(struct aspeed_jtag *aspeed_jtag,
+ struct jtag_xfer *xfer, u32 *data)
+{
+ static const u8 sm_update_shiftir[] = { 1, 1, 0, 0 };
+ static const u8 sm_update_shiftdr[] = { 1, 0, 0 };
+ static const u8 sm_pause_idle[] = { 1, 1, 0 };
+ static const u8 sm_pause_update[] = { 1, 1 };
+ unsigned long remain_xfer = xfer->length;
+ unsigned long shift_bits = 0;
+ unsigned long index = 0;
+ unsigned long tdi;
+ char tdo;
+
+ if (aspeed_jtag->status != JTAG_STATE_IDLE) {
+ /*IR/DR Pause->Exit2 IR / DR->Update IR /DR */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_pause_update,
+ sizeof(sm_pause_update));
+ }
+
+ if (xfer->type == JTAG_SIR_XFER)
+ /* ->IRSCan->CapIR->ShiftIR */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_update_shiftir,
+ sizeof(sm_update_shiftir));
+ else
+ /* ->DRScan->DRCap->DRShift */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_update_shiftdr,
+ sizeof(sm_update_shiftdr));
+
+ tdi = ASPEED_JTAG_GET_TDI(xfer->direction, data[index]);
+
+ while (remain_xfer > 1) {
+ tdo = aspeed_jtag_tck_cycle(aspeed_jtag, 0,
+ tdi & ASPEED_JTAG_DATA_MSB);
+ data[index] |= tdo << (shift_bits %
+ ASPEED_JTAG_DATA_CHUNK_SIZE);
+
+ tdi >>= 1;
+ shift_bits++;
+ remain_xfer--;
+
+ if (shift_bits % ASPEED_JTAG_DATA_CHUNK_SIZE == 0) {
+ tdo = 0;
+ index++;
+
+ tdi = ASPEED_JTAG_GET_TDI(xfer->direction, data[index]);
+ }
+ }
+
+ tdo = aspeed_jtag_tck_cycle(aspeed_jtag, 1, tdi & ASPEED_JTAG_DATA_MSB);
+ data[index] |= tdo << (shift_bits % ASPEED_JTAG_DATA_CHUNK_SIZE);
+
+ /* DIPause/DRPause */
+ aspeed_jtag_tck_cycle(aspeed_jtag, 0, 0);
+
+ if (xfer->endstate == JTAG_STATE_IDLE) {
+ /* ->DRExit2->DRUpdate->IDLE */
+ aspeed_jtag_sm_cycle(aspeed_jtag, sm_pause_idle,
+ sizeof(sm_pause_idle));
+ }
+}
+
+static void aspeed_jtag_xfer_push_data(struct aspeed_jtag *aspeed_jtag,
+ enum jtag_xfer_type type, u32 bits_len)
+{
+ if (type == JTAG_SIR_XFER) {
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_IOUT_LEN(bits_len),
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_DOUT_LEN(bits_len) |
+ ASPEED_JTAG_CTL_INST_EN, ASPEED_JTAG_CTRL);
+ } else {
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_DOUT_LEN(bits_len),
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_DOUT_LEN(bits_len) |
+ ASPEED_JTAG_CTL_DATA_EN, ASPEED_JTAG_CTRL);
+ }
+}
+
+static void aspeed_jtag_xfer_push_data_last(struct aspeed_jtag *aspeed_jtag,
+ enum jtag_xfer_type type,
+ u32 shift_bits,
+ enum jtag_endstate endstate)
+{
+ if (endstate == JTAG_STATE_IDLE) {
+ if (type == JTAG_SIR_XFER) {
+ dev_dbg(aspeed_jtag->dev, "IR Keep Pause\n");
+
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_IOUT_LEN(shift_bits),
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_IOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_INST_EN,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_wait_instruction_pause(aspeed_jtag);
+ } else {
+ dev_dbg(aspeed_jtag->dev, "DR Keep Pause\n");
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_DOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_DR_UPDATE,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_DOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_DR_UPDATE |
+ ASPEED_JTAG_CTL_DATA_EN,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_wait_data_pause_complete(aspeed_jtag);
+ }
+ } else {
+ if (type == JTAG_SIR_XFER) {
+ dev_dbg(aspeed_jtag->dev, "IR go IDLE\n");
+
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_IOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_LASPEED_INST,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_IOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_LASPEED_INST |
+ ASPEED_JTAG_CTL_INST_EN,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_wait_instruction_complete(aspeed_jtag);
+ } else {
+ dev_dbg(aspeed_jtag->dev, "DR go IDLE\n");
+
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_DOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_LASPEED_DATA,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag,
+ ASPEED_JTAG_DOUT_LEN(shift_bits) |
+ ASPEED_JTAG_CTL_LASPEED_DATA |
+ ASPEED_JTAG_CTL_DATA_EN,
+ ASPEED_JTAG_CTRL);
+ aspeed_jtag_wait_data_complete(aspeed_jtag);
+ }
+ }
+}
+
+static void aspeed_jtag_xfer_hw(struct aspeed_jtag *aspeed_jtag,
+ struct jtag_xfer *xfer, u32 *data)
+{
+ unsigned long remain_xfer = xfer->length;
+ unsigned long index = 0;
+ char shift_bits;
+ u32 data_reg;
+
+ data_reg = xfer->type == JTAG_SIR_XFER ?
+ ASPEED_JTAG_INST : ASPEED_JTAG_DATA;
+ while (remain_xfer) {
+ if (xfer->direction == JTAG_WRITE_XFER)
+ aspeed_jtag_write(aspeed_jtag, data[index], data_reg);
+ else
+ aspeed_jtag_write(aspeed_jtag, 0, data_reg);
+
+ if (remain_xfer > ASPEED_JTAG_DATA_CHUNK_SIZE) {
+ shift_bits = ASPEED_JTAG_DATA_CHUNK_SIZE;
+
+ /*
+ * Read bytes were not equals to column length
+ * and go to Pause-DR
+ */
+ aspeed_jtag_xfer_push_data(aspeed_jtag, xfer->type,
+ shift_bits);
+ } else {
+ /*
+ * Read bytes equals to column length =>
+ * Update-DR
+ */
+ shift_bits = remain_xfer;
+ aspeed_jtag_xfer_push_data_last(aspeed_jtag, xfer->type,
+ shift_bits,
+ xfer->endstate);
+ }
+
+ if (xfer->direction == JTAG_READ_XFER) {
+ if (shift_bits < ASPEED_JTAG_DATA_CHUNK_SIZE) {
+ data[index] = aspeed_jtag_read(aspeed_jtag,
+ data_reg);
+
+ data[index] >>= ASPEED_JTAG_DATA_CHUNK_SIZE -
+ shift_bits;
+ } else {
+ data[index] = aspeed_jtag_read(aspeed_jtag,
+ data_reg);
+ }
+ }
+
+ remain_xfer = remain_xfer - shift_bits;
+ index++;
+ }
+}
+
+static int aspeed_jtag_xfer(struct jtag *jtag, struct jtag_xfer *xfer,
+ u8 *xfer_data)
+{
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+
+ dev_dbg(aspeed_jtag->dev, " %s %s xfer, mode:%s, END:%d, len:%d\n",
+ xfer->type == JTAG_SIR_XFER ? "SIR" : "SDR",
+ xfer->direction == JTAG_READ_XFER ? "READ" : "WRITE",
+ aspeed_jtag->mode & JTAG_XFER_HW_MODE ? "HW" : "SW",
+ xfer->endstate, xfer->length);
+
+ if (!(aspeed_jtag->mode & JTAG_XFER_HW_MODE)) {
+ /* SW mode */
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_TDIO, ASPEED_JTAG_SW);
+
+ aspeed_jtag_xfer_sw(aspeed_jtag, xfer, (u32 *)xfer_data);
+ } else {
+ /* HW mode */
+ aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_SW);
+ aspeed_jtag_xfer_hw(aspeed_jtag, xfer, (u32 *)xfer_data);
+ }
+
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_TDIO, ASPEED_JTAG_SW);
+ aspeed_jtag->status = xfer->endstate;
+ return 0;
+}
+
+static int aspeed_jtag_status_get(struct jtag *jtag, u32 *status)
+{
+ struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag);
+
+ *status = aspeed_jtag->status;
+ return 0;
+}
+
+static irqreturn_t aspeed_jtag_interrupt(s32 this_irq, void *dev_id)
+{
+ struct aspeed_jtag *aspeed_jtag = dev_id;
+ irqreturn_t ret;
+ u32 status;
+
+ status = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_ISR);
+
+ if (status & ASPEED_JTAG_ISR_INT_MASK) {
+ aspeed_jtag_write(aspeed_jtag,
+ (status & ASPEED_JTAG_ISR_INT_MASK)
+ | (status & ASPEED_JTAG_ISR_INT_EN_MASK),
+ ASPEED_JTAG_ISR);
+ aspeed_jtag->flag |= status & ASPEED_JTAG_ISR_INT_MASK;
+ }
+
+ if (aspeed_jtag->flag) {
+ wake_up_interruptible(&aspeed_jtag->jtag_wq);
+ ret = IRQ_HANDLED;
+ } else {
+ dev_err(aspeed_jtag->dev, "irq status:%x\n",
+ status);
+ ret = IRQ_NONE;
+ }
+ return ret;
+}
+
+static int aspeed_jtag_init(struct platform_device *pdev,
+ struct aspeed_jtag *aspeed_jtag)
+{
+ struct resource *res;
+ int err;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ aspeed_jtag->reg_base = devm_ioremap_resource(aspeed_jtag->dev, res);
+ if (IS_ERR(aspeed_jtag->reg_base))
+ return -ENOMEM;
+
+ aspeed_jtag->pclk = devm_clk_get(aspeed_jtag->dev, NULL);
+ if (IS_ERR(aspeed_jtag->pclk)) {
+ dev_err(aspeed_jtag->dev, "devm_clk_get failed\n");
+ return PTR_ERR(aspeed_jtag->pclk);
+ }
+
+ aspeed_jtag->irq = platform_get_irq(pdev, 0);
+ if (aspeed_jtag->irq < 0) {
+ dev_err(aspeed_jtag->dev, "no irq specified\n");
+ return -ENOENT;
+ }
+
+ if (clk_prepare_enable(aspeed_jtag->pclk)) {
+ dev_err(aspeed_jtag->dev, "no irq specified\n");
+ return -ENOENT;
+ }
+
+ aspeed_jtag->rst = devm_reset_control_get_shared(&pdev->dev, NULL);
+ if (IS_ERR(aspeed_jtag->rst)) {
+ dev_err(aspeed_jtag->dev,
+ "missing or invalid reset controller device tree entry");
+ return PTR_ERR(aspeed_jtag->rst);
+ }
+ reset_control_deassert(aspeed_jtag->rst);
+
+ /* Enable clock */
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_CTL_ENG_EN |
+ ASPEED_JTAG_CTL_ENG_OUT_EN, ASPEED_JTAG_CTRL);
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_TDIO, ASPEED_JTAG_SW);
+
+ err = devm_request_irq(aspeed_jtag->dev, aspeed_jtag->irq,
+ aspeed_jtag_interrupt, 0,
+ "aspeed-jtag", aspeed_jtag);
+ if (err) {
+ dev_err(aspeed_jtag->dev, "unable to get IRQ");
+ goto clk_unprep;
+ }
+
+ aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_ISR_INST_PAUSE |
+ ASPEED_JTAG_ISR_INST_COMPLETE |
+ ASPEED_JTAG_ISR_DATA_PAUSE |
+ ASPEED_JTAG_ISR_DATA_COMPLETE |
+ ASPEED_JTAG_ISR_INST_PAUSE_EN |
+ ASPEED_JTAG_ISR_INST_COMPLETE_EN |
+ ASPEED_JTAG_ISR_DATA_PAUSE_EN |
+ ASPEED_JTAG_ISR_DATA_COMPLETE_EN,
+ ASPEED_JTAG_ISR);
+
+ aspeed_jtag->flag = 0;
+ aspeed_jtag->mode = 0;
+ init_waitqueue_head(&aspeed_jtag->jtag_wq);
+ return 0;
+
+clk_unprep:
+ clk_disable_unprepare(aspeed_jtag->pclk);
+ return err;
+}
+
+static int aspeed_jtag_deinit(struct platform_device *pdev,
+ struct aspeed_jtag *aspeed_jtag)
+{
+ aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_ISR);
+ /* Disable clock */
+ aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_CTRL);
+ reset_control_assert(aspeed_jtag->rst);
+ clk_disable_unprepare(aspeed_jtag->pclk);
+ return 0;
+}
+
+static const struct jtag_ops aspeed_jtag_ops = {
+ .freq_get = aspeed_jtag_freq_get,
+ .freq_set = aspeed_jtag_freq_set,
+ .status_get = aspeed_jtag_status_get,
+ .idle = aspeed_jtag_idle,
+ .xfer = aspeed_jtag_xfer,
+ .mode_set = aspeed_jtag_mode_set
+};
+
+static int aspeed_jtag_probe(struct platform_device *pdev)
+{
+ struct aspeed_jtag *aspeed_jtag;
+ struct jtag *jtag;
+ int err;
+
+ jtag = jtag_alloc(&pdev->dev, sizeof(*aspeed_jtag), &aspeed_jtag_ops);
+ if (!jtag)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, jtag);
+ aspeed_jtag = jtag_priv(jtag);
+ aspeed_jtag->dev = &pdev->dev;
+
+ /* Initialize device*/
+ err = aspeed_jtag_init(pdev, aspeed_jtag);
+ if (err)
+ goto err_jtag_init;
+
+ /* Initialize JTAG core structure*/
+ err = devm_jtag_register(aspeed_jtag->dev, jtag);
+ if (err)
+ goto err_jtag_register;
+
+ return 0;
+
+err_jtag_register:
+ aspeed_jtag_deinit(pdev, aspeed_jtag);
+err_jtag_init:
+ jtag_free(jtag);
+ return err;
+}
+
+static int aspeed_jtag_remove(struct platform_device *pdev)
+{
+ struct jtag *jtag = platform_get_drvdata(pdev);
+
+ aspeed_jtag_deinit(pdev, jtag_priv(jtag));
+ return 0;
+}
+
+static const struct of_device_id aspeed_jtag_of_match[] = {
+ { .compatible = "aspeed,ast2400-jtag", },
+ { .compatible = "aspeed,ast2500-jtag", },
+ {}
+};
+
+static struct platform_driver aspeed_jtag_driver = {
+ .probe = aspeed_jtag_probe,
+ .remove = aspeed_jtag_remove,
+ .driver = {
+ .name = ASPEED_JTAG_NAME,
+ .of_match_table = aspeed_jtag_of_match,
+ },
+};
+module_platform_driver(aspeed_jtag_driver);
+
+MODULE_AUTHOR("Oleksandr Shamray <oleksandrs@mellanox.com>");
+MODULE_DESCRIPTION("ASPEED JTAG driver");
+MODULE_LICENSE("GPL v2");
--
1.7.1
^ permalink raw reply related
* [patch v22 1/4] drivers: jtag: Add JTAG core driver
From: Oleksandr Shamray @ 2018-05-28 12:00 UTC (permalink / raw)
To: gregkh, arnd
Cc: linux-kernel, linux-arm-kernel, devicetree, openbmc, joel, jiri,
tklauser, linux-serial, system-sw-low-level, robh+dt,
openocd-devel-owner, linux-api, davem, mchehab, Oleksandr Shamray
In-Reply-To: <1527508827-30724-1-git-send-email-oleksandrs@mellanox.com>
Initial patch for JTAG driver
JTAG class driver provide infrastructure to support hardware/software
JTAG platform drivers. It provide user layer API interface for flashing
and debugging external devices which equipped with JTAG interface
using standard transactions.
Driver exposes set of IOCTL to user space for:
- XFER:
- SIR (Scan Instruction Register, IEEE 1149.1 Data Register scan);
- SDR (Scan Data Register, IEEE 1149.1 Instruction Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks).
- SIOCFREQ/GIOCFREQ for setting and reading JTAG frequency.
Driver core provides set of internal APIs for allocation and
registration:
- jtag_register;
- jtag_unregister;
- jtag_alloc;
- jtag_free;
Platform driver on registration with jtag-core creates the next
entry in dev folder:
/dev/jtagX
Signed-off-by: Oleksandr Shamray <oleksandrs@mellanox.com>
Signed-off-by: Jiri Pirko <jiri@mellanox.com>
Acked-by: Philippe Ombredanne <pombredanne@nexb.com>
---
v21->v22
Comments pointed by Andy Shevchenko <andy.shevchenko@gmail.com>
- Fix 0x0f -> 0x0F in ioctl-number.txt
- Add description to #define MAX_JTAG_NAME_LEN
- Remove unnecessary entry *dev from struct jtag
- Remove redundant parens
- Described mandatory callbacks and removed unnecessary
- Set JTAG_MAX_XFER_DATA_LEN to power of 2
- rework driver alloc/register to devm_ variant
- increasing line length up to 84 in order to improve readability.
Comments pointed by Randy Dunlap <rdunlap@infradead.org>
- fix spell in ABI doccumentation
v20->v21
Comments pointed by Randy Dunlap <rdunlap@infradead.org>
- Fix JTAG dirver help in Kconfig
v19->v20
Comments pointed by Randy Dunlap <rdunlap@infradead.org>
- Fix JTAG dirver help in Kconfig
Notifications from kbuild test robot <lkp@intel.com>
- fix incompatible type casts
v18->v19
Comments pointed by Julia Cartwright <juliac@eso.teric.us>
- Fix memory leak on jtag_alloc exit
v17->v18
Comments pointed by Julia Cartwright <juliac@eso.teric.us>
- Change to return -EOPNOTSUPP in case of error in JTAG_GIOCFREQ
- Add ops callbacks check to jtag_alloc
- Add err check for copy_to_user
- Move the kfree() above the if (err) in JTAG_IOCXFER
- remove unnecessary check for error after put_user
- add padding to struct jtag_xfer
v16->v17
Comments pointed by Julia Cartwright <juliac@eso.teric.us>
- Fix memory allocation on jtag alloc
- Move out unnecessary form lock on jtag open
- Rework jtag register behavior
v15->v16
Comments pointed by Florian Fainelli <f.fainelli@gmail.com>
- move check jtag->ops->* in ioctl before get_user()
- change error type -EINVAL --> -EBUSY on open already opened jtag
- remove unnecessary ARCH_DMA_MINALIGN flag from kzalloc
- remove define ARCH_DMA_MINALIGN
v14->v15
v13->v14
Comments pointed by Philippe Ombredanne <pombredanne@nexb.com>
- Change style of head block comment from /**/ to //
v12->v13
Comments pointed by Philippe Ombredanne <pombredanne@nexb.com>
- Change jtag.c licence type to
SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
and reorder line with license in description
v11->v12
Comments pointed by Greg KH <gregkh@linuxfoundation.org>
- Change jtag.h licence type to
SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
and reorder line with license in description
Comments pointed by Chip Bilbrey <chip@bilbrey.org>
- Remove Apeed reference from uapi jtag.h header
- Remove access mode from xfer and idle transactions
- Add new ioctl JTAG_SIOCMODE for set hw mode
- Add single open per device blocking
v10->v11
Notifications from kbuild test robot <lkp@intel.com>
- Add include types.h header to jtag.h
- fix incompatible type of xfer callback
- remove rdundant class defination
- Fix return order in case of xfer error
V9->v10
Comments pointed by Greg KH <gregkh@linuxfoundation.org>
- remove unnecessary alignment for pirv data
- move jtag_copy_to_user and jtag_copy_from_user code just to ioctl
- move int jtag_run_test_idle_op and jtag_xfer_op code
just to ioctl
- change return error codes to more applicable
- add missing error checks
- fix error check order in ioctl
- remove unnecessary blank lines
- add param validation to ioctl
- remove compat_ioctl
- remove only one open per JTAG port blocking.
User will care about this.
- Fix idr memory leak on jtag_exit
- change cdev device type to misc
V8->v9
Comments pointed by Arnd Bergmann <arnd@arndb.de>
- use get_user() instead of __get_user().
- change jtag->open type from int to atomic_t
- remove spinlock on jtg_open
- remove mutex on jtag_register
- add unregister_chrdev_region on jtag_init err
- add unregister_chrdev_region on jtag_exit
- remove unnecessary pointer casts
- add *data parameter to xfer function prototype
v7->v8
Comments pointed by Moritz Fischer <moritz.fischer@ettus.com>
- Fix misspelling s/friver/driver
v6->v7
Notifications from kbuild test robot <lkp@intel.com>
- Remove include asm/types.h from jtag.h
- Add include <linux/types.h> to jtag.c
v5->v6
v4->v5
v3->v4
Comments pointed by Arnd Bergmann <arnd@arndb.de>
- change transaction pointer tdio type to __u64
- change internal status type from enum to __u32
- reorder jtag_xfer members to avoid the implied padding
- add __packed attribute to jtag_xfer and jtag_run_test_idle
v2->v3
Notifications from kbuild test robot <lkp@intel.com>
- Change include path to <linux/types.h> in jtag.h
v1->v2
Comments pointed by Greg KH <gregkh@linuxfoundation.org>
- Change license type from GPLv2/BSD to GPLv2
- Change type of variables which crossed user/kernel to __type
- Remove "default n" from Kconfig
Comments pointed by Andrew Lunn <andrew@lunn.ch>
- Change list_add_tail in jtag_unregister to list_del
Comments pointed by Neil Armstrong <narmstrong@baylibre.com>
- Add SPDX-License-Identifier instead of license text
Comments pointed by Arnd Bergmann <arnd@arndb.de>
- Change __copy_to_user to memdup_user
- Change __put_user to put_user
- Change type of variables to __type for compatible 32 and 64-bit systems
- Add check for maximum xfer data size
- Change lookup data mechanism to get jtag data from inode
- Add .compat_ioctl to file ops
- Add mem alignment for jtag priv data
Comments pointed by Tobias Klauser <tklauser@distanz.ch>
- Change function names to avoid match with variable types
- Fix description for jtag_ru_test_idle in uapi jtag.h
- Fix misprints IDEL/IDLE, trough/through
---
Documentation/ioctl/ioctl-number.txt | 2 +
MAINTAINERS | 8 +
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/jtag/Kconfig | 17 ++
drivers/jtag/Makefile | 1 +
drivers/jtag/jtag.c | 322 ++++++++++++++++++++++++++++++++++
include/linux/jtag.h | 42 +++++
include/uapi/linux/jtag.h | 102 +++++++++++
9 files changed, 497 insertions(+), 0 deletions(-)
create mode 100644 drivers/jtag/Kconfig
create mode 100644 drivers/jtag/Makefile
create mode 100644 drivers/jtag/jtag.c
create mode 100644 include/linux/jtag.h
create mode 100644 include/uapi/linux/jtag.h
diff --git a/Documentation/ioctl/ioctl-number.txt b/Documentation/ioctl/ioctl-number.txt
index 7f7413e..886e676 100644
--- a/Documentation/ioctl/ioctl-number.txt
+++ b/Documentation/ioctl/ioctl-number.txt
@@ -318,6 +318,8 @@ Code Seq#(hex) Include File Comments
0xB0 all RATIO devices in development:
<mailto:vgo@ratio.de>
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
+0xB2 00-0F linux/jtag.h JTAG driver
+ <mailto:oleksandrs@mellanox.com>
0xB3 00 linux/mmc/ioctl.h
0xB4 00-0F linux/gpio.h <mailto:linux-gpio@vger.kernel.org>
0xB5 00-0F uapi/linux/rpmsg.h <mailto:linux-remoteproc@vger.kernel.org>
diff --git a/MAINTAINERS b/MAINTAINERS
index 79bb02f..e7b8b2c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7610,6 +7610,14 @@ L: linux-serial@vger.kernel.org
S: Maintained
F: drivers/tty/serial/jsm/
+JTAG SUBSYSTEM
+M: Oleksandr Shamray <oleksandrs@mellanox.com>
+M: Vadim Pasternak <vadimp@mellanox.com>
+S: Maintained
+F: include/linux/jtag.h
+F: include/uapi/linux/jtag.h
+F: drivers/jtag/
+
K10TEMP HARDWARE MONITORING DRIVER
M: Clemens Ladisch <clemens@ladisch.de>
L: linux-hwmon@vger.kernel.org
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 95b9ccc..bb71e48 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -217,4 +217,6 @@ source "drivers/siox/Kconfig"
source "drivers/slimbus/Kconfig"
+source "drivers/jtag/Kconfig"
+
endmenu
diff --git a/drivers/Makefile b/drivers/Makefile
index 24cd470..c92636b 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -185,3 +185,4 @@ obj-$(CONFIG_TEE) += tee/
obj-$(CONFIG_MULTIPLEXER) += mux/
obj-$(CONFIG_UNISYS_VISORBUS) += visorbus/
obj-$(CONFIG_SIOX) += siox/
+obj-$(CONFIG_JTAG) += jtag/
diff --git a/drivers/jtag/Kconfig b/drivers/jtag/Kconfig
new file mode 100644
index 0000000..47771fc
--- /dev/null
+++ b/drivers/jtag/Kconfig
@@ -0,0 +1,17 @@
+menuconfig JTAG
+ tristate "JTAG support"
+ help
+ This provides basic core functionality support for JTAG class devices.
+ Hardware that is equipped with a JTAG microcontroller can be
+ supported by using this driver's interfaces.
+ This driver exposes a set of IOCTLs to the user space for
+ the following commands:
+ SDR: Performs an IEEE 1149.1 Data Register scan
+ SIR: Performs an IEEE 1149.1 Instruction Register scan.
+ RUNTEST: Forces the IEEE 1149.1 bus to a run state for a specified
+ number of clocks or a specified time period.
+
+ If you want this support, you should say Y here.
+
+ To compile this driver as a module, choose M here: the module will
+ be called jtag.
diff --git a/drivers/jtag/Makefile b/drivers/jtag/Makefile
new file mode 100644
index 0000000..af37493
--- /dev/null
+++ b/drivers/jtag/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_JTAG) += jtag.o
diff --git a/drivers/jtag/jtag.c b/drivers/jtag/jtag.c
new file mode 100644
index 0000000..f1e666b
--- /dev/null
+++ b/drivers/jtag/jtag.c
@@ -0,0 +1,322 @@
+// SPDX-License-Identifier: GPL-2.0-only
+// drivers/jtag/jtag.c
+//
+// Copyright (c) 2018 Mellanox Technologies. All rights reserved.
+// Copyright (c) 2018 Oleksandr Shamray <oleksandrs@mellanox.com>
+
+#include <linux/cdev.h>
+#include <linux/device.h>
+#include <linux/jtag.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/rtnetlink.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <uapi/linux/jtag.h>
+
+/*
+ * JTAG core driver supports up to 256 devices
+ * JTAG device name will be in range jtag0-jtag255
+ * Set maximum len of jtag id to 3
+ */
+
+#define MAX_JTAG_DEVS 255
+#define MAX_JTAG_NAME_LEN (sizeof("jtag") + 3)
+
+struct jtag {
+ struct miscdevice miscdev;
+ const struct jtag_ops *ops;
+ int id;
+ bool opened;
+ struct mutex open_lock;
+ unsigned long priv[0];
+};
+
+static DEFINE_IDA(jtag_ida);
+
+static atomic_t jtag_refcount = ATOMIC_INIT(0);
+
+void *jtag_priv(struct jtag *jtag)
+{
+ return jtag->priv;
+}
+EXPORT_SYMBOL_GPL(jtag_priv);
+
+static long jtag_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
+{
+ struct jtag *jtag = file->private_data;
+ struct jtag_run_test_idle idle;
+ struct jtag_xfer xfer;
+ u8 *xfer_data;
+ u32 data_size;
+ u32 value;
+ int err;
+
+ if (!arg)
+ return -EINVAL;
+
+ switch (cmd) {
+ case JTAG_GIOCFREQ:
+ if (!jtag->ops->freq_get)
+ return -EOPNOTSUPP;
+
+ err = jtag->ops->freq_get(jtag, &value);
+ if (err)
+ break;
+
+ if (put_user(value, (__u32 __user *)arg))
+ err = -EFAULT;
+ break;
+
+ case JTAG_SIOCFREQ:
+ if (!jtag->ops->freq_set)
+ return -EOPNOTSUPP;
+
+ if (get_user(value, (__u32 __user *)arg))
+ return -EFAULT;
+ if (value == 0)
+ return -EINVAL;
+
+ err = jtag->ops->freq_set(jtag, value);
+ break;
+
+ case JTAG_IOCRUNTEST:
+ if (copy_from_user(&idle, (const void __user *)arg,
+ sizeof(struct jtag_run_test_idle)))
+ return -EFAULT;
+
+ if (idle.endstate > JTAG_STATE_PAUSEDR)
+ return -EINVAL;
+
+ err = jtag->ops->idle(jtag, &idle);
+ break;
+
+ case JTAG_IOCXFER:
+ if (copy_from_user(&xfer, (const void __user *)arg,
+ sizeof(struct jtag_xfer)))
+ return -EFAULT;
+
+ if (xfer.length >= JTAG_MAX_XFER_DATA_LEN)
+ return -EINVAL;
+
+ if (xfer.type > JTAG_SDR_XFER)
+ return -EINVAL;
+
+ if (xfer.direction > JTAG_WRITE_XFER)
+ return -EINVAL;
+
+ if (xfer.endstate > JTAG_STATE_PAUSEDR)
+ return -EINVAL;
+
+ data_size = DIV_ROUND_UP(xfer.length, BITS_PER_BYTE);
+ xfer_data = memdup_user(u64_to_user_ptr(xfer.tdio), data_size);
+
+ if (IS_ERR(xfer_data))
+ return -EFAULT;
+
+ err = jtag->ops->xfer(jtag, &xfer, xfer_data);
+ if (err) {
+ kfree(xfer_data);
+ return -EFAULT;
+ }
+
+ err = copy_to_user(u64_to_user_ptr(xfer.tdio),
+ (void *)xfer_data, data_size);
+ kfree(xfer_data);
+ if (err)
+ return -EFAULT;
+
+ if (copy_to_user((void __user *)arg, (void *)&xfer,
+ sizeof(struct jtag_xfer)))
+ return -EFAULT;
+ break;
+
+ case JTAG_GIOCSTATUS:
+ err = jtag->ops->status_get(jtag, &value);
+ if (err)
+ break;
+
+ err = put_user(value, (__u32 __user *)arg);
+ break;
+ case JTAG_SIOCMODE:
+ if (!jtag->ops->mode_set)
+ return -EOPNOTSUPP;
+
+ if (get_user(value, (__u32 __user *)arg))
+ return -EFAULT;
+ if (value == 0)
+ return -EINVAL;
+
+ err = jtag->ops->mode_set(jtag, value);
+ break;
+
+ default:
+ return -EINVAL;
+ }
+ return err;
+}
+
+static int jtag_open(struct inode *inode, struct file *file)
+{
+ struct jtag *jtag = container_of(file->private_data, struct jtag, miscdev);
+
+ if (mutex_lock_interruptible(&jtag->open_lock))
+ return -ERESTARTSYS;
+
+ if (jtag->opened) {
+ mutex_unlock(&jtag->open_lock);
+ return -EBUSY;
+ }
+ jtag->opened = true;
+ mutex_unlock(&jtag->open_lock);
+
+ nonseekable_open(inode, file);
+ file->private_data = jtag;
+ return 0;
+}
+
+static int jtag_release(struct inode *inode, struct file *file)
+{
+ struct jtag *jtag = file->private_data;
+
+ mutex_lock(&jtag->open_lock);
+ jtag->opened = false;
+ mutex_unlock(&jtag->open_lock);
+ return 0;
+}
+
+static const struct file_operations jtag_fops = {
+ .owner = THIS_MODULE,
+ .open = jtag_open,
+ .release = jtag_release,
+ .llseek = noop_llseek,
+ .unlocked_ioctl = jtag_ioctl,
+};
+
+struct jtag *jtag_alloc(struct device *host, size_t priv_size,
+ const struct jtag_ops *ops)
+{
+ struct jtag *jtag;
+
+ if (!host)
+ return NULL;
+
+ if (!ops)
+ return NULL;
+
+ if (!ops->idle || !ops->status_get || !ops->xfer)
+ return NULL;
+
+ jtag = kzalloc(sizeof(*jtag) + priv_size, GFP_KERNEL);
+ if (!jtag)
+ return NULL;
+
+ jtag->ops = ops;
+ jtag->miscdev.parent = host;
+
+ return jtag;
+}
+EXPORT_SYMBOL_GPL(jtag_alloc);
+
+void jtag_free(struct jtag *jtag)
+{
+ kfree(jtag);
+}
+EXPORT_SYMBOL_GPL(jtag_free);
+
+static int jtag_register(struct jtag *jtag)
+{
+ struct device *dev = jtag->miscdev.parent;
+ char *name;
+ int err;
+ int id;
+
+ if (!dev)
+ return -ENODEV;
+
+ if (atomic_read(&jtag_refcount) >= MAX_JTAG_DEVS)
+ return -ENOSPC;
+
+ id = ida_simple_get(&jtag_ida, 0, 0, GFP_KERNEL);
+ if (id < 0)
+ return id;
+
+ jtag->id = id;
+ jtag->opened = false;
+
+ name = kzalloc(MAX_JTAG_NAME_LEN, GFP_KERNEL);
+ if (!name) {
+ err = -ENOMEM;
+ goto err_jtag_alloc;
+ }
+
+ err = snprintf(name, MAX_JTAG_NAME_LEN, "jtag%d", id);
+ if (err < 0)
+ goto err_jtag_name;
+
+ mutex_init(&jtag->open_lock);
+ jtag->miscdev.fops = &jtag_fops;
+ jtag->miscdev.minor = MISC_DYNAMIC_MINOR;
+ jtag->miscdev.name = name;
+
+ err = misc_register(&jtag->miscdev);
+ if (err) {
+ dev_err(jtag->miscdev.parent, "Unable to register device\n");
+ goto err_jtag_name;
+ }
+ pr_info("%s %d\n", __func__, __LINE__);
+ atomic_inc(&jtag_refcount);
+ return 0;
+
+err_jtag_name:
+ kfree(name);
+err_jtag_alloc:
+ ida_simple_remove(&jtag_ida, id);
+ return err;
+}
+
+static void jtag_unregister(struct jtag *jtag)
+{
+ misc_deregister(&jtag->miscdev);
+ kfree(jtag->miscdev.name);
+ ida_simple_remove(&jtag_ida, jtag->id);
+ atomic_dec(&jtag_refcount);
+}
+
+static void devm_jtag_unregister(struct device *dev, void *res)
+{
+ jtag_unregister(*(struct jtag **)res);
+}
+
+int devm_jtag_register(struct device *dev, struct jtag *jtag)
+{
+ struct jtag **ptr;
+ int ret;
+
+ ptr = devres_alloc(devm_jtag_unregister, sizeof(*ptr), GFP_KERNEL);
+ if (!ptr)
+ return -ENOMEM;
+
+ ret = jtag_register(jtag);
+ if (!ret) {
+ *ptr = jtag;
+ devres_add(dev, ptr);
+ } else {
+ devres_free(ptr);
+ }
+ return ret;
+}
+EXPORT_SYMBOL_GPL(devm_jtag_register);
+
+static void __exit jtag_exit(void)
+{
+ ida_destroy(&jtag_ida);
+}
+
+module_exit(jtag_exit);
+
+MODULE_AUTHOR("Oleksandr Shamray <oleksandrs@mellanox.com>");
+MODULE_DESCRIPTION("Generic jtag support");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/jtag.h b/include/linux/jtag.h
new file mode 100644
index 0000000..555812e
--- /dev/null
+++ b/include/linux/jtag.h
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0
+// include/linux/jtag.h - JTAG class driver
+//
+// Copyright (c) 2018 Mellanox Technologies. All rights reserved.
+// Copyright (c) 2018 Oleksandr Shamray <oleksandrs@mellanox.com>
+
+#ifndef __JTAG_H
+#define __JTAG_H
+
+#include <uapi/linux/jtag.h>
+
+#define jtag_u64_to_ptr(arg) ((void *)(uintptr_t)arg)
+
+#define JTAG_MAX_XFER_DATA_LEN 65535
+
+struct jtag;
+/**
+ * struct jtag_ops - callbacks for JTAG control functions:
+ *
+ * @freq_get: get frequency function. Filled by dev driver
+ * @freq_set: set frequency function. Filled by dev driver
+ * @status_get: set status function. Mandatory func. Filled by dev driver
+ * @idle: set JTAG to idle state function. Mandatory func. Filled by dev driver
+ * @xfer: send JTAG xfer function. Mandatory func. Filled by dev driver
+ * @mode_set: set specific work mode for JTAG. Filled by dev driver
+ */
+struct jtag_ops {
+ int (*freq_get)(struct jtag *jtag, u32 *freq);
+ int (*freq_set)(struct jtag *jtag, u32 freq);
+ int (*status_get)(struct jtag *jtag, u32 *state);
+ int (*idle)(struct jtag *jtag, struct jtag_run_test_idle *idle);
+ int (*xfer)(struct jtag *jtag, struct jtag_xfer *xfer, u8 *xfer_data);
+ int (*mode_set)(struct jtag *jtag, u32 mode_mask);
+};
+
+void *jtag_priv(struct jtag *jtag);
+int devm_jtag_register(struct device *dev, struct jtag *jtag);
+struct jtag *jtag_alloc(struct device *host, size_t priv_size,
+ const struct jtag_ops *ops);
+void jtag_free(struct jtag *jtag);
+
+#endif /* __JTAG_H */
diff --git a/include/uapi/linux/jtag.h b/include/uapi/linux/jtag.h
new file mode 100644
index 0000000..8bbf1a7
--- /dev/null
+++ b/include/uapi/linux/jtag.h
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+// include/uapi/linux/jtag.h - JTAG class driver uapi
+//
+// Copyright (c) 2018 Mellanox Technologies. All rights reserved.
+// Copyright (c) 2018 Oleksandr Shamray <oleksandrs@mellanox.com>
+
+#ifndef __UAPI_LINUX_JTAG_H
+#define __UAPI_LINUX_JTAG_H
+
+/*
+ * JTAG_XFER_HW_MODE: JTAG hardware mode. Used to set HW drived or bitbang
+ * mode. This is bitmask param of ioctl JTAG_SIOCMODE command
+ */
+#define JTAG_XFER_HW_MODE 1
+
+/**
+ * enum jtag_endstate:
+ *
+ * @JTAG_STATE_IDLE: JTAG state machine IDLE state
+ * @JTAG_STATE_PAUSEIR: JTAG state machine PAUSE_IR state
+ * @JTAG_STATE_PAUSEDR: JTAG state machine PAUSE_DR state
+ */
+enum jtag_endstate {
+ JTAG_STATE_IDLE,
+ JTAG_STATE_PAUSEIR,
+ JTAG_STATE_PAUSEDR,
+};
+
+/**
+ * enum jtag_xfer_type:
+ *
+ * @JTAG_SIR_XFER: SIR transfer
+ * @JTAG_SDR_XFER: SDR transfer
+ */
+enum jtag_xfer_type {
+ JTAG_SIR_XFER,
+ JTAG_SDR_XFER,
+};
+
+/**
+ * enum jtag_xfer_direction:
+ *
+ * @JTAG_READ_XFER: read transfer
+ * @JTAG_WRITE_XFER: write transfer
+ */
+enum jtag_xfer_direction {
+ JTAG_READ_XFER,
+ JTAG_WRITE_XFER,
+};
+
+/**
+ * struct jtag_run_test_idle - forces JTAG state machine to
+ * RUN_TEST/IDLE state
+ *
+ * @reset: 0 - run IDLE/PAUSE from current state
+ * 1 - go through TEST_LOGIC/RESET state before IDLE/PAUSE
+ * @end: completion flag
+ * @tck: clock counter
+ *
+ * Structure provide interface to JTAG device for JTAG IDLE execution.
+ */
+struct jtag_run_test_idle {
+ __u8 reset;
+ __u8 endstate;
+ __u8 tck;
+};
+
+/**
+ * struct jtag_xfer - jtag xfer:
+ *
+ * @type: transfer type
+ * @direction: xfer direction
+ * @length: xfer bits len
+ * @tdio : xfer data array
+ * @endir: xfer end state
+ *
+ * Structure provide interface to JTAG device for JTAG SDR/SIR xfer execution.
+ */
+struct jtag_xfer {
+ __u8 type;
+ __u8 direction;
+ __u8 endstate;
+ __u8 padding;
+ __u32 length;
+ __u64 tdio;
+};
+
+/* ioctl interface */
+#define __JTAG_IOCTL_MAGIC 0xb2
+
+#define JTAG_IOCRUNTEST _IOW(__JTAG_IOCTL_MAGIC, 0,\
+ struct jtag_run_test_idle)
+#define JTAG_SIOCFREQ _IOW(__JTAG_IOCTL_MAGIC, 1, unsigned int)
+#define JTAG_GIOCFREQ _IOR(__JTAG_IOCTL_MAGIC, 2, unsigned int)
+#define JTAG_IOCXFER _IOWR(__JTAG_IOCTL_MAGIC, 3, struct jtag_xfer)
+#define JTAG_GIOCSTATUS _IOWR(__JTAG_IOCTL_MAGIC, 4, enum jtag_endstate)
+#define JTAG_SIOCMODE _IOW(__JTAG_IOCTL_MAGIC, 5, unsigned int)
+
+#define JTAG_FIRST_MINOR 0
+#define JTAG_MAX_DEVICES 32
+
+#endif /* __UAPI_LINUX_JTAG_H */
--
1.7.1
^ permalink raw reply related
* [patch v22 0/4] JTAG driver introduction
From: Oleksandr Shamray @ 2018-05-28 12:00 UTC (permalink / raw)
To: gregkh, arnd
Cc: linux-kernel, linux-arm-kernel, devicetree, openbmc, joel, jiri,
tklauser, linux-serial, system-sw-low-level, robh+dt,
openocd-devel-owner, linux-api, davem, mchehab, Oleksandr Shamray
When a need raise up to use JTAG interface for system's devices
programming or CPU debugging, usually the user layer
application implements jtag protocol by bit-bang or using a
proprietary connection to vendor hardware.
This method can be slow and not generic.
We propose to implement general JTAG interface and infrastructure
to communicate with user layer application. In such way, we can
have the standard JTAG interface core part and separation from
specific HW implementation.
This allow new capability to debug the CPU or program system's
device via BMC without additional devices nor cost.
This patch purpose is to add JTAG master core infrastructure by
defining new JTAG class and provide generic JTAG interface
to allow hardware specific drivers to connect this interface.
This will enable all JTAG drivers to use the common interface
part and will have separate for hardware implementation.
The JTAG (Joint Test Action Group) core driver provides minimal generic
JTAG interface, which can be used by hardware specific JTAG master
controllers. By providing common interface for the JTAG controllers,
user space device programing is hardware independent.
Modern SoC which in use for embedded system' equipped with
internal JTAG master interface.
This interface is used for programming and debugging system's
hardware components, like CPLD, FPGA, CPU, voltage and
industrial controllers.
Firmware for such devices can be upgraded through JTAG interface during
Runtime. The JTAG standard support for multiple devices programming,
is in case their lines are daisy-chained together.
For example, systems which equipped with host CPU, BMC SoC or/and
number of programmable devices are capable to connect a pin and
select system components dynamically for programming and debugging,
This is using by the BMC which is equipped with internal SoC master
controller.
For example:
BMC JTAG master --> pin selected to CPLDs chain for programming (filed
upgrade, production)
BMC JTAG master --> pin selected to voltage monitors for programming
(field upgrade, production)
BMC JTAG master --> pin selected to host CPU (on-site debugging
and developers debugging)
For example, we can have application in user space which using calls
to JTAG driver executes CPLD programming directly from SVF file
The JTAG standard (IEEE 1149.1) defines the next connector pins:
- TDI (Test Data In);
- TDO (Test Data Out);
- TCK (Test Clock);
- TMS (Test Mode Select);
- TRST (Test Reset) (Optional);
The SoC equipped with JTAG master controller, performs
device programming on command or vector level. For example
a file in a standard SVF (Serial Vector Format) that contains
boundary scan vectors, can be used by sending each vector
to the JTAG interface and the JTAG controller will execute
the programming.
Initial version provides the system calls set for:
- SIR (Scan Instruction Register, IEEE 1149.1 Instruction Register scan);
- SDR (Scan Data Register, IEEE 1149.1 Data Register scan);
- RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified
number of clocks.
SoC which are not equipped with JTAG master interface, can be built
on top of JTAG core driver infrastructure, by applying bit-banging of
TDI, TDO, TCK and TMS pins within the hardware specific driver.
Oleksandr Shamray (4):
drivers: jtag: Add JTAG core driver
drivers: jtag: Add Aspeed SoC 24xx and 25xx families JTAG master
driver
Documentation: jtag: Add bindings for Aspeed SoC 24xx and 25xx
families JTAG master driver
Documentation: jtag: Add ABI documentation
Documentation/ABI/testing/jtag-dev | 27 +
.../devicetree/bindings/jtag/aspeed-jtag.txt | 22 +
Documentation/ioctl/ioctl-number.txt | 2 +
Documentation/jtag/overview | 28 +
Documentation/jtag/transactions | 109 +++
MAINTAINERS | 10 +
drivers/Kconfig | 2 +
drivers/Makefile | 1 +
drivers/jtag/Kconfig | 31 +
drivers/jtag/Makefile | 2 +
drivers/jtag/jtag-aspeed.c | 769 ++++++++++++++++++++
drivers/jtag/jtag.c | 322 ++++++++
include/linux/jtag.h | 42 ++
include/uapi/linux/jtag.h | 102 +++
14 files changed, 1469 insertions(+), 0 deletions(-)
create mode 100644 Documentation/ABI/testing/jtag-dev
create mode 100644 Documentation/devicetree/bindings/jtag/aspeed-jtag.txt
create mode 100644 Documentation/jtag/overview
create mode 100644 Documentation/jtag/transactions
create mode 100644 drivers/jtag/Kconfig
create mode 100644 drivers/jtag/Makefile
create mode 100644 drivers/jtag/jtag-aspeed.c
create mode 100644 drivers/jtag/jtag.c
create mode 100644 include/linux/jtag.h
create mode 100644 include/uapi/linux/jtag.h
^ permalink raw reply
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