* [PATCH v3] PCI: mediatek: Add system pm support for MT2712
From: honghui.zhang @ 2018-06-01 3:04 UTC (permalink / raw)
To: lorenzo.pieralisi, marc.zyngier, bhelgaas, matthias.bgg,
linux-arm-kernel, linux-mediatek, linux-pci, linux-kernel,
devicetree, yingjoe.chen, eddie.huang, ryder.lee
Cc: honghui.zhang, hongkun.cao, youlin.pei, yong.wu, yt.shen,
sean.wang, xinping.qian
From: Honghui Zhang <honghui.zhang@mediatek.com>
The MTCMOS of PCIe Host for MT2712 will be off when system suspend, and all
the internal control register will be reset after system resume. The PCIe
link should be re-established and the related control register values
should be re-set after system resume.
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
CC: Ryder Lee <ryder.lee@mediatek.com>
---
drivers/pci/host/pcie-mediatek.c | 60 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c
index dabf1086..5363cc7 100644
--- a/drivers/pci/host/pcie-mediatek.c
+++ b/drivers/pci/host/pcie-mediatek.c
@@ -132,12 +132,14 @@ struct mtk_pcie_port;
/**
* struct mtk_pcie_soc - differentiate between host generations
* @need_fix_class_id: whether this host's class ID needed to be fixed or not
+ * @pm_support: whether the host's MTCMOS will be off when suspend
* @ops: pointer to configuration access functions
* @startup: pointer to controller setting functions
* @setup_irq: pointer to initialize IRQ functions
*/
struct mtk_pcie_soc {
bool need_fix_class_id;
+ bool pm_support;
struct pci_ops *ops;
int (*startup)(struct mtk_pcie_port *port);
int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
@@ -1179,12 +1181,69 @@ static int mtk_pcie_probe(struct platform_device *pdev)
return err;
}
+#ifdef CONFIG_PM_SLEEP
+static int mtk_pcie_suspend_noirq(struct device *dev)
+{
+ struct mtk_pcie *pcie = dev_get_drvdata(dev);
+ const struct mtk_pcie_soc *soc = pcie->soc;
+ struct mtk_pcie_port *port;
+
+ if (!soc->pm_support)
+ return 0;
+
+ list_for_each_entry(port, &pcie->ports, list) {
+ clk_disable_unprepare(port->ahb_ck);
+ clk_disable_unprepare(port->sys_ck);
+ phy_power_off(port->phy);
+ }
+
+ return 0;
+}
+
+static int mtk_pcie_resume_noirq(struct device *dev)
+{
+ struct mtk_pcie *pcie = dev_get_drvdata(dev);
+ const struct mtk_pcie_soc *soc = pcie->soc;
+ struct mtk_pcie_port *port;
+ int ret;
+
+ if (!soc->pm_support)
+ return 0;
+
+ list_for_each_entry(port, &pcie->ports, list) {
+ phy_power_on(port->phy);
+ clk_prepare_enable(port->sys_ck);
+ clk_prepare_enable(port->ahb_ck);
+
+ ret = soc->startup(port);
+ if (ret) {
+ dev_err(dev, "Port%d link down\n", port->slot);
+ phy_power_off(port->phy);
+ clk_disable_unprepare(port->sys_ck);
+ clk_disable_unprepare(port->ahb_ck);
+ return ret;
+ }
+
+ if (IS_ENABLED(CONFIG_PCI_MSI))
+ mtk_pcie_enable_msi(port);
+ }
+
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops mtk_pcie_pm_ops = {
+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
+ mtk_pcie_resume_noirq)
+};
+
static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
.ops = &mtk_pcie_ops,
.startup = mtk_pcie_startup_port,
};
static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = {
+ .pm_support = true,
.ops = &mtk_pcie_ops_v2,
.startup = mtk_pcie_startup_port_v2,
.setup_irq = mtk_pcie_setup_irq,
@@ -1211,6 +1270,7 @@ static struct platform_driver mtk_pcie_driver = {
.name = "mtk-pcie",
.of_match_table = mtk_pcie_ids,
.suppress_bind_attrs = true,
+ .pm = &mtk_pcie_pm_ops,
},
};
builtin_platform_driver(mtk_pcie_driver);
--
2.6.4
^ permalink raw reply related
* Re: [PATCH v3 2/5] gpio: syscon: rockchip: add GPIO_MUTE support for rk3328
From: Levin @ 2018-06-01 2:05 UTC (permalink / raw)
To: Rob Herring
Cc: open list:ARM/Rockchip SoC..., Wayne Chou, Heiko Stuebner,
devicetree, Linus Walleij, linux-kernel@vger.kernel.org,
open list:GPIO SUBSYSTEM, Mark Rutland,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE, Levin
In-Reply-To: <CAL_JsqJK4vrmLBeN_ZeGCXAyqshshL16B0KN_+8uvt+=-O9TEw@mail.gmail.com>
Hi Rob,
On 2018-05-31 10:45 PM, Rob Herring wrote:
> On Wed, May 30, 2018 at 10:27 PM, <djw@t-chip.com.cn> wrote:
>> From: Levin Du <djw@t-chip.com.cn>
>>
>> In Rockchip RK3328, the output only GPIO_MUTE pin, originally for codec
>> mute control, can also be used for general purpose. It is manipulated by
>> the GRF_SOC_CON10 register.
>>
>> Signed-off-by: Levin Du <djw@t-chip.com.cn>
>>
>> ---
>>
>> Changes in v3:
>> - Change from general gpio-syscon to specific rk3328-gpio-mute
>>
>> Changes in v2:
>> - Rename gpio_syscon10 to gpio_mute in doc
>>
>> Changes in v1:
>> - Refactured for general gpio-syscon usage for Rockchip SoCs.
>> - Add doc rockchip,gpio-syscon.txt
>>
>> .../bindings/gpio/rockchip,rk3328-gpio-mute.txt | 28 +++++++++++++++++++
>> drivers/gpio/gpio-syscon.c | 31 ++++++++++++++++++++++
>> 2 files changed, 59 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/gpio/rockchip,rk3328-gpio-mute.txt
>>
>> diff --git a/Documentation/devicetree/bindings/gpio/rockchip,rk3328-gpio-mute.txt b/Documentation/devicetree/bindings/gpio/rockchip,rk3328-gpio-mute.txt
>> new file mode 100644
>> index 0000000..10bc632
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/gpio/rockchip,rk3328-gpio-mute.txt
>> @@ -0,0 +1,28 @@
>> +Rockchip RK3328 GPIO controller dedicated for the GPIO_MUTE pin.
>> +
>> +In Rockchip RK3328, the output only GPIO_MUTE pin, originally for codec mute
>> +control, can also be used for general purpose. It is manipulated by the
>> +GRF_SOC_CON10 register.
>> +
>> +Required properties:
>> +- compatible: Should contain "rockchip,rk3328-gpio-mute".
>> +- gpio-controller: Marks the device node as a gpio controller.
>> +- #gpio-cells: Should be 2. The first cell is the pin number and
>> + the second cell is used to specify the gpio polarity:
>> + 0 = Active high,
>> + 1 = Active low.
>> +
>> +Example:
>> +
>> + grf: syscon@ff100000 {
>> + compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
>> +
>> + gpio_mute: gpio-mute {
> Node names should be generic:
>
> gpio {
>
> This also means you can't add another GPIO node in the future and
> you'll have to live with "rockchip,rk3328-gpio-mute" covering more
> than 1 GPIO if you do need to add more GPIOs.
As the first line describes, this GPIO controller is dedicated for the
GPIO_MUTE pin.
There's only one GPIO pin in the GRF_SOC_CON10 register. Therefore the
gpio_mute
name is proper IMHO.
>> + compatible = "rockchip,rk3328-gpio-mute";
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + };
>> + };
>> +
>> +Note: The gpio_mute node should be declared as the child of the GRF (General
>> +Register File) node. The GPIO_MUTE pin is referred to as <&gpio_mute 0>.
> This is wrong because you should have 2 cells. The phandle doesn't
> count as a cell.
>
> Rob
>
Thanks for pointing that out. So it should be:
The GPIO_MUTE pin is referred to as <&gpio_mute 0 POLARITY>.
Thanks,
Levin
^ permalink raw reply
* Re: [PATCH 1/2] power: supply: sbs-battery: don't assume MANUFACTURER_DATA formats
From: Guenter Roeck @ 2018-06-01 1:20 UTC (permalink / raw)
To: Brian Norris, Sebastian Reichel
Cc: linux-kernel, Rob Herring, linux-pm, devicetree, Alexandru Stan,
Doug Anderson
In-Reply-To: <20180601003252.42810-1-briannorris@chromium.org>
Hi Brian,
On 05/31/2018 05:32 PM, Brian Norris wrote:
> This driver was originally submitted for the TI BQ20Z75 battery IC
> (commit a7640bfa10c5 ("power_supply: Add driver for TI BQ20Z75 gas gauge
> IC")) and later renamed to express generic SBS support. While it's
> mostly true that this driver implemented a standard SBS command set, it
> takes liberties with the REG_MANUFACTURER_DATA register. This register
> is specified in the SBS spec, but it doesn't make any mention of what
> its actual contents are.
>
> We've sort of noticed this optionality previously, with commit
> 17c6d3979e5b ("sbs-battery: make writes to ManufacturerAccess
> optional"), where we found that some batteries NAK writes to this
> register.
>
> What this really means is that so far, we've just been lucky that most
> batteries have either been compatible with the TI chip, or else at least
> haven't reported highly-unexpected values.
>
> For instance, one battery I have here seems to report either 0x0000 or
> 0x0100 to the MANUFACTURER_ACCESS_STATUS command -- while this seems to
> match either Wake Up (bits[11:8] = 0000b) or Normal Discharge
> (bits[11:8] = 0001b) status for the TI part [1], they don't seem to
> actually correspond to real states (for instance, I never see 0101b =
> Charge, even when charging).
>
> On other batteries, I'm getting apparently random data in return, which
> means that occasionally, we interpret this as "battery not present" or
> "battery is not healthy".
>
> All in all, it seems to be a really bad idea to make assumptions about
> REG_MANUFACTURER_DATA, unless we already know what battery we're using.
> Therefore, this patch reimplements the "present" and "health" checks to
> the following on most SBS batteries:
>
> 1. HEALTH: report "unknown" -- I couldn't find a standard SBS command
> that gives us much useful here
> 2. PRESENT: just send a REG_STATUS command; if it succeeds, then the
> battery is present
>
> Also, we stop sending MANUFACTURER_ACCESS_SLEEP to non-TI parts. I have
> no proof that this is useful and supported.
>
> If someone explicitly provided a 'ti,bq20z75' compatible property, then
> we retain the existing TI command behaviors.
>
> [1] http://www.ti.com/lit/er/sluu265a/sluu265a.pdf
>
Excellent idea. Couple of comments below.
Thanks,
Guenter
> Signed-off-by: Brian Norris <briannorris@chromium.org>
> ---
> drivers/power/supply/sbs-battery.c | 61 +++++++++++++++++++++++++-----
> 1 file changed, 52 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/power/supply/sbs-battery.c b/drivers/power/supply/sbs-battery.c
> index 83d7b4115857..e15d0ca4729d 100644
> --- a/drivers/power/supply/sbs-battery.c
> +++ b/drivers/power/supply/sbs-battery.c
> @@ -23,6 +23,7 @@
> #include <linux/kernel.h>
> #include <linux/module.h>
> #include <linux/of.h>
> +#include <linux/of_device.h>
> #include <linux/power/sbs-battery.h>
> #include <linux/power_supply.h>
> #include <linux/slab.h>
> @@ -84,8 +85,9 @@ static const struct chip_data {
> int min_value;
> int max_value;
> } sbs_data[] = {
> + /* Manuf. data isn't directly useful as a POWER_SUPPLY_PROP */
> [REG_MANUFACTURER_DATA] =
> - SBS_DATA(POWER_SUPPLY_PROP_PRESENT, 0x00, 0, 65535),
> + SBS_DATA(-1, 0x00, 0, 65535),
I don't think this change is necessary. For example, POWER_SUPPLY_PROP_SERIAL_NUMBER
is also not directly accessed, yet the REG_SERIAL_NUMBER array entry includes
POWER_SUPPLY_PROP_SERIAL_NUMBER.
> [REG_TEMPERATURE] =
> SBS_DATA(POWER_SUPPLY_PROP_TEMP, 0x08, 0, 65535),
> [REG_VOLTAGE] =
> @@ -156,6 +158,9 @@ static enum power_supply_property sbs_properties[] = {
> POWER_SUPPLY_PROP_MODEL_NAME
> };
>
> +/* Supports special manufacturer commands from TI BQ20Z75 IC. */
> +#define SBS_FLAGS_TI_BQ20Z75 BIT(0)
> +
> struct sbs_info {
> struct i2c_client *client;
> struct power_supply *power_supply;
> @@ -168,6 +173,7 @@ struct sbs_info {
> u32 poll_retry_count;
> struct delayed_work work;
> struct mutex mode_lock;
> + u32 flags;
> };
>
> static char model_name[I2C_SMBUS_BLOCK_MAX + 1];
> @@ -315,6 +321,31 @@ static int sbs_status_correct(struct i2c_client *client, int *intval)
> static int sbs_get_battery_presence_and_health(
> struct i2c_client *client, enum power_supply_property psp,
> union power_supply_propval *val)
> +{
> + int ret;
> +
> + switch (psp) {
> + case POWER_SUPPLY_PROP_PRESENT:
> + /* Dummy command; if it succeeds, battery is present. */
> + ret = sbs_read_word_data(client, sbs_data[REG_STATUS].addr);
> + if (ret < 0)
> + val->intval = 0; /* battery disconnected */
I don't know the relevance, but the original code returns the error
in this situation.
> + else
> + val->intval = 1; /* battery present */
> + return 0;
> + case POWER_SUPPLY_PROP_HEALTH:
> + /* SBS spec doesn't have a general health command. */
> + val->intval = POWER_SUPPLY_HEALTH_UNKNOWN;
> + return 0;
> + default:
> + dev_err(&client->dev, "unexpected prop %d\n", psp);
> + return -EINVAL;
Personally I would prefer if/else here, for the simple reason that the default case
will never be executed and just wastes a bit of code space.
> + }
> +}
> +
> +static int sbs_get_ti_battery_presence_and_health(
> + struct i2c_client *client, enum power_supply_property psp,
> + union power_supply_propval *val)
> {
> s32 ret;
>
> @@ -600,7 +631,12 @@ static int sbs_get_property(struct power_supply *psy,
> switch (psp) {
> case POWER_SUPPLY_PROP_PRESENT:
> case POWER_SUPPLY_PROP_HEALTH:
> - ret = sbs_get_battery_presence_and_health(client, psp, val);
> + if (client->flags & SBS_FLAGS_TI_BQ20Z75)
> + ret = sbs_get_ti_battery_presence_and_health(client,
> + psp, val);
> + else
> + ret = sbs_get_battery_presence_and_health(client, psp,
> + val);
> if (psp == POWER_SUPPLY_PROP_PRESENT)
> return 0;
> break;
> @@ -806,6 +842,7 @@ static int sbs_probe(struct i2c_client *client,
> if (!chip)
> return -ENOMEM;
>
> + chip->flags = (u32)(uintptr_t)of_device_get_match_data(&client->dev);
> chip->client = client;
> chip->enable_detection = false;
> psy_cfg.of_node = client->dev.of_node;
> @@ -915,12 +952,15 @@ static int sbs_suspend(struct device *dev)
> if (chip->poll_time > 0)
> cancel_delayed_work_sync(&chip->work);
>
> - /*
> - * Write to manufacturer access with sleep command.
> - * Support is manufacturer dependend, so ignore errors.
> - */
> - sbs_write_word_data(client, sbs_data[REG_MANUFACTURER_DATA].addr,
> - MANUFACTURER_ACCESS_SLEEP);
> + if (chip->flags & SBS_FLAGS_TI_BQ20Z75) {
> + /*
> + * Write to manufacturer access with sleep command.
> + * Support is manufacturer dependent, so ignore errors.
> + */
> + sbs_write_word_data(client,
> + sbs_data[REG_MANUFACTURER_DATA].addr,
> + MANUFACTURER_ACCESS_SLEEP);
> + }
>
> return 0;
> }
> @@ -941,7 +981,10 @@ MODULE_DEVICE_TABLE(i2c, sbs_id);
>
> static const struct of_device_id sbs_dt_ids[] = {
> { .compatible = "sbs,sbs-battery" },
> - { .compatible = "ti,bq20z75" },
> + {
> + .compatible = "ti,bq20z75",
> + .data = (void *)SBS_FLAGS_TI_BQ20Z75,
> + },
> { }
> };
> MODULE_DEVICE_TABLE(of, sbs_dt_ids);
>
^ permalink raw reply
* Re: [PATCH] PCI: mediatek: Add system pm support for MT2712
From: kbuild test robot @ 2018-06-01 0:42 UTC (permalink / raw)
Cc: kbuild-all, lorenzo.pieralisi, marc.zyngier, bhelgaas,
matthias.bgg, linux-arm-kernel, linux-mediatek, linux-pci,
linux-kernel, devicetree, yingjoe.chen, eddie.huang, ryder.lee,
honghui.zhang, hongkun.cao, youlin.pei, yong.wu, yt.shen,
sean.wang, xinping.qian
In-Reply-To: <1527647736-19986-1-git-send-email-honghui.zhang@mediatek.com>
Hi Honghui,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on pci/next]
[also build test WARNING on next-20180531]
[cannot apply to v4.17-rc7]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/honghui-zhang-mediatek-com/PCI-mediatek-Add-system-pm-support-for-MT2712/20180601-053217
base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
reproduce:
# apt-get install sparse
make ARCH=x86_64 allmodconfig
make C=1 CF=-D__CHECK_ENDIAN__
sparse warnings: (new ones prefixed by >>)
drivers/pci/host/pcie-mediatek.c:463:40: sparse: incorrect type in argument 1 (different address spaces) @@ expected void volatile *address @@ got void [novoid volatile *address @@
drivers/pci/host/pcie-mediatek.c:463:40: expected void volatile *address
drivers/pci/host/pcie-mediatek.c:463:40: got void [noderef] <asn:2>*
drivers/pci/host/pcie-mediatek.c:586:44: sparse: incorrect type in argument 1 (different address spaces) @@ expected void volatile *address @@ got void [novoid volatile *address @@
drivers/pci/host/pcie-mediatek.c:586:44: expected void volatile *address
drivers/pci/host/pcie-mediatek.c:586:44: got void [noderef] <asn:2>*
>> drivers/pci/host/pcie-mediatek.c:1259:25: sparse: symbol 'mtk_pcie_pm_ops' was not declared. Should it be static?
Please review and possibly fold the followup patch.
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
^ permalink raw reply
* [RFC PATCH] PCI: mediatek: mtk_pcie_pm_ops can be static
From: kbuild test robot @ 2018-06-01 0:42 UTC (permalink / raw)
Cc: kbuild-all, lorenzo.pieralisi, marc.zyngier, bhelgaas,
matthias.bgg, linux-arm-kernel, linux-mediatek, linux-pci,
linux-kernel, devicetree, yingjoe.chen, eddie.huang, ryder.lee,
honghui.zhang, hongkun.cao, youlin.pei, yong.wu, yt.shen,
sean.wang, xinping.qian
In-Reply-To: <1527647736-19986-1-git-send-email-honghui.zhang@mediatek.com>
Fixes: 24dc21cd1e9d ("PCI: mediatek: Add system pm support for MT2712")
Signed-off-by: kbuild test robot <fengguang.wu@intel.com>
---
pcie-mediatek.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c
index e3b16b0..e01cc66 100644
--- a/drivers/pci/host/pcie-mediatek.c
+++ b/drivers/pci/host/pcie-mediatek.c
@@ -1256,7 +1256,7 @@ static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev)
return 0;
}
-const struct dev_pm_ops mtk_pcie_pm_ops = {
+static const struct dev_pm_ops mtk_pcie_pm_ops = {
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
mtk_pcie_resume_noirq)
};
^ permalink raw reply related
* [PATCH 2/2] dt-bindings: power: sbs-battery: re-document "ti,bq20z75"
From: Brian Norris @ 2018-06-01 0:32 UTC (permalink / raw)
To: Sebastian Reichel
Cc: linux-kernel, Rob Herring, linux-pm, devicetree, Alexandru Stan,
Guenter Roeck, Doug Anderson, Brian Norris, Rhyland Klein
In-Reply-To: <20180601003252.42810-1-briannorris@chromium.org>
This compatible property was documented before the driver was renamed to
"SBS" (see commit e57f1b68c406 ("devicetree-bindings: Propagate
bq20z75->sbs rename to dt bindings")). The driver has continued to
support this property as an alternative to "sbs,sbs-battery", and
because we've noticed there are some lingering TI specifics (in the
manufacturer-specific portion of the SBS spec), we'd like to start using
this property again to differentiate.
Cc: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Brian Norris <briannorris@chromium.org>
---
.../devicetree/bindings/power/supply/sbs_sbs-battery.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/power/supply/sbs_sbs-battery.txt b/Documentation/devicetree/bindings/power/supply/sbs_sbs-battery.txt
index c40e8926facf..a7a9c3366f82 100644
--- a/Documentation/devicetree/bindings/power/supply/sbs_sbs-battery.txt
+++ b/Documentation/devicetree/bindings/power/supply/sbs_sbs-battery.txt
@@ -2,7 +2,7 @@ SBS sbs-battery
~~~~~~~~~~
Required properties :
- - compatible : "sbs,sbs-battery"
+ - compatible : "sbs,sbs-battery" or "ti,bq20z75"
Optional properties :
- sbs,i2c-retry-count : The number of times to retry i2c transactions on i2c
--
2.17.0.921.gf22659ad46-goog
^ permalink raw reply related
* [PATCH 1/2] power: supply: sbs-battery: don't assume MANUFACTURER_DATA formats
From: Brian Norris @ 2018-06-01 0:32 UTC (permalink / raw)
To: Sebastian Reichel
Cc: linux-kernel, Rob Herring, linux-pm, devicetree, Alexandru Stan,
Guenter Roeck, Doug Anderson, Brian Norris
This driver was originally submitted for the TI BQ20Z75 battery IC
(commit a7640bfa10c5 ("power_supply: Add driver for TI BQ20Z75 gas gauge
IC")) and later renamed to express generic SBS support. While it's
mostly true that this driver implemented a standard SBS command set, it
takes liberties with the REG_MANUFACTURER_DATA register. This register
is specified in the SBS spec, but it doesn't make any mention of what
its actual contents are.
We've sort of noticed this optionality previously, with commit
17c6d3979e5b ("sbs-battery: make writes to ManufacturerAccess
optional"), where we found that some batteries NAK writes to this
register.
What this really means is that so far, we've just been lucky that most
batteries have either been compatible with the TI chip, or else at least
haven't reported highly-unexpected values.
For instance, one battery I have here seems to report either 0x0000 or
0x0100 to the MANUFACTURER_ACCESS_STATUS command -- while this seems to
match either Wake Up (bits[11:8] = 0000b) or Normal Discharge
(bits[11:8] = 0001b) status for the TI part [1], they don't seem to
actually correspond to real states (for instance, I never see 0101b =
Charge, even when charging).
On other batteries, I'm getting apparently random data in return, which
means that occasionally, we interpret this as "battery not present" or
"battery is not healthy".
All in all, it seems to be a really bad idea to make assumptions about
REG_MANUFACTURER_DATA, unless we already know what battery we're using.
Therefore, this patch reimplements the "present" and "health" checks to
the following on most SBS batteries:
1. HEALTH: report "unknown" -- I couldn't find a standard SBS command
that gives us much useful here
2. PRESENT: just send a REG_STATUS command; if it succeeds, then the
battery is present
Also, we stop sending MANUFACTURER_ACCESS_SLEEP to non-TI parts. I have
no proof that this is useful and supported.
If someone explicitly provided a 'ti,bq20z75' compatible property, then
we retain the existing TI command behaviors.
[1] http://www.ti.com/lit/er/sluu265a/sluu265a.pdf
Signed-off-by: Brian Norris <briannorris@chromium.org>
---
drivers/power/supply/sbs-battery.c | 61 +++++++++++++++++++++++++-----
1 file changed, 52 insertions(+), 9 deletions(-)
diff --git a/drivers/power/supply/sbs-battery.c b/drivers/power/supply/sbs-battery.c
index 83d7b4115857..e15d0ca4729d 100644
--- a/drivers/power/supply/sbs-battery.c
+++ b/drivers/power/supply/sbs-battery.c
@@ -23,6 +23,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/power/sbs-battery.h>
#include <linux/power_supply.h>
#include <linux/slab.h>
@@ -84,8 +85,9 @@ static const struct chip_data {
int min_value;
int max_value;
} sbs_data[] = {
+ /* Manuf. data isn't directly useful as a POWER_SUPPLY_PROP */
[REG_MANUFACTURER_DATA] =
- SBS_DATA(POWER_SUPPLY_PROP_PRESENT, 0x00, 0, 65535),
+ SBS_DATA(-1, 0x00, 0, 65535),
[REG_TEMPERATURE] =
SBS_DATA(POWER_SUPPLY_PROP_TEMP, 0x08, 0, 65535),
[REG_VOLTAGE] =
@@ -156,6 +158,9 @@ static enum power_supply_property sbs_properties[] = {
POWER_SUPPLY_PROP_MODEL_NAME
};
+/* Supports special manufacturer commands from TI BQ20Z75 IC. */
+#define SBS_FLAGS_TI_BQ20Z75 BIT(0)
+
struct sbs_info {
struct i2c_client *client;
struct power_supply *power_supply;
@@ -168,6 +173,7 @@ struct sbs_info {
u32 poll_retry_count;
struct delayed_work work;
struct mutex mode_lock;
+ u32 flags;
};
static char model_name[I2C_SMBUS_BLOCK_MAX + 1];
@@ -315,6 +321,31 @@ static int sbs_status_correct(struct i2c_client *client, int *intval)
static int sbs_get_battery_presence_and_health(
struct i2c_client *client, enum power_supply_property psp,
union power_supply_propval *val)
+{
+ int ret;
+
+ switch (psp) {
+ case POWER_SUPPLY_PROP_PRESENT:
+ /* Dummy command; if it succeeds, battery is present. */
+ ret = sbs_read_word_data(client, sbs_data[REG_STATUS].addr);
+ if (ret < 0)
+ val->intval = 0; /* battery disconnected */
+ else
+ val->intval = 1; /* battery present */
+ return 0;
+ case POWER_SUPPLY_PROP_HEALTH:
+ /* SBS spec doesn't have a general health command. */
+ val->intval = POWER_SUPPLY_HEALTH_UNKNOWN;
+ return 0;
+ default:
+ dev_err(&client->dev, "unexpected prop %d\n", psp);
+ return -EINVAL;
+ }
+}
+
+static int sbs_get_ti_battery_presence_and_health(
+ struct i2c_client *client, enum power_supply_property psp,
+ union power_supply_propval *val)
{
s32 ret;
@@ -600,7 +631,12 @@ static int sbs_get_property(struct power_supply *psy,
switch (psp) {
case POWER_SUPPLY_PROP_PRESENT:
case POWER_SUPPLY_PROP_HEALTH:
- ret = sbs_get_battery_presence_and_health(client, psp, val);
+ if (client->flags & SBS_FLAGS_TI_BQ20Z75)
+ ret = sbs_get_ti_battery_presence_and_health(client,
+ psp, val);
+ else
+ ret = sbs_get_battery_presence_and_health(client, psp,
+ val);
if (psp == POWER_SUPPLY_PROP_PRESENT)
return 0;
break;
@@ -806,6 +842,7 @@ static int sbs_probe(struct i2c_client *client,
if (!chip)
return -ENOMEM;
+ chip->flags = (u32)(uintptr_t)of_device_get_match_data(&client->dev);
chip->client = client;
chip->enable_detection = false;
psy_cfg.of_node = client->dev.of_node;
@@ -915,12 +952,15 @@ static int sbs_suspend(struct device *dev)
if (chip->poll_time > 0)
cancel_delayed_work_sync(&chip->work);
- /*
- * Write to manufacturer access with sleep command.
- * Support is manufacturer dependend, so ignore errors.
- */
- sbs_write_word_data(client, sbs_data[REG_MANUFACTURER_DATA].addr,
- MANUFACTURER_ACCESS_SLEEP);
+ if (chip->flags & SBS_FLAGS_TI_BQ20Z75) {
+ /*
+ * Write to manufacturer access with sleep command.
+ * Support is manufacturer dependent, so ignore errors.
+ */
+ sbs_write_word_data(client,
+ sbs_data[REG_MANUFACTURER_DATA].addr,
+ MANUFACTURER_ACCESS_SLEEP);
+ }
return 0;
}
@@ -941,7 +981,10 @@ MODULE_DEVICE_TABLE(i2c, sbs_id);
static const struct of_device_id sbs_dt_ids[] = {
{ .compatible = "sbs,sbs-battery" },
- { .compatible = "ti,bq20z75" },
+ {
+ .compatible = "ti,bq20z75",
+ .data = (void *)SBS_FLAGS_TI_BQ20Z75,
+ },
{ }
};
MODULE_DEVICE_TABLE(of, sbs_dt_ids);
--
2.17.0.921.gf22659ad46-goog
^ permalink raw reply related
* Re: [PATCH v8 0/7] i2c: Add FSI-attached I2C master algorithm
From: Benjamin Herrenschmidt @ 2018-05-31 23:33 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Eddie James, linux-i2c, Linux Kernel Mailing List, devicetree,
Wolfram Sang, Rob Herring, Joel Stanley, Mark Rutland,
Greg Kroah-Hartman, Randy Dunlap
In-Reply-To: <CAHp75Vec+KZCkjcs3qpB=qLmaTon=yTLyu7S_tDrMGcobHW5eQ@mail.gmail.com>
On Thu, 2018-05-31 at 09:29 +0300, Andy Shevchenko wrote:
> > If you have specific issues with how this is done, please express them
> > clearly. It's quite possible that there's some better way to do what
> > Eddie is doing here, but without *construtive* feedback this is
> > pointless.
>
> It feels like you duplicate approach which is done in OF generic case.
> That is my concern. Though, if Wolfram is telling that is OK, I have
> no objections.
THe OF generic case is about discovering slaves underneath a port, not
ports inside of a mulit-port master.
I am not aware of a generic mechanism for the latter. We *could* make
the ports sub-devices but it gets messy then to arbitrate the
communication and deal with the common part. I've seen (and written)
multi-port masters in the past that use a similar approach to what
Eddie's doing and it works fine.
> > I'm disappointed here because we have an example of somebody rather new
> > producing what is overall pretty damn good code,
>
> That is true. His code much better than many I have seen before
Thanks. Also thanks for taking the time to review.
> > despite a few corner
> > issues, and being (again) treated like crap.
>
> Sorry for that, life is harsh.
>
> > This isn't the right way to operate, and I believe this has been made
> > clear many times before.
>
> Yes.
Cheers,
Ben.
^ permalink raw reply
* [PATCH v3 6/6] ARM: dts: tegra: enable NAND flash on Colibri T20
From: Stefan Agner @ 2018-05-31 22:16 UTC (permalink / raw)
To: boris.brezillon, dwmw2, computersforpeace, marek.vasut, robh+dt,
mark.rutland, thierry.reding
Cc: dev, miquel.raynal, richard, marcel, krzk, digetx,
benjamin.lindqvist, jonathanh, pdeschrijver, pgaikwad, mirza.krak,
stefan, linux-mtd, linux-tegra, devicetree, linux-kernel
In-Reply-To: <20180531221637.6017-1-stefan@agner.ch>
From: Lucas Stach <dev@lynxeye.de>
This enables the on-module ONFI conformant NAND flash.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 5c202b3e3bb1..5a80ee4557db 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -462,6 +462,22 @@
};
};
+ nand@70008000 {
+ status = "okay";
+
+ nand-chip@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ nand-bus-width = <8>;
+ nand-on-flash-bbt;
+ nand-ecc-algo = "bch";
+ nand-is-boot-medium;
+ nand-ecc-maximize;
+ wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+ };
+ };
+
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
--
2.17.0
^ permalink raw reply related
* [PATCH v3 5/6] ARM: dts: tegra: add Tegra20 NAND flash controller node
From: Stefan Agner @ 2018-05-31 22:16 UTC (permalink / raw)
To: boris.brezillon, dwmw2, computersforpeace, marek.vasut, robh+dt,
mark.rutland, thierry.reding
Cc: dev, miquel.raynal, richard, marcel, krzk, digetx,
benjamin.lindqvist, jonathanh, pdeschrijver, pgaikwad, mirza.krak,
stefan, linux-mtd, linux-tegra, devicetree, linux-kernel
In-Reply-To: <20180531221637.6017-1-stefan@agner.ch>
From: Lucas Stach <dev@lynxeye.de>
Add basic controller device tree node to be extended by
individual boards. Use the assigned-clocks mechanism to set
NDFLASH clock to a sensible default rate of 150MHz.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
arch/arm/boot/dts/tegra20.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 0a7136462a1a..64911903ef99 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -425,6 +425,21 @@
status = "disabled";
};
+ nand: nand@70008000 {
+ compatible = "nvidia,tegra20-nand";
+ reg = <0x70008000 0x100>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
+ clock-names = "nand";
+ resets = <&tegra_car 13>;
+ reset-names = "nand";
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
+ assigned-clock-rates = <150000000>;
+ };
+
pwm: pwm@7000a000 {
compatible = "nvidia,tegra20-pwm";
reg = <0x7000a000 0x100>;
--
2.17.0
^ permalink raw reply related
* [PATCH v3 4/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver
From: Stefan Agner @ 2018-05-31 22:16 UTC (permalink / raw)
To: boris.brezillon, dwmw2, computersforpeace, marek.vasut, robh+dt,
mark.rutland, thierry.reding
Cc: dev, miquel.raynal, richard, marcel, krzk, digetx,
benjamin.lindqvist, jonathanh, pdeschrijver, pgaikwad, mirza.krak,
stefan, linux-mtd, linux-tegra, devicetree, linux-kernel
In-Reply-To: <20180531221637.6017-1-stefan@agner.ch>
Add support for the NAND flash controller found on NVIDIA
Tegra 2 SoCs. This implementation does not make use of the
command queue feature. Regular operations/data transfers are
done in PIO mode. Page read/writes with hardware ECC make
use of the DMA for data transfer.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
MAINTAINERS | 7 +
drivers/mtd/nand/raw/Kconfig | 6 +
drivers/mtd/nand/raw/Makefile | 1 +
drivers/mtd/nand/raw/tegra_nand.c | 1143 +++++++++++++++++++++++++++++
4 files changed, 1157 insertions(+)
create mode 100644 drivers/mtd/nand/raw/tegra_nand.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 58b9861ccf99..c2e5571c85d4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13844,6 +13844,13 @@ M: Laxman Dewangan <ldewangan@nvidia.com>
S: Supported
F: drivers/input/keyboard/tegra-kbc.c
+TEGRA NAND DRIVER
+M: Stefan Agner <stefan@agner.ch>
+M: Lucas Stach <dev@lynxeye.de>
+S: Maintained
+F: Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
+F: drivers/mtd/nand/raw/tegra_nand.c
+
TEGRA PWM DRIVER
M: Thierry Reding <thierry.reding@gmail.com>
S: Supported
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 19a2b283fbbe..e9093f52371e 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -534,4 +534,10 @@ config MTD_NAND_MTK
Enables support for NAND controller on MTK SoCs.
This controller is found on mt27xx, mt81xx, mt65xx SoCs.
+config MTD_NAND_TEGRA
+ tristate "Support for NAND controller on NVIDIA Tegra"
+ depends on ARCH_TEGRA || COMPILE_TEST
+ help
+ Enables support for NAND flash controller on NVIDIA Tegra SoC.
+
endif # MTD_NAND
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index 165b7ef9e9a1..d5a5f9832b88 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -56,6 +56,7 @@ obj-$(CONFIG_MTD_NAND_HISI504) += hisi504_nand.o
obj-$(CONFIG_MTD_NAND_BRCMNAND) += brcmnand/
obj-$(CONFIG_MTD_NAND_QCOM) += qcom_nandc.o
obj-$(CONFIG_MTD_NAND_MTK) += mtk_ecc.o mtk_nand.o
+obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o
nand-objs := nand_base.o nand_bbt.o nand_timings.o nand_ids.o
nand-objs += nand_amd.o
diff --git a/drivers/mtd/nand/raw/tegra_nand.c b/drivers/mtd/nand/raw/tegra_nand.c
new file mode 100644
index 000000000000..e9664f2938a3
--- /dev/null
+++ b/drivers/mtd/nand/raw/tegra_nand.c
@@ -0,0 +1,1143 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Stefan Agner <stefan@agner.ch>
+ * Copyright (C) 2014-2015 Lucas Stach <dev@lynxeye.de>
+ * Copyright (C) 2012 Avionic Design GmbH
+ */
+
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/gpio/consumer.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/rawnand.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+#define CMD 0x00
+#define CMD_GO BIT(31)
+#define CMD_CLE BIT(30)
+#define CMD_ALE BIT(29)
+#define CMD_PIO BIT(28)
+#define CMD_TX BIT(27)
+#define CMD_RX BIT(26)
+#define CMD_SEC_CMD BIT(25)
+#define CMD_AFT_DAT BIT(24)
+#define CMD_TRANS_SIZE(x) (((x - 1) & 0xf) << 20)
+#define CMD_A_VALID BIT(19)
+#define CMD_B_VALID BIT(18)
+#define CMD_RD_STATUS_CHK BIT(17)
+#define CMD_RBSY_CHK BIT(16)
+#define CMD_CE(x) BIT((8 + ((x) & 0x7)))
+#define CMD_CLE_SIZE(x) (((x - 1) & 0x3) << 4)
+#define CMD_ALE_SIZE(x) (((x - 1) & 0xf) << 0)
+
+#define STATUS 0x04
+
+#define ISR 0x08
+#define ISR_CORRFAIL_ERR BIT(24)
+#define ISR_UND BIT(7)
+#define ISR_OVR BIT(6)
+#define ISR_CMD_DONE BIT(5)
+#define ISR_ECC_ERR BIT(4)
+
+#define IER 0x0c
+#define IER_ERR_TRIG_VAL(x) (((x) & 0xf) << 16)
+#define IER_UND BIT(7)
+#define IER_OVR BIT(6)
+#define IER_CMD_DONE BIT(5)
+#define IER_ECC_ERR BIT(4)
+#define IER_GIE BIT(0)
+
+#define CFG 0x10
+#define CFG_HW_ECC BIT(31)
+#define CFG_ECC_SEL BIT(30)
+#define CFG_ERR_COR BIT(29)
+#define CFG_PIPE_EN BIT(28)
+#define CFG_TVAL_4 (0 << 24)
+#define CFG_TVAL_6 (1 << 24)
+#define CFG_TVAL_8 (2 << 24)
+#define CFG_SKIP_SPARE BIT(23)
+#define CFG_BUS_WIDTH_16 BIT(21)
+#define CFG_COM_BSY BIT(20)
+#define CFG_PS_256 (0 << 16)
+#define CFG_PS_512 (1 << 16)
+#define CFG_PS_1024 (2 << 16)
+#define CFG_PS_2048 (3 << 16)
+#define CFG_PS_4096 (4 << 16)
+#define CFG_SKIP_SPARE_SIZE_4 (0 << 14)
+#define CFG_SKIP_SPARE_SIZE_8 (1 << 14)
+#define CFG_SKIP_SPARE_SIZE_12 (2 << 14)
+#define CFG_SKIP_SPARE_SIZE_16 (3 << 14)
+#define CFG_TAG_BYTE_SIZE(x) ((x) & 0xff)
+
+#define TIMING_1 0x14
+#define TIMING_TRP_RESP(x) (((x) & 0xf) << 28)
+#define TIMING_TWB(x) (((x) & 0xf) << 24)
+#define TIMING_TCR_TAR_TRR(x) (((x) & 0xf) << 20)
+#define TIMING_TWHR(x) (((x) & 0xf) << 16)
+#define TIMING_TCS(x) (((x) & 0x3) << 14)
+#define TIMING_TWH(x) (((x) & 0x3) << 12)
+#define TIMING_TWP(x) (((x) & 0xf) << 8)
+#define TIMING_TRH(x) (((x) & 0x3) << 4)
+#define TIMING_TRP(x) (((x) & 0xf) << 0)
+
+#define RESP 0x18
+
+#define TIMING_2 0x1c
+#define TIMING_TADL(x) ((x) & 0xf)
+
+#define CMD_1 0x20
+#define CMD_2 0x24
+#define ADDR_1 0x28
+#define ADDR_2 0x2c
+
+#define DMA_CTRL 0x30
+#define DMA_CTRL_GO BIT(31)
+#define DMA_CTRL_IN (0 << 30)
+#define DMA_CTRL_OUT BIT(30)
+#define DMA_CTRL_PERF_EN BIT(29)
+#define DMA_CTRL_IE_DONE BIT(28)
+#define DMA_CTRL_REUSE BIT(27)
+#define DMA_CTRL_BURST_1 (2 << 24)
+#define DMA_CTRL_BURST_4 (3 << 24)
+#define DMA_CTRL_BURST_8 (4 << 24)
+#define DMA_CTRL_BURST_16 (5 << 24)
+#define DMA_CTRL_IS_DONE BIT(20)
+#define DMA_CTRL_EN_A BIT(2)
+#define DMA_CTRL_EN_B BIT(1)
+
+#define DMA_CFG_A 0x34
+#define DMA_CFG_B 0x38
+
+#define FIFO_CTRL 0x3c
+#define FIFO_CTRL_CLR_ALL BIT(3)
+
+#define DATA_PTR 0x40
+#define TAG_PTR 0x44
+#define ECC_PTR 0x48
+
+#define DEC_STATUS 0x4c
+#define DEC_STATUS_A_ECC_FAIL BIT(1)
+#define DEC_STATUS_ERR_COUNT_MASK 0x00ff0000
+#define DEC_STATUS_ERR_COUNT_SHIFT 16
+
+#define HWSTATUS_CMD 0x50
+#define HWSTATUS_MASK 0x54
+#define HWSTATUS_RDSTATUS_MASK(x) (((x) & 0xff) << 24)
+#define HWSTATUS_RDSTATUS_VALUE(x) (((x) & 0xff) << 16)
+#define HWSTATUS_RBSY_MASK(x) (((x) & 0xff) << 8)
+#define HWSTATUS_RBSY_VALUE(x) (((x) & 0xff) << 0)
+
+#define BCH_CONFIG 0xcc
+#define BCH_ENABLE BIT(0)
+#define BCH_TVAL_4 (0 << 4)
+#define BCH_TVAL_8 (1 << 4)
+#define BCH_TVAL_14 (2 << 4)
+#define BCH_TVAL_16 (3 << 4)
+
+#define DEC_STAT_RESULT 0xd0
+#define DEC_STAT_BUF 0xd4
+#define DEC_STAT_BUF_FAIL_SEC_FLAG_MASK 0xff000000
+#define DEC_STAT_BUF_FAIL_SEC_FLAG_SHIFT 24
+#define DEC_STAT_BUF_CORR_SEC_FLAG_MASK 0x00ff0000
+#define DEC_STAT_BUF_CORR_SEC_FLAG_SHIFT 16
+#define DEC_STAT_BUF_MAX_CORR_CNT_MASK 0x00001f00
+#define DEC_STAT_BUF_MAX_CORR_CNT_SHIFT 8
+
+#define OFFSET(val, off) ((val) < (off) ? 0 : (val) - (off))
+
+#define SKIP_SPARE_BYTES 4
+#define BITS_PER_STEP_RS 18
+#define BITS_PER_STEP_BCH 13
+
+struct tegra_nand_controller {
+ struct nand_hw_control controller;
+ void __iomem *regs;
+ struct clk *clk;
+ struct device *dev;
+ struct completion command_complete;
+ struct completion dma_complete;
+ bool last_read_error;
+ int cur_chip;
+ struct nand_chip *chip;
+};
+
+struct tegra_nand_chip {
+ struct nand_chip chip;
+ struct gpio_desc *wp_gpio;
+ struct mtd_oob_region tag;
+};
+
+static inline struct tegra_nand_controller *to_tegra_ctrl(
+ struct nand_hw_control *hw_ctrl)
+{
+ return container_of(hw_ctrl, struct tegra_nand_controller, controller);
+}
+
+static inline struct tegra_nand_chip *to_tegra_chip(struct nand_chip *chip)
+{
+ return container_of(chip, struct tegra_nand_chip, chip);
+}
+
+static int tegra_nand_ooblayout_rs_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength,
+ BITS_PER_BYTE);
+
+ if (section > 0)
+ return -ERANGE;
+
+ oobregion->offset = SKIP_SPARE_BYTES;
+ oobregion->length = round_up(bytes_per_step * chip->ecc.steps, 4);
+
+ return 0;
+}
+
+static int tegra_nand_ooblayout_rs_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_RS * chip->ecc.strength,
+ BITS_PER_BYTE);
+
+ if (section > 0)
+ return -ERANGE;
+
+ oobregion->offset = SKIP_SPARE_BYTES +
+ round_up(bytes_per_step * chip->ecc.steps, 4);
+ oobregion->length = mtd->oobsize - oobregion->offset;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops tegra_nand_oob_rs_ops = {
+ .ecc = tegra_nand_ooblayout_rs_ecc,
+ .free = tegra_nand_ooblayout_rs_free,
+};
+
+static int tegra_nand_ooblayout_bch_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_BCH * chip->ecc.strength,
+ BITS_PER_BYTE);
+
+ if (section > 0)
+ return -ERANGE;
+
+ oobregion->offset = SKIP_SPARE_BYTES;
+ oobregion->length = round_up(bytes_per_step * chip->ecc.steps, 4);
+
+ return 0;
+}
+
+static int tegra_nand_ooblayout_bch_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ int bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_BCH * chip->ecc.strength,
+ BITS_PER_BYTE);
+
+ if (section > 0)
+ return -ERANGE;
+
+ oobregion->offset = SKIP_SPARE_BYTES +
+ round_up(bytes_per_step * chip->ecc.steps, 4);
+ oobregion->length = mtd->oobsize - oobregion->offset;
+
+ return 0;
+}
+
+/*
+ * Layout with tag bytes is
+ *
+ * --------------------------------------------------------------------------
+ * | main area | skip bytes | tag bytes | parity | .. |
+ * --------------------------------------------------------------------------
+ *
+ * If not tag bytes are written, parity moves right after skip bytes!
+ */
+static const struct mtd_ooblayout_ops tegra_nand_oob_bch_ops = {
+ .ecc = tegra_nand_ooblayout_bch_ecc,
+ .free = tegra_nand_ooblayout_bch_free,
+};
+
+static irqreturn_t tegra_nand_irq(int irq, void *data)
+{
+ struct tegra_nand_controller *ctrl = data;
+ u32 isr, dma;
+
+ isr = readl_relaxed(ctrl->regs + ISR);
+ dma = readl_relaxed(ctrl->regs + DMA_CTRL);
+ dev_dbg(ctrl->dev, "isr %08x\n", isr);
+
+ if (!isr && !(dma & DMA_CTRL_IS_DONE))
+ return IRQ_NONE;
+
+ /*
+ * The bit name is somewhat missleading: This is also set when
+ * HW ECC was successful. The data sheet states:
+ * Correctable OR Un-correctable errors occurred in the DMA transfer...
+ */
+ if (isr & ISR_CORRFAIL_ERR)
+ ctrl->last_read_error = true;
+
+ if (isr & ISR_CMD_DONE)
+ complete(&ctrl->command_complete);
+
+ if (isr & ISR_UND)
+ dev_err(ctrl->dev, "FIFO underrun\n");
+
+ if (isr & ISR_OVR)
+ dev_err(ctrl->dev, "FIFO overrun\n");
+
+ /* handle DMA interrupts */
+ if (dma & DMA_CTRL_IS_DONE) {
+ writel_relaxed(dma, ctrl->regs + DMA_CTRL);
+ complete(&ctrl->dma_complete);
+ }
+
+ /* clear interrupts */
+ writel_relaxed(isr, ctrl->regs + ISR);
+
+ return IRQ_HANDLED;
+}
+
+static const char * const tegra_nand_reg_names[] = {
+ "COMMAND",
+ "STATUS",
+ "ISR",
+ "IER",
+ "CONFIG",
+ "TIMING",
+ NULL,
+ "TIMING2",
+ "CMD_REG1",
+ "CMD_REG2",
+ "ADDR_REG1",
+ "ADDR_REG2",
+ "DMA_MST_CTRL",
+ "DMA_CFG_A",
+ "DMA_CFG_B",
+ "FIFO_CTRL",
+};
+
+static void tegra_nand_dump_reg(struct tegra_nand_controller *ctrl)
+{
+ u32 reg;
+ int i;
+
+ dev_err(ctrl->dev, "Tegra NAND controller register dump\n");
+ for (i = 0; i < ARRAY_SIZE(tegra_nand_reg_names); i++) {
+ const char *reg_name = tegra_nand_reg_names[i];
+
+ if (!reg_name)
+ continue;
+
+ reg = readl_relaxed(ctrl->regs + (i * 4));
+ dev_err(ctrl->dev, "%s: 0x%08x\n", reg_name, reg);
+ }
+}
+
+static int tegra_nand_cmd(struct nand_chip *chip,
+ const struct nand_subop *subop)
+{
+ const struct nand_op_instr *instr;
+ const struct nand_op_instr *instr_data_in = NULL;
+ struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
+ unsigned int op_id, size = 0, offset = 0;
+ bool first_cmd = true;
+ u32 reg, cmd = 0;
+ int ret;
+
+ for (op_id = 0; op_id < subop->ninstrs; op_id++) {
+ unsigned int naddrs, i;
+ const u8 *addrs;
+ u32 addr1 = 0, addr2 = 0;
+
+ instr = &subop->instrs[op_id];
+
+ switch (instr->type) {
+ case NAND_OP_CMD_INSTR:
+ if (first_cmd) {
+ cmd |= CMD_CLE;
+ writel_relaxed(instr->ctx.cmd.opcode,
+ ctrl->regs + CMD_1);
+ } else {
+ cmd |= CMD_SEC_CMD;
+ writel_relaxed(instr->ctx.cmd.opcode,
+ ctrl->regs + CMD_2);
+ }
+ first_cmd = false;
+ break;
+ case NAND_OP_ADDR_INSTR:
+ offset = nand_subop_get_addr_start_off(subop, op_id);
+ naddrs = nand_subop_get_num_addr_cyc(subop, op_id);
+ addrs = &instr->ctx.addr.addrs[offset];
+
+ cmd |= CMD_ALE | CMD_ALE_SIZE(naddrs);
+ for (i = 0; i < min_t(unsigned int, 4, naddrs); i++)
+ addr1 |= *addrs++ << (BITS_PER_BYTE * i);
+ naddrs -= i;
+ for (i = 0; i < min_t(unsigned int, 4, naddrs); i++)
+ addr2 |= *addrs++ << (BITS_PER_BYTE * i);
+ writel_relaxed(addr1, ctrl->regs + ADDR_1);
+ writel_relaxed(addr2, ctrl->regs + ADDR_2);
+ break;
+
+ case NAND_OP_DATA_IN_INSTR:
+ size = nand_subop_get_data_len(subop, op_id);
+ offset = nand_subop_get_data_start_off(subop, op_id);
+
+ cmd |= CMD_TRANS_SIZE(size) | CMD_PIO | CMD_RX |
+ CMD_A_VALID;
+
+ instr_data_in = instr;
+ break;
+
+ case NAND_OP_DATA_OUT_INSTR:
+ size = nand_subop_get_data_len(subop, op_id);
+ offset = nand_subop_get_data_start_off(subop, op_id);
+
+ cmd |= CMD_TRANS_SIZE(size) | CMD_PIO | CMD_TX |
+ CMD_A_VALID;
+
+ memcpy(®, instr->ctx.data.buf.out + offset, size);
+ writel_relaxed(reg, ctrl->regs + RESP);
+
+ break;
+ case NAND_OP_WAITRDY_INSTR:
+ cmd |= CMD_RBSY_CHK;
+ break;
+
+ }
+ }
+
+ cmd |= CMD_GO | CMD_CE(ctrl->cur_chip);
+ writel_relaxed(cmd, ctrl->regs + CMD);
+ ret = wait_for_completion_timeout(&ctrl->command_complete,
+ msecs_to_jiffies(500));
+ if (!ret) {
+ dev_err(ctrl->dev, "CMD timeout\n");
+ tegra_nand_dump_reg(ctrl);
+ return -ETIMEDOUT;
+ }
+
+ if (instr_data_in) {
+ reg = readl_relaxed(ctrl->regs + RESP);
+ memcpy(instr_data_in->ctx.data.buf.in + offset, ®, size);
+ }
+
+ return 0;
+}
+
+static const struct nand_op_parser tegra_nand_op_parser = NAND_OP_PARSER(
+ NAND_OP_PARSER_PATTERN(tegra_nand_cmd,
+ NAND_OP_PARSER_PAT_CMD_ELEM(true),
+ NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8),
+ NAND_OP_PARSER_PAT_CMD_ELEM(true),
+ NAND_OP_PARSER_PAT_WAITRDY_ELEM(true)),
+ NAND_OP_PARSER_PATTERN(tegra_nand_cmd,
+ NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, 4)),
+ NAND_OP_PARSER_PATTERN(tegra_nand_cmd,
+ NAND_OP_PARSER_PAT_CMD_ELEM(true),
+ NAND_OP_PARSER_PAT_ADDR_ELEM(true, 8),
+ NAND_OP_PARSER_PAT_CMD_ELEM(true),
+ NAND_OP_PARSER_PAT_WAITRDY_ELEM(true),
+ NAND_OP_PARSER_PAT_DATA_IN_ELEM(true, 4)),
+ );
+
+static int tegra_nand_exec_op(struct nand_chip *chip,
+ const struct nand_operation *op,
+ bool check_only)
+{
+ return nand_op_parser_exec_op(chip, &tegra_nand_op_parser, op,
+ check_only);
+}
+static void tegra_nand_select_chip(struct mtd_info *mtd, int chip_nr)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
+
+ ctrl->cur_chip = chip_nr;
+}
+
+static void tegra_nand_hw_ecc(struct tegra_nand_controller *ctrl,
+ struct nand_chip *chip, bool enable)
+{
+ u32 reg;
+
+ switch (chip->ecc.algo) {
+ case NAND_ECC_RS:
+ reg = readl_relaxed(ctrl->regs + CFG);
+ if (enable)
+ reg |= CFG_HW_ECC | CFG_ERR_COR;
+ else
+ reg &= ~(CFG_HW_ECC | CFG_ERR_COR);
+ writel_relaxed(reg, ctrl->regs + CFG);
+ break;
+ case NAND_ECC_BCH:
+ reg = readl_relaxed(ctrl->regs + BCH_CONFIG);
+ if (enable)
+ reg |= BCH_ENABLE;
+ else
+ reg &= ~BCH_ENABLE;
+ writel_relaxed(reg, ctrl->regs + BCH_CONFIG);
+ break;
+ default:
+ dev_err(ctrl->dev, "Unsupported hardware ECC algorithm\n");
+ break;
+ }
+}
+
+static int tegra_nand_page_xfer(struct mtd_info *mtd, struct nand_chip *chip,
+ void *buf, int oob_required, int page,
+ bool read)
+{
+ struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
+ struct tegra_nand_chip *nand = to_tegra_chip(chip);
+ enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
+ dma_addr_t dma_addr;
+ u32 cmd, dma_ctrl;
+ int ret, dma_len;
+
+ if (read) {
+ writel_relaxed(NAND_CMD_READ0, ctrl->regs + CMD_1);
+ writel_relaxed(NAND_CMD_READSTART, ctrl->regs + CMD_2);
+ } else {
+ writel_relaxed(NAND_CMD_SEQIN, ctrl->regs + CMD_1);
+ writel_relaxed(NAND_CMD_PAGEPROG, ctrl->regs + CMD_2);
+ }
+ cmd = CMD_CLE | CMD_SEC_CMD;
+
+ /* Lower 16-bits are column, always 0 */
+ writel_relaxed(page << 16, ctrl->regs + ADDR_1);
+
+ if (chip->options & NAND_ROW_ADDR_3) {
+ writel_relaxed(page >> 16, ctrl->regs + ADDR_2);
+ cmd |= CMD_ALE | CMD_ALE_SIZE(5);
+ } else {
+ cmd |= CMD_ALE | CMD_ALE_SIZE(4);
+ }
+
+ dma_len = mtd->writesize + (oob_required ? mtd->oobsize : 0);
+ dma_addr = dma_map_single(ctrl->dev, buf, dma_len, dir);
+ ret = dma_mapping_error(ctrl->dev, dma_addr);
+ if (ret) {
+ dev_err(ctrl->dev, "dma mapping error\n");
+ return -EINVAL;
+ }
+
+ writel_relaxed(mtd->writesize - 1, ctrl->regs + DMA_CFG_A);
+ writel_relaxed(dma_addr, ctrl->regs + DATA_PTR);
+
+ if (oob_required) {
+ dma_addr_t dma_addr_tag = dma_addr + mtd->writesize;
+
+ writel_relaxed(nand->tag.length - 1, ctrl->regs + DMA_CFG_B);
+ writel_relaxed(dma_addr_tag + nand->tag.offset,
+ ctrl->regs + TAG_PTR);
+ } else {
+ writel_relaxed(0, ctrl->regs + DMA_CFG_B);
+ writel_relaxed(0, ctrl->regs + TAG_PTR);
+ }
+
+ dma_ctrl = DMA_CTRL_GO | DMA_CTRL_PERF_EN |
+ DMA_CTRL_IE_DONE | DMA_CTRL_IS_DONE |
+ DMA_CTRL_BURST_16 | DMA_CTRL_EN_A;
+ if (oob_required)
+ dma_ctrl |= DMA_CTRL_EN_B;
+ if (read)
+ dma_ctrl |= DMA_CTRL_IN | DMA_CTRL_REUSE;
+ else
+ dma_ctrl |= DMA_CTRL_OUT;
+
+ writel_relaxed(dma_ctrl, ctrl->regs + DMA_CTRL);
+
+ cmd |= CMD_GO | CMD_RBSY_CHK | CMD_TRANS_SIZE(9) |
+ CMD_CE(ctrl->cur_chip) | CMD_A_VALID;
+ if (oob_required)
+ cmd |= CMD_B_VALID;
+ if (read)
+ cmd |= CMD_RX;
+ else
+ cmd |= CMD_TX | CMD_AFT_DAT;
+
+ writel_relaxed(cmd, ctrl->regs + CMD);
+
+ ret = wait_for_completion_timeout(&ctrl->command_complete,
+ msecs_to_jiffies(500));
+ if (!ret) {
+ dev_err(ctrl->dev, "CMD timeout\n");
+ tegra_nand_dump_reg(ctrl);
+ ret = -ETIMEDOUT;
+ goto err_unmap_dma;
+ }
+
+ ret = wait_for_completion_timeout(&ctrl->dma_complete,
+ msecs_to_jiffies(500));
+ if (!ret) {
+ dev_err(ctrl->dev, "DMA timeout\n");
+ tegra_nand_dump_reg(ctrl);
+ ret = -ETIMEDOUT;
+ goto err_unmap_dma;
+ }
+ ret = 0;
+
+err_unmap_dma:
+ dma_unmap_single(ctrl->dev, dma_addr, dma_len, dir);
+
+ return ret;
+}
+
+static int tegra_nand_read_page_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip,
+ uint8_t *buf, int oob_required, int page)
+{
+ struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
+ u32 dec_stat, max_corr_cnt;
+ unsigned long fail_sec_flag;
+ int ret;
+
+ tegra_nand_hw_ecc(ctrl, chip, true);
+ ret = tegra_nand_page_xfer(mtd, chip, buf, oob_required, page, true);
+ tegra_nand_hw_ecc(ctrl, chip, false);
+ if (ret)
+ return ret;
+
+ /* No correctable or un-correctable errors, page must have 0 bitflips */
+ if (!ctrl->last_read_error)
+ return 0;
+
+ /*
+ * Correctable or un-correctable errors occurred. Use DEC_STAT_BUF
+ * which contains information for all ECC selections.
+ *
+ * Note that since we do not use Command Queues DEC_RESULT does not
+ * state the number of pages we can read from the DEC_STAT_BUF. But
+ * since CORRFAIL_ERR did occur during page read we do have a valid
+ * result in DEC_STAT_BUF.
+ */
+ ctrl->last_read_error = false;
+ dec_stat = readl_relaxed(ctrl->regs + DEC_STAT_BUF);
+
+ fail_sec_flag = (dec_stat & DEC_STAT_BUF_FAIL_SEC_FLAG_MASK) >>
+ DEC_STAT_BUF_FAIL_SEC_FLAG_SHIFT;
+
+ max_corr_cnt = (dec_stat & DEC_STAT_BUF_MAX_CORR_CNT_MASK) >>
+ DEC_STAT_BUF_MAX_CORR_CNT_SHIFT;
+
+ if (fail_sec_flag) {
+ int bit, max_bitflips = 0;
+
+ /*
+ * Check if all sectors in a page failed. If only some failed
+ * its definitly not an erased page and we can return error
+ * stats right away.
+ *
+ * E.g. controller might return fail_sec_flag with 0x4, which
+ * would mean only the third sector failed to correct.
+ */
+ if (fail_sec_flag ^ GENMASK(chip->ecc.steps - 1, 0)) {
+ mtd->ecc_stats.failed += hweight8(fail_sec_flag);
+ return max_corr_cnt;
+ }
+
+ /*
+ * All sectors failed to correct, but the ECC isn't smart
+ * enough to figure out if a page is really completely erased.
+ * We check the read data here to figure out if it's a
+ * legitimate ECC error or only an erased page.
+ */
+ for_each_set_bit(bit, &fail_sec_flag, chip->ecc.steps) {
+ u8 *data = buf + (chip->ecc.size * bit);
+
+ ret = nand_check_erased_ecc_chunk(data, chip->ecc.size,
+ NULL, 0,
+ NULL, 0,
+ chip->ecc.strength);
+ if (ret < 0)
+ mtd->ecc_stats.failed++;
+ else
+ max_bitflips = max(ret, max_bitflips);
+ }
+
+ return max_t(unsigned int, max_corr_cnt, max_bitflips);
+ } else {
+ int corr_sec_flag;
+
+ corr_sec_flag = (dec_stat & DEC_STAT_BUF_CORR_SEC_FLAG_MASK) >>
+ DEC_STAT_BUF_CORR_SEC_FLAG_SHIFT;
+
+ /*
+ * The value returned in the register is the maximum of
+ * bitflips encountered in any of the ECC regions. As there is
+ * no way to get the number of bitflips in a specific regions
+ * we are not able to deliver correct stats but instead
+ * overestimate the number of corrected bitflips by assuming
+ * that all regions where errors have been corrected
+ * encountered the maximum number of bitflips.
+ */
+ mtd->ecc_stats.corrected += max_corr_cnt * hweight8(corr_sec_flag);
+
+ return max_corr_cnt;
+ }
+
+}
+
+static int tegra_nand_write_page_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip,
+ const uint8_t *buf, int oob_required,
+ int page)
+{
+ struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
+ int ret;
+
+ tegra_nand_hw_ecc(ctrl, chip, true);
+ ret = tegra_nand_page_xfer(mtd, chip, (void *)buf, oob_required, page,
+ false);
+ tegra_nand_hw_ecc(ctrl, chip, false);
+
+ return ret;
+}
+
+static void tegra_nand_setup_timing(struct tegra_nand_controller *ctrl,
+ const struct nand_sdr_timings *timings)
+{
+ /*
+ * The period (and all other timings in this function) is in ps,
+ * so need to take care here to avoid integer overflows.
+ */
+ unsigned int rate = clk_get_rate(ctrl->clk) / 1000000;
+ unsigned int period = DIV_ROUND_UP(1000000, rate);
+ u32 val, reg = 0;
+
+ val = DIV_ROUND_UP(max3(timings->tAR_min, timings->tRR_min,
+ timings->tRC_min), period);
+ reg |= TIMING_TCR_TAR_TRR(OFFSET(val, 3));
+
+ val = DIV_ROUND_UP(max(max(timings->tCS_min, timings->tCH_min),
+ max(timings->tALS_min, timings->tALH_min)),
+ period);
+ reg |= TIMING_TCS(OFFSET(val, 2));
+
+ val = DIV_ROUND_UP(max(timings->tRP_min, timings->tREA_max) + 6000,
+ period);
+ reg |= TIMING_TRP(OFFSET(val, 1)) | TIMING_TRP_RESP(OFFSET(val, 1));
+
+ reg |= TIMING_TWB(OFFSET(DIV_ROUND_UP(timings->tWB_max, period), 1));
+ reg |= TIMING_TWHR(OFFSET(DIV_ROUND_UP(timings->tWHR_min, period), 1));
+ reg |= TIMING_TWH(OFFSET(DIV_ROUND_UP(timings->tWH_min, period), 1));
+ reg |= TIMING_TWP(OFFSET(DIV_ROUND_UP(timings->tWP_min, period), 1));
+ reg |= TIMING_TRH(OFFSET(DIV_ROUND_UP(timings->tREH_min, period), 1));
+
+ writel_relaxed(reg, ctrl->regs + TIMING_1);
+
+ val = DIV_ROUND_UP(timings->tADL_min, period);
+ reg = TIMING_TADL(OFFSET(val, 3));
+
+ writel_relaxed(reg, ctrl->regs + TIMING_2);
+}
+
+static int tegra_nand_setup_data_interface(struct mtd_info *mtd, int csline,
+ const struct nand_data_interface *conf)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+ struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller);
+ const struct nand_sdr_timings *timings;
+
+ timings = nand_get_sdr_timings(conf);
+ if (IS_ERR(timings))
+ return PTR_ERR(timings);
+
+ if (csline == NAND_DATA_IFACE_CHECK_ONLY)
+ return 0;
+
+ tegra_nand_setup_timing(ctrl, timings);
+
+ return 0;
+}
+
+
+const int rs_strength_bootable[] = { 4 };
+const int rs_strength[] = { 4, 6, 8 };
+const int bch_strength_bootable[] = { 8, 16 };
+const int bch_strength[] = { 4, 8, 14, 16 };
+
+static int tegra_nand_get_strength(struct nand_chip *chip, const int *strength,
+ int strength_len, int oobsize)
+{
+ bool maximize = chip->ecc.options & NAND_ECC_MAXIMIZE;
+ int i;
+
+ /*
+ * Loop through available strengths. Backwards in case we try to
+ * maximize the BCH strength.
+ */
+ for (i = 0; i < strength_len; i++) {
+ int strength_sel, bytes_per_step, bytes_per_page;
+
+ if (maximize) {
+ strength_sel = strength[strength_len - i - 1];
+ } else {
+ strength_sel = strength[i];
+
+ if (strength_sel < chip->ecc_strength_ds)
+ continue;
+ }
+
+ bytes_per_step = DIV_ROUND_UP(BITS_PER_STEP_BCH * strength_sel,
+ BITS_PER_BYTE);
+ bytes_per_page = round_up(bytes_per_step * chip->ecc.steps, 4);
+
+ /* Check whether strength fits OOB */
+ if (bytes_per_page < (oobsize - SKIP_SPARE_BYTES))
+ return strength_sel;
+ }
+
+ return -EINVAL;
+}
+
+static int tegra_nand_select_strength(struct nand_chip *chip, int oobsize)
+{
+ const int *strength;
+ int strength_len;
+
+ switch (chip->ecc.algo) {
+ case NAND_ECC_RS:
+ if (chip->options & NAND_IS_BOOT_MEDIUM) {
+ strength = rs_strength_bootable;
+ strength_len = ARRAY_SIZE(rs_strength_bootable);
+ } else {
+ strength = rs_strength;
+ strength_len = ARRAY_SIZE(rs_strength);
+ }
+ break;
+ case NAND_ECC_BCH:
+ if (chip->options & NAND_IS_BOOT_MEDIUM) {
+ strength = bch_strength_bootable;
+ strength_len = ARRAY_SIZE(bch_strength_bootable);
+ } else {
+ strength = bch_strength;
+ strength_len = ARRAY_SIZE(bch_strength);
+ }
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return tegra_nand_get_strength(chip, strength, strength_len, oobsize);
+}
+
+static int tegra_nand_chips_init(struct device *dev,
+ struct tegra_nand_controller *ctrl)
+{
+ struct device_node *np = dev->of_node;
+ struct device_node *np_nand;
+ int nchips = of_get_child_count(np);
+ struct tegra_nand_chip *nand;
+ struct mtd_info *mtd;
+ struct nand_chip *chip;
+ unsigned long config, bch_config = 0;
+ int bits_per_step;
+ int ret;
+
+ if (nchips != 1) {
+ dev_err(dev, "Currently only one NAND chip supported\n");
+ return -EINVAL;
+ }
+
+ np_nand = of_get_next_child(np, NULL);
+
+ nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
+ if (!nand)
+ return -ENOMEM;
+
+ nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
+
+ if (IS_ERR(nand->wp_gpio)) {
+ ret = PTR_ERR(nand->wp_gpio);
+ dev_err(dev, "Failed to request WP GPIO: %d\n", ret);
+ return ret;
+ }
+
+ chip = &nand->chip;
+ chip->controller = &ctrl->controller;
+
+ mtd = nand_to_mtd(chip);
+
+ mtd->dev.parent = dev;
+ if (!mtd->name)
+ mtd->name = "tegra_nand";
+ mtd->owner = THIS_MODULE;
+
+ nand_set_flash_node(chip, np_nand);
+
+ chip->options = NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;
+ chip->exec_op = tegra_nand_exec_op;
+ chip->select_chip = tegra_nand_select_chip;
+ chip->setup_data_interface = tegra_nand_setup_data_interface;
+
+ ret = nand_scan_ident(mtd, 1, NULL);
+ if (ret)
+ return ret;
+
+ if (chip->bbt_options & NAND_BBT_USE_FLASH)
+ chip->bbt_options |= NAND_BBT_NO_OOB;
+
+ chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.size = 512;
+ chip->ecc.steps = mtd->writesize / chip->ecc.size;
+ if (chip->ecc_step_ds != 512) {
+ dev_err(dev, "Unsupported step size %d\n", chip->ecc_step_ds);
+ return -EINVAL;
+ }
+
+ chip->ecc.read_page = tegra_nand_read_page_hwecc;
+ chip->ecc.write_page = tegra_nand_write_page_hwecc;
+
+ config = readl_relaxed(ctrl->regs + CFG);
+ config |= CFG_PIPE_EN | CFG_SKIP_SPARE | CFG_SKIP_SPARE_SIZE_4;
+
+ if (chip->options & NAND_BUSWIDTH_16)
+ config |= CFG_BUS_WIDTH_16;
+
+ if (chip->ecc.algo == NAND_ECC_UNKNOWN) {
+ if (mtd->writesize < 2048)
+ chip->ecc.algo = NAND_ECC_RS;
+ else
+ chip->ecc.algo = NAND_ECC_BCH;
+ }
+
+ if (chip->ecc.algo == NAND_ECC_BCH && mtd->writesize < 2048) {
+ dev_err(dev, "BCH supportes 2K or 4K page size only\n");
+ return -EINVAL;
+ }
+
+ if (!chip->ecc.strength) {
+ ret = tegra_nand_select_strength(chip, mtd->oobsize);
+ if (ret < 0) {
+ dev_err(dev, "No valid strenght found, minimum %d\n",
+ chip->ecc_strength_ds);
+ return ret;
+ }
+
+ chip->ecc.strength = ret;
+ }
+
+ switch (chip->ecc.algo) {
+ case NAND_ECC_RS:
+ bits_per_step = BITS_PER_STEP_RS * chip->ecc.strength;
+ mtd_set_ooblayout(mtd, &tegra_nand_oob_rs_ops);
+ switch (chip->ecc.strength) {
+ case 4:
+ config |= CFG_ECC_SEL | CFG_TVAL_4;
+ break;
+ case 6:
+ config |= CFG_ECC_SEL | CFG_TVAL_6;
+ break;
+ case 8:
+ config |= CFG_ECC_SEL | CFG_TVAL_8;
+ break;
+ default:
+ dev_err(dev, "ECC strength %d not supported\n",
+ chip->ecc.strength);
+ return -EINVAL;
+ }
+ break;
+ case NAND_ECC_BCH:
+ bits_per_step = BITS_PER_STEP_BCH * chip->ecc.strength;
+ mtd_set_ooblayout(mtd, &tegra_nand_oob_bch_ops);
+ switch (chip->ecc.strength) {
+ case 4:
+ bch_config = BCH_TVAL_4;
+ break;
+ case 8:
+ bch_config = BCH_TVAL_8;
+ break;
+ case 14:
+ bch_config = BCH_TVAL_14;
+ break;
+ case 16:
+ bch_config = BCH_TVAL_16;
+ break;
+ default:
+ dev_err(dev, "ECC strength %d not supported\n",
+ chip->ecc.strength);
+ return -EINVAL;
+ }
+ break;
+ default:
+ dev_err(dev, "ECC algorithm not supported\n");
+ return -EINVAL;
+ }
+
+ dev_info(dev, "Using %s with strength %d per 512 byte step\n",
+ chip->ecc.algo == NAND_ECC_BCH ? "BCH" : "RS",
+ chip->ecc.strength);
+
+ chip->ecc.bytes = DIV_ROUND_UP(bits_per_step, BITS_PER_BYTE);
+
+ switch (mtd->writesize) {
+ case 256:
+ config |= CFG_PS_256;
+ break;
+ case 512:
+ config |= CFG_PS_512;
+ break;
+ case 1024:
+ config |= CFG_PS_1024;
+ break;
+ case 2048:
+ config |= CFG_PS_2048;
+ break;
+ case 4096:
+ config |= CFG_PS_4096;
+ break;
+ default:
+ dev_err(dev, "Unsupported writesize %d\n", mtd->writesize);
+ return -ENODEV;
+ }
+
+ writel_relaxed(config, ctrl->regs + CFG);
+ writel_relaxed(bch_config, ctrl->regs + BCH_CONFIG);
+
+ ret = nand_scan_tail(mtd);
+ if (ret)
+ return ret;
+
+ mtd_ooblayout_free(mtd, 0, &nand->tag);
+
+ config |= CFG_TAG_BYTE_SIZE(nand->tag.length - 1);
+ writel_relaxed(config, ctrl->regs + CFG);
+
+ ret = mtd_device_register(mtd, NULL, 0);
+ if (ret) {
+ dev_err(dev, "Failed to register mtd device: %d\n", ret);
+ nand_cleanup(chip);
+ return ret;
+ }
+
+ ctrl->chip = chip;
+
+ return 0;
+}
+
+static int tegra_nand_probe(struct platform_device *pdev)
+{
+ struct reset_control *rst;
+ struct tegra_nand_controller *ctrl;
+ struct resource *res;
+ unsigned long reg;
+ int irq, err = 0;
+
+ ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
+ if (!ctrl)
+ return -ENOMEM;
+
+ ctrl->dev = &pdev->dev;
+ nand_hw_control_init(&ctrl->controller);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ ctrl->regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(ctrl->regs))
+ return PTR_ERR(ctrl->regs);
+
+ rst = devm_reset_control_get(&pdev->dev, "nand");
+ if (IS_ERR(rst))
+ return PTR_ERR(rst);
+
+ ctrl->clk = devm_clk_get(&pdev->dev, "nand");
+ if (IS_ERR(ctrl->clk))
+ return PTR_ERR(ctrl->clk);
+
+ err = clk_prepare_enable(ctrl->clk);
+ if (err)
+ return err;
+
+ err = reset_control_reset(rst);
+ if (err)
+ goto err_disable_clk;
+
+ reg = HWSTATUS_RDSTATUS_MASK(1) | HWSTATUS_RDSTATUS_VALUE(0) |
+ HWSTATUS_RBSY_MASK(NAND_STATUS_READY) |
+ HWSTATUS_RBSY_VALUE(NAND_STATUS_READY);
+ writel_relaxed(NAND_CMD_STATUS, ctrl->regs + HWSTATUS_CMD);
+ writel_relaxed(reg, ctrl->regs + HWSTATUS_MASK);
+
+ init_completion(&ctrl->command_complete);
+ init_completion(&ctrl->dma_complete);
+
+ /* clear interrupts */
+ reg = readl_relaxed(ctrl->regs + ISR);
+ writel_relaxed(reg, ctrl->regs + ISR);
+
+ irq = platform_get_irq(pdev, 0);
+ err = devm_request_irq(&pdev->dev, irq, tegra_nand_irq, 0,
+ dev_name(&pdev->dev), ctrl);
+ if (err)
+ goto err_disable_clk;
+
+ writel_relaxed(DMA_CTRL_IS_DONE, ctrl->regs + DMA_CTRL);
+
+ /* enable interrupts */
+ reg = IER_UND | IER_OVR | IER_CMD_DONE | IER_GIE;
+ writel_relaxed(reg, ctrl->regs + IER);
+
+ /* reset config */
+ writel_relaxed(0, ctrl->regs + CFG);
+
+ err = tegra_nand_chips_init(ctrl->dev, ctrl);
+ if (err)
+ goto err_disable_clk;
+
+ platform_set_drvdata(pdev, ctrl);
+
+ return 0;
+
+err_disable_clk:
+ clk_disable_unprepare(ctrl->clk);
+ return err;
+}
+
+static int tegra_nand_remove(struct platform_device *pdev)
+{
+ struct tegra_nand_controller *ctrl = platform_get_drvdata(pdev);
+
+ nand_release(nand_to_mtd(ctrl->chip));
+
+ clk_disable_unprepare(ctrl->clk);
+
+ return 0;
+}
+
+static const struct of_device_id tegra_nand_of_match[] = {
+ { .compatible = "nvidia,tegra20-nand" },
+ { /* sentinel */ }
+};
+
+static struct platform_driver tegra_nand_driver = {
+ .driver = {
+ .name = "tegra-nand",
+ .of_match_table = tegra_nand_of_match,
+ },
+ .probe = tegra_nand_probe,
+ .remove = tegra_nand_remove,
+};
+module_platform_driver(tegra_nand_driver);
+
+MODULE_DESCRIPTION("NVIDIA Tegra NAND driver");
+MODULE_AUTHOR("Thierry Reding <thierry.reding@nvidia.com>");
+MODULE_AUTHOR("Lucas Stach <dev@lynxeye.de>");
+MODULE_AUTHOR("Stefan Agner <stefan@agner.ch>");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, tegra_nand_of_match);
--
2.17.0
^ permalink raw reply related
* [PATCH v3 3/6] mtd: rawnand: tegra: add devicetree binding
From: Stefan Agner @ 2018-05-31 22:16 UTC (permalink / raw)
To: boris.brezillon, dwmw2, computersforpeace, marek.vasut, robh+dt,
mark.rutland, thierry.reding
Cc: dev, miquel.raynal, richard, marcel, krzk, digetx,
benjamin.lindqvist, jonathanh, pdeschrijver, pgaikwad, mirza.krak,
stefan, linux-mtd, linux-tegra, devicetree, linux-kernel
In-Reply-To: <20180531221637.6017-1-stefan@agner.ch>
This adds the devicetree binding for the Tegra 2 NAND flash
controller.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
.../bindings/mtd/nvidia-tegra20-nand.txt | 64 +++++++++++++++++++
1 file changed, 64 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
diff --git a/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
new file mode 100644
index 000000000000..5cd984ef046b
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
@@ -0,0 +1,64 @@
+NVIDIA Tegra NAND Flash controller
+
+Required properties:
+- compatible: Must be one of:
+ - "nvidia,tegra20-nand"
+- reg: MMIO address range
+- interrupts: interrupt output of the NFC controller
+- clocks: Must contain an entry for each entry in clock-names.
+ See ../clocks/clock-bindings.txt for details.
+- clock-names: Must include the following entries:
+ - nand
+- resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+- reset-names: Must include the following entries:
+ - nand
+
+Optional children nodes:
+Individual NAND chips are children of the NAND controller node. Currently
+only one NAND chip supported.
+
+Required children node properties:
+- reg: An integer ranging from 1 to 6 representing the CS line to use.
+
+Optional children node properties:
+- nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
+ "hw" is supported.
+- nand-ecc-algo: string, algorithm of NAND ECC.
+ Supported values with "hw" ECC mode are: "rs", "bch".
+- nand-bus-width : See nand.txt
+- nand-on-flash-bbt: See nand.txt
+- nand-ecc-strength: integer representing the number of bits to correct
+ per ECC step (always 512). Supported strength using HW ECC
+ modes are:
+ - RS: 4, 6, 8
+ - BCH: 4, 8, 14, 16
+- nand-ecc-maximize: See nand.txt
+- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
+ are choosen.
+- wp-gpios: GPIO specifier for the write protect pin.
+
+Optional child node of NAND chip nodes:
+Partitions: see partition.txt
+
+ Example:
+ nand@70008000 {
+ compatible = "nvidia,tegra20-nand";
+ reg = <0x70008000 0x100>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
+ clock-names = "nand";
+ resets = <&tegra_car 13>;
+ reset-names = "nand";
+
+ nand-chip@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ nand-bus-width = <8>;
+ nand-on-flash-bbt;
+ nand-ecc-algo = "bch";
+ nand-ecc-strength = <8>;
+ wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+ };
+ };
--
2.17.0
^ permalink raw reply related
* [PATCH v3 2/6] mtd: rawnand: add an option to specify NAND chip as a boot device
From: Stefan Agner @ 2018-05-31 22:16 UTC (permalink / raw)
To: boris.brezillon, dwmw2, computersforpeace, marek.vasut, robh+dt,
mark.rutland, thierry.reding
Cc: dev, miquel.raynal, richard, marcel, krzk, digetx,
benjamin.lindqvist, jonathanh, pdeschrijver, pgaikwad, mirza.krak,
stefan, linux-mtd, linux-tegra, devicetree, linux-kernel
In-Reply-To: <20180531221637.6017-1-stefan@agner.ch>
Allow to define a NAND chip as a boot device. This can be helpful
for the selection of the ECC algorithm and strength in case the boot
ROM supports only a subset of controller provided options.
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
Documentation/devicetree/bindings/mtd/nand.txt | 4 ++++
drivers/mtd/nand/raw/nand_base.c | 3 +++
include/linux/mtd/rawnand.h | 6 ++++++
3 files changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/nand.txt b/Documentation/devicetree/bindings/mtd/nand.txt
index 8bb11d809429..8daf81b9748c 100644
--- a/Documentation/devicetree/bindings/mtd/nand.txt
+++ b/Documentation/devicetree/bindings/mtd/nand.txt
@@ -43,6 +43,10 @@ Optional NAND chip properties:
This is particularly useful when only the in-band area is
used by the upper layers, and you want to make your NAND
as reliable as possible.
+- nand-is-boot-medium: Whether the NAND chip is a boot medium. Drivers might use
+ this information to select ECC algorithms supported by
+ the boot ROM or similar restrictions.
+
- nand-rb: shall contain the native Ready/Busy ids.
The ECC strength and ECC step size properties define the correction capability
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 9eb5678dd6d0..c8fb7c9855e2 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -5826,6 +5826,9 @@ static int nand_dt_init(struct nand_chip *chip)
if (of_get_nand_bus_width(dn) == 16)
chip->options |= NAND_BUSWIDTH_16;
+ if (of_property_read_bool(dn, "nand-is-boot-medium"))
+ chip->options |= NAND_IS_BOOT_MEDIUM;
+
if (of_get_nand_on_flash_bbt(dn))
chip->bbt_options |= NAND_BBT_USE_FLASH;
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 6a82da8c44ce..8e54fcf2fa94 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -212,6 +212,12 @@ enum nand_ecc_algo {
*/
#define NAND_WAIT_TCCS 0x00200000
+/*
+ * Whether the NAND chip is a boot medium. Drivers might use this information
+ * to select ECC algorithms supported by the boot ROM or similar restrictions.
+ */
+#define NAND_IS_BOOT_MEDIUM 0x00400000
+
/* Options set by nand scan */
/* Nand scan has allocated controller struct */
#define NAND_CONTROLLER_ALLOC 0x80000000
--
2.17.0
^ permalink raw reply related
* [PATCH v3 1/6] mtd: rawnand: add Reed-Solomon error correction algorithm
From: Stefan Agner @ 2018-05-31 22:16 UTC (permalink / raw)
To: boris.brezillon, dwmw2, computersforpeace, marek.vasut, robh+dt,
mark.rutland, thierry.reding
Cc: dev, miquel.raynal, richard, marcel, krzk, digetx,
benjamin.lindqvist, jonathanh, pdeschrijver, pgaikwad, mirza.krak,
stefan, linux-mtd, linux-tegra, devicetree, linux-kernel
In-Reply-To: <20180531221637.6017-1-stefan@agner.ch>
Add Reed-Solomon (RS) to the enumeration of ECC algorithms.
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
drivers/mtd/nand/raw/nand_base.c | 1 +
include/linux/mtd/rawnand.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index f28c3a555861..9eb5678dd6d0 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -5744,6 +5744,7 @@ static int of_get_nand_ecc_mode(struct device_node *np)
static const char * const nand_ecc_algos[] = {
[NAND_ECC_HAMMING] = "hamming",
[NAND_ECC_BCH] = "bch",
+ [NAND_ECC_RS] = "rs",
};
static int of_get_nand_ecc_algo(struct device_node *np)
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 5dad59b31244..6a82da8c44ce 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -114,6 +114,7 @@ enum nand_ecc_algo {
NAND_ECC_UNKNOWN,
NAND_ECC_HAMMING,
NAND_ECC_BCH,
+ NAND_ECC_RS,
};
/*
--
2.17.0
^ permalink raw reply related
* [PATCH v3 0/6] mtd: rawnand: add NVIDIA Tegra NAND flash support
From: Stefan Agner @ 2018-05-31 22:16 UTC (permalink / raw)
To: boris.brezillon, dwmw2, computersforpeace, marek.vasut, robh+dt,
mark.rutland, thierry.reding
Cc: dev, miquel.raynal, richard, marcel, krzk, digetx,
benjamin.lindqvist, jonathanh, pdeschrijver, pgaikwad, mirza.krak,
stefan, linux-mtd, linux-tegra, devicetree, linux-kernel
This third revision is again a rather major overhaul. The driver
is now able to select a sensible ECC strenght automatically.
Review of the timing code uncovered few issues. Fixing them lead to
a tighter timing which lead to a performance increase of about 35%.
The in kernel speed test measures 11770/15058 KiB/s write/read speed.
Still open is the OOB layout discrepancy issue:
When using HW BCH support, the location of the ECC bytes changes
depending on whether extra OOB bytes (tag data) are transmitted or
not... Writing/Reading should always be with tag enabled or always
without. I am not sure how to solve this correctly, maybe disallow
using OOB data with HW ECC completely? Or just leave as is?
--
Stefan
Changes since v1:
- Split controller and NAND chip structure
- Add BCH support
- Allow to select algorithm and strength using device tree
- Improve HW ECC error reporting and use DEC_STATUS_BUF only
- Use SPDX license identifier
- Use per algorithm mtd_ooblayout_ops
- Use setup_data_interface callback for NAND timing configuration
Changes since v2:
- Set clock rate using assigned-clocks
- Use BIT() macro
- Fix and improve timing calculation
- Improve ECC error handling
- Store OOB layout for tag area in Tegra chip structure
- Update/fix bindings
- Use more specific variable names (replace "value")
- Introduce nand-is-boot-medium
- Choose sensible ECC strenght automatically
- Use wait_for_completion_timeout
- Print register dump on completion timeout
- Unify tegra_nand_(read|write)_page in tegra_nand_page_xfer
Lucas Stach (2):
ARM: dts: tegra: add Tegra20 NAND flash controller node
ARM: dts: tegra: enable NAND flash on Colibri T20
Stefan Agner (4):
mtd: rawnand: add Reed-Solomon error correction algorithm
mtd: rawnand: add an option to specify NAND chip as a boot device
mtd: rawnand: tegra: add devicetree binding
mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver
.../devicetree/bindings/mtd/nand.txt | 4 +
.../bindings/mtd/nvidia-tegra20-nand.txt | 64 +
MAINTAINERS | 7 +
arch/arm/boot/dts/tegra20-colibri-512.dtsi | 16 +
arch/arm/boot/dts/tegra20.dtsi | 15 +
drivers/mtd/nand/raw/Kconfig | 6 +
drivers/mtd/nand/raw/Makefile | 1 +
drivers/mtd/nand/raw/nand_base.c | 4 +
drivers/mtd/nand/raw/tegra_nand.c | 1143 +++++++++++++++++
include/linux/mtd/rawnand.h | 7 +
10 files changed, 1267 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/nvidia-tegra20-nand.txt
create mode 100644 drivers/mtd/nand/raw/tegra_nand.c
--
2.17.0
^ permalink raw reply
* Re: [PATCH] HID: i2c-hid: Add vddl regulator control
From: Dmitry Torokhov @ 2018-05-31 22:03 UTC (permalink / raw)
To: Stephen Boyd
Cc: Jiri Kosina, open list:HID CORE LAYER, Benjamin Tissoires,
Hans de Goede, Andy Shevchenko, Doug Anderson, devicetree
In-Reply-To: <20180531204250.209216-1-swboyd@chromium.org>
On Thu, May 31, 2018 at 1:42 PM, Stephen Boyd <swboyd@chromium.org> wrote:
> Some wacom w9013 devices have a vddl supply for "low voltage"
> requirements. Add support in this driver to turn on this low voltage
> supply.
>
> Cc: Benjamin Tissoires <benjamin.tissoires@redhat.com>
> Cc: Hans de Goede <hdegoede@redhat.com>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Dmitry Torokhov <dtor@chromium.org>
> Cc: Doug Anderson <dianders@chromium.org>
> Cc: <devicetree@vger.kernel.org>
> Signed-off-by: Stephen Boyd <swboyd@chromium.org>
> ---
> .../bindings/input/hid-over-i2c.txt | 3 ++-
> drivers/hid/i2c-hid/i2c-hid.c | 19 +++++++++++++++++++
> include/linux/platform_data/i2c-hid.h | 2 ++
> 3 files changed, 23 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/input/hid-over-i2c.txt b/Documentation/devicetree/bindings/input/hid-over-i2c.txt
> index 4d3da9d91de4..89e6ab89ba38 100644
> --- a/Documentation/devicetree/bindings/input/hid-over-i2c.txt
> +++ b/Documentation/devicetree/bindings/input/hid-over-i2c.txt
> @@ -26,7 +26,8 @@ device-specific compatible properties, which should be used in addition to the
>
> - compatible:
> * "wacom,w9013" (Wacom W9013 digitizer). Supports:
> - - vdd-supply
> + - vdd-supply (3.3V)
> + - vddl-supply (1.8V)
> - post-power-on-delay-ms
>
> - vdd-supply: phandle of the regulator that provides the supply voltage.
> diff --git a/drivers/hid/i2c-hid/i2c-hid.c b/drivers/hid/i2c-hid/i2c-hid.c
> index 6e803f361249..b6f02f98fec6 100644
> --- a/drivers/hid/i2c-hid/i2c-hid.c
> +++ b/drivers/hid/i2c-hid/i2c-hid.c
> @@ -1032,12 +1032,29 @@ static int i2c_hid_probe(struct i2c_client *client,
> goto err;
> }
>
> + ihid->pdata.supply_l = devm_regulator_get(&client->dev, "vddl");
> + if (IS_ERR(ihid->pdata.supply_l)) {
> + ret = PTR_ERR(ihid->pdata.supply_l);
> + if (ret != -EPROBE_DEFER)
> + dev_err(&client->dev, "Failed to get regulator: %d\n",
> + ret);
> + goto err;
> + }
> +
> ret = regulator_enable(ihid->pdata.supply);
> if (ret < 0) {
> dev_err(&client->dev, "Failed to enable regulator: %d\n",
> ret);
> goto err;
> }
> +
> + ret = regulator_enable(ihid->pdata.supply_l);
> + if (ret < 0) {
> + dev_err(&client->dev, "Failed to enable low regulator: %d\n",
> + ret);
> + goto err_regulator_l;
> + }
> +
Since there don't seem to be any timing constraints between powering
various supplies, maybe use bulk regulator API?
> if (ihid->pdata.post_power_delay_ms)
> msleep(ihid->pdata.post_power_delay_ms);
>
> @@ -1124,6 +1141,8 @@ static int i2c_hid_probe(struct i2c_client *client,
> pm_runtime_disable(&client->dev);
>
> err_regulator:
> + regulator_disable(ihid->pdata.supply_l);
> +err_regulator_l:
> regulator_disable(ihid->pdata.supply);
>
> err:
> diff --git a/include/linux/platform_data/i2c-hid.h b/include/linux/platform_data/i2c-hid.h
> index 1fb088239d12..1e4612751adf 100644
> --- a/include/linux/platform_data/i2c-hid.h
> +++ b/include/linux/platform_data/i2c-hid.h
> @@ -20,6 +20,7 @@ struct regulator;
> * struct i2chid_platform_data - used by hid over i2c implementation.
> * @hid_descriptor_address: i2c register where the HID descriptor is stored.
> * @supply: regulator for powering on the device.
> + * @supply_l: regulator for powering on the low voltage supply for device.
> * @post_power_delay_ms: delay after powering on before device is usable.
> *
> * Note that it is the responsibility of the platform driver (or the acpi 5.0
> @@ -36,6 +37,7 @@ struct regulator;
> struct i2c_hid_platform_data {
> u16 hid_descriptor_address;
> struct regulator *supply;
> + struct regulator *supply_l;
> int post_power_delay_ms;
> };
>
> --
> Sent by a computer through tubes
>
^ permalink raw reply
* Re: [PATCH 2/2] PM / devfreq: Generic cpufreq governor
From: Saravana Kannan @ 2018-05-31 21:53 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring,
Mark Rutland
Cc: Rajendra Nayak, Amit Kucheria, linux-pm, devicetree, linux-kernel
In-Reply-To: <1526631889-5084-3-git-send-email-skannan@codeaurora.org>
Chanwoo,
Friendly reminder for a review. I've addressed your comments on v1 of
this patch.
-Saravana
On 05/18/2018 01:24 AM, Saravana Kannan wrote:
> This devfreq governor is a generic implementation that can scale any
> devfreq device based on the current CPU frequency of all ONLINE CPUs. It
> allows for specifying CPU freq to devfreq mapping for specific devices.
> When such a mapping is not present, it defaults to scaling the device
> frequency in proportion to the CPU frequency.
>
> Change-Id: I7f786b9059435afe85b9ec8c504a4655731ee20e
> Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
> ---
> .../bindings/devfreq/devfreq-cpufreq.txt | 53 ++
> drivers/devfreq/Kconfig | 8 +
> drivers/devfreq/Makefile | 1 +
> drivers/devfreq/governor_cpufreq.c | 628 +++++++++++++++++++++
> 4 files changed, 690 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/devfreq/devfreq-cpufreq.txt
> create mode 100644 drivers/devfreq/governor_cpufreq.c
>
> diff --git a/Documentation/devicetree/bindings/devfreq/devfreq-cpufreq.txt b/Documentation/devicetree/bindings/devfreq/devfreq-cpufreq.txt
> new file mode 100644
> index 0000000..6537538
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/devfreq-cpufreq.txt
> @@ -0,0 +1,53 @@
> +Devfreq CPUfreq governor
> +
> +devfreq-cpufreq is a parent device that contains one or more child devices.
> +Each child device provides CPU frequency to device frequency mapping for a
> +specific device. Examples of devices that could use this are: DDR, cache and
> +CCI.
> +
> +Parent device name shall be "devfreq-cpufreq".
> +
> +Required child device properties:
> +- cpu-to-dev-map, or cpu-to-dev-map-<X>:
> + A list of tuples where each tuple consists of a
> + CPU frequency (KHz) and the corresponding device
> + frequency. CPU frequencies not listed in the table
> + will use the device frequency that corresponds to the
> + next rounded up CPU frequency.
> + Use "cpu-to-dev-map" if all CPUs in the system should
> + share same mapping.
> + Use cpu-to-dev-map-<cpuid> to describe different
> + mappings for different CPUs. The property should be
> + listed only for the first CPU if multiple CPUs are
> + synchronous.
> +- target-dev: Phandle to device that this mapping applies to.
> +
> +Example:
> + devfreq-cpufreq {
> + cpubw-cpufreq {
> + target-dev = <&cpubw>;
> + cpu-to-dev-map =
> + < 300000 1144 >,
> + < 422400 2288 >,
> + < 652800 3051 >,
> + < 883200 5996 >,
> + < 1190400 8056 >,
> + < 1497600 10101 >,
> + < 1728000 12145 >,
> + < 2649600 16250 >;
> + };
> +
> + cache-cpufreq {
> + target-dev = <&cache>;
> + cpu-to-dev-map =
> + < 300000 300000 >,
> + < 422400 422400 >,
> + < 652800 499200 >,
> + < 883200 576000 >,
> + < 960000 960000 >,
> + < 1497600 1036800 >,
> + < 1574400 1574400 >,
> + < 1728000 1651200 >,
> + < 2649600 1728000 >;
> + };
> + };
> diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
> index 8503018..5eeb33f 100644
> --- a/drivers/devfreq/Kconfig
> +++ b/drivers/devfreq/Kconfig
> @@ -73,6 +73,14 @@ config DEVFREQ_GOV_PASSIVE
> through sysfs entries. The passive governor recommends that
> devfreq device uses the OPP table to get the frequency/voltage.
>
> +config DEVFREQ_GOV_CPUFREQ
> + tristate "CPUfreq"
> + depends on CPU_FREQ
> + help
> + Chooses frequency based on the online CPUs' current frequency and a
> + CPU frequency to device frequency mapping table(s). This governor
> + can be useful for controlling devices such as DDR, cache, CCI, etc.
> +
> comment "DEVFREQ Drivers"
>
> config ARM_EXYNOS_BUS_DEVFREQ
> diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
> index f1cc8990..cafe7c2 100644
> --- a/drivers/devfreq/Makefile
> +++ b/drivers/devfreq/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PERFORMANCE) += governor_performance.o
> obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) += governor_powersave.o
> obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o
> obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o
> +obj-$(CONFIG_DEVFREQ_GOV_CPUFREQ) += governor_cpufreq.o
>
> # DEVFREQ Drivers
> obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
> diff --git a/drivers/devfreq/governor_cpufreq.c b/drivers/devfreq/governor_cpufreq.c
> new file mode 100644
> index 0000000..8f8ea26
> --- /dev/null
> +++ b/drivers/devfreq/governor_cpufreq.c
> @@ -0,0 +1,628 @@
> +/*
> + * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#define pr_fmt(fmt) "dev-cpufreq: " fmt
> +
> +#include <linux/devfreq.h>
> +#include <linux/cpu.h>
> +#include <linux/cpufreq.h>
> +#include <linux/cpumask.h>
> +#include <linux/slab.h>
> +#include <linux/platform_device.h>
> +#include <linux/of.h>
> +#include <linux/module.h>
> +#include "governor.h"
> +
> +struct cpu_state {
> + unsigned int freq;
> + unsigned int min_freq;
> + unsigned int max_freq;
> + bool on;
> + unsigned int first_cpu;
> +};
> +static struct cpu_state *state[NR_CPUS];
> +static int cpufreq_cnt;
> +
> +struct freq_map {
> + unsigned int cpu_khz;
> + unsigned int target_freq;
> +};
> +
> +struct devfreq_node {
> + struct devfreq *df;
> + void *orig_data;
> + struct device *dev;
> + struct device_node *of_node;
> + struct list_head list;
> + struct freq_map **map;
> + struct freq_map *common_map;
> +};
> +static LIST_HEAD(devfreq_list);
> +static DEFINE_MUTEX(state_lock);
> +static DEFINE_MUTEX(cpufreq_reg_lock);
> +
> +static void update_all_devfreqs(void)
> +{
> + struct devfreq_node *node;
> +
> + list_for_each_entry(node, &devfreq_list, list) {
> + struct devfreq *df = node->df;
> + if (!node->df)
> + continue;
> + mutex_lock(&df->lock);
> + update_devfreq(df);
> + mutex_unlock(&df->lock);
> +
> + }
> +}
> +
> +static struct devfreq_node *find_devfreq_node(struct device *dev)
> +{
> + struct devfreq_node *node;
> +
> + list_for_each_entry(node, &devfreq_list, list)
> + if (node->dev == dev || node->of_node == dev->of_node)
> + return node;
> +
> + return NULL;
> +}
> +
> +/* ==================== cpufreq part ==================== */
> +static void add_policy(struct cpufreq_policy *policy)
> +{
> + struct cpu_state *new_state;
> + unsigned int cpu, first_cpu;
> +
> + if (state[policy->cpu]) {
> + state[policy->cpu]->freq = policy->cur;
> + state[policy->cpu]->on = true;
> + } else {
> + new_state = kzalloc(sizeof(struct cpu_state), GFP_KERNEL);
> + if (!new_state)
> + return;
> +
> + first_cpu = cpumask_first(policy->related_cpus);
> + new_state->first_cpu = first_cpu;
> + new_state->freq = policy->cur;
> + new_state->min_freq = policy->cpuinfo.min_freq;
> + new_state->max_freq = policy->cpuinfo.max_freq;
> + new_state->on = true;
> +
> + for_each_cpu(cpu, policy->related_cpus)
> + state[cpu] = new_state;
> + }
> +}
> +
> +static int cpufreq_policy_notifier(struct notifier_block *nb,
> + unsigned long event, void *data)
> +{
> + struct cpufreq_policy *policy = data;
> +
> + switch (event) {
> + case CPUFREQ_CREATE_POLICY:
> + mutex_lock(&state_lock);
> + add_policy(policy);
> + update_all_devfreqs();
> + mutex_unlock(&state_lock);
> + break;
> +
> + case CPUFREQ_REMOVE_POLICY:
> + mutex_lock(&state_lock);
> + if (state[policy->cpu]) {
> + state[policy->cpu]->on = false;
> + update_all_devfreqs();
> + }
> + mutex_unlock(&state_lock);
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static struct notifier_block cpufreq_policy_nb = {
> + .notifier_call = cpufreq_policy_notifier
> +};
> +
> +static int cpufreq_trans_notifier(struct notifier_block *nb,
> + unsigned long event, void *data)
> +{
> + struct cpufreq_freqs *freq = data;
> + struct cpu_state *s;
> +
> + if (event != CPUFREQ_POSTCHANGE)
> + return 0;
> +
> + mutex_lock(&state_lock);
> +
> + s = state[freq->cpu];
> + if (!s)
> + goto out;
> +
> + if (s->freq != freq->new) {
> + s->freq = freq->new;
> + update_all_devfreqs();
> + }
> +
> +out:
> + mutex_unlock(&state_lock);
> + return 0;
> +}
> +
> +static struct notifier_block cpufreq_trans_nb = {
> + .notifier_call = cpufreq_trans_notifier
> +};
> +
> +static int register_cpufreq(void)
> +{
> + int ret = 0;
> + unsigned int cpu;
> + struct cpufreq_policy *policy;
> +
> + mutex_lock(&cpufreq_reg_lock);
> +
> + if (cpufreq_cnt)
> + goto cnt_not_zero;
> +
> + get_online_cpus();
> + ret = cpufreq_register_notifier(&cpufreq_policy_nb,
> + CPUFREQ_POLICY_NOTIFIER);
> + if (ret)
> + goto out;
> +
> + ret = cpufreq_register_notifier(&cpufreq_trans_nb,
> + CPUFREQ_TRANSITION_NOTIFIER);
> + if (ret) {
> + cpufreq_unregister_notifier(&cpufreq_policy_nb,
> + CPUFREQ_POLICY_NOTIFIER);
> + goto out;
> + }
> +
> + for_each_online_cpu(cpu) {
> + policy = cpufreq_cpu_get(cpu);
> + if (policy) {
> + add_policy(policy);
> + cpufreq_cpu_put(policy);
> + }
> + }
> +out:
> + put_online_cpus();
> +cnt_not_zero:
> + if (!ret)
> + cpufreq_cnt++;
> + mutex_unlock(&cpufreq_reg_lock);
> + return ret;
> +}
> +
> +static int unregister_cpufreq(void)
> +{
> + int ret = 0;
> + int cpu;
> +
> + mutex_lock(&cpufreq_reg_lock);
> +
> + if (cpufreq_cnt > 1)
> + goto out;
> +
> + cpufreq_unregister_notifier(&cpufreq_policy_nb,
> + CPUFREQ_POLICY_NOTIFIER);
> + cpufreq_unregister_notifier(&cpufreq_trans_nb,
> + CPUFREQ_TRANSITION_NOTIFIER);
> +
> + for (cpu = ARRAY_SIZE(state) - 1; cpu >= 0; cpu--) {
> + if (!state[cpu])
> + continue;
> + if (state[cpu]->first_cpu == cpu)
> + kfree(state[cpu]);
> + state[cpu] = NULL;
> + }
> +
> +out:
> + cpufreq_cnt--;
> + mutex_unlock(&cpufreq_reg_lock);
> + return ret;
> +}
> +
> +/* ==================== devfreq part ==================== */
> +
> +static unsigned int interpolate_freq(struct devfreq *df, unsigned int cpu)
> +{
> + unsigned long *freq_table = df->profile->freq_table;
> + unsigned int cpu_min = state[cpu]->min_freq;
> + unsigned int cpu_max = state[cpu]->max_freq;
> + unsigned int cpu_freq = state[cpu]->freq;
> + unsigned int dev_min, dev_max, cpu_percent;
> +
> + if (freq_table) {
> + dev_min = freq_table[0];
> + dev_max = freq_table[df->profile->max_state - 1];
> + } else {
> + if (df->max_freq <= df->min_freq)
> + return 0;
> + dev_min = df->min_freq;
> + dev_max = df->max_freq;
> + }
> +
> + cpu_percent = ((cpu_freq - cpu_min) * 100) / (cpu_max - cpu_min);
> + return dev_min + mult_frac(dev_max - dev_min, cpu_percent, 100);
> +}
> +
> +static unsigned int cpu_to_dev_freq(struct devfreq *df, unsigned int cpu)
> +{
> + struct freq_map *map = NULL;
> + unsigned int cpu_khz = 0, freq;
> + struct devfreq_node *n = df->data;
> +
> + if (!state[cpu] || !state[cpu]->on || state[cpu]->first_cpu != cpu) {
> + freq = 0;
> + goto out;
> + }
> +
> + if (n->common_map)
> + map = n->common_map;
> + else if (n->map)
> + map = n->map[cpu];
> +
> + cpu_khz = state[cpu]->freq;
> +
> + if (!map) {
> + freq = interpolate_freq(df, cpu);
> + goto out;
> + }
> +
> + while (map->cpu_khz && map->cpu_khz < cpu_khz)
> + map++;
> + if (!map->cpu_khz)
> + map--;
> + freq = map->target_freq;
> +
> +out:
> + dev_dbg(df->dev.parent, "CPU%u: %d -> dev: %u\n", cpu, cpu_khz, freq);
> + return freq;
> +}
> +
> +static int devfreq_cpufreq_get_freq(struct devfreq *df,
> + unsigned long *freq)
> +{
> + unsigned int cpu, tgt_freq = 0;
> + struct devfreq_node *node;
> +
> + node = df->data;
> + if (!node) {
> + pr_err("Unable to find devfreq node!\n");
> + return -ENODEV;
> + }
> +
> + for_each_possible_cpu(cpu)
> + tgt_freq = max(tgt_freq, cpu_to_dev_freq(df, cpu));
> +
> + *freq = tgt_freq;
> + return 0;
> +}
> +
> +static unsigned int show_table(char *buf, unsigned int len,
> + struct freq_map *map)
> +{
> + unsigned int cnt = 0;
> +
> + cnt += snprintf(buf + cnt, len - cnt, "CPU freq\tDevice freq\n");
> +
> + while (map->cpu_khz && cnt < len) {
> + cnt += snprintf(buf + cnt, len - cnt, "%8u\t%11u\n",
> + map->cpu_khz, map->target_freq);
> + map++;
> + }
> + if (cnt < len)
> + cnt += snprintf(buf + cnt, len - cnt, "\n");
> +
> + return cnt;
> +}
> +
> +static ssize_t show_map(struct device *dev, struct device_attribute *attr,
> + char *buf)
> +{
> + struct devfreq *df = to_devfreq(dev);
> + struct devfreq_node *n = df->data;
> + struct freq_map *map;
> + unsigned int cnt = 0, cpu;
> +
> + mutex_lock(&state_lock);
> + if (n->common_map) {
> + map = n->common_map;
> + cnt += snprintf(buf + cnt, PAGE_SIZE - cnt,
> + "Common table for all CPUs:\n");
> + cnt += show_table(buf + cnt, PAGE_SIZE - cnt, map);
> + } else if (n->map) {
> + for_each_possible_cpu(cpu) {
> + map = n->map[cpu];
> + if (!map)
> + continue;
> + cnt += snprintf(buf + cnt, PAGE_SIZE - cnt,
> + "CPU %u:\n", cpu);
> + if (cnt >= PAGE_SIZE)
> + break;
> + cnt += show_table(buf + cnt, PAGE_SIZE - cnt, map);
> + if (cnt >= PAGE_SIZE)
> + break;
> + }
> + } else {
> + cnt += snprintf(buf + cnt, PAGE_SIZE - cnt,
> + "Device freq interpolated based on CPU freq\n");
> + }
> + mutex_unlock(&state_lock);
> +
> + return cnt;
> +}
> +
> +static DEVICE_ATTR(freq_map, 0444, show_map, NULL);
> +static struct attribute *dev_attr[] = {
> + &dev_attr_freq_map.attr,
> + NULL,
> +};
> +
> +static struct attribute_group dev_attr_group = {
> + .name = "cpufreq",
> + .attrs = dev_attr,
> +};
> +
> +static int devfreq_cpufreq_gov_start(struct devfreq *devfreq)
> +{
> + int ret = 0;
> + struct devfreq_node *node;
> + bool alloc = false;
> +
> + ret = register_cpufreq();
> + if (ret)
> + return ret;
> +
> + ret = sysfs_create_group(&devfreq->dev.kobj, &dev_attr_group);
> + if (ret) {
> + unregister_cpufreq();
> + return ret;
> + }
> +
> + mutex_lock(&state_lock);
> +
> + node = find_devfreq_node(devfreq->dev.parent);
> + if (node == NULL) {
> + node = kzalloc(sizeof(struct devfreq_node), GFP_KERNEL);
> + if (!node) {
> + pr_err("Out of memory!\n");
> + ret = -ENOMEM;
> + goto alloc_fail;
> + }
> + alloc = true;
> + node->dev = devfreq->dev.parent;
> + list_add_tail(&node->list, &devfreq_list);
> + }
> + node->df = devfreq;
> + node->orig_data = devfreq->data;
> + devfreq->data = node;
> +
> + mutex_lock(&devfreq->lock);
> + ret = update_devfreq(devfreq);
> + mutex_unlock(&devfreq->lock);
> + if (ret) {
> + pr_err("Freq update failed!\n");
> + goto update_fail;
> + }
> +
> + mutex_unlock(&state_lock);
> + return 0;
> +
> +update_fail:
> + devfreq->data = node->orig_data;
> + if (alloc) {
> + list_del(&node->list);
> + kfree(node);
> + }
> +alloc_fail:
> + mutex_unlock(&state_lock);
> + sysfs_remove_group(&devfreq->dev.kobj, &dev_attr_group);
> + unregister_cpufreq();
> + return ret;
> +}
> +
> +static void devfreq_cpufreq_gov_stop(struct devfreq *devfreq)
> +{
> + struct devfreq_node *node = devfreq->data;
> +
> + mutex_lock(&state_lock);
> + devfreq->data = node->orig_data;
> + if (node->map || node->common_map) {
> + node->df = NULL;
> + } else {
> + list_del(&node->list);
> + kfree(node);
> + }
> + mutex_unlock(&state_lock);
> +
> + sysfs_remove_group(&devfreq->dev.kobj, &dev_attr_group);
> + unregister_cpufreq();
> +}
> +
> +static int devfreq_cpufreq_ev_handler(struct devfreq *devfreq,
> + unsigned int event, void *data)
> +{
> + int ret;
> +
> + switch (event) {
> + case DEVFREQ_GOV_START:
> +
> + ret = devfreq_cpufreq_gov_start(devfreq);
> + if (ret) {
> + pr_err("Governor start failed!\n");
> + return ret;
> + }
> + pr_debug("Enabled dev CPUfreq governor\n");
> + break;
> +
> + case DEVFREQ_GOV_STOP:
> +
> + devfreq_cpufreq_gov_stop(devfreq);
> + pr_debug("Disabled dev CPUfreq governor\n");
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static struct devfreq_governor devfreq_cpufreq = {
> + .name = "cpufreq",
> + .get_target_freq = devfreq_cpufreq_get_freq,
> + .event_handler = devfreq_cpufreq_ev_handler,
> +};
> +
> +#define NUM_COLS 2
> +static struct freq_map *read_tbl(struct device_node *of_node, char *prop_name)
> +{
> + int len, nf, i, j;
> + u32 data;
> + struct freq_map *tbl;
> +
> + if (!of_find_property(of_node, prop_name, &len))
> + return NULL;
> + len /= sizeof(data);
> +
> + if (len % NUM_COLS || len == 0)
> + return NULL;
> + nf = len / NUM_COLS;
> +
> + tbl = kzalloc((nf + 1) * sizeof(*tbl), GFP_KERNEL);
> + if (!tbl)
> + return NULL;
> +
> + for (i = 0, j = 0; i < nf; i++, j += 2) {
> + of_property_read_u32_index(of_node, prop_name, j, &data);
> + tbl[i].cpu_khz = data;
> +
> + of_property_read_u32_index(of_node, prop_name, j + 1, &data);
> + tbl[i].target_freq = data;
> + }
> + tbl[i].cpu_khz = 0;
> +
> + return tbl;
> +}
> +
> +#define PROP_TARGET "target-dev"
> +#define PROP_TABLE "cpu-to-dev-map"
> +static int add_table_from_of(struct device_node *of_node)
> +{
> + struct device_node *target_of_node;
> + struct devfreq_node *node;
> + struct freq_map *common_tbl;
> + struct freq_map **tbl_list = NULL;
> + static char prop_name[] = PROP_TABLE "-999999";
> + int cpu, ret, cnt = 0, prop_sz = ARRAY_SIZE(prop_name);
> +
> + target_of_node = of_parse_phandle(of_node, PROP_TARGET, 0);
> + if (!target_of_node)
> + return -EINVAL;
> +
> + node = kzalloc(sizeof(struct devfreq_node), GFP_KERNEL);
> + if (!node)
> + return -ENOMEM;
> +
> + common_tbl = read_tbl(of_node, PROP_TABLE);
> + if (!common_tbl) {
> + tbl_list = kzalloc(sizeof(*tbl_list) * NR_CPUS, GFP_KERNEL);
> + if (!tbl_list) {
> + ret = -ENOMEM;
> + goto err_list;
> + }
> +
> + for_each_possible_cpu(cpu) {
> + ret = snprintf(prop_name, prop_sz, "%s-%d",
> + PROP_TABLE, cpu);
> + if (ret >= prop_sz) {
> + pr_warn("More CPUs than I can handle!\n");
> + pr_warn("Skipping rest of the tables!\n");
> + break;
> + }
> + tbl_list[cpu] = read_tbl(of_node, prop_name);
> + if (tbl_list[cpu])
> + cnt++;
> + }
> + }
> + if (!common_tbl && !cnt) {
> + ret = -EINVAL;
> + goto err_tbl;
> + }
> +
> + mutex_lock(&state_lock);
> + node->of_node = target_of_node;
> + node->map = tbl_list;
> + node->common_map = common_tbl;
> + list_add_tail(&node->list, &devfreq_list);
> + mutex_unlock(&state_lock);
> +
> + return 0;
> +err_tbl:
> + kfree(tbl_list);
> +err_list:
> + kfree(node);
> + return ret;
> +}
> +
> +static int __init devfreq_cpufreq_init(void)
> +{
> + int ret;
> + struct device_node *of_par, *of_child;
> +
> + of_par = of_find_node_by_name(NULL, "devfreq-cpufreq");
> + if (of_par) {
> + for_each_child_of_node(of_par, of_child) {
> + ret = add_table_from_of(of_child);
> + if (ret)
> + pr_err("Parsing %s failed!\n", of_child->name);
> + else
> + pr_debug("Parsed %s.\n", of_child->name);
> + }
> + of_node_put(of_par);
> + } else {
> + pr_info("No tables parsed from DT.\n");
> + }
> +
> + ret = devfreq_add_governor(&devfreq_cpufreq);
> + if (ret) {
> + pr_err("Governor add failed!\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +subsys_initcall(devfreq_cpufreq_init);
> +
> +static void __exit devfreq_cpufreq_exit(void)
> +{
> + int ret, cpu;
> + struct devfreq_node *node, *tmp;
> +
> + ret = devfreq_remove_governor(&devfreq_cpufreq);
> + if (ret)
> + pr_err("Governor remove failed!\n");
> +
> + mutex_lock(&state_lock);
> + list_for_each_entry_safe(node, tmp, &devfreq_list, list) {
> + kfree(node->common_map);
> + for_each_possible_cpu(cpu)
> + kfree(node->map[cpu]);
> + kfree(node->map);
> + list_del(&node->list);
> + kfree(node);
> + }
> + mutex_unlock(&state_lock);
> +}
> +module_exit(devfreq_cpufreq_exit);
> +
> +MODULE_DESCRIPTION("CPU freq based generic governor for devfreq devices");
> +MODULE_LICENSE("GPL v2");
--
Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver
From: Stefan Agner @ 2018-05-31 21:44 UTC (permalink / raw)
To: Boris Brezillon
Cc: Miquel Raynal, robh+dt, dwmw2, computersforpeace, marek.vasut,
mark.rutland, thierry.reding, mturquette, sboyd, dev, richard,
marcel, krzk, digetx, benjamin.lindqvist, jonathanh, pdeschrijver,
pgaikwad, mirza.krak, linux-mtd, linux-tegra, devicetree,
linux-kernel, linux-clk
In-Reply-To: <20180531223027.57e36d0b@bbrezillon>
On 31.05.2018 22:30, Boris Brezillon wrote:
> On Thu, 31 May 2018 19:54:08 +0200
> Stefan Agner <stefan@agner.ch> wrote:
>
>> >> +
>> >> + mtd->dev.parent = &pdev->dev;
>> >> + mtd->name = "tegra_nand";
>> >
>> > I just figured it was undocumented (yet) but you could have a label
>> > string property in your nand DT node that tells you the name of the
>> > MTD device instead of something too generic like tegra_nand.
>> >
>>
>> Using label in the NAND chip subnode actually causes current U-Boot to
>> delete (!!) the chip node and create partitions on the controller node.
>>
>> See:
>> https://elixir.bootlin.com/u-boot/latest/source/common/fdt_support.c#L757
>>
>> The code essentially uses the property label to detect whether its a
>> NAND chip or a partition...
>
> Why not fixing that in uboot? The representation where the NAND device
> and NAND controller are mixed in a single node called nand@xxx is just
> wrong from a HW PoV, and it seems uboot is using this representation,
> which is probably why you have a problem when trying to find the
> partition directly under the NAND controller node.
>
>>
>> At least this is the case when using fdt_fixup_mtdparts and passing the
>> controller compatible ("nvidia,tegra20-nand") in node_info,
>
> Just a digression, but I recommend using
> "nvidia,tegra20-nand-controller" for the compatible, because the node
> is describing the NAND controller not the NAND chip.
>
Ok.
>> what our
>> downstream U-Boot is currently doing. Maybe we should pass the
>> compatible property of the NAND chip?
>
> Or maybe you should search for partitions in children of the controller
> node instead of searching directly under the controller node itself.
>
Yes, that is what it is doing... But only if that child has not a label.
fdt_fixup_mtdparts is common code. Change the behaviour now probably
breaks boards...
Anyway, this discussion needs to be shifted to the U-Boot mailing list.
>> But afaik, chips do not have a
>> compatible necessarily.
>
> Nope, and it should stay like that.
>
>>
>> So using label in the chip node is currently a no-go for me.
>
> I hope I'm wrong but I fear this is not the only problem you'll face
> when switching to a controller+chip representation. This is just the
> tip of the iceberg.
>
Works not too bad otherwise, so far :-)
>>
>> Will send out v3 soon.
>
> Sure, let's see how v3 looks.
--
Stefan
^ permalink raw reply
* Re: [PATCH 10/11] dt-bindings: misc: add bindings for throttler
From: Matthias Kaehlcke @ 2018-05-31 21:10 UTC (permalink / raw)
To: Rob Herring
Cc: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Arnd Bergmann,
Greg Kroah-Hartman, Mark Rutland, linux-pm, devicetree,
linux-kernel@vger.kernel.org, Brian Norris, Douglas Anderson
In-Reply-To: <CAL_JsqK_nFtuxhNbAn3yYueLKAxvwfnY=5M6zFdGrwwwPVrP5g@mail.gmail.com>
On Thu, May 31, 2018 at 03:04:18PM -0500, Rob Herring wrote:
> On Thu, May 31, 2018 at 1:34 PM, Matthias Kaehlcke <mka@chromium.org> wrote:
> > Hi Rob,
> >
> > On Thu, May 31, 2018 at 11:31:59AM -0500, Rob Herring wrote:
> >> On Fri, May 25, 2018 at 01:30:42PM -0700, Matthias Kaehlcke wrote:
> >>
> >> Commit msg?
> >
> > Will add some more info in the next revision.
> >
> >> > Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
> >> > ---
> >> > .../devicetree/bindings/misc/throttler.txt | 41 +++++++++++++++++++
> >> > 1 file changed, 41 insertions(+)
> >> > create mode 100644 Documentation/devicetree/bindings/misc/throttler.txt
> >> >
> >> > diff --git a/Documentation/devicetree/bindings/misc/throttler.txt b/Documentation/devicetree/bindings/misc/throttler.txt
> >> > new file mode 100644
> >> > index 000000000000..92f13e94451a
> >> > --- /dev/null
> >> > +++ b/Documentation/devicetree/bindings/misc/throttler.txt
> >> > @@ -0,0 +1,41 @@
> >> > +Throttler driver
> >> > +
> >> > +The Throttler is used for non-thermal throttling of system components like
> >> > +CPUs or devfreq devices.
> >>
> >> This all looks very Linux specific and not a h/w device. Perhaps you can
> >> add hint properties to OPP tables as to what entries can be used for
> >> throttling, but otherwise this doesn't belong in DT.
> >
> > My idea is to allow multiple throttlers, which might operate on
> > different throttling devices or use different OPPs for the same
> > device. To support this a simple boolean hint that the OPP can be used
> > for throttling would not be sufficient.
> >
> > What should work is a property with an array of phandles of the
> > throttlers that use a given OPP.
> >
> > AFAIK it is currently not possible to enumerate the devfreq devices in
> > the system, so besides the info in the OPPs the throttler itself would
> > still need a phandle to the devfreq device(s) it uses.
>
> Why don't you fix that OS problem instead of working around it in DT?
I can try, though it's not exclusively in my hands, depends on what
the devfreq maintainers think about it.
> > I envision something like this:
> >
> > gpu_opp_table: opp-table2 {
> > compatible = "operating-points-v2";
> >
> > opp00 {
> > opp-hz = /bits/ 64 <200000000>;
> > opp-microvolt = <800000>;
> > };
> > opp01 {
> > opp-hz = /bits/ 64 <297000000>;
> > opp-microvolt = <800000>;
> > opp-throttlers = <&cros_ec_throttler>;
> > };
> > ...
> > };
> >
> > cros_ec_throttler: cros-ec-throttler {
> > compatible = "google,cros-ec-throttler";
>
> Is this an actual h/w device?
The Chrome OS Embedded Controller is a MCU that communicates with
Linux over SPI or I2C. The low-level communication with the EC is
handled by drivers/mfd/cros_ec* and then there are multiple drivers
representing 'remote devices' on top of this (rtc-cros-ec.c,
extcon-usbc-cros-ec.c, pwm-cros-ec.c, ...). cros_ec_throttler is a
similar 'device' that responds to signals from the EC with frequency
adjustments.
^ permalink raw reply
* Re: [PATCH 01/13] dt-bindings: net: bluetooth: add support for Realtek Bluetooth chips
From: Hans de Goede @ 2018-05-31 20:50 UTC (permalink / raw)
To: Rob Herring
Cc: Marcel Holtmann, Johan Hedberg, Martin Blumenstingl, Jeremy Cline,
linux-bluetooth, linux-serial, linux-acpi, devicetree
In-Reply-To: <20180531164214.GA12210@rob-hp-laptop>
Hi,
On 31-05-18 18:42, Rob Herring wrote:
> On Wed, May 30, 2018 at 10:04:37AM +0200, Hans de Goede wrote:
>> Hi,
>>
>> On 30-05-18 08:42, Marcel Holtmann wrote:
>>> Hi Hans,
>>>
>>>> This adds the documentation for Bluetooth functionality of the Realtek
>>>> RTL8723BS and RTL8723DS.
>>>> Both are SDIO wifi chips with an additional Bluetooth module which is
>>>> connected via UART to the host.
>>>>
>>>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>>> Signed-off-by: Jeremy Cline <jeremy@jcline.org>
>>>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>>>> ---
>>>> .../bindings/net/realtek-bluetooth.txt | 41 +++++++++++++++++++
>>>> 1 file changed, 41 insertions(+)
>>>> create mode 100644 Documentation/devicetree/bindings/net/realtek-bluetooth.txt
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/net/realtek-bluetooth.txt b/Documentation/devicetree/bindings/net/realtek-bluetooth.txt
>>>> new file mode 100644
>>>> index 000000000000..1491329c4cd1
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/net/realtek-bluetooth.txt
>>>> @@ -0,0 +1,41 @@
>>>> +Realtek Bluetooth Chips
>>>> +-----------------------
>>>> +
>>>> +This documents the binding structure and common properties for serial
>>>> +attached Realtek devices.
>>>> +
>>>> +Serial attached Realtek devices shall be a child node of the host UART
>>>> +device the slave device is attached to. See ../serial/slave-device.txt
>>>> +for more information
>>>> +
>>>> +Required properties:
>>>> +- compatible: should contain one of the following:
>>>> + * "realtek,rtl8723bs-bluetooth"
>>>> + * "realtek,rtl8723ds-bluetooth"
>>>> +
>>>> +Optional properties:
>>>> +- realtek,config-data: Bluetooth chipset configuration data which is
>>>> + needed for communication (it typically contains
>>>> + board specific settings like the baudrate and
>>>> + whether flow-control is used).
>>>> + This is an array of u8 values.
>>>> +- enable-gpios: GPIO specifier, used to enable/disable the BT module
>>>> +- reset-gpios: GPIO specifier, used to reset the BT module
>>>> +
>>>> +
>>>> +Example:
>>>> +
>>>> +&uart {
>>>> + ...
>>>> +
>>>> + bluetooth {
>>>> + compatible = "realtek,rtl8723bs-bluetooth";
>>>> + enable-gpios = <&gpio 20 GPIO_ACTIVE_HIGH>;
>>>> + reset-gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
>>>> + realtek,config-data = /bits/ 8 <
>>>> + 0x55 0xab 0x23 0x87 0x29 0x00 0xf4 0x00 0x01 0x01 0xf6 0x00
>>>> + 0x02 0x81 0x00 0xfa 0x00 0x02 0x12 0x80 0x0c 0x00 0x10 0x02
>>>> + 0x80 0x92 0x04 0x50 0xc5 0xea 0x19 0xe1 0x1b 0xfd 0xaf 0x5f
>>>> + 0x01 0xa4 0x0b 0xd9 0x00 0x01 0x0f 0xe4 0x00 0x01 0x08>;
>>>> + };
>>>> +};
>>>
>>> we actually need to agree on this config-data. As I wrote in an earlier email some time ago, the actual config-data files are just memory portions that will overload the default config area. I wrote tools/rtlfw.c to parse these.
>>>
>>> So now I wonder if we can just read the current configuration and run with that when no extra blob is provided. That way it would always work and we might just give the config-data filename here. Mostly this is the for PCM and UART settings anyway.
>>
>> I've been thinking about this too and 2 different solutions come to mind.
>>
>> Note this is all x86 specific, I think it best to solve this for x86 first
>> and then we can apply the lessons learned there to ARM/devicetree when
>> someone comes along who wants to hook-up things on ARM.
>>
>> My first idea was to stick with a config blob using the firmware_load
>> mechanism, but to add a postfix to the filename based on the ACPI
>> HID (hardware-id) of the serdev device, so in practice this means
>> we would try to load:
>>
>> /lib/firmware/rtl_bt/rtl8723bs_config-OBDA8723.bin
>>
>> On most x86 devices, so far all my testing on a bunch of different
>> devices has shown that the same config works for all x86 devices
>> (I took the config from a Chuwi Vi8 tablet which uses 3000000bps
>> + hardware flowcontrol).
>>
>> This way we can put the config in linux-firmware, without it
>> getting loaded on ARM boards where it might very well be wrong.
>>
>>
>> My second idea is to include a default config inside the driver,
>> which can be optionally overridden by a file in
>> /lib/firmware/rtl_bt and/or dt. Combined with module-options to
>> override the baudrate and flowcontrol setting (and patch the
>> builtin config accordingly).
>>
>>
>> Your idea to read back the config from the device is also
>> interesting, but I don't think that will gain us anything because
>> AFAIK the whole purpose of the board specific config file
>> bits is that the chip lack eeprom space to store this info,
>> so we will just always get some generic defaults.
>>
>>
>> I've run your rtlfw tool on a bunch of different config files and
>> there are a lot of unknown fields, and even of the known fields
>> I don't think we understand all the bits. So all in all the
>> config file is a bit of a black box and as such I believe it
>> would be best to just treat it as such and I personally
>> prefer my first idea, which is to add a postfix to the
>> firmware filename request, so on x86 load:
>>
>> /lib/firmware/rtl_bt/rtl8723bs_config-OBDA8723.bin
>>
>> And on devicetree we could postfix things with the machine
>> model string (as returned by of_flat_dt_get_machine_name())
>
> If the firmware file is going to depend on the DT, then you might as
> well just put the data into the DT.
Ok, note we don't need the entire firmware in DT, just a (binary
format) config file for the firmware. The question is if we are
going to try and break up the info from the config-file and then
regenerate it inside the kernel driver. Or if we are just going
to put the say 60 bytes in DT as an u8 array as the original
binding proposed by Martin Blumenstingl suggests.
Since we only know the meaning for a couple of the bytes in
the file, which is typically 40 - 60 bytes big, I think it
is probably best to just treat it as a blob.
> There's a similar issue on QCom Dragonboards. The WiFi (and BT?)
> firmware files are supposedly board specific, so folks don't want to put
> them into linux-firmware. But it also seems to be unknown as to which
> parts are board specific are not.
In my experience with broadcom and now the rtl8723bs the
actual firmware and the needed config data are separate.
Hmm that is actually no entirely true, for broadcom the
bluetooth patchram file depends on the clockcrystal freq
used on the board, so there are 2 versions of it for a
single chip, 1 for each of the 2 different freqs used.
Regards,
Hans
^ permalink raw reply
* [PATCH] HID: i2c-hid: Add vddl regulator control
From: Stephen Boyd @ 2018-05-31 20:42 UTC (permalink / raw)
To: Jiri Kosina
Cc: linux-input, Benjamin Tissoires, Hans de Goede, Andy Shevchenko,
Dmitry Torokhov, Doug Anderson, devicetree
Some wacom w9013 devices have a vddl supply for "low voltage"
requirements. Add support in this driver to turn on this low voltage
supply.
Cc: Benjamin Tissoires <benjamin.tissoires@redhat.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Dmitry Torokhov <dtor@chromium.org>
Cc: Doug Anderson <dianders@chromium.org>
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
---
.../bindings/input/hid-over-i2c.txt | 3 ++-
drivers/hid/i2c-hid/i2c-hid.c | 19 +++++++++++++++++++
include/linux/platform_data/i2c-hid.h | 2 ++
3 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/input/hid-over-i2c.txt b/Documentation/devicetree/bindings/input/hid-over-i2c.txt
index 4d3da9d91de4..89e6ab89ba38 100644
--- a/Documentation/devicetree/bindings/input/hid-over-i2c.txt
+++ b/Documentation/devicetree/bindings/input/hid-over-i2c.txt
@@ -26,7 +26,8 @@ device-specific compatible properties, which should be used in addition to the
- compatible:
* "wacom,w9013" (Wacom W9013 digitizer). Supports:
- - vdd-supply
+ - vdd-supply (3.3V)
+ - vddl-supply (1.8V)
- post-power-on-delay-ms
- vdd-supply: phandle of the regulator that provides the supply voltage.
diff --git a/drivers/hid/i2c-hid/i2c-hid.c b/drivers/hid/i2c-hid/i2c-hid.c
index 6e803f361249..b6f02f98fec6 100644
--- a/drivers/hid/i2c-hid/i2c-hid.c
+++ b/drivers/hid/i2c-hid/i2c-hid.c
@@ -1032,12 +1032,29 @@ static int i2c_hid_probe(struct i2c_client *client,
goto err;
}
+ ihid->pdata.supply_l = devm_regulator_get(&client->dev, "vddl");
+ if (IS_ERR(ihid->pdata.supply_l)) {
+ ret = PTR_ERR(ihid->pdata.supply_l);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&client->dev, "Failed to get regulator: %d\n",
+ ret);
+ goto err;
+ }
+
ret = regulator_enable(ihid->pdata.supply);
if (ret < 0) {
dev_err(&client->dev, "Failed to enable regulator: %d\n",
ret);
goto err;
}
+
+ ret = regulator_enable(ihid->pdata.supply_l);
+ if (ret < 0) {
+ dev_err(&client->dev, "Failed to enable low regulator: %d\n",
+ ret);
+ goto err_regulator_l;
+ }
+
if (ihid->pdata.post_power_delay_ms)
msleep(ihid->pdata.post_power_delay_ms);
@@ -1124,6 +1141,8 @@ static int i2c_hid_probe(struct i2c_client *client,
pm_runtime_disable(&client->dev);
err_regulator:
+ regulator_disable(ihid->pdata.supply_l);
+err_regulator_l:
regulator_disable(ihid->pdata.supply);
err:
diff --git a/include/linux/platform_data/i2c-hid.h b/include/linux/platform_data/i2c-hid.h
index 1fb088239d12..1e4612751adf 100644
--- a/include/linux/platform_data/i2c-hid.h
+++ b/include/linux/platform_data/i2c-hid.h
@@ -20,6 +20,7 @@ struct regulator;
* struct i2chid_platform_data - used by hid over i2c implementation.
* @hid_descriptor_address: i2c register where the HID descriptor is stored.
* @supply: regulator for powering on the device.
+ * @supply_l: regulator for powering on the low voltage supply for device.
* @post_power_delay_ms: delay after powering on before device is usable.
*
* Note that it is the responsibility of the platform driver (or the acpi 5.0
@@ -36,6 +37,7 @@ struct regulator;
struct i2c_hid_platform_data {
u16 hid_descriptor_address;
struct regulator *supply;
+ struct regulator *supply_l;
int post_power_delay_ms;
};
--
Sent by a computer through tubes
^ permalink raw reply related
* Re: [PATCH] Input: of_touchscreen / generic bindings - Add support for touchscreen-min-x|y
From: Hans de Goede @ 2018-05-31 20:42 UTC (permalink / raw)
To: Rob Herring; +Cc: Dmitry Torokhov, Benjamin Tissoires, devicetree, linux-input
In-Reply-To: <20180531172519.GA27468@rob-hp-laptop>
Hi,
On 31-05-18 19:25, Rob Herring wrote:
> On Tue, May 29, 2018 at 01:52:38PM +0200, Hans de Goede wrote:
>> Some touchscreens, depending on the firmware and/or the digitizer report
>> coordinates which never reach 0 along one or both of their axis.
>>
>> This has been seen for example on the Silead touchscreens on a Onda V891w
>> and a Point of View mobii TAB-P800w(v2.0).
>>
>> This commit adds support for touchscreen-min-x and touchscreen-min-y
>> device-properties which can be set to communicate the actual start
>> coordinates (rather then 0,0) to userspace.
>>
>> When set this fixes e.g. not being able to click things in the GNOME3
>> top-bar on the 2 example tablets.
>>
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>> ---
>> .../input/touchscreen/touchscreen.txt | 6 ++--
>
> Please split bindings to separate patch.
Will do for v2.
>> drivers/input/touchscreen/of_touchscreen.c | 36 ++++++++++++++-----
>> 2 files changed, 32 insertions(+), 10 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt b/Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt
>> index 537643e86f61..8aff9551259f 100644
>> --- a/Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt
>> +++ b/Documentation/devicetree/bindings/input/touchscreen/touchscreen.txt
>> @@ -1,10 +1,12 @@
>> General Touchscreen Properties:
>>
>> Optional properties for Touchscreens:
>> + - touchscreen-min-x : minimum x coordinate reported (0 if not set)
>> + - touchscreen-min-y : minimum y coordinate reported (0 if not set)
>
> Maybe a min-max range would be better if size (in pixels) is also
> needed?
Size in pixels is never needed. The touchscreen-size-x /
touchscreen-size-y have always been the max x/y coordinate reported + 1
and may or may not have anything to do with pixels. I've noticed on
some ARM tablets that the firmware in the touchscreen controller was
programmed to send coordinates in the same range as the display
resolution, but then the manufacturer would turn around, put in
a higher res display and keep the same touchscreen range (or the
otherway around). So it seems that there has been a 1:1 mapping on
some devices, but that has not been true for a long time now.
>> - touchscreen-size-x : horizontal resolution of touchscreen
>> - (in pixels)
>> + (maximum x coordinate reported + 1)
>
> This is unrelated or at least not explained in the commit msg. I agree
> this probably makes sense as units are often not pixels unless the hw/fw
> is doing some scaling itself.
Right I added this fix to make clear that we are indeed specifying a
min-max range, with the oddity that instead of max we specify max + 1
for historical reasons.
Do you want me to split this out into a separate patch?
Regards,
Hans
>
>> - touchscreen-size-y : vertical resolution of touchscreen
>> - (in pixels)
>> + (maximum y coordinate reported + 1)
>> - touchscreen-max-pressure : maximum reported pressure (arbitrary range
>> dependent on the controller)
>> - touchscreen-fuzz-x : horizontal noise value of the absolute input
^ permalink raw reply
* Re: [RESEND PATCH 2/5] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver
From: Boris Brezillon @ 2018-05-31 20:30 UTC (permalink / raw)
To: Stefan Agner
Cc: Miquel Raynal, robh+dt, dwmw2, computersforpeace, marek.vasut,
mark.rutland, thierry.reding, mturquette, sboyd, dev, richard,
marcel, krzk, digetx, benjamin.lindqvist, jonathanh, pdeschrijver,
pgaikwad, mirza.krak, linux-mtd, linux-tegra, devicetree,
linux-kernel, linux-clk
In-Reply-To: <047a9a5e72c8db52858a505865d4f720@agner.ch>
On Thu, 31 May 2018 19:54:08 +0200
Stefan Agner <stefan@agner.ch> wrote:
> >> +
> >> + mtd->dev.parent = &pdev->dev;
> >> + mtd->name = "tegra_nand";
> >
> > I just figured it was undocumented (yet) but you could have a label
> > string property in your nand DT node that tells you the name of the
> > MTD device instead of something too generic like tegra_nand.
> >
>
> Using label in the NAND chip subnode actually causes current U-Boot to
> delete (!!) the chip node and create partitions on the controller node.
>
> See:
> https://elixir.bootlin.com/u-boot/latest/source/common/fdt_support.c#L757
>
> The code essentially uses the property label to detect whether its a
> NAND chip or a partition...
Why not fixing that in uboot? The representation where the NAND device
and NAND controller are mixed in a single node called nand@xxx is just
wrong from a HW PoV, and it seems uboot is using this representation,
which is probably why you have a problem when trying to find the
partition directly under the NAND controller node.
>
> At least this is the case when using fdt_fixup_mtdparts and passing the
> controller compatible ("nvidia,tegra20-nand") in node_info,
Just a digression, but I recommend using
"nvidia,tegra20-nand-controller" for the compatible, because the node
is describing the NAND controller not the NAND chip.
> what our
> downstream U-Boot is currently doing. Maybe we should pass the
> compatible property of the NAND chip?
Or maybe you should search for partitions in children of the controller
node instead of searching directly under the controller node itself.
> But afaik, chips do not have a
> compatible necessarily.
Nope, and it should stay like that.
>
> So using label in the chip node is currently a no-go for me.
I hope I'm wrong but I fear this is not the only problem you'll face
when switching to a controller+chip representation. This is just the
tip of the iceberg.
>
> Will send out v3 soon.
Sure, let's see how v3 looks.
^ permalink raw reply
* [PATCH v2 2/2] arm64: dts: renesas: condor: add I2C0 support
From: Sergei Shtylyov @ 2018-05-31 20:26 UTC (permalink / raw)
To: Simon Horman, Rob Herring, Catalin Marinas, Will Deacon,
linux-renesas-soc, devicetree
Cc: Mark Rutland, Magnus Damm, linux-arm-kernel@lists.infradead.org
In-Reply-To: <2a88f4e9-0a86-8e6f-0ef2-20913dc9431d@cogentembedded.com>
Define the Condor board dependent part of the I2C0 device node.
The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders
and Analog Devices ADV7511W HDMI transmitter (but we're only describing
the former chips now).
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
---
Changes in version 2:
- added Simon's tag.
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 27 ++++++++++++++++++++++++
1 file changed, 27 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -80,6 +80,28 @@
clock-frequency = <32768>;
};
+&i2c0 {
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ io_expander0: gpio@20 {
+ compatible = "onnn,pca9654";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ io_expander1: gpio@21 {
+ compatible = "onnn,pca9654";
+ reg = <0x21>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins_uhs>;
@@ -104,6 +126,11 @@
function = "canfd0";
};
+ i2c0_pins: i2c0 {
+ groups = "i2c0";
+ function = "i2c0";
+ };
+
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
^ permalink raw reply
* [PATCH 2/2] ARM: davinci_all_defconfig: Enable Bluetooth
From: David Lechner @ 2018-05-31 20:25 UTC (permalink / raw)
To: linux-arm-kernel
Cc: David Lechner, Sekhar Nori, Kevin Hilman, devicetree,
linux-kernel
In-Reply-To: <20180531202549.11255-1-david@lechnology.com>
This enables Bluetooth modules in davinic_all_defconfig needed for LEGO
MINDSTORMS EV3.
Signed-off-by: David Lechner <david@lechnology.com>
---
arch/arm/configs/davinci_all_defconfig | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index a1b6e106b867..f8448c4703c1 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -54,6 +54,13 @@ CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_NETFILTER=y
+CONFIG_BT=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_BNEP=m
+CONFIG_BT_HIDP=m
+CONFIG_BT_LEDS=y
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_LL=y
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_FW_LOADER=m
@@ -113,6 +120,7 @@ CONFIG_SERIAL_8250_CONSOLE=y
CONFIG_SERIAL_8250_NR_UARTS=3
CONFIG_SERIAL_8250_RUNTIME_UARTS=3
CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_DEV_BUS=y
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
@@ -212,6 +220,7 @@ CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_OMAP=m
CONFIG_DMADEVICES=y
CONFIG_TI_EDMA=y
+CONFIG_COMMON_CLK_PWM=m
CONFIG_REMOTEPROC=m
CONFIG_DA8XX_REMOTEPROC=m
CONFIG_MEMORY=y
--
2.17.0
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox