* Re: [PATCH v3 7/9] dt-bindings: vendor-prefixes: add Sipeed
From: Rob Herring @ 2019-07-09 22:57 UTC (permalink / raw)
Cc: Maxime Ripard, Chen-Yu Tsai, Linus Walleij,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
In-Reply-To: <20190623043801.14040-8-icenowy-h8G6r0blFSE@public.gmane.org>
On Sun, 23 Jun 2019 12:37:59 +0800, Icenowy Zheng wrote:
> Shenzhen Sipeed Technology Co., Ltd. is a company focused on development
> kits, which also contains rebranded Lichee Pi series.
>
> Add its vendor prefix binding.
>
> Signed-off-by: Icenowy Zheng <icenowy-h8G6r0blFSE@public.gmane.org>
> ---
> Changes in v3:
> - Rebased because of the addition of sinlinx and sinovoip.
>
> Patch introduced in v2.
>
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Applied, thanks.
Rob
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^ permalink raw reply
* Re: [PATCH v3 4/9] clk: sunxi-ng: v3s: add Allwinner V3 support
From: Rob Herring @ 2019-07-09 22:56 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Maxime Ripard, Chen-Yu Tsai, Linus Walleij, devicetree,
linux-arm-kernel, linux-kernel, linux-clk, linux-gpio,
linux-sunxi
In-Reply-To: <20190623043801.14040-5-icenowy@aosc.io>
On Sun, Jun 23, 2019 at 12:37:56PM +0800, Icenowy Zheng wrote:
> Allwinner V3 has the same main die with V3s, but with more pins wired.
> There's a I2S bus on V3 that is not available on V3s.
>
> Add the V3-only peripheral's clocks and reset to the V3s CCU driver,
> bound to a new V3 compatible string. The driver name is not changed
> because it's part of the device tree binding (the header file name).
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> No changes in v3/v2.
>
> drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 225 +++++++++++++++++++++-
> drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 2 +-
> include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 +
> include/dt-bindings/reset/sun8i-v3s-ccu.h | 3 +
Acked-by: Rob Herring <robh@kernel.org>
> 4 files changed, 231 insertions(+), 3 deletions(-)
^ permalink raw reply
* Re: [PATCH] dt-bindings: 83xx-512x-pci: Drop cell-index property
From: Rob Herring @ 2019-07-09 22:50 UTC (permalink / raw)
To: Kefeng Wang; +Cc: Bjorn Helgaas, linux-pci, devicetree, Kumar Gala
In-Reply-To: <20190622034557.196097-1-wangkefeng.wang@huawei.com>
On Sat, 22 Jun 2019 11:45:57 +0800, Kefeng Wang wrote:
> 28eac2b74cc7 ("powerpc/fsl: Remove cell-index from PCI nodes"),
> and for now it is still not used, drop it from doc.
>
> Cc: Kumar Gala <galak@kernel.crashing.org>
> Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
> ---
> Documentation/devicetree/bindings/pci/83xx-512x-pci.txt | 1 -
> 1 file changed, 1 deletion(-)
>
Applied, thanks.
Rob
^ permalink raw reply
* Re: [PATCH v2 1/3] dt-bindings: display: rockchip: document VOP gamma LUT address
From: Rob Herring @ 2019-07-09 22:50 UTC (permalink / raw)
Cc: Mark Rutland, devicetree, Jacopo Mondi, linux-kernel, dri-devel,
Douglas Anderson, linux-rockchip, Boris Brezillon, Sean Paul,
kernel, Ezequiel Garcia
In-Reply-To: <20190621211346.1324-2-ezequiel@collabora.com>
On Fri, 21 Jun 2019 18:13:44 -0300, Ezequiel Garcia wrote:
> Add the register specifier description for an
> optional gamma LUT address.
>
> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
> ---
> Changes from v1:
> * Drop reg-names, suggested by Doug.
> ---
> .../devicetree/bindings/display/rockchip/rockchip-vop.txt | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [RFC PATCH v4 net-next 05/11] dt-bindings: net: ti: add new cpsw switch driver bindings
From: Rob Herring @ 2019-07-09 22:48 UTC (permalink / raw)
To: Grygorii Strashko
Cc: netdev, Ilias Apalodimas, Andrew Lunn, David S . Miller,
Ivan Khoronzhuk, Jiri Pirko, Florian Fainelli, Sekhar Nori,
linux-kernel, linux-omap, Murali Karicheri, Ivan Vecera,
devicetree
In-Reply-To: <20190621181314.20778-6-grygorii.strashko@ti.com>
On Fri, Jun 21, 2019 at 09:13:08PM +0300, Grygorii Strashko wrote:
> Add bindings for the new TI CPSW switch driver. Comparing to the legacy
> bindings (net/cpsw.txt):
> - ports definition follows DSA bindings (net/dsa/dsa.txt) and ports can be
> marked as "disabled" if not physically wired.
> - ports definition follows DSA bindings (net/dsa/dsa.txt) and ports can be
> marked as "disabled" if not physically wired.
> - all deprecated properties dropped;
> - all legacy propertiies dropped which represents constant HW cpapbilities
> (cpdma_channels, ale_entries, bd_ram_size, mac_control, slaves,
> active_slave)
> - cpts properties grouped in "cpts" sub-node
>
> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
> ---
> .../bindings/net/ti,cpsw-switch.txt | 147 ++++++++++++++++++
> 1 file changed, 147 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/ti,cpsw-switch.txt
>
> diff --git a/Documentation/devicetree/bindings/net/ti,cpsw-switch.txt b/Documentation/devicetree/bindings/net/ti,cpsw-switch.txt
> new file mode 100644
> index 000000000000..787219cddccd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/ti,cpsw-switch.txt
> @@ -0,0 +1,147 @@
> +TI SoC Ethernet Switch Controller Device Tree Bindings (new)
> +------------------------------------------------------
> +
> +The 3-port switch gigabit ethernet subsystem provides ethernet packet
> +communication and can be configured as an ethernet switch. It provides the
> +gigabit media independent interface (GMII),reduced gigabit media
> +independent interface (RGMII), reduced media independent interface (RMII),
> +the management data input output (MDIO) for physical layer device (PHY)
> +management.
> +
> +Required properties:
> +- compatible : be one of the below:
> + "ti,cpsw-switch" for backward compatible
> + "ti,am335x-cpsw-switch" for AM335x controllers
> + "ti,am4372-cpsw-switch" for AM437x controllers
> + "ti,dra7-cpsw-switch" for DRA7x controllers
> +- reg : physical base address and size of the CPSW module IO range
> +- ranges : shall contain the CPSW module IO range available for child devices
> +- clocks : should contain the CPSW functional clock
> +- clock-names : should be "fck"
> + See bindings/clock/clock-bindings.txt
> +- interrupts : should contain CPSW RX, TX, MISC, RX_THRESH interrupts
> +- interrupt-names : should contain "rx_thresh", "rx", "tx", "misc"
What's the defined order because it's not consistent here.
> + See bindings/interrupt-controller/interrupts.txt
> +
> +Optional properties:
> +- syscon : phandle to the system control device node which provides access to
> + efuse IO range with MAC addresses
> +
> +Required Sub-nodes:
> +- ports : contains CPSW external ports descriptions
Use ethernet-ports to avoid 'ports' from the graph binding.
> + Required properties:
> + - #address-cells : Must be 1
> + - #size-cells : Must be 0
> + - reg : CPSW port number. Should be 1 or 2
> + - phys : phandle on phy-gmii-sel PHY (see phy/ti-phy-gmii-sel.txt)
> + - phy-mode : operation mode of the PHY interface [1]
> + - phy-handle : phandle to a PHY on an MDIO bus [1]
> +
> + Optional properties:
> + - ti,label : Describes the label associated with this port
What's wrong with standard 'label' property.
> + - ti,dual_emac_pvid : Specifies default PORT VID to be used to segregate
s/_/-/
> + ports. Default value - CPSW port number.
> + - mac-address : array of 6 bytes, specifies the MAC address. Always
> + accounted first if present [1]
No need to re-define this here.
> + - local-mac-address : See [1]
> +
> +- mdio : CPSW MDIO bus block description
> + - bus_freq : MDIO Bus frequency
> + See bindings/net/mdio.txt and davinci-mdio.txt
Standard properties clock-frequency or bus-frequency would have been
better...
> +
> +- cpts : The Common Platform Time Sync (CPTS) module description
> + - clocks : should contain the CPTS reference clock
> + - clock-names : should be "cpts"
> + See bindings/clock/clock-bindings.txt
> +
> + Optional properties - all ports:
> + - cpts_clock_mult : Numerator to convert input clock ticks into ns
> + - cpts_clock_shift : Denominator to convert input clock ticks into ns
> + Mult and shift will be calculated basing on CPTS
> + rftclk frequency if both cpts_clock_shift and
> + cpts_clock_mult properties are not provided.
Should have 'ti' prefix and use '-' rather than '_'. However, these are
already defined somewhere else, right? I can't tell that from reading
this.
> +
> +[1] See Documentation/devicetree/bindings/net/ethernet.txt
> +
> +Examples - SOC:
Please don't split example into SoC and board. Just show the flat
example.
> +mac_sw: ethernet_switch@0 {
switch@0
> + compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
> + reg = <0x0 0x4000>;
> + ranges = <0 0 0x4000>;
> + clocks = <&gmac_main_clk>;
> + clock-names = "fck";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + syscon = <&scm_conf>;
> + status = "disabled";
> +
> + interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "rx_thresh", "rx", "tx", "misc"
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpsw_port1: port@1 {
> + reg = <1>;
> + ti,label = "port1";
Not really any better than the node name. Do you really even need this
property?
> + /* Filled in by U-Boot */
> + mac-address = [ 00 00 00 00 00 00 ];
> + phys = <&phy_gmii_sel 1>;
> + };
> +
> + cpsw_port2: port@2 {
> + reg = <2>;
> + ti,label = "port2";
> + /* Filled in by U-Boot */
> + mac-address = [ 00 00 00 00 00 00 ];
> + phys = <&phy_gmii_sel 2>;
> + };
> + };
> +
> + davinci_mdio_sw: mdio@1000 {
> + compatible = "ti,cpsw-mdio","ti,davinci_mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + ti,hwmods = "davinci_mdio";
> + bus_freq = <1000000>;
> + reg = <0x1000 0x100>;
> + };
> +
> + cpts {
> + clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
> + clock-names = "cpts";
> + };
> +};
> +
> +Examples - platform/board:
> +
> +&mac_sw {
> + pinctrl-names = "default", "sleep";
> + status = "okay";
> +};
> +
> +&cpsw_port1 {
> + phy-handle = <ðphy0_sw>;
> + phy-mode = "rgmii";
> + ti,dual_emac_pvid = <1>;
> +};
> +
> +&cpsw_port2 {
> + phy-handle = <ðphy1_sw>;
> + phy-mode = "rgmii";
> + ti,dual_emac_pvid = <2>;
> +};
> +
> +&davinci_mdio_sw {
> + ethphy0_sw: ethernet-phy@0 {
> + reg = <0>;
> + };
> +
> + ethphy1_sw: ethernet-phy@1 {
> + reg = <1>;
> + };
> +};
> --
> 2.17.1
>
^ permalink raw reply
* [PATCH 3/3] EDAC, altera: Use common framework for Stratix10 SDRAM ECC
From: thor.thayer @ 2019-07-09 22:24 UTC (permalink / raw)
To: bp, mchehab, james.morse, robh+dt, mark.rutland, dinguyen
Cc: devicetree, linux-edac, Thor Thayer
In-Reply-To: <1562711090-900-1-git-send-email-thor.thayer@linux.intel.com>
From: Thor Thayer <thor.thayer@linux.intel.com>
The Stratix10 SDRAM ECC is a better match with the devices ECC
framework.
Use the ECC device framework with the linked list to track
SDRAM errors. This simplifies the device tree node as well.
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
---
drivers/edac/altera_edac.c | 32 +++++++++++++++++++++++++++++---
drivers/edac/altera_edac.h | 25 ++++++++++++++++++++++++-
2 files changed, 53 insertions(+), 4 deletions(-)
diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index c2e693e34d43..23e6af7287e4 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -222,7 +222,6 @@ static unsigned long get_total_mem(void)
static const struct of_device_id altr_sdram_ctrl_of_match[] = {
{ .compatible = "altr,sdram-edac", .data = &c5_data},
{ .compatible = "altr,sdram-edac-a10", .data = &a10_data},
- { .compatible = "altr,sdram-edac-s10", .data = &a10_data},
{},
};
MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
@@ -1170,6 +1169,24 @@ static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
return 0;
}
+/*********************** SDRAM EDAC Device Functions *********************/
+
+#ifdef CONFIG_EDAC_ALTERA_SDRAM
+
+static const struct edac_device_prv_data s10_sdramecc_data = {
+ .setup = altr_check_ecc_deps,
+ .ce_clear_mask = ALTR_S10_ECC_SERRPENA,
+ .ue_clear_mask = ALTR_S10_ECC_DERRPENA,
+ .ecc_enable_mask = ALTR_S10_ECC_EN,
+ .ecc_en_ofst = ALTR_S10_ECC_CTRL_SDRAM_OFST,
+ .ce_set_mask = ALTR_S10_ECC_TSERRA,
+ .ue_set_mask = ALTR_S10_ECC_TDERRA,
+ .set_err_ofst = ALTR_S10_ECC_INTTEST_OFST,
+ .ecc_irq_handler = altr_edac_a10_ecc_irq,
+ .inject_fops = &altr_edac_a10_device_inject_fops,
+};
+#endif /* CONFIG_EDAC_ALTERA_SDRAM */
+
/*********************** OCRAM EDAC Device Functions *********************/
#ifdef CONFIG_EDAC_ALTERA_OCRAM
@@ -1759,6 +1776,9 @@ static const struct of_device_id altr_edac_a10_device_of_match[] = {
#ifdef CONFIG_EDAC_ALTERA_SDMMC
{ .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data },
#endif
+#ifdef CONFIG_EDAC_ALTERA_SDRAM
+ { .compatible = "altr,sdram-edac-s10", .data = &s10_sdramecc_data },
+#endif
{},
};
MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
@@ -1889,6 +1909,10 @@ static int validate_parent_available(struct device_node *np)
struct device_node *parent;
int ret = 0;
+ /* SDRAM must be present for Linux (implied parent) */
+ if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
+ return 0;
+
/* Ensure parent device is enabled if parent node exists */
parent = of_parse_phandle(np, "altr,ecc-parent", 0);
if (parent && !of_device_is_available(parent))
@@ -2231,13 +2255,15 @@ static int altr_edac_a10_probe(struct platform_device *pdev)
of_device_is_compatible(child, "altr,socfpga-dma-ecc") ||
of_device_is_compatible(child, "altr,socfpga-usb-ecc") ||
of_device_is_compatible(child, "altr,socfpga-qspi-ecc") ||
+#ifdef CONFIG_EDAC_ALTERA_SDRAM
+ of_device_is_compatible(child, "altr,sdram-edac-s10") ||
+#endif
of_device_is_compatible(child, "altr,socfpga-sdmmc-ecc"))
altr_edac_a10_device_add(edac, child);
#ifdef CONFIG_EDAC_ALTERA_SDRAM
- else if ((of_device_is_compatible(child, "altr,sdram-edac-a10")) ||
- (of_device_is_compatible(child, "altr,sdram-edac-s10")))
+ else if (of_device_is_compatible(child, "altr,sdram-edac-a10"))
of_platform_populate(pdev->dev.of_node,
altr_sdram_ctrl_of_match,
NULL, &pdev->dev);
diff --git a/drivers/edac/altera_edac.h b/drivers/edac/altera_edac.h
index 55654cc4bcdf..3727e72c8c2e 100644
--- a/drivers/edac/altera_edac.h
+++ b/drivers/edac/altera_edac.h
@@ -289,6 +289,29 @@ struct altr_sdram_mc_data {
#define ALTR_A10_ECC_INIT_WATCHDOG_10US 10000
/************* Stratix10 Defines **************/
+#define ALTR_S10_ECC_CTRL_SDRAM_OFST 0x00
+#define ALTR_S10_ECC_EN BIT(0)
+
+#define ALTR_S10_ECC_ERRINTEN_OFST 0x10
+#define ALTR_S10_ECC_ERRINTENS_OFST 0x14
+#define ALTR_S10_ECC_ERRINTENR_OFST 0x18
+#define ALTR_S10_ECC_SERRINTEN BIT(0)
+
+#define ALTR_S10_ECC_INTMODE_OFST 0x1C
+#define ALTR_S10_ECC_INTMODE BIT(0)
+
+#define ALTR_S10_ECC_INTSTAT_OFST 0x20
+#define ALTR_S10_ECC_SERRPENA BIT(0)
+#define ALTR_S10_ECC_DERRPENA BIT(8)
+#define ALTR_S10_ECC_ERRPENA_MASK (ALTR_S10_ECC_SERRPENA | \
+ ALTR_S10_ECC_DERRPENA)
+
+#define ALTR_S10_ECC_INTTEST_OFST 0x24
+#define ALTR_S10_ECC_TSERRA BIT(0)
+#define ALTR_S10_ECC_TDERRA BIT(8)
+#define ALTR_S10_ECC_TSERRB BIT(16)
+#define ALTR_S10_ECC_TDERRB BIT(24)
+
#define ALTR_S10_DERR_ADDRA_OFST 0x2C
/* Stratix10 ECC Manager Defines */
@@ -300,7 +323,7 @@ struct altr_sdram_mc_data {
#define S10_SYSMGR_UE_ADDR_OFST 0x224
#define S10_DDR0_IRQ_MASK BIT(16)
-#define S10_DBE_IRQ_MASK 0x3FE
+#define S10_DBE_IRQ_MASK 0x3FFFE
/* Define ECC Block Offsets for peripherals */
#define ECC_BLK_ADDRESS_OFST 0x40
--
2.7.4
^ permalink raw reply related
* [PATCH 2/3] arm64: dts: Stratix10: Include regs in SDRAM ECC node
From: thor.thayer @ 2019-07-09 22:24 UTC (permalink / raw)
To: bp, mchehab, james.morse, robh+dt, mark.rutland, dinguyen
Cc: devicetree, linux-edac, Thor Thayer
In-Reply-To: <1562711090-900-1-git-send-email-thor.thayer@linux.intel.com>
From: Thor Thayer <thor.thayer@linux.intel.com>
Include the regs directly in the SDRAM node instead of using
a syscon. The Stratix10 SDRAM ECC registers are partitioned
away from other Sys Manager registers so the syscon is no
longer needed for Stratix10.
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 9 ++-------
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index 4b0f674df849..a1e9545de3d3 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -517,11 +517,6 @@
status = "disabled";
};
- sdr: sdr@f8011100 {
- compatible = "altr,sdr-ctl", "syscon";
- reg = <0xf8011100 0xc0>;
- };
-
eccmgr {
compatible = "altr,socfpga-s10-ecc-manager",
"altr,socfpga-a10-ecc-manager";
@@ -533,9 +528,9 @@
#interrupt-cells = <2>;
ranges;
- sdramedac {
+ sdramedac@0xf8011100 {
compatible = "altr,sdram-edac-s10";
- altr,sdr-syscon = <&sdr>;
+ reg = <0xf8011100 0xc0>;
interrupts = <16 4>;
};
--
2.7.4
^ permalink raw reply related
* [PATCH 1/3] Documentation: dt: edac: Add reg to S10 SDRAM node
From: thor.thayer @ 2019-07-09 22:24 UTC (permalink / raw)
To: bp, mchehab, james.morse, robh+dt, mark.rutland, dinguyen
Cc: devicetree, linux-edac, Thor Thayer
In-Reply-To: <1562711090-900-1-git-send-email-thor.thayer@linux.intel.com>
From: Thor Thayer <thor.thayer@linux.intel.com>
Include the register offset and size in the Stratix10 SDRAM node
to be consistent with other ECC modules.
Previously had to follow the phandle to get the register size/offset.
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
---
Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
index 8f52206cfd2a..dd6ba6c020a7 100644
--- a/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
@@ -256,6 +256,7 @@ Subcomponents:
SDRAM ECC
Required Properties:
- compatible : Should be "altr,sdram-edac-s10"
+- reg : Address and size for ECC block registers.
- interrupts : Should be single bit error interrupt.
On-Chip RAM ECC
@@ -313,8 +314,9 @@ Example:
#interrupt-cells = <2>;
ranges;
- sdramedac {
+ sdramedac@0xf8011100 {
compatible = "altr,sdram-edac-s10";
+ reg = <0xf8011100 0xc0>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
};
--
2.7.4
^ permalink raw reply related
* [PATCH 0/3] Stratix10 SDRAM Common EDAC Framework
From: thor.thayer @ 2019-07-09 22:24 UTC (permalink / raw)
To: bp, mchehab, james.morse, robh+dt, mark.rutland, dinguyen
Cc: devicetree, linux-edac, Thor Thayer
From: Thor Thayer <thor.thayer@linux.intel.com>
Use the common Altera EDAC Device Framework for the SDRAM so that
Double Bit Error Addresses can be tracked for SDRAM.
This also simplifies the device tree.
Thor Thayer (3):
Documentation: dt: edac: Add reg to S10 SDRAM node
arm64: dts: Stratix10: Include regs in SDRAM ECC node
EDAC, altera: Use common framework for Stratix10 SDRAM ECC
.../devicetree/bindings/edac/socfpga-eccmgr.txt | 4 ++-
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 9 ++----
drivers/edac/altera_edac.c | 32 ++++++++++++++++++++--
drivers/edac/altera_edac.h | 25 ++++++++++++++++-
4 files changed, 58 insertions(+), 12 deletions(-)
--
2.7.4
^ permalink raw reply
* Re: [PATCH v4 2/2] dt-bindings: mfd: max8998: Add charger subnode binding
From: Rob Herring @ 2019-07-09 21:58 UTC (permalink / raw)
To: Paweł Chmiel
Cc: sre, lee.jones, mark.rutland, linux-kernel, linux-pm, devicetree,
linux-samsung-soc
In-Reply-To: <20190621115602.17559-3-pawel.mikolaj.chmiel@gmail.com>
On Fri, Jun 21, 2019 at 01:56:02PM +0200, Paweł Chmiel wrote:
> This patch adds devicetree bindings documentation for
> battery charging controller as the subnode of MAX8998 PMIC.
>
> Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
> ---
> Changes from v3:
> - Property prefix should be maxim, not max8998
> - Describe what End of Charge in percent means
>
> Changes from v2:
> - Make charge-restart-level-microvolt optional.
> - Make charge-timeout-hours optional.
>
> Changes from v1:
> - Removed unneeded Fixes tag
> - Correct description of all charger values
> - Added missing property unit
> ---
> .../devicetree/bindings/mfd/max8998.txt | 26 +++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/max8998.txt b/Documentation/devicetree/bindings/mfd/max8998.txt
> index 5f2f07c09c90..368f787d6079 100644
> --- a/Documentation/devicetree/bindings/mfd/max8998.txt
> +++ b/Documentation/devicetree/bindings/mfd/max8998.txt
> @@ -48,6 +48,25 @@ Additional properties required if max8998,pmic-buck2-dvs-gpio is defined:
> - max8998,pmic-buck2-dvs-voltage: An array of 2 voltage values in microvolts
> for buck2 regulator that can be selected using dvs gpio.
>
> +Charger: Configuration for battery charging controller should be added
> +inside a child node named 'charger'.
> + Required properties:
> + - maxim,end-of-charge-percentage: End of Charge in percent.
> + When the charge current in constant-voltage phase drops below
> + end-of-charge-percentage of it's start value, charging is terminated.
> + If value equals 0, leave it unchanged. Otherwise it should be value
> + from 10 to 45 by 5 step.
> +
> + Optional properties:
> + - maxim,charge-restart-threshold: Charge restart threshold in millivolts.
> + If property is not present, this will be disabled.
> + Valid values are: 0, 100, 150, 200. If the value equals 0, leave it
> + unchanged.
Needs a unit suffix as defined in property-units.txt.
> +
> + - maxim,charge-timeout: Charge timeout in hours. If property is not
> + present, this will be disabled. Valid values are: 0, 5, 6, 7.
> + If the value equals 0, leave it unchanged.
Needs a unit suffix as defined in property-units.txt.
> +
> Regulators: All the regulators of MAX8998 to be instantiated shall be
> listed in a child node named 'regulators'. Each regulator is represented
> by a child node of the 'regulators' node.
> @@ -97,6 +116,13 @@ Example:
> max8998,pmic-buck2-dvs-gpio = <&gpx0 0 3 0 0>; /* SET3 */
> max8998,pmic-buck2-dvs-voltage = <1350000>, <1300000>;
>
> + /* Charger configuration */
> + charger {
> + maxim,end-of-charge-percentage = <20>;
> + maxim,charge-restart-threshold = <100>;
> + maxim,charge-timeout = <7>;
> + };
> +
> /* Regulators to instantiate */
> regulators {
> ldo2_reg: LDO2 {
> --
> 2.17.1
>
^ permalink raw reply
* Re: devicetree-rebasing.git updates pausing for a couple of months
From: Rob Herring @ 2019-07-09 21:54 UTC (permalink / raw)
To: Ian Campbell; +Cc: devicetree, Frank Rowand, Mark Rutland, Andre Przywara
In-Reply-To: <3bc28d409a6e09046c001611972cc3c33b1695e3.camel@hellion.org.uk>
On Fri, Jun 21, 2019 at 01:01:27PM +0100, Ian Campbell wrote:
> Hi all,
>
> I've no idea if anyone actually uses it any more, but the split out
> devicetree only git repo [0] is not going to receive any new updates
> for a little while (likely 1-2 months) while I relocate to another
> country.
Can you sync your move to the kernel release schedule? JK
Seriously, I've been wondering if we could turn this into a Gitlab CI
job instead. Then it's not solely up to you to run it.
Rob
>
> Ian.
>
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/
>
^ permalink raw reply
* Re: [PATCH v3 1/2] dt-bindings: soc: add mtk svs dt-bindings
From: Rob Herring @ 2019-07-09 21:47 UTC (permalink / raw)
To: Roger Lu
Cc: Kevin Hilman, Nicolas Boichat, Stephen Boyd, Fan Chen,
HenryC Chen, Mark Rutland, Matthias Brugger, Nishanth Menon,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
linux-pm
In-Reply-To: <20190621084348.16834-2-roger.lu@mediatek.com>
On Fri, Jun 21, 2019 at 04:43:47PM +0800, Roger Lu wrote:
> Document the binding for enabling mtk svs on MediaTek SoC.
>
> Signed-off-by: Roger Lu <roger.lu@mediatek.com>
> ---
> .../devicetree/bindings/power/mtk-svs.txt | 88 +++++++++++++++++++
> 1 file changed, 88 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/power/mtk-svs.txt
>
> diff --git a/Documentation/devicetree/bindings/power/mtk-svs.txt b/Documentation/devicetree/bindings/power/mtk-svs.txt
> new file mode 100644
> index 000000000000..6a71992ef162
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/mtk-svs.txt
> @@ -0,0 +1,88 @@
> +* Mediatek Smart Voltage Scaling (MTK SVS)
> +
> +This describes the device tree binding for the MTK SVS controller (bank)
> +which helps provide the optimized CPU/GPU/CCI voltages. This device also
> +needs thermal data to calculate thermal slope for accurately compensate
> +the voltages when temperature change.
> +
> +Required properties:
> +- compatible:
> + - "mediatek,mt8183-svs" : For MT8183 family of SoCs
> +- reg: Address range of the MTK SVS controller.
> +- interrupts: IRQ for the MTK SVS controller.
> +- clocks, clock-names: Clocks needed for the svs controller. required
> + clocks are:
> + "main_clk": Main clock needed for register access
'_clk' is redundant and can be dropped.
> +- nvmem-cells: Phandle to the calibration data provided by a nvmem device.
> +- nvmem-cell-names: Should be "svs-calibration-data" and "calibration-data"
> +
> +Subnodes:
> +- svs_cpu_little: SVS bank device node of little CPU
> + compatible: "mediatek,mt8183-svs-cpu-little"
> + operating-points-v2: OPP table hooked by SVS little CPU bank.
> + SVS will optimze this OPP table voltage part.
> + vcpu-little-supply: PMIC buck of little CPU
> +- svs_cpu_big: SVS bank device node of big CPU
> + compatible: "mediatek,mt8183-svs-cpu-big"
> + operating-points-v2: OPP table hooked by SVS big CPU bank.
> + SVS will optimze this OPP table voltage part.
> + vcpu-big-supply: PMIC buck of big CPU
> +- svs_cci: SVS bank device node of CCI
> + compatible: "mediatek,mt8183-svs-cci"
> + operating-points-v2: OPP table hooked by SVS CCI bank.
> + SVS will optimze this OPP table voltage part.
> + vcci-supply: PMIC buck of CCI
> +- svs_gpu: SVS bank device node of GPU
> + compatible: "mediatek,mt8183-svs-gpu"
> + operating-points-v2: OPP table hooked by SVS GPU bank.
> + SVS will optimze this OPP table voltage part.
> + vgpu-spply: PMIC buck of GPU
typo
> +
> +Example:
> +
> + svs: svs@1100b000 {
> + compatible = "mediatek,mt8183-svs";
> + reg = <0 0x1100b000 0 0x1000>;
> + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW 0>;
> + clocks = <&infracfg CLK_INFRA_THERM>;
> + clock-names = "main_clk";
> + nvmem-cells = <&svs_calibration>, <&thermal_calibration>;
> + nvmem-cell-names = "svs-calibration-data", "calibration-data";
> +
> + svs_cpu_little: svs_cpu_little {
> + compatible = "mediatek,mt8183-svs-cpu-little";
> + operating-points-v2 = <&cluster0_opp>;
> + };
> +
> + svs_cpu_big: svs_cpu_big {
> + compatible = "mediatek,mt8183-svs-cpu-big";
> + operating-points-v2 = <&cluster1_opp>;
> + };
> +
> + svs_cci: svs_cci {
> + compatible = "mediatek,mt8183-svs-cci";
> + operating-points-v2 = <&cci_opp>;
> + };
> +
> + svs_gpu: svs_gpu {
> + compatible = "mediatek,mt8183-svs-gpu";
> + power-domains = <&scpsys MT8183_POWER_DOMAIN_MFG_2D>;
> + operating-points-v2 = <&gpu_opp_table>;
> + };
This all looks like redundant data which can be found in the cpu, gpu,
etc. nodes. Can't you parse those nodes to get the information?
> + };
> +
> + &svs_cpu_little {
> + vcpu-little-supply = <&mt6358_vproc12_reg>;
Don't split examples like this. Just should one flat example.
> + };
> +
> + &svs_cpu_big {
> + vcpu-big-supply = <&mt6358_vproc11_reg>;
> + };
> +
> + &svs_cci {
> + vcci-supply = <&mt6358_vproc12_reg>;
> + };
> +
> + &svs_gpu {
> + vgpu-spply = <&mt6358_vgpu_reg>;
> + };
> --
> 2.18.0
>
^ permalink raw reply
* Re: [PATCH v2 00/10] net: hisilicon: Add support for HI13X1 to hip04_eth
From: David Miller @ 2019-07-09 21:29 UTC (permalink / raw)
To: xiaojiangfeng
Cc: robh+dt, yisen.zhuang, salil.mehta, mark.rutland, dingtianhong,
netdev, devicetree, linux-kernel, leeyou.li, nixiaoming,
jianping.liu, xiekunxun
In-Reply-To: <1562643071-46811-1-git-send-email-xiaojiangfeng@huawei.com>
From: Jiangfeng Xiao <xiaojiangfeng@huawei.com>
Date: Tue, 9 Jul 2019 11:31:01 +0800
> The main purpose of this patch series is to extend the
> hip04_eth driver to support HI13X1_GMAC.
>
> The offset and bitmap of some registers of HI13X1_GMAC
> are different from hip04_eth common soc. In addition,
> the definition of send descriptor and parsing descriptor
> are different from hip04_eth common soc. So the macro
> of the register offset is redefined to adapt the HI13X1_GMAC.
>
> Clean up the sparse warning by the way.
>
> Change since v1:
> * Add a cover letter.
Series applied, thanks.
^ permalink raw reply
* Re: [PATCH V4 2/5] clocksource/drivers/sysctr: Add clock-frequency property
From: Rob Herring @ 2019-07-09 20:30 UTC (permalink / raw)
To: Anson Huang
Cc: Daniel Lezcano, Thomas Gleixner, Mark Rutland, Shawn Guo,
Sascha Hauer, Sascha Hauer, Fabio Estevam, Leonard Crestez,
Viresh Kumar, Daniel Baluta, Bai Ping, Lucas Stach, Abel Vesa,
Andrey Smirnov, Carlo Caione, Angus Ainslie (Purism),
Guido Günther, linux-kernel@vger.kernel.org, devicetree
In-Reply-To: <20190701093826.5472-2-Anson.Huang@nxp.com>
On Mon, Jul 1, 2019 at 3:47 AM <Anson.Huang@nxp.com> wrote:
>
> From: Anson Huang <Anson.Huang@nxp.com>
'dt-bindings: timer: ...' for the subject.
>
> Systems which use platform driver model for clock driver require the
> clock frequency to be supplied via device tree when system counter
> driver is enabled.
This is a DT binding. What's a platform driver?
>
> This is necessary as in the platform driver model the of_clk operations
> do not work correctly because system counter driver is initialized in
> early phase of system boot up, and clock driver using platform driver
> model is NOT ready at that time, it will cause system counter driver
> initialization failed.
>
> Add clock-frequency property to the device tree bindings of the NXP
> system counter, so the driver can tell timer-of driver to get clock
> frequency from DT directly instead of doing of_clk operations via
> clk APIs.
While you've now given a good explanation why you need this, it all
sounds like linux specific issues and a DT change should not be
necessary.
Presumably, 'clocks' points to a fixed-clock node, right? Just parse
the 'clocks' phandle and fetch the frequency from that node if you
need to get the frequency 'early'.
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> No change.
> ---
> .../devicetree/bindings/timer/nxp,sysctr-timer.txt | 15 +++++++++------
> 1 file changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.txt b/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.txt
> index d576599..7088a0e 100644
> --- a/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.txt
> +++ b/Documentation/devicetree/bindings/timer/nxp,sysctr-timer.txt
> @@ -11,15 +11,18 @@ Required properties:
> - reg : Specifies the base physical address and size of the comapre
> frame and the counter control, read & compare.
> - interrupts : should be the first compare frames' interrupt
> -- clocks : Specifies the counter clock.
> -- clock-names: Specifies the clock's name of this module
> +- clocks : Specifies the counter clock, mutually exclusive with clock-frequency.
> +- clock-names : Specifies the clock's name of this module, mutually exclusive with
> + clock-frequency.
> +- clock-frequency : Specifies system counter clock frequency, mutually exclusive with
> + clocks/clock-names.
It doesn't really work to say one or the other is needed unless you
make the OS support both cases.
Rob
^ permalink raw reply
* Re: [PATCH v2 7/7] arm64: dts: allwinner: a64: enable ANX6345 bridge on Teres-I
From: Vasily Khoruzhick @ 2019-07-09 20:30 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mark Rutland, devicetree, Sean Paul, David Airlie,
Greg Kroah-Hartman, linux-kernel, dri-devel, Chen-Yu Tsai,
Rob Herring, Torsten Duwe, Laurent Pinchart, Harald Geyer,
Thierry Reding, Thomas Gleixner, arm-linux, Icenowy Zheng
In-Reply-To: <20190709085532.cdqv7whuesrjs64c@flea>
On Tue, Jul 9, 2019 at 1:55 AM Maxime Ripard <maxime.ripard@bootlin.com> wrote:
>
> On Mon, Jul 08, 2019 at 05:49:21PM -0700, Vasily Khoruzhick wrote:
> > > > Maybe instead of edp-connector one would introduce integrator's specific
> > > > connector, for example with compatible "olimex,teres-edp-connector"
> > > > which should follow edp abstract connector rules? This will be at least
> > > > consistent with below presentation[1] - eDP requirements depends on
> > > > integrator. Then if olimex has standard way of dealing with panels
> > > > present in olimex/teres platforms the driver would then create
> > > > drm_panel/drm_connector/drm_bridge(?) according to these rules, I guess.
> > > > Anyway it still looks fishy for me :), maybe because I am not
> > > > familiarized with details of these platforms.
> > >
> > > That makes sense yes
> >
> > Actually, it makes no sense at all. Current implementation for anx6345
> > driver works fine as is with any panel specified assuming panel delays
> > are long enough for connected panel. It just doesn't use panel timings
> > from the driver. Creating a platform driver for connector itself looks
> > redundant since it can't be reused, it doesn't describe actual
> > hardware and it's just defeats purpose of DT by introducing
> > board-specific code.
>
> I'm not sure where you got the idea that the purpose of DT is to not
> have any board-specific code.
I believe DT was an attempt to move to declarative approach for
describing hardware. Yes, we have different compatibles for different
devices but they're specific to particular device rather than
particular board. Device interconnection is described in DT along with
some properties rather than in board-specific C-file. Introducing
board-specific compatible for a connector isn't looking right to me.
> It's perfectly fine to have some, that's even why there's a compatible
> assigned to each and every board.
>
> What the DT is about is allowing us to have a generic behaviour that
> we can detect: we can have a given behaviour for a given board, and a
> separate one for another one, and this will be evaluated at runtime.
>
> This is *exactly* what this is about: we can have a compatible that
> sets a given, more specific, behaviour (olimex,teres-edp-connector)
> while saying that this is compatible with the generic behaviour
> (edp-connector). That way, any OS will know what quirk to apply if
> needed, and if not that it can use the generic behaviour.
>
> And we could create a generic driver, for the generic behaviour if
> needed.
>
> > There's another issue: if we introduce edp-connector we'll have to
> > specify power up delays somewhere (in dts? or in platform driver?), so
> > edp-connector doesn't really solve the issue of multiple panels with
> > same motherboard.
>
> And that's what that compatible is about :)
Sorry, I fail to see how it would be different from using existing
panels infrastructure and different panels compatibles. I think Rob's
idea was to introduce generic edp-connector. If we can't make it
generic then let's use panel infrastructure.
> > I'd say DT overlays should be preferred solution here, not another
> > connector binding.
>
> Overlays are a way to apply a device tree dynamically. It's orthogonal
> to the binding.
It isn't orthogonal to original problem though.
> Maxime
>
> --
> Maxime Ripard, Bootlin
> Embedded Linux and Kernel engineering
> https://bootlin.com
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCH 2/4] dt-bindings: clock: imx8mm: Add system counter clock
From: Rob Herring @ 2019-07-09 20:18 UTC (permalink / raw)
To: Anson.Huang
Cc: catalin.marinas, will, robh+dt, mark.rutland, shawnguo, s.hauer,
kernel, festevam, mturquette, sboyd, leonard.crestez,
aisheng.dong, ping.bai, daniel.baluta, peng.fan, abel.vesa,
linux-arm-kernel, linux-kernel, devicetree, linux-clk, Linux-imx
In-Reply-To: <20190621070720.12395-2-Anson.Huang@nxp.com>
On Fri, 21 Jun 2019 15:07:18 +0800, Anson.Huang@nxp.com wrote:
> From: Anson Huang <Anson.Huang@nxp.com>
>
> Add i.MX8MM system counter clock macro definition.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> include/dt-bindings/clock/imx8mm-clock.h | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 5/6] dt-bindings: usb: bdc: Update compatible strings
From: Rob Herring @ 2019-07-09 20:14 UTC (permalink / raw)
Cc: linux-kernel, Al Cooper, devicetree, Felipe Balbi,
Greg Kroah-Hartman, linux-usb, Luis Chamberlain, Mark Rutland
In-Reply-To: <1561064991-16874-6-git-send-email-alcooperx@gmail.com>
On Thu, 20 Jun 2019 17:09:50 -0400, Al Cooper wrote:
> Remove "brcm,bdc-v0.16" because it was never used on any system.
> Add "brcm,bdc-udc-v3.1" which exists for any STB system with BDC.
>
> Signed-off-by: Al Cooper <alcooperx@gmail.com>
> ---
> Documentation/devicetree/bindings/usb/brcm,bdc.txt | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v14 2/2] dt-bindings: spi: Document Renesas R-Car Gen3 RPC-IF controller bindings
From: Rob Herring @ 2019-07-09 20:12 UTC (permalink / raw)
Cc: broonie, marek.vasut, linux-kernel, linux-spi, bbrezillon,
linux-renesas-soc, Geert Uytterhoeven, lee.jones, sergei.shtylyov,
robh+dt, mark.rutland, devicetree, juliensu, Simon Horman,
Mason Yang, miquel.raynal
In-Reply-To: <1561023046-20886-3-git-send-email-masonccyang@mxic.com.tw>
On Thu, 20 Jun 2019 17:30:46 +0800, Mason Yang wrote:
> Dcument the bindings used by the Renesas R-Car Gen3 RPC-IF controller.
>
> Signed-off-by: Mason Yang <masonccyang@mxic.com.tw>
> ---
> .../devicetree/bindings/spi/spi-renesas-rpc.txt | 43 ++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/spi-renesas-rpc.txt
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v6 1/6] dt-bindings: ap806: add the cluster clock node in the syscon file
From: Rob Herring @ 2019-07-09 20:10 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Stephen Boyd, Mike Turquette, linux-clk, linux-kernel, devicetree,
Jason Cooper, Andrew Lunn, Sebastian Hesselbarth,
Thomas Petazzoni, linux-arm-kernel, Antoine Tenart,
Miquèl Raynal, Maxime Chevallier
In-Reply-To: <20190619141539.16884-2-gregory.clement@bootlin.com>
On Wed, Jun 19, 2019 at 04:15:34PM +0200, Gregory CLEMENT wrote:
> Document the device tree binding for the cluster clock controllers found
> in the Armada 7K/8K SoCs.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> .../arm/marvell/ap806-system-controller.txt | 25 +++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
> index 7b8b8eb0191f..4a3bb9c12312 100644
> --- a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
> +++ b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
> @@ -143,3 +143,28 @@ ap_syscon1: system-controller@6f8000 {
> #thermal-sensor-cells = <1>;
> };
> };
> +
> +Cluster clocks:
> +---------------
> +
> +Device Tree Clock bindings for cluster clock of AP806 Marvell. Each
> +cluster contain up to 2 CPUs running at the same frequency.
> +
> +Required properties:
> +- compatible: must be "marvell,ap806-cpu-clock";
> +- #clock-cells : should be set to 1.
> +- clocks : shall be the input parents clock phandle for the clock.
How many clocks?
> +- reg: register range associated with the cluster clocks
> +
> +
> +ap_syscon1: system-controller@6f8000 {
> + compatible = "marvell,armada-ap806-syscon1", "syscon", "simple-mfd";
> + reg = <0x6f8000 0x1000>;
> +
> + cpu_clk: clock-cpu@0 {
Should be '...@274'
> + compatible = "marvell,ap806-cpu-clock";
> + clocks = <&ap_clk 0>, <&ap_clk 1>;
> + #clock-cells = <1>;
> + reg = <0x274 0xa30>;
> + };
> +};
> --
> 2.20.1
>
^ permalink raw reply
* Re: [Patch v3 2/2] dt-bindings: spi: spi-fsl-qspi: Add bindings of ls1088a and ls1012a
From: Rob Herring @ 2019-07-09 20:08 UTC (permalink / raw)
To: Ashish Kumar
Cc: devicetree, bbrezillon, Kuldeep Singh, Ashish Kumar, broonie,
linux-mtd, linux-arm-kernel
In-Reply-To: <1560942714-13330-3-git-send-email-Ashish.Kumar@nxp.com>
On Wed, 19 Jun 2019 16:41:54 +0530, Ashish Kumar wrote:
> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
> ---
> v3:
> Rebase to top
> v2:
> Convert to patch series and rebasing done on top of tree
>
> Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt | 2 ++
> 1 file changed, 2 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [Patch v3 1/2] dt-bindings: spi: spi-fsl-qspi: Add ls2080a compatibility string to bindings
From: Rob Herring @ 2019-07-09 20:08 UTC (permalink / raw)
To: Ashish Kumar
Cc: devicetree, bbrezillon, Kuldeep Singh, Ashish Kumar, broonie,
linux-mtd, linux-arm-kernel
In-Reply-To: <1560942714-13330-2-git-send-email-Ashish.Kumar@nxp.com>
On Wed, 19 Jun 2019 16:41:53 +0530, Ashish Kumar wrote:
> There are 2 version of QSPI-IP, according to which controller registers sets
> can be big endian or little endian.There are some other minor changes like
> RX fifo depth etc.
>
> The big endian version uses driver compatible "fsl,ls1021a-qspi" and
> little endian version uses driver compatible "fsl,ls2080a-qspi"
>
> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com>
> ---
> v3:
> Rebase to top
> v2:
> Convert to patch series and rebasing done on top of tree
>
> Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 1/5] dt-bindings: pwm-stm32: add #pwm-cells
From: Rob Herring @ 2019-07-09 20:04 UTC (permalink / raw)
Cc: thierry.reding, robh+dt, alexandre.torgue, mark.rutland, linux,
mcoquelin.stm32, fabrice.gasnier, devicetree, linux-arm-kernel,
linux-kernel, linux-pwm, benjamin.gaignard, linux-stm32
In-Reply-To: <1560937925-8990-2-git-send-email-fabrice.gasnier@st.com>
On Wed, 19 Jun 2019 11:52:01 +0200, Fabrice Gasnier wrote:
> STM32 Timers support generic 3 cells PWM bindings to encode PWM number,
> period and polarity as defined in pwm.txt.
>
> Fixes: cd9a99c2f8e8 ("dt-bindings: pwm: Add STM32 bindings")
>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
> ---
> Documentation/devicetree/bindings/pwm/pwm-stm32.txt | 3 +++
> 1 file changed, 3 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2] dt-bindings: serial: add documentation for Rx in-band wakeup support
From: Rob Herring @ 2019-07-09 20:04 UTC (permalink / raw)
Cc: mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA,
drinkcat-F7+t8E8rja9g9hUCZPvPmw,
changqi.hu-NuS5LvNUpcJWk0Htik3J/w,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-serial-u79uwXL29TY76Z2rM5mHXA, Claire Chang
In-Reply-To: <20190619084110.136713-1-tientzu-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
On Wed, 19 Jun 2019 16:41:10 +0800, Claire Chang wrote:
> To support Rx in-band wakeup, one must create an interrupt specifier with
> edge sensitivity on Rx pin and an addtional pinctrl to reconfigure Rx pin
> to normal GPIO in sleep state. Driver will switch to sleep mode pinctrl and
> enable irq wake before suspend and restore to default settings when
> resuming.
>
> Signed-off-by: Claire Chang <tientzu-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> ---
> changes in v2:
> just document 'interrupts' instead of 'interrupts-extended'
>
> .../devicetree/bindings/serial/mtk-uart.txt | 13 +++++++++++--
> 1 file changed, 11 insertions(+), 2 deletions(-)
>
Applied, thanks.
Rob
^ permalink raw reply
* Re: [PATCHv2] clk: add imx8 clk defines
From: Rob Herring @ 2019-07-09 20:03 UTC (permalink / raw)
To: Oliver Graute
Cc: sboyd, mturquette, Oliver Graute, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Mark Rutland, Aisheng Dong, Ulf Hansson, linux-kernel,
linux-arm-kernel, devicetree
In-Reply-To: <20190619074000.30852-1-oliver.graute@gmail.com>
On Wed, 19 Jun 2019 09:39:52 +0200, Oliver Graute wrote:
> From: Oliver Graute <oliver.graute@kococonnector.com>
>
> added header defines for imx8qm clock
>
> Signed-off-by: Oliver Graute <oliver.graute@kococonnector.com>
> ---
> include/dt-bindings/clock/imx8qm-clock.h | 851 +++++++++++++++++++++++
> 1 file changed, 851 insertions(+)
> create mode 100644 include/dt-bindings/clock/imx8qm-clock.h
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 5/7] ASoC: rockchip: rockchip-max98090: Add node for HDMI
From: Rob Herring @ 2019-07-09 20:01 UTC (permalink / raw)
To: Cheng-Yi Chiang
Cc: linux-kernel, Hans Verkuil, Bartlomiej Zolnierkiewicz,
Greg Kroah-Hartman, Philipp Zabel, Mark Brown, Liam Girdwood,
Takashi Iwai, Jaroslav Kysela, Russell King, Andrzej Hajda,
Laurent Pinchart, David Airlie, Daniel Vetter, Heiko Stuebner,
dianders, dgreid, tzungbi, linux-media, alsa-devel, dri-devel,
linux-arm-kernel
In-Reply-To: <20190603043251.226549-6-cychiang@chromium.org>
On Mon, Jun 03, 2019 at 12:32:49PM +0800, Cheng-Yi Chiang wrote:
> Let user specify HDMI node so machine driver can use it to let codec
> driver register callback on correct hdmi-notifier.
>
> Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
> ---
> Documentation/devicetree/bindings/sound/rockchip-max98090.txt | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/sound/rockchip-max98090.txt b/Documentation/devicetree/bindings/sound/rockchip-max98090.txt
> index a805aa99ad75..dae57c14864e 100644
> --- a/Documentation/devicetree/bindings/sound/rockchip-max98090.txt
> +++ b/Documentation/devicetree/bindings/sound/rockchip-max98090.txt
> @@ -7,6 +7,7 @@ Required properties:
> connected to the CODEC
> - rockchip,audio-codec: The phandle of the MAX98090 audio codec
> - rockchip,headset-codec: The phandle of Ext chip for jack detection
> +- rockchip,hdmi: The phandle of HDMI node for HDMI jack detection
>
> Example:
>
> @@ -16,4 +17,5 @@ sound {
> rockchip,i2s-controller = <&i2s>;
> rockchip,audio-codec = <&max98090>;
> rockchip,headset-codec = <&headsetcodec>;
> + rockchip,hdmi= <&hdmi>;
space ^
With that,
Acked-by: Rob Herring <robh@kernel.org>
> };
> --
> 2.22.0.rc1.257.g3120a18244-goog
>
^ permalink raw reply
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