* [PATCH 2/3 v2] dt-bindings: gpio: aspeed: Add SGPIO support
From: Hongwei Zhang @ 2019-07-12 20:14 UTC (permalink / raw)
To: Joel Stanley, Andrew Jeffery, Linus Walleij, devicetree
Cc: Hongwei Zhang, Rob Herring, Mark Rutland, Bartosz Golaszewski,
linux-aspeed, linux-kernel, linux-arm-kernel, linux-gpio
Add bindings to support SGPIO on AST2400 or AST2500.
Signed-off-by: Hongwei Zhang <hongweiz@ami.com>
---
.../devicetree/bindings/gpio/sgpio-aspeed.txt | 43 ++++++++++++++++++++++
1 file changed, 43 insertions(+)
create mode 100755 Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
diff --git a/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt b/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
new file mode 100755
index 0000000..3ae2b79
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/sgpio-aspeed.txt
@@ -0,0 +1,43 @@
+Aspeed SGPIO controller Device Tree Bindings
+-------------------------------------------
+
+Required properties:
+- compatible : Either "aspeed,ast2400-sgpio" or "aspeed,ast2500-sgpio"
+
+- #gpio-cells : Should be two
+ - First cell is the GPIO line number
+ - Second cell is used to specify optional
+ parameters (unused)
+
+- reg : Address and length of the register set for the device
+- gpio-controller : Marks the device node as a GPIO controller.
+- interrupts : Interrupt specifier (see interrupt bindings for
+ details)
+
+- interrupt-controller : Mark the GPIO controller as an interrupt-controller
+
+- nr-gpios : number of GPIO pins to serialise. (should be multiple of 8, up to 80 pins)
+ if not specified, defaults to 80.
+
+- clocks : A phandle to the APB clock for SGPM clock division
+
+- bus-frequency : SGPM CLK frequency, if not specified defaults to 1 MHz
+
+
+The sgpio and interrupt properties are further described in their respective bindings documentation:
+
+- Documentation/devicetree/bindings/sgpio/gpio.txt
+- Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+
+ Example:
+ sgpio@1e780200 {
+ #gpio-cells = <2>;
+ compatible = "aspeed,ast2500-sgpio";
+ gpio-controller;
+ interrupts = <40>;
+ reg = <0x1e780200 0x0100>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ interrupt-controller;
+ nr-gpios = <80>;
+ bus-frequency = <1000000>;
+ };
--
2.7.4
^ permalink raw reply related
* Re: [PATCH 1/2] leds: Add control of the voltage/current regulator to the LED core
From: Dan Murphy @ 2019-07-12 18:49 UTC (permalink / raw)
To: Jean-Jacques Hiblot, jacek.anaszewski, pavel, robh+dt,
mark.rutland, daniel.thompson
Cc: linux-leds, linux-kernel, devicetree
In-Reply-To: <20190708103547.23528-2-jjhiblot@ti.com>
JJ
On 7/8/19 5:35 AM, Jean-Jacques Hiblot wrote:
> A LED is usually powered by a voltage/current regulator. Let the LED core
Let the LED core know
> about it. This allows the LED core to turn on or off the power supply
> as needed.
>
> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
> ---
> drivers/leds/led-class.c | 10 ++++++++
> drivers/leds/led-core.c | 53 +++++++++++++++++++++++++++++++++++++---
> include/linux/leds.h | 4 +++
> 3 files changed, 64 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/leds/led-class.c b/drivers/leds/led-class.c
> index 4793e77808e2..e01b2d982564 100644
> --- a/drivers/leds/led-class.c
> +++ b/drivers/leds/led-class.c
> @@ -17,6 +17,7 @@
> #include <linux/slab.h>
> #include <linux/spinlock.h>
> #include <linux/timer.h>
> +#include <linux/regulator/consumer.h>
What if you move this to leds.h so core and class can both include it.
> #include <uapi/linux/uleds.h>
> #include "leds.h"
>
> @@ -272,6 +273,15 @@ int of_led_classdev_register(struct device *parent, struct device_node *np,
> dev_warn(parent, "Led %s renamed to %s due to name collision",
> led_cdev->name, dev_name(led_cdev->dev));
>
> + led_cdev->regulator = devm_regulator_get(led_cdev->dev, "power");
Is the regulator always going to be called power?
> + if (IS_ERR(led_cdev->regulator)) {
> + dev_err(led_cdev->dev, "Cannot get the power supply for %s\n",
> + led_cdev->name);
> + device_unregister(led_cdev->dev);
> + mutex_unlock(&led_cdev->led_access);
> + return PTR_ERR(led_cdev->regulator);
This is listed as optional in the DT doc. This appears to be required.
I prefer to keep it optional. Many LED drivers are connected to fixed
non-managed supplies.
> + }
> +
> if (led_cdev->flags & LED_BRIGHT_HW_CHANGED) {
> ret = led_add_brightness_hw_changed(led_cdev);
> if (ret) {
> diff --git a/drivers/leds/led-core.c b/drivers/leds/led-core.c
> index 7107cd7e87cf..139de6b08cad 100644
> --- a/drivers/leds/led-core.c
> +++ b/drivers/leds/led-core.c
> @@ -16,6 +16,7 @@
> #include <linux/rwsem.h>
> #include <linux/slab.h>
> #include "leds.h"
> +#include <linux/regulator/consumer.h>
>
> DECLARE_RWSEM(leds_list_lock);
> EXPORT_SYMBOL_GPL(leds_list_lock);
> @@ -23,6 +24,31 @@ EXPORT_SYMBOL_GPL(leds_list_lock);
> LIST_HEAD(leds_list);
> EXPORT_SYMBOL_GPL(leds_list);
>
> +static bool __led_need_regulator_update(struct led_classdev *led_cdev,
> + int brightness)
> +{
> + bool new_regulator_state = (brightness != LED_OFF);
> +
> + return led_cdev->regulator_state != new_regulator_state;
> +}
> +
> +static int __led_handle_regulator(struct led_classdev *led_cdev,
> + int brightness)
> +{
> + if (__led_need_regulator_update(led_cdev, brightness)) {
> + int ret;
Prefer to this to be moved up.
> +
> + if (brightness != LED_OFF)
> + ret = regulator_enable(led_cdev->regulator);
> + else
> + ret = regulator_disable(led_cdev->regulator);
> + if (ret)
> + return ret;
new line
> + led_cdev->regulator_state = (brightness != LED_OFF);
> + }
> + return 0;
> +}
> +
> static int __led_set_brightness(struct led_classdev *led_cdev,
> enum led_brightness value)
> {
> @@ -80,6 +106,7 @@ static void led_timer_function(struct timer_list *t)
> }
>
> led_set_brightness_nosleep(led_cdev, brightness);
> + __led_handle_regulator(led_cdev, brightness);
Again this seems to indicate that the regulator is a required property
for the LEDs
This needs to be made optional. And the same comment through out for
every call.
>
> /* Return in next iteration if led is in one-shot mode and we are in
> * the final blink state so that the led is toggled each delay_on +
> @@ -115,6 +142,8 @@ static void set_brightness_delayed(struct work_struct *ws)
> if (ret == -ENOTSUPP)
> ret = __led_set_brightness_blocking(led_cdev,
> led_cdev->delayed_set_value);
> + __led_handle_regulator(led_cdev, led_cdev->delayed_set_value);
> +
> if (ret < 0 &&
> /* LED HW might have been unplugged, therefore don't warn */
> !(ret == -ENODEV && (led_cdev->flags & LED_UNREGISTERING) &&
> @@ -141,6 +170,7 @@ static void led_set_software_blink(struct led_classdev *led_cdev,
> /* never on - just set to off */
> if (!delay_on) {
> led_set_brightness_nosleep(led_cdev, LED_OFF);
> + __led_handle_regulator(led_cdev, LED_OFF);
> return;
> }
>
> @@ -148,6 +178,7 @@ static void led_set_software_blink(struct led_classdev *led_cdev,
> if (!delay_off) {
> led_set_brightness_nosleep(led_cdev,
> led_cdev->blink_brightness);
> + __led_handle_regulator(led_cdev, led_cdev->blink_brightness);
> return;
> }
>
> @@ -256,8 +287,14 @@ void led_set_brightness_nopm(struct led_classdev *led_cdev,
> enum led_brightness value)
> {
> /* Use brightness_set op if available, it is guaranteed not to sleep */
> - if (!__led_set_brightness(led_cdev, value))
> - return;
> + if (!__led_set_brightness(led_cdev, value)) {
> + /*
> + * if regulator state doesn't need to be changed, that is all/
> + * Otherwise delegate the change to a work queue
> + */
> + if (!__led_need_regulator_update(led_cdev, value))
> + return;
> + }
>
> /* If brightness setting can sleep, delegate it to a work queue task */
> led_cdev->delayed_set_value = value;
> @@ -280,6 +317,8 @@ EXPORT_SYMBOL_GPL(led_set_brightness_nosleep);
> int led_set_brightness_sync(struct led_classdev *led_cdev,
> enum led_brightness value)
> {
> + int ret;
> +
> if (led_cdev->blink_delay_on || led_cdev->blink_delay_off)
> return -EBUSY;
>
> @@ -288,7 +327,15 @@ int led_set_brightness_sync(struct led_classdev *led_cdev,
> if (led_cdev->flags & LED_SUSPENDED)
> return 0;
>
> - return __led_set_brightness_blocking(led_cdev, led_cdev->brightness);
> + ret = __led_set_brightness_blocking(led_cdev, led_cdev->brightness);
> + if (ret)
> + return ret;
> +
> + ret = __led_handle_regulator(led_cdev, led_cdev->brightness);
Can't you just return here?
Dan
> + if (ret)
> + return ret;
> +
> + return 0;
> }
> EXPORT_SYMBOL_GPL(led_set_brightness_sync);
>
> diff --git a/include/linux/leds.h b/include/linux/leds.h
> index 9b2bf574a17a..bee8e3f8dddd 100644
> --- a/include/linux/leds.h
> +++ b/include/linux/leds.h
> @@ -123,6 +123,10 @@ struct led_classdev {
>
> /* Ensures consistent access to the LED Flash Class device */
> struct mutex led_access;
> +
> + /* regulator */
> + struct regulator *regulator;
> + bool regulator_state;
> };
>
> extern int of_led_classdev_register(struct device *parent,
^ permalink raw reply
* Re: [PATCH 2/2] dt-bindings: leds: document new "power-supply" property
From: Dan Murphy @ 2019-07-12 18:38 UTC (permalink / raw)
To: Jean-Jacques Hiblot, jacek.anaszewski, pavel, robh+dt,
mark.rutland, daniel.thompson
Cc: linux-leds, linux-kernel, devicetree
In-Reply-To: <20190708103547.23528-3-jjhiblot@ti.com>
JJ
On 7/8/19 5:35 AM, Jean-Jacques Hiblot wrote:
> Most of the LEDs are powered by a voltage/current regulator. describing in
> the device-tree makes it possible for the LED core to enable/disable it
> when needed.
This should be patch 1.
> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
> ---
> Documentation/devicetree/bindings/leds/common.txt | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/leds/common.txt b/Documentation/devicetree/bindings/leds/common.txt
> index 70876ac11367..e093a2b7eb90 100644
> --- a/Documentation/devicetree/bindings/leds/common.txt
> +++ b/Documentation/devicetree/bindings/leds/common.txt
> @@ -61,6 +61,11 @@ Optional properties for child nodes:
> - panic-indicator : This property specifies that the LED should be used,
> if at all possible, as a panic indicator.
>
> +- power-supply : A voltage/current regulator used to to power the LED. When a
> + LED is turned off, the LED core disable its regulator. The
> + same regulator can power many LED (or other) devices. It is
> + turned off only when all of its users disabled it.
> +
> - trigger-sources : List of devices which should be used as a source triggering
> this LED activity. Some LEDs can be related to a specific
> device and should somehow indicate its state. E.g. USB 2.0
Do you have an example update?
Dan
^ permalink raw reply
* Re: [PATCH v2 6/7] dt-bindings: net: realtek: Add property to configure LED mode
From: Matthias Kaehlcke @ 2019-07-12 17:28 UTC (permalink / raw)
To: Florian Fainelli
Cc: Rob Herring, Andrew Lunn, Heiner Kallweit, David S . Miller,
Mark Rutland, netdev, devicetree, linux-kernel@vger.kernel.org,
Douglas Anderson
In-Reply-To: <7d102d81-750d-32d9-a554-95f018e69f2f@gmail.com>
Hi Florian,
On Wed, Jul 10, 2019 at 09:28:39AM -0700, Florian Fainelli wrote:
> On 7/10/19 8:55 AM, Rob Herring wrote:
> > On Wed, Jul 3, 2019 at 5:23 PM Matthias Kaehlcke <mka@chromium.org> wrote:
> >>
> >> Hi Florian,
> >>
> >> On Wed, Jul 03, 2019 at 02:37:47PM -0700, Florian Fainelli wrote:
> >>> On 7/3/19 12:37 PM, Matthias Kaehlcke wrote:
> >>>> The LED behavior of some Realtek PHYs is configurable. Add the
> >>>> property 'realtek,led-modes' to specify the configuration of the
> >>>> LEDs.
> >>>>
> >>>> Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
> >>>> ---
> >>>> Changes in v2:
> >>>> - patch added to the series
> >>>> ---
> >>>> .../devicetree/bindings/net/realtek.txt | 9 +++++++++
> >>>> include/dt-bindings/net/realtek.h | 17 +++++++++++++++++
> >>>> 2 files changed, 26 insertions(+)
> >>>> create mode 100644 include/dt-bindings/net/realtek.h
> >>>>
> >>>> diff --git a/Documentation/devicetree/bindings/net/realtek.txt b/Documentation/devicetree/bindings/net/realtek.txt
> >>>> index 71d386c78269..40b0d6f9ee21 100644
> >>>> --- a/Documentation/devicetree/bindings/net/realtek.txt
> >>>> +++ b/Documentation/devicetree/bindings/net/realtek.txt
> >>>> @@ -9,6 +9,12 @@ Optional properties:
> >>>>
> >>>> SSC is only available on some Realtek PHYs (e.g. RTL8211E).
> >>>>
> >>>> +- realtek,led-modes: LED mode configuration.
> >>>> +
> >>>> + A 0..3 element vector, with each element configuring the operating
> >>>> + mode of an LED. Omitted LEDs are turned off. Allowed values are
> >>>> + defined in "include/dt-bindings/net/realtek.h".
> >>>
> >>> This should probably be made more general and we should define LED modes
> >>> that makes sense regardless of the PHY device, introduce a set of
> >>> generic functions for validating and then add new function pointer for
> >>> setting the LED configuration to the PHY driver. This would allow to be
> >>> more future proof where each PHY driver could expose standard LEDs class
> >>> devices to user-space, and it would also allow facilities like: ethtool
> >>> -p to plug into that.
> >>>
> >>> Right now, each driver invents its own way of configuring LEDs, that
> >>> does not scale, and there is not really a good reason for that other
> >>> than reviewing drivers in isolation and therefore making it harder to
> >>> extract the commonality. Yes, I realize that since you are the latest
> >>> person submitting something in that area, you are being selected :)
> >
> > I agree.
> >
> >> I see the merit of your proposal to come up with a generic mechanism
> >> to configure Ethernet LEDs, however I can't justify spending much of
> >> my work time on this. If it is deemed useful I'm happy to send another
> >> version of the current patchset that addresses the reviewer's comments,
> >> but if the implementation of a generic LED configuration interface is
> >> a requirement I will have to abandon at least the LED configuration
> >> part of this series.
> >
> > Can you at least define a common binding for this. Maybe that's just
> > removing 'realtek'. While the kernel side can evolve to a common
> > infrastructure, the DT bindings can't.
>
> That would be a great start, and that is actually what I had in mind
> (should have been more specific), I was not going to have you Matthias
> do the grand slam and convert all this LED configuration into the LEDs
> class etc. that would not be fair.
>
> It seems to be that we can fairly easily agree on a common binding for
> LED configuration, I would define something along those lines to be
> flexible:
>
> phy-led-configuration = <LED_NUM_MASK LED_CFG_MASK>;
>
> where LED_NUM_MASK is one of:
>
> 0 -> link
> 1 -> activity
> 2 -> speed
I don't understand this proposal completely. Is LED_NUM_MASK actually
a mask/set (potentially containing multiple LEDs) or is it "one of"
the LEDs?
Are you suggesting to assign each LED a specific role (link, activity,
speed)?
Could you maybe post a specific example involving multiple LEDs?
Thanks
Matthias
> that way you can define single/dual/triple LED configurations by
> updating the bitmask.
>
> LED_CFG_MASK is one of:
>
> 0 -> LED_CFG_10
> 1 -> LED_CFG_100
> 2 -> LED_CFG_1000
>
> (let's assume 1Gbps or less for now)
>
> or this can be combined in a single cell with a left shift.
>
> Andrew, Heiner, do you see that approach working correctly and scaling
> appropriately?
^ permalink raw reply
* Re: [PATCH v2 6/7] dt-bindings: net: realtek: Add property to configure LED mode
From: Matthias Kaehlcke @ 2019-07-12 17:20 UTC (permalink / raw)
To: Rob Herring
Cc: Florian Fainelli, David S . Miller, Mark Rutland, Andrew Lunn,
Heiner Kallweit, netdev, devicetree, linux-kernel@vger.kernel.org,
Douglas Anderson
In-Reply-To: <CAL_JsqL_AU+JV0c2mNbXiPh2pvfYbPbLV-2PHHX0hC3vUH4QWg@mail.gmail.com>
On Wed, Jul 10, 2019 at 09:55:12AM -0600, Rob Herring wrote:
> On Wed, Jul 3, 2019 at 5:23 PM Matthias Kaehlcke <mka@chromium.org> wrote:
> >
> > Hi Florian,
> >
> > On Wed, Jul 03, 2019 at 02:37:47PM -0700, Florian Fainelli wrote:
> > > On 7/3/19 12:37 PM, Matthias Kaehlcke wrote:
> > > > The LED behavior of some Realtek PHYs is configurable. Add the
> > > > property 'realtek,led-modes' to specify the configuration of the
> > > > LEDs.
> > > >
> > > > Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
> > > > ---
> > > > Changes in v2:
> > > > - patch added to the series
> > > > ---
> > > > .../devicetree/bindings/net/realtek.txt | 9 +++++++++
> > > > include/dt-bindings/net/realtek.h | 17 +++++++++++++++++
> > > > 2 files changed, 26 insertions(+)
> > > > create mode 100644 include/dt-bindings/net/realtek.h
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/net/realtek.txt b/Documentation/devicetree/bindings/net/realtek.txt
> > > > index 71d386c78269..40b0d6f9ee21 100644
> > > > --- a/Documentation/devicetree/bindings/net/realtek.txt
> > > > +++ b/Documentation/devicetree/bindings/net/realtek.txt
> > > > @@ -9,6 +9,12 @@ Optional properties:
> > > >
> > > > SSC is only available on some Realtek PHYs (e.g. RTL8211E).
> > > >
> > > > +- realtek,led-modes: LED mode configuration.
> > > > +
> > > > + A 0..3 element vector, with each element configuring the operating
> > > > + mode of an LED. Omitted LEDs are turned off. Allowed values are
> > > > + defined in "include/dt-bindings/net/realtek.h".
> > >
> > > This should probably be made more general and we should define LED modes
> > > that makes sense regardless of the PHY device, introduce a set of
> > > generic functions for validating and then add new function pointer for
> > > setting the LED configuration to the PHY driver. This would allow to be
> > > more future proof where each PHY driver could expose standard LEDs class
> > > devices to user-space, and it would also allow facilities like: ethtool
> > > -p to plug into that.
> > >
> > > Right now, each driver invents its own way of configuring LEDs, that
> > > does not scale, and there is not really a good reason for that other
> > > than reviewing drivers in isolation and therefore making it harder to
> > > extract the commonality. Yes, I realize that since you are the latest
> > > person submitting something in that area, you are being selected :)
>
> I agree.
>
> > I see the merit of your proposal to come up with a generic mechanism
> > to configure Ethernet LEDs, however I can't justify spending much of
> > my work time on this. If it is deemed useful I'm happy to send another
> > version of the current patchset that addresses the reviewer's comments,
> > but if the implementation of a generic LED configuration interface is
> > a requirement I will have to abandon at least the LED configuration
> > part of this series.
>
> Can you at least define a common binding for this. Maybe that's just
> removing 'realtek'. While the kernel side can evolve to a common
> infrastructure, the DT bindings can't.
Defining a common binding sounds good to me, I will follow up on
Florian's reply to this.
^ permalink raw reply
* Re: [PATCH v8 0/7] Unify CPU topology across ARM & RISC-V
From: Paul Walmsley @ 2019-07-12 17:16 UTC (permalink / raw)
To: Atish Patra
Cc: linux-kernel, Jeremy Linton, Albert Ou, Anup Patel,
Catalin Marinas, David S. Miller, devicetree, Greg Kroah-Hartman,
Ingo Molnar, Johan Hovold, Linus Walleij, linux-riscv,
Mark Rutland, Mauro Carvalho Chehab, Morten Rasmussen,
Otto Sabart, Palmer Dabbelt, Peter Zijlstra (Intel),
Rafael J. Wysocki, Rob
In-Reply-To: <20190627195302.28300-1-atish.patra@wdc.com>
Folks,
On Thu, 27 Jun 2019, Atish Patra wrote:
> The cpu-map DT entry in ARM can describe the CPU topology in much better
> way compared to other existing approaches. RISC-V can easily adopt this
> binding to represent its own CPU topology. Thus, both cpu-map DT
> binding and topology parsing code can be moved to a common location so
> that RISC-V or any other architecture can leverage that.
>
> The relevant discussion regarding unifying cpu topology can be found in
> [1].
>
> arch_topology seems to be a perfect place to move the common code. I
> have not introduced any significant functional changes in the moved code.
> The only downside in this approach is that the capacity code will be
> executed for RISC-V as well. But, it will exit immediately after not
> able to find the appropriate DT node. If the overhead is considered too
> much, we can always compile out capacity related functions under a
> different config for the architectures that do not support them.
>
> There was an opportunity to unify topology data structure for ARM32 done
> by patch 3/4. But, I refrained from making any other changes as I am not
> very well versed with original intention for some functions that
> are present in arch_topology.c. I hope this patch series can be served
> as a baseline for such changes in the future.
>
> The patches have been tested for RISC-V, ARM64, ARM32 & compile tested for
> x86.
Since these patches touch files across several different architectures,
and thus really should sit in -next for a while; and because it's late in
the merge window, I'm planning to postpone sending these patches upstream
until after v5.3-rc1 is released.
Once v5.3-rc1 is released, let's plan to get these patches rebased and
reposted and into linux-next as soon as possible.
Sorry for the delay here,
- Paul
^ permalink raw reply
* Re: [PATCHv8 1/5] arm64: dts: qcom: sdm845: Add Coresight support
From: saiprakash.ranjan @ 2019-07-12 16:49 UTC (permalink / raw)
To: Suzuki K Poulose
Cc: gregkh, mathieu.poirier, leo.yan, alexander.shishkin, mike.leach,
robh+dt, bjorn.andersson, devicetree, david.brown, mark.rutland,
rnayak, vivek.gautam, sibis, linux-arm-kernel, linux-kernel,
linux-arm-msm, marc.w.gonzalez, devicetree-owner
In-Reply-To: <06c1a087-53f7-4841-1ae3-07ccbed22a72@arm.com>
Hi Suzuki,
On 2019-07-12 22:14, Suzuki K Poulose wrote:
> Hi Sai,
>
> On 12/07/2019 15:16, Sai Prakash Ranjan wrote:
>> Add coresight components found on Qualcomm SDM845 SoC.
>
>>
>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> ---
>> arch/arm64/boot/dts/qcom/sdm845.dtsi | 451
>> +++++++++++++++++++++++++++
>> 1 file changed, 451 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> index 4babff5f19b5..5d7e3f8e0f91 100644
>> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> @@ -1815,6 +1815,457 @@
>> clock-names = "xo";
>> };
>> + stm@6002000 {
>> + compatible = "arm,coresight-stm", "arm,primecell";
>> + reg = <0 0x06002000 0 0x1000>,
>> + <0 0x16280000 0 0x180000>;
>> + reg-names = "stm-base", "stm-stimulus-base";
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>
>
> Which tree is this based on ? I can't see aoss_qmp anywhere under
> dts/qcom
> on 5.2-rc7.
>
It's based on linux-next.
Thanks,
Sai
^ permalink raw reply
* Re: [PATCHv8 1/5] arm64: dts: qcom: sdm845: Add Coresight support
From: Suzuki K Poulose @ 2019-07-12 16:44 UTC (permalink / raw)
To: saiprakash.ranjan, gregkh, mathieu.poirier, leo.yan,
alexander.shishkin, mike.leach, robh+dt, bjorn.andersson,
devicetree, david.brown, mark.rutland
Cc: rnayak, vivek.gautam, sibis, linux-arm-kernel, linux-kernel,
linux-arm-msm, marc.w.gonzalez
In-Reply-To: <52550ed9bbc10dca860eb1700aef5c97f644327b.1562940244.git.saiprakash.ranjan@codeaurora.org>
Hi Sai,
On 12/07/2019 15:16, Sai Prakash Ranjan wrote:
> Add coresight components found on Qualcomm SDM845 SoC.
>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 451 +++++++++++++++++++++++++++
> 1 file changed, 451 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 4babff5f19b5..5d7e3f8e0f91 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -1815,6 +1815,457 @@
> clock-names = "xo";
> };
>
> + stm@6002000 {
> + compatible = "arm,coresight-stm", "arm,primecell";
> + reg = <0 0x06002000 0 0x1000>,
> + <0 0x16280000 0 0x180000>;
> + reg-names = "stm-base", "stm-stimulus-base";
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
Which tree is this based on ? I can't see aoss_qmp anywhere under dts/qcom
on 5.2-rc7.
Cheers
Suzuki
^ permalink raw reply
* Re: [PATCH V13 12/12] PCI: tegra: Add Tegra194 PCIe support
From: Lorenzo Pieralisi @ 2019-07-12 16:07 UTC (permalink / raw)
To: Vidya Sagar
Cc: bhelgaas, robh+dt, mark.rutland, thierry.reding, jonathanh,
kishon, catalin.marinas, will.deacon, jingoohan1,
gustavo.pimentel, digetx, mperttunen, linux-pci, devicetree,
linux-tegra, linux-kernel, linux-arm-kernel, kthota, mmaddireddy,
sagar.tv
In-Reply-To: <986d0b1a-666a-7b05-a9f3-e761518bdc92@nvidia.com>
On Fri, Jul 12, 2019 at 09:02:49PM +0530, Vidya Sagar wrote:
[...]
> > > +static irqreturn_t tegra_pcie_irq_handler(int irq, void *arg)
> > > +{
> > > + struct tegra_pcie_dw *pcie = arg;
> > > +
> > > + if (pcie->mode == DW_PCIE_RC_TYPE)
> > > + return tegra_pcie_rp_irq_handler(pcie);
> >
> > What's the point of registering the handler if mode != DW_PCIE_RC_TYPE ?
> Currently this driver supports only root port mode but we have a plan
> to add support for endpoint mode (as Tegra194 as dual mode
> controllers) also in future and when that happens, we'll have a
> corresponding tegra_pcie_ep_irq_handler() to take care of ep specific
> interrupts.
Sure, that's why you should add tegra_pcie_dw->mode when it is needed,
not in this patch.
[...]
> > > +static int tegra_pcie_dw_host_init(struct pcie_port *pp)
> > > +{
> > > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
> > > + u32 val, tmp, offset, speed;
> > > + unsigned int count;
> > > + u16 val_w;
> > > +
> > > +core_init:
> >
> > I think it would be cleaner to include all registers programming
> > within a function and we remove this label (and goto) below.
> Some background: As per spec r4.0 v1.0, downstream ports that support
> 16.0 GT/s must support Scaled Flow Control (sec 3.4.2) and Tegra194's
> downstream ports being 16.0 GT/s capable, enable scaled flow control
> by having Data Link Feature (sec 7.7.4) enabled by default. There is
> one endpoint (ASMedia USB3.0 controller) that doesn't link up with
> root port because of this (i.e. DLF being enabled). The way we are
> detecting this situation is to check for partial linkup i.e. one of
> application logic registers (i.e. from "appl" region) says link is up
> but the same is not reflected in configuration space of root port.
> Recommendation from our hardware team in this situation is to disable
> DLF in root port and try link up with endpoint again. To achieve
> this, we put the core through reset cycle, disable DLF and proceed
> with configuring all other registers and check for link up.
>
> Initially in Patch-1, I didn't have goto statement but a recursion
> with depth-1 (as the above situation occurs only once). It was
> reviewed @ http://patchwork.ozlabs.org/patch/1065707/ and Thierry said
> it would be simpler to use a goto instead of calling the same function
> again. So, I modified the code accordingly. Please do let me know if
> you strongly feel we should call tegra_pcie_dw_host_init() instead of
> goto here. I'll change it.
I did not say we should call tegra_pcie_dw_host_init(), sorry for
not being clear. What I asked is factoring out registers programming
in a function and call it where core_init: label is and call it
again if DLF enablement causes link up to fail.
[...]
> > > +static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
> > > + bool enable)
> > > +{
> > > + struct mrq_uphy_response resp;
> > > + struct tegra_bpmp_message msg;
> > > + struct mrq_uphy_request req;
> > > + int err;
> > > +
> > > + if (pcie->cid == 5)
> > > + return 0;
> >
> > What's wrong with cid == 5 ? Explain please.
> Controller with ID=5 doesn't need any programming to enable it which is
> done here through calling firmware API.
>
> >
> > > + memset(&req, 0, sizeof(req));
> > > + memset(&resp, 0, sizeof(resp));
> > > +
> > > + req.cmd = CMD_UPHY_PCIE_CONTROLLER_STATE;
> > > + req.controller_state.pcie_controller = pcie->cid;
> > > + req.controller_state.enable = enable;
> > > +
> > > + memset(&msg, 0, sizeof(msg));
> > > + msg.mrq = MRQ_UPHY;
> > > + msg.tx.data = &req;
> > > + msg.tx.size = sizeof(req);
> > > + msg.rx.data = &resp;
> > > + msg.rx.size = sizeof(resp);
> > > +
> > > + if (irqs_disabled())
> >
> > Can you explain to me what this check is meant to achieve please ?
> Firmware interface provides different APIs to be called when there are
> no interrupts enabled in the system (noirq context) and otherwise
> hence checking that situation here and calling appropriate API.
That's what I am questioning. Being called from {suspend/resume}_noirq()
callbacks (if that's the code path this check caters for) does not mean
irqs_disabled() == true.
Actually, if tegra_bpmp_transfer() requires IRQs to be enabled you may
even end up in a situation where that blocking call does not wake up
because the IRQ in question was disabled in the NOIRQ suspend/resume
phase.
[...]
> > > +static int tegra_pcie_dw_probe(struct platform_device *pdev)
> > > +{
> > > + const struct tegra_pcie_soc *data;
> > > + struct device *dev = &pdev->dev;
> > > + struct resource *atu_dma_res;
> > > + struct tegra_pcie_dw *pcie;
> > > + struct resource *dbi_res;
> > > + struct pcie_port *pp;
> > > + struct dw_pcie *pci;
> > > + struct phy **phys;
> > > + char *name;
> > > + int ret;
> > > + u32 i;
> > > +
> > > + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
> > > + if (!pcie)
> > > + return -ENOMEM;
> > > +
> > > + pci = &pcie->pci;
> > > + pci->dev = &pdev->dev;
> > > + pci->ops = &tegra_dw_pcie_ops;
> > > + pp = &pci->pp;
> > > + pcie->dev = &pdev->dev;
> > > +
> > > + data = (struct tegra_pcie_soc *)of_device_get_match_data(dev);
> > > + if (!data)
> > > + return -EINVAL;
> > > + pcie->mode = (enum dw_pcie_device_mode)data->mode;
> > > +
> > > + ret = tegra_pcie_dw_parse_dt(pcie);
> > > + if (ret < 0) {
> > > + dev_err(dev, "Failed to parse device tree: %d\n", ret);
> > > + return ret;
> > > + }
> > > +
> > > + pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl");
> > > + if (IS_ERR(pcie->pex_ctl_supply)) {
> > > + dev_err(dev, "Failed to get regulator: %ld\n",
> > > + PTR_ERR(pcie->pex_ctl_supply));
> > > + return PTR_ERR(pcie->pex_ctl_supply);
> > > + }
> > > +
> > > + pcie->core_clk = devm_clk_get(dev, "core");
> > > + if (IS_ERR(pcie->core_clk)) {
> > > + dev_err(dev, "Failed to get core clock: %ld\n",
> > > + PTR_ERR(pcie->core_clk));
> > > + return PTR_ERR(pcie->core_clk);
> > > + }
> > > +
> > > + pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > > + "appl");
> > > + if (!pcie->appl_res) {
> > > + dev_err(dev, "Failed to find \"appl\" region\n");
> > > + return PTR_ERR(pcie->appl_res);
> > > + }
> > > + pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res);
> > > + if (IS_ERR(pcie->appl_base))
> > > + return PTR_ERR(pcie->appl_base);
> > > +
> > > + pcie->core_apb_rst = devm_reset_control_get(dev, "apb");
> > > + if (IS_ERR(pcie->core_apb_rst)) {
> > > + dev_err(dev, "Failed to get APB reset: %ld\n",
> > > + PTR_ERR(pcie->core_apb_rst));
> > > + return PTR_ERR(pcie->core_apb_rst);
> > > + }
> > > +
> > > + phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL);
> > > + if (!phys)
> > > + return PTR_ERR(phys);
> > > +
> > > + for (i = 0; i < pcie->phy_count; i++) {
> > > + name = kasprintf(GFP_KERNEL, "p2u-%u", i);
> > > + if (!name) {
> > > + dev_err(dev, "Failed to create P2U string\n");
> > > + return -ENOMEM;
> > > + }
> > > + phys[i] = devm_phy_get(dev, name);
> > > + kfree(name);
> > > + if (IS_ERR(phys[i])) {
> > > + ret = PTR_ERR(phys[i]);
> > > + dev_err(dev, "Failed to get PHY: %d\n", ret);
> > > + return ret;
> > > + }
> > > + }
> > > +
> > > + pcie->phys = phys;
> > > +
> > > + dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
> > > + if (!dbi_res) {
> > > + dev_err(dev, "Failed to find \"dbi\" region\n");
> > > + return PTR_ERR(dbi_res);
> > > + }
> > > + pcie->dbi_res = dbi_res;
> > > +
> > > + pci->dbi_base = devm_ioremap_resource(dev, dbi_res);
> > > + if (IS_ERR(pci->dbi_base))
> > > + return PTR_ERR(pci->dbi_base);
> > > +
> > > + /* Tegra HW locates DBI2 at a fixed offset from DBI */
> > > + pci->dbi_base2 = pci->dbi_base + 0x1000;
> > > +
> > > + atu_dma_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > > + "atu_dma");
> > > + if (!atu_dma_res) {
> > > + dev_err(dev, "Failed to find \"atu_dma\" region\n");
> > > + return PTR_ERR(atu_dma_res);
> > > + }
> > > + pcie->atu_dma_res = atu_dma_res;
> > > + pci->atu_base = devm_ioremap_resource(dev, atu_dma_res);
> > > + if (IS_ERR(pci->atu_base))
> > > + return PTR_ERR(pci->atu_base);
> > > +
> > > + pcie->core_rst = devm_reset_control_get(dev, "core");
> > > + if (IS_ERR(pcie->core_rst)) {
> > > + dev_err(dev, "Failed to get core reset: %ld\n",
> > > + PTR_ERR(pcie->core_rst));
> > > + return PTR_ERR(pcie->core_rst);
> > > + }
> > > +
> > > + pp->irq = platform_get_irq_byname(pdev, "intr");
> > > + if (!pp->irq) {
> > > + dev_err(dev, "Failed to get \"intr\" interrupt\n");
> > > + return -ENODEV;
> > > + }
> > > +
> > > + ret = devm_request_irq(dev, pp->irq, tegra_pcie_irq_handler,
> > > + IRQF_SHARED, "tegra-pcie-intr", pcie);
> > > + if (ret) {
> > > + dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, ret);
> > > + return ret;
> > > + }
> > > +
> > > + pcie->bpmp = tegra_bpmp_get(dev);
> > > + if (IS_ERR(pcie->bpmp))
> > > + return PTR_ERR(pcie->bpmp);
> > > +
> > > + platform_set_drvdata(pdev, pcie);
> > > +
> > > + if (pcie->mode == DW_PCIE_RC_TYPE) {
> > > + ret = tegra_pcie_config_rp(pcie);
> > > + if (ret && ret != -ENOMEDIUM)
> > > + goto fail;
> > > + else
> > > + return 0;
> >
> > So if the link is not up we still go ahead and make probe
> > succeed. What for ?
> We may need root port to be available to support hot-plugging of
> endpoint devices, so, we don't fail the probe.
We need it or we don't. If you do support hotplugging of endpoint
devices point me at the code, otherwise link up failure means
failure to probe.
> > > + }
> > > +
> > > +fail:
> > > + tegra_bpmp_put(pcie->bpmp);
> > > + return ret;
> > > +}
> > > +
> > > +static int tegra_pcie_dw_remove(struct platform_device *pdev)
> > > +{
> > > + struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
> > > +
> > > + if (pcie->mode != DW_PCIE_RC_TYPE)
> > > + return 0;
> > > +
> > > + if (!pcie->link_state)
> > > + return 0;
> > > +
> > > + debugfs_remove_recursive(pcie->debugfs);
> > > + tegra_pcie_deinit_controller(pcie);
> > > + pm_runtime_put_sync(pcie->dev);
> > > + pm_runtime_disable(pcie->dev);
> > > + tegra_bpmp_put(pcie->bpmp);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int tegra_pcie_dw_suspend_late(struct device *dev)
> > > +{
> > > + struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
> > > + u32 val;
> > > +
> > > + if (!pcie->link_state)
> > > + return 0;
> > > +
> > > + /* Enable HW_HOT_RST mode */
> > > + val = appl_readl(pcie, APPL_CTRL);
> > > + val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
> > > + APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
> > > + val |= APPL_CTRL_HW_HOT_RST_EN;
> > > + appl_writel(pcie, val, APPL_CTRL);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int tegra_pcie_dw_suspend_noirq(struct device *dev)
> > > +{
> > > + struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
> > > +
> > > + if (!pcie->link_state)
> > > + return 0;
> > > +
> > > + /* Save MSI interrupt vector */
> > > + pcie->msi_ctrl_int = dw_pcie_readl_dbi(&pcie->pci,
> > > + PORT_LOGIC_MSI_CTRL_INT_0_EN);
> > > + tegra_pcie_downstream_dev_to_D0(pcie);
> >
> > I think this requires some comments. AFAIU this is allowed by
> > the PCI specs (PCI Express Base 4.0 r1.0 September 29-2017,
> > 5.2 Link State Power Management). However, I would like to
> > understand how this plays with the D state the devices are left
> > in upon system suspend.
> >
> > "As the following example illustrates, it is also possible to remove
> > power without first placing all Functions into D3Hot".
> >
> > I assume that's what happens on this platform to allow L2 entry but
> > again, this needs clarification.
> Yes. It is true that in the case of Tegra194, it brings devices back
> to D0 before putting link to L2 state.
Comment it, extensively, so that anyone reading the code understands
why it is done so and what happens to devices then.
Lorenzo
^ permalink raw reply
* Re: [PATCH V13 12/12] PCI: tegra: Add Tegra194 PCIe support
From: Vidya Sagar @ 2019-07-12 15:32 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: bhelgaas, robh+dt, mark.rutland, thierry.reding, jonathanh,
kishon, catalin.marinas, will.deacon, jingoohan1,
gustavo.pimentel, digetx, mperttunen, linux-pci, devicetree,
linux-tegra, linux-kernel, linux-arm-kernel, kthota, mmaddireddy,
sagar.tv
In-Reply-To: <20190711125433.GB26088@e121166-lin.cambridge.arm.com>
On 7/11/2019 6:24 PM, Lorenzo Pieralisi wrote:
> On Wed, Jul 10, 2019 at 11:52:12AM +0530, Vidya Sagar wrote:
>
> [...]
>
>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>> new file mode 100644
>> index 000000000000..189779edd976
>> --- /dev/null
>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>> @@ -0,0 +1,1632 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * PCIe host controller driver for Tegra194 SoC
>> + *
>> + * Copyright (C) 2019 NVIDIA Corporation.
>> + *
>> + * Author: Vidya Sagar <vidyas@nvidia.com>
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/debugfs.h>
>> +#include <linux/delay.h>
>> +#include <linux/gpio.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/iopoll.h>
>> +#include <linux/kernel.h>
>> +#include <linux/kfifo.h>
>> +#include <linux/kthread.h>
>
> What do you need these two headers for ?
These were added for a different reason. They are not required
and I'll remove them.
>
> [...]
>
>> +struct tegra_pcie_dw {
>> + struct device *dev;
>> + struct resource *appl_res;
>> + struct resource *dbi_res;
>> + struct resource *atu_dma_res;
>> + void __iomem *appl_base;
>> + struct clk *core_clk;
>> + struct reset_control *core_apb_rst;
>> + struct reset_control *core_rst;
>> + struct dw_pcie pci;
>> + enum dw_pcie_device_mode mode;
>> + struct tegra_bpmp *bpmp;
>> +
>> + bool supports_clkreq;
>> + bool enable_cdm_check;
>> + u8 init_link_width;
>> + bool link_state;
>> + u32 msi_ctrl_int;
>> + u32 num_lanes;
>> + u32 max_speed;
>> + u32 cid;
>> + bool update_fc_fixup;
>> + u32 cfg_link_cap_l1sub;
>> + u32 pcie_cap_base;
>> + u32 aspm_cmrt;
>> + u32 aspm_pwr_on_t;
>> + u32 aspm_l0s_enter_lat;o
>
> Nit: You should try to group variables according to their usage,
> it would make sense to group booleans together.
Ok.
>
>> + struct regulator *pex_ctl_supply;
>> +
>> + unsigned int phy_count;
>> + struct phy **phys;
>> +
>> + struct dentry *debugfs;
>> +};
>> +
>> +static inline struct tegra_pcie_dw *to_tegra_pcie(struct dw_pcie *pci)
>> +{
>> + return container_of(pci, struct tegra_pcie_dw, pci);
>> +}
>> +
>> +static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value,
>> + const u32 reg)
>> +{
>> + writel_relaxed(value, pcie->appl_base + reg);
>> +}
>> +
>> +static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg)
>> +{
>> + return readl_relaxed(pcie->appl_base + reg);
>> +}
>> +
>> +struct tegra_pcie_soc {
>> + enum dw_pcie_device_mode mode;
>> +};
>> +
>> +static void apply_bad_link_workaround(struct pcie_port *pp)
>> +{
>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
>> + u32 current_link_width;
>> + u16 val;
>> +
>> + /*
>> + * NOTE:- Since this scenario is uncommon and link as such is not
>> + * stable anyway, not waiting to confirm if link is really
>> + * transitioning to Gen-2 speed
>> + */
>> + val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
>> + if (val & PCI_EXP_LNKSTA_LBMS) {
>> + current_link_width = (val & PCI_EXP_LNKSTA_NLW) >>
>> + PCI_EXP_LNKSTA_NLW_SHIFT;
>> + if (pcie->init_link_width > current_link_width) {
>> + dev_warn(pci->dev, "PCIe link is bad, width reduced\n");
>> + val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
>> + PCI_EXP_LNKCTL2);
>> + val &= ~PCI_EXP_LNKCTL2_TLS;
>> + val |= PCI_EXP_LNKCTL2_TLS_2_5GT;
>> + dw_pcie_writew_dbi(pci, pcie->pcie_cap_base +
>> + PCI_EXP_LNKCTL2, val);
>> +
>> + val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
>> + PCI_EXP_LNKCTL);
>> + val |= PCI_EXP_LNKCTL_RL;
>> + dw_pcie_writew_dbi(pci, pcie->pcie_cap_base +
>> + PCI_EXP_LNKCTL, val);
>> + }
>> + }
>> +}
>> +
>> +static irqreturn_t tegra_pcie_rp_irq_handler(struct tegra_pcie_dw *pcie)
>> +{
>> + struct dw_pcie *pci = &pcie->pci;
>> + struct pcie_port *pp = &pci->pp;
>> + u32 val, tmp;
>> + u16 val_w;
>> +
>> + val = appl_readl(pcie, APPL_INTR_STATUS_L0);
>> + if (val & APPL_INTR_STATUS_L0_LINK_STATE_INT) {
>> + val = appl_readl(pcie, APPL_INTR_STATUS_L1_0_0);
>> + if (val & APPL_INTR_STATUS_L1_0_0_LINK_REQ_RST_NOT_CHGED) {
>> + appl_writel(pcie, val, APPL_INTR_STATUS_L1_0_0);
>> +
>> + /* SBR & Surprise Link Down WAR */
>> + val = appl_readl(pcie, APPL_CAR_RESET_OVRD);
>> + val &= ~APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N;
>> + appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
>> + udelay(1);
>> + val = appl_readl(pcie, APPL_CAR_RESET_OVRD);
>> + val |= APPL_CAR_RESET_OVRD_CYA_OVERRIDE_CORE_RST_N;
>> + appl_writel(pcie, val, APPL_CAR_RESET_OVRD);
>> +
>> + val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL);
>> + val |= PORT_LOGIC_GEN2_CTRL_DIRECT_SPEED_CHANGE;
>> + dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val);
>> + }
>> + }
>> +
>> + if (val & APPL_INTR_STATUS_L0_INT_INT) {
>> + val = appl_readl(pcie, APPL_INTR_STATUS_L1_8_0);
>> + if (val & APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS) {
>> + appl_writel(pcie,
>> + APPL_INTR_STATUS_L1_8_0_AUTO_BW_INT_STS,
>> + APPL_INTR_STATUS_L1_8_0);
>> + apply_bad_link_workaround(pp);
>> + }
>> + if (val & APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS) {
>> + appl_writel(pcie,
>> + APPL_INTR_STATUS_L1_8_0_BW_MGT_INT_STS,
>> + APPL_INTR_STATUS_L1_8_0);
>> +
>> + val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
>> + PCI_EXP_LNKSTA);
>> + dev_dbg(pci->dev, "Link Speed : Gen-%u\n", val_w &
>> + PCI_EXP_LNKSTA_CLS);
>> + }
>> + }
>> +
>> + val = appl_readl(pcie, APPL_INTR_STATUS_L0);
>> + if (val & APPL_INTR_STATUS_L0_CDM_REG_CHK_INT) {
>> + val = appl_readl(pcie, APPL_INTR_STATUS_L1_18);
>> + tmp = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
>> + if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMPLT) {
>> + dev_info(pci->dev, "CDM check complete\n");
>> + tmp |= PCIE_PL_CHK_REG_CHK_REG_COMPLETE;
>> + }
>> + if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_CMP_ERR) {
>> + dev_err(pci->dev, "CDM comparison mismatch\n");
>> + tmp |= PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR;
>> + }
>> + if (val & APPL_INTR_STATUS_L1_18_CDM_REG_CHK_LOGIC_ERR) {
>> + dev_err(pci->dev, "CDM Logic error\n");
>> + tmp |= PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERROR;
>> + }
>> + dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, tmp);
>> + tmp = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_ERR_ADDR);
>> + dev_err(pci->dev, "CDM Error Address Offset = 0x%08X\n", tmp);
>> + }
>> +
>> + return IRQ_HANDLED;
>> +}
>> +
>> +static irqreturn_t tegra_pcie_irq_handler(int irq, void *arg)
>> +{
>> + struct tegra_pcie_dw *pcie = arg;
>> +
>> + if (pcie->mode == DW_PCIE_RC_TYPE)
>> + return tegra_pcie_rp_irq_handler(pcie);
>
> What's the point of registering the handler if mode != DW_PCIE_RC_TYPE ?
Currently this driver supports only root port mode but we have a plan to add
support for endpoint mode (as Tegra194 as dual mode controllers) also in future
and when that happens, we'll have a corresponding tegra_pcie_ep_irq_handler()
to take care of ep specific interrupts.
>
>> + return IRQ_NONE;
>> +}
>> +
>> +static int tegra_pcie_dw_rd_own_conf(struct pcie_port *pp, int where, int size,
>> + u32 *val)
>> +{
>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> +
>> + /*
>> + * This is an endpoint mode specific register happen to appear even
>> + * when controller is operating in root port mode and system hangs
>> + * when it is accessed with link being in ASPM-L1 state.
>> + * So skip accessing it altogether
>> + */
>> + if (where == PORT_LOGIC_MSIX_DOORBELL) {
>> + *val = 0x00000000;
>> + return PCIBIOS_SUCCESSFUL;
>> + }
>> +
>> + return dw_pcie_read(pci->dbi_base + where, size, val);
>> +}
>> +
>> +static int tegra_pcie_dw_wr_own_conf(struct pcie_port *pp, int where, int size,
>> + u32 val)
>> +{
>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> +
>> + /*
>> + * This is an endpoint mode specific register happen to appear even
>> + * when controller is operating in root port mode and system hangs
>> + * when it is accessed with link being in ASPM-L1 state.
>> + * So skip accessing it altogether
>> + */
>> + if (where == PORT_LOGIC_MSIX_DOORBELL)
>> + return PCIBIOS_SUCCESSFUL;
>> +
>> + return dw_pcie_write(pci->dbi_base + where, size, val);
>> +}
>> +
>> +#if defined(CONFIG_PCIEASPM)
>> +static void disable_aspm_l11(struct tegra_pcie_dw *pcie)
>> +{
>> + u32 val;
>> +
>> + val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
>> + val &= ~PCI_L1SS_CAP_ASPM_L1_1;
>> + dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
>> +}
>> +
>> +static void disable_aspm_l12(struct tegra_pcie_dw *pcie)
>> +{
>> + u32 val;
>> +
>> + val = dw_pcie_readl_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub);
>> + val &= ~PCI_L1SS_CAP_ASPM_L1_2;
>> + dw_pcie_writel_dbi(&pcie->pci, pcie->cfg_link_cap_l1sub, val);
>> +}
>> +
>> +static inline u32 event_counter_prog(struct tegra_pcie_dw *pcie, u32 event)
>> +{
>> + u32 val;
>> +
>> + val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid]);
>> + val &= ~(EVENT_COUNTER_EVENT_SEL_MASK << EVENT_COUNTER_EVENT_SEL_SHIFT);
>> + val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
>> + val |= event << EVENT_COUNTER_EVENT_SEL_SHIFT;
>> + val |= EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
>> + dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val);
>> + val = dw_pcie_readl_dbi(&pcie->pci, event_cntr_data_offset[pcie->cid]);
>> + return val;
>> +}
>> +
>> +static int aspm_state_cnt(struct seq_file *s, void *data)
>> +{
>> + struct tegra_pcie_dw *pcie = (struct tegra_pcie_dw *)
>> + dev_get_drvdata(s->private);
>> + u32 val;
>> +
>> + seq_printf(s, "Tx L0s entry count : %u\n",
>> + event_counter_prog(pcie, EVENT_COUNTER_EVENT_Tx_L0S));
>> +
>> + seq_printf(s, "Rx L0s entry count : %u\n",
>> + event_counter_prog(pcie, EVENT_COUNTER_EVENT_Rx_L0S));
>> +
>> + seq_printf(s, "Link L1 entry count : %u\n",
>> + event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1));
>> +
>> + seq_printf(s, "Link L1.1 entry count : %u\n",
>> + event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_1));
>> +
>> + seq_printf(s, "Link L1.2 entry count : %u\n",
>> + event_counter_prog(pcie, EVENT_COUNTER_EVENT_L1_2));
>> +
>> + /* Clear all counters */
>> + dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid],
>> + EVENT_COUNTER_ALL_CLEAR);
>> +
>> + /* Re-enable counting */
>> + val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
>> + val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
>> + dw_pcie_writel_dbi(&pcie->pci, event_cntr_ctrl_offset[pcie->cid], val);
>> +
>> + return 0;
>> +}
>> +#endif
>> +
>> +static int init_debugfs(struct tegra_pcie_dw *pcie)
>> +{
>> +#if defined(CONFIG_PCIEASPM)
>> + struct dentry *d;
>> +
>> + d = debugfs_create_devm_seqfile(pcie->dev, "aspm_state_cnt",
>> + pcie->debugfs, aspm_state_cnt);
>> + if (IS_ERR_OR_NULL(d))
>> + dev_err(pcie->dev,
>> + "Failed to create debugfs file \"aspm_state_cnt\"\n");
>> +#endif
>> + return 0;
>> +}
>> +
>> +static void tegra_pcie_enable_system_interrupts(struct pcie_port *pp)
>> +{
>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
>> + u32 val;
>> + u16 val_w;
>> +
>> + val = appl_readl(pcie, APPL_INTR_EN_L0_0);
>> + val |= APPL_INTR_EN_L0_0_LINK_STATE_INT_EN;
>> + appl_writel(pcie, val, APPL_INTR_EN_L0_0);
>> +
>> + val = appl_readl(pcie, APPL_INTR_EN_L1_0_0);
>> + val |= APPL_INTR_EN_L1_0_0_LINK_REQ_RST_NOT_INT_EN;
>> + appl_writel(pcie, val, APPL_INTR_EN_L1_0_0);
>> +
>> + if (pcie->enable_cdm_check) {
>> + val = appl_readl(pcie, APPL_INTR_EN_L0_0);
>> + val |= APPL_INTR_EN_L0_0_CDM_REG_CHK_INT_EN;
>> + appl_writel(pcie, val, APPL_INTR_EN_L0_0);
>> +
>> + val = appl_readl(pcie, APPL_INTR_EN_L1_18);
>> + val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_CMP_ERR;
>> + val |= APPL_INTR_EN_L1_18_CDM_REG_CHK_LOGIC_ERR;
>> + appl_writel(pcie, val, APPL_INTR_EN_L1_18);
>> + }
>> +
>> + val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +
>> + PCI_EXP_LNKSTA);
>> + pcie->init_link_width = (val_w & PCI_EXP_LNKSTA_NLW) >>
>> + PCI_EXP_LNKSTA_NLW_SHIFT;
>> +
>> + val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +
>> + PCI_EXP_LNKCTL);
>> + val_w |= PCI_EXP_LNKCTL_LBMIE;
>> + dw_pcie_writew_dbi(&pcie->pci, pcie->pcie_cap_base + PCI_EXP_LNKCTL,
>> + val_w);
>> +}
>> +
>> +static void tegra_pcie_enable_legacy_interrupts(struct pcie_port *pp)
>> +{
>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
>> + u32 val;
>> +
>> + /* Enable legacy interrupt generation */
>> + val = appl_readl(pcie, APPL_INTR_EN_L0_0);
>> + val |= APPL_INTR_EN_L0_0_SYS_INTR_EN;
>> + val |= APPL_INTR_EN_L0_0_INT_INT_EN;
>> + appl_writel(pcie, val, APPL_INTR_EN_L0_0);
>> +
>> + val = appl_readl(pcie, APPL_INTR_EN_L1_8_0);
>> + val |= APPL_INTR_EN_L1_8_INTX_EN;
>> + val |= APPL_INTR_EN_L1_8_AUTO_BW_INT_EN;
>> + val |= APPL_INTR_EN_L1_8_BW_MGT_INT_EN;
>> + if (IS_ENABLED(CONFIG_PCIEAER))
>> + val |= APPL_INTR_EN_L1_8_AER_INT_EN;
>> + appl_writel(pcie, val, APPL_INTR_EN_L1_8_0);
>> +}
>> +
>> +static void tegra_pcie_enable_msi_interrupts(struct pcie_port *pp)
>> +{
>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
>> + u32 val;
>> +
>> + dw_pcie_msi_init(pp);
>> +
>> + /* Enable MSI interrupt generation */
>> + val = appl_readl(pcie, APPL_INTR_EN_L0_0);
>> + val |= APPL_INTR_EN_L0_0_SYS_MSI_INTR_EN;
>> + val |= APPL_INTR_EN_L0_0_MSI_RCV_INT_EN;
>> + appl_writel(pcie, val, APPL_INTR_EN_L0_0);
>> +}
>> +
>> +static void tegra_pcie_enable_interrupts(struct pcie_port *pp)
>> +{
>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
>> +
>> + /* Clear interrupt statuses before enabling interrupts */
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L0);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_0_0);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_1);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_2);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_3);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_6);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_7);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_8_0);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_9);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_10);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_11);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_13);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_14);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_15);
>> + appl_writel(pcie, 0xFFFFFFFF, APPL_INTR_STATUS_L1_17);
>> +
>> + tegra_pcie_enable_system_interrupts(pp);
>> + tegra_pcie_enable_legacy_interrupts(pp);
>> + if (IS_ENABLED(CONFIG_PCI_MSI))
>> + tegra_pcie_enable_msi_interrupts(pp);
>> +}
>> +
>> +static void config_gen3_gen4_eq_presets(struct tegra_pcie_dw *pcie)
>> +{
>> + struct dw_pcie *pci = &pcie->pci;
>> + u32 val, offset, i;
>> +
>> + /* Program init preset */
>> + for (i = 0; i < pcie->num_lanes; i++) {
>> + dw_pcie_read(pci->dbi_base + CAP_SPCIE_CAP_OFF
>> + + (i * 2), 2, &val);
>> + val &= ~CAP_SPCIE_CAP_OFF_DSP_TX_PRESET0_MASK;
>> + val |= GEN3_GEN4_EQ_PRESET_INIT;
>> + val &= ~CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_MASK;
>> + val |= (GEN3_GEN4_EQ_PRESET_INIT <<
>> + CAP_SPCIE_CAP_OFF_USP_TX_PRESET0_SHIFT);
>> + dw_pcie_write(pci->dbi_base + CAP_SPCIE_CAP_OFF
>> + + (i * 2), 2, val);
>> +
>> + offset = dw_pcie_find_ext_capability(pci,
>> + PCI_EXT_CAP_ID_PL_16GT) +
>> + PCI_PL_16GT_LE_CTRL;
>> + dw_pcie_read(pci->dbi_base + offset + i, 1, &val);
>> + val &= ~PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK;
>> + val |= GEN3_GEN4_EQ_PRESET_INIT;
>> + val &= ~PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK;
>> + val |= (GEN3_GEN4_EQ_PRESET_INIT <<
>> + PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT);
>> + dw_pcie_write(pci->dbi_base + offset + i, 1, val);
>> + }
>> +
>> + val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
>> + val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
>> + dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
>> +
>> + val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
>> + val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK;
>> + val |= (0x3ff << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT);
>> + val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK;
>> + dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);
>> +
>> + val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
>> + val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
>> + val |= (0x1 << GEN3_RELATED_OFF_RATE_SHADOW_SEL_SHIFT);
>> + dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
>> +
>> + val = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
>> + val &= ~GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK;
>> + val |= (0x360 << GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT);
>> + val &= ~GEN3_EQ_CONTROL_OFF_FB_MODE_MASK;
>> + dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, val);
>> +
>> + val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
>> + val &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
>> + dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
>> +}
>> +
>> +static int tegra_pcie_dw_host_init(struct pcie_port *pp)
>> +{
>> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
>> + u32 val, tmp, offset, speed;
>> + unsigned int count;
>> + u16 val_w;
>> +
>> +core_init:
>
> I think it would be cleaner to include all registers programming
> within a function and we remove this label (and goto) below.
Some background:
As per spec r4.0 v1.0, downstream ports that support 16.0 GT/s must
support Scaled Flow Control (sec 3.4.2) and Tegra194's downstream ports
being 16.0 GT/s capable, enable scaled flow control by having
Data Link Feature (sec 7.7.4) enabled by default. There is one
endpoint (ASMedia USB3.0 controller) that doesn't link up with root port
because of this (i.e. DLF being enabled). The way we are detecting this situation
is to check for partial linkup i.e. one of application logic registers (i.e. from
"appl" region) says link is up but the same is not reflected in configuration space
of root port. Recommendation from our hardware team in this situation is to disable
DLF in root port and try link up with endpoint again. To achieve this, we put the
core through reset cycle, disable DLF and proceed with configuring all other registers
and check for link up.
Initially in Patch-1, I didn't have goto statement but a recursion with depth-1 (as the
above situation occurs only once). It was reviewed @ http://patchwork.ozlabs.org/patch/1065707/
and Thierry said it would be simpler to use a goto instead of calling the same
function again. So, I modified the code accordingly. Please do let me know if you strongly
feel we should call tegra_pcie_dw_host_init() instead of goto here. I'll change it.
>
>> + count = 200;
>
> It would be easier to read if we could inizialize this value closer
> to where it is actually used. Actually explaining why 200 as value
> was chosen would be appreciated.
Ok.
>
>> +#if defined(CONFIG_PCIEASPM)
>> + offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS);
>> + pcie->cfg_link_cap_l1sub = offset + PCI_L1SS_CAP;
>> +#endif
>
> Please try to factor this out within a single #ifdef guard.
Ok.
>
>> + val = dw_pcie_readl_dbi(pci, PCI_IO_BASE);
>> + val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8);
>> + dw_pcie_writel_dbi(pci, PCI_IO_BASE, val);
>> +
>> + val = dw_pcie_readl_dbi(pci, PCI_PREF_MEMORY_BASE);
>> + val |= CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE;
>> + val |= CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE;
>> + dw_pcie_writel_dbi(pci, PCI_PREF_MEMORY_BASE, val);
>> +
>> + dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
>> +
>> + /* Configure FTS */
>> + val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL);
>> + val &= ~(N_FTS_MASK << N_FTS_SHIFT);
>> + val |= N_FTS_VAL << N_FTS_SHIFT;
>> + dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val);
>> +
>> + val = dw_pcie_readl_dbi(pci, PORT_LOGIC_GEN2_CTRL);
>> + val &= ~FTS_MASK;
>> + val |= FTS_VAL;
>> + dw_pcie_writel_dbi(pci, PORT_LOGIC_GEN2_CTRL, val);
>> +
>> + /* Enable as 0xFFFF0001 response for CRS */
>> + val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT);
>> + val &= ~(AMBA_ERROR_RESPONSE_CRS_MASK << AMBA_ERROR_RESPONSE_CRS_SHIFT);
>> + val |= (AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 <<
>> + AMBA_ERROR_RESPONSE_CRS_SHIFT);
>> + dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val);
>> +
>> + /* Configure Max Speed from DT */
>> + if (pcie->max_speed && pcie->max_speed != -EINVAL) {
>> + val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base +
>> + PCI_EXP_LNKCAP);
>> + val &= ~PCI_EXP_LNKCAP_SLS;
>> + val |= pcie->max_speed;
>> + dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP,
>> + val);
>> + }
>> +
>> + /* Configure Max lane width from DT */
>> + val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP);
>> + val &= ~PCI_EXP_LNKCAP_MLW;
>> + val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT);
>> + dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val);
>> +
>> + config_gen3_gen4_eq_presets(pcie);
>> +
>> +#if defined(CONFIG_PCIEASPM)
>> + /* Enable ASPM counters */
>> + val = EVENT_COUNTER_ENABLE_ALL << EVENT_COUNTER_ENABLE_SHIFT;
>> + val |= EVENT_COUNTER_GROUP_5 << EVENT_COUNTER_GROUP_SEL_SHIFT;
>> + dw_pcie_writel_dbi(pci, event_cntr_ctrl_offset[pcie->cid], val);
>> +
>> + /* Program T_cmrt and T_pwr_on values */
>> + val = dw_pcie_readl_dbi(pci, pcie->cfg_link_cap_l1sub);
>> + val &= ~(PCI_L1SS_CAP_CM_RESTORE_TIME | PCI_L1SS_CAP_P_PWR_ON_VALUE);
>> + val |= (pcie->aspm_cmrt << 8);
>> + val |= (pcie->aspm_pwr_on_t << 19);
>> + dw_pcie_writel_dbi(pci, pcie->cfg_link_cap_l1sub, val);
>> +
>> + /* Program L0s and L1 entrance latencies */
>> + val = dw_pcie_readl_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL);
>> + val &= ~L0S_ENTRANCE_LAT_MASK;
>> + val |= (pcie->aspm_l0s_enter_lat << L0S_ENTRANCE_LAT_SHIFT);
>> + val |= ENTER_ASPM;
>> + dw_pcie_writel_dbi(pci, PORT_LOGIC_ACK_F_ASPM_CTRL, val);
>> +#endif
>
> See above.
Ok.
>
>> + val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
>> + val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
>> + dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
>> +
>> + if (pcie->update_fc_fixup) {
>> + val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
>> + val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;
>> + dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val);
>> + }
>> +
>> + dw_pcie_setup_rc(pp);
>> +
>> + clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
>> +
>> + /* Assert RST */
>> + val = appl_readl(pcie, APPL_PINMUX);
>> + val &= ~APPL_PINMUX_PEX_RST;
>> + appl_writel(pcie, val, APPL_PINMUX);
>> +
>> + usleep_range(100, 200);
>> +
>> + /* Enable LTSSM */
>> + val = appl_readl(pcie, APPL_CTRL);
>> + val |= APPL_CTRL_LTSSM_EN;
>> + appl_writel(pcie, val, APPL_CTRL);
>> +
>> + /* De-assert RST */
>> + val = appl_readl(pcie, APPL_PINMUX);
>> + val |= APPL_PINMUX_PEX_RST;
>> + appl_writel(pcie, val, APPL_PINMUX);
>> +
>> + msleep(100);
>> +
>> + val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
>> + while (!(val_w & PCI_EXP_LNKSTA_DLLLA)) {
>> + if (count) {
>> + dev_dbg(pci->dev, "Waiting for link up\n");
>> + usleep_range(1000, 2000);
>> + val_w = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
>> + PCI_EXP_LNKSTA);
>> + count--;
>> + continue;
>> + }
>> +
>> + val = appl_readl(pcie, APPL_DEBUG);
>> + val &= APPL_DEBUG_LTSSM_STATE_MASK;
>> + val >>= APPL_DEBUG_LTSSM_STATE_SHIFT;
>> + tmp = appl_readl(pcie, APPL_LINK_STATUS);
>> + tmp &= APPL_LINK_STATUS_RDLH_LINK_UP;
>> + if (!(val == 0x11 && !tmp)) {
>> + dev_info(pci->dev, "Link is down\n");
>> + return 0;
>> + }
>> +
>> + dev_info(pci->dev, "Link is down in DLL");
>> + dev_info(pci->dev, "Trying again with DLFE disabled\n");
>> + /* Disable LTSSM */
>> + val = appl_readl(pcie, APPL_CTRL);
>> + val &= ~APPL_CTRL_LTSSM_EN;
>> + appl_writel(pcie, val, APPL_CTRL);
>> +
>> + reset_control_assert(pcie->core_rst);
>> + reset_control_deassert(pcie->core_rst);
>> +
>> + offset = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_DLF);
>> + val = dw_pcie_readl_dbi(pci, offset + PCI_DLF_CAP);
>> + val &= ~PCI_DLF_EXCHANGE_ENABLE;
>> + dw_pcie_writel_dbi(pci, offset, val);
>> +
>> + /* Retry now with DLF Exchange disabled */
>> + goto core_init;
>
> This goto upwards honestly is a bit horrible. Use some functions
> to make the code more readable.
Updated my comments above.
>
>> + }
>> + dev_dbg(pci->dev, "Link is up\n");
>> +
>> + speed = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA) &
>> + PCI_EXP_LNKSTA_CLS;
>> + clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]);
>> +
>> + tegra_pcie_enable_interrupts(pp);
>> +
>> + return 0;
>> +}
>> +
>> +static int tegra_pcie_dw_link_up(struct dw_pcie *pci)
>> +{
>> + struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
>> + u32 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);
>> +
>> + return !!(val & PCI_EXP_LNKSTA_DLLLA);
>
> It looks like this can be common code reusable by other DWC drivers ?
>
> Not mandatory, just a hint.
Well, each DesignWare core based implementation has a different way to find out
if the link is up and hence this hook is provided by DWC framework to let host controller
drivers implement their implementation specific link up check. In Tegra194, we are just
relying on spec defined configuration space register for link up.
>
>> +}
>> +
>> +static void tegra_pcie_set_msi_vec_num(struct pcie_port *pp)
>> +{
>> + pp->num_vectors = MAX_MSI_IRQS;
>> +}
>> +
>> +static const struct dw_pcie_ops tegra_dw_pcie_ops = {
>> + .link_up = tegra_pcie_dw_link_up,
>> +};
>> +
>> +static struct dw_pcie_host_ops tegra_pcie_dw_host_ops = {
>> + .rd_own_conf = tegra_pcie_dw_rd_own_conf,
>> + .wr_own_conf = tegra_pcie_dw_wr_own_conf,
>> + .host_init = tegra_pcie_dw_host_init,
>> + .set_num_vectors = tegra_pcie_set_msi_vec_num,
>> +};
>> +
>> +static void tegra_pcie_disable_phy(struct tegra_pcie_dw *pcie)
>> +{
>> + unsigned int phy_count = pcie->phy_count;
>> +
>> + while (phy_count--) {
>> + phy_power_off(pcie->phys[phy_count]);
>> + phy_exit(pcie->phys[phy_count]);
>> + }
>> +}
>> +
>> +static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie)
>> +{
>> + unsigned int i;
>> + int ret;
>> +
>> + for (i = 0; i < pcie->phy_count; i++) {
>> + ret = phy_init(pcie->phys[i]);
>> + if (ret < 0)
>> + goto phy_power_off;
>> +
>> + ret = phy_power_on(pcie->phys[i]);
>> + if (ret < 0)
>> + goto phy_exit;
>> + }
>> +
>> + return 0;
>> +
>> +phy_power_off:
>> + while (i--) {
>> + phy_power_off(pcie->phys[i]);
>> +phy_exit:
>> + phy_exit(pcie->phys[i]);
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
>> +{
>> + struct device_node *np = pcie->dev->of_node;
>> + int ret;
>> +
>> + ret = of_property_read_u32(np, "nvidia,aspm-cmrt-us", &pcie->aspm_cmrt);
>> + if (ret < 0) {
>> + dev_info(pcie->dev, "Failed to read ASPM T_cmrt: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + ret = of_property_read_u32(np, "nvidia,aspm-pwr-on-t-us",
>> + &pcie->aspm_pwr_on_t);
>> + if (ret < 0)
>> + dev_info(pcie->dev, "Failed to read ASPM Power On time: %d\n",
>> + ret);
>> +
>> + ret = of_property_read_u32(np, "nvidia,aspm-l0s-entrance-latency-us",
>> + &pcie->aspm_l0s_enter_lat);
>> + if (ret < 0)
>> + dev_info(pcie->dev,
>> + "Failed to read ASPM L0s Entrance latency: %d\n", ret);
>> +
>> + ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes);
>> + if (ret < 0) {
>> + dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + pcie->max_speed = of_pci_get_max_link_speed(np);
>> +
>> + ret = of_property_read_u32_index(np, "nvidia,bpmp", 1, &pcie->cid);
>> + if (ret) {
>> + dev_err(pcie->dev, "Failed to read Controller-ID: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + pcie->phy_count = of_property_count_strings(np, "phy-names");
>> + if (pcie->phy_count < 0) {
>> + dev_err(pcie->dev, "Failed to find PHY entries: %d\n",
>> + pcie->phy_count);
>> + return pcie->phy_count;
>> + }
>> +
>> + if (of_property_read_bool(np, "nvidia,update-fc-fixup"))
>> + pcie->update_fc_fixup = true;
>> +
>> + pcie->supports_clkreq =
>> + of_property_read_bool(pcie->dev->of_node, "supports-clkreq");
>> +
>> + pcie->enable_cdm_check =
>> + of_property_read_bool(np, "snps,enable-cdm-check");
>> +
>> + return 0;
>> +}
>> +
>> +static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
>> + bool enable)
>> +{
>> + struct mrq_uphy_response resp;
>> + struct tegra_bpmp_message msg;
>> + struct mrq_uphy_request req;
>> + int err;
>> +
>> + if (pcie->cid == 5)
>> + return 0;
>
> What's wrong with cid == 5 ? Explain please.
Controller with ID=5 doesn't need any programming to enable it which is
done here through calling firmware API.
>
>> + memset(&req, 0, sizeof(req));
>> + memset(&resp, 0, sizeof(resp));
>> +
>> + req.cmd = CMD_UPHY_PCIE_CONTROLLER_STATE;
>> + req.controller_state.pcie_controller = pcie->cid;
>> + req.controller_state.enable = enable;
>> +
>> + memset(&msg, 0, sizeof(msg));
>> + msg.mrq = MRQ_UPHY;
>> + msg.tx.data = &req;
>> + msg.tx.size = sizeof(req);
>> + msg.rx.data = &resp;
>> + msg.rx.size = sizeof(resp);
>> +
>> + if (irqs_disabled())
>
> Can you explain to me what this check is meant to achieve please ?
Firmware interface provides different APIs to be called when there are no
interrupts enabled in the system (noirq context) and otherwise hence
checking that situation here and calling appropriate API.
>
>> + err = tegra_bpmp_transfer_atomic(pcie->bpmp, &msg);
>> + else
>> + err = tegra_bpmp_transfer(pcie->bpmp, &msg);
>> +
>> + return err;
>> +}
>> +
>> +static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)
>> +{
>> + struct pcie_port *pp = &pcie->pci.pp;
>> + struct pci_dev *pdev;
>> + struct pci_bus *child;
>> +
>> + list_for_each_entry(child, &pp->root_bus->children, node) {
>> + /* Bring downstream devices to D0 if they are not already in */
>> + if (child->parent == pp->root_bus)
>> + break;
>> + }
>> + list_for_each_entry(pdev, &child->devices, bus_list) {
>> + if (PCI_SLOT(pdev->devfn) == 0) {
>> + if (pci_set_power_state(pdev, PCI_D0))
>> + dev_err(pcie->dev,
>> + "Failed to transition %s to D0 state\n",
>> + dev_name(&pdev->dev));
>> + }
>> + }
>> +}
>> +
>> +static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
>> + bool en_hw_hot_rst)
>> +{
>> + int ret;
>> + u32 val;
>> +
>> + ret = tegra_pcie_bpmp_set_ctrl_state(pcie, true);
>> + if (ret) {
>> + dev_err(pcie->dev,
>> + "Failed to enable controller %u: %d\n", pcie->cid, ret);
>> + return ret;
>> + }
>> +
>> + ret = regulator_enable(pcie->pex_ctl_supply);
>> + if (ret < 0) {
>> + dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret);
>> + goto fail_reg_en;
>> + }
>> +
>> + ret = clk_prepare_enable(pcie->core_clk);
>> + if (ret) {
>> + dev_err(pcie->dev, "Failed to enable core clock: %d\n", ret);
>> + goto fail_core_clk;
>> + }
>> +
>> + ret = reset_control_deassert(pcie->core_apb_rst);
>> + if (ret) {
>> + dev_err(pcie->dev, "Failed to deassert core APB reset: %d\n",
>> + ret);
>> + goto fail_core_apb_rst;
>> + }
>> +
>> + if (en_hw_hot_rst) {
>> + /* Enable HW_HOT_RST mode */
>> + val = appl_readl(pcie, APPL_CTRL);
>> + val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
>> + APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
>> + val |= APPL_CTRL_HW_HOT_RST_EN;
>> + appl_writel(pcie, val, APPL_CTRL);
>> + }
>> +
>> + ret = tegra_pcie_enable_phy(pcie);
>> + if (ret) {
>> + dev_err(pcie->dev, "Failed to enable PHY: %d\n", ret);
>> + goto fail_phy;
>> + }
>> +
>> + /* Update CFG base address */
>> + appl_writel(pcie, pcie->dbi_res->start & APPL_CFG_BASE_ADDR_MASK,
>> + APPL_CFG_BASE_ADDR);
>> +
>> + /* Configure this core for RP mode operation */
>> + appl_writel(pcie, APPL_DM_TYPE_RP, APPL_DM_TYPE);
>> +
>> + appl_writel(pcie, 0x0, APPL_CFG_SLCG_OVERRIDE);
>> +
>> + val = appl_readl(pcie, APPL_CTRL);
>> + appl_writel(pcie, val | APPL_CTRL_SYS_PRE_DET_STATE, APPL_CTRL);
>> +
>> + val = appl_readl(pcie, APPL_CFG_MISC);
>> + val |= (APPL_CFG_MISC_ARCACHE_VAL << APPL_CFG_MISC_ARCACHE_SHIFT);
>> + appl_writel(pcie, val, APPL_CFG_MISC);
>> +
>> + if (!pcie->supports_clkreq) {
>> + val = appl_readl(pcie, APPL_PINMUX);
>> + val |= APPL_PINMUX_CLKREQ_OUT_OVRD_EN;
>> + val |= APPL_PINMUX_CLKREQ_OUT_OVRD;
>> + appl_writel(pcie, val, APPL_PINMUX);
>> + }
>> +
>> + /* Update iATU_DMA base address */
>> + appl_writel(pcie,
>> + pcie->atu_dma_res->start & APPL_CFG_IATU_DMA_BASE_ADDR_MASK,
>> + APPL_CFG_IATU_DMA_BASE_ADDR);
>> +
>> + reset_control_deassert(pcie->core_rst);
>> +
>> + pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
>> + PCI_CAP_ID_EXP);
>> +
>> +#if defined(CONFIG_PCIEASPM)
>> + /* Disable ASPM-L1SS advertisement as there is no CLKREQ routing */
>> + if (!pcie->supports_clkreq) {
>> + disable_aspm_l11(pcie);
>> + disable_aspm_l12(pcie);
>> + }
>> +#endif
>> + return ret;
>> +
>> +fail_phy:
>> + reset_control_assert(pcie->core_apb_rst);
>> +fail_core_apb_rst:
>> + clk_disable_unprepare(pcie->core_clk);
>> +fail_core_clk:
>> + regulator_disable(pcie->pex_ctl_supply);
>> +fail_reg_en:
>> + tegra_pcie_bpmp_set_ctrl_state(pcie, false);
>> +
>> + return ret;
>> +}
>> +
>> +static int __deinit_controller(struct tegra_pcie_dw *pcie)
>> +{
>> + int ret;
>> +
>> + ret = reset_control_assert(pcie->core_rst);
>> + if (ret) {
>> + dev_err(pcie->dev, "Failed to assert \"core\" reset: %d\n",
>> + ret);
>> + return ret;
>> + }
>> + tegra_pcie_disable_phy(pcie);
>> + ret = reset_control_assert(pcie->core_apb_rst);
>> + if (ret) {
>> + dev_err(pcie->dev, "Failed to assert APB reset: %d\n", ret);
>> + return ret;
>> + }
>> + clk_disable_unprepare(pcie->core_clk);
>> + ret = regulator_disable(pcie->pex_ctl_supply);
>> + if (ret) {
>> + dev_err(pcie->dev, "Failed to disable regulator: %d\n", ret);
>> + return ret;
>> + }
>> + ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false);
>> + if (ret) {
>> + dev_err(pcie->dev, "Failed to disable controller %d: %d\n",
>> + pcie->cid, ret);
>> + return ret;
>> + }
>> + return ret;
>> +}
>> +
>> +static int tegra_pcie_init_controller(struct tegra_pcie_dw *pcie)
>> +{
>> + struct dw_pcie *pci = &pcie->pci;
>> + struct pcie_port *pp = &pci->pp;
>> + int ret;
>> +
>> + ret = tegra_pcie_config_controller(pcie, false);
>> + if (ret < 0)
>> + return ret;
>> +
>> + pp->root_bus_nr = -1;
>> + pp->ops = &tegra_pcie_dw_host_ops;
>> +
>> + ret = dw_pcie_host_init(pp);
>> + if (ret < 0) {
>> + dev_err(pcie->dev, "Failed to add PCIe port: %d\n", ret);
>> + goto fail_host_init;
>> + }
>> +
>> + return 0;
>> +
>> +fail_host_init:
>> + return __deinit_controller(pcie);
>> +}
>> +
>> +static int tegra_pcie_try_link_l2(struct tegra_pcie_dw *pcie)
>> +{
>> + u32 val;
>> +
>> + if (!tegra_pcie_dw_link_up(&pcie->pci))
>> + return 0;
>> +
>> + val = appl_readl(pcie, APPL_RADM_STATUS);
>> + val |= APPL_PM_XMT_TURNOFF_STATE;
>> + appl_writel(pcie, val, APPL_RADM_STATUS);
>> +
>> + return readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG, val,
>> + val & APPL_DEBUG_PM_LINKST_IN_L2_LAT,
>> + 1, PME_ACK_TIMEOUT);
>> +}
>> +
>> +static void tegra_pcie_dw_pme_turnoff(struct tegra_pcie_dw *pcie)
>> +{
>> + u32 data;
>> + int err;
>> +
>> + if (!tegra_pcie_dw_link_up(&pcie->pci)) {
>> + dev_dbg(pcie->dev, "PCIe link is not up...!\n");
>> + return;
>> + }
>> +
>> + if (tegra_pcie_try_link_l2(pcie)) {
>> + dev_info(pcie->dev, "Link didn't transition to L2 state\n");
>> + /*
>> + * TX lane clock freq will reset to Gen1 only if link is in L2
>> + * or detect state.
>> + * So apply pex_rst to end point to force RP to go into detect
>> + * state
>> + */
>> + data = appl_readl(pcie, APPL_PINMUX);
>> + data &= ~APPL_PINMUX_PEX_RST;
>> + appl_writel(pcie, data, APPL_PINMUX);
>> +
>> + err = readl_poll_timeout_atomic(pcie->appl_base + APPL_DEBUG,
>> + data,
>> + ((data &
>> + APPL_DEBUG_LTSSM_STATE_MASK) >>
>> + APPL_DEBUG_LTSSM_STATE_SHIFT) ==
>> + LTSSM_STATE_PRE_DETECT,
>> + 1, LTSSM_TIMEOUT);
>> + if (err) {
>> + dev_info(pcie->dev, "Link didn't go to detect state\n");
>> + } else {
>> + /* Disable LTSSM after link is in detect state */
>> + data = appl_readl(pcie, APPL_CTRL);
>> + data &= ~APPL_CTRL_LTSSM_EN;
>> + appl_writel(pcie, data, APPL_CTRL);
>> + }
>> + }
>> + /*
>> + * DBI registers may not be accessible after this as PLL-E would be
>> + * down depending on how CLKREQ is pulled by end point
>> + */
>> + data = appl_readl(pcie, APPL_PINMUX);
>> + data |= (APPL_PINMUX_CLKREQ_OVERRIDE_EN | APPL_PINMUX_CLKREQ_OVERRIDE);
>> + /* Cut REFCLK to slot */
>> + data |= APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN;
>> + data &= ~APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE;
>> + appl_writel(pcie, data, APPL_PINMUX);
>> +}
>> +
>> +static int tegra_pcie_deinit_controller(struct tegra_pcie_dw *pcie)
>> +{
>> + /*
>> + * link doesn't go into L2 state with some of the endpoints with Tegra
>> + * if they are not in D0 state. So, need to make sure that immediate
>> + * downstream devices are in D0 state before sending PME_TurnOff to put
>> + * link into L2 state
>> + */
>> + tegra_pcie_downstream_dev_to_D0(pcie);
>> + dw_pcie_host_deinit(&pcie->pci.pp);
>> + tegra_pcie_dw_pme_turnoff(pcie);
>> + return __deinit_controller(pcie);
>> +}
>> +
>> +static int tegra_pcie_config_rp(struct tegra_pcie_dw *pcie)
>> +{
>> + struct pcie_port *pp = &pcie->pci.pp;
>> + struct device *dev = pcie->dev;
>> + char *name;
>> + int ret;
>> +
>> + if (IS_ENABLED(CONFIG_PCI_MSI)) {
>> + pp->msi_irq = of_irq_get_byname(dev->of_node, "msi");
>> + if (!pp->msi_irq) {
>> + dev_err(dev, "Failed to get MSI interrupt\n");
>> + return -ENODEV;
>> + }
>> + }
>> +
>> + pm_runtime_enable(dev);
>> + ret = pm_runtime_get_sync(dev);
>> + if (ret < 0) {
>> + dev_err(dev, "Failed to get runtime sync for PCIe dev: %d\n",
>> + ret);
>> + pm_runtime_disable(dev);
>> + return ret;
>> + }
>> +
>> + tegra_pcie_init_controller(pcie);
>> +
>> + pcie->link_state = tegra_pcie_dw_link_up(&pcie->pci);
>> +
>> + if (!pcie->link_state) {
>> + ret = -ENOMEDIUM;
>> + goto fail_host_init;
>> + }
>> +
>> + name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node);
>> + if (!name) {
>> + ret = -ENOMEM;
>> + goto fail_host_init;
>> + }
>> +
>> + pcie->debugfs = debugfs_create_dir(name, NULL);
>> + if (!pcie->debugfs)
>> + dev_err(dev, "Failed to create debugfs\n");
>> + else
>> + init_debugfs(pcie);
>> +
>> + return ret;
>> +
>> +fail_host_init:
>> + tegra_pcie_deinit_controller(pcie);
>> + pm_runtime_put_sync(dev);
>> + pm_runtime_disable(dev);
>> + return ret;
>> +}
>> +
>> +static const struct tegra_pcie_soc tegra_pcie_rc_of_data = {
>> + .mode = DW_PCIE_RC_TYPE,
>> +};
>> +
>> +static const struct of_device_id tegra_pcie_dw_of_match[] = {
>> + {
>> + .compatible = "nvidia,tegra194-pcie",
>> + .data = &tegra_pcie_rc_of_data,
>> + },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, tegra_pcie_dw_of_match);
>> +
>> +static int tegra_pcie_dw_probe(struct platform_device *pdev)
>> +{
>> + const struct tegra_pcie_soc *data;
>> + struct device *dev = &pdev->dev;
>> + struct resource *atu_dma_res;
>> + struct tegra_pcie_dw *pcie;
>> + struct resource *dbi_res;
>> + struct pcie_port *pp;
>> + struct dw_pcie *pci;
>> + struct phy **phys;
>> + char *name;
>> + int ret;
>> + u32 i;
>> +
>> + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
>> + if (!pcie)
>> + return -ENOMEM;
>> +
>> + pci = &pcie->pci;
>> + pci->dev = &pdev->dev;
>> + pci->ops = &tegra_dw_pcie_ops;
>> + pp = &pci->pp;
>> + pcie->dev = &pdev->dev;
>> +
>> + data = (struct tegra_pcie_soc *)of_device_get_match_data(dev);
>> + if (!data)
>> + return -EINVAL;
>> + pcie->mode = (enum dw_pcie_device_mode)data->mode;
>> +
>> + ret = tegra_pcie_dw_parse_dt(pcie);
>> + if (ret < 0) {
>> + dev_err(dev, "Failed to parse device tree: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl");
>> + if (IS_ERR(pcie->pex_ctl_supply)) {
>> + dev_err(dev, "Failed to get regulator: %ld\n",
>> + PTR_ERR(pcie->pex_ctl_supply));
>> + return PTR_ERR(pcie->pex_ctl_supply);
>> + }
>> +
>> + pcie->core_clk = devm_clk_get(dev, "core");
>> + if (IS_ERR(pcie->core_clk)) {
>> + dev_err(dev, "Failed to get core clock: %ld\n",
>> + PTR_ERR(pcie->core_clk));
>> + return PTR_ERR(pcie->core_clk);
>> + }
>> +
>> + pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
>> + "appl");
>> + if (!pcie->appl_res) {
>> + dev_err(dev, "Failed to find \"appl\" region\n");
>> + return PTR_ERR(pcie->appl_res);
>> + }
>> + pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res);
>> + if (IS_ERR(pcie->appl_base))
>> + return PTR_ERR(pcie->appl_base);
>> +
>> + pcie->core_apb_rst = devm_reset_control_get(dev, "apb");
>> + if (IS_ERR(pcie->core_apb_rst)) {
>> + dev_err(dev, "Failed to get APB reset: %ld\n",
>> + PTR_ERR(pcie->core_apb_rst));
>> + return PTR_ERR(pcie->core_apb_rst);
>> + }
>> +
>> + phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL);
>> + if (!phys)
>> + return PTR_ERR(phys);
>> +
>> + for (i = 0; i < pcie->phy_count; i++) {
>> + name = kasprintf(GFP_KERNEL, "p2u-%u", i);
>> + if (!name) {
>> + dev_err(dev, "Failed to create P2U string\n");
>> + return -ENOMEM;
>> + }
>> + phys[i] = devm_phy_get(dev, name);
>> + kfree(name);
>> + if (IS_ERR(phys[i])) {
>> + ret = PTR_ERR(phys[i]);
>> + dev_err(dev, "Failed to get PHY: %d\n", ret);
>> + return ret;
>> + }
>> + }
>> +
>> + pcie->phys = phys;
>> +
>> + dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
>> + if (!dbi_res) {
>> + dev_err(dev, "Failed to find \"dbi\" region\n");
>> + return PTR_ERR(dbi_res);
>> + }
>> + pcie->dbi_res = dbi_res;
>> +
>> + pci->dbi_base = devm_ioremap_resource(dev, dbi_res);
>> + if (IS_ERR(pci->dbi_base))
>> + return PTR_ERR(pci->dbi_base);
>> +
>> + /* Tegra HW locates DBI2 at a fixed offset from DBI */
>> + pci->dbi_base2 = pci->dbi_base + 0x1000;
>> +
>> + atu_dma_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
>> + "atu_dma");
>> + if (!atu_dma_res) {
>> + dev_err(dev, "Failed to find \"atu_dma\" region\n");
>> + return PTR_ERR(atu_dma_res);
>> + }
>> + pcie->atu_dma_res = atu_dma_res;
>> + pci->atu_base = devm_ioremap_resource(dev, atu_dma_res);
>> + if (IS_ERR(pci->atu_base))
>> + return PTR_ERR(pci->atu_base);
>> +
>> + pcie->core_rst = devm_reset_control_get(dev, "core");
>> + if (IS_ERR(pcie->core_rst)) {
>> + dev_err(dev, "Failed to get core reset: %ld\n",
>> + PTR_ERR(pcie->core_rst));
>> + return PTR_ERR(pcie->core_rst);
>> + }
>> +
>> + pp->irq = platform_get_irq_byname(pdev, "intr");
>> + if (!pp->irq) {
>> + dev_err(dev, "Failed to get \"intr\" interrupt\n");
>> + return -ENODEV;
>> + }
>> +
>> + ret = devm_request_irq(dev, pp->irq, tegra_pcie_irq_handler,
>> + IRQF_SHARED, "tegra-pcie-intr", pcie);
>> + if (ret) {
>> + dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, ret);
>> + return ret;
>> + }
>> +
>> + pcie->bpmp = tegra_bpmp_get(dev);
>> + if (IS_ERR(pcie->bpmp))
>> + return PTR_ERR(pcie->bpmp);
>> +
>> + platform_set_drvdata(pdev, pcie);
>> +
>> + if (pcie->mode == DW_PCIE_RC_TYPE) {
>> + ret = tegra_pcie_config_rp(pcie);
>> + if (ret && ret != -ENOMEDIUM)
>> + goto fail;
>> + else
>> + return 0;
>
> So if the link is not up we still go ahead and make probe
> succeed. What for ?
We may need root port to be available to support hot-plugging of endpoint
devices, so, we don't fail the probe.
>
>> + }
>> +
>> +fail:
>> + tegra_bpmp_put(pcie->bpmp);
>> + return ret;
>> +}
>> +
>> +static int tegra_pcie_dw_remove(struct platform_device *pdev)
>> +{
>> + struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
>> +
>> + if (pcie->mode != DW_PCIE_RC_TYPE)
>> + return 0;
>> +
>> + if (!pcie->link_state)
>> + return 0;
>> +
>> + debugfs_remove_recursive(pcie->debugfs);
>> + tegra_pcie_deinit_controller(pcie);
>> + pm_runtime_put_sync(pcie->dev);
>> + pm_runtime_disable(pcie->dev);
>> + tegra_bpmp_put(pcie->bpmp);
>> +
>> + return 0;
>> +}
>> +
>> +static int tegra_pcie_dw_suspend_late(struct device *dev)
>> +{
>> + struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
>> + u32 val;
>> +
>> + if (!pcie->link_state)
>> + return 0;
>> +
>> + /* Enable HW_HOT_RST mode */
>> + val = appl_readl(pcie, APPL_CTRL);
>> + val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
>> + APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
>> + val |= APPL_CTRL_HW_HOT_RST_EN;
>> + appl_writel(pcie, val, APPL_CTRL);
>> +
>> + return 0;
>> +}
>> +
>> +static int tegra_pcie_dw_suspend_noirq(struct device *dev)
>> +{
>> + struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
>> +
>> + if (!pcie->link_state)
>> + return 0;
>> +
>> + /* Save MSI interrupt vector */
>> + pcie->msi_ctrl_int = dw_pcie_readl_dbi(&pcie->pci,
>> + PORT_LOGIC_MSI_CTRL_INT_0_EN);
>> + tegra_pcie_downstream_dev_to_D0(pcie);
>
> I think this requires some comments. AFAIU this is allowed by
> the PCI specs (PCI Express Base 4.0 r1.0 September 29-2017,
> 5.2 Link State Power Management). However, I would like to
> understand how this plays with the D state the devices are left
> in upon system suspend.
>
> "As the following example illustrates, it is also possible to remove
> power without first placing all Functions into D3Hot".
>
> I assume that's what happens on this platform to allow L2 entry but
> again, this needs clarification.
Yes. It is true that in the case of Tegra194, it brings devices back to D0
before putting link to L2 state.
>
> Lorenzo
>
>> + tegra_pcie_dw_pme_turnoff(pcie);
>> + return __deinit_controller(pcie);
>> +}
>> +
>> +static int tegra_pcie_dw_resume_noirq(struct device *dev)
>> +{
>> + struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
>> + int ret;
>> +
>> + if (!pcie->link_state)
>> + return 0;
>> +
>> + ret = tegra_pcie_config_controller(pcie, true);
>> + if (ret < 0)
>> + return ret;
>> +
>> + ret = tegra_pcie_dw_host_init(&pcie->pci.pp);
>> + if (ret < 0) {
>> + dev_err(dev, "Failed to init host: %d\n", ret);
>> + goto fail_host_init;
>> + }
>> +
>> + /* Restore MSI interrupt vector */
>> + dw_pcie_writel_dbi(&pcie->pci, PORT_LOGIC_MSI_CTRL_INT_0_EN,
>> + pcie->msi_ctrl_int);
>> +
>> + return 0;
>> +fail_host_init:
>> + return __deinit_controller(pcie);
>> +}
>> +
>> +static int tegra_pcie_dw_resume_early(struct device *dev)
>> +{
>> + struct tegra_pcie_dw *pcie = dev_get_drvdata(dev);
>> + u32 val;
>> +
>> + if (!pcie->link_state)
>> + return 0;
>> +
>> + /* Disable HW_HOT_RST mode */
>> + val = appl_readl(pcie, APPL_CTRL);
>> + val &= ~(APPL_CTRL_HW_HOT_RST_MODE_MASK <<
>> + APPL_CTRL_HW_HOT_RST_MODE_SHIFT);
>> + val |= APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST <<
>> + APPL_CTRL_HW_HOT_RST_MODE_SHIFT;
>> + val &= ~APPL_CTRL_HW_HOT_RST_EN;
>> + appl_writel(pcie, val, APPL_CTRL);
>> +
>> + return 0;
>> +}
>> +
>> +static void tegra_pcie_dw_shutdown(struct platform_device *pdev)
>> +{
>> + struct tegra_pcie_dw *pcie = platform_get_drvdata(pdev);
>> +
>> + if (pcie->mode != DW_PCIE_RC_TYPE)
>> + return;
>> +
>> + if (!pcie->link_state)
>> + return;
>> +
>> + debugfs_remove_recursive(pcie->debugfs);
>> + tegra_pcie_downstream_dev_to_D0(pcie);
>> +
>> + disable_irq(pcie->pci.pp.irq);
>> + if (IS_ENABLED(CONFIG_PCI_MSI))
>> + disable_irq(pcie->pci.pp.msi_irq);
>> +
>> + tegra_pcie_dw_pme_turnoff(pcie);
>> + __deinit_controller(pcie);
>> +}
>> +
>> +static const struct dev_pm_ops tegra_pcie_dw_pm_ops = {
>> + .suspend_late = tegra_pcie_dw_suspend_late,
>> + .suspend_noirq = tegra_pcie_dw_suspend_noirq,
>> + .resume_noirq = tegra_pcie_dw_resume_noirq,
>> + .resume_early = tegra_pcie_dw_resume_early,
>> +};
>> +
>> +static struct platform_driver tegra_pcie_dw_driver = {
>> + .probe = tegra_pcie_dw_probe,
>> + .remove = tegra_pcie_dw_remove,
>> + .shutdown = tegra_pcie_dw_shutdown,
>> + .driver = {
>> + .name = "tegra194-pcie",
>> + .pm = &tegra_pcie_dw_pm_ops,
>> + .of_match_table = tegra_pcie_dw_of_match,
>> + },
>> +};
>> +module_platform_driver(tegra_pcie_dw_driver);
>> +
>> +MODULE_AUTHOR("Vidya Sagar <vidyas@nvidia.com>");
>> +MODULE_DESCRIPTION("NVIDIA PCIe host controller driver");
>> +MODULE_LICENSE("GPL v2");
>> --
>> 2.17.1
>>
^ permalink raw reply
* Re: [PATCH 1/3] Documentation: dt: edac: Add reg to S10 SDRAM node
From: Thor Thayer @ 2019-07-12 15:27 UTC (permalink / raw)
To: bp, mchehab, james.morse, robh+dt, mark.rutland, dinguyen
Cc: devicetree, linux-edac
In-Reply-To: <1562711090-900-2-git-send-email-thor.thayer@linux.intel.com>
On 7/9/19 5:24 PM, thor.thayer@linux.intel.com wrote:
> From: Thor Thayer <thor.thayer@linux.intel.com>
>
> Include the register offset and size in the Stratix10 SDRAM node
> to be consistent with other ECC modules.
> Previously had to follow the phandle to get the register size/offset.
>
> Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
> ---
> Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
> index 8f52206cfd2a..dd6ba6c020a7 100644
> --- a/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
> +++ b/Documentation/devicetree/bindings/edac/socfpga-eccmgr.txt
> @@ -256,6 +256,7 @@ Subcomponents:
> SDRAM ECC
> Required Properties:
> - compatible : Should be "altr,sdram-edac-s10"
> +- reg : Address and size for ECC block registers.
> - interrupts : Should be single bit error interrupt.
>
> On-Chip RAM ECC
> @@ -313,8 +314,9 @@ Example:
> #interrupt-cells = <2>;
> ranges;
>
> - sdramedac {
> + sdramedac@0xf8011100 {
> compatible = "altr,sdram-edac-s10";
> + reg = <0xf8011100 0xc0>;
> interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
> };
>
>
Please disregard this patch, there is a simpler solution that I will
submit shortly.
^ permalink raw reply
* Re: [PATCH 0/3] Stratix10 SDRAM Common EDAC Framework
From: Thor Thayer @ 2019-07-12 15:26 UTC (permalink / raw)
To: bp, mchehab, james.morse, robh+dt, mark.rutland, dinguyen
Cc: devicetree, linux-edac
In-Reply-To: <1562711090-900-1-git-send-email-thor.thayer@linux.intel.com>
On 7/9/19 5:24 PM, thor.thayer@linux.intel.com wrote:
> From: Thor Thayer <thor.thayer@linux.intel.com>
>
> Use the common Altera EDAC Device Framework for the SDRAM so that
> Double Bit Error Addresses can be tracked for SDRAM.
> This also simplifies the device tree.
>
> Thor Thayer (3):
> Documentation: dt: edac: Add reg to S10 SDRAM node
> arm64: dts: Stratix10: Include regs in SDRAM ECC node
> EDAC, altera: Use common framework for Stratix10 SDRAM ECC
>
> .../devicetree/bindings/edac/socfpga-eccmgr.txt | 4 ++-
> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 9 ++----
> drivers/edac/altera_edac.c | 32 ++++++++++++++++++++--
> drivers/edac/altera_edac.h | 25 ++++++++++++++++-
> 4 files changed, 58 insertions(+), 12 deletions(-)
>
Please disregard this patchset, there is a simpler solution.
^ permalink raw reply
* Re: [PATCH 2/3] arm64: dts: Stratix10: Include regs in SDRAM ECC node
From: Thor Thayer @ 2019-07-12 15:27 UTC (permalink / raw)
To: bp, mchehab, james.morse, robh+dt, mark.rutland, dinguyen
Cc: devicetree, linux-edac
In-Reply-To: <1562711090-900-3-git-send-email-thor.thayer@linux.intel.com>
On 7/9/19 5:24 PM, thor.thayer@linux.intel.com wrote:
> From: Thor Thayer <thor.thayer@linux.intel.com>
>
> Include the regs directly in the SDRAM node instead of using
> a syscon. The Stratix10 SDRAM ECC registers are partitioned
> away from other Sys Manager registers so the syscon is no
> longer needed for Stratix10.
>
> Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
> ---
> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 9 ++-------
> 1 file changed, 2 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> index 4b0f674df849..a1e9545de3d3 100644
> --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> @@ -517,11 +517,6 @@
> status = "disabled";
> };
>
> - sdr: sdr@f8011100 {
> - compatible = "altr,sdr-ctl", "syscon";
> - reg = <0xf8011100 0xc0>;
> - };
> -
> eccmgr {
> compatible = "altr,socfpga-s10-ecc-manager",
> "altr,socfpga-a10-ecc-manager";
> @@ -533,9 +528,9 @@
> #interrupt-cells = <2>;
> ranges;
>
> - sdramedac {
> + sdramedac@0xf8011100 {
> compatible = "altr,sdram-edac-s10";
> - altr,sdr-syscon = <&sdr>;
> + reg = <0xf8011100 0xc0>;
> interrupts = <16 4>;
> };
>
>
Please disregard this patch, there is a simpler solution that I will
submit shortly.
^ permalink raw reply
* Re: [PATCH] ARM: dts: imx6ul-kontron-ul2: Add Exceet/Kontron iMX6-UL2 SoM
From: Schrempf Frieder @ 2019-07-12 15:21 UTC (permalink / raw)
To: Krzysztof Kozlowski, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190712141242.4915-1-krzk@kernel.org>
Hi Krzysztof,
On 12.07.19 16:12, Krzysztof Kozlowski wrote:
> Add support for iMX6-UL2 modules from Kontron Electronics GmbH (before
> acquisition: Exceet Electronics) and evalkit boards based on it:
>
> 1. i.MX6 UL System-on-Module, a 25x25 mm solderable module (LGA pads and
> pin castellations) with 256 MB RAM, 1 MB NOR-Flash, 256 MB NAND and
> other interfaces,
> 1. UL2 evalkit, w/wo eMMC, without display,
> 2. UL2 evalkit with 4.3" display,
> 3. UL2 evalkit with 5.0" display.
>
> This includes device nodes for unsupported displays (Admatec
> T043C004800272T2A and T070P133T0S301).
>
> The work is based on Exceet source code (GPLv2) with numerous changes:
> 1. Reorganize files,
> 2. Rename Exceet -> Kontron,
> 3. Fix coding style errors,
> 4. Fix DTC warnings,
> 5. Extend compatibles so eval boards inherit the SoM compatible,
> 6. Use defines instead of GPIO flag values,
> 7. Adjust operating points of CPU0,
> 8. Sort nodes alphabetically.
>
> In downstream BSP the Exceet name still appears in multiple places
> therefore I left it in the model names.
First, thanks for your work. I planned to upstream these boards myself
after the FSL QSPI spi-mem driver was merged in 5.1, but didn't have
time to finalize and send the patches.
Meanwhile we came up with a new naming scheme for our boards, that
hasn't been implemented yet. But I would like to take this chance to
implement the new scheme.
Also there are some more flavors of the SoM (with i.MX6ULL instead of
i.MX6UL, with 512MiB instead of 256MiB flash/RAM), that I would like to
add and for which common parts of the SoM dtsi would need to be factored
out to a separate file.
I would prefer to at least apply the naming changes before merging. The
additional board flavors could be added before merging or I could send
them as follow-up patches. What do you think?
Thanks,
Frieder
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
> arch/arm/boot/dts/Makefile | 3 +
> arch/arm/boot/dts/imx6ul-kontron-ul2-43.dts | 123 +++++
> arch/arm/boot/dts/imx6ul-kontron-ul2-50.dts | 123 +++++
> arch/arm/boot/dts/imx6ul-kontron-ul2-som.dtsi | 152 ++++++
> arch/arm/boot/dts/imx6ul-kontron-ul2.dts | 435 ++++++++++++++++++
> 5 files changed, 836 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6ul-kontron-ul2-43.dts
> create mode 100644 arch/arm/boot/dts/imx6ul-kontron-ul2-50.dts
> create mode 100644 arch/arm/boot/dts/imx6ul-kontron-ul2-som.dtsi
> create mode 100644 arch/arm/boot/dts/imx6ul-kontron-ul2.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 9159fa2cea90..3431bb44fb5d 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -569,6 +569,9 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
> imx6ul-geam.dtb \
> imx6ul-isiot-emmc.dtb \
> imx6ul-isiot-nand.dtb \
> + imx6ul-kontron-ul2.dtb \
> + imx6ul-kontron-ul2-43.dtb \
> + imx6ul-kontron-ul2-50.dtb \
> imx6ul-liteboard.dtb \
> imx6ul-opos6uldev.dtb \
> imx6ul-pico-hobbit.dtb \
> diff --git a/arch/arm/boot/dts/imx6ul-kontron-ul2-43.dts b/arch/arm/boot/dts/imx6ul-kontron-ul2-43.dts
> new file mode 100644
> index 000000000000..a2b68ba14765
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6ul-kontron-ul2-43.dts
> @@ -0,0 +1,123 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2017 exceet electronics GmbH
> + * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include "imx6ul-kontron-ul2.dts"
> +
> +/ {
> + model = "Exceet/Kontron iMX6 UL-2 S 43";
> + compatible = "kontron,imx6ul-ul2-s-43", "kontron,imx6ul-ul2-s",
> + "kontron,imx6ul-ul2-som", "fsl,imx6ul";
> +
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + pwms = <&pwm7 0 5000000>;
> + brightness-levels = <0 4 8 16 32 64 128 255>;
> + default-brightness-level = <6>;
> + status = "okay";
> + };
> +
> + panel {
> + compatible = "admatec,t043c004800272t2a";
> + backlight = <&backlight>;
> +
> + port {
> + panel_in: endpoint {
> + remote-endpoint = <&display_out>;
> + };
> + };
> + };
> +};
> +
> +&i2c4 {
> + gt911@5d {
> + compatible = "goodix,gt928";
> + reg = <0x5d>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_cap_touch>;
> + interrupt-parent = <&gpio5>;
> + interrupts = <6 8>;
> + reset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
> + irq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
> + };
> +};
> +
> +&iomuxc {
> + pinctrl_lcdif_dat: lcdifdatgrp {
> + fsl,pins = <
> + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
> + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
> + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
> + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
> + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
> + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
> + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
> + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
> + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
> + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
> + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
> + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
> + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
> + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
> + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
> + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
> + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
> + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
> + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
> + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
> + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
> + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
> + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
> + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
> + >;
> + };
> +
> + pinctrl_lcdif_ctrl: lcdifctrlgrp {
> + fsl,pins = <
> + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
> + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
> + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
> + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
> + MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79
> + >;
> + };
> +
> + pinctrl_cap_touch: captouchgrp {
> + fsl,pins = <
> + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* Touch Interrupt */
> + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 /* Touch Reset */
> + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Touch Wake */
> + >;
> + };
> +
> + pinctrl_pwm7: pwm7grp {
> + fsl,pins = <
> + MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x110b0
> + >;
> + };
> +};
> +
> +&lcdif {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lcdif_dat
> + &pinctrl_lcdif_ctrl>;
> + status = "okay";
> +
> + port {
> + display_out: endpoint {
> + remote-endpoint = <&panel_in>;
> + };
> + };
> +};
> +
> +&pwm7 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm7>;
> + status = "okay";
> +};
> diff --git a/arch/arm/boot/dts/imx6ul-kontron-ul2-50.dts b/arch/arm/boot/dts/imx6ul-kontron-ul2-50.dts
> new file mode 100644
> index 000000000000..61017020e02f
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6ul-kontron-ul2-50.dts
> @@ -0,0 +1,123 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2017 exceet electronics GmbH
> + * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include "imx6ul-kontron-ul2.dts"
> +
> +/ {
> + model = "Exceet/Kontron iMX6 UL-2 S 50";
> + compatible = "kontron,imx6ul-ul2-s-50", "kontron,imx6ul-ul2-s",
> + "kontron,imx6ul-ul2-som", "fsl,imx6ul";
> +
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + pwms = <&pwm7 0 5000000>;
> + brightness-levels = <0 4 8 16 32 64 128 255>;
> + default-brightness-level = <6>;
> + status = "okay";
> + };
> +
> + panel {
> + compatible = "admatec,t070p133t0s301";
> + backlight = <&backlight>;
> +
> + port {
> + panel_in: endpoint {
> + remote-endpoint = <&display_out>;
> + };
> + };
> + };
> +};
> +
> +&i2c4 {
> + gt911@5d {
> + compatible = "goodix,gt928";
> + reg = <0x5d>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_cap_touch>;
> + interrupt-parent = <&gpio5>;
> + interrupts = <6 8>;
> + reset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
> + irq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
> + };
> +};
> +
> +&iomuxc {
> + pinctrl_lcdif_dat: lcdifdatgrp {
> + fsl,pins = <
> + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
> + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
> + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
> + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
> + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
> + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
> + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
> + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
> + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
> + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
> + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
> + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
> + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
> + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
> + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
> + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
> + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
> + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
> + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
> + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
> + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
> + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
> + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
> + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
> + >;
> + };
> +
> + pinctrl_lcdif_ctrl: lcdifctrlgrp {
> + fsl,pins = <
> + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
> + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
> + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
> + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
> + MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79
> + >;
> + };
> +
> + pinctrl_cap_touch: captouchgrp {
> + fsl,pins = <
> + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* Touch Interrupt */
> + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 /* Touch Reset */
> + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Touch Wake */
> + >;
> + };
> +
> + pinctrl_pwm7: pwm7grp {
> + fsl,pins = <
> + MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x110b0
> + >;
> + };
> +};
> +
> +&lcdif {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lcdif_dat
> + &pinctrl_lcdif_ctrl>;
> + status = "okay";
> +
> + port {
> + display_out: endpoint {
> + remote-endpoint = <&panel_in>;
> + };
> + };
> +};
> +
> +&pwm7 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm7>;
> + status = "okay";
> +};
> diff --git a/arch/arm/boot/dts/imx6ul-kontron-ul2-som.dtsi b/arch/arm/boot/dts/imx6ul-kontron-ul2-som.dtsi
> new file mode 100644
> index 000000000000..26b6615cf839
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6ul-kontron-ul2-som.dtsi
> @@ -0,0 +1,152 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2017 exceet electronics GmbH
> + * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include "imx6ul.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "Exceet/Kontron iMX6 UL-2 SOM";
> + compatible = "kontron,imx6ul-ul2-som", "fsl,imx6ul";
> +
> + memory@80000000 {
> + reg = <0x80000000 0x10000000>;
> + };
> +};
> +
> +&cpu0 {
> + clock-frequency = <528000000>;
> + operating-points = <
> + /* kHz uV */
> + 528000 1175000
> + 396000 1025000
> + 198000 950000
> + >;
> + fsl,soc-operating-points = <
> + /* KHz uV */
> + 528000 1175000
> + 396000 1175000
> + 198000 1175000
> + >;
> +};
> +
> +&ecspi2 {
> + cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi2>;
> + status = "okay";
> +
> + flash: mx25v80@0 {
> + compatible = "macronix,mx25v8035f", "jedec,spi-nor";
> + spi-max-frequency = <50000000>;
> + reg = <0>;
> + };
> +};
> +
> +&fec1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
> + phy-mode = "rmii";
> + phy-handle = <ðphy1>;
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy1: ethernet-phy@1 {
> + reg = <1>;
> + micrel,led-mode = <0>;
> + clocks = <&clks IMX6UL_CLK_ENET_REF>;
> + clock-names = "rmii-ref";
> + };
> + };
> +};
> +
> +&fec2 {
> + phy-mode = "rmii";
> + status = "disabled";
> +};
> +
> +&iomuxc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reset_out>;
> +
> + pinctrl_reset_out: rstoutgrp {
> + fsl,pins = <
> + MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
> + >;
> + };
> +
> + pinctrl_ecspi2: ecspi2grp {
> + fsl,pins = <
> + MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1
> + MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1
> + MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1
> + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1
> + >;
> + };
> +
> + pinctrl_enet1: enet1grp {
> + fsl,pins = <
> + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
> + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
> + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
> + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
> + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
> + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
> + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
> + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009
> + >;
> + };
> +
> + pinctrl_enet1_mdio: enet1mdiogrp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
> + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
> + >;
> + };
> +
> + pinctrl_qspi: qspigrp {
> + fsl,pins = <
> + MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
> + MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
> + MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
> + MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
> + MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
> + MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
> + >;
> + };
> +};
> +
> +&qspi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_qspi>;
> + status = "okay";
> +
> + flash0: w25m02gv@0 {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "spi-nand";
> + spi-max-frequency = <108000000>;
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> + reg = <0>;
> +
> + partition@0 {
> + label = "ubi1";
> + reg = <0x00000000 0x08000000>;
> + };
> +
> + partition@8000000 {
> + label = "ubi2";
> + reg = <0x08000000 0x08000000>;
> + };
> + };
> +};
> diff --git a/arch/arm/boot/dts/imx6ul-kontron-ul2.dts b/arch/arm/boot/dts/imx6ul-kontron-ul2.dts
> new file mode 100644
> index 000000000000..6d394a97712b
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6ul-kontron-ul2.dts
> @@ -0,0 +1,435 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2017 exceet electronics GmbH
> + * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +/dts-v1/;
> +
> +#include "imx6ul-kontron-ul2-som.dtsi"
> +
> +/ {
> + model = "Exceet/Kontron iMX6 UL-2 S";
> + compatible = "kontron,imx6ul-ul2-s", "kontron,imx6ul-ul2-som",
> + "fsl,imx6ul";
> +
> + pwm-beeper {
> + compatible = "pwm-beeper";
> + pwms = <&pwm8 0 5000>;
> + };
> +
> + gpio-leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio_leds>;
> +
> + led1 {
> + label = "debug-led1";
> + gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
> + default-state = "off";
> + linux,default-trigger = "heartbeat";
> + };
> +
> + led2 {
> + label = "debug-led2";
> + gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
> + default-state = "off";
> + };
> +
> + led3 {
> + label = "debug-led3";
> + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
> + default-state = "off";
> + };
> + };
> +
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg_3v3: regulator@0 {
> + compatible = "regulator-fixed";
> + reg = <0>;
> + regulator-name = "3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + reg_vref_adc: regulator@1 {
> + compatible = "regulator-fixed";
> + reg = <1>;
> + regulator-name = "vref-adc";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + reg_usb_otg1_vbus: regulator@2 {
> + compatible = "regulator-fixed";
> + reg = <2>;
> + regulator-name = "usb_otg1_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> + };
> +
> +};
> +
> +&adc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_adc1>;
> + num-channels = <3>;
> + vref-supply = <®_vref_adc>;
> + status = "okay";
> +};
> +
> +&can2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan2>;
> + status = "okay";
> +};
> +
> +&ecspi1 {
> + fsl,spi-num-chipselects = <1>;
> + cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi1>;
> + status = "okay";
> +
> + fram@0 {
> + compatible = "atmel,at25";
> + reg = <0>;
> + spi-max-frequency = <20000000>;
> + spi-cpha;
> + spi-cpol;
> + pagesize = <1>;
> + size = <8192>;
> + address-width = <16>;
> + };
> +};
> +
> +&fec1 {
> + pinctrl-0 = <&pinctrl_enet1>;
> + /delete-node/ mdio;
> +};
> +
> +&fec2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
> + phy-mode = "rmii";
> + phy-handle = <ðphy2>;
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy1: ethernet-phy@1 {
> + reg = <1>;
> + micrel,led-mode = <0>;
> + clocks = <&clks IMX6UL_CLK_ENET_REF>;
> + clock-names = "rmii-ref";
> + };
> +
> + ethphy2: ethernet-phy@2 {
> + reg = <2>;
> + micrel,led-mode = <0>;
> + clocks = <&clks IMX6UL_CLK_ENET2_REF>;
> + clock-names = "rmii-ref";
> + };
> + };
> +};
> +
> +&i2c1 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +};
> +
> +&i2c4 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c4>;
> + status = "okay";
> +
> + rtc@32 {
> + compatible = "epson,rx8900";
> + reg = <0x32>;
> + };
> +};
> +
> +&iomuxc {
> + pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
> +
> + pinctrl_wdog: wdoggrp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0
> + >;
> + };
> +
> + pinctrl_gpio: gpio {
> + fsl,pins = <
> + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
> + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
> + MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
> + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
> + >;
> + };
> +
> + pinctrl_usbotg1: usbotg1 {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
> + >;
> + };
> +
> + pinctrl_gpio_leds: gpio_leds {
> + fsl,pins = <
> + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
> + MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
> + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
> + >;
> + };
> +
> + /* FRAM */
> + pinctrl_ecspi1: ecspi1grp-1 {
> + fsl,pins = <
> + MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
> + MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
> + MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
> + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
> + >;
> + };
> +
> + pinctrl_enet2: enet2grp {
> + fsl,pins = <
> + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
> + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
> + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
> + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
> + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
> + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
> + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
> + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
> + >;
> + };
> +
> + pinctrl_enet2_mdio: enet2mdiogrp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
> + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
> + >;
> + };
> +
> + pinctrl_flexcan2: flexcan2grp{
> + fsl,pins = <
> + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
> + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
> + >;
> + };
> +
> + pinctrl_pwm8: pwm8grp {
> + fsl,pins = <
> + MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
> + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> + MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
> + MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
> + MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
> + /*
> + * mux unused RTS to make sure it doesn't cause
> + * any interrupts when it is undefined
> + */
> + MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart3: uart3grp {
> + fsl,pins = <
> + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
> + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
> + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
> + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart4: uart4grp {
> + fsl,pins = <
> + MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
> + MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
> + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
> + >;
> + };
> +
> + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
> + fsl,pins = <
> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
> + >;
> + };
> +
> + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
> + fsl,pins = <
> + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
> + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
> + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
> + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
> + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
> + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
> + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
> + >;
> + };
> +
> + pinctrl_i2c4: i2c4grp {
> + fsl,pins = <
> + MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
> + MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
> + >;
> + };
> +
> + pinctrl_adc1: adc1grp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
> + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
> + MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
> + >;
> + };
> +};
> +
> +&pwm8 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm8>;
> + status = "okay";
> +};
> +
> +&snvs_poweroff {
> + status = "okay";
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + status = "okay";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2>;
> + linux,rs485-enabled-at-boot-time;
> + rs485-rx-during-tx;
> + rs485-rts-active-low;
> + uart-has-rtscts;
> + status = "okay";
> +};
> +
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3>;
> + fsl,uart-has-rtscts;
> + status = "okay";
> +};
> +
> +&uart4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart4>;
> + status = "okay";
> +};
> +
> +&usbotg1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbotg1>;
> + dr_mode = "otg";
> + status = "okay";
> + srp-disable;
> + hnp-disable;
> + adp-disable;
> + vbus-supply = <®_usb_otg1_vbus>;
> +};
> +
> +&usbotg2 {
> + dr_mode = "host";
> + disable-over-current;
> + status = "okay";
> +};
> +
> +&usdhc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
> + keep-power-in-suspend;
> + enable-sdio-wakeup;
> + vmmc-supply = <®_3v3>;
> + voltage-ranges = <3300 3300>;
> + no-1-8-v;
> + status = "okay";
> +};
> +
> +&usdhc2 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc2>;
> + pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
> + tuning-step = <2>;
> + non-removable;
> + keep-power-in-suspend;
> + enable-sdio-wakeup;
> + vmmc-supply = <®_3v3>;
> + voltage-ranges = <3300 3300>;
> + no-1-8-v;
> + status = "okay";
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog>;
> + status = "okay";
> + fsl,ext-reset-output;
> +};
>
^ permalink raw reply
* [PATCHv8 5/5] coresight: cpu-debug: Add support for Qualcomm Kryo
From: Sai Prakash Ranjan @ 2019-07-12 14:16 UTC (permalink / raw)
To: Greg Kroah-Hartman, Mathieu Poirier, Suzuki K Poulose, Leo Yan,
Alexander Shishkin, Mike Leach, Rob Herring, Bjorn Andersson,
devicetree, David Brown, Mark Rutland
Cc: Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel,
linux-kernel, linux-arm-msm, Marc Gonzalez, Sai Prakash Ranjan
In-Reply-To: <cover.1562940244.git.saiprakash.ranjan@codeaurora.org>
Add support for coresight CPU debug module on Qualcomm
Kryo CPUs. This patch adds the UCI entries for Kryo CPUs
found on MSM8996 which shares the same PIDs as ETMs.
Without this, below error is observed on MSM8996:
[ 5.429867] OF: graph: no port node found in /soc/debug@3810000
[ 5.429938] coresight-etm4x: probe of 3810000.debug failed with error -22
[ 5.435415] coresight-cpu-debug 3810000.debug: Coresight debug-CPU0 initialized
[ 5.446474] OF: graph: no port node found in /soc/debug@3910000
[ 5.448927] coresight-etm4x: probe of 3910000.debug failed with error -22
[ 5.454681] coresight-cpu-debug 3910000.debug: Coresight debug-CPU1 initialized
[ 5.487765] OF: graph: no port node found in /soc/debug@3a10000
[ 5.488007] coresight-etm4x: probe of 3a10000.debug failed with error -22
[ 5.493024] coresight-cpu-debug 3a10000.debug: Coresight debug-CPU2 initialized
[ 5.501802] OF: graph: no port node found in /soc/debug@3b10000
[ 5.512901] coresight-etm4x: probe of 3b10000.debug failed with error -22
[ 5.513192] coresight-cpu-debug 3b10000.debug: Coresight debug-CPU3 initialized
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
.../hwtracing/coresight/coresight-cpu-debug.c | 33 +++++++++----------
drivers/hwtracing/coresight/coresight-priv.h | 10 +++---
2 files changed, 21 insertions(+), 22 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c b/drivers/hwtracing/coresight/coresight-cpu-debug.c
index 2463aa7ab4f6..96544b348c27 100644
--- a/drivers/hwtracing/coresight/coresight-cpu-debug.c
+++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c
@@ -646,24 +646,23 @@ static int debug_remove(struct amba_device *adev)
return 0;
}
+static const struct amba_cs_uci_id uci_id_debug[] = {
+ {
+ /* CPU Debug UCI data */
+ .devarch = 0x47706a15,
+ .devarch_mask = 0xfff0ffff,
+ .devtype = 0x00000015,
+ }
+};
+
static const struct amba_id debug_ids[] = {
- { /* Debug for Cortex-A53 */
- .id = 0x000bbd03,
- .mask = 0x000fffff,
- },
- { /* Debug for Cortex-A57 */
- .id = 0x000bbd07,
- .mask = 0x000fffff,
- },
- { /* Debug for Cortex-A72 */
- .id = 0x000bbd08,
- .mask = 0x000fffff,
- },
- { /* Debug for Cortex-A73 */
- .id = 0x000bbd09,
- .mask = 0x000fffff,
- },
- { 0, 0 },
+ CS_AMBA_ID(0x000bbd03), /* Cortex-A53 */
+ CS_AMBA_ID(0x000bbd07), /* Cortex-A57 */
+ CS_AMBA_ID(0x000bbd08), /* Cortex-A72 */
+ CS_AMBA_ID(0x000bbd09), /* Cortex-A73 */
+ CS_AMBA_UCI_ID(0x000f0205, uci_id_debug), /* Qualcomm Kryo */
+ CS_AMBA_UCI_ID(0x000f0211, uci_id_debug), /* Qualcomm Kryo */
+ {},
};
static struct amba_driver debug_driver = {
diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index 7d401790dd7e..41ae5863104d 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -185,11 +185,11 @@ static inline int etm_writel_cp14(u32 off, u32 val) { return 0; }
}
/* coresight AMBA ID, full UCI structure: id table entry. */
-#define CS_AMBA_UCI_ID(pid, uci_ptr) \
- { \
- .id = pid, \
- .mask = 0x000fffff, \
- .data = uci_ptr \
+#define CS_AMBA_UCI_ID(pid, uci_ptr) \
+ { \
+ .id = pid, \
+ .mask = 0x000fffff, \
+ .data = (void *)uci_ptr \
}
/* extract the data value from a UCI structure given amba_id pointer. */
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCHv8 4/5] coresight: etm4x: Add ETM PIDs for SDM845 and MSM8996
From: Sai Prakash Ranjan @ 2019-07-12 14:16 UTC (permalink / raw)
To: Greg Kroah-Hartman, Mathieu Poirier, Suzuki K Poulose, Leo Yan,
Alexander Shishkin, Mike Leach, Rob Herring, Bjorn Andersson,
devicetree, David Brown, Mark Rutland
Cc: Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel,
linux-kernel, linux-arm-msm, Marc Gonzalez, Sai Prakash Ranjan
In-Reply-To: <cover.1562940244.git.saiprakash.ranjan@codeaurora.org>
Instead of overriding the peripheral id(PID) check in AMBA
by hardcoding them in DT, add the PIDs to the ETM4x driver.
Here we use Unique Component Identifier(UCI) for MSM8996
since the ETM and CPU debug module shares the same PIDs.
SDM845 does not support CPU debug module.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
drivers/hwtracing/coresight/coresight-etm4x.c | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index 7bcac8896fc1..28bcc0e58d7a 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -1192,11 +1192,15 @@ static struct amba_cs_uci_id uci_id_etm4[] = {
};
static const struct amba_id etm4_ids[] = {
- CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */
- CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */
- CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */
- CS_AMBA_ID(0x000bb959), /* Cortex-A73 */
- CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4), /* Cortex-A35 */
+ CS_AMBA_ID(0x000bb95d), /* Cortex-A53 */
+ CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */
+ CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */
+ CS_AMBA_ID(0x000bb959), /* Cortex-A73 */
+ CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */
+ CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
+ CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
+ CS_AMBA_ID(0x000bb802), /* Qualcomm Kryo 385 Cortex-A55 */
+ CS_AMBA_ID(0x000bb803), /* Qualcomm Kryo 385 Cortex-A75 */
{},
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCHv8 3/5] arm64: dts: qcom: msm8996: Add Coresight support
From: Sai Prakash Ranjan @ 2019-07-12 14:16 UTC (permalink / raw)
To: Greg Kroah-Hartman, Mathieu Poirier, Suzuki K Poulose, Leo Yan,
Alexander Shishkin, Mike Leach, Rob Herring, Bjorn Andersson,
devicetree, David Brown, Mark Rutland
Cc: Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel,
linux-kernel, linux-arm-msm, Marc Gonzalez, Sai Prakash Ranjan
In-Reply-To: <cover.1562940244.git.saiprakash.ranjan@codeaurora.org>
From: Vivek Gautam <vivek.gautam@codeaurora.org>
Enable coresight support by adding device nodes for the
available source, sinks and channel blocks on msm8996.
This also adds coresight cpu debug nodes.
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-By: Suzuki K Poulose <suzuki.poulose@arm.com>
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 434 ++++++++++++++++++++++++++
1 file changed, 434 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index 96c0a481f454..8968431e772c 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -633,6 +633,440 @@
reg = <0x300000 0x90000>;
};
+ stm@3002000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0x3002000 0x1000>,
+ <0x8280000 0x180000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ out-ports {
+ port {
+ stm_out: endpoint {
+ remote-endpoint =
+ <&funnel0_in>;
+ };
+ };
+ };
+ };
+
+ tpiu@3020000 {
+ compatible = "arm,coresight-tpiu", "arm,primecell";
+ reg = <0x3020000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ in-ports {
+ port {
+ tpiu_in: endpoint {
+ remote-endpoint =
+ <&replicator_out1>;
+ };
+ };
+ };
+ };
+
+ funnel@3021000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x3021000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ in-ports {
+ port {
+ funnel0_in: endpoint {
+ remote-endpoint =
+ <&stm_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel0_out: endpoint {
+ remote-endpoint =
+ <&merge_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ funnel@3022000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x3022000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ in-ports {
+ port {
+ funnel1_in: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ funnel1_out: endpoint {
+ remote-endpoint =
+ <&merge_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ funnel@3025000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x3025000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ merge_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ merge_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel1_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ merge_funnel_out: endpoint {
+ remote-endpoint =
+ <&etf_in>;
+ };
+ };
+ };
+ };
+
+ replicator@3026000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x3026000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ in-ports {
+ port {
+ replicator_in: endpoint {
+ remote-endpoint =
+ <&etf_out>;
+ };
+ };
+ };
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ replicator_out0: endpoint {
+ remote-endpoint =
+ <&etr_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ replicator_out1: endpoint {
+ remote-endpoint =
+ <&tpiu_in>;
+ };
+ };
+ };
+ };
+
+ etf@3027000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x3027000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ in-ports {
+ port {
+ etf_in: endpoint {
+ remote-endpoint =
+ <&merge_funnel_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ etf_out: endpoint {
+ remote-endpoint =
+ <&replicator_in>;
+ };
+ };
+ };
+ };
+
+ etr@3028000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x3028000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+ arm,scatter-gather;
+
+ in-ports {
+ port {
+ etr_in: endpoint {
+ remote-endpoint =
+ <&replicator_out0>;
+ };
+ };
+ };
+ };
+
+ debug@3810000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x3810000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ cpu = <&CPU0>;
+ };
+
+ etm@3840000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x3840000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU0>;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel0_in0>;
+ };
+ };
+ };
+ };
+
+ debug@3910000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x3910000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ cpu = <&CPU1>;
+ };
+
+ etm@3940000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x3940000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU1>;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel0_in1>;
+ };
+ };
+ };
+ };
+
+ funnel@39b0000 { /* APSS Funnel 0 */
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x39b0000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ apss_funnel0_in0: endpoint {
+ remote-endpoint = <&etm0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ apss_funnel0_in1: endpoint {
+ remote-endpoint = <&etm1_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ apss_funnel0_out: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ debug@3a10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x3a10000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ cpu = <&CPU2>;
+ };
+
+ etm@3a40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x3a40000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU2>;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel1_in0>;
+ };
+ };
+ };
+ };
+
+ debug@3b10000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0x3b10000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+
+ cpu = <&CPU3>;
+ };
+
+ etm@3b40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x3b40000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU3>;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel1_in1>;
+ };
+ };
+ };
+ };
+
+ funnel@3bb0000 { /* APSS Funnel 1 */
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x3bb0000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ apss_funnel1_in0: endpoint {
+ remote-endpoint = <&etm2_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ apss_funnel1_in1: endpoint {
+ remote-endpoint = <&etm3_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ apss_funnel1_out: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ funnel@3bc0000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x3bc0000 0x1000>;
+
+ clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ apss_merge_funnel_in0: endpoint {
+ remote-endpoint =
+ <&apss_funnel0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ apss_merge_funnel_in1: endpoint {
+ remote-endpoint =
+ <&apss_funnel1_out>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ apss_merge_funnel_out: endpoint {
+ remote-endpoint =
+ <&funnel1_in>;
+ };
+ };
+ };
+ };
+
kryocc: clock-controller@6400000 {
compatible = "qcom,apcc-msm8996";
reg = <0x6400000 0x90000>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCHv8 2/5] arm64: dts: qcom: msm8998: Add Coresight support
From: Sai Prakash Ranjan @ 2019-07-12 14:16 UTC (permalink / raw)
To: Greg Kroah-Hartman, Mathieu Poirier, Suzuki K Poulose, Leo Yan,
Alexander Shishkin, Mike Leach, Rob Herring, Bjorn Andersson,
devicetree, David Brown, Mark Rutland
Cc: Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel,
linux-kernel, linux-arm-msm, Marc Gonzalez, Sai Prakash Ranjan
In-Reply-To: <cover.1562940244.git.saiprakash.ranjan@codeaurora.org>
Enable coresight support by adding device nodes for the
available source, sinks and channel blocks on MSM8998.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
arch/arm64/boot/dts/qcom/msm8998.dtsi | 435 ++++++++++++++++++++++++++
1 file changed, 435 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi
index c13ed7aeb1e0..ad9cb5e8675d 100644
--- a/arch/arm64/boot/dts/qcom/msm8998.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi
@@ -822,6 +822,441 @@
#interrupt-cells = <0x2>;
};
+ stm@6002000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0x06002000 0x1000>,
+ <0x16280000 0x180000>;
+ reg-names = "stm-base", "stm-data-base";
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ out-ports {
+ port {
+ stm_out: endpoint {
+ remote-endpoint = <&funnel0_in7>;
+ };
+ };
+ };
+ };
+
+ funnel@6041000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x06041000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ out-ports {
+ port {
+ funnel0_out: endpoint {
+ remote-endpoint =
+ <&merge_funnel_in0>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@7 {
+ reg = <7>;
+ funnel0_in7: endpoint {
+ remote-endpoint = <&stm_out>;
+ };
+ };
+ };
+ };
+
+ funnel@6042000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x06042000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ out-ports {
+ port {
+ funnel1_out: endpoint {
+ remote-endpoint =
+ <&merge_funnel_in1>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@6 {
+ reg = <6>;
+ funnel1_in6: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_out>;
+ };
+ };
+ };
+ };
+
+ funnel@6045000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x06045000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ out-ports {
+ port {
+ merge_funnel_out: endpoint {
+ remote-endpoint =
+ <&etf_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ merge_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ merge_funnel_in1: endpoint {
+ remote-endpoint =
+ <&funnel1_out>;
+ };
+ };
+ };
+ };
+
+ replicator@6046000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0x06046000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ out-ports {
+ port {
+ replicator_out: endpoint {
+ remote-endpoint = <&etr_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ replicator_in: endpoint {
+ remote-endpoint = <&etf_out>;
+ };
+ };
+ };
+ };
+
+ etf@6047000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x06047000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ out-ports {
+ port {
+ etf_out: endpoint {
+ remote-endpoint =
+ <&replicator_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ etf_in: endpoint {
+ remote-endpoint =
+ <&merge_funnel_out>;
+ };
+ };
+ };
+ };
+
+ etr@6048000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0x06048000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+ arm,scatter-gather;
+
+ in-ports {
+ port {
+ etr_in: endpoint {
+ remote-endpoint =
+ <&replicator_out>;
+ };
+ };
+ };
+ };
+
+ etm@7840000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x07840000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU0>;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ etm@7940000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x07940000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU1>;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ etm@7a40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x07a40000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU2>;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ etm@7b40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x07b40000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU3>;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ funnel@7b60000 { /* APSS Funnel */
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x07b60000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ out-ports {
+ port {
+ apss_funnel_out: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ apss_funnel_in0: endpoint {
+ remote-endpoint =
+ <&etm0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ apss_funnel_in1: endpoint {
+ remote-endpoint =
+ <&etm1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ apss_funnel_in2: endpoint {
+ remote-endpoint =
+ <&etm2_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ apss_funnel_in3: endpoint {
+ remote-endpoint =
+ <&etm3_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ apss_funnel_in4: endpoint {
+ remote-endpoint =
+ <&etm4_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ apss_funnel_in5: endpoint {
+ remote-endpoint =
+ <&etm5_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ apss_funnel_in6: endpoint {
+ remote-endpoint =
+ <&etm6_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ apss_funnel_in7: endpoint {
+ remote-endpoint =
+ <&etm7_out>;
+ };
+ };
+ };
+ };
+
+ funnel@7b70000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0x07b70000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ out-ports {
+ port {
+ apss_merge_funnel_out: endpoint {
+ remote-endpoint =
+ <&funnel1_in6>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ apss_merge_funnel_in: endpoint {
+ remote-endpoint =
+ <&apss_funnel_out>;
+ };
+ };
+ };
+ };
+
+ etm@7c40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x07c40000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU4>;
+
+ port{
+ etm4_out: endpoint {
+ remote-endpoint = <&apss_funnel_in4>;
+ };
+ };
+ };
+
+ etm@7d40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x07d40000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU5>;
+
+ port{
+ etm5_out: endpoint {
+ remote-endpoint = <&apss_funnel_in5>;
+ };
+ };
+ };
+
+ etm@7e40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x07e40000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU6>;
+
+ port{
+ etm6_out: endpoint {
+ remote-endpoint = <&apss_funnel_in6>;
+ };
+ };
+ };
+
+ etm@7f40000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0x07f40000 0x1000>;
+
+ clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
+ clock-names = "apb_pclk", "atclk";
+
+ cpu = <&CPU7>;
+
+ port{
+ etm7_out: endpoint {
+ remote-endpoint = <&apss_funnel_in7>;
+ };
+ };
+ };
+
spmi_bus: spmi@800f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x800f000 0x1000>,
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCHv8 1/5] arm64: dts: qcom: sdm845: Add Coresight support
From: Sai Prakash Ranjan @ 2019-07-12 14:16 UTC (permalink / raw)
To: Greg Kroah-Hartman, Mathieu Poirier, Suzuki K Poulose, Leo Yan,
Alexander Shishkin, Mike Leach, Rob Herring, Bjorn Andersson,
devicetree, David Brown, Mark Rutland
Cc: Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel,
linux-kernel, linux-arm-msm, Marc Gonzalez, Sai Prakash Ranjan
In-Reply-To: <cover.1562940244.git.saiprakash.ranjan@codeaurora.org>
Add coresight components found on Qualcomm SDM845 SoC.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 451 +++++++++++++++++++++++++++
1 file changed, 451 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 4babff5f19b5..5d7e3f8e0f91 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1815,6 +1815,457 @@
clock-names = "xo";
};
+ stm@6002000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0 0x06002000 0 0x1000>,
+ <0 0x16280000 0 0x180000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ stm_out: endpoint {
+ remote-endpoint =
+ <&funnel0_in7>;
+ };
+ };
+ };
+ };
+
+ funnel@6041000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0x06041000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel0_out: endpoint {
+ remote-endpoint =
+ <&merge_funnel_in0>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@7 {
+ reg = <7>;
+ funnel0_in7: endpoint {
+ remote-endpoint = <&stm_out>;
+ };
+ };
+ };
+ };
+
+ funnel@6043000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0x06043000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel2_out: endpoint {
+ remote-endpoint =
+ <&merge_funnel_in2>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@5 {
+ reg = <5>;
+ funnel2_in5: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_out>;
+ };
+ };
+ };
+ };
+
+ funnel@6045000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0x06045000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ merge_funnel_out: endpoint {
+ remote-endpoint = <&etf_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ merge_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ merge_funnel_in2: endpoint {
+ remote-endpoint =
+ <&funnel2_out>;
+ };
+ };
+ };
+ };
+
+ replicator@6046000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0 0x06046000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ replicator_out: endpoint {
+ remote-endpoint = <&etr_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ replicator_in: endpoint {
+ remote-endpoint = <&etf_out>;
+ };
+ };
+ };
+ };
+
+ etf@6047000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x06047000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etf_out: endpoint {
+ remote-endpoint =
+ <&replicator_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ etf_in: endpoint {
+ remote-endpoint =
+ <&merge_funnel_out>;
+ };
+ };
+ };
+ };
+
+ etr@6048000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x06048000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,scatter-gather;
+
+ in-ports {
+ port {
+ etr_in: endpoint {
+ remote-endpoint =
+ <&replicator_out>;
+ };
+ };
+ };
+ };
+
+ etm@7040000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07040000 0 0x1000>;
+
+ cpu = <&CPU0>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ etm@7140000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07140000 0 0x1000>;
+
+ cpu = <&CPU1>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ etm@7240000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07240000 0 0x1000>;
+
+ cpu = <&CPU2>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ etm@7340000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07340000 0 0x1000>;
+
+ cpu = <&CPU3>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ etm@7440000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07440000 0 0x1000>;
+
+ cpu = <&CPU4>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm4_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in4>;
+ };
+ };
+ };
+ };
+
+ etm@7540000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07540000 0 0x1000>;
+
+ cpu = <&CPU5>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm5_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in5>;
+ };
+ };
+ };
+ };
+
+ etm@7640000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07640000 0 0x1000>;
+
+ cpu = <&CPU6>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm6_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in6>;
+ };
+ };
+ };
+ };
+
+ etm@7740000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07740000 0 0x1000>;
+
+ cpu = <&CPU7>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etm7_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in7>;
+ };
+ };
+ };
+ };
+
+ funnel@7800000 { /* APSS Funnel */
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0x07800000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ apss_funnel_out: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ apss_funnel_in0: endpoint {
+ remote-endpoint =
+ <&etm0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ apss_funnel_in1: endpoint {
+ remote-endpoint =
+ <&etm1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ apss_funnel_in2: endpoint {
+ remote-endpoint =
+ <&etm2_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ apss_funnel_in3: endpoint {
+ remote-endpoint =
+ <&etm3_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ apss_funnel_in4: endpoint {
+ remote-endpoint =
+ <&etm4_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ apss_funnel_in5: endpoint {
+ remote-endpoint =
+ <&etm5_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ apss_funnel_in6: endpoint {
+ remote-endpoint =
+ <&etm6_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ apss_funnel_in7: endpoint {
+ remote-endpoint =
+ <&etm7_out>;
+ };
+ };
+ };
+ };
+
+ funnel@7810000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0x07810000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ apss_merge_funnel_out: endpoint {
+ remote-endpoint =
+ <&funnel2_in5>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ apss_merge_funnel_in: endpoint {
+ remote-endpoint =
+ <&apss_funnel_out>;
+ };
+ };
+ };
+ };
+
sdhc_2: sdhci@8804000 {
compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5";
reg = <0 0x08804000 0 0x1000>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCHv8 0/5] Add coresight support for SDM845, MSM8998 and MSM8996
From: Sai Prakash Ranjan @ 2019-07-12 14:16 UTC (permalink / raw)
To: Greg Kroah-Hartman, Mathieu Poirier, Suzuki K Poulose, Leo Yan,
Alexander Shishkin, Mike Leach, Rob Herring, Bjorn Andersson,
devicetree, David Brown, Mark Rutland
Cc: Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel,
linux-kernel, linux-arm-msm, Marc Gonzalez, Sai Prakash Ranjan
This patch series adds support for coresight on SDM845, MSM8998, and MSM8996.
* Patch 1 adds device tree nodes for SDM845 coresight components.
* Patch 2 adds device tree nodes for MSM8998 coresight components.
* Patch 3 adds device tree nodes for MSM8996 coresight components.
* Patch 4 adds ETM PIDs for SDM845 and MSM8996.
* Patch 5 adds coresight CPU debug module for Qualcomm Kryo.
All the previous dependencies are now merged.
This patch series has been tested on SDM845 MTP and MSM8996
based Dragonboard 820c and MSM8998 MTP.
v8:
* Change to clocks instead of power domain for SDM845.
* Fix compilation with uci_id_debug struct changed to const.
* Rebase on top of linux-next.
v7:
* Change uci_id_debug struct to const.
* Update the subject as suggested by Suzuki.
v6:
* Update the UCI table with the new macro introduced by
Mike.
* Rebase on top of coresight-next and provide a tree with
all the dependent patches applied.
v5:
* Added coresight support for MSM8998.
* Added ETM PIDs for SDM845 and MSM8996 as suggested
by Suzuki.
* Added UCI table for Coresight CPU debug module.
v4:
* Mask out the minor version as suggested by Mathieu.
* Added the dependent patch description in patch 1.
v3:
* Added arm,scatter-gather property as suggested by Suzuki.
v2:
* Added coresight support for msm8996 based on Vivek's patch.
Cleaned up and added coresight cpu debug nodes for msm8996.
* Merged coresight dtsi file into sdm845.dtsi as suggested by Bjorn
* Addressed Mathieu's feedback about masking the minor version in
etm4_arch_supported() and added a comment for reason to bypass
the AMBA bus discovery method.
Sai Prakash Ranjan (4):
arm64: dts: qcom: sdm845: Add Coresight support
arm64: dts: qcom: msm8998: Add Coresight support
coresight: etm4x: Add ETM PIDs for SDM845 and MSM8996
coresight: cpu-debug: Add support for Qualcomm Kryo
Vivek Gautam (1):
arm64: dts: qcom: msm8996: Add Coresight support
arch/arm64/boot/dts/qcom/msm8996.dtsi | 434 +++++++++++++++++
arch/arm64/boot/dts/qcom/msm8998.dtsi | 435 +++++++++++++++++
arch/arm64/boot/dts/qcom/sdm845.dtsi | 451 ++++++++++++++++++
.../hwtracing/coresight/coresight-cpu-debug.c | 33 +-
drivers/hwtracing/coresight/coresight-etm4x.c | 14 +-
drivers/hwtracing/coresight/coresight-priv.h | 10 +-
6 files changed, 1350 insertions(+), 27 deletions(-)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply
* [PATCH] ARM: dts: imx6ul-kontron-ul2: Add Exceet/Kontron iMX6-UL2 SoM
From: Krzysztof Kozlowski @ 2019-07-12 14:12 UTC (permalink / raw)
To: Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, devicetree, linux-kernel, linux-arm-kernel
Cc: frieder.schrempf, Krzysztof Kozlowski
Add support for iMX6-UL2 modules from Kontron Electronics GmbH (before
acquisition: Exceet Electronics) and evalkit boards based on it:
1. i.MX6 UL System-on-Module, a 25x25 mm solderable module (LGA pads and
pin castellations) with 256 MB RAM, 1 MB NOR-Flash, 256 MB NAND and
other interfaces,
1. UL2 evalkit, w/wo eMMC, without display,
2. UL2 evalkit with 4.3" display,
3. UL2 evalkit with 5.0" display.
This includes device nodes for unsupported displays (Admatec
T043C004800272T2A and T070P133T0S301).
The work is based on Exceet source code (GPLv2) with numerous changes:
1. Reorganize files,
2. Rename Exceet -> Kontron,
3. Fix coding style errors,
4. Fix DTC warnings,
5. Extend compatibles so eval boards inherit the SoM compatible,
6. Use defines instead of GPIO flag values,
7. Adjust operating points of CPU0,
8. Sort nodes alphabetically.
In downstream BSP the Exceet name still appears in multiple places
therefore I left it in the model names.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/Makefile | 3 +
arch/arm/boot/dts/imx6ul-kontron-ul2-43.dts | 123 +++++
arch/arm/boot/dts/imx6ul-kontron-ul2-50.dts | 123 +++++
arch/arm/boot/dts/imx6ul-kontron-ul2-som.dtsi | 152 ++++++
arch/arm/boot/dts/imx6ul-kontron-ul2.dts | 435 ++++++++++++++++++
5 files changed, 836 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ul-kontron-ul2-43.dts
create mode 100644 arch/arm/boot/dts/imx6ul-kontron-ul2-50.dts
create mode 100644 arch/arm/boot/dts/imx6ul-kontron-ul2-som.dtsi
create mode 100644 arch/arm/boot/dts/imx6ul-kontron-ul2.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9159fa2cea90..3431bb44fb5d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -569,6 +569,9 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-geam.dtb \
imx6ul-isiot-emmc.dtb \
imx6ul-isiot-nand.dtb \
+ imx6ul-kontron-ul2.dtb \
+ imx6ul-kontron-ul2-43.dtb \
+ imx6ul-kontron-ul2-50.dtb \
imx6ul-liteboard.dtb \
imx6ul-opos6uldev.dtb \
imx6ul-pico-hobbit.dtb \
diff --git a/arch/arm/boot/dts/imx6ul-kontron-ul2-43.dts b/arch/arm/boot/dts/imx6ul-kontron-ul2-43.dts
new file mode 100644
index 000000000000..a2b68ba14765
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-kontron-ul2-43.dts
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6ul-kontron-ul2.dts"
+
+/ {
+ model = "Exceet/Kontron iMX6 UL-2 S 43";
+ compatible = "kontron,imx6ul-ul2-s-43", "kontron,imx6ul-ul2-s",
+ "kontron,imx6ul-ul2-som", "fsl,imx6ul";
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm7 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+ };
+
+ panel {
+ compatible = "admatec,t043c004800272t2a";
+ backlight = <&backlight>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
+};
+
+&i2c4 {
+ gt911@5d {
+ compatible = "goodix,gt928";
+ reg = <0x5d>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_cap_touch>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <6 8>;
+ reset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
+ irq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&iomuxc {
+ pinctrl_lcdif_dat: lcdifdatgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
+ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
+ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
+ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
+ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
+ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
+ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
+ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
+ MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
+ MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
+ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
+ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
+ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
+ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
+ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
+ MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
+ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
+ MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
+ MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
+ MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
+ MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
+ MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
+ MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
+ >;
+ };
+
+ pinctrl_lcdif_ctrl: lcdifctrlgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
+ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
+ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
+ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
+ MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79
+ >;
+ };
+
+ pinctrl_cap_touch: captouchgrp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* Touch Interrupt */
+ MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 /* Touch Reset */
+ MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Touch Wake */
+ >;
+ };
+
+ pinctrl_pwm7: pwm7grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x110b0
+ >;
+ };
+};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif_dat
+ &pinctrl_lcdif_ctrl>;
+ status = "okay";
+
+ port {
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+};
+
+&pwm7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm7>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ul-kontron-ul2-50.dts b/arch/arm/boot/dts/imx6ul-kontron-ul2-50.dts
new file mode 100644
index 000000000000..61017020e02f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-kontron-ul2-50.dts
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6ul-kontron-ul2.dts"
+
+/ {
+ model = "Exceet/Kontron iMX6 UL-2 S 50";
+ compatible = "kontron,imx6ul-ul2-s-50", "kontron,imx6ul-ul2-s",
+ "kontron,imx6ul-ul2-som", "fsl,imx6ul";
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm7 0 5000000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+ };
+
+ panel {
+ compatible = "admatec,t070p133t0s301";
+ backlight = <&backlight>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
+};
+
+&i2c4 {
+ gt911@5d {
+ compatible = "goodix,gt928";
+ reg = <0x5d>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_cap_touch>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <6 8>;
+ reset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
+ irq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&iomuxc {
+ pinctrl_lcdif_dat: lcdifdatgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
+ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
+ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
+ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
+ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
+ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
+ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
+ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
+ MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
+ MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
+ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
+ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
+ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
+ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
+ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
+ MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
+ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
+ MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
+ MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
+ MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
+ MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
+ MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
+ MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
+ >;
+ };
+
+ pinctrl_lcdif_ctrl: lcdifctrlgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
+ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
+ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
+ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
+ MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x79
+ >;
+ };
+
+ pinctrl_cap_touch: captouchgrp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* Touch Interrupt */
+ MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 /* Touch Reset */
+ MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Touch Wake */
+ >;
+ };
+
+ pinctrl_pwm7: pwm7grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x110b0
+ >;
+ };
+};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif_dat
+ &pinctrl_lcdif_ctrl>;
+ status = "okay";
+
+ port {
+ display_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+};
+
+&pwm7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm7>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ul-kontron-ul2-som.dtsi b/arch/arm/boot/dts/imx6ul-kontron-ul2-som.dtsi
new file mode 100644
index 000000000000..26b6615cf839
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-kontron-ul2-som.dtsi
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6ul.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Exceet/Kontron iMX6 UL-2 SOM";
+ compatible = "kontron,imx6ul-ul2-som", "fsl,imx6ul";
+
+ memory@80000000 {
+ reg = <0x80000000 0x10000000>;
+ };
+};
+
+&cpu0 {
+ clock-frequency = <528000000>;
+ operating-points = <
+ /* kHz uV */
+ 528000 1175000
+ 396000 1025000
+ 198000 950000
+ >;
+ fsl,soc-operating-points = <
+ /* KHz uV */
+ 528000 1175000
+ 396000 1175000
+ 198000 1175000
+ >;
+};
+
+&ecspi2 {
+ cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi2>;
+ status = "okay";
+
+ flash: mx25v80@0 {
+ compatible = "macronix,mx25v8035f", "jedec,spi-nor";
+ spi-max-frequency = <50000000>;
+ reg = <0>;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy1>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "rmii-ref";
+ };
+ };
+};
+
+&fec2 {
+ phy-mode = "rmii";
+ status = "disabled";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reset_out>;
+
+ pinctrl_reset_out: rstoutgrp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
+ >;
+ };
+
+ pinctrl_ecspi2: ecspi2grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1
+ MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1
+ MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1
+ MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1
+ >;
+ };
+
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009
+ >;
+ };
+
+ pinctrl_enet1_mdio: enet1mdiogrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ >;
+ };
+
+ pinctrl_qspi: qspigrp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
+ MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
+ MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
+ MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
+ MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
+ MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
+ >;
+ };
+};
+
+&qspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "okay";
+
+ flash0: w25m02gv@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "spi-nand";
+ spi-max-frequency = <108000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ reg = <0>;
+
+ partition@0 {
+ label = "ubi1";
+ reg = <0x00000000 0x08000000>;
+ };
+
+ partition@8000000 {
+ label = "ubi2";
+ reg = <0x08000000 0x08000000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ul-kontron-ul2.dts b/arch/arm/boot/dts/imx6ul-kontron-ul2.dts
new file mode 100644
index 000000000000..6d394a97712b
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-kontron-ul2.dts
@@ -0,0 +1,435 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2017 exceet electronics GmbH
+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx6ul-kontron-ul2-som.dtsi"
+
+/ {
+ model = "Exceet/Kontron iMX6 UL-2 S";
+ compatible = "kontron,imx6ul-ul2-s", "kontron,imx6ul-ul2-som",
+ "fsl,imx6ul";
+
+ pwm-beeper {
+ compatible = "pwm-beeper";
+ pwms = <&pwm8 0 5000>;
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_leds>;
+
+ led1 {
+ label = "debug-led1";
+ gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ linux,default-trigger = "heartbeat";
+ };
+
+ led2 {
+ label = "debug-led2";
+ gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+
+ led3 {
+ label = "debug-led3";
+ gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ default-state = "off";
+ };
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_3v3: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_vref_adc: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "vref-adc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_usb_otg1_vbus: regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "usb_otg1_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+ };
+
+};
+
+&adc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc1>;
+ num-channels = <3>;
+ vref-supply = <®_vref_adc>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+
+&ecspi1 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1>;
+ status = "okay";
+
+ fram@0 {
+ compatible = "atmel,at25";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ spi-cpha;
+ spi-cpol;
+ pagesize = <1>;
+ size = <8192>;
+ address-width = <16>;
+ };
+};
+
+&fec1 {
+ pinctrl-0 = <&pinctrl_enet1>;
+ /delete-node/ mdio;
+};
+
+&fec2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy2>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ reg = <1>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET_REF>;
+ clock-names = "rmii-ref";
+ };
+
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+ micrel,led-mode = <0>;
+ clocks = <&clks IMX6UL_CLK_ENET2_REF>;
+ clock-names = "rmii-ref";
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+
+ rtc@32 {
+ compatible = "epson,rx8900";
+ reg = <0x32>;
+ };
+};
+
+&iomuxc {
+ pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0
+ >;
+ };
+
+ pinctrl_gpio: gpio {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
+ MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
+ MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
+ MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
+ >;
+ };
+
+ pinctrl_usbotg1: usbotg1 {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
+ >;
+ };
+
+ pinctrl_gpio_leds: gpio_leds {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
+ MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
+ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
+ >;
+ };
+
+ /* FRAM */
+ pinctrl_ecspi1: ecspi1grp-1 {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
+ MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
+ MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
+ MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
+ >;
+ };
+
+ pinctrl_enet2_mdio: enet2mdiogrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
+ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp{
+ fsl,pins = <
+ MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
+ MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
+ >;
+ };
+
+ pinctrl_pwm8: pwm8grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
+ MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
+ MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
+ /*
+ * mux unused RTS to make sure it doesn't cause
+ * any interrupts when it is undefined
+ */
+ MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart3: uart3grp {
+ fsl,pins = <
+ MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
+ MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
+ MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
+ MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
+ MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
+ MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
+ MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
+ MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
+ MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
+ MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
+ >;
+ };
+
+ pinctrl_adc1: adc1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
+ MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
+ >;
+ };
+};
+
+&pwm8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm8>;
+ status = "okay";
+};
+
+&snvs_poweroff {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ linux,rs485-enabled-at-boot-time;
+ rs485-rx-during-tx;
+ rs485-rts-active-low;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart4>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1>;
+ dr_mode = "otg";
+ status = "okay";
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+ vbus-supply = <®_usb_otg1_vbus>;
+};
+
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
+ keep-power-in-suspend;
+ enable-sdio-wakeup;
+ vmmc-supply = <®_3v3>;
+ voltage-ranges = <3300 3300>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ tuning-step = <2>;
+ non-removable;
+ keep-power-in-suspend;
+ enable-sdio-wakeup;
+ vmmc-supply = <®_3v3>;
+ voltage-ranges = <3300 3300>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ status = "okay";
+ fsl,ext-reset-output;
+};
--
2.17.1
^ permalink raw reply related
* Re: [PATCH] arm: dts: imx6qdl: add gpio expander pca9535
From: Marco Felsch @ 2019-07-12 13:55 UTC (permalink / raw)
To: Gilles DOFFE
Cc: linux-kernel, linux-arm-kernel, devicetree, mark.rutland,
festevam, s.hauer, robh+dt, linux-imx, kernel, shawnguo
In-Reply-To: <20190712124522.571-1-gilles.doffe@savoirfairelinux.com>
Hi,
On 19-07-12 14:45, Gilles DOFFE wrote:
> The pca9535 gpio expander is present on the Rex baseboard, but missing
> from the dtsi.
>
> Add the new gpio controller and the associated interrupt line
> MX6QDL_PAD_NANDF_CS3__GPIO6_IO16.
>
> Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
> ---
> arch/arm/boot/dts/imx6qdl-rex.dtsi | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/imx6qdl-rex.dtsi
> index 97f1659144ea..d5324c6761c1 100644
> --- a/arch/arm/boot/dts/imx6qdl-rex.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-rex.dtsi
> @@ -136,6 +136,19 @@
> compatible = "atmel,24c02";
> reg = <0x57>;
> };
> +
> + gpio8: pca9535@27 {
Just a nitpick, I would change that to
pca9535: gpio8@27 {
Regards,
Marco
> + compatible = "nxp,pca9535";
> + reg = <0x27>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pca9535>;
> + interrupt-parent = <&gpio6>;
> + interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> };
>
> &i2c3 {
> @@ -237,6 +250,12 @@
> >;
> };
>
> + pinctrl_pca9535: pca9535 {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x00017059
> + >;
> + };
> +
> pinctrl_uart1: uart1grp {
> fsl,pins = <
> MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
> --
> 2.19.1
>
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* Re: [PATCH 0/3] Add HDMI audio support to the HiHope RZ/G2[MN]
From: Geert Uytterhoeven @ 2019-07-12 13:54 UTC (permalink / raw)
To: Fabrizio Castro
Cc: Geert Uytterhoeven, Rob Herring, Mark Rutland, Simon Horman,
Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, xu_shunji
In-Reply-To: <1562333979-28516-1-git-send-email-fabrizio.castro@bp.renesas.com>
Hi Fabrizio,
On Fri, Jul 5, 2019 at 3:39 PM Fabrizio Castro
<fabrizio.castro@bp.renesas.com> wrote:
> this series adds HDMI audio support to the HiHope RZ/G2[MN].
>
> Thanks,
> Fab
>
> Fabrizio Castro (3):
> arm64: dts: renesas: r8a774a1: Use extended audio dmac register
> arm64: dts: renesas: r8a774a1: Add SSIU support for sound
> arm64: dts: renesas: hihope-common: Add HDMI audio support
Thanks, I have applied and queued for v5.4 the first two patches.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH] Input: atmel_mxt_ts - allow specification of config name
From: Lucas Stach @ 2019-07-12 13:53 UTC (permalink / raw)
To: Nick Dyer, Dmitry Torokhov, Rob Herring
Cc: linux-input, devicetree, kernel, patchwork-lst, Chris Healy
From: Nick Dyer <nick@shmanahar.org>
Some systems require different touchscreen configurations depending on the
populated touchscreen. To allow different configs to co-exist in the file
system we need a way to tell the driver, which config should be loaded.
Signed-off-by: Nick Dyer <nick@shmanahar.org>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
lst:
- switch to property name to not use underscore
- Add more elaborate commit message
---
Documentation/devicetree/bindings/input/atmel,maxtouch.txt | 3 +++
drivers/input/touchscreen/atmel_mxt_ts.c | 6 +++++-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/input/atmel,maxtouch.txt b/Documentation/devicetree/bindings/input/atmel,maxtouch.txt
index c88919480d37..dd2c278824b8 100644
--- a/Documentation/devicetree/bindings/input/atmel,maxtouch.txt
+++ b/Documentation/devicetree/bindings/input/atmel,maxtouch.txt
@@ -31,6 +31,9 @@ Optional properties for main touchpad device:
- reset-gpios: GPIO specifier for the touchscreen's reset pin (active low)
+- atmel,cfg-name: Provide name of configuration file in OBP_RAW format. This
+ will be downloaded from the firmware loader on probe to the device.
+
Example:
touch@4b {
diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c b/drivers/input/touchscreen/atmel_mxt_ts.c
index 19378f200c63..c37c5ab8d847 100644
--- a/drivers/input/touchscreen/atmel_mxt_ts.c
+++ b/drivers/input/touchscreen/atmel_mxt_ts.c
@@ -318,6 +318,7 @@ struct mxt_data {
struct t7_config t7_cfg;
struct mxt_dbg dbg;
struct gpio_desc *reset_gpio;
+ const char *cfg_name;
/* Cached parameters from object table */
u16 T5_address;
@@ -2151,7 +2152,8 @@ static int mxt_initialize(struct mxt_data *data)
if (error)
return error;
- error = request_firmware_nowait(THIS_MODULE, true, MXT_CFG_NAME,
+ error = request_firmware_nowait(THIS_MODULE, true,
+ data->cfg_name ? : MXT_CFG_NAME,
&client->dev, GFP_KERNEL, data,
mxt_config_cb);
if (error) {
@@ -3015,6 +3017,8 @@ static int mxt_parse_device_properties(struct mxt_data *data)
data->t19_num_keys = n_keys;
}
+ device_property_read_string(dev, "atmel,cfg-name", &data->cfg_name);
+
return 0;
}
--
2.20.1
^ permalink raw reply related
* Re: [PATCH 0/3] Add WLAN/BT support
From: Geert Uytterhoeven @ 2019-07-12 13:52 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Mark Rutland, Simon Horman, Geert Uytterhoeven,
Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Fabrizio Castro
In-Reply-To: <1562321720-18735-1-git-send-email-biju.das@bp.renesas.com>
Hi Biju,
On Fri, Jul 5, 2019 at 12:20 PM Biju Das <biju.das@bp.renesas.com> wrote:
> This series adds WLAN/BT support for the HiHope RZ/G2M platform.
>
> This patchset is based on renesas devel branch.
>
> Biju Das (3):
> arm64: dts: renesas: hihope-common: Add PCA9654 I/O expander
> arm64: dts: renesas: hihope-common: Add BT support
> arm64: dts: renesas: hihope-common: Add WLAN support
Thanks, applied and queued for v5.4.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox