* [PATCH v1 11/50] clk: samsung: add IDs to UART clocks in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
Add IDs to MUXes for UART to manage them from DT.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index c13f34d3d9a1..7bf74401c4e7 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -768,10 +768,10 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
/* PERIC Block */
- MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
- MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
- MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
- MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
+ MUX(CLK_MOUT_UART0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
+ MUX(CLK_MOUT_UART1, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
+ MUX(CLK_MOUT_UART2, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
+ MUX(CLK_MOUT_UART3, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
--
2.17.1
^ permalink raw reply related
* [PATCH v1 10/50] clk: samsung: change ACLK100_NOC clocks definitions Exynos5x
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The ACLK100_NOC has different topology in Exynos5420 and 5422/5800. In
Exynos5420 this clock divider has 3 bits while in 5422/5800 has 4 bits.
The patch adds needed dividers in the exynos5800_div_clks, updates
exynos5x_div_clks and exynos5420_div_clks properly. It also adds IDs to
manage clocks from DT.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 6164d0ca75e0..c13f34d3d9a1 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -471,7 +471,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
SRC_TOP0, 4, 3),
MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group2_5800_p,
SRC_TOP0, 16, 3),
- MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
+ MUX(CLK_MOUT_ACLK100_NOC, "mout_aclk100_noc", mout_group1_5800_p,
+ SRC_TOP0, 20, 2),
MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
@@ -534,6 +535,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
"mout_aclk400_wcore", DIV_TOP0, 16, 3),
+ DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
+ DIV_TOP0, 20, 4),
DIV(CLK_DOUT_ACLK266_ISP, "dout_aclk266_isp", "mout_aclk266_isp",
DIV_TOP8, 12, 3),
DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
@@ -569,7 +572,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
SRC_TOP0, 4, 2),
MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group1_p,
SRC_TOP0, 16, 2),
- MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
+ MUX(CLK_MOUT_ACLK100_NOC, "mout_aclk100_noc", mout_group1_p,
+ SRC_TOP0, 20, 2),
MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
MUX(0, "mout_aclk333_432_isp", mout_group4_p,
@@ -600,6 +604,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
"mout_aclk400_wcore", DIV_TOP0, 16, 3),
+ DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
+ DIV_TOP0, 20, 3),
};
static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
@@ -798,8 +804,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
DIV_TOP0, 8, 3),
DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2",
DIV_TOP0, 12, 3),
- DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
- DIV_TOP0, 20, 3),
DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys",
DIV_TOP0, 24, 3),
DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys",
--
2.17.1
^ permalink raw reply related
* [PATCH v1 09/50] clk: samsung: add IDs to FSYS clocks in Exynos5x
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
Add IDs to MUXes of ACLK200_FSYS, ACLK_FSYS2, PCLK200_FSYS to manage them
from DT.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 5f251279b4c8..6164d0ca75e0 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -622,9 +622,12 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
- MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
- MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
- MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
+ MUX(CLK_MOUT_ACLK200_FSYS2, "mout_aclk200_fsys2", mout_group1_p,
+ SRC_TOP0, 12, 2),
+ MUX(CLK_MOUT_PCLK200_FSYS, "mout_pclk200_fsys", mout_group1_p,
+ SRC_TOP0, 24, 2),
+ MUX(CLK_MOUT_ACLK200_FSYS, "mout_aclk200_fsys", mout_group1_p,
+ SRC_TOP0, 28, 2),
MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
--
2.17.1
^ permalink raw reply related
* [PATCH v1 08/50] clk: samsung: change aclk266_isp clocks definitions Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The ACLK266_ISP has different topology in Exynos5420 and 5422/5800. In
Exynos5420 this clock does not have dedicated MUX which chooses PLL instead
it takes the clock from 2-level mux from ACLK266. In Exynos5422 there is a
dedicated clock tree and the PLL can be chosen. The patch adds needed
MUXes in the exynos5800_mux_cloks, updates exynos5x_mux_clks and
exynos5420_mux_clks properly. It also adds IDs to mange these clocks from
DT.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 9d54856dbcda..5f251279b4c8 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -432,6 +432,10 @@ PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" };
PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_sclk_dpll",
"mout_sclk_mpll", "ff_dout_spll2",
"mout_sclk_spll", "mout_sclk_epll"};
+PNAME(mout_group17_5800_p) = { "dout_aclk266_isp", "dout_sclk_sw" };
+PNAME(mout_group18_5800_p) = { "dout_osc_div", "mout_sw_aclk266_isp" };
+PNAME(mout_group19_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
+ "mout_sclk_mpll", "mout_sclk_ipll"};
/* fixed rate clocks generated outside the soc */
static struct samsung_fixed_rate_clock
@@ -494,6 +498,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
+ MUX(CLK_MOUT_ACLK266_ISP, "mout_aclk266_isp", mout_group19_5800_p,
+ SRC_TOP8, 12, 2),
MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
@@ -501,6 +507,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,
SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0),
+ MUX(CLK_MOUT_USER_ACLK266_ISP, "mout_user_aclk266_isp",
+ mout_group18_5800_p, SRC_TOP9, 12, 1),
MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
SRC_TOP9, 16, 1),
MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
@@ -510,6 +518,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
SRC_TOP9, 28, 1),
+ MUX(CLK_MOUT_SW_ACLK266_ISP, "mout_sw_aclk266_isp", mout_group17_5800_p,
+ SRC_TOP13, 12, 1),
MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
SRC_TOP13, 20, 1),
@@ -524,6 +534,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
"mout_aclk400_wcore", DIV_TOP0, 16, 3),
+ DIV(CLK_DOUT_ACLK266_ISP, "dout_aclk266_isp", "mout_aclk266_isp",
+ DIV_TOP8, 12, 3),
DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
DIV_TOP8, 16, 3),
DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
@@ -574,6 +586,9 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
+ MUX(CLK_MOUT_USER_ACLK266_ISP, "mout_user_aclk266_isp",
+ mout_user_aclk266_isp_p, SRC_TOP4, 16, 1),
+
MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
mout_group5_5800_p, SRC_TOP7, 16, 2),
MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
@@ -641,8 +656,6 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
SRC_TOP4, 8, 1),
MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
SRC_TOP4, 12, 1),
- MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
- SRC_TOP4, 16, 1),
MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
--
2.17.1
^ permalink raw reply related
* [PATCH v1 07/50] clk: samsung: add IDs to ACLK266_G2D clocks in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene, myungjoo.ham,
s.nawrocki, m.szyprowski
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
Add IDs to MUXes of ACLK266_G2D to manage them from DT.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 9b4a1d81f708..9d54856dbcda 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -478,7 +478,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2),
- MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2),
+ MUX(CLK_MOUT_ACLK266_G2D, "mout_aclk266_g2d", mout_group5_5800_p,
+ SRC_TOP2, 12, 2),
MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2),
MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
@@ -567,7 +568,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
- MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
+ MUX(CLK_MOUT_ACLK266_G2D, "mout_aclk266_g2d", mout_group1_p,
+ SRC_TOP2, 12, 2),
MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
--
2.17.1
^ permalink raw reply related
* [PATCH v1 06/50] clk: samsung: add IDs to ACLK266 clocks in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene, myungjoo.ham,
s.nawrocki, m.szyprowski
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
Add IDs to MUXes related to ACLK266 for managing them from DT.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 74276875bc3e..9b4a1d81f708 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -472,7 +472,8 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
- MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
+ MUX(CLK_MOUT_ACLK266, "mout_aclk266", mout_group5_5800_p,
+ SRC_TOP1, 20, 2),
MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
@@ -561,7 +562,7 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
MUX(0, "mout_aclk333_432_isp", mout_group4_p,
SRC_TOP1, 4, 2),
MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
- MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
+ MUX(CLK_MOUT_ACLK266, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
--
2.17.1
^ permalink raw reply related
* [PATCH v1 05/50] clk: samsung: add IDs to aclk400_isp in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
Add clock IDs to MUXes related to ACLK400_ISP for managing them from DT
devices.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 8f1d39cb2f1e..74276875bc3e 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -461,7 +461,8 @@ static const struct samsung_fixed_factor_clock
};
static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
- MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
+ MUX(CLK_MOUT_ACLK400_ISP, "mout_aclk400_isp", mout_group3_5800_p,
+ SRC_TOP0, 0, 3),
MUX(CLK_MOUT_ACLK400_MSCL, "mout_aclk400_mscl", mout_group3_5800_p,
SRC_TOP0, 4, 3),
MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group2_5800_p,
@@ -548,7 +549,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
TOP_SPARE2, 4, 1),
- MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
+ MUX(CLK_MOUT_ACLK400_ISP, "mout_aclk400_isp", mout_group1_p,
+ SRC_TOP0, 0, 2),
MUX(CLK_MOUT_ACLK400_MSCL, "mout_aclk400_mscl", mout_group1_p,
SRC_TOP0, 4, 2),
MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group1_p,
@@ -670,8 +672,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
- MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
- SRC_TOP10, 0, 1),
+ MUX(CLK_MOUT_SW_ACLK400_ISP, "mout_sw_aclk400_isp",
+ mout_sw_aclk400_isp_p, SRC_TOP10, 0, 1),
MUX(CLK_MOUT_SW_ACLK400_MSCL, "mout_sw_aclk400_mscl",
mout_sw_aclk400_mscl_p, SRC_TOP10, 4, 1),
MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
--
2.17.1
^ permalink raw reply related
* [PATCH v1 04/50] clk: samsung: add IDs to manage aclk400_mscl in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene, myungjoo.ham,
s.nawrocki, m.szyprowski
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
Add needed IDs to MUXes which are used from DT to properly set clock
hierarchy.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 361ee53fc9fc..8f1d39cb2f1e 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -462,7 +462,8 @@ static const struct samsung_fixed_factor_clock
static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
- MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
+ MUX(CLK_MOUT_ACLK400_MSCL, "mout_aclk400_mscl", mout_group3_5800_p,
+ SRC_TOP0, 4, 3),
MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group2_5800_p,
SRC_TOP0, 16, 3),
MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
@@ -548,7 +549,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
TOP_SPARE2, 4, 1),
MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
- MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
+ MUX(CLK_MOUT_ACLK400_MSCL, "mout_aclk400_mscl", mout_group1_p,
+ SRC_TOP0, 4, 2),
MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group1_p,
SRC_TOP0, 16, 2),
MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
@@ -670,8 +672,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
SRC_TOP10, 0, 1),
- MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
- SRC_TOP10, 4, 1),
+ MUX(CLK_MOUT_SW_ACLK400_MSCL, "mout_sw_aclk400_mscl",
+ mout_sw_aclk400_mscl_p, SRC_TOP10, 4, 1),
MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
SRC_TOP10, 8, 1),
MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
--
2.17.1
^ permalink raw reply related
* [PATCH v1 03/50] clk: samsung: change parent of dout_aclk400_wcore in Exynos5420
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
Change parent of dout_aclk400_wcore to mout_aclk400_wcore which reflects
topology described in the RM.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index d353870e7fda..361ee53fc9fc 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -577,7 +577,7 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
- "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),
+ "mout_aclk400_wcore", DIV_TOP0, 16, 3),
};
static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
--
2.17.1
^ permalink raw reply related
* [PATCH v1 02/50] clk: samsung: add IDs for Exynos5420 NoC clocks
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
The patch adds NoC WCORE clock IDs needed used for changing parent of the
main NoC clock from the DT device.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 16ad498e3f3f..d353870e7fda 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -463,7 +463,8 @@ static const struct samsung_fixed_factor_clock
static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
- MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
+ MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group2_5800_p,
+ SRC_TOP0, 16, 3),
MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
@@ -548,7 +549,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
- MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
+ MUX(CLK_MOUT_ACLK400_WCORE, "mout_aclk400_wcore", mout_group1_p,
+ SRC_TOP0, 16, 2),
MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
@@ -674,8 +676,8 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
SRC_TOP10, 8, 1),
MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
SRC_TOP10, 12, 1),
- MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
- SRC_TOP10, 16, 1),
+ MUX(CLK_MOUT_SW_ACLK400_WCORE, "mout_sw_aclk400_wcore",
+ mout_sw_aclk400_wcore_p, SRC_TOP10, 16, 1),
MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
SRC_TOP10, 20, 1),
MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
--
2.17.1
^ permalink raw reply related
* [PATCH v1 01/50] clk: samsung: add new IDs for Exynos5420 clocks
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mark.rutland, cw00.choi, b.zolnierkie, sboyd, mturquette, krzk,
Lukasz Luba, a.hajda, robh+dt, kyungmin.park, kgene, myungjoo.ham,
s.nawrocki, m.szyprowski
In-Reply-To: <20190715124417.4787-1-l.luba@partner.samsung.com>
There is a need of new IDs which will be used for modeling proper hierarchy
in the Exynos54xx SoCs. Previous implementation rely on bootloader
settings, which are not configuring properly some clocks.
These IDs provide interface to set proper parents.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
include/dt-bindings/clock/exynos5420.h | 27 +++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 02d5ac469a3d..c37a28eeaf7e 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -230,6 +230,30 @@
#define CLK_MOUT_USER_MAU_EPLL 659
#define CLK_MOUT_SCLK_SPLL 660
#define CLK_MOUT_MX_MSPLL_CCORE_PHY 661
+#define CLK_MOUT_ACLK400_WCORE 662
+#define CLK_MOUT_SCLK_DPLL 663
+#define CLK_MOUT_ACLK100_NOC 664
+#define CLK_MOUT_ACLK200_FSYS2 665
+#define CLK_MOUT_PCLK200_FSYS 666
+#define CLK_MOUT_ACLK200_FSYS 667
+#define CLK_MOUT_ACLK400_ISP 668
+#define CLK_MOUT_ACLK400_MSCL 669
+#define CLK_MOUT_SCLK_MPLL 700
+#define CLK_MOUT_ACLK266 701
+#define CLK_MOUT_UART0 702
+#define CLK_MOUT_UART1 703
+#define CLK_MOUT_UART2 704
+#define CLK_MOUT_UART3 705
+#define CLK_MOUT_SCLK_CPLL 706
+#define CLK_MOUT_PWM 707
+#define CLK_MOUT_ACLK266_G2D 708
+#define CLK_MOUT_SW_ACLK400_WCORE 709
+#define CLK_MOUT_SW_ACLK400_MSCL 710
+#define CLK_MOUT_SW_ACLK400_ISP 711
+#define CLK_MOUT_SW_ACLK266_ISP 712
+#define CLK_MOUT_USER_ACLK266_ISP 713
+#define CLK_MOUT_ACLK266_ISP 714
+#define CLK_MOUT_MMC0 715
/* divider clocks */
#define CLK_DOUT_PIXEL 768
@@ -264,8 +288,9 @@
#define CLK_FF_DOUT_SPLL2 797
#define CLK_DOUT_PCLK_DREX0 798
#define CLK_DOUT_PCLK_DREX1 799
+#define CLK_DOUT_ACLK266_ISP 800
/* must be greater than maximal clock id */
-#define CLK_NR_CLKS 800
+#define CLK_NR_CLKS 801
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
--
2.17.1
^ permalink raw reply related
* [PATCH v1 00/50] Exynos5x clocks and buses changes
From: Lukasz Luba @ 2019-07-15 12:43 UTC (permalink / raw)
To: devicetree, linux-kernel, linux-arm-kernel, linux-samsung-soc,
linux-clk
Cc: mturquette, sboyd, b.zolnierkie, krzk, kgene, mark.rutland,
robh+dt, cw00.choi, kyungmin.park, a.hajda, m.szyprowski,
s.nawrocki, myungjoo.ham, Lukasz Luba
In-Reply-To: <CGME20190715124433eucas1p2a292f236ea55751117836742c1ca5d23@eucas1p2.samsung.com>
Hi all,
The patch set fixes clock settings for the Exynos5420/5422/5800 SoCs which
can be found in Odroid XU3/4, Google Peach Pi. Support for DT board files
with Exynos5420 (like Google Peach Pit) are under development. The old
implementation did not configure properly the clock rates or the
connections which could cause performance issues or instability. The
Exynos5x SoC has complex clocks topology. Some of the NoC clock branches
provide clock to the device internal buses or AXI interface and had wrong
settings.
In the old configuration the OPP values where not reflecting the actually
set frequencies, which were possible by setting the divider value on the
clock tree. The algorithms in governors, which use these frequencies,
relied on wrong assumption during their calculations. It also applies to
device drivers code, which does not check the rate of the clock but relay
on OPP values, which in some cases are different. It is not only the bus
frequency but also the connected component internal buses (accelerators
like e.g. G2D, scaler, rotator) frequency. Wrong frequency set due to
impossible division from PLL rate caused that some devices had lower than
possible clock for internal logic and for the AXI bus which transfers the
data. For example fixes for MMC controller, where OPP max frequency
changed from 150MHz to 240MHz, changing the PLL rate to proper value caused
performance increase up to 20% (FSYS2 OPP table).
Affected components inside SoC: image rotator, usb3.0 and 2.0 controller,
jpeg accelerator, image/video scaler, mmc controller, ISP, display
controller, all NoC buses.
Some of the clocks have name which might indicate their max speed, e.g.
CLK_DOUT_ACLK266 but it is not true. The max speed clock from this example
is 300MHz (according to the RM) and has been reflected accordingly in this
patch set.
Main changes:
- defined new clocks or added IDs to take them from DT nodes
- set proper PLLs frequency for: MPLL, DPLL, which would handle children
clock requirements down in the tree,
- changed parents of some clocks to proper PLL or to proper parent clock,
- properly calculated OPP values for the buses keeping in mind the parent
clock frequency and possible values derived from there by one clock
divider with proper bit length indicating maximum allowed divider; thanks
to that it is possible to set the requested frequency in all children
without changing the PLL frequency, which also makes the governor frequency
values assumption true,
- some OPPs were removed because it was not possible to set them due to
different base frequency, which would require of changing PLL rate, which
might affect other devices connected to this PLL and their misscalculated
rates.
The last two patches touches Exynos5800 and are optional. They have been
checked due to some issues with disabling parent, which accidently was
populated up to MPLL and shut down the PLL. They might be used for testing
on Peach Pi.
The patch set is based on Samsung clock repo and branch 'for-v5.3/next'
[1].
Regards,
Lukasz Luba
[1] https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git/log/?h=for-v5.3/next
Lukasz Luba (50):
clk: samsung: add new IDs for Exynos5420 clocks
clk: samsung: add IDs for Exynos5420 NoC clocks
clk: samsung: change parent of dout_aclk400_wcore in Exynos5420
clk: samsung: add IDs to manage aclk400_mscl in Exynos5420
clk: samsung: add IDs to aclk400_isp in Exynos5420
clk: samsung: add IDs to ACLK266 clocks in Exynos5420
clk: samsung: add IDs to ACLK266_G2D clocks in Exynos5420
clk: samsung: change aclk266_isp clocks definitions Exynos5420
clk: samsung: add IDs to FSYS clocks in Exynos5x
clk: samsung: change ACLK100_NOC clocks definitions Exynos5x
clk: samsung: add IDs to UART clocks in Exynos5420
clk: add ID to PWM MUX in Exynos5420
clk: samsung: add DPLL rate table in Exynos5420
clk: samsung: add CLK_MOUT_SCLK_CPLL in the Exynos5420
clk: samsung: add MPLL rate table in Exynos5420
clk: samsung: add SPLL rate table in Exynos5420
clk: samsung: add CLK_MOUT_MMC0 in the Exynos5420
ARM: dts: exynos: add bus_isp with OPP table
ARM: dts: exynos: change OPPs values for FSYS2 in Exynos5420
ARM: dts: exynos: change and rename FSYS OPP table in Exynos5420
ARM: dts: exynos: add OPP into FSYS APB bus in Exynos5420
ARM: dts: exynos: OPPs for bus_disp1 in Exynos5420
ARM: dts: exynos: change lowest OPP in bus_disp1_fimd in Exynos5420
ARM: dts: exynos: align OPPs with PLL rate for MSCL in Exynos5420
ARM: dts: exynos: add 300MHz to bus_disp1_fimd in Exynos5420
ARM: dts: exynos: align NOC100 bus OPPs in Exynos5420
ARM: dts: exynos: align bus_wcore OPPs in Exynos5420
ARM: dts: exynos: change OPPs for g2d and g2d_acp buses in Exynos5420
ARM: dts: exynos: align OPPs of bus_gen in Exynos5420
ARM: dts: exynos: add bus_isp266 into Exynos5800
ARM: dts: exynos: align lowest OPP in bus_jpeg in Exynos5420
ARM: dts: exynos: remove lowest OPP from bus_mfc in Exynos5420
ARM: dts: exynos: set parent clocks to UARTs in Exynos5420
ARM: dts: exynos: set parent clocks to PWM in Exynos5420
ARM: dts: exynos: change speed and parent of NoC clock in Exynos5420
ARM: dts: exynos: change ACLK100_NOC config in Exynos5422
ARM: dts: exynos: change parent and rate of bus_fsys in Exynos5422
ARM: dts: exynos: change parent and rate of bus_fsys2 in Exynos5422
ARM: dts: exynos: change parent and rate of bus_fsys_acp in Exynos5422
ARM: dts: exynos: change parent and rate of bus_gen in Exynos5422
ARM: dts: exynos: change parent and rate of bus_g2d in Exynos5422
ARM: dts: exynos: change parent and rate of bus_mscl in Exynos5422
ARM: dts: exynos: add bus_isp in Exynos5422
ARM: dts: exynos: change rate of bus_jpeg in Exynos5422
ARM: dts: exynos: change rate of bus_disp1_fimd in Exynos5422
ARM: dts: exynos: change rates of bus_disp1 in Exynos5422
ARM: dts: exynos: change rate of bus_gscl_scaler in Exynos5422
ARM: dts: exynos: set proper parents to bus_isp266 Exynos5422
ARM: dts: exynos: add buses support for Exynos5800 Peach Pi
ARM: dts: exynos: change MMC0 clock parent in Exynos5800 Peach Pi
arch/arm/boot/dts/exynos5420.dtsi | 116 +++++++-----
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 74 ++++++++
arch/arm/boot/dts/exynos5800-peach-pi.dts | 175 ++++++++++++++++++
arch/arm/boot/dts/exynos5800.dtsi | 10 +
drivers/clk/samsung/clk-exynos5420.c | 109 +++++++----
include/dt-bindings/clock/exynos5420.h | 27 ++-
6 files changed, 429 insertions(+), 82 deletions(-)
--
2.17.1
^ permalink raw reply
* Re: [PATCH v5 04/13] media: rc: sunxi: Add RXSTA bits definition
From: Sean Young @ 2019-07-15 12:12 UTC (permalink / raw)
To: Clément Péron
Cc: Mauro Carvalho Chehab, Maxime Ripard, Rob Herring, Mark Rutland,
Chen-Yu Tsai, devicetree, linux-kernel, linux-sunxi,
linux-arm-kernel, linux-media
In-Reply-To: <CAJiuCcfyjGTBbsjZQYj2p3KD6O-WaXhFe5NZrnKQwJYACmatUw@mail.gmail.com>
On Sun, Jul 14, 2019 at 04:32:22PM +0200, Clément Péron wrote:
> Hi Sean,
>
> You acked the whole v3 series but this patch has been introduced in v5
> could you ack this one too?
Acked-by: Sean Young <sean@mess.org>
Thanks
Sean
>
> Thanks,
> Clément
>
>
>
>
> On Mon, 10 Jun 2019 at 11:52, Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> >
> > On Sat, Jun 08, 2019 at 01:10:51AM +0200, Clément Péron wrote:
> > > We are using RXINT bits definition when looking at RXSTA register.
> > >
> > > These bits are equal but it's not really proper.
> > >
> > > Introduce the RXSTA bits and use them to have coherency.
> > >
> > > Signed-off-by: Clément Péron <peron.clem@gmail.com>
> >
> > Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
> >
> > Maxime
> >
> > --
> > Maxime Ripard, Bootlin
> > Embedded Linux and Kernel engineering
> > https://bootlin.com
^ permalink raw reply
* [PATCH v3 8/8] irqchip: Ingenic: Add support for X1500.
From: Zhou Yanjie @ 2019-07-15 12:09 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, devicetree, paul.burton, tglx, robh+dt,
mark.rutland, jason, marc.zyngier
In-Reply-To: <1563192595-53546-1-git-send-email-zhouyanjie@zoho.com>
Add support for probing the irq-ingenic driver on the
X1500 Soc from Ingenic.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
drivers/irqchip/irq-ingenic.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index e8f7ae7..b72430c 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -180,3 +180,4 @@ IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);
IRQCHIP_DECLARE(x1000_intc, "ingenic,x1000-intc", intc_2chip_of_init);
IRQCHIP_DECLARE(x1000e_intc, "ingenic,x1000e-intc", intc_2chip_of_init);
+IRQCHIP_DECLARE(x1500_intc, "ingenic,x1500-intc", intc_2chip_of_init);
--
2.7.4
^ permalink raw reply related
* [PATCH v3 7/8] dt-bindings: interrupt-controller: Add X1500 bindings.
From: Zhou Yanjie @ 2019-07-15 12:09 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, devicetree, paul.burton, tglx, robh+dt,
mark.rutland, jason, marc.zyngier
In-Reply-To: <1563192595-53546-1-git-send-email-zhouyanjie@zoho.com>
Add the interrupt-controller bindings for the
X1500 Soc from Ingenic.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
index 4f91bda..a96e120 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
@@ -12,6 +12,7 @@ Required properties:
ingenic,jz4780-intc
ingenic,x1000-intc
ingenic,x1000e-intc
+ ingenic,x1500-intc
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
--
2.7.4
^ permalink raw reply related
* [PATCH v3 6/8] irqchip: Ingenic: Add support for X1000 and X1000E.
From: Zhou Yanjie @ 2019-07-15 12:09 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, devicetree, paul.burton, tglx, robh+dt,
mark.rutland, jason, marc.zyngier
In-Reply-To: <1563192595-53546-1-git-send-email-zhouyanjie@zoho.com>
Add support for probing the irq-ingenic driver on the X1000 Soc
and the X1000E Soc from Ingenic.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
drivers/irqchip/irq-ingenic.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index e9e959c..e8f7ae7 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -178,3 +178,5 @@ IRQCHIP_DECLARE(jz4760b_intc, "ingenic,jz4760b-intc", intc_2chip_of_init);
IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);
+IRQCHIP_DECLARE(x1000_intc, "ingenic,x1000-intc", intc_2chip_of_init);
+IRQCHIP_DECLARE(x1000e_intc, "ingenic,x1000e-intc", intc_2chip_of_init);
--
2.7.4
^ permalink raw reply related
* [PATCH v3 5/8] dt-bindings: interrupt-controller: Add X1000 and X1000E bindings.
From: Zhou Yanjie @ 2019-07-15 12:09 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, devicetree, paul.burton, tglx, robh+dt,
mark.rutland, jason, marc.zyngier
In-Reply-To: <1563192595-53546-1-git-send-email-zhouyanjie@zoho.com>
Add the interrupt-controller bindings for the X1000 Soc and
the X1000E Soc from Ingenic.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
index fa1ad54..4f91bda 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
@@ -10,6 +10,8 @@ Required properties:
ingenic,jz4770-intc
ingenic,jz4775-intc
ingenic,jz4780-intc
+ ingenic,x1000-intc
+ ingenic,x1000e-intc
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
--
2.7.4
^ permalink raw reply related
* [PATCH v3 4/8] irqchip: Ingenic: Add support for JZ4760 and JZ4760B.
From: Zhou Yanjie @ 2019-07-15 12:09 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, devicetree, paul.burton, tglx, robh+dt,
mark.rutland, jason, marc.zyngier
In-Reply-To: <1563192595-53546-1-git-send-email-zhouyanjie@zoho.com>
Add support for probing the irq-ingenic driver on the JZ4760 Soc
and the JZ4760B Soc from Ingenic.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
drivers/irqchip/irq-ingenic.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 8430f5a..e9e959c 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -173,6 +173,8 @@ static int __init intc_2chip_of_init(struct device_node *node,
{
return ingenic_intc_of_init(node, 2);
}
+IRQCHIP_DECLARE(jz4760_intc, "ingenic,jz4760-intc", intc_2chip_of_init);
+IRQCHIP_DECLARE(jz4760b_intc, "ingenic,jz4760b-intc", intc_2chip_of_init);
IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);
--
2.7.4
^ permalink raw reply related
* [PATCH v3 3/8] dt-bindings: interrupt-controller: Add JZ4760 and JZ4760B bindings.
From: Zhou Yanjie @ 2019-07-15 12:09 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, devicetree, paul.burton, tglx, robh+dt,
mark.rutland, jason, marc.zyngier
In-Reply-To: <1563192595-53546-1-git-send-email-zhouyanjie@zoho.com>
Add the interrupt-controller bindings for the JZ4760 Soc and
the JZ4760B Soc from Ingenic.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
index d4373d0..fa1ad54 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
@@ -5,6 +5,8 @@ Required properties:
- compatible : should be "ingenic,<socname>-intc". Valid strings are:
ingenic,jz4740-intc
ingenic,jz4725b-intc
+ ingenic,jz4760-intc
+ ingenic,jz4760b-intc
ingenic,jz4770-intc
ingenic,jz4775-intc
ingenic,jz4780-intc
--
2.7.4
^ permalink raw reply related
* [PATCH v3 2/8] irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_".
From: Zhou Yanjie @ 2019-07-15 12:09 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, devicetree, paul.burton, tglx, robh+dt,
mark.rutland, jason, marc.zyngier
In-Reply-To: <1563192595-53546-1-git-send-email-zhouyanjie@zoho.com>
For the sake of uniform style, function "intc_irq_set_mask" is
changed to "ingenic_intc_intc_irq_set_mask".
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
drivers/irqchip/irq-ingenic.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 49f7685..8430f5a 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -63,7 +63,8 @@ static void ingenic_chained_handle_irq(struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
-static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
+static void ingenic_intc_irq_set_mask(struct irq_chip_generic *gc,
+ uint32_t mask)
{
struct irq_chip_regs *regs = &gc->chip_types->regs;
@@ -74,13 +75,13 @@ static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
void ingenic_intc_irq_suspend(struct irq_data *data)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
- intc_irq_set_mask(gc, gc->wake_active);
+ ingenic_intc_irq_set_mask(gc, gc->wake_active);
}
void ingenic_intc_irq_resume(struct irq_data *data)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
- intc_irq_set_mask(gc, gc->mask_cache);
+ ingenic_intc_irq_set_mask(gc, gc->mask_cache);
}
static int __init ingenic_intc_of_init(struct device_node *node,
--
2.7.4
^ permalink raw reply related
* [PATCH v3 1/8] irqchip: Ingenic: Change interrupt handling form cascade to chained_irq.
From: Zhou Yanjie @ 2019-07-15 12:09 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, devicetree, paul.burton, tglx, robh+dt,
mark.rutland, jason, marc.zyngier
In-Reply-To: <1563192595-53546-1-git-send-email-zhouyanjie@zoho.com>
The interrupt handling method is changed from old-style cascade to
chained_irq which is more appropriate. Also, it can process the
corner situation that more than one irq is coming to a single
chip at the same time.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
drivers/irqchip/irq-ingenic.c | 37 +++++++++++++++++++++++--------------
1 file changed, 23 insertions(+), 14 deletions(-)
diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index f126255..49f7685 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
- * JZ4740 platform IRQ support
+ * Ingenic XBurst platform IRQ support
*/
#include <linux/errno.h>
@@ -10,6 +10,7 @@
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/irqchip/ingenic.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
@@ -32,22 +33,34 @@ struct ingenic_intc_data {
#define JZ_REG_INTC_PENDING 0x10
#define CHIP_SIZE 0x20
-static irqreturn_t intc_cascade(int irq, void *data)
+static void ingenic_chained_handle_irq(struct irq_desc *desc)
{
- struct ingenic_intc_data *intc = irq_get_handler_data(irq);
- uint32_t irq_reg;
+ struct ingenic_intc_data *intc = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ bool have_irq = false;
+ uint32_t pending;
unsigned i;
+ chained_irq_enter(chip, desc);
for (i = 0; i < intc->num_chips; i++) {
- irq_reg = readl(intc->base + (i * CHIP_SIZE) +
+ pending = readl(intc->base + (i * CHIP_SIZE) +
JZ_REG_INTC_PENDING);
- if (!irq_reg)
+ if (!pending)
continue;
- generic_handle_irq(__fls(irq_reg) + (i * 32) + JZ4740_IRQ_BASE);
+ have_irq = true;
+ while (pending) {
+ int bit = __fls(pending);
+
+ generic_handle_irq(bit + (i * 32) + JZ4740_IRQ_BASE);
+ pending &= ~BIT(bit);
+ }
}
- return IRQ_HANDLED;
+ if (!have_irq)
+ spurious_interrupt();
+
+ chained_irq_exit(chip, desc);
}
static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
@@ -70,11 +83,6 @@ void ingenic_intc_irq_resume(struct irq_data *data)
intc_irq_set_mask(gc, gc->mask_cache);
}
-static struct irqaction intc_cascade_action = {
- .handler = intc_cascade,
- .name = "SoC intc cascade interrupt",
-};
-
static int __init ingenic_intc_of_init(struct device_node *node,
unsigned num_chips)
{
@@ -139,7 +147,8 @@ static int __init ingenic_intc_of_init(struct device_node *node,
if (!domain)
pr_warn("unable to register IRQ domain\n");
- setup_irq(parent_irq, &intc_cascade_action);
+ irq_set_chained_handler_and_data(parent_irq,
+ ingenic_chained_handle_irq, intc);
return 0;
out_unmap_irq:
--
2.7.4
^ permalink raw reply related
* Add Ingenic JZ4760 and X1000 and X1500 irqchip support v3.
From: Zhou Yanjie @ 2019-07-15 12:09 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, devicetree, paul.burton, tglx, robh+dt,
mark.rutland, jason, marc.zyngier
In-Reply-To: <1548517123-60058-1-git-send-email-zhouyanjie@zoho.com>
v1->v2: Replace "__fls(pending)" with "bit" in function "generic_handle_irq".
v2->v3: Add support for probing irq-ingenic driver on JZ4760 and X1500 Soc.
^ permalink raw reply
* [PATCH v2 4/4] dt-bindings: devfreq: exynos-bus: remove unused property
From: Kamil Konieczny @ 2019-07-15 12:04 UTC (permalink / raw)
To: k.konieczny
Cc: Bartlomiej Zolnierkiewicz, Marek Szyprowski, Chanwoo Choi,
Krzysztof Kozlowski, Kukjin Kim, Kyungmin Park, Mark Rutland,
MyungJoo Ham, Nishanth Menon, Rob Herring, Stephen Boyd,
Viresh Kumar, devicetree, linux-arm-kernel, linux-kernel,
linux-pm, linux-samsung-soc
In-Reply-To: <20190715120416.3561-1-k.konieczny@partner.samsung.com>
Remove unused DT property "exynos,voltage-tolerance".
Signed-off-by: Kamil Konieczny <k.konieczny@partner.samsung.com>
---
Documentation/devicetree/bindings/devfreq/exynos-bus.txt | 2 --
1 file changed, 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
index f8e946471a58..e71f752cc18f 100644
--- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
+++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
@@ -50,8 +50,6 @@ Required properties only for passive bus device:
Optional properties only for parent bus device:
- exynos,saturation-ratio: the percentage value which is used to calibrate
the performance count against total cycle count.
-- exynos,voltage-tolerance: the percentage value for bus voltage tolerance
- which is used to calculate the max voltage.
Detailed correlation between sub-blocks and power line according to Exynos SoC:
- In case of Exynos3250, there are two power line as following:
--
2.22.0
^ permalink raw reply related
* [PATCH v2 3/4] ARM: dts: exynos: add initial data for coupled regulators for Exynos5422/5800
From: Kamil Konieczny @ 2019-07-15 12:04 UTC (permalink / raw)
To: k.konieczny
Cc: Bartlomiej Zolnierkiewicz, Marek Szyprowski, Chanwoo Choi,
Krzysztof Kozlowski, Kukjin Kim, Kyungmin Park, Mark Rutland,
MyungJoo Ham, Nishanth Menon, Rob Herring, Stephen Boyd,
Viresh Kumar, devicetree, linux-arm-kernel, linux-kernel,
linux-pm, linux-samsung-soc
In-Reply-To: <20190715120416.3561-1-k.konieczny@partner.samsung.com>
Declare Exynos5422/5800 voltage ranges for opp points for big cpu core and
bus wcore and couple their voltage supllies as vdd_arm and vdd_int should
be in 300mV range.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kamil Konieczny <k.konieczny@partner.samsung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 34 +++++++++----------
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 4 +++
arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 +++
arch/arm/boot/dts/exynos5800.dtsi | 32 ++++++++---------
4 files changed, 41 insertions(+), 33 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 5fb2326875dc..0cbf74750553 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -48,62 +48,62 @@
opp-shared;
opp-1800000000 {
opp-hz = /bits/ 64 <1800000000>;
- opp-microvolt = <1250000>;
+ opp-microvolt = <1250000 1250000 1500000>;
clock-latency-ns = <140000>;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
- opp-microvolt = <1212500>;
+ opp-microvolt = <1212500 1212500 1500000>;
clock-latency-ns = <140000>;
};
opp-1600000000 {
opp-hz = /bits/ 64 <1600000000>;
- opp-microvolt = <1175000>;
+ opp-microvolt = <1175000 1175000 1500000>;
clock-latency-ns = <140000>;
};
opp-1500000000 {
opp-hz = /bits/ 64 <1500000000>;
- opp-microvolt = <1137500>;
+ opp-microvolt = <1137500 1137500 1500000>;
clock-latency-ns = <140000>;
};
opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
- opp-microvolt = <1112500>;
+ opp-microvolt = <1112500 1112500 1500000>;
clock-latency-ns = <140000>;
};
opp-1300000000 {
opp-hz = /bits/ 64 <1300000000>;
- opp-microvolt = <1062500>;
+ opp-microvolt = <1062500 1062500 1500000>;
clock-latency-ns = <140000>;
};
opp-1200000000 {
opp-hz = /bits/ 64 <1200000000>;
- opp-microvolt = <1037500>;
+ opp-microvolt = <1037500 1037500 1500000>;
clock-latency-ns = <140000>;
};
opp-1100000000 {
opp-hz = /bits/ 64 <1100000000>;
- opp-microvolt = <1012500>;
+ opp-microvolt = <1012500 1012500 1500000>;
clock-latency-ns = <140000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = < 987500>;
+ opp-microvolt = < 987500 987500 1500000>;
clock-latency-ns = <140000>;
};
opp-900000000 {
opp-hz = /bits/ 64 <900000000>;
- opp-microvolt = < 962500>;
+ opp-microvolt = < 962500 962500 1500000>;
clock-latency-ns = <140000>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
- opp-microvolt = < 937500>;
+ opp-microvolt = < 937500 937500 1500000>;
clock-latency-ns = <140000>;
};
opp-700000000 {
opp-hz = /bits/ 64 <700000000>;
- opp-microvolt = < 912500>;
+ opp-microvolt = < 912500 912500 1500000>;
clock-latency-ns = <140000>;
};
};
@@ -1100,23 +1100,23 @@
opp00 {
opp-hz = /bits/ 64 <84000000>;
- opp-microvolt = <925000>;
+ opp-microvolt = <925000 925000 1400000>;
};
opp01 {
opp-hz = /bits/ 64 <111000000>;
- opp-microvolt = <950000>;
+ opp-microvolt = <950000 950000 1400000>;
};
opp02 {
opp-hz = /bits/ 64 <222000000>;
- opp-microvolt = <950000>;
+ opp-microvolt = <950000 950000 1400000>;
};
opp03 {
opp-hz = /bits/ 64 <333000000>;
- opp-microvolt = <950000>;
+ opp-microvolt = <950000 950000 1400000>;
};
opp04 {
opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <987500>;
+ opp-microvolt = <987500 987500 1400000>;
};
};
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index 25d95de15c9b..65d094256b54 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -428,6 +428,8 @@
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&buck3_reg>;
+ regulator-coupled-max-spread = <300000>;
};
buck3_reg: BUCK3 {
@@ -436,6 +438,8 @@
regulator-max-microvolt = <1400000>;
regulator-always-on;
regulator-boot-on;
+ regulator-coupled-with = <&buck2_reg>;
+ regulator-coupled-max-spread = <300000>;
};
buck4_reg: BUCK4 {
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index e0f470fe54c8..5c1e965ed7e9 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -257,6 +257,8 @@
regulator-always-on;
regulator-boot-on;
regulator-ramp-delay = <12500>;
+ regulator-coupled-with = <&buck3_reg>;
+ regulator-coupled-max-spread = <300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
@@ -269,6 +271,8 @@
regulator-always-on;
regulator-boot-on;
regulator-ramp-delay = <12500>;
+ regulator-coupled-with = <&buck2_reg>;
+ regulator-coupled-max-spread = <300000>;
regulator-state-mem {
regulator-off-in-suspend;
};
diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
index 57d3b319fd65..2a74735d161c 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -22,61 +22,61 @@
&cluster_a15_opp_table {
opp-1700000000 {
- opp-microvolt = <1250000>;
+ opp-microvolt = <1250000 1250000 1500000>;
};
opp-1600000000 {
- opp-microvolt = <1250000>;
+ opp-microvolt = <1250000 1250000 1500000>;
};
opp-1500000000 {
- opp-microvolt = <1100000>;
+ opp-microvolt = <1100000 1100000 1500000>;
};
opp-1400000000 {
- opp-microvolt = <1100000>;
+ opp-microvolt = <1100000 1100000 1500000>;
};
opp-1300000000 {
- opp-microvolt = <1100000>;
+ opp-microvolt = <1100000 1100000 1500000>;
};
opp-1200000000 {
- opp-microvolt = <1000000>;
+ opp-microvolt = <1000000 1000000 1500000>;
};
opp-1100000000 {
- opp-microvolt = <1000000>;
+ opp-microvolt = <1000000 1000000 1500000>;
};
opp-1000000000 {
- opp-microvolt = <1000000>;
+ opp-microvolt = <1000000 1000000 1500000>;
};
opp-900000000 {
- opp-microvolt = <1000000>;
+ opp-microvolt = <1000000 1000000 1500000>;
};
opp-800000000 {
- opp-microvolt = <900000>;
+ opp-microvolt = <900000 900000 1500000>;
};
opp-700000000 {
- opp-microvolt = <900000>;
+ opp-microvolt = <900000 900000 1500000>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <900000 900000 1500000>;
clock-latency-ns = <140000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <900000 900000 1500000>;
clock-latency-ns = <140000>;
};
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <900000 900000 1500000>;
clock-latency-ns = <140000>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <900000 900000 1500000>;
clock-latency-ns = <140000>;
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
- opp-microvolt = <900000>;
+ opp-microvolt = <900000 900000 1500000>;
clock-latency-ns = <140000>;
};
};
--
2.22.0
^ permalink raw reply related
* [PATCH v2 2/4] devfreq: exynos-bus: convert to use dev_pm_opp_set_rate()
From: Kamil Konieczny @ 2019-07-15 12:04 UTC (permalink / raw)
To: k.konieczny
Cc: Bartlomiej Zolnierkiewicz, Marek Szyprowski, Chanwoo Choi,
Krzysztof Kozlowski, Kukjin Kim, Kyungmin Park, Mark Rutland,
MyungJoo Ham, Nishanth Menon, Rob Herring, Stephen Boyd,
Viresh Kumar, devicetree, linux-arm-kernel, linux-kernel,
linux-pm, linux-samsung-soc
In-Reply-To: <20190715120416.3561-1-k.konieczny@partner.samsung.com>
Reuse opp core code for setting bus clock and voltage. As a side
effect this allow useage of coupled regulators feature (required
for boards using Exynos5422/5800 SoCs) because dev_pm_opp_set_rate()
uses regulator_set_voltage_triplet() for setting regulator voltage
while the old code used regulator_set_voltage_tol() with fixed
tolerance. This patch also removes no longer needed parsing of DT
property "exynos,voltage-tolerance" (no Exynos devfreq DT node uses
it).
Signed-off-by: Kamil Konieczny <k.konieczny@partner.samsung.com>
---
drivers/devfreq/exynos-bus.c | 172 ++++++++++++++---------------------
1 file changed, 66 insertions(+), 106 deletions(-)
diff --git a/drivers/devfreq/exynos-bus.c b/drivers/devfreq/exynos-bus.c
index 486cc5b422f1..7fc4f76bd848 100644
--- a/drivers/devfreq/exynos-bus.c
+++ b/drivers/devfreq/exynos-bus.c
@@ -25,7 +25,6 @@
#include <linux/slab.h>
#define DEFAULT_SATURATION_RATIO 40
-#define DEFAULT_VOLTAGE_TOLERANCE 2
struct exynos_bus {
struct device *dev;
@@ -37,9 +36,9 @@ struct exynos_bus {
unsigned long curr_freq;
- struct regulator *regulator;
+ struct opp_table *opp_table;
+
struct clk *clk;
- unsigned int voltage_tolerance;
unsigned int ratio;
};
@@ -99,56 +98,25 @@ static int exynos_bus_target(struct device *dev, unsigned long *freq, u32 flags)
{
struct exynos_bus *bus = dev_get_drvdata(dev);
struct dev_pm_opp *new_opp;
- unsigned long old_freq, new_freq, new_volt, tol;
int ret = 0;
-
- /* Get new opp-bus instance according to new bus clock */
+ /*
+ * New frequency for bus may not be exactly matched to opp, adjust
+ * *freq to correct value.
+ */
new_opp = devfreq_recommended_opp(dev, freq, flags);
if (IS_ERR(new_opp)) {
dev_err(dev, "failed to get recommended opp instance\n");
return PTR_ERR(new_opp);
}
- new_freq = dev_pm_opp_get_freq(new_opp);
- new_volt = dev_pm_opp_get_voltage(new_opp);
dev_pm_opp_put(new_opp);
- old_freq = bus->curr_freq;
-
- if (old_freq == new_freq)
- return 0;
- tol = new_volt * bus->voltage_tolerance / 100;
-
/* Change voltage and frequency according to new OPP level */
mutex_lock(&bus->lock);
+ ret = dev_pm_opp_set_rate(dev, *freq);
+ if (!ret)
+ bus->curr_freq = *freq;
- if (old_freq < new_freq) {
- ret = regulator_set_voltage_tol(bus->regulator, new_volt, tol);
- if (ret < 0) {
- dev_err(bus->dev, "failed to set voltage\n");
- goto out;
- }
- }
-
- ret = clk_set_rate(bus->clk, new_freq);
- if (ret < 0) {
- dev_err(dev, "failed to change clock of bus\n");
- clk_set_rate(bus->clk, old_freq);
- goto out;
- }
-
- if (old_freq > new_freq) {
- ret = regulator_set_voltage_tol(bus->regulator, new_volt, tol);
- if (ret < 0) {
- dev_err(bus->dev, "failed to set voltage\n");
- goto out;
- }
- }
- bus->curr_freq = new_freq;
-
- dev_dbg(dev, "Set the frequency of bus (%luHz -> %luHz, %luHz)\n",
- old_freq, new_freq, clk_get_rate(bus->clk));
-out:
mutex_unlock(&bus->lock);
return ret;
@@ -194,10 +162,11 @@ static void exynos_bus_exit(struct device *dev)
if (ret < 0)
dev_warn(dev, "failed to disable the devfreq-event devices\n");
- if (bus->regulator)
- regulator_disable(bus->regulator);
+ if (bus->opp_table)
+ dev_pm_opp_put_regulators(bus->opp_table);
dev_pm_opp_of_remove_table(dev);
+
clk_disable_unprepare(bus->clk);
}
@@ -209,39 +178,26 @@ static int exynos_bus_passive_target(struct device *dev, unsigned long *freq,
{
struct exynos_bus *bus = dev_get_drvdata(dev);
struct dev_pm_opp *new_opp;
- unsigned long old_freq, new_freq;
- int ret = 0;
+ int ret;
- /* Get new opp-bus instance according to new bus clock */
+ /*
+ * New frequency for bus may not be exactly matched to opp, adjust
+ * *freq to correct value.
+ */
new_opp = devfreq_recommended_opp(dev, freq, flags);
if (IS_ERR(new_opp)) {
dev_err(dev, "failed to get recommended opp instance\n");
return PTR_ERR(new_opp);
}
- new_freq = dev_pm_opp_get_freq(new_opp);
dev_pm_opp_put(new_opp);
- old_freq = bus->curr_freq;
-
- if (old_freq == new_freq)
- return 0;
-
/* Change the frequency according to new OPP level */
mutex_lock(&bus->lock);
+ ret = dev_pm_opp_set_rate(dev, *freq);
+ if (!ret)
+ bus->curr_freq = *freq;
- ret = clk_set_rate(bus->clk, new_freq);
- if (ret < 0) {
- dev_err(dev, "failed to set the clock of bus\n");
- goto out;
- }
-
- *freq = new_freq;
- bus->curr_freq = new_freq;
-
- dev_dbg(dev, "Set the frequency of bus (%luHz -> %luHz, %luHz)\n",
- old_freq, new_freq, clk_get_rate(bus->clk));
-out:
mutex_unlock(&bus->lock);
return ret;
@@ -259,20 +215,7 @@ static int exynos_bus_parent_parse_of(struct device_node *np,
struct exynos_bus *bus)
{
struct device *dev = bus->dev;
- int i, ret, count, size;
-
- /* Get the regulator to provide each bus with the power */
- bus->regulator = devm_regulator_get(dev, "vdd");
- if (IS_ERR(bus->regulator)) {
- dev_err(dev, "failed to get VDD regulator\n");
- return PTR_ERR(bus->regulator);
- }
-
- ret = regulator_enable(bus->regulator);
- if (ret < 0) {
- dev_err(dev, "failed to enable VDD regulator\n");
- return ret;
- }
+ int i, count, size;
/*
* Get the devfreq-event devices to get the current utilization of
@@ -281,24 +224,20 @@ static int exynos_bus_parent_parse_of(struct device_node *np,
count = devfreq_event_get_edev_count(dev);
if (count < 0) {
dev_err(dev, "failed to get the count of devfreq-event dev\n");
- ret = count;
- goto err_regulator;
+ return count;
}
+
bus->edev_count = count;
size = sizeof(*bus->edev) * count;
bus->edev = devm_kzalloc(dev, size, GFP_KERNEL);
- if (!bus->edev) {
- ret = -ENOMEM;
- goto err_regulator;
- }
+ if (!bus->edev)
+ return -ENOMEM;
for (i = 0; i < count; i++) {
bus->edev[i] = devfreq_event_get_edev_by_phandle(dev, i);
- if (IS_ERR(bus->edev[i])) {
- ret = -EPROBE_DEFER;
- goto err_regulator;
- }
+ if (IS_ERR(bus->edev[i]))
+ return -EPROBE_DEFER;
}
/*
@@ -314,22 +253,15 @@ static int exynos_bus_parent_parse_of(struct device_node *np,
if (of_property_read_u32(np, "exynos,saturation-ratio", &bus->ratio))
bus->ratio = DEFAULT_SATURATION_RATIO;
- if (of_property_read_u32(np, "exynos,voltage-tolerance",
- &bus->voltage_tolerance))
- bus->voltage_tolerance = DEFAULT_VOLTAGE_TOLERANCE;
-
return 0;
-
-err_regulator:
- regulator_disable(bus->regulator);
-
- return ret;
}
static int exynos_bus_parse_of(struct device_node *np,
- struct exynos_bus *bus)
+ struct exynos_bus *bus, bool passive)
{
struct device *dev = bus->dev;
+ struct opp_table *opp_table;
+ const char *vdd = "vdd";
struct dev_pm_opp *opp;
unsigned long rate;
int ret;
@@ -347,11 +279,22 @@ static int exynos_bus_parse_of(struct device_node *np,
return ret;
}
+ if (!passive) {
+ opp_table = dev_pm_opp_set_regulators(dev, &vdd, 1);
+ if (IS_ERR(opp_table)) {
+ ret = PTR_ERR(opp_table);
+ dev_err(dev, "failed to set regulators %d\n", ret);
+ goto err_clk;
+ }
+
+ bus->opp_table = opp_table;
+ }
+
/* Get the freq and voltage from OPP table to scale the bus freq */
ret = dev_pm_opp_of_add_table(dev);
if (ret < 0) {
dev_err(dev, "failed to get OPP table\n");
- goto err_clk;
+ goto err_regulator;
}
rate = clk_get_rate(bus->clk);
@@ -362,6 +305,7 @@ static int exynos_bus_parse_of(struct device_node *np,
ret = PTR_ERR(opp);
goto err_opp;
}
+
bus->curr_freq = dev_pm_opp_get_freq(opp);
dev_pm_opp_put(opp);
@@ -369,6 +313,13 @@ static int exynos_bus_parse_of(struct device_node *np,
err_opp:
dev_pm_opp_of_remove_table(dev);
+
+err_regulator:
+ if (bus->opp_table) {
+ dev_pm_opp_put_regulators(bus->opp_table);
+ bus->opp_table = NULL;
+ }
+
err_clk:
clk_disable_unprepare(bus->clk);
@@ -386,6 +337,7 @@ static int exynos_bus_probe(struct platform_device *pdev)
struct exynos_bus *bus;
int ret, max_state;
unsigned long min_freq, max_freq;
+ bool passive = false;
if (!np) {
dev_err(dev, "failed to find devicetree node\n");
@@ -395,12 +347,18 @@ static int exynos_bus_probe(struct platform_device *pdev)
bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
if (!bus)
return -ENOMEM;
+
mutex_init(&bus->lock);
bus->dev = &pdev->dev;
platform_set_drvdata(pdev, bus);
+ node = of_parse_phandle(dev->of_node, "devfreq", 0);
+ if (node) {
+ of_node_put(node);
+ passive = true;
+ }
/* Parse the device-tree to get the resource information */
- ret = exynos_bus_parse_of(np, bus);
+ ret = exynos_bus_parse_of(np, bus, passive);
if (ret < 0)
return ret;
@@ -410,13 +368,10 @@ static int exynos_bus_probe(struct platform_device *pdev)
goto err;
}
- node = of_parse_phandle(dev->of_node, "devfreq", 0);
- if (node) {
- of_node_put(node);
+ if (passive)
goto passive;
- } else {
- ret = exynos_bus_parent_parse_of(np, bus);
- }
+
+ ret = exynos_bus_parent_parse_of(np, bus);
if (ret < 0)
goto err;
@@ -509,6 +464,11 @@ static int exynos_bus_probe(struct platform_device *pdev)
err:
dev_pm_opp_of_remove_table(dev);
+ if (bus->opp_table) {
+ dev_pm_opp_put_regulators(bus->opp_table);
+ bus->opp_table = NULL;
+ }
+
clk_disable_unprepare(bus->clk);
return ret;
--
2.22.0
^ permalink raw reply related
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