* Re: [PATCH v1 37/50] ARM: dts: exynos: change parent and rate of bus_fsys in Exynos5422
From: Krzysztof Kozlowski @ 2019-07-17 10:25 UTC (permalink / raw)
To: Lukasz Luba
Cc: devicetree, linux-kernel, linux-arm-kernel,
linux-samsung-soc@vger.kernel.org, linux-clk, mturquette, sboyd,
Bartłomiej Żołnierkiewicz, kgene, mark.rutland,
robh+dt, Chanwoo Choi, kyungmin.park, Andrzej Hajda,
Marek Szyprowski, s.nawrocki, myungjoo.ham
In-Reply-To: <20190715124417.4787-38-l.luba@partner.samsung.com>
On Mon, 15 Jul 2019 at 14:45, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> The FSYS bus OPP table has been aligned to the new parent rate. This patch
> sets the proper parent and picks the init frequency before the devfreq
> governor starts working. It sets also parent rate (DPLL to 1200MHz).
1. I see what the patch is doing, but please write why you are doing
this. What problem are you solving here?
2. Commit title is wrong - it is not Exynos 5422 but Odroid XU3/XU4
family of boards.
>
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
> arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> index d460041f716c..6a82dd175b8a 100644
> --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> @@ -72,6 +72,11 @@
>
> &bus_fsys {
> devfreq = <&bus_wcore>;
> + assigned-clocks = <&clock CLK_MOUT_ACLK200_FSYS>,
> + <&clock CLK_DOUT_ACLK200_FSYS>,
> + <&clock CLK_FOUT_DPLL>;
> + assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>;
> + assigned-clock-rates = <0>, <240000000>,<1200000000>;
Here and in all other patches:
I am not entirely sure that this should be here. It looks like
property of the SoC. Do we expect that buses will be configured to
different clock rates between different boards? Since the OPP tables
are shared (they are property of the SoC, not board) then I would
assume that default frequency is shared as well.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v1 27/50] ARM: dts: exynos: align bus_wcore OPPs in Exynos5420
From: Krzysztof Kozlowski @ 2019-07-17 10:15 UTC (permalink / raw)
To: Lukasz Luba
Cc: devicetree, linux-kernel, linux-arm-kernel,
linux-samsung-soc@vger.kernel.org, linux-clk, mturquette, sboyd,
Bartłomiej Żołnierkiewicz, kgene, mark.rutland,
robh+dt, Chanwoo Choi, kyungmin.park, Andrzej Hajda,
Marek Szyprowski, s.nawrocki, myungjoo.ham
In-Reply-To: <20190715124417.4787-28-l.luba@partner.samsung.com>
On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> This is the most important bus in the Exynos5x SoC. The whole communication
> inside SoC does through that bus (apart from direct requests from CCI to
> DRAM controller). It is also modeled as a master bus in devfreq framework.
> It is also the only one OPP table throughout other buses which has voltage
> values. The devfreq software controls the speed of that bus and other
> buses. The other buses follows the rate of the master. There is only one
> regulator. The old lowest OPP had pair 925mV, 84MHz which is enough for
s/lowest/slowest/
> this frequency. However, due to the fact that the other buses follows the
> WCORE bus by taking the OPP from their table with the same id, e.g. opp02,
> the children frequency should be stable with the set voltage.
> It could cause random faults very hard to debug.
> Thus, the patch removes the lowest OPP to make other buses' lowest OPPs
s/lowest/slowest/
> working. The new lowest OPP has voltage high enough for buses working up
> to 333MHz. It also changes the frequencies of the OPPs to align them to
> PLL value such that it is possible to set them using only a divider without
> reprogramming OPP.
Reprogramming OPP? What is it?
> Reprogramming the PLL was not set, so the real frequency
I understood from the previous that reprogramming the OPP (PLL?) was
happening... Please rephrase entire sentence.
BR,
Krzysztof
> values were not the one from the OPP table, which could confuse the
> governor algorithms which relay on OPP speed values making the system to
> behave weird.
>
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
> arch/arm/boot/dts/exynos5420.dtsi | 12 ++++--------
> 1 file changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
> index f8c36ff0d4c3..a355c76af5a5 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> @@ -1107,22 +1107,18 @@
> compatible = "operating-points-v2";
>
> opp00 {
> - opp-hz = /bits/ 64 <84000000>;
> - opp-microvolt = <925000>;
> + opp-hz = /bits/ 64 <150000000>;
> + opp-microvolt = <950000>;
> };
> opp01 {
> - opp-hz = /bits/ 64 <111000000>;
> + opp-hz = /bits/ 64 <200000000>;
> opp-microvolt = <950000>;
> };
> opp02 {
> - opp-hz = /bits/ 64 <222000000>;
> + opp-hz = /bits/ 64 <300000000>;
> opp-microvolt = <950000>;
> };
> opp03 {
> - opp-hz = /bits/ 64 <333000000>;
> - opp-microvolt = <950000>;
> - };
> - opp04 {
> opp-hz = /bits/ 64 <400000000>;
> opp-microvolt = <987500>;
> };
> --
> 2.17.1
>
^ permalink raw reply
* Re: [PATCH v1 43/50] ARM: dts: exynos: add bus_isp in Exynos5422
From: Lukasz Luba @ 2019-07-17 10:12 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: devicetree, linux-kernel, linux-arm-kernel,
linux-samsung-soc@vger.kernel.org, linux-clk, mturquette, sboyd,
Bartłomiej Żołnierkiewicz, kgene, mark.rutland,
robh+dt, Chanwoo Choi, kyungmin.park, Andrzej Hajda,
Marek Szyprowski, s.nawrocki, myungjoo.ham
In-Reply-To: <CAJKOXPcsH9YRzLOA1P5xc0Y3Zqh9+5o0RSxP-JcYOVEm7eO0Sw@mail.gmail.com>
On 7/17/19 12:02 PM, Krzysztof Kozlowski wrote:
> On Mon, 15 Jul 2019 at 14:45, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>>
>> Add bus_isp which changes ACLK400_ISP clock speed according to the bus
>> documentation in the documentation. The bus_isp OPP table has been
>> aligned to the new parent rate.
>
> Title and msg needs fixing.
>
> Please squash it with patch 18.
You are right, it needs to be squashed. As I mentioned earlier Barek
suggested offline to make 'atomic modifications' of OPPs and PLL/clocks
rates for all affected children in the clock tree.
Regards,
Lukasz
>
> Best regards,
> Krzysztof
>
>> This patch sets the proper parent and
>> picks the init frequency before the devfreq governor starts working.
>> It sets also parent rate (DPLL to 1200MHz).
>>
>> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
>> ---
>> arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 12 ++++++++++++
>> 1 file changed, 12 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
>> index 990fe03fce75..852cb3dd495d 100644
>> --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
>> +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
>> @@ -166,6 +166,18 @@
>> status = "okay";
>> };
>>
>> +&bus_isp {
>> + devfreq = <&bus_wcore>;
>> + assigned-clocks = <&clock CLK_MOUT_ACLK400_ISP>,
>> + <&clock CLK_MOUT_SW_ACLK400_ISP>,
>> + <&clock CLK_DOUT_ACLK400_ISP>,
>> + <&clock CLK_FOUT_DPLL>;
>> + assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>,
>> + <&clock CLK_DOUT_ACLK400_ISP>;
>> + assigned-clock-rates = <0>, <0>, <400000000>, <1200000000>;
>> + status = "okay";
>> +};
>> +
>> &cpu0 {
>> cpu-supply = <&buck6_reg>;
>> };
>> --
>> 2.17.1
>>
>
>
^ permalink raw reply
* Re: [PATCH v1 26/50] ARM: dts: exynos: align NOC100 bus OPPs in Exynos5420
From: Krzysztof Kozlowski @ 2019-07-17 10:10 UTC (permalink / raw)
To: Lukasz Luba
Cc: devicetree, linux-kernel, linux-arm-kernel,
linux-samsung-soc@vger.kernel.org, linux-clk, mturquette, sboyd,
Bartłomiej Żołnierkiewicz, kgene, mark.rutland,
robh+dt, Chanwoo Choi, kyungmin.park, Andrzej Hajda,
Marek Szyprowski, s.nawrocki, myungjoo.ham
In-Reply-To: <20190715124417.4787-27-l.luba@partner.samsung.com>
On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> The NOC100 has a parent which clock rate is set tot 400MHz. The OPPs which
> are not possible to set are removed and new one is added.
I think it is just NOC bus... or are there more of such and this is 100 MHz one?
Best regards,
Krzysztof
^ permalink raw reply
* RE: [EXT] Re: [v5,2/2] Documentation: dt: binding: rtc: add binding for ftm alarm driver
From: Biwen Li @ 2019-07-17 10:05 UTC (permalink / raw)
To: Rob Herring
Cc: Alessandro Zummo, Alexandre Belloni, Leo Li,
open list:REAL TIME CLOCK (RTC) SUBSYSTEM,
linux-kernel@vger.kernel.org, Xiaobo Xie, Jiafei Pan, Ran Wang,
Mark Rutland, devicetree@vger.kernel.org
In-Reply-To: <CAL_Jsq+U=W_51qUDvOMPgexMOLuqTyYua5H6G-cwFnKCh8YmPg@mail.gmail.com>
>
> Caution: EXT Email
>
> On Tue, Jul 16, 2019 at 4:26 AM Biwen Li <biwen.li@nxp.com> wrote:
> >
> > The patch adds binding for ftm alarm driver
>
> Bindings are for h/w, not drivers...
>
> 'dt-bindings: rtc: ...' for the subject prefix.
I will correct it in v6.
>
> >
> > Signed-off-by: Biwen Li <biwen.li@nxp.com>
> > ---
> > Change in v5:
> > - None
> >
> > Change in v4:
> > - add note about dts and kernel options
> > - add aliases in example
> >
> > Change in v3:
> > - remove reg-names property
> > - correct cells number
> >
> > Change in v2:
> > - replace ls1043a with ls1088a as example
> > - add rcpm node and fsl,rcpm-wakeup property
> >
> >
> > .../bindings/rtc/rtc-fsl-ftm-alarm.txt | 49 +++++++++++++++++++
> > 1 file changed, 49 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/rtc/rtc-fsl-ftm-alarm.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/rtc/rtc-fsl-ftm-alarm.txt
> > b/Documentation/devicetree/bindings/rtc/rtc-fsl-ftm-alarm.txt
> > new file mode 100644
> > index 000000000000..fb018065406c
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/rtc/rtc-fsl-ftm-alarm.txt
> > @@ -0,0 +1,49 @@
> > +Freescale FlexTimer Module (FTM) Alarm
> > +
> > +Note:
> > +- The driver depends on RCPM driver
> > + to wake up system in sleep.
> > +- Need stop using RTC_HCTOSYS or use the DT aliases
> > + to ensure the driver is not used as the primary RTC.
> > + (Select DT aliases defaultly)
>
> This is Linux specific and not relevant to the binding.
Ok, I will remove all of the Note in v6.
>
> > +
> > +Required properties:
> > +- compatible : Should be "fsl,<chip>-ftm-alarm", the
> > + supported chips include
> > + "fsl,ls1012a-ftm-alarm"
> > + "fsl,ls1021a-ftm-alarm"
> > + "fsl,ls1028a-ftm-alarm"
> > + "fsl,ls1043a-ftm-alarm"
> > + "fsl,ls1046a-ftm-alarm"
> > + "fsl,ls1088a-ftm-alarm"
> > + "fsl,ls208xa-ftm-alarm"
> > +- reg : Specifies base physical address and size of the register sets
> > +for the
> > + FlexTimer Module and base physical address of IP Powerdown
> > +Exception Control
> > + Register.
> > +- interrupts : Should be the FlexTimer Module interrupt.
> > +- fsl,rcpm-wakeup property and rcpm node : Please refer
> > + Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > +
> > +Optional properties:
> > +- big-endian: If the host controller is big-endian mode, specify this property.
> > + The default endian mode is little-endian.
> > +
> > +Example:
> > +aliases {
> > + ...
> > + rtc1 = ftm_alarm0; /* Use flextimer alarm driver as /dev/rtc1 */
> > + ...
> > +};
>
> Drop the aliases part. It's not going to work when this is converted to DT schema
> and the comment is Linux specific.
Sorry,I can't drop the aliases part. If any user uses the alarm driver as rtc0,
the user will get wrong time from /dev/rtc0.It is very important.
>
> > +
> > +rcpm: rcpm@1e34040 {
> > + compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
> > + reg = <0x0 0x1e34040 0x0 0x18>;
> > + fsl,#rcpm-wakeup-cells = <6>;
>
> Before there are any users of this, either drop it if it is not variable or the correct
> form would be '#fsl,rcpm-wakeup-cells'.
I will replace 'fsl,#rcpm-wakeup-cells' with '#fsl,rcpm-wakeup-cells' in v6.
>
> > +};
> > +
> > +ftm_alarm0: timer@2800000 {
> > + compatible = "fsl,ls1088a-ftm-alarm";
> > + reg = <0x0 0x2800000 0x0 0x10000>;
> > + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
> > + interrupts = <0 44 4>;
> > +};
> > --
> > 2.17.1
> >
^ permalink raw reply
* Re: [PATCH v1 20/50] ARM: dts: exynos: change and rename FSYS OPP table in Exynos5420
From: Lukasz Luba @ 2019-07-17 10:04 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: devicetree, linux-kernel, linux-arm-kernel,
linux-samsung-soc@vger.kernel.org, linux-clk, mturquette, sboyd,
Bartłomiej Żołnierkiewicz, kgene, mark.rutland,
robh+dt, Chanwoo Choi, kyungmin.park, Andrzej Hajda,
Marek Szyprowski, s.nawrocki, myungjoo.ham
In-Reply-To: <CAJKOXPfHgmBo9NX6jO8qSqXjN1pFmnKkQEWbou+q7-BDq2XKQg@mail.gmail.com>
Hi Krzysztof,
On 7/17/19 10:39 AM, Krzysztof Kozlowski wrote:
> On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>>
>> The FSYS and FSYS2 buses have similar characteristics and both have max
>> frequency 240MHz. The old OPP table bus_fsys_apb_opp_table should be used
>> only to FSYS APB bus because APB max frequency is 200MHz.
>> The new OPPs for FSYS should increase its performance and related devices.
>
> I do not understand the explanation. You say that there are two buses
> - FSYS and FSYS2 - and old OPP table should be used for FSYS APB but
> you remove the old one (by renaming). Or which one is the 'old one'
> here? The reason is speed... wait, what? Usually DTS should describe
> the HW so I imagine that proper opp table should be used for proper
> bus. It surprised me that we switch a bus to different OPP table just
> because of speed concerns. It should be correctness concern.
>
> Please clarify and reword all this.
>
> I am also not sure how this relates with previous patch - whether you
> are fixing independent issues. Maybe because I do not see the issue
> fixed... change the commit title and adjust the messages to focus WHY
> you are doing it. For small fixes WHAT you are doing is rather obvious
> so commit msg (and title) should not focus on it.
I don't know how familiar you are with AMBA standard or general concept
of NoC, so I am not sure if the explanation below would be sufficient.
There are 3 buses: FSYS, FSYS2, FSYS APB. The first two are connecting
AXI Slave/Master interfaces of the IP blocks. They are dedicated to
transfer the data i.e. to MMC block using 128 bit bus width and 240MHz
clock. The 3rd is dedicated for accessing peripheral registers -
connecting to IP block interfaces called APB3 slave.
As I mentioned in the comment the FSYS and FSYS2 are able to run faster
than the APB bus.
Thus, changing the old implementation which pinned FSYS and FSYS APB
to the same OPP table is wrong. The right connection made by OPP
reference should be FSYS and FSYS2 with also 240MHz max freq inside.
I have discussed offline with Bartek and I will squash DT patches to
an atomic-change-with-OPPs-and-PLL-rate-for-all-children, with more
detailed comment in the commit message describing the old state and the
new one.
Thank you for the review.
Regards,
Lukasz
>
> Best regards,
> Krzysztof
>
>>
>> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
>> ---
>> arch/arm/boot/dts/exynos5420.dtsi | 6 +++---
>> 1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
>> index 941c58bdd809..c7fc4b829b2a 100644
>> --- a/arch/arm/boot/dts/exynos5420.dtsi
>> +++ b/arch/arm/boot/dts/exynos5420.dtsi
>> @@ -995,7 +995,7 @@
>> compatible = "samsung,exynos-bus";
>> clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
>> clock-names = "bus";
>> - operating-points-v2 = <&bus_fsys_apb_opp_table>;
>> + operating-points-v2 = <&bus_fsys_opp_table>;
>> status = "disabled";
>> };
>>
>> @@ -1003,7 +1003,7 @@
>> compatible = "samsung,exynos-bus";
>> clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
>> clock-names = "bus";
>> - operating-points-v2 = <&bus_fsys2_opp_table>;
>> + operating-points-v2 = <&bus_fsys_opp_table>;
>> status = "disabled";
>> };
>>
>> @@ -1157,7 +1157,7 @@
>> };
>> };
>>
>> - bus_fsys2_opp_table: opp_table5 {
>> + bus_fsys_opp_table: opp_table5 {
>> compatible = "operating-points-v2";
>>
>> opp00 {
>> --
>> 2.17.1
>>
>
>
^ permalink raw reply
* Re: [PATCH v1 25/50] ARM: dts: exynos: add 300MHz to bus_disp1_fimd in Exynos5420
From: Krzysztof Kozlowski @ 2019-07-17 10:04 UTC (permalink / raw)
To: Lukasz Luba
Cc: mark.rutland, devicetree, linux-samsung-soc@vger.kernel.org,
Bartłomiej Żołnierkiewicz, sboyd, mturquette,
linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi, kyungmin.park,
kgene, myungjoo.ham, s.nawrocki, linux-clk, linux-arm-kernel,
Marek Szyprowski
In-Reply-To: <20190715124417.4787-26-l.luba@partner.samsung.com>
On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> According to the documentation max frequency for ACLK300_DISP1 is 300MHz.
> Add an OPP which makes it possible to use the full performance when needed.
Squash it with #23.
BR,
Krzysztof
^ permalink raw reply
* Re: [PATCH v1 43/50] ARM: dts: exynos: add bus_isp in Exynos5422
From: Krzysztof Kozlowski @ 2019-07-17 10:02 UTC (permalink / raw)
To: Lukasz Luba
Cc: mark.rutland, devicetree, linux-samsung-soc@vger.kernel.org,
Bartłomiej Żołnierkiewicz, sboyd, mturquette,
linux-kernel, robh+dt, Andrzej Hajda, Chanwoo Choi, kyungmin.park,
kgene, myungjoo.ham, s.nawrocki, linux-clk, linux-arm-kernel,
Marek Szyprowski
In-Reply-To: <20190715124417.4787-44-l.luba@partner.samsung.com>
On Mon, 15 Jul 2019 at 14:45, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> Add bus_isp which changes ACLK400_ISP clock speed according to the bus
> documentation in the documentation. The bus_isp OPP table has been
> aligned to the new parent rate.
Title and msg needs fixing.
Please squash it with patch 18.
Best regards,
Krzysztof
> This patch sets the proper parent and
> picks the init frequency before the devfreq governor starts working.
> It sets also parent rate (DPLL to 1200MHz).
>
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
> arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> index 990fe03fce75..852cb3dd495d 100644
> --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
> @@ -166,6 +166,18 @@
> status = "okay";
> };
>
> +&bus_isp {
> + devfreq = <&bus_wcore>;
> + assigned-clocks = <&clock CLK_MOUT_ACLK400_ISP>,
> + <&clock CLK_MOUT_SW_ACLK400_ISP>,
> + <&clock CLK_DOUT_ACLK400_ISP>,
> + <&clock CLK_FOUT_DPLL>;
> + assigned-clock-parents = <&clock CLK_MOUT_SCLK_DPLL>,
> + <&clock CLK_DOUT_ACLK400_ISP>;
> + assigned-clock-rates = <0>, <0>, <400000000>, <1200000000>;
> + status = "okay";
> +};
> +
> &cpu0 {
> cpu-supply = <&buck6_reg>;
> };
> --
> 2.17.1
>
^ permalink raw reply
* [PATCH] arm64: dts: imx8mq: fix SAI compatible
From: Lucas Stach @ 2019-07-17 9:54 UTC (permalink / raw)
To: Shawn Guo
Cc: devicetree, patchwork-lst, NXP Linux Team, kernel, Fabio Estevam,
linux-arm-kernel
The i.MX8M SAI block is not compatible with the i.MX6SX one, as the
register layout has changed due to two version registers being added
at the beginning of the address map. Remove the bogus compatible.
Fixes: 8c61538dc945 "arm64: dts: imx8mq: Add SAI2 node"
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 9326bd4150a3..0c533c66b340 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -718,8 +718,7 @@
sai2: sai@308b0000 {
#sound-dai-cells = <0>;
- compatible = "fsl,imx8mq-sai",
- "fsl,imx6sx-sai";
+ compatible = "fsl,imx8mq-sai";
reg = <0x308b0000 0x10000>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
--
2.20.1
^ permalink raw reply related
* RE: [v5,2/2] Documentation: dt: binding: rtc: add binding for ftm alarm driver
From: Biwen Li @ 2019-07-17 9:37 UTC (permalink / raw)
To: Leo Li, a.zummo@towertech.it, alexandre.belloni@bootlin.com,
robh+dt@kernel.org
Cc: linux-rtc@vger.kernel.org, linux-kernel@vger.kernel.org,
Xiaobo Xie, Jiafei Pan, Ran Wang, mark.rutland@arm.com,
devicetree@vger.kernel.org
In-Reply-To: <VE1PR04MB668718A642D1E521BF5F3F198FCE0@VE1PR04MB6687.eurprd04.prod.outlook.com>
> > From: Biwen Li <biwen.li@nxp.com>
> > Sent: Tuesday, July 16, 2019 5:17 AM
> > To: a.zummo@towertech.it; alexandre.belloni@bootlin.com; Leo Li
> > <leoyang.li@nxp.com>; robh+dt@kernel.org
> > Cc: linux-rtc@vger.kernel.org; linux-kernel@vger.kernel.org; Xiaobo
> > Xie <xiaobo.xie@nxp.com>; Jiafei Pan <jiafei.pan@nxp.com>; Ran Wang
> > <ran.wang_1@nxp.com>; mark.rutland@arm.com;
> > devicetree@vger.kernel.org; Biwen Li <biwen.li@nxp.com>
> > Subject: [v5,2/2] Documentation: dt: binding: rtc: add binding for ftm
> > alarm driver
> >
> > The patch adds binding for ftm alarm driver
> >
> > Signed-off-by: Biwen Li <biwen.li@nxp.com>
> > ---
> > Change in v5:
> > - None
> >
> > Change in v4:
> > - add note about dts and kernel options
> > - add aliases in example
> >
> > Change in v3:
> > - remove reg-names property
> > - correct cells number
> >
> > Change in v2:
> > - replace ls1043a with ls1088a as example
> > - add rcpm node and fsl,rcpm-wakeup property
> >
> >
> > .../bindings/rtc/rtc-fsl-ftm-alarm.txt | 49 +++++++++++++++++++
> > 1 file changed, 49 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/rtc/rtc-fsl-ftm-
> > alarm.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/rtc/rtc-fsl-ftm-alarm.txt
> > b/Documentation/devicetree/bindings/rtc/rtc-fsl-ftm-alarm.txt
> > new file mode 100644
> > index 000000000000..fb018065406c
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/rtc/rtc-fsl-ftm-alarm.txt
> > @@ -0,0 +1,49 @@
> > +Freescale FlexTimer Module (FTM) Alarm
> > +
> > +Note:
> > +- The driver depends on RCPM driver
> > + to wake up system in sleep.
> > +- Need stop using RTC_HCTOSYS or use the DT aliases
> > + to ensure the driver is not used as the primary RTC.
> > + (Select DT aliases defaultly)
> > +
> > +Required properties:
> > +- compatible : Should be "fsl,<chip>-ftm-alarm", the
> > + supported chips include
> > + "fsl,ls1012a-ftm-alarm"
> > + "fsl,ls1021a-ftm-alarm"
> > + "fsl,ls1028a-ftm-alarm"
> > + "fsl,ls1043a-ftm-alarm"
> > + "fsl,ls1046a-ftm-alarm"
> > + "fsl,ls1088a-ftm-alarm"
> > + "fsl,ls208xa-ftm-alarm"
> > +- reg : Specifies base physical address and size of the register sets
> > +for the
> > + FlexTimer Module and base physical address of IP Powerdown
> > +Exception
> > Control
> > + Register.
>
> You removed the IP Powerdown exception register in the examples, but not
> here.
Ok,I will remove it in v6.
>
> > +- interrupts : Should be the FlexTimer Module interrupt.
> > +- fsl,rcpm-wakeup property and rcpm node : Please refer
> > + Documentation/devicetree/bindings/soc/fsl/rcpm.txt
> > +
> > +Optional properties:
> > +- big-endian: If the host controller is big-endian mode, specify this property.
> > + The default endian mode is little-endian.
> > +
> > +Example:
> > +aliases {
> > + ...
> > + rtc1 = ftm_alarm0; /* Use flextimer alarm driver as /dev/rtc1 */
> > + ...
> > +};
> > +
> > +rcpm: rcpm@1e34040 {
> > + compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
> > + reg = <0x0 0x1e34040 0x0 0x18>;
> > + fsl,#rcpm-wakeup-cells = <6>;
> > +};
> > +
> > +ftm_alarm0: timer@2800000 {
> > + compatible = "fsl,ls1088a-ftm-alarm";
> > + reg = <0x0 0x2800000 0x0 0x10000>;
> > + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
> > + interrupts = <0 44 4>;
> > +};
> > --
> > 2.17.1
^ permalink raw reply
* [PATCH 5/5] arm: dts: add jpeg enc device tree node
From: Xia Jiang @ 2019-07-17 9:30 UTC (permalink / raw)
To: Hans Verkuil, Rob Herring, Matthias Brugger, Rick Chang
Cc: linux-media, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Marek Szyprowski, Tomasz Figa, srv_heupstream,
Xia Jiang
In-Reply-To: <20190717093034.22826-1-xia.jiang@mediatek.com>
add jpeg enc device tree node
Change-Id: I901602f04540d619a490746ed61c8cd8b420b051
Signed-off-by: Xia Jiang <xia.jiang@mediatek.com>
---
arch/arm/boot/dts/mt2701.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 51e1305c6471..560f27fd9d9e 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -569,6 +569,18 @@
<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
};
+ jpegenc: jpegenc@1500a000 {
+ compatible = "mediatek,mt2701-jpgenc", "mediatek,mtk-jpgenc";
+ reg = <0 0x1500a000 0 0x1000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&imgsys CLK_IMG_VENC>;
+ clock-names = "jpgenc";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
+ mediatek,larb = <&larb2>;
+ iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
+ <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
+ };
+
vdecsys: syscon@16000000 {
compatible = "mediatek,mt2701-vdecsys", "syscon";
reg = <0 0x16000000 0 0x1000>;
--
2.18.0
^ permalink raw reply related
* [PATCH 4/5] media: platform: change GPLv2 license to SPDX
From: Xia Jiang @ 2019-07-17 9:30 UTC (permalink / raw)
To: Hans Verkuil, Rob Herring, Matthias Brugger, Rick Chang
Cc: linux-media, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Marek Szyprowski, Tomasz Figa, srv_heupstream,
Xia Jiang
In-Reply-To: <20190717093034.22826-1-xia.jiang@mediatek.com>
Switch GPLv2 license to SPDX license.
Change-Id: I2311eb85c06bbf93181f77f1ac6b09780efa8795
Signed-off-by: Xia Jiang <xia.jiang@mediatek.com>
---
drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c | 9 +--------
drivers/media/platform/mtk-jpeg/mtk_jpeg_core.h | 9 +--------
drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.c | 9 +--------
drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.h | 9 +--------
drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.c | 9 +--------
drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.h | 9 +--------
drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_reg.h | 9 +--------
7 files changed, 7 insertions(+), 56 deletions(-)
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c b/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c
index b2d6537e8c34..1ec1a9953b7d 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c
@@ -1,17 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2016 MediaTek Inc.
* Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
* Rick Chang <rick.chang@mediatek.com>
* Xia Jiang <xia.jiang@mediatek.com>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/clk.h>
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.h b/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.h
index 65ef920651a5..34cd139ee502 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.h
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.h
@@ -1,17 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2016 MediaTek Inc.
* Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
* Rick Chang <rick.chang@mediatek.com>
* Xia Jiang <xia.jiang@mediatek.com>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef _MTK_JPEG_CORE_H
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.c b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.c
index aad834d98059..0a8200a0a5c6 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.c
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.c
@@ -1,16 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2016 MediaTek Inc.
* Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
* Rick Chang <rick.chang@mediatek.com>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/io.h>
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.h b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.h
index 725ce94fd58f..be9a756d6242 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.h
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.h
@@ -1,17 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2016 MediaTek Inc.
* Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
* Rick Chang <rick.chang@mediatek.com>
* Xia Jiang <xia.jiang@mediatek.com>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef _MTK_JPEG_DEC_HW_H
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.c b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.c
index c887f90c3a66..c63d61a957a5 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.c
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.c
@@ -1,16 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2016 MediaTek Inc.
* Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
* Rick Chang <rick.chang@mediatek.com>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/kernel.h>
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.h b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.h
index fdad7f2da6be..8760ff71d38f 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.h
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.h
@@ -1,16 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2016 MediaTek Inc.
* Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
* Rick Chang <rick.chang@mediatek.com>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef _MTK_JPEG_PARSE_H
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_reg.h b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_reg.h
index fc490d62b012..e01470449b8b 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_reg.h
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_reg.h
@@ -1,16 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2016 MediaTek Inc.
* Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
* Rick Chang <rick.chang@mediatek.com>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef _MTK_JPEG_REG_H
--
2.18.0
^ permalink raw reply related
* [PATCH 3/5] media: platform: Add jpeg enc feature
From: Xia Jiang @ 2019-07-17 9:30 UTC (permalink / raw)
To: Hans Verkuil, Rob Herring, Matthias Brugger, Rick Chang
Cc: linux-media, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Marek Szyprowski, Tomasz Figa, srv_heupstream,
Xia Jiang
In-Reply-To: <20190717093034.22826-1-xia.jiang@mediatek.com>
Add mtk jpeg encode v4l2 driver based on jpeg decode, because that jpeg
decode and encode have great similarities with function operation.
add EXIF enable control for jpeg encode.
Change-Id: I38bf86a372f69d42a4680c4d772b64a30e81d7be
Signed-off-by: Xia Jiang <xia.jiang@mediatek.com>
---
drivers/media/platform/mtk-jpeg/Makefile | 5 +-
.../media/platform/mtk-jpeg/mtk_jpeg_core.c | 740 ++++++++++++++----
.../media/platform/mtk-jpeg/mtk_jpeg_core.h | 114 ++-
.../media/platform/mtk-jpeg/mtk_jpeg_dec_hw.h | 7 +-
.../media/platform/mtk-jpeg/mtk_jpeg_enc_hw.c | 175 +++++
.../media/platform/mtk-jpeg/mtk_jpeg_enc_hw.h | 60 ++
.../platform/mtk-jpeg/mtk_jpeg_enc_reg.h | 49 ++
drivers/media/v4l2-core/v4l2-ctrls.c | 1 +
include/uapi/linux/v4l2-controls.h | 2 +
9 files changed, 986 insertions(+), 167 deletions(-)
create mode 100644 drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_hw.c
create mode 100644 drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_hw.h
create mode 100644 drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_reg.h
diff --git a/drivers/media/platform/mtk-jpeg/Makefile b/drivers/media/platform/mtk-jpeg/Makefile
index 994fcd66069c..c2d7774e59fb 100644
--- a/drivers/media/platform/mtk-jpeg/Makefile
+++ b/drivers/media/platform/mtk-jpeg/Makefile
@@ -1,2 +1,5 @@
-mtk_jpeg-objs := mtk_jpeg_core.o mtk_jpeg_dec_hw.o mtk_jpeg_dec_parse.o
+mtk_jpeg-objs := mtk_jpeg_core.o \
+ mtk_jpeg_dec_hw.o \
+ mtk_jpeg_dec_parse.o \
+ mtk_jpeg_enc_hw.o
obj-$(CONFIG_VIDEO_MEDIATEK_JPEG) += mtk_jpeg.o
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c b/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c
index 49e3b5284006..b2d6537e8c34 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c
@@ -2,6 +2,7 @@
* Copyright (c) 2016 MediaTek Inc.
* Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
* Rick Chang <rick.chang@mediatek.com>
+ * Xia Jiang <xia.jiang@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -31,6 +32,7 @@
#include <media/videobuf2-dma-contig.h>
#include <soc/mediatek/smi.h>
+#include "mtk_jpeg_enc_hw.h"
#include "mtk_jpeg_dec_hw.h"
#include "mtk_jpeg_core.h"
#include "mtk_jpeg_dec_parse.h"
@@ -39,7 +41,8 @@ static struct mtk_jpeg_fmt mtk_jpeg_formats[] = {
{
.fourcc = V4L2_PIX_FMT_JPEG,
.colplanes = 1,
- .flags = MTK_JPEG_FMT_FLAG_DEC_OUTPUT,
+ .flags = MTK_JPEG_FMT_FLAG_DEC_OUTPUT |
+ MTK_JPEG_FMT_FLAG_ENC_CAPTURE,
},
{
.fourcc = V4L2_PIX_FMT_YUV420M,
@@ -59,6 +62,42 @@ static struct mtk_jpeg_fmt mtk_jpeg_formats[] = {
.v_align = 3,
.flags = MTK_JPEG_FMT_FLAG_DEC_CAPTURE,
},
+ {
+ .fourcc = V4L2_PIX_FMT_NV12M,
+ .h_sample = {4, 2, 2},
+ .v_sample = {4, 2, 2},
+ .colplanes = 2,
+ .h_align = 4,
+ .v_align = 4,
+ .flags = MTK_JPEG_FMT_FLAG_ENC_OUTPUT,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_NV21M,
+ .h_sample = {4, 2, 2},
+ .v_sample = {4, 2, 2},
+ .colplanes = 2,
+ .h_align = 4,
+ .v_align = 4,
+ .flags = MTK_JPEG_FMT_FLAG_ENC_OUTPUT,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_YUYV,
+ .h_sample = {4, 2, 2},
+ .v_sample = {4, 4, 4},
+ .colplanes = 1,
+ .h_align = 4,
+ .v_align = 3,
+ .flags = MTK_JPEG_FMT_FLAG_ENC_OUTPUT,
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_YVYU,
+ .h_sample = {4, 2, 2},
+ .v_sample = {4, 4, 4},
+ .colplanes = 1,
+ .h_align = 4,
+ .v_align = 3,
+ .flags = MTK_JPEG_FMT_FLAG_ENC_OUTPUT,
+ },
};
#define MTK_JPEG_NUM_FORMATS ARRAY_SIZE(mtk_jpeg_formats)
@@ -73,11 +112,19 @@ struct mtk_jpeg_src_buf {
struct list_head list;
int flags;
struct mtk_jpeg_dec_param dec_param;
+ struct mtk_jpeg_enc_param enc_param;
};
+#define MTK_MAX_CTRLS_HINT 20
+
static int debug;
module_param(debug, int, 0644);
+static inline struct mtk_jpeg_ctx *ctrl_to_ctx(struct v4l2_ctrl *ctrl)
+{
+ return container_of(ctrl->handler, struct mtk_jpeg_ctx, ctrl_hdl);
+}
+
static inline struct mtk_jpeg_ctx *mtk_jpeg_fh_to_ctx(struct v4l2_fh *fh)
{
return container_of(fh, struct mtk_jpeg_ctx, fh);
@@ -94,10 +141,81 @@ static int mtk_jpeg_querycap(struct file *file, void *priv,
{
struct mtk_jpeg_dev *jpeg = video_drvdata(file);
- strscpy(cap->driver, MTK_JPEG_NAME " decoder", sizeof(cap->driver));
- strscpy(cap->card, MTK_JPEG_NAME " decoder", sizeof(cap->card));
- snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
- dev_name(jpeg->dev));
+ strscpy(cap->driver, MTK_JPEG_NAME, sizeof(cap->driver));
+ if (jpeg->mode == MTK_JPEG_ENC)
+ strscpy(cap->card, MTK_JPEG_NAME " encoder", sizeof(cap->card));
+ else
+ strscpy(cap->card, MTK_JPEG_NAME " decoder", sizeof(cap->card));
+ snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
+ dev_name(jpeg->dev));
+
+ return 0;
+}
+
+static int vidioc_jpeg_s_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct mtk_jpeg_ctx *ctx = ctrl_to_ctx(ctrl);
+ struct jpeg_enc_param *p = &ctx->jpeg_param;
+ struct mtk_jpeg_dev *jpeg = ctx->jpeg;
+ int ret = 0;
+
+ switch (ctrl->id) {
+ case V4L2_CID_JPEG_RESTART_INTERVAL:
+ p->restart_interval = ctrl->val;
+ break;
+ case V4L2_CID_JPEG_COMPRESSION_QUALITY:
+ p->enc_quality = ctrl->val;
+ break;
+ case V4L2_CID_JPEG_ENABLE_EXIF:
+ p->enable_exif = ctrl->val;
+ break;
+ }
+
+ v4l2_dbg(2, debug, &jpeg->v4l2_dev, "%s val = %d",
+ v4l2_ctrl_get_name(ctrl->id), ctrl->val);
+
+ return ret;
+}
+
+static const struct v4l2_ctrl_ops mtk_jpeg_ctrl_ops = {
+ .s_ctrl = vidioc_jpeg_s_ctrl,
+};
+
+int mtk_jpeg_ctrls_setup(struct mtk_jpeg_ctx *ctx)
+{
+ const struct v4l2_ctrl_ops *ops = &mtk_jpeg_ctrl_ops;
+ struct v4l2_ctrl_handler *handler = &ctx->ctrl_hdl;
+ struct mtk_jpeg_dev *jpeg = ctx->jpeg;
+
+ v4l2_ctrl_handler_init(handler, MTK_MAX_CTRLS_HINT);
+
+ if (jpeg->mode == MTK_JPEG_ENC) {
+ v4l2_ctrl_new_std(handler, ops, V4L2_CID_JPEG_RESTART_INTERVAL,
+ 0, 100, 1, 0);
+ if (handler->error) {
+ v4l2_err(&jpeg->v4l2_dev, "V4L2_CID_JPEG_RESTART_INTERVAL Init",
+ "control handler fail %d\n", handler->error);
+ return handler->error;
+ }
+ v4l2_ctrl_new_std(handler, ops,
+ V4L2_CID_JPEG_COMPRESSION_QUALITY, 48, 100, 1,
+ 90);
+ if (handler->error) {
+ v4l2_err(&jpeg->v4l2_dev, "V4L2_CID_JPEG_COMPRESSION_QUALITY",
+ "Init control handler fail %d\n",
+ handler->error);
+ return handler->error;
+ }
+ v4l2_ctrl_new_std(handler, ops, V4L2_CID_JPEG_ENABLE_EXIF, 0,
+ 1, 1, 0);
+ if (handler->error) {
+ v4l2_err(&jpeg->v4l2_dev, "V4L2_CID_JPEG_ENABLE_EXIF Init",
+ "control handler fail %d\n", handler->error);
+ return handler->error;
+ }
+ }
+
+ v4l2_ctrl_handler_setup(&ctx->ctrl_hdl);
return 0;
}
@@ -126,23 +244,29 @@ static int mtk_jpeg_enum_fmt(struct mtk_jpeg_fmt *mtk_jpeg_formats, int n,
static int mtk_jpeg_enum_fmt_vid_cap(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
+ struct mtk_jpeg_ctx *ctx = mtk_jpeg_fh_to_ctx(priv);
+
return mtk_jpeg_enum_fmt(mtk_jpeg_formats, MTK_JPEG_NUM_FORMATS, f,
+ ctx->jpeg->mode == MTK_JPEG_ENC ?
+ MTK_JPEG_FMT_FLAG_ENC_CAPTURE :
MTK_JPEG_FMT_FLAG_DEC_CAPTURE);
}
static int mtk_jpeg_enum_fmt_vid_out(struct file *file, void *priv,
struct v4l2_fmtdesc *f)
{
+ struct mtk_jpeg_ctx *ctx = mtk_jpeg_fh_to_ctx(priv);
+
return mtk_jpeg_enum_fmt(mtk_jpeg_formats, MTK_JPEG_NUM_FORMATS, f,
+ ctx->jpeg->mode == MTK_JPEG_ENC ?
+ MTK_JPEG_FMT_FLAG_ENC_OUTPUT :
MTK_JPEG_FMT_FLAG_DEC_OUTPUT);
}
-static struct mtk_jpeg_q_data *mtk_jpeg_get_q_data(struct mtk_jpeg_ctx *ctx,
- enum v4l2_buf_type type)
+static struct mtk_jpeg_q_data *
+mtk_jpeg_get_q_data(struct mtk_jpeg_ctx *ctx, enum v4l2_buf_type type)
{
- if (V4L2_TYPE_IS_OUTPUT(type))
- return &ctx->out_q;
- return &ctx->cap_q;
+ return V4L2_TYPE_IS_OUTPUT(type) ? &ctx->out_q : &ctx->cap_q;
}
static struct mtk_jpeg_fmt *mtk_jpeg_find_format(struct mtk_jpeg_ctx *ctx,
@@ -151,9 +275,14 @@ static struct mtk_jpeg_fmt *mtk_jpeg_find_format(struct mtk_jpeg_ctx *ctx,
{
unsigned int k, fmt_flag;
- fmt_flag = (fmt_type == MTK_JPEG_FMT_TYPE_OUTPUT) ?
- MTK_JPEG_FMT_FLAG_DEC_OUTPUT :
- MTK_JPEG_FMT_FLAG_DEC_CAPTURE;
+ if (ctx->jpeg->mode == MTK_JPEG_ENC)
+ fmt_flag = (fmt_type == MTK_JPEG_FMT_TYPE_OUTPUT) ?
+ MTK_JPEG_FMT_FLAG_ENC_OUTPUT :
+ MTK_JPEG_FMT_FLAG_ENC_CAPTURE;
+ else
+ fmt_flag = (fmt_type == MTK_JPEG_FMT_TYPE_OUTPUT) ?
+ MTK_JPEG_FMT_FLAG_DEC_OUTPUT :
+ MTK_JPEG_FMT_FLAG_DEC_CAPTURE;
for (k = 0; k < MTK_JPEG_NUM_FORMATS; k++) {
struct mtk_jpeg_fmt *fmt = &mtk_jpeg_formats[k];
@@ -210,7 +339,7 @@ static int mtk_jpeg_try_fmt_mplane(struct v4l2_format *f,
{
struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp;
struct mtk_jpeg_dev *jpeg = ctx->jpeg;
- int i;
+ int i, align_w, align_h;
memset(pix_mp->reserved, 0, sizeof(pix_mp->reserved));
pix_mp->field = V4L2_FIELD_NONE;
@@ -224,36 +353,111 @@ static int mtk_jpeg_try_fmt_mplane(struct v4l2_format *f,
pix_mp->pixelformat = fmt->fourcc;
if (q_type == MTK_JPEG_FMT_TYPE_OUTPUT) {
- struct v4l2_plane_pix_format *pfmt = &pix_mp->plane_fmt[0];
-
- mtk_jpeg_bound_align_image(&pix_mp->width, MTK_JPEG_MIN_WIDTH,
- MTK_JPEG_MAX_WIDTH, 0,
- &pix_mp->height, MTK_JPEG_MIN_HEIGHT,
- MTK_JPEG_MAX_HEIGHT, 0);
+ if (jpeg->mode == MTK_JPEG_ENC) {
+ pix_mp->height = clamp(pix_mp->height,
+ MTK_JPEG_MIN_HEIGHT,
+ MTK_JPEG_MAX_HEIGHT);
+ pix_mp->width = clamp(pix_mp->width,
+ MTK_JPEG_MIN_WIDTH,
+ MTK_JPEG_MAX_WIDTH);
+ align_w = pix_mp->width;
+ align_h = pix_mp->height;
+ align_w = round_up(align_w, 2);
+ if (pix_mp->num_planes == 1U) {
+ align_w = align_w << 1;
+ mtk_jpeg_bound_align_image(&align_w,
+ MTK_JPEG_MIN_WIDTH,
+ MTK_JPEG_MAX_WIDTH,
+ 5, &align_h,
+ MTK_JPEG_MIN_HEIGHT,
+ MTK_JPEG_MAX_HEIGHT,
+ 3);
+ pix_mp->plane_fmt[0].bytesperline = align_w;
+ pix_mp->plane_fmt[0].sizeimage =
+ align_w * align_h;
+ } else if (pix_mp->num_planes == 2U) {
+ mtk_jpeg_bound_align_image(&align_w,
+ MTK_JPEG_MIN_WIDTH,
+ MTK_JPEG_MAX_WIDTH,
+ 4, &align_h,
+ MTK_JPEG_MIN_HEIGHT,
+ MTK_JPEG_MAX_HEIGHT,
+ 4);
+ pix_mp->plane_fmt[0].bytesperline = align_w;
+ pix_mp->plane_fmt[0].sizeimage =
+ align_w * align_h;
+ pix_mp->plane_fmt[1].bytesperline = align_w;
+ pix_mp->plane_fmt[1].sizeimage =
+ (align_w * align_h) / 2;
+ } else {
+ v4l2_err(&ctx->jpeg->v4l2_dev,
+ "Unsupport num planes = %d\n",
+ pix_mp->num_planes);
+ }
+ goto end;
+ } else {
+ struct v4l2_plane_pix_format *pfmt =
+ &pix_mp->plane_fmt[0];
+
+ mtk_jpeg_bound_align_image(&pix_mp->width,
+ MTK_JPEG_MIN_WIDTH,
+ MTK_JPEG_MAX_WIDTH, 0,
+ &pix_mp->height,
+ MTK_JPEG_MIN_HEIGHT,
+ MTK_JPEG_MAX_HEIGHT, 0);
- memset(pfmt->reserved, 0, sizeof(pfmt->reserved));
pfmt->bytesperline = 0;
/* Source size must be aligned to 128 */
pfmt->sizeimage = mtk_jpeg_align(pfmt->sizeimage, 128);
if (pfmt->sizeimage == 0)
pfmt->sizeimage = MTK_JPEG_DEFAULT_SIZEIMAGE;
+
goto end;
}
+ }
/* type is MTK_JPEG_FMT_TYPE_CAPTURE */
- mtk_jpeg_bound_align_image(&pix_mp->width, MTK_JPEG_MIN_WIDTH,
- MTK_JPEG_MAX_WIDTH, fmt->h_align,
- &pix_mp->height, MTK_JPEG_MIN_HEIGHT,
- MTK_JPEG_MAX_HEIGHT, fmt->v_align);
+ if (jpeg->mode == MTK_JPEG_ENC) {
+ mtk_jpeg_bound_align_image(&pix_mp->width, MTK_JPEG_MIN_WIDTH,
+ MTK_JPEG_MAX_WIDTH, 0,
+ &pix_mp->height, MTK_JPEG_MIN_HEIGHT,
+ MTK_JPEG_MAX_HEIGHT, 0);
- for (i = 0; i < fmt->colplanes; i++) {
- struct v4l2_plane_pix_format *pfmt = &pix_mp->plane_fmt[i];
- u32 stride = pix_mp->width * fmt->h_sample[i] / 4;
- u32 h = pix_mp->height * fmt->v_sample[i] / 4;
+ if (fmt->fourcc == V4L2_PIX_FMT_JPEG) {
+ pix_mp->plane_fmt[0].bytesperline = 0;
+ pix_mp->plane_fmt[0].sizeimage =
+ mtk_jpeg_align(pix_mp->plane_fmt[0].sizeimage,
+ 128);
+ if (pix_mp->plane_fmt[0].sizeimage == 0)
+ pix_mp->plane_fmt[0].sizeimage =
+ MTK_JPEG_DEFAULT_SIZEIMAGE;
+ }
+ } else {
+ pix_mp->height = clamp(pix_mp->height, MTK_JPEG_MIN_HEIGHT,
+ MTK_JPEG_MAX_HEIGHT);
+ pix_mp->width = clamp(pix_mp->width, MTK_JPEG_MIN_WIDTH,
+ MTK_JPEG_MAX_WIDTH);
+ mtk_jpeg_bound_align_image(&pix_mp->width, MTK_JPEG_MIN_WIDTH,
+ MTK_JPEG_MAX_WIDTH, fmt->h_align,
+ &pix_mp->height,
+ MTK_JPEG_MIN_HEIGHT,
+ MTK_JPEG_MAX_HEIGHT, fmt->v_align);
+
+ for (i = 0; i < fmt->colplanes; i++) {
+ struct v4l2_plane_pix_format *pfmt =
+ &pix_mp->plane_fmt[i];
+ u32 stride = pix_mp->width * fmt->h_sample[i] / 4;
+ u32 h = pix_mp->height * fmt->v_sample[i] / 4;
+
+ pfmt->bytesperline = stride;
+ pfmt->sizeimage = stride * h;
+ }
+ }
+ for (i = 0; i < fmt->colplanes; i++) {
+ struct v4l2_plane_pix_format *pfmt =
+ &pix_mp->plane_fmt[i];
memset(pfmt->reserved, 0, sizeof(pfmt->reserved));
- pfmt->bytesperline = stride;
- pfmt->sizeimage = stride * h;
}
end:
v4l2_dbg(2, debug, &jpeg->v4l2_dev, "wxh:%ux%u\n",
@@ -454,9 +658,9 @@ static int mtk_jpeg_subscribe_event(struct v4l2_fh *fh,
switch (sub->type) {
case V4L2_EVENT_SOURCE_CHANGE:
return v4l2_src_change_event_subscribe(fh, sub);
- default:
- return -EINVAL;
}
+
+ return v4l2_ctrl_subscribe_event(fh, sub);
}
static int mtk_jpeg_g_selection(struct file *file, void *priv,
@@ -579,6 +783,13 @@ static int mtk_jpeg_queue_setup(struct vb2_queue *q,
if (!q_data)
return -EINVAL;
+ if (*num_planes) {
+ for (i = 0; i < *num_planes; i++)
+ if (sizes[i] < q_data->sizeimage[i])
+ return -EINVAL;
+ return 0;
+ }
+
*num_planes = q_data->fmt->colplanes;
for (i = 0; i < q_data->fmt->colplanes; i++) {
sizes[i] = q_data->sizeimage[i];
@@ -659,10 +870,92 @@ static void mtk_jpeg_set_queue_data(struct mtk_jpeg_ctx *ctx,
param->dec_w, param->dec_h);
}
+static void mtk_jpeg_set_param(struct mtk_jpeg_ctx *ctx,
+ struct mtk_jpeg_enc_param *param)
+{
+ struct mtk_jpeg_q_data *q_data_src = &ctx->out_q;
+ struct jpeg_enc_param *jpeg_params = &ctx->jpeg_param;
+ struct mtk_jpeg_dev *jpeg = ctx->jpeg;
+ u32 width_even;
+ u32 is_420;
+ u32 padding_width;
+ u32 padding_height;
+
+ switch (q_data_src->fmt->fourcc) {
+ case V4L2_PIX_FMT_YUYV:
+ param->enc_format = JPEG_YUV_FORMAT_YUYV;
+ break;
+ case V4L2_PIX_FMT_YVYU:
+ param->enc_format = JPEG_YUV_FORMAT_YVYU;
+ break;
+ case V4L2_PIX_FMT_NV12M:
+ param->enc_format = JPEG_YUV_FORMAT_NV12;
+ break;
+ case V4L2_PIX_FMT_NV21M:
+ param->enc_format = JPEG_YUV_FORMAT_NV12;
+ break;
+ default:
+ v4l2_err(&jpeg->v4l2_dev, "Unsupport fourcc =%d\n",
+ q_data_src->fmt->fourcc);
+ break;
+ }
+ param->enc_w = q_data_src->w;
+ param->enc_h = q_data_src->h;
+
+ if (jpeg_params->enc_quality >= 97)
+ param->enc_quality = JPEG_ENCODE_QUALITY_Q97;
+ else if (jpeg_params->enc_quality >= 95)
+ param->enc_quality = JPEG_ENCODE_QUALITY_Q95;
+ else if (jpeg_params->enc_quality >= 92)
+ param->enc_quality = JPEG_ENCODE_QUALITY_Q92;
+ else if (jpeg_params->enc_quality >= 90)
+ param->enc_quality = JPEG_ENCODE_QUALITY_Q90;
+ else if (jpeg_params->enc_quality >= 87)
+ param->enc_quality = JPEG_ENCODE_QUALITY_Q87;
+ else if (jpeg_params->enc_quality >= 84)
+ param->enc_quality = JPEG_ENCODE_QUALITY_Q84;
+ else if (jpeg_params->enc_quality >= 80)
+ param->enc_quality = JPEG_ENCODE_QUALITY_Q80;
+ else if (jpeg_params->enc_quality >= 74)
+ param->enc_quality = JPEG_ENCODE_QUALITY_Q74;
+ else if (jpeg_params->enc_quality >= 64)
+ param->enc_quality = JPEG_ENCODE_QUALITY_Q64;
+ else if (jpeg_params->enc_quality >= 60)
+ param->enc_quality = JPEG_ENCODE_QUALITY_Q60;
+ else
+ param->enc_quality = JPEG_ENCODE_QUALITY_Q48;
+
+ param->enable_exif = jpeg_params->enable_exif;
+ param->restart_interval = jpeg_params->restart_interval;
+
+ width_even = ((param->enc_w + 1) >> 1) << 1;
+ is_420 = (param->enc_format == JPEG_YUV_FORMAT_NV12 ||
+ param->enc_format == JPEG_YUV_FORMAT_NV12) ? 1 : 0;
+ padding_width = mtk_jpeg_align(param->enc_w, 16);
+ padding_height = mtk_jpeg_align(param->enc_h, is_420 ? 16 : 8);
+ if (!is_420)
+ width_even = width_even << 1;
+
+ param->img_stride = mtk_jpeg_align(width_even, (is_420 ? 16 : 32));
+ param->mem_stride = mtk_jpeg_align(width_even, (is_420 ? 16 : 32));
+ param->total_encdu =
+ ((padding_width >> 4) * (padding_height >> (is_420 ? 4 : 3)) *
+ (is_420 ? 6 : 4)) - 1;
+
+ v4l2_dbg(0, 2, &jpeg->v4l2_dev, "fmt %d, w,h %d,%d, enable_exif %d,",
+ "enc_quality %d, restart_interval %d,img_stride %d,",
+ "mem_stride %d,totalEncDu %d\n",
+ param->enc_format, param->enc_w, param->enc_h,
+ param->enable_exif, param->enc_quality,
+ param->restart_interval, param->img_stride,
+ param->mem_stride, param->total_encdu);
+}
+
static void mtk_jpeg_buf_queue(struct vb2_buffer *vb)
{
struct mtk_jpeg_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
struct mtk_jpeg_dec_param *param;
+ struct mtk_jpeg_enc_param *enc_param;
struct mtk_jpeg_dev *jpeg = ctx->jpeg;
struct mtk_jpeg_src_buf *jpeg_src_buf;
bool header_valid;
@@ -674,29 +967,45 @@ static void mtk_jpeg_buf_queue(struct vb2_buffer *vb)
goto end;
jpeg_src_buf = mtk_jpeg_vb2_to_srcbuf(vb);
- param = &jpeg_src_buf->dec_param;
- memset(param, 0, sizeof(*param));
-
- if (jpeg_src_buf->flags & MTK_JPEG_BUF_FLAGS_LAST_FRAME) {
- v4l2_dbg(1, debug, &jpeg->v4l2_dev, "Got eos\n");
- goto end;
- }
- header_valid = mtk_jpeg_parse(param, (u8 *)vb2_plane_vaddr(vb, 0),
- vb2_get_plane_payload(vb, 0));
- if (!header_valid) {
- v4l2_err(&jpeg->v4l2_dev, "Header invalid.\n");
- vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
- return;
- }
-
- if (ctx->state == MTK_JPEG_INIT) {
- struct vb2_queue *dst_vq = v4l2_m2m_get_vq(
- ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
+ if (jpeg->mode == MTK_JPEG_ENC) {
+ enc_param = &jpeg_src_buf->enc_param;
+ memset(enc_param, 0, sizeof(*enc_param));
+ mtk_jpeg_set_param(ctx, enc_param);
+ if (jpeg_src_buf->flags & MTK_JPEG_BUF_FLAGS_LAST_FRAME) {
+ v4l2_dbg(1, debug, &jpeg->v4l2_dev, "Got eos");
+ goto end;
+ }
+ if (ctx->state == MTK_JPEG_INIT)
+ ctx->state = MTK_JPEG_RUNNING;
+ } else {
+ param = &jpeg_src_buf->dec_param;
+ memset(param, 0, sizeof(*param));
+
+ if (jpeg_src_buf->flags & MTK_JPEG_BUF_FLAGS_LAST_FRAME) {
+ v4l2_dbg(1, debug, &jpeg->v4l2_dev, "Got eos\n");
+ goto end;
+ }
+ header_valid = mtk_jpeg_parse(param,
+ (u8 *)vb2_plane_vaddr(vb, 0),
+ vb2_get_plane_payload(vb, 0));
+ if (!header_valid) {
+ v4l2_err(&jpeg->v4l2_dev, "Header invalid.\n");
+ vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
+ return;
+ }
- mtk_jpeg_queue_src_chg_event(ctx);
- mtk_jpeg_set_queue_data(ctx, param);
- ctx->state = vb2_is_streaming(dst_vq) ?
- MTK_JPEG_SOURCE_CHANGE : MTK_JPEG_RUNNING;
+ if (ctx->state == MTK_JPEG_INIT) {
+ struct vb2_queue *dst_vq;
+
+ dst_vq = v4l2_m2m_get_vq
+ (ctx->fh.m2m_ctx,
+ V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
+ mtk_jpeg_queue_src_chg_event(ctx);
+ mtk_jpeg_set_queue_data(ctx, param);
+ ctx->state = vb2_is_streaming(dst_vq) ?
+ MTK_JPEG_SOURCE_CHANGE :
+ MTK_JPEG_RUNNING;
+ }
}
end:
v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, to_vb2_v4l2_buffer(vb));
@@ -739,16 +1048,16 @@ static void mtk_jpeg_stop_streaming(struct vb2_queue *q)
* subsampling. Update capture queue when the stream is off.
*/
if (ctx->state == MTK_JPEG_SOURCE_CHANGE &&
- !V4L2_TYPE_IS_OUTPUT(q->type)) {
+ !V4L2_TYPE_IS_OUTPUT(q->type) &&
+ ctx->jpeg->mode == MTK_JPEG_DEC) {
struct mtk_jpeg_src_buf *src_buf;
vb = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
src_buf = mtk_jpeg_vb2_to_srcbuf(&vb->vb2_buf);
mtk_jpeg_set_queue_data(ctx, &src_buf->dec_param);
ctx->state = MTK_JPEG_RUNNING;
- } else if (V4L2_TYPE_IS_OUTPUT(q->type)) {
+ } else if (V4L2_TYPE_IS_OUTPUT(q->type))
ctx->state = MTK_JPEG_INIT;
- }
while ((vb = mtk_jpeg_buf_remove(ctx, q->type)))
v4l2_m2m_buf_done(vb, VB2_BUF_STATE_ERROR);
@@ -803,6 +1112,28 @@ static int mtk_jpeg_set_dec_dst(struct mtk_jpeg_ctx *ctx,
return 0;
}
+static void mtk_jpeg_set_enc_dst(struct mtk_jpeg_ctx *ctx,
+ struct vb2_buffer *dst_buf,
+ struct mtk_jpeg_enc_bs *bs)
+{
+ bs->dma_addr = vb2_dma_contig_plane_dma_addr(dst_buf, 0) &
+ (~JPEG_ENC_DST_ADDR_OFFSET_MASK);
+ bs->dma_addr_offset = 0;
+ bs->dma_addr_offsetmask = bs->dma_addr & JPEG_ENC_DST_ADDR_OFFSET_MASK;
+ bs->size = mtk_jpeg_align(vb2_plane_size(dst_buf, 0), 128);
+}
+
+static void mtk_jpeg_set_enc_src(struct mtk_jpeg_ctx *ctx,
+ struct vb2_buffer *src_buf,
+ struct mtk_jpeg_enc_fb *fb)
+{
+ int i;
+
+ for (i = 0; i < src_buf->num_planes; i++)
+ fb->fb_addr[i].dma_addr =
+ vb2_dma_contig_plane_dma_addr(src_buf, i);
+}
+
static void mtk_jpeg_device_run(void *priv)
{
struct mtk_jpeg_ctx *ctx = priv;
@@ -813,6 +1144,8 @@ static void mtk_jpeg_device_run(void *priv)
struct mtk_jpeg_src_buf *jpeg_src_buf;
struct mtk_jpeg_bs bs;
struct mtk_jpeg_fb fb;
+ struct mtk_jpeg_enc_bs enc_bs;
+ struct mtk_jpeg_enc_fb enc_fb;
int i;
src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
@@ -823,30 +1156,45 @@ static void mtk_jpeg_device_run(void *priv)
for (i = 0; i < dst_buf->vb2_buf.num_planes; i++)
vb2_set_plane_payload(&dst_buf->vb2_buf, i, 0);
buf_state = VB2_BUF_STATE_DONE;
- goto dec_end;
+ goto device_run_end;
}
- if (mtk_jpeg_check_resolution_change(ctx, &jpeg_src_buf->dec_param)) {
- mtk_jpeg_queue_src_chg_event(ctx);
- ctx->state = MTK_JPEG_SOURCE_CHANGE;
- v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
- return;
- }
+ if (jpeg->mode == MTK_JPEG_ENC) {
+ mtk_jpeg_set_enc_dst(ctx, &dst_buf->vb2_buf, &enc_bs);
+ mtk_jpeg_set_enc_src(ctx, &src_buf->vb2_buf, &enc_fb);
+
+ spin_lock_irqsave(&jpeg->hw_lock, flags);
+ mtk_jpeg_enc_reset(jpeg->reg_base);
+ mtk_jpeg_enc_set_config(jpeg->reg_base,
+ &jpeg_src_buf->enc_param, &enc_bs,
+ &enc_fb);
+
+ mtk_jpeg_enc_start(jpeg->reg_base);
+ } else {
+ if (mtk_jpeg_check_resolution_change
+ (ctx, &jpeg_src_buf->dec_param)) {
+ mtk_jpeg_queue_src_chg_event(ctx);
+ ctx->state = MTK_JPEG_SOURCE_CHANGE;
+ v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
+ return;
+ }
- mtk_jpeg_set_dec_src(ctx, &src_buf->vb2_buf, &bs);
- if (mtk_jpeg_set_dec_dst(ctx, &jpeg_src_buf->dec_param, &dst_buf->vb2_buf, &fb))
- goto dec_end;
+ mtk_jpeg_set_dec_src(ctx, &src_buf->vb2_buf, &bs);
+ if (mtk_jpeg_set_dec_dst(ctx, &jpeg_src_buf->dec_param,
+ &dst_buf->vb2_buf, &fb))
+ goto device_run_end;
- spin_lock_irqsave(&jpeg->hw_lock, flags);
- mtk_jpeg_dec_reset(jpeg->dec_reg_base);
- mtk_jpeg_dec_set_config(jpeg->dec_reg_base,
- &jpeg_src_buf->dec_param, &bs, &fb);
+ spin_lock_irqsave(&jpeg->hw_lock, flags);
+ mtk_jpeg_dec_reset(jpeg->reg_base);
+ mtk_jpeg_dec_set_config(jpeg->reg_base,
+ &jpeg_src_buf->dec_param, &bs, &fb);
- mtk_jpeg_dec_start(jpeg->dec_reg_base);
+ mtk_jpeg_dec_start(jpeg->reg_base);
+ }
spin_unlock_irqrestore(&jpeg->hw_lock, flags);
return;
-dec_end:
+device_run_end:
v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
v4l2_m2m_buf_done(src_buf, buf_state);
@@ -906,30 +1254,30 @@ static void mtk_jpeg_clk_on(struct mtk_jpeg_dev *jpeg)
ret = mtk_smi_larb_get(jpeg->larb);
if (ret)
dev_err(jpeg->dev, "mtk_smi_larb_get larbvdec fail %d\n", ret);
- clk_prepare_enable(jpeg->clk_jdec_smi);
- clk_prepare_enable(jpeg->clk_jdec);
+ if (jpeg->mode == MTK_JPEG_DEC)
+ clk_prepare_enable(jpeg->clk_jpeg_smi);
+ clk_prepare_enable(jpeg->clk_jpeg);
}
static void mtk_jpeg_clk_off(struct mtk_jpeg_dev *jpeg)
{
- clk_disable_unprepare(jpeg->clk_jdec);
- clk_disable_unprepare(jpeg->clk_jdec_smi);
+ clk_disable_unprepare(jpeg->clk_jpeg);
+ if (jpeg->mode == MTK_JPEG_DEC)
+ clk_disable_unprepare(jpeg->clk_jpeg_smi);
mtk_smi_larb_put(jpeg->larb);
}
-static irqreturn_t mtk_jpeg_dec_irq(int irq, void *priv)
+static irqreturn_t mtk_jpeg_irq(int irq, void *priv)
{
struct mtk_jpeg_dev *jpeg = priv;
struct mtk_jpeg_ctx *ctx;
struct vb2_v4l2_buffer *src_buf, *dst_buf;
struct mtk_jpeg_src_buf *jpeg_src_buf;
enum vb2_buffer_state buf_state = VB2_BUF_STATE_ERROR;
- u32 dec_irq_ret;
- u32 dec_ret;
+ u32 irq_ret;
+ u32 ret, result_size;
int i;
- dec_ret = mtk_jpeg_dec_get_int_status(jpeg->dec_reg_base);
- dec_irq_ret = mtk_jpeg_dec_enum_result(dec_ret);
ctx = v4l2_m2m_get_curr_priv(jpeg->m2m_dev);
if (!ctx) {
v4l2_err(&jpeg->v4l2_dev, "Context is NULL\n");
@@ -940,21 +1288,42 @@ static irqreturn_t mtk_jpeg_dec_irq(int irq, void *priv)
dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
jpeg_src_buf = mtk_jpeg_vb2_to_srcbuf(&src_buf->vb2_buf);
- if (dec_irq_ret >= MTK_JPEG_DEC_RESULT_UNDERFLOW)
- mtk_jpeg_dec_reset(jpeg->dec_reg_base);
+ if (jpeg->mode == MTK_JPEG_ENC) {
+ ret = mtk_jpeg_enc_get_int_status(jpeg->reg_base);
+ irq_ret = mtk_jpeg_enc_enum_result(jpeg->reg_base, ret,
+ &result_size);
- if (dec_irq_ret != MTK_JPEG_DEC_RESULT_EOF_DONE) {
- dev_err(jpeg->dev, "decode failed\n");
- goto dec_end;
- }
+ if (irq_ret >= MTK_JPEG_ENC_RESULT_STALL)
+ mtk_jpeg_enc_reset(jpeg->reg_base);
+
+ if (irq_ret != MTK_JPEG_ENC_RESULT_DONE) {
+ dev_err(jpeg->dev, "encode failed\n");
+ goto irq_end;
+ }
+
+ vb2_set_plane_payload(&dst_buf->vb2_buf, 0,
+ result_size);
+ } else {
+ ret = mtk_jpeg_dec_get_int_status(jpeg->reg_base);
+ irq_ret = mtk_jpeg_dec_enum_result(ret);
- for (i = 0; i < dst_buf->vb2_buf.num_planes; i++)
- vb2_set_plane_payload(&dst_buf->vb2_buf, i,
- jpeg_src_buf->dec_param.comp_size[i]);
+ if (irq_ret >= MTK_JPEG_DEC_RESULT_UNDERFLOW)
+ mtk_jpeg_dec_reset(jpeg->reg_base);
+
+ if (irq_ret != MTK_JPEG_DEC_RESULT_EOF_DONE) {
+ dev_err(jpeg->dev, "decode failed\n");
+ goto irq_end;
+ }
+
+ for (i = 0; i < dst_buf->vb2_buf.num_planes; i++)
+ vb2_set_plane_payload
+ (&dst_buf->vb2_buf, i,
+ jpeg_src_buf->dec_param.comp_size[i]);
+ }
buf_state = VB2_BUF_STATE_DONE;
-dec_end:
+irq_end:
v4l2_m2m_buf_done(src_buf, buf_state);
v4l2_m2m_buf_done(dst_buf, buf_state);
v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
@@ -964,32 +1333,72 @@ static irqreturn_t mtk_jpeg_dec_irq(int irq, void *priv)
static void mtk_jpeg_set_default_params(struct mtk_jpeg_ctx *ctx)
{
struct mtk_jpeg_q_data *q = &ctx->out_q;
- int i;
+ int i, align_w, align_h;
+
+ ctx->fh.ctrl_handler = &ctx->ctrl_hdl;
ctx->colorspace = V4L2_COLORSPACE_JPEG,
ctx->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
ctx->quantization = V4L2_QUANTIZATION_DEFAULT;
ctx->xfer_func = V4L2_XFER_FUNC_DEFAULT;
- q->fmt = mtk_jpeg_find_format(ctx, V4L2_PIX_FMT_JPEG,
+ if (ctx->jpeg->mode == MTK_JPEG_ENC) {
+ q->w = MTK_JPEG_MIN_WIDTH;
+ q->h = MTK_JPEG_MIN_HEIGHT;
+
+ q->fmt = mtk_jpeg_find_format(ctx, V4L2_PIX_FMT_YUYV,
+ MTK_JPEG_FMT_TYPE_OUTPUT);
+
+ align_w = q->w;
+ align_h = q->h;
+ align_w = round_up(align_w, 2);
+ align_w = align_w << 1;
+ v4l_bound_align_image(&align_w,
+ MTK_JPEG_MIN_WIDTH,
+ MTK_JPEG_MAX_WIDTH, 5,
+ &align_h,
+ MTK_JPEG_MIN_HEIGHT,
+ MTK_JPEG_MAX_HEIGHT, 3, 0);
+
+ if (align_w < MTK_JPEG_MIN_WIDTH &&
+ (align_w + 32) <= MTK_JPEG_MAX_WIDTH)
+ align_w += 32;
+ if (align_h < MTK_JPEG_MIN_HEIGHT &&
+ (align_h + 8) <= MTK_JPEG_MAX_HEIGHT)
+ align_h += 8;
+
+ q->sizeimage[0] = align_w * align_h;
+ q->bytesperline[0] = align_w;
+ } else {
+ q->fmt = mtk_jpeg_find_format(ctx, V4L2_PIX_FMT_JPEG,
MTK_JPEG_FMT_TYPE_OUTPUT);
- q->w = MTK_JPEG_MIN_WIDTH;
- q->h = MTK_JPEG_MIN_HEIGHT;
- q->bytesperline[0] = 0;
- q->sizeimage[0] = MTK_JPEG_DEFAULT_SIZEIMAGE;
+ q->w = MTK_JPEG_MIN_WIDTH;
+ q->h = MTK_JPEG_MIN_HEIGHT;
+ q->bytesperline[0] = 0;
+ q->sizeimage[0] = MTK_JPEG_DEFAULT_SIZEIMAGE;
+ }
q = &ctx->cap_q;
- q->fmt = mtk_jpeg_find_format(ctx, V4L2_PIX_FMT_YUV420M,
+ if (ctx->jpeg->mode == MTK_JPEG_ENC) {
+ q->w = MTK_JPEG_MIN_WIDTH;
+ q->h = MTK_JPEG_MIN_HEIGHT;
+ q->fmt = mtk_jpeg_find_format(ctx, V4L2_PIX_FMT_JPEG,
+ MTK_JPEG_FMT_TYPE_CAPTURE);
+ q->bytesperline[0] = 0;
+ q->sizeimage[0] = MTK_JPEG_DEFAULT_SIZEIMAGE;
+ } else {
+ q->fmt = mtk_jpeg_find_format(ctx, V4L2_PIX_FMT_YUV420M,
MTK_JPEG_FMT_TYPE_CAPTURE);
- q->w = MTK_JPEG_MIN_WIDTH;
- q->h = MTK_JPEG_MIN_HEIGHT;
+ q->w = MTK_JPEG_MIN_WIDTH;
+ q->h = MTK_JPEG_MIN_HEIGHT;
- for (i = 0; i < q->fmt->colplanes; i++) {
- u32 stride = q->w * q->fmt->h_sample[i] / 4;
- u32 h = q->h * q->fmt->v_sample[i] / 4;
+ for (i = 0; i < q->fmt->colplanes; i++) {
+ u32 stride = q->w * q->fmt->h_sample[i] / 4;
+ u32 h = q->h * q->fmt->v_sample[i] / 4;
- q->bytesperline[i] = stride;
- q->sizeimage[i] = stride * h;
+ q->bytesperline[i] = stride;
+ q->sizeimage[i] = stride * h;
+ }
}
}
@@ -1021,6 +1430,13 @@ static int mtk_jpeg_open(struct file *file)
goto error;
}
+ ret = mtk_jpeg_ctrls_setup(ctx);
+ if (ret) {
+ v4l2_err(&jpeg->v4l2_dev, "Failed to setup controls() (%d)\n",
+ ret);
+ goto error;
+ }
+
mtk_jpeg_set_default_params(ctx);
mutex_unlock(&jpeg->lock);
return 0;
@@ -1041,6 +1457,7 @@ static int mtk_jpeg_release(struct file *file)
mutex_lock(&jpeg->lock);
v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
+ v4l2_ctrl_handler_free(&ctx->ctrl_hdl);
v4l2_fh_del(&ctx->fh);
v4l2_fh_exit(&ctx->fh);
kfree(ctx);
@@ -1065,6 +1482,7 @@ static int mtk_jpeg_clk_init(struct mtk_jpeg_dev *jpeg)
node = of_parse_phandle(jpeg->dev->of_node, "mediatek,larb", 0);
if (!node)
return -EINVAL;
+
pdev = of_find_device_by_node(node);
if (WARN_ON(!pdev)) {
of_node_put(node);
@@ -1074,19 +1492,24 @@ static int mtk_jpeg_clk_init(struct mtk_jpeg_dev *jpeg)
jpeg->larb = &pdev->dev;
- jpeg->clk_jdec = devm_clk_get(jpeg->dev, "jpgdec");
- if (IS_ERR(jpeg->clk_jdec))
- return PTR_ERR(jpeg->clk_jdec);
+ if (jpeg->mode == MTK_JPEG_ENC) {
+ jpeg->clk_jpeg = devm_clk_get(jpeg->dev, "jpgenc");
+ return PTR_ERR_OR_ZERO(jpeg->clk_jpeg);
+ }
- jpeg->clk_jdec_smi = devm_clk_get(jpeg->dev, "jpgdec-smi");
- return PTR_ERR_OR_ZERO(jpeg->clk_jdec_smi);
+ jpeg->clk_jpeg = devm_clk_get(jpeg->dev, "jpgdec");
+ if (IS_ERR(jpeg->clk_jpeg))
+ return PTR_ERR(jpeg->clk_jpeg);
+
+ jpeg->clk_jpeg_smi = devm_clk_get(jpeg->dev, "jpgdec-smi");
+ return PTR_ERR_OR_ZERO(jpeg->clk_jpeg_smi);
}
static int mtk_jpeg_probe(struct platform_device *pdev)
{
struct mtk_jpeg_dev *jpeg;
struct resource *res;
- int dec_irq;
+ int jpeg_irq;
int ret;
jpeg = devm_kzalloc(&pdev->dev, sizeof(*jpeg), GFP_KERNEL);
@@ -1096,28 +1519,26 @@ static int mtk_jpeg_probe(struct platform_device *pdev)
mutex_init(&jpeg->lock);
spin_lock_init(&jpeg->hw_lock);
jpeg->dev = &pdev->dev;
+ jpeg->mode = (enum mtk_jpeg_mode)of_device_get_match_data(jpeg->dev);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- jpeg->dec_reg_base = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(jpeg->dec_reg_base)) {
- ret = PTR_ERR(jpeg->dec_reg_base);
+ jpeg->reg_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(jpeg->reg_base)) {
+ ret = PTR_ERR(jpeg->reg_base);
return ret;
}
- res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- dec_irq = platform_get_irq(pdev, 0);
- if (!res || dec_irq < 0) {
- dev_err(&pdev->dev, "Failed to get dec_irq %d.\n", dec_irq);
- ret = -EINVAL;
- return ret;
+ jpeg_irq = platform_get_irq(pdev, 0);
+ if (jpeg_irq < 0) {
+ dev_err(&pdev->dev, "Failed to get jpeg_irq %d.\n", jpeg_irq);
+ return jpeg_irq;
}
- ret = devm_request_irq(&pdev->dev, dec_irq, mtk_jpeg_dec_irq, 0,
+ ret = devm_request_irq(&pdev->dev, jpeg_irq, mtk_jpeg_irq, 0,
pdev->name, jpeg);
if (ret) {
- dev_err(&pdev->dev, "Failed to request dec_irq %d (%d)\n",
- dec_irq, ret);
- ret = -EINVAL;
+ dev_err(&pdev->dev, "Failed to request jpeg_irq %d (%d)\n",
+ jpeg_irq, ret);
goto err_req_irq;
}
@@ -1141,33 +1562,35 @@ static int mtk_jpeg_probe(struct platform_device *pdev)
goto err_m2m_init;
}
- jpeg->dec_vdev = video_device_alloc();
- if (!jpeg->dec_vdev) {
+ jpeg->vfd_jpeg = video_device_alloc();
+ if (!jpeg->vfd_jpeg) {
ret = -ENOMEM;
- goto err_dec_vdev_alloc;
+ goto err_vfd_jpeg_alloc;
}
- snprintf(jpeg->dec_vdev->name, sizeof(jpeg->dec_vdev->name),
- "%s-dec", MTK_JPEG_NAME);
- jpeg->dec_vdev->fops = &mtk_jpeg_fops;
- jpeg->dec_vdev->ioctl_ops = &mtk_jpeg_ioctl_ops;
- jpeg->dec_vdev->minor = -1;
- jpeg->dec_vdev->release = video_device_release;
- jpeg->dec_vdev->lock = &jpeg->lock;
- jpeg->dec_vdev->v4l2_dev = &jpeg->v4l2_dev;
- jpeg->dec_vdev->vfl_dir = VFL_DIR_M2M;
- jpeg->dec_vdev->device_caps = V4L2_CAP_STREAMING |
+ snprintf(jpeg->vfd_jpeg->name, sizeof(jpeg->vfd_jpeg->name),
+ "%s-%s", MTK_JPEG_NAME,
+ jpeg->mode == MTK_JPEG_ENC ? "enc" : "dec");
+ jpeg->vfd_jpeg->fops = &mtk_jpeg_fops;
+ jpeg->vfd_jpeg->ioctl_ops = &mtk_jpeg_ioctl_ops;
+ jpeg->vfd_jpeg->minor = -1;
+ jpeg->vfd_jpeg->release = video_device_release;
+ jpeg->vfd_jpeg->lock = &jpeg->lock;
+ jpeg->vfd_jpeg->v4l2_dev = &jpeg->v4l2_dev;
+ jpeg->vfd_jpeg->vfl_dir = VFL_DIR_M2M;
+ jpeg->vfd_jpeg->device_caps = V4L2_CAP_STREAMING |
V4L2_CAP_VIDEO_M2M_MPLANE;
- ret = video_register_device(jpeg->dec_vdev, VFL_TYPE_GRABBER, 3);
+ ret = video_register_device(jpeg->vfd_jpeg, VFL_TYPE_GRABBER, -1);
if (ret) {
v4l2_err(&jpeg->v4l2_dev, "Failed to register video device\n");
- goto err_dec_vdev_register;
+ goto err_vfd_jpeg_register;
}
- video_set_drvdata(jpeg->dec_vdev, jpeg);
+ video_set_drvdata(jpeg->vfd_jpeg, jpeg);
v4l2_info(&jpeg->v4l2_dev,
- "decoder device registered as /dev/video%d (%d,%d)\n",
- jpeg->dec_vdev->num, VIDEO_MAJOR, jpeg->dec_vdev->minor);
+ "jpeg device %d registered as /dev/video%d (%d,%d)\n",
+ jpeg->mode, jpeg->vfd_jpeg->num, VIDEO_MAJOR,
+ jpeg->vfd_jpeg->minor);
platform_set_drvdata(pdev, jpeg);
@@ -1175,10 +1598,10 @@ static int mtk_jpeg_probe(struct platform_device *pdev)
return 0;
-err_dec_vdev_register:
- video_device_release(jpeg->dec_vdev);
+err_vfd_jpeg_register:
+ video_device_release(jpeg->vfd_jpeg);
-err_dec_vdev_alloc:
+err_vfd_jpeg_alloc:
v4l2_m2m_release(jpeg->m2m_dev);
err_m2m_init:
@@ -1198,8 +1621,8 @@ static int mtk_jpeg_remove(struct platform_device *pdev)
struct mtk_jpeg_dev *jpeg = platform_get_drvdata(pdev);
pm_runtime_disable(&pdev->dev);
- video_unregister_device(jpeg->dec_vdev);
- video_device_release(jpeg->dec_vdev);
+ video_unregister_device(jpeg->vfd_jpeg);
+ video_device_release(jpeg->vfd_jpeg);
v4l2_m2m_release(jpeg->m2m_dev);
v4l2_device_unregister(&jpeg->v4l2_dev);
@@ -1210,7 +1633,11 @@ static __maybe_unused int mtk_jpeg_pm_suspend(struct device *dev)
{
struct mtk_jpeg_dev *jpeg = dev_get_drvdata(dev);
- mtk_jpeg_dec_reset(jpeg->dec_reg_base);
+ if (jpeg->mode == MTK_JPEG_ENC)
+ mtk_jpeg_enc_reset(jpeg->reg_base);
+ else
+ mtk_jpeg_dec_reset(jpeg->reg_base);
+
mtk_jpeg_clk_off(jpeg);
return 0;
@@ -1221,7 +1648,10 @@ static __maybe_unused int mtk_jpeg_pm_resume(struct device *dev)
struct mtk_jpeg_dev *jpeg = dev_get_drvdata(dev);
mtk_jpeg_clk_on(jpeg);
- mtk_jpeg_dec_reset(jpeg->dec_reg_base);
+ if (jpeg->mode == MTK_JPEG_ENC)
+ mtk_jpeg_enc_reset(jpeg->reg_base);
+ else
+ mtk_jpeg_dec_reset(jpeg->reg_base);
return 0;
}
@@ -1257,11 +1687,15 @@ static const struct dev_pm_ops mtk_jpeg_pm_ops = {
static const struct of_device_id mtk_jpeg_match[] = {
{
.compatible = "mediatek,mt8173-jpgdec",
- .data = NULL,
+ .data = (void *)MTK_JPEG_DEC,
},
{
.compatible = "mediatek,mt2701-jpgdec",
- .data = NULL,
+ .data = (void *)MTK_JPEG_DEC,
+ },
+ {
+ .compatible = "mediatek,mtk-jpgenc",
+ .data = (void *)MTK_JPEG_ENC,
},
{},
};
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.h b/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.h
index 1a6cdfd4ea70..65ef920651a5 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.h
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.h
@@ -2,6 +2,7 @@
* Copyright (c) 2016 MediaTek Inc.
* Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
* Rick Chang <rick.chang@mediatek.com>
+ * Xia Jiang <xia.jiang@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -25,6 +26,8 @@
#define MTK_JPEG_FMT_FLAG_DEC_OUTPUT BIT(0)
#define MTK_JPEG_FMT_FLAG_DEC_CAPTURE BIT(1)
+#define MTK_JPEG_FMT_FLAG_ENC_OUTPUT BIT(2)
+#define MTK_JPEG_FMT_FLAG_ENC_CAPTURE BIT(3)
#define MTK_JPEG_FMT_TYPE_OUTPUT 1
#define MTK_JPEG_FMT_TYPE_CAPTURE 2
@@ -36,12 +39,63 @@
#define MTK_JPEG_DEFAULT_SIZEIMAGE (1 * 1024 * 1024)
+#define MTK_JPEG_ENCODE 0
+#define MTK_JPEG_DECODE 1
+
+/**
+ * enum mtk_jpeg_ctx_state - contex state of jpeg
+ */
enum mtk_jpeg_ctx_state {
MTK_JPEG_INIT = 0,
MTK_JPEG_RUNNING,
MTK_JPEG_SOURCE_CHANGE,
};
+/**
+ * enum mtk_jpeg_mode - mode of jpeg
+ */
+enum mtk_jpeg_mode {
+ MTK_JPEG_ENC,
+ MTK_JPEG_DEC,
+};
+
+/**
+ * enum jpeg_enc_yuv_fmt - yuv format of jpeg enc
+ */
+enum jpeg_enc_yuv_fmt {
+ JPEG_YUV_FORMAT_YUYV = 0,
+ JPEG_YUV_FORMAT_YVYU = 1,
+ JPEG_YUV_FORMAT_NV12 = 2,
+ JEPG_YUV_FORMAT_NV21 = 3,
+};
+
+/**
+ * enum JPEG_ENCODE_QUALITY_ENUM - number of jpeg encoder quality
+ */
+enum JPEG_ENCODE_QUALITY_ENUM {
+ JPEG_ENCODE_QUALITY_Q60 = 0x0,
+ JPEG_ENCODE_QUALITY_Q80 = 0x1,
+ JPEG_ENCODE_QUALITY_Q90 = 0x2,
+ JPEG_ENCODE_QUALITY_Q95 = 0x3,
+
+ JPEG_ENCODE_QUALITY_Q39 = 0x4,
+ JPEG_ENCODE_QUALITY_Q68 = 0x5,
+ JPEG_ENCODE_QUALITY_Q84 = 0x6,
+ JPEG_ENCODE_QUALITY_Q92 = 0x7,
+
+ JPEG_ENCODE_QUALITY_Q48 = 0x8,
+ JPEG_ENCODE_QUALITY_Q74 = 0xA,
+ JPEG_ENCODE_QUALITY_Q87 = 0xB,
+
+ JPEG_ENCODE_QUALITY_Q34 = 0xC,
+ JPEG_ENCODE_QUALITY_Q64 = 0xE,
+ JPEG_ENCODE_QUALITY_Q82 = 0xF,
+
+ JPEG_ENCODE_QUALITY_Q97 = 0x10,
+
+ JPEG_ENCODE_QUALITY_ALL = 0xFFFFFFFF
+};
+
/**
* struct mt_jpeg - JPEG IP abstraction
* @lock: the mutex protecting this structure
@@ -51,11 +105,12 @@ enum mtk_jpeg_ctx_state {
* @v4l2_dev: v4l2 device for mem2mem mode
* @m2m_dev: v4l2 mem2mem device data
* @alloc_ctx: videobuf2 memory allocator's context
- * @dec_vdev: video device node for decoder mem2mem mode
- * @dec_reg_base: JPEG registers mapping
- * @clk_jdec: JPEG hw working clock
- * @clk_jdec_smi: JPEG SMI bus clock
+ * @vfd_jpeg: video device node for jpeg mem2mem mode
+ * @reg_base: JPEG registers mapping
+ * @clk_jpeg: JPEG hw working clock
+ * @clk_jpeg_smi: JPEG SMI bus clock
* @larb: SMI device
+ * @mode: compression (encode) operation or decompression (decode)
*/
struct mtk_jpeg_dev {
struct mutex lock;
@@ -65,11 +120,12 @@ struct mtk_jpeg_dev {
struct v4l2_device v4l2_dev;
struct v4l2_m2m_dev *m2m_dev;
void *alloc_ctx;
- struct video_device *dec_vdev;
- void __iomem *dec_reg_base;
- struct clk *clk_jdec;
- struct clk *clk_jdec_smi;
+ struct video_device *vfd_jpeg;
+ void __iomem *reg_base;
+ struct clk *clk_jpeg;
+ struct clk *clk_jpeg_smi;
struct device *larb;
+ enum mtk_jpeg_mode mode;
};
/**
@@ -109,15 +165,51 @@ struct mtk_jpeg_q_data {
u32 sizeimage[VIDEO_MAX_PLANES];
};
+/**
+ * jpeg_enc_param - parameters of jpeg encode control
+ * @enable_exif: EXIF enable for jpeg encode mode
+ * @enc_quality: destination image quality in encode mode
+ * @restart_interval: JPEG restart interval for JPEG encoding
+ */
+struct jpeg_enc_param {
+ u32 enable_exif;
+ u32 enc_quality;
+ u32 restart_interval;
+};
+
+/**
+ * mtk_jpeg_enc_param: General jpeg encoding parameters
+ * @enc_w: image width
+ * @enc_h: image height
+ * @enable_exif: EXIF enable for jpeg encode mode
+ * @enc_quality: destination image quality in encode mode
+ * @enc_format: input image format
+ * @restart_interval: JPEG restart interval for JPEG encoding
+ * @img_stride: jpeg encoder image stride
+ * @mem_stride: jpeg encoder memory stride
+ * @total_encdu: total 8x8 block number
+ */
+struct mtk_jpeg_enc_param {
+ u32 enc_w;
+ u32 enc_h;
+ u32 enable_exif;
+ u32 enc_quality;
+ u32 enc_format;
+ u32 restart_interval;
+ u32 img_stride;
+ u32 mem_stride;
+ u32 total_encdu;
+};
+
/**
* mtk_jpeg_ctx - the device context data
* @jpeg: JPEG IP device for this context
* @out_q: source (output) queue information
* @cap_q: destination (capture) queue queue information
* @fh: V4L2 file handle
- * @dec_param parameters for HW decoding
* @state: state of the context
- * @header_valid: set if header has been parsed and valid
+ * @jpeg_param: jpeg encode parameters
+ * @ctrl_hdl: controls handler
* @colorspace: enum v4l2_colorspace; supplemental to pixelformat
* @ycbcr_enc: enum v4l2_ycbcr_encoding, Y'CbCr encoding
* @quantization: enum v4l2_quantization, colorspace quantization
@@ -129,6 +221,8 @@ struct mtk_jpeg_ctx {
struct mtk_jpeg_q_data cap_q;
struct v4l2_fh fh;
enum mtk_jpeg_ctx_state state;
+ struct jpeg_enc_param jpeg_param;
+ struct v4l2_ctrl_handler ctrl_hdl;
enum v4l2_colorspace colorspace;
enum v4l2_ycbcr_encoding ycbcr_enc;
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.h b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.h
index bff6a4aab57a..725ce94fd58f 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.h
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.h
@@ -2,6 +2,7 @@
* Copyright (c) 2016 MediaTek Inc.
* Author: Ming Hsiu Tsai <minghsiu.tsai@mediatek.com>
* Rick Chang <rick.chang@mediatek.com>
+ * Xia Jiang <xia.jiang@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@@ -13,8 +14,8 @@
* GNU General Public License for more details.
*/
-#ifndef _MTK_JPEG_HW_H
-#define _MTK_JPEG_HW_H
+#ifndef _MTK_JPEG_DEC_HW_H
+#define _MTK_JPEG_DEC_HW_H
#include <media/videobuf2-core.h>
@@ -88,4 +89,4 @@ void mtk_jpeg_dec_set_config(void __iomem *base,
void mtk_jpeg_dec_reset(void __iomem *dec_reg_base);
void mtk_jpeg_dec_start(void __iomem *dec_reg_base);
-#endif /* _MTK_JPEG_HW_H */
+#endif /* _MTK_JPEG_DEC_HW_H */
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_hw.c b/drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_hw.c
new file mode 100644
index 000000000000..b82d39f1022b
--- /dev/null
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_hw.c
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Xia Jiang <xia.jiang@mediatek.com>
+ *
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <media/videobuf2-core.h>
+
+#include "mtk_jpeg_enc_hw.h"
+
+void mtk_jpeg_enc_reset(void __iomem *base)
+{
+ writel(0x00, base + JPGENC_RSTB);
+ writel(JPEG_ENC_RESET_BIT, base + JPGENC_RSTB);
+ writel(0x00, base + JPGENC_CODEC_SEL);
+}
+
+u32 mtk_jpeg_enc_get_int_status(void __iomem *base)
+{
+ u32 ret;
+
+ ret = readl(base + JPGENC_INT_STS) &
+ JPEG_DRV_ENC_INT_STATUS_MASK_ALLIRQ;
+ if (ret)
+ writel(0, base + JPGENC_INT_STS);
+
+ return ret;
+}
+
+u32 mtk_jpeg_enc_get_file_size(void __iomem *base)
+{
+ return readl(base + JPGENC_DMA_ADDR0) - readl(base + JPGENC_DST_ADDR0);
+}
+
+u32 mtk_jpeg_enc_enum_result(void __iomem *base, u32 irq_status, u32 *file_size)
+{
+ *file_size = mtk_jpeg_enc_get_file_size(base);
+ if (irq_status & JPEG_DRV_ENC_INT_STATUS_DONE)
+ return MTK_JPEG_ENC_RESULT_DONE;
+ else if (irq_status & JPEG_DRV_ENC_INT_STATUS_STALL)
+ return MTK_JPEG_ENC_RESULT_STALL;
+ else if (irq_status & JPEG_DRV_ENC_INT_STATUS_VCODEC_IRQ)
+ return MTK_JPEG_ENC_RESULT_VCODEC_IRQ;
+ return MTK_JPEG_ENC_RESULT_ERROR_UNKNOWN;
+}
+
+static void mtk_jpeg_enc_set_blk_num(void __iomem *base, u32 blk_num)
+{
+ writel(blk_num, base + JPGENC_BLK_NUM);
+}
+
+static void mtk_jpeg_enc_set_encFormat(void __iomem *base, u32 enc_format)
+{
+ u32 value;
+
+ value = readl(base + JPGENC_CTRL);
+ value &= ~JPEG_ENC_CTRL_YUV_BIT;
+ value |= JPGENC_FORMAT(enc_format);
+ writel(value, base + JPGENC_CTRL);
+}
+
+static void mtk_jpeg_enc_set_img_size(void __iomem *base, u32 width, u32 height)
+{
+ u32 value;
+
+ value = JPGENC_WIDTH_HEIGHT(width, height);
+ writel(value, base + JPGENC_IMG_SIZE);
+}
+
+static void mtk_jpeg_enc_set_src_img(void __iomem *base, u32 width,
+ u32 height, u32 yuv_format,
+ u32 total_encdu)
+{
+ mtk_jpeg_enc_set_img_size(base, width, height);
+ mtk_jpeg_enc_set_encFormat(base, yuv_format);
+ mtk_jpeg_enc_set_blk_num(base, total_encdu);
+}
+
+static void mtk_jpeg_enc_set_src_buf(void __iomem *base, u32 img_stride,
+ u32 mem_stride, u32 src_addr,
+ u32 src_addr_c)
+{
+ writel(img_stride, base + JPGENC_IMG_STRIDE);
+ writel(mem_stride, base + JPGENC_STRIDE);
+ writel(src_addr, base + JPGENC_SRC_LUMA_ADDR);
+ writel(src_addr_c, base + JPGENC_SRC_CHROMA_ADDR);
+}
+
+static void mtk_jpeg_enc_set_dst_buf(void __iomem *base, u32 dst_addr,
+ u32 stall_size, u32 init_offset,
+ u32 offset_mask)
+{
+ writel(JPGENC_INIT_OFFSET(init_offset), base + JPGENC_OFFSET_ADDR);
+ writel(JPGENC_OFFSET_MASK(offset_mask), base + JPGENC_BYTE_OFFSET_MASK);
+ writel(JPGENC_DST_ADDR(dst_addr), base + JPGENC_DST_ADDR0);
+ writel(JPGENC_STALL_ADDR(dst_addr, stall_size),
+ base + JPGENC_STALL_ADDR0);
+}
+
+static void mtk_jpeg_enc_set_quality(void __iomem *base, u32 quality)
+{
+ u32 value;
+
+ value = readl(base + JPGENC_QUALITY);
+ value = JPGENC_SET_QUALITY(value, quality);
+ writel(value, base + JPGENC_QUALITY);
+}
+
+static void mtk_jpeg_enc_set_restart_interval(void __iomem *base,
+ u32 restart_interval)
+{
+ u32 value;
+
+ value = readl(base + JPGENC_CTRL);
+ if (restart_interval)
+ value |= JPEG_ENC_CTRL_RESTART_EN_BIT;
+ else
+ value &= ~JPEG_ENC_CTRL_RESTART_EN_BIT;
+ writel(value, base + JPGENC_CTRL);
+ writel(restart_interval, base + JPGENC_RST_MCU_NUM);
+}
+
+static void mtk_jpeg_enc_set_encode_mode(void __iomem *base, u32 exif_en)
+{
+ u32 value;
+
+ value = readl(base + JPGENC_CTRL);
+ value &= ~JPEG_ENC_CTRL_FILE_FORMAT_BIT;
+ writel(value, base + JPGENC_CTRL);
+
+ if (exif_en) {
+ value = readl(base + JPGENC_CTRL);
+ value |= JPEG_ENC_EN_JFIF_EXIF;
+ writel(value, base + JPGENC_CTRL);
+ }
+}
+
+static void mtk_jpeg_enc_set_ctrl_cfg(void __iomem *base, u32 exif_en,
+ u32 quality, u32 restart_interval)
+{
+ mtk_jpeg_enc_set_quality(base, quality);
+
+ mtk_jpeg_enc_set_restart_interval(base, restart_interval);
+
+ mtk_jpeg_enc_set_encode_mode(base, exif_en);
+}
+
+void mtk_jpeg_enc_start(void __iomem *base)
+{
+ u32 value;
+
+ value = readl(base + JPGENC_CTRL);
+ value |= JPEG_ENC_CTRL_INT_EN_BIT | JPEG_ENC_CTRL_ENABLE_BIT;
+ writel(value, base + JPGENC_CTRL);
+}
+
+void mtk_jpeg_enc_set_config(void __iomem *base,
+ struct mtk_jpeg_enc_param *config,
+ struct mtk_jpeg_enc_bs *bs,
+ struct mtk_jpeg_enc_fb *fb)
+{
+ mtk_jpeg_enc_set_src_img(base, config->enc_w, config->enc_h,
+ config->enc_format, config->total_encdu);
+ mtk_jpeg_enc_set_src_buf(base, config->img_stride, config->mem_stride,
+ fb->fb_addr[0].dma_addr,
+ fb->fb_addr[1].dma_addr);
+ mtk_jpeg_enc_set_dst_buf(base, bs->dma_addr, bs->size,
+ bs->dma_addr_offset, bs->dma_addr_offsetmask);
+ mtk_jpeg_enc_set_ctrl_cfg(base, config->enable_exif,
+ config->enc_quality,
+ config->restart_interval);
+}
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_hw.h b/drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_hw.h
new file mode 100644
index 000000000000..ef3e6d97cdcd
--- /dev/null
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_hw.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Xia Jiang <xia.jiang@mediatek.com>
+ *
+ */
+
+#ifndef _MTK_JPEG_ENC_HW_H
+#define _MTK_JPEG_ENC_HW_H
+
+#include <media/videobuf2-core.h>
+
+#include "mtk_jpeg_core.h"
+#include "mtk_jpeg_enc_reg.h"
+
+#define JPEG_ENC_DST_ADDR_OFFSET_MASK GENMASK(3, 0)
+
+#define JPEG_ENC_CTRL_YUV_BIT 0x18
+#define JPEG_ENC_CTRL_RESTART_EN_BIT BIT(10)
+#define JPEG_ENC_CTRL_FILE_FORMAT_BIT BIT(5)
+#define JPEG_ENC_EN_JFIF_EXIF BIT(5)
+#define JPEG_ENC_CTRL_INT_EN_BIT BIT(2)
+#define JPEG_ENC_CTRL_ENABLE_BIT BIT(0)
+#define JPEG_ENC_RESET_BIT BIT(0)
+
+enum {
+ MTK_JPEG_ENC_RESULT_DONE = 0,
+ MTK_JPEG_ENC_RESULT_STALL,
+ MTK_JPEG_ENC_RESULT_VCODEC_IRQ,
+ MTK_JPEG_ENC_RESULT_ERROR_UNKNOWN
+};
+
+struct mtk_jpeg_enc_bs {
+ dma_addr_t dma_addr;
+ size_t size;
+ u32 dma_addr_offset;
+ u32 dma_addr_offsetmask;
+};
+
+struct mtk_jpeg_mem {
+ dma_addr_t dma_addr;
+ size_t size;
+};
+
+struct mtk_jpeg_enc_fb {
+ struct mtk_jpeg_mem fb_addr[MTK_JPEG_COMP_MAX];
+ u32 num_planes;
+};
+
+void mtk_jpeg_enc_reset(void __iomem *base);
+u32 mtk_jpeg_enc_get_int_status(void __iomem *base);
+u32 mtk_jpeg_enc_get_file_size(void __iomem *base);
+u32 mtk_jpeg_enc_enum_result(void __iomem *base, u32 irq_status,
+ u32 *file_size);
+void mtk_jpeg_enc_start(void __iomem *enc_reg_base);
+void mtk_jpeg_enc_set_config(void __iomem *base,
+ struct mtk_jpeg_enc_param *config,
+ struct mtk_jpeg_enc_bs *bs,
+ struct mtk_jpeg_enc_fb *fb);
+#endif /* _MTK_JPEG_ENC_HW_H */
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_reg.h b/drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_reg.h
new file mode 100644
index 000000000000..2e64fcd58bf6
--- /dev/null
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_reg.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Xia Jiang <xia.jiang@mediatek.com>
+ *
+ */
+#ifndef _MTK_JPEG_ENC_REG_H
+#define _MTK_JPEG_ENC_REG_H
+#define MTK_JPEG_COMP_MAX 3
+
+#define JPEG_DRV_ENC_INT_STATUS_DONE BIT(0)
+#define JPEG_DRV_ENC_INT_STATUS_STALL BIT(1)
+#define JPEG_DRV_ENC_INT_STATUS_VCODEC_IRQ BIT(4)
+#define JPEG_DRV_ENC_INT_STATUS_MASK_ALLIRQ 0x13
+
+#define JPGENC_RSTB 0x100
+#define JPGENC_CTRL 0x104
+#define JPGENC_QUALITY 0x108
+#define JPGENC_BLK_NUM 0x10C
+#define JPGENC_BLK_CNT 0x110
+#define JPGENC_INT_STS 0x11C
+#define JPGENC_DST_ADDR0 0x120
+#define JPGENC_DMA_ADDR0 0x124
+#define JPGENC_STALL_ADDR0 0x128
+#define JPGENC_OFFSET_ADDR 0x138
+#define JPGENC_RST_MCU_NUM 0x150
+#define JPGENC_IMG_SIZE 0x154
+#define JPGENC_DEBUG_INFO0 0x160
+#define JPGENC_DEBUG_INFO1 0x164
+#define JPGENC_TOTAL_CYCLE 0x168
+#define JPGENC_BYTE_OFFSET_MASK 0x16C
+#define JPGENC_SRC_LUMA_ADDR 0x170
+#define JPGENC_SRC_CHROMA_ADDR 0x174
+#define JPGENC_STRIDE 0x178
+#define JPGENC_IMG_STRIDE 0x17C
+#define JPGENC_DCM_CTRL 0x300
+#define JPGENC_CODEC_SEL 0x314
+#define JPGENC_ULTRA_THRES 0x318
+
+#define JPGENC_FORMAT(x) (((x) & 3) << 3)
+#define JPGENC_WIDTH_HEIGHT(w, h) (((w) << 16) | (h))
+#define JPGENC_INIT_OFFSET(x) ((x) & (~0xF))
+#define JPGENC_OFFSET_MASK(x) ((x) & 0xF)
+#define JPGENC_DST_ADDR(x) ((x) & (~0xF))
+#define JPGENC_STALL_ADDR(x, y) (((x) + (y)) & (~0xF))
+#define JPGENC_QUALITY_MASK 0xFFFF0000
+#define JPGENC_SET_QUALITY(x, y) (((x) & JPGENC_QUALITY_MASK) | (y))
+
+#endif /* _MTK_JPEG_ENC_REG_H */
diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c
index 89a1fe564675..02826c0dceb9 100644
--- a/drivers/media/v4l2-core/v4l2-ctrls.c
+++ b/drivers/media/v4l2-core/v4l2-ctrls.c
@@ -1010,6 +1010,7 @@ const char *v4l2_ctrl_get_name(u32 id)
case V4L2_CID_JPEG_CHROMA_SUBSAMPLING: return "Chroma Subsampling";
case V4L2_CID_JPEG_RESTART_INTERVAL: return "Restart Interval";
case V4L2_CID_JPEG_COMPRESSION_QUALITY: return "Compression Quality";
+ case V4L2_CID_JPEG_ENABLE_EXIF: return "Enable Exif";
case V4L2_CID_JPEG_ACTIVE_MARKER: return "Active Markers";
/* Image source controls */
diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h
index 37807f23231e..863ea6f93562 100644
--- a/include/uapi/linux/v4l2-controls.h
+++ b/include/uapi/linux/v4l2-controls.h
@@ -998,6 +998,8 @@ enum v4l2_jpeg_chroma_subsampling {
#define V4L2_JPEG_ACTIVE_MARKER_COM (1 << 16)
#define V4L2_JPEG_ACTIVE_MARKER_DQT (1 << 17)
#define V4L2_JPEG_ACTIVE_MARKER_DHT (1 << 18)
+#define V4L2_CID_JPEG_ENABLE_EXIF (V4L2_CID_JPEG_CLASS_BASE + 5)
+
/* Image source controls */
--
2.18.0
^ permalink raw reply related
* [PATCH 2/5] media: platform: Rename jpeg dec file name
From: Xia Jiang @ 2019-07-17 9:30 UTC (permalink / raw)
To: Hans Verkuil, Rob Herring, Matthias Brugger, Rick Chang
Cc: linux-media, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Marek Szyprowski, Tomasz Figa, srv_heupstream,
Xia Jiang
In-Reply-To: <20190717093034.22826-1-xia.jiang@mediatek.com>
Rename the files which are for decode feature. This is a preparing
patch since the jpeg enc patch will be added later.
Change-Id: Ie037f3f62d07632e323e5beff7420759e4862516
Signed-off-by: Xia Jiang <xia.jiang@mediatek.com>
---
drivers/media/platform/mtk-jpeg/Makefile | 2 +-
drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c | 4 ++--
.../platform/mtk-jpeg/{mtk_jpeg_hw.c => mtk_jpeg_dec_hw.c} | 2 +-
.../platform/mtk-jpeg/{mtk_jpeg_hw.h => mtk_jpeg_dec_hw.h} | 2 +-
.../mtk-jpeg/{mtk_jpeg_parse.c => mtk_jpeg_dec_parse.c} | 2 +-
.../mtk-jpeg/{mtk_jpeg_parse.h => mtk_jpeg_dec_parse.h} | 2 +-
.../platform/mtk-jpeg/{mtk_jpeg_reg.h => mtk_jpeg_dec_reg.h} | 0
7 files changed, 7 insertions(+), 7 deletions(-)
rename drivers/media/platform/mtk-jpeg/{mtk_jpeg_hw.c => mtk_jpeg_dec_hw.c} (99%)
rename drivers/media/platform/mtk-jpeg/{mtk_jpeg_hw.h => mtk_jpeg_dec_hw.h} (98%)
rename drivers/media/platform/mtk-jpeg/{mtk_jpeg_parse.c => mtk_jpeg_dec_parse.c} (99%)
rename drivers/media/platform/mtk-jpeg/{mtk_jpeg_parse.h => mtk_jpeg_dec_parse.h} (96%)
rename drivers/media/platform/mtk-jpeg/{mtk_jpeg_reg.h => mtk_jpeg_dec_reg.h} (100%)
diff --git a/drivers/media/platform/mtk-jpeg/Makefile b/drivers/media/platform/mtk-jpeg/Makefile
index b2e6069f3959..994fcd66069c 100644
--- a/drivers/media/platform/mtk-jpeg/Makefile
+++ b/drivers/media/platform/mtk-jpeg/Makefile
@@ -1,2 +1,2 @@
-mtk_jpeg-objs := mtk_jpeg_core.o mtk_jpeg_hw.o mtk_jpeg_parse.o
+mtk_jpeg-objs := mtk_jpeg_core.o mtk_jpeg_dec_hw.o mtk_jpeg_dec_parse.o
obj-$(CONFIG_VIDEO_MEDIATEK_JPEG) += mtk_jpeg.o
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c b/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c
index f761e4d8bf2a..49e3b5284006 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_core.c
@@ -31,9 +31,9 @@
#include <media/videobuf2-dma-contig.h>
#include <soc/mediatek/smi.h>
-#include "mtk_jpeg_hw.h"
+#include "mtk_jpeg_dec_hw.h"
#include "mtk_jpeg_core.h"
-#include "mtk_jpeg_parse.h"
+#include "mtk_jpeg_dec_parse.h"
static struct mtk_jpeg_fmt mtk_jpeg_formats[] = {
{
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.c
similarity index 99%
rename from drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c
rename to drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.c
index 77b4cc6a8873..aad834d98059 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.c
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.c
@@ -17,7 +17,7 @@
#include <linux/kernel.h>
#include <media/videobuf2-core.h>
-#include "mtk_jpeg_hw.h"
+#include "mtk_jpeg_dec_hw.h"
#define MTK_JPEG_DUNUM_MASK(val) (((val) - 1) & 0x3)
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.h b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.h
similarity index 98%
rename from drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.h
rename to drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.h
index 37152a630dea..bff6a4aab57a 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_hw.h
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_hw.h
@@ -19,7 +19,7 @@
#include <media/videobuf2-core.h>
#include "mtk_jpeg_core.h"
-#include "mtk_jpeg_reg.h"
+#include "mtk_jpeg_dec_reg.h"
enum {
MTK_JPEG_DEC_RESULT_EOF_DONE = 0,
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_parse.c b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.c
similarity index 99%
rename from drivers/media/platform/mtk-jpeg/mtk_jpeg_parse.c
rename to drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.c
index 38868547f5d4..c887f90c3a66 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_parse.c
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.c
@@ -16,7 +16,7 @@
#include <linux/kernel.h>
#include <linux/videodev2.h>
-#include "mtk_jpeg_parse.h"
+#include "mtk_jpeg_dec_parse.h"
#define TEM 0x01
#define SOF0 0xc0
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_parse.h b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.h
similarity index 96%
rename from drivers/media/platform/mtk-jpeg/mtk_jpeg_parse.h
rename to drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.h
index 5d92340ea81b..fdad7f2da6be 100644
--- a/drivers/media/platform/mtk-jpeg/mtk_jpeg_parse.h
+++ b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.h
@@ -16,7 +16,7 @@
#ifndef _MTK_JPEG_PARSE_H
#define _MTK_JPEG_PARSE_H
-#include "mtk_jpeg_hw.h"
+#include "mtk_jpeg_dec_hw.h"
bool mtk_jpeg_parse(struct mtk_jpeg_dec_param *param, u8 *src_addr_va,
u32 src_size);
diff --git a/drivers/media/platform/mtk-jpeg/mtk_jpeg_reg.h b/drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_reg.h
similarity index 100%
rename from drivers/media/platform/mtk-jpeg/mtk_jpeg_reg.h
rename to drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_reg.h
--
2.18.0
^ permalink raw reply related
* [PATCH 1/5] media: dt-bindings: Add JPEG ENC device tree node document
From: Xia Jiang @ 2019-07-17 9:30 UTC (permalink / raw)
To: Hans Verkuil, Rob Herring, Matthias Brugger, Rick Chang
Cc: linux-media, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Marek Szyprowski, Tomasz Figa, srv_heupstream,
Xia Jiang
In-Reply-To: <20190717093034.22826-1-xia.jiang@mediatek.com>
add JPEG ENC device tree node document
Change-Id: I9f0a8aec7eced20c88acbc88d6ff179763f91246
Signed-off-by: Xia Jiang <xia.jiang@mediatek.com>
---
.../bindings/media/mediatek-jpeg-encoder.txt | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.txt
diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.txt b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.txt
new file mode 100644
index 000000000000..1231fedb70bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.txt
@@ -0,0 +1,33 @@
+* MediaTek JPEG Encoder
+
+MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs
+
+Required properties:
+- compatible : must be "mediatek,mtk-jpgenc"
+- reg : physical base address of the JPEG encoder registers and length of
+ memory mapped region.
+- interrupts : interrupt number to the interrupt controller.
+- clocks: device clocks, see
+ Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+- clock-names: must contain "jpgenc". It is the clock of JPEG encoder.
+- power-domains: a phandle to the power domain, see
+ Documentation/devicetree/bindings/power/power_domain.txt for details.
+- mediatek,larb: must contain the local arbiters in the current SoCs, see
+ Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
+ for details.
+- iommus: should point to the respective IOMMU block with master port as
+ argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+ for details.
+
+Example:
+ jpegenc: jpegenc@1500a000 {
+ compatible = "mediatek,mtk-jpgenc";
+ reg = <0 0x1500a000 0 0x1000>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&imgsys CLK_IMG_VENC>;
+ clock-names = "jpgenc";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
+ mediatek,larb = <&larb2>;
+ iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
+ <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>;
+ };
--
2.18.0
^ permalink raw reply related
* [PATCH v2 0/5]Add support for mt2701 JPEG ENC support
From: Xia Jiang @ 2019-07-17 9:30 UTC (permalink / raw)
To: Hans Verkuil, Rob Herring, Matthias Brugger, Rick Chang
Cc: devicetree, srv_heupstream, linux-kernel, Tomasz Figa,
linux-mediatek, linux-media, linux-arm-kernel, Marek Szyprowski
This patchset add support for mt2701 JPEG ENC support.
This is the compliance test result for jpeg dec and enc.
The JPEG dec log:
------------------------------------------------------------
v4l2-compliance -d /dev/video0
v4l2-compliance SHA: 1b961f5e82b0805faea0ba68bfa8037213a02351, 32 bits
Compliance test for mtk-jpeg device /dev/video0:
Driver Info:
Driver name : mtk-jpeg
Card type : mtk-jpeg decoder
Bus info : platform:15004000.jpegdec
Driver version : 5.2.0
Capabilities : 0x84204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Detected JPEG Decoder
Required ioctls:
test VIDIOC_QUERYCAP: OK
Allow for multiple opens:
test second /dev/video0 open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
test VIDIOC_G/S/TRY_EXT_CTRLS: OK
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK (Not Supported)
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 0 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK (Not Supported)
test Composing: OK
test Scaling: OK
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test VIDIOC_EXPBUF: OK
test Requests: OK (Not Supported)
Total for mtk-jpeg device /dev/video0: 44, Succeeded: 44, Failed: 0, Warnings: 0
------------------------------------------------------------
The JPEG enc log:
------------------------------------------------------------
v4l2-compliance -d /dev/video1
v4l2-compliance SHA: 1b961f5e82b0805faea0ba68bfa8037213a02351, 32 bits
Compliance test for mtk-jpeg device /dev/video1:
Driver Info:
Driver name : mtk-jpeg
Card type : mtk-jpeg encoder
Bus info : platform:1500a000.jpegenc
Driver version : 5.2.0
Capabilities : 0x84204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Detected JPEG Encoder
Required ioctls:
test VIDIOC_QUERYCAP: OK
Allow for multiple opens:
test second /dev/video1 open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
test VIDIOC_G/S/TRY_EXT_CTRLS: OK
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 4 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK (Not Supported)
test Composing: OK
test Scaling: OK
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test VIDIOC_EXPBUF: OK
test Requests: OK (Not Supported)
Total for mtk-jpeg device /dev/video1: 44, Succeeded: 44, Failed: 0, Warnings: 0
------------------------------------------------------------
Change compared to v1:
-fix compliance test fail, check created buffer size in driver
Xia Jiang (5):
media: dt-bindings: Add JPEG ENC device tree node document
media: platform: Rename jpeg dec file name
media: platform: Add jpeg enc feature
media: platform: change GPLv2 license to SPDX
arm: dts: add jpeg enc device tree node
.../bindings/media/mediatek-jpeg-encoder.txt | 33 +
arch/arm/boot/dts/mt2701.dtsi | 12 +
drivers/media/platform/mtk-jpeg/Makefile | 5 +-
.../media/platform/mtk-jpeg/mtk_jpeg_core.c | 753 ++++++++++++++----
.../media/platform/mtk-jpeg/mtk_jpeg_core.h | 123 ++-
.../{mtk_jpeg_hw.c => mtk_jpeg_dec_hw.c} | 11 +-
.../{mtk_jpeg_hw.h => mtk_jpeg_dec_hw.h} | 18 +-
...{mtk_jpeg_parse.c => mtk_jpeg_dec_parse.c} | 11 +-
.../platform/mtk-jpeg/mtk_jpeg_dec_parse.h | 18 +
.../{mtk_jpeg_reg.h => mtk_jpeg_dec_reg.h} | 9 +-
.../media/platform/mtk-jpeg/mtk_jpeg_enc_hw.c | 175 ++++
.../media/platform/mtk-jpeg/mtk_jpeg_enc_hw.h | 60 ++
.../platform/mtk-jpeg/mtk_jpeg_enc_reg.h | 49 ++
.../media/platform/mtk-jpeg/mtk_jpeg_parse.h | 25 -
drivers/media/v4l2-core/v4l2-ctrls.c | 1 +
include/uapi/linux/v4l2-controls.h | 2 +
16 files changed, 1060 insertions(+), 245 deletions(-)
create mode 100644 Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.txt
rename drivers/media/platform/mtk-jpeg/{mtk_jpeg_hw.c => mtk_jpeg_dec_hw.c} (96%)
rename drivers/media/platform/mtk-jpeg/{mtk_jpeg_hw.h => mtk_jpeg_dec_hw.h} (76%)
rename drivers/media/platform/mtk-jpeg/{mtk_jpeg_parse.c => mtk_jpeg_dec_parse.c} (85%)
create mode 100644 drivers/media/platform/mtk-jpeg/mtk_jpeg_dec_parse.h
rename drivers/media/platform/mtk-jpeg/{mtk_jpeg_reg.h => mtk_jpeg_dec_reg.h} (78%)
create mode 100644 drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_hw.c
create mode 100644 drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_hw.h
create mode 100644 drivers/media/platform/mtk-jpeg/mtk_jpeg_enc_reg.h
delete mode 100644 drivers/media/platform/mtk-jpeg/mtk_jpeg_parse.h
--
2.18.0
^ permalink raw reply
* Re: [PATCH v1 23/50] ARM: dts: exynos: change lowest OPP in bus_disp1_fimd in Exynos5420
From: Krzysztof Kozlowski @ 2019-07-17 9:08 UTC (permalink / raw)
To: Lukasz Luba
Cc: devicetree, linux-kernel, linux-arm-kernel,
linux-samsung-soc@vger.kernel.org, linux-clk, mturquette, sboyd,
Bartłomiej Żołnierkiewicz, kgene, mark.rutland,
robh+dt, Chanwoo Choi, kyungmin.park, Andrzej Hajda,
Marek Szyprowski, s.nawrocki, myungjoo.ham
In-Reply-To: <20190715124417.4787-24-l.luba@partner.samsung.com>
On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> The lowest OPP must be aligned to possible value after division of parent
> clock rate. Thus, change it to the value which is true for clock 1200MHz.
I think this is getting slightly too granular. It seems you are
solving the same problem (or very small subset of the same problem) as
in patch 22:
https://patchwork.kernel.org/patch/11043849/
Please combine such changes per IP block, unless you have really
reproducible different issues (e.g. reproducible different performance
problem or OOPS, but not just what clk_summary prints). I imagine that
you align entire subsystem (DISP) buses to real clock frequencies (or
to match real frequencies, or to achieve more granular scaling, or to
get slightly better performance).
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH 1/2] net/macb: bindings doc: add sifive fu540-c000 binding
From: Yash Shah @ 2019-07-17 9:07 UTC (permalink / raw)
To: Nicolas Ferre
Cc: Rob Herring, David Miller, netdev,
linux-kernel@vger.kernel.org List, linux-riscv, devicetree,
Mark Rutland, Palmer Dabbelt, Albert Ou, Petr Štetiar,
Paul Walmsley, Sachin Ghadi
In-Reply-To: <b0c60ec9-2f57-c3f5-c3b4-ee83a5ec4c45@microchip.com>
On Mon, Jun 24, 2019 at 9:08 PM <Nicolas.Ferre@microchip.com> wrote:
>
> On 23/05/2019 at 22:50, Rob Herring wrote:
> > On Thu, May 23, 2019 at 6:46 AM Yash Shah <yash.shah@sifive.com> wrote:
> >>
> >> Add the compatibility string documentation for SiFive FU540-C0000
> >> interface.
> >> On the FU540, this driver also needs to read and write registers in a
> >> management IP block that monitors or drives boundary signals for the
> >> GEMGXL IP block that are not directly mapped to GEMGXL registers.
> >> Therefore, add additional range to "reg" property for SiFive GEMGXL
> >> management IP registers.
> >>
> >> Signed-off-by: Yash Shah <yash.shah@sifive.com>
> >> ---
> >> Documentation/devicetree/bindings/net/macb.txt | 3 +++
> >> 1 file changed, 3 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt
> >> index 9c5e944..91a2a66 100644
> >> --- a/Documentation/devicetree/bindings/net/macb.txt
> >> +++ b/Documentation/devicetree/bindings/net/macb.txt
> >> @@ -4,6 +4,7 @@ Required properties:
> >> - compatible: Should be "cdns,[<chip>-]{macb|gem}"
> >> Use "cdns,at91rm9200-emac" Atmel at91rm9200 SoC.
> >> Use "cdns,at91sam9260-macb" for Atmel at91sam9 SoCs.
> >> + Use "cdns,fu540-macb" for SiFive FU540-C000 SoC.
> >
> > This pattern that Atmel started isn't really correct. The vendor
> > prefix here should be sifive. 'cdns' would be appropriate for a
> > fallback.
>
> Ok, we missed this for the sam9x60 SoC that we added recently then.
>
> Anyway a little too late, coming back to this machine, and talking to
> Yash, isn't "sifive,fu540-c000-macb" more specific and a better match
> for being future proof? I would advice for the most specific possible
> with other compatible strings on the same line in the DT, like:
>
> "sifive,fu540-c000-macb", "sifive,fu540-macb"
>
Yes, I agree that "sifive,fu540-c000-macb" is a better match.
> Moreover, is it really a "macb" or a "gem" type of interface from
> Cadence? Not a big deal, but just to discuss the topic to the bone...
I believe it should be "gem". I will plan to submit the patch for
these changes. Thanks for pointing it out.
- Yash
>
> Note that I'm fine if you consider that what you have in net-next new is
> correct.
>
> Regards,
> Nicolas
>
> >> Use "cdns,sam9x60-macb" for Microchip sam9x60 SoC.
> >> Use "cdns,np4-macb" for NP4 SoC devices.
> >> Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb".
> >> @@ -17,6 +18,8 @@ Required properties:
> >> Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
> >> Or the generic form: "cdns,emac".
> >> - reg: Address and length of the register set for the device
> >> + For "cdns,fu540-macb", second range is required to specify the
> >> + address and length of the registers for GEMGXL Management block.
> >> - interrupts: Should contain macb interrupt
> >> - phy-mode: See ethernet.txt file in the same directory.
> >> - clock-names: Tuple listing input clock names.
> >> --
> >> 1.9.1
> >>
> >
>
>
> --
> Nicolas Ferre
^ permalink raw reply
* Re: [PATCH 2/3] rtc: Add support for the MediaTek MT2712 RTC
From: Alexandre Belloni @ 2019-07-17 9:06 UTC (permalink / raw)
To: Ran Bi
Cc: Rob Herring, Matthias Brugger, Alessandro Zummo, Mark Rutland,
linux-rtc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, srv_heupstream, YT Shen, Eddie Huang,
Yingjoe Chen, Flora Fu, Sean Wang
In-Reply-To: <1563353694.19945.33.camel@mhfsdcap03>
On 17/07/2019 16:54:54+0800, Ran Bi wrote:
> > > +
> > > +/* we map HW YEAR 0 to 1968 not 1970 because 2000 is the leap year */
> > > +#define RTC_MIN_YEAR 1968
> > > +#define RTC_BASE_YEAR 1900
> > > +#define RTC_MIN_YEAR_OFFSET (RTC_MIN_YEAR - RTC_BASE_YEAR)
> >
> > Do not do that. If this RTC range starts in 200, ths is what the driver
> > has to support, you should not care about dates before 2000. Note that
> > the RTC core can still properly shift the range if it is absolutely
> > necessary.
> >
>
> Do we need to care about default alarm date 1970-01-01? Or can I just
> set it to 2000-01-01?
>
You never have to set a default value. It doesn't add any value versus
an unknown value.
> > > +
> > > +static inline u32 rtc_readl(struct mt2712_rtc *rtc, u32 reg)
> >
> > Please use a more descriptive prefix than just rtc_.
> >
>
> Do you mean it's better to use prefix "mt2712_rtc_"?
>
Yes.
> > > +
> > > + /*
> > > + * register status was not correct,
> > > + * need set time and alarm to default
> > > + */
> > > + if (p1 != RTC_POWERKEY1_KEY || p2 != RTC_POWERKEY2_KEY
> > > + || !valid_rtc_time(rtc)) {
> > > + reset_rtc_time(rtc);
> >
> > Do not do that. This is valuable information. If the time is invalid,
> > report it as such in read_time and read_alarm. Resetting the time here
> > will lead to more issues later (i.e. userspace is not able to know
> > whether the time is set correctly or not).
> >
>
> When RTC's power run out, RTC will lost it's registers value and time
> data at next boot up. We even cannot know what the date and time it
> shows. We want to check this state here and set a default RTC date. Do
> you think it's no need here and the date should be set by system?
>
If I understand correctly, the POWERKEY register will lose their value.
This means that you know that the time is incorrect. instead of setting
it to a default value and losing that valuable information, simply check
for that in read_time and return EINVAL in that case. then on the next
set_time invocation, you can set the POWERKEY registers and set the time
to a known value.
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH 2/2] ARM: dts: Add support for i.MX6 UltraLite DART Variscite Customboard
From: Shawn Guo @ 2019-07-17 9:05 UTC (permalink / raw)
To: Oliver Graute
Cc: narmstrong, Rob Herring, Mark Rutland, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <1561398017-10548-3-git-send-email-oliver.graute@gmail.com>
On Mon, Jun 24, 2019 at 07:40:13PM +0200, Oliver Graute wrote:
> This patch adds DeviceTree Source for the i.MX6 UltraLite DART NAND/WIFI
>
> Signed-off-by: Oliver Graute <oliver.graute@gmail.com>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts | 203 ++++++++++++++++++++++++
> 2 files changed, 204 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index c4742af..5dc3fbf 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -577,6 +577,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
> imx6ul-tx6ul-0010.dtb \
> imx6ul-tx6ul-0011.dtb \
> imx6ul-tx6ul-mainboard.dtb \
> + imx6ul-var-6ulcustomboard.dtb \
> imx6ull-14x14-evk.dtb \
> imx6ull-colibri-eval-v3.dtb \
> imx6ull-colibri-wifi-eval-v3.dtb \
> diff --git a/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
> new file mode 100644
> index 0000000..59354e6
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6ul-var-6ulcustomboard.dts
> @@ -0,0 +1,203 @@
> +// SPDX-License-Identifier: (GPL-2.0)
> +/*
> + * Support for Variscite DART-6UL Module
> + *
> + * Copyright (C) 2015 Freescale Semiconductor, Inc.
> + * Copyright (C) 2015-2016 Variscite Ltd. - http://www.variscite.com
> + * Copyright (C) 2018-2019 Oliver Graute <oliver.graute@gmail.com>
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/input/input.h>
> +#include "imx6ul-imx6ull-var-dart-common.dtsi"
> +
> +/ {
> + model = "Variscite i.MX6 UltraLite Carrier-board";
> + compatible = "fsl,6ulcustomboard", "fsl,imx6ul";
The board compatible is documented?
> +
> + backlight {
> + compatible = "pwm-backlight";
> + pwms = <&pwm1 0 20000>;
> + brightness-levels = <0 4 8 16 32 64 128 255>;
> + default-brightness-level = <6>;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> +
> + user {
> + gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_BACK>;
> + gpio-key,wakeup;
> + };
> + };
> +
> + gpio-leds {
> + compatible = "gpio-leds";
> +
> + d16-led {
> + gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "heartbeat";
> + };
> + };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,name = "wm8731audio";
> + simple-audio-card,widgets =
> + "Headphone", "Headphone Jack",
> + "Line", "Line Jack",
> + "Microphone", "Mic Jack";
> + simple-audio-card,routing =
> + "Headphone Jack", "RHPOUT",
> + "Headphone Jack", "LHPOUT",
> + "LLINEIN", "Line Jack",
> + "RLINEIN", "Line Jack",
> + "MICIN", "Mic Bias",
> + "Mic Bias", "Mic Jack";
> + simple-audio-card,format = "i2s";
> + simple-audio-card,bitclock-master = <&sound_master>;
> + simple-audio-card,frame-master = <&sound_master>;
> +
> + sound_master: simple-audio-card,cpu {
> + sound-dai = <&sai2>;
> + };
> + };
> +};
> +
> +&can1 {
> + status = "okay";
> +};
> +
> +&can2 {
> + status = "okay";
> +};
> +
> +&gpc {
> + fsl,cpu_pupscr_sw2iso = <0x2>;
> + fsl,cpu_pupscr_sw = <0x1>;
> + fsl,cpu_pdnscr_iso2sw = <0x1>;
> + fsl,cpu_pdnscr_iso = <0x1>;
> + fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
These are not supported by mainline kernel, IIRC.
Shawn
> +};
> +
> +&fec1 {
> + phy-mode = "rgmii";
> + phy-reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
> + phy-handle = <ðphy0>;
> + status = "okay";
> +};
> +
> +&fec2 {
> + phy-mode = "rgmii";
> + phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
> + phy-handle = <ðphy1>;
> + status = "okay";
> +};
> +
> +&i2c1 {
> + clock-frequency = <400000>;
> + status = "okay";
> +};
> +
> +&i2c2 {
> + clock_frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + status = "okay";
> +
> + wm8731: audio-codec@1a {
> + #sound-dai-cells = <0>;
> + compatible = "wlf,wm8731";
> + reg = <0x1a>;
> + clocks = <&clks IMX6UL_CLK_SAI2>;
> + clock-names = "mclk";
> + };
> +
> + touchscreen@38 {
> + compatible = "edt,edt-ft5x06";
> + reg = <0x38>;
> + interrupt-parent = <&gpio3>;
> + interrupts = <4 0>;
> + touchscreen-size-x = <800>;
> + touchscreen-size-y = <480>;
> + touchscreen-inverted-x;
> + touchscreen-inverted-y;
> + };
> +
> + rtc@68 {
> + compatible = "dallas,ds1337";
> + reg = <0x68>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_rtc>;
> + interrupt-parent = <&gpio5>;
> + interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
> + };
> +};
> +
> +&lcdif {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lcdif_dat
> + &pinctrl_lcdif_ctrl>;
> + display = <&display0>;
> + status = "okay";
> +
> + display0: display0 {
> + bits-per-pixel = <16>;
> + bus-width = <24>;
> +
> + display-timings {
> + native-mode = <&timing0>;
> + timing0: timing0 {
> + clock-frequency =<35000000>;
> + hactive = <800>;
> + vactive = <480>;
> + hfront-porch = <40>;
> + hback-porch = <40>;
> + hsync-len = <48>;
> + vback-porch = <29>;
> + vfront-porch = <13>;
> + vsync-len = <3>;
> + hsync-active = <0>;
> + vsync-active = <0>;
> + de-active = <1>;
> + pixelclk-active = <0>;
> + };
> + };
> + };
> +};
> +
> +&pwm1 {
> + status = "okay";
> +};
> +
> +&uart1 {
> + status = "okay";
> +};
> +
> +&uart2 {
> + status = "okay";
> +};
> +
> +&uart3 {
> + status = "okay";
> +};
> +
> +&usbotg1 {
> + dr_mode = "host";
> + status = "okay";
> +};
> +
> +&usbotg2 {
> + dr_mode = "host";
> + status = "okay";
> +};
> +
> +&iomuxc {
> + pinctrl_rtc: rtcgrp {
> + fsl,pins = <
> + MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0
> + >;
> + };
> +};
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH 1/2] ARM: dts: imx6ul: Add Variscite DART-6UL SoM support
From: Shawn Guo @ 2019-07-17 8:56 UTC (permalink / raw)
To: Oliver Graute
Cc: narmstrong, Rob Herring, Mark Rutland, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <1561398017-10548-2-git-send-email-oliver.graute@gmail.com>
On Mon, Jun 24, 2019 at 07:40:12PM +0200, Oliver Graute wrote:
> This patch adds support for the i.MX6UL variant of the Variscite DART-6UL
> SoM Carrier-Board
>
> Signed-off-by: Oliver Graute <oliver.graute@gmail.com>
> ---
> .../boot/dts/imx6ul-imx6ull-var-dart-common.dtsi | 458 +++++++++++++++++++++
> 1 file changed, 458 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
>
> diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
> new file mode 100644
> index 0000000..57d62e8
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6ul-imx6ull-var-dart-common.dtsi
> @@ -0,0 +1,458 @@
> +// SPDX-License-Identifier: (GPL-2.0)
> +/dts-v1/;
> +
> +#include "imx6ul.dtsi"
> +/ {
> + chosen {
> + stdout-path = &uart1;
> + };
> +
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x80000000 0x20000000>;
> + };
> +
> + touch_3v3_regulator: regulator-touch-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "touch_3v3_supply";
> + regulator-always-on;
> + };
> +
> + reg_sd1_vmmc: regulator-sd1-vmmc {
> + compatible = "regulator-fixed";
> + regulator-name = "VSD_3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + reg_gpio_dvfs: regulator-gpio {
> + compatible = "regulator-gpio";
> + regulator-min-microvolt = <1300000>;
> + regulator-max-microvolt = <1400000>;
> + regulator-name = "gpio_dvfs";
> + regulator-type = "voltage";
> + gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
If it's active-high, I think you need enable-active-high property.
> + states = <1300000 0x1 1400000 0x0>;
> + };
> +
> + clk-phy {
You do not need this container node.
> + /* ref_clk for micrel ethernet phy */
> + rmii_ref_clk: rmii_ref_clk_grp {
The node name could be better named, because:
1. We prefer to use hyphen than underscore in node name.
2. Not sure why the '_grp' suffix is there.
Something like 'clock-rmii-ref' might be better.
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + clock-output-names = "rmii-ref";
> + };
> + };
> +
> + clk-pll {
> + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
> + assigned-clock-rates = <786432000>;
> + };
Not sure what this node is about and how it works.
> +};
> +
> +&adc1 {
> + vref-supply = <&touch_3v3_regulator>;
> + status = "okay";
> +};
> +
> +&can1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan1>;
> + status = "disabled";
> +};
> +
> +&can2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan2>;
> + status = "disabled";
> +};
> +
> +&cpu0 {
> + arm-supply = <®_arm>;
> + soc-supply = <®_soc>;
> + dc-supply = <®_gpio_dvfs>;
What is this 'dc-supply'? I'm not sure cpufreq driver supports it.
> +};
> +
> +&fec1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet1>;
> + phy-mode = "rmii";
> + status = "disabled";
> +};
> +
> +&fec2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet2>;
> + phy-mode = "rmii";
> + status = "disabled";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy0: ethernet-phy@1 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + micrel,rmii-reference-clock-select-25-mhz;
> + clocks = <&rmii_ref_clk>;
> + clock-names = "rmii-ref";
> + reg = <1>;
> + };
> +
> + ethphy1: ethernet-phy@3 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + micrel,rmii-reference-clock-select-25-mhz;
> + clocks = <&rmii_ref_clk>;
> + clock-names = "rmii-ref";
> + reg = <3>;
> + };
> + };
> +};
> +
> +&gpmi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpmi_nand>;
> + fsl,legacy-bch-geometry;
Are you sure this property is supported by mainline kernel?
> + status = "okay";
> +
> + partition@0 {
> + label = "spl";
> + reg = <0x00000000 0x00200000>;
> + };
> +
> + partition@200000 {
> + label = "uboot";
> + reg = <0x00200000 0x00200000>;
> + };
> +
> + partition@400000 {
> + label = "uboot-env";
> + reg = <0x00400000 0x00200000>;
> + };
> +
> + partition@600000 {
> + label = "kernel";
> + reg = <0x00600000 0x00800000>;
> + };
> +
> + partition@e00000 {
> + label = "rootfs";
> + reg = <0x00e00000 0x3f200000>;
> + };
> +};
> +
> +&i2c1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "disabled";
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + status = "disabled";
> +};
> +
> +&pwm1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm1>;
> + status = "disabled";
> +};
> +
> +&sai2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_sai2>;
> + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
> + <&clks IMX6UL_CLK_SAI2>;
> + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
> + assigned-clock-rates = <0>, <12288000>;
> + fsl,sai-mclk-direction-output;
> + status = "okay";
> +};
> +
> +&snvs_poweroff {
> + status = "okay";
> +};
> +
> +&snvs_rtc {
> + status = "disabled";
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + status = "disabled";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2>;
> + uart-has-rtscts;
> + status = "disabled";
> +};
> +
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3>;
> + uart-has-rtscts;
> + status = "disabled";
> +};
> +
> +&usbotg1 {
> + disable-over-current;
> + status = "disabled";
> +};
> +
> +&usbotg2 {
> + disable-over-current;
> + status = "disabled";
> +};
> +
> +&usdhc1 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> + no-1-8-v;
> + keep-power-in-suspend;
> + vmmc-supply = <®_sd1_vmmc>;
> + non-removable;
> + status = "okay";
> +};
> +
> +&usdhc2 {
> + status = "disabled";
> +};
> +
> +&iomuxc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hog_1>;
Where is this pinctrl_hog_1 defined?
> +
> + pinctrl_enet1: enet1grp {
> + fsl,pins = <
> + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
> + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
> + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
> + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
> + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
> + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
> + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
> + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
> + >;
> + };
> +
> + pinctrl_enet2: enet2grp {
> + fsl,pins = <
> + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
> + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
> + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
> + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
> + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
> + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
> + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
> + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
> + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
> + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
> + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0
> + >;
> + };
> +
> + pinctrl_flexcan1: flexcan1grp{
> + fsl,pins = <
> + MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x1b020
> + MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x1b020
> + >;
> + };
> +
> + pinctrl_flexcan2: flexcan2grp{
> + fsl,pins = <
> + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
> + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
> + >;
> + };
> +
> + pinctrl_gpio_leds: gpioledsgrp {
> + fsl,pins = <
> + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x1b0b0
> + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x17059
> + >;
> + };
> +
> + pinctrl_gpmi_nand: gpminandgrp {
> + fsl,pins = <
> + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
> + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
> + MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
> + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
> + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
> + MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1
> + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
> + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
> + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
> + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
> + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
> + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
> + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
> + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
> + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
> + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
> + >;
> + };
> +
> + pinctrl_hog: hoggrp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x03029
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
> + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
> + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
> + >;
> + };
> +
> + pinctrl_lcdif_dat: lcdifdatgrp {
> + fsl,pins = <
> + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
> + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
> + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
> + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
> + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
> + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
> + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
> + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
> + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
> + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
> + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
> + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
> + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
> + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
> + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
> + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
> + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
> + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
> + >;
> + };
> +
> + pinctrl_lcdif_ctrl: lcdifctrlgrp {
> + fsl,pins = <
> + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
> + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
> + >;
> + };
Is it really needed to split LCDIF pins into data and ctrl groups?
> +
> + pinctrl_pwm1: pwm1grp {
> + fsl,pins = <
> + MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x110b0
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
> + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
> + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
> + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
> + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart3: uart3grp {
> + fsl,pins = <
> + MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
> + MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
> + MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
> + MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059
> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
> + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> + fsl,pins = <
> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
> + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> + fsl,pins = <
> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
> + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x1b0b1
> + >;
> + };
> +
> + pinctrl_sai1: sai1grp {
Please keep the pinctrl nodes alphabetically sorted.
> + fsl,pins = <
> + MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x11088
> + MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x17088
> + MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x11088
> + MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x11088
> + >;
> + };
> +
> + pinctrl_sai2: sai2grp {
> + fsl,pins = <
> + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
> + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
> + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
> + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
> + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
> + >;
> + };
> +
> + pinctrl_tsc: tscgrp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
> + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
> + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
> + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
> + >;
> + };
> +
> + pinctrl_wdog: wdoggrp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x78b0
> + >;
> + };
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog>;
> + fsl,ext-reset-output;
> +};
The iomuxc node is put at the end of the file to improve readability due
to its huge number of pinctrl data. But wdog should find its place per
alphabetic order.
Shawn
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH 2/3] rtc: Add support for the MediaTek MT2712 RTC
From: Ran Bi @ 2019-07-17 8:54 UTC (permalink / raw)
To: Alexandre Belloni
Cc: Rob Herring, Matthias Brugger, Alessandro Zummo, Mark Rutland,
linux-rtc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, srv_heupstream, YT Shen, Eddie Huang,
Yingjoe Chen, Flora Fu, Sean Wang
In-Reply-To: <20190713211231.GD4732@piout.net>
Hi Belloni,
On Sat, 2019-07-13 at 23:12 +0200, Alexandre Belloni wrote:
> > +#define RTC_BBPU 0x0000
> > +#define RTC_BBPU_CLRPKY (1U << 4)
>
> Please use BIT(). Also, I don't feel that the RTC prefix is adding any
> value. MT2712 would be a better choice here.
>
Will change to MT2712 at next patch.
> > +
> > +/* we map HW YEAR 0 to 1968 not 1970 because 2000 is the leap year */
> > +#define RTC_MIN_YEAR 1968
> > +#define RTC_BASE_YEAR 1900
> > +#define RTC_MIN_YEAR_OFFSET (RTC_MIN_YEAR - RTC_BASE_YEAR)
>
> Do not do that. If this RTC range starts in 200, ths is what the driver
> has to support, you should not care about dates before 2000. Note that
> the RTC core can still properly shift the range if it is absolutely
> necessary.
>
Do we need to care about default alarm date 1970-01-01? Or can I just
set it to 2000-01-01?
> > +
> > +static inline u32 rtc_readl(struct mt2712_rtc *rtc, u32 reg)
>
> Please use a more descriptive prefix than just rtc_.
>
Do you mean it's better to use prefix "mt2712_rtc_"?
> > + mutex_lock(&rtc->lock);
>
> You should take rtc->rtc_dev->ops_lock. This would remove the need for
> rtc->lock.
>
Will change it at next patch.
> > + tm->tm_year += RTC_MIN_YEAR_OFFSET;
> > +
>
> As stated before, do not do that, simply add 100.
>
Will change it at next patch.
> > + /* rtc_tm_to_time64 convert Gregorian date to seconds since
> > + * 01-01-1970 00:00:00, and this date is Thursday
> > + */
> > + time = rtc_tm_to_time64(tm);
> > + days = div_s64(time, 86400);
> > + tm->tm_wday = (days + 4) % 7;
> > +
>
> This is not necessary, nobody cares about tm_wday, if you don't have it,
> do not set it.
>
Will remove this part at next patch.
> > + dev_info(rtc->dev, "set al time = %04d-%02d-%02d %02d:%02d:%02d (%d)\n",
>
> Do not use dev_info, dev_dbg is probably what you want here. Also, use
> %ptR.
>
Will change it at next patch.
> > + mutex_lock(&rtc->lock);
>
> You probably need to disable the alarm before starting to modify the
> registers.
>
Will change it at next patch.
> > +static bool valid_rtc_time(struct mt2712_rtc *rtc)
>
> This function is not necessary, see later.
>
Will change it at next patch.
> > + rtc_writel(rtc, RTC_IRQ_EN, 0);
>
> Are you sure you want to disable interrupts every time you reboot? I
> guess the RTC has its own power domain and may be used across reboots.
>
Will remove this at next patch.
> > + dev_info(rtc->dev, "%s rtc p1 is %x, p2 is %x!\n", __func__, p1, p2);
>
> This debug message has to be removed.
>
Will remove this at next patch.
> > +
> > + /*
> > + * register status was not correct,
> > + * need set time and alarm to default
> > + */
> > + if (p1 != RTC_POWERKEY1_KEY || p2 != RTC_POWERKEY2_KEY
> > + || !valid_rtc_time(rtc)) {
> > + reset_rtc_time(rtc);
>
> Do not do that. This is valuable information. If the time is invalid,
> report it as such in read_time and read_alarm. Resetting the time here
> will lead to more issues later (i.e. userspace is not able to know
> whether the time is set correctly or not).
>
When RTC's power run out, RTC will lost it's registers value and time
data at next boot up. We even cannot know what the date and time it
shows. We want to check this state here and set a default RTC date. Do
you think it's no need here and the date should be set by system?
> > + ret = request_threaded_irq(rtc->irq, NULL,
>
> devm_request_threaded_irq would remove the need for out_free_irq and
> mtk_rtc_remove().
>
Will change it at next patch. And will remove mtk_rtc_remove() function.
--
Ran Bi, MediaTek
^ permalink raw reply
* Re: [PATCH v1 21/50] ARM: dts: exynos: add OPP into FSYS APB bus in Exynos5420
From: Krzysztof Kozlowski @ 2019-07-17 8:48 UTC (permalink / raw)
To: Lukasz Luba
Cc: devicetree, linux-kernel, linux-arm-kernel,
linux-samsung-soc@vger.kernel.org, linux-clk, mturquette, sboyd,
Bartłomiej Żołnierkiewicz, kgene, mark.rutland,
robh+dt, Chanwoo Choi, kyungmin.park, Andrzej Hajda,
Marek Szyprowski, s.nawrocki, myungjoo.ham
In-Reply-To: <20190715124417.4787-22-l.luba@partner.samsung.com>
On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> Add an OPP for FSYS APB which reflects the real possible frequency.
> The bus will have a new parent clock which speed has 600MHz, thus
> a new possible frequency provided by the clock divider is 150MHz.
> According to the documentation max possible frequency for this bus is
> 200MHz.
Commit msg is good but title could be improved. Focus in the title
what problem/issue you are solving - add intermediate step in scaling
of FSYS APB?
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v1 20/50] ARM: dts: exynos: change and rename FSYS OPP table in Exynos5420
From: Krzysztof Kozlowski @ 2019-07-17 8:39 UTC (permalink / raw)
To: Lukasz Luba
Cc: devicetree, linux-kernel, linux-arm-kernel,
linux-samsung-soc@vger.kernel.org, linux-clk, mturquette, sboyd,
Bartłomiej Żołnierkiewicz, kgene, mark.rutland,
robh+dt, Chanwoo Choi, kyungmin.park, Andrzej Hajda,
Marek Szyprowski, s.nawrocki, myungjoo.ham
In-Reply-To: <20190715124417.4787-21-l.luba@partner.samsung.com>
On Mon, 15 Jul 2019 at 14:44, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> The FSYS and FSYS2 buses have similar characteristics and both have max
> frequency 240MHz. The old OPP table bus_fsys_apb_opp_table should be used
> only to FSYS APB bus because APB max frequency is 200MHz.
> The new OPPs for FSYS should increase its performance and related devices.
I do not understand the explanation. You say that there are two buses
- FSYS and FSYS2 - and old OPP table should be used for FSYS APB but
you remove the old one (by renaming). Or which one is the 'old one'
here? The reason is speed... wait, what? Usually DTS should describe
the HW so I imagine that proper opp table should be used for proper
bus. It surprised me that we switch a bus to different OPP table just
because of speed concerns. It should be correctness concern.
Please clarify and reword all this.
I am also not sure how this relates with previous patch - whether you
are fixing independent issues. Maybe because I do not see the issue
fixed... change the commit title and adjust the messages to focus WHY
you are doing it. For small fixes WHAT you are doing is rather obvious
so commit msg (and title) should not focus on it.
Best regards,
Krzysztof
>
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
> arch/arm/boot/dts/exynos5420.dtsi | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
> index 941c58bdd809..c7fc4b829b2a 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> @@ -995,7 +995,7 @@
> compatible = "samsung,exynos-bus";
> clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
> clock-names = "bus";
> - operating-points-v2 = <&bus_fsys_apb_opp_table>;
> + operating-points-v2 = <&bus_fsys_opp_table>;
> status = "disabled";
> };
>
> @@ -1003,7 +1003,7 @@
> compatible = "samsung,exynos-bus";
> clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
> clock-names = "bus";
> - operating-points-v2 = <&bus_fsys2_opp_table>;
> + operating-points-v2 = <&bus_fsys_opp_table>;
> status = "disabled";
> };
>
> @@ -1157,7 +1157,7 @@
> };
> };
>
> - bus_fsys2_opp_table: opp_table5 {
> + bus_fsys_opp_table: opp_table5 {
> compatible = "operating-points-v2";
>
> opp00 {
> --
> 2.17.1
>
^ permalink raw reply
* Re: [PATCH v2 13/15] arm64: dts: imx: add imx8qm common dts file
From: Dong Aisheng @ 2019-07-17 8:28 UTC (permalink / raw)
To: Fabio Estevam
Cc: Dong Aisheng,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Catalin Marinas, Will Deacon, Rob Herring, NXP Linux Team,
Sascha Hauer, Fabio Estevam, Mark Rutland, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <CAOMZO5Cc6XLjFFEVd59Pru7t72jvW=OCikyXK7W6E8rWRVO3jA@mail.gmail.com>
On Wed, Jul 17, 2019 at 3:33 AM Fabio Estevam <festevam@gmail.com> wrote:
>
> On Tue, Jul 16, 2019 at 12:37 PM Dong Aisheng <aisheng.dong@nxp.com> wrote:
>
> > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> > @@ -144,7 +144,7 @@
> > };
> >
> > clk: clock-controller {
> > - compatible = "fsl,imx8qxp-clk";
> > + compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
>
> This looks like unrelated to adding imx8qm support.
Sorry, it's a mistake. Will remove in next version.
I will first wait to see if any more comments on the rest part.
Regards
Aisheng
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox