* [PATCH 2/3] Revert "usb: usb251xb: Add US port lanes inversion property"
From: Lucas Stach @ 2019-07-19 8:44 UTC (permalink / raw)
To: Richard Leitner, Greg Kroah-Hartman, Rob Herring
Cc: Mark Rutland, Serge Semin, linux-usb, devicetree, kernel,
patchwork-lst
In-Reply-To: <20190719084407.28041-1-l.stach@pengutronix.de>
This property isn't needed and not yet used anywhere. The swap-dx-lanes
property is perfectly fine for doing the swap on the upstream port
lanes.
CC: stable@vger.kernel.org #5.2
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
drivers/usb/misc/usb251xb.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/usb/misc/usb251xb.c b/drivers/usb/misc/usb251xb.c
index 4d6ae3795a88..119aeb658c81 100644
--- a/drivers/usb/misc/usb251xb.c
+++ b/drivers/usb/misc/usb251xb.c
@@ -574,8 +574,6 @@ static int usb251xb_get_ofdata(struct usb251xb *hub,
hub->port_swap = USB251XB_DEF_PORT_SWAP;
usb251xb_get_ports_field(hub, "swap-dx-lanes", data->port_cnt,
&hub->port_swap);
- if (of_get_property(np, "swap-us-lanes", NULL))
- hub->port_swap |= BIT(0);
/* The following parameters are currently not exposed to devicetree, but
* may be as soon as needed.
--
2.20.1
^ permalink raw reply related
* [PATCH 3/3] usb: usb251xb: Reallow swap-dx-lanes to apply to the upstream port
From: Lucas Stach @ 2019-07-19 8:44 UTC (permalink / raw)
To: Richard Leitner, Greg Kroah-Hartman, Rob Herring
Cc: Mark Rutland, Serge Semin, linux-usb, devicetree, kernel,
patchwork-lst
In-Reply-To: <20190719084407.28041-1-l.stach@pengutronix.de>
This is a partial revert of 73d31def1aab "usb: usb251xb: Create a ports
field collector method", which broke a existing devicetree
(arch/arm64/boot/dts/freescale/imx8mq.dtsi).
There is no reason why the swap-dx-lanes property should not apply to
the upstream port. The reason given in the breaking commit was that it's
inconsitent with respect to other port properties, but in fact it is not.
All other properties which only apply to the downstream ports explicitly
reject port 0, so there is pretty strong precedence that the driver
referred to the upstream port as port 0. So there is no inconsistency in
this property at all, other than the swapping being also applicable to
the upstream port.
CC: stable@vger.kernel.org #5.2
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
drivers/usb/misc/usb251xb.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/misc/usb251xb.c b/drivers/usb/misc/usb251xb.c
index 119aeb658c81..6ca9111d150a 100644
--- a/drivers/usb/misc/usb251xb.c
+++ b/drivers/usb/misc/usb251xb.c
@@ -375,7 +375,8 @@ static int usb251xb_connect(struct usb251xb *hub)
#ifdef CONFIG_OF
static void usb251xb_get_ports_field(struct usb251xb *hub,
- const char *prop_name, u8 port_cnt, u8 *fld)
+ const char *prop_name, u8 port_cnt,
+ bool ds_only, u8 *fld)
{
struct device *dev = hub->dev;
struct property *prop;
@@ -383,7 +384,7 @@ static void usb251xb_get_ports_field(struct usb251xb *hub,
u32 port;
of_property_for_each_u32(dev->of_node, prop_name, prop, p, port) {
- if ((port >= 1) && (port <= port_cnt))
+ if ((port >= ds_only ? 1 : 0) && (port <= port_cnt))
*fld |= BIT(port);
else
dev_warn(dev, "port %u doesn't exist\n", port);
@@ -501,15 +502,15 @@ static int usb251xb_get_ofdata(struct usb251xb *hub,
hub->non_rem_dev = USB251XB_DEF_NON_REMOVABLE_DEVICES;
usb251xb_get_ports_field(hub, "non-removable-ports", data->port_cnt,
- &hub->non_rem_dev);
+ true, &hub->non_rem_dev);
hub->port_disable_sp = USB251XB_DEF_PORT_DISABLE_SELF;
usb251xb_get_ports_field(hub, "sp-disabled-ports", data->port_cnt,
- &hub->port_disable_sp);
+ true, &hub->port_disable_sp);
hub->port_disable_bp = USB251XB_DEF_PORT_DISABLE_BUS;
usb251xb_get_ports_field(hub, "bp-disabled-ports", data->port_cnt,
- &hub->port_disable_bp);
+ true, &hub->port_disable_bp);
hub->max_power_sp = USB251XB_DEF_MAX_POWER_SELF;
if (!of_property_read_u32(np, "sp-max-total-current-microamp",
@@ -573,7 +574,7 @@ static int usb251xb_get_ofdata(struct usb251xb *hub,
*/
hub->port_swap = USB251XB_DEF_PORT_SWAP;
usb251xb_get_ports_field(hub, "swap-dx-lanes", data->port_cnt,
- &hub->port_swap);
+ false, &hub->port_swap);
/* The following parameters are currently not exposed to devicetree, but
* may be as soon as needed.
--
2.20.1
^ permalink raw reply related
* RE: [PATCH v2 6/8] PCI: al: Add support for DW based driver type
From: Gustavo Pimentel @ 2019-07-19 8:55 UTC (permalink / raw)
To: Jonathan Chocron, lorenzo.pieralisi@arm.com, bhelgaas@google.com,
jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
robh+dt@kernel.org, mark.rutland@arm.com
Cc: dwmw@amazon.co.uk, benh@kernel.crashing.org, alisaidi@amazon.com,
ronenk@amazon.com, barakw@amazon.com, talel@amazon.com,
hanochu@amazon.com, hhhawa@amazon.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
In-Reply-To: <20190718094718.25083-2-jonnyc@amazon.com>
On Thu, Jul 18, 2019 at 10:47:16, Jonathan Chocron <jonnyc@amazon.com>
wrote:
> This driver is DT based and utilizes the DesignWare APIs.
> It allows using a smaller ECAM range for a larger bus range -
> usually an entire bus uses 1MB of address space, but the driver
> can use it for a larger number of buses.
>
> All link initializations are handled by the boot FW.
>
> Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
> ---
> drivers/pci/controller/dwc/Kconfig | 12 +
> drivers/pci/controller/dwc/pcie-al.c | 373 +++++++++++++++++++++++++++
> 2 files changed, 385 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
> index 6ea778ae4877..3c6094cbcc3b 100644
> --- a/drivers/pci/controller/dwc/Kconfig
> +++ b/drivers/pci/controller/dwc/Kconfig
> @@ -230,4 +230,16 @@ config PCIE_UNIPHIER
> Say Y here if you want PCIe controller support on UniPhier SoCs.
> This driver supports LD20 and PXs3 SoCs.
>
> +config PCIE_AL
> + bool "Amazon Annapurna Labs PCIe controller"
> + depends on OF && (ARM64 || COMPILE_TEST)
> + depends on PCI_MSI_IRQ_DOMAIN
> + select PCIE_DW_HOST
> + help
> + Say Y here to enable support of the Amazon's Annapurna Labs PCIe
> + controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
> + core plus Annapurna Labs proprietary hardware wrappers. This is
> + required only for DT-based platforms. ACPI platforms with the
> + Annapurna Labs PCIe controller don't need to enable this.
> +
> endmenu
> diff --git a/drivers/pci/controller/dwc/pcie-al.c b/drivers/pci/controller/dwc/pcie-al.c
> index 3ab58f0584a8..40555532fb9a 100644
> --- a/drivers/pci/controller/dwc/pcie-al.c
> +++ b/drivers/pci/controller/dwc/pcie-al.c
> @@ -91,3 +91,376 @@ struct pci_ecam_ops al_pcie_ops = {
> };
>
> #endif /* defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) */
> +
> +#ifdef CONFIG_PCIE_AL
> +
> +#include <linux/of_pci.h>
> +#include "pcie-designware.h"
> +
> +#define AL_PCIE_REV_ID_2 2
> +#define AL_PCIE_REV_ID_3 3
> +#define AL_PCIE_REV_ID_4 4
> +
> +#define AXI_BASE_OFFSET 0x0
> +
> +#define DEVICE_ID_OFFSET 0x16c
> +
> +#define DEVICE_REV_ID 0x0
> +#define DEVICE_REV_ID_DEV_ID_MASK GENMASK(31, 16)
> +
> +#define DEVICE_REV_ID_DEV_ID_X4 0
> +#define DEVICE_REV_ID_DEV_ID_X8 2
> +#define DEVICE_REV_ID_DEV_ID_X16 4
> +
> +#define OB_CTRL_REV1_2_OFFSET 0x0040
> +#define OB_CTRL_REV3_5_OFFSET 0x0030
> +
> +#define CFG_TARGET_BUS 0x0
> +#define CFG_TARGET_BUS_MASK_MASK GENMASK(7, 0)
> +#define CFG_TARGET_BUS_BUSNUM_MASK GENMASK(15, 8)
> +
> +#define CFG_CONTROL 0x4
> +#define CFG_CONTROL_SUBBUS_MASK GENMASK(15, 8)
> +#define CFG_CONTROL_SEC_BUS_MASK GENMASK(23, 16)
> +
> +struct al_pcie_reg_offsets {
> + unsigned int ob_ctrl;
> +};
> +
> +struct al_pcie_target_bus_cfg {
> + u8 reg_val;
> + u8 reg_mask;
> + u8 ecam_mask;
> +};
> +
> +struct al_pcie {
> + struct dw_pcie *pci;
> + void __iomem *controller_base; /* base of PCIe unit (not DW core) */
> + struct device *dev;
> + resource_size_t ecam_size;
> + unsigned int controller_rev_id;
> + struct al_pcie_reg_offsets reg_offsets;
> + struct al_pcie_target_bus_cfg target_bus_cfg;
> +};
> +
> +#define PCIE_ECAM_DEVFN(x) (((x) & 0xff) << 12)
> +
> +#define to_al_pcie(x) dev_get_drvdata((x)->dev)
> +
> +static int al_pcie_rev_id_get(struct al_pcie *pcie, unsigned int *rev_id)
> +{
> + void __iomem *dev_rev_id_addr;
> + u32 dev_rev_id;
> +
> + dev_rev_id_addr = (void __iomem *)((uintptr_t)pcie->controller_base +
> + AXI_BASE_OFFSET + DEVICE_ID_OFFSET + DEVICE_REV_ID);
> +
> + dev_rev_id = FIELD_GET(DEVICE_REV_ID_DEV_ID_MASK,
> + readl(dev_rev_id_addr));
> + switch (dev_rev_id) {
> + case DEVICE_REV_ID_DEV_ID_X4:
> + *rev_id = AL_PCIE_REV_ID_2;
> + break;
> + case DEVICE_REV_ID_DEV_ID_X8:
> + *rev_id = AL_PCIE_REV_ID_3;
> + break;
> + case DEVICE_REV_ID_DEV_ID_X16:
> + *rev_id = AL_PCIE_REV_ID_4;
> + break;
> + default:
> + dev_err(pcie->dev, "Unsupported dev_rev_id (0x%x)\n",
> + dev_rev_id);
> + return -EINVAL;
> + }
> +
> + dev_dbg(pcie->dev, "dev_rev_id: 0x%x\n", dev_rev_id);
Consider s/dev_dbg/pci_dbg/g
> +
> + return 0;
> +}
> +
> +static int al_pcie_reg_offsets_set(struct al_pcie *pcie)
> +{
> + switch (pcie->controller_rev_id) {
> + case AL_PCIE_REV_ID_2:
> + pcie->reg_offsets.ob_ctrl = OB_CTRL_REV1_2_OFFSET;
> + break;
> + case AL_PCIE_REV_ID_3:
> + case AL_PCIE_REV_ID_4:
> + pcie->reg_offsets.ob_ctrl = OB_CTRL_REV3_5_OFFSET;
> + break;
> + default:
> + dev_err(pcie->dev, "Unsupported controller rev_id: 0x%x\n",
> + pcie->controller_rev_id);
Consider s/dev_err/pci_err/g
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static inline void al_pcie_target_bus_set(struct al_pcie *pcie,
> + u8 target_bus,
> + u8 mask_target_bus)
> +{
> + void __iomem *cfg_control_addr;
> + u32 reg;
> +
> + reg = FIELD_PREP(CFG_TARGET_BUS_MASK_MASK, mask_target_bus) |
> + FIELD_PREP(CFG_TARGET_BUS_BUSNUM_MASK, target_bus);
> +
> + cfg_control_addr = (void __iomem *)((uintptr_t)pcie->controller_base +
> + AXI_BASE_OFFSET + pcie->reg_offsets.ob_ctrl +
> + CFG_TARGET_BUS);
> +
> + writel(reg, cfg_control_addr);
>From what I'm seeing you commonly use writel() and readl() with a common
base address, such as pcie->controller_base + AXI_BASE_OFFSET.
I'd suggest to creating a writel and readl with that offset built-in.
> +}
> +
> +static void __iomem *al_pcie_conf_addr_map(struct al_pcie *pcie,
> + unsigned int busnr,
> + unsigned int devfn)
> +{
> + void __iomem *pci_base_addr;
Consider passing this variable declaration to the bottom, following the
reverse tree order.
> + struct pcie_port *pp = &pcie->pci->pp;
> + struct al_pcie_target_bus_cfg *target_bus_cfg = &pcie->target_bus_cfg;
> + unsigned int busnr_ecam = busnr & target_bus_cfg->ecam_mask;
> + unsigned int busnr_reg = busnr & target_bus_cfg->reg_mask;
> +
> + pci_base_addr = (void __iomem *)((uintptr_t)pp->va_cfg0_base +
> + (busnr_ecam << 20) +
> + PCIE_ECAM_DEVFN(devfn));
> +
> + if (busnr_reg != target_bus_cfg->reg_val) {
> + dev_dbg(pcie->pci->dev, "Changing target bus busnum val from 0x%x to 0x%x\n",
> + target_bus_cfg->reg_val, busnr_reg);
> + target_bus_cfg->reg_val = busnr_reg;
> + al_pcie_target_bus_set(pcie,
> + target_bus_cfg->reg_val,
> + target_bus_cfg->reg_mask);
> + }
> +
> + return pci_base_addr;
> +}
> +
> +static int al_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
> + unsigned int devfn, int where, int size,
> + u32 *val)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct al_pcie *pcie = to_al_pcie(pci);
> + unsigned int busnr = bus->number;
> + void __iomem *pci_addr;
> + int rc;
> +
> + pci_addr = al_pcie_conf_addr_map(pcie, busnr, devfn);
> +
> + rc = dw_pcie_read(pci_addr + where, size, val);
> +
> + dev_dbg(pci->dev, "%d-byte config read from %04x:%02x:%02x.%d offset 0x%x (pci_addr: 0x%px) - val:0x%x\n",
> + size, pci_domain_nr(bus), bus->number,
> + PCI_SLOT(devfn), PCI_FUNC(devfn), where,
> + (pci_addr + where), *val);
> +
> + return rc;
> +}
> +
> +static int al_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
> + unsigned int devfn, int where, int size,
> + u32 val)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct al_pcie *pcie = to_al_pcie(pci);
> + unsigned int busnr = bus->number;
> + void __iomem *pci_addr;
> + int rc;
> +
> + pci_addr = al_pcie_conf_addr_map(pcie, busnr, devfn);
> +
> + rc = dw_pcie_write(pci_addr + where, size, val);
> +
> + dev_err(pci->dev, "%d-byte config write to %04x:%02x:%02x.%d offset 0x%x (pci_addr: 0x%px) - val:0x%x\n",
> + size, pci_domain_nr(bus), bus->number,
> + PCI_SLOT(devfn), PCI_FUNC(devfn), where,
> + (pci_addr + where), val);
> +
> + return rc;
> +}
> +
> +static int al_pcie_config_prepare(struct al_pcie *pcie)
> +{
> + struct al_pcie_target_bus_cfg *target_bus_cfg;
> + struct pcie_port *pp = &pcie->pci->pp;
> + unsigned int ecam_bus_mask;
> + u8 secondary_bus;
> + u8 subordinate_bus;
> + void __iomem *cfg_control_addr;
> + u32 cfg_control;
> + u32 reg;
> +
> + target_bus_cfg = &pcie->target_bus_cfg;
> +
> + ecam_bus_mask = (pcie->ecam_size >> 20) - 1;
> + if (ecam_bus_mask > 255) {
> + dev_warn(pcie->dev, "ECAM window size is larger than 256MB. Cutting off at 256\n");
> + ecam_bus_mask = 255;
> + }
> +
> + /* This portion is taken from the transaction address */
> + target_bus_cfg->ecam_mask = ecam_bus_mask;
> + /* This portion is taken from the cfg_target_bus reg */
> + target_bus_cfg->reg_mask = ~target_bus_cfg->ecam_mask;
> + target_bus_cfg->reg_val = pp->busn->start & target_bus_cfg->reg_mask;
> +
> + al_pcie_target_bus_set(pcie, target_bus_cfg->reg_val,
> + target_bus_cfg->reg_mask);
> +
> + secondary_bus = pp->busn->start + 1;
> + subordinate_bus = pp->busn->end;
> +
> + /* Set the valid values of secondary and subordinate buses */
> + cfg_control_addr = pcie->controller_base + AXI_BASE_OFFSET +
> + pcie->reg_offsets.ob_ctrl + CFG_CONTROL;
> +
> + cfg_control = readl(cfg_control_addr);
> +
> + reg = cfg_control &
> + ~(CFG_CONTROL_SEC_BUS_MASK | CFG_CONTROL_SUBBUS_MASK);
> +
> + reg |= FIELD_PREP(CFG_CONTROL_SUBBUS_MASK, subordinate_bus) |
> + FIELD_PREP(CFG_CONTROL_SEC_BUS_MASK, secondary_bus);
> +
> + writel(reg, cfg_control_addr);
> +
> + return 0;
> +}
> +
> +static int al_pcie_host_init(struct pcie_port *pp)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct al_pcie *pcie = to_al_pcie(pci);
> + int link_up;
> + int rc;
> +
> + link_up = dw_pcie_link_up(pci);
> + if (!link_up) {
> + dev_err(pci->dev, "link is not up!\n");
> + return -ENOLINK;
> + }
> +
> + dev_info(pci->dev, "link is up\n");
Consider s/dev_info/pci_info/g
> +
> + rc = al_pcie_rev_id_get(pcie, &pcie->controller_rev_id);
> + if (rc)
> + return rc;
> +
> + rc = al_pcie_reg_offsets_set(pcie);
> + if (rc)
> + return rc;
> +
> + rc = al_pcie_config_prepare(pcie);
> + if (rc)
> + return rc;
> +
> + return 0;
> +}
> +
> +static const struct dw_pcie_host_ops al_pcie_host_ops = {
> + .rd_other_conf = al_pcie_rd_other_conf,
> + .wr_other_conf = al_pcie_wr_other_conf,
> + .host_init = al_pcie_host_init,
> +};
> +
> +static int al_add_pcie_port(struct pcie_port *pp,
> + struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + int ret;
> +
> + pp->ops = &al_pcie_host_ops;
> +
> + ret = dw_pcie_host_init(pp);
> + if (ret) {
> + dev_err(dev, "failed to initialize host\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static const struct dw_pcie_ops dw_pcie_ops = {
> +};
> +
> +static int al_pcie_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct al_pcie *al_pcie;
> + struct dw_pcie *pci;
> + struct resource *dbi_res;
> + struct resource *controller_res;
> + struct resource *ecam_res;
> + int ret;
Please sort the variables following the reverse tree order.
> +
> + al_pcie = devm_kzalloc(dev, sizeof(*al_pcie), GFP_KERNEL);
> + if (!al_pcie)
> + return -ENOMEM;
> +
> + pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
> + if (!pci)
> + return -ENOMEM;
> +
> + pci->dev = dev;
> + pci->ops = &dw_pcie_ops;
> +
> + al_pcie->pci = pci;
> + al_pcie->dev = dev;
> +
> + dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
> + pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res);
> + if (IS_ERR(pci->dbi_base)) {
> + dev_err(dev, "couldn't remap dbi base %pR\n", dbi_res);
> + return PTR_ERR(pci->dbi_base);
> + }
> +
> + ecam_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
> + if (!ecam_res) {
> + dev_err(dev, "couldn't find 'config' reg in DT\n");
> + return -ENOENT;
> + }
> + al_pcie->ecam_size = resource_size(ecam_res);
> +
> + controller_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> + "controller");
> + al_pcie->controller_base = devm_ioremap_resource(dev, controller_res);
> + if (IS_ERR(al_pcie->controller_base)) {
> + dev_err(dev, "couldn't remap controller base %pR\n",
> + controller_res);
> + return PTR_ERR(al_pcie->controller_base);
> + }
> +
> + dev_dbg(dev, "From DT: dbi_base: %pR, controller_base: %pR\n",
> + dbi_res, controller_res);
> +
> + platform_set_drvdata(pdev, al_pcie);
> +
> + ret = al_add_pcie_port(&pci->pp, pdev);
> + if (ret)
> + return ret;
> +
> + return 0;
Those operations are redundant, aren't they? They can be replaced just
by:
return ret;
> +}
> +
> +static const struct of_device_id al_pcie_of_match[] = {
> + { .compatible = "amazon,al-pcie",
> + },
> + {},
> +};
> +
> +static struct platform_driver al_pcie_driver = {
> + .driver = {
> + .name = "al-pcie",
> + .of_match_table = al_pcie_of_match,
> + .suppress_bind_attrs = true,
> + },
> + .probe = al_pcie_probe,
> +};
> +builtin_platform_driver(al_pcie_driver);
> +
> +#endif /* CONFIG_PCIE_AL*/
> --
> 2.17.1
^ permalink raw reply
* RE: [PATCH v2 7/8] PCI: dw: Add validation that PCIe core is set to correct mode
From: Gustavo Pimentel @ 2019-07-19 9:15 UTC (permalink / raw)
To: Jonathan Chocron, lorenzo.pieralisi@arm.com, bhelgaas@google.com,
jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
robh+dt@kernel.org, mark.rutland@arm.com
Cc: dwmw@amazon.co.uk, benh@kernel.crashing.org, alisaidi@amazon.com,
ronenk@amazon.com, barakw@amazon.com, talel@amazon.com,
hanochu@amazon.com, hhhawa@amazon.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
In-Reply-To: <20190718094718.25083-3-jonnyc@amazon.com>
On Thu, Jul 18, 2019 at 10:47:17, Jonathan Chocron <jonnyc@amazon.com>
wrote:
> Some PCIe controllers can be set to either Host or EP according to some
> early boot FW. To make sure there is no discrepancy (e.g. FW configured
> the port to EP mode while the DT specifies it as a host bridge or vice
> versa), a check has been added for each mode.
>
> Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
> ---
> drivers/pci/controller/dwc/pcie-designware-ep.c | 8 ++++++++
> drivers/pci/controller/dwc/pcie-designware-host.c | 8 ++++++++
> 2 files changed, 16 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 2bf5a35c0570..00e59a134b93 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -531,6 +531,7 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> int ret;
> u32 reg;
> void *addr;
> + u8 hdr_type;
> unsigned int nbars;
> unsigned int offset;
> struct pci_epc *epc;
> @@ -543,6 +544,13 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
> return -EINVAL;
> }
>
> + hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
> + if (hdr_type != PCI_HEADER_TYPE_NORMAL) {
> + dev_err(pci->dev, "PCIe controller is not set to EP mode (hdr_type:0x%x)!\n",
> + hdr_type);
> + return -EIO;
> + }
> +
> ret = of_property_read_u32(np, "num-ib-windows", &ep->num_ib_windows);
> if (ret < 0) {
> dev_err(dev, "Unable to read *num-ib-windows* property\n");
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index f93252d0da5b..d2ca748e4c85 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -323,6 +323,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
> struct pci_bus *child;
> struct pci_host_bridge *bridge;
> struct resource *cfg_res;
> + u8 hdr_type;
> int ret;
>
> raw_spin_lock_init(&pci->pp.lock);
> @@ -396,6 +397,13 @@ int dw_pcie_host_init(struct pcie_port *pp)
> }
> }
>
> + hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
> + if (hdr_type != PCI_HEADER_TYPE_BRIDGE) {
> + dev_err(pci->dev, "PCIe controller is not set to bridge type (hdr_type: 0x%x)!\n",
> + hdr_type);
> + return -EIO;
> + }
> +
> pp->mem_base = pp->mem->start;
>
> if (!pp->va_cfg0_base) {
> --
> 2.17.1
It doesn't harm.
Thanks.
Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
^ permalink raw reply
* RE: [PATCH v2 4/8] PCI: Add quirk to disable MSI-X support for Amazon's Annapurna Labs Root Port
From: Gustavo Pimentel @ 2019-07-19 9:17 UTC (permalink / raw)
To: Jonathan Chocron, lorenzo.pieralisi@arm.com, bhelgaas@google.com,
jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
robh+dt@kernel.org, mark.rutland@arm.com
Cc: dwmw@amazon.co.uk, benh@kernel.crashing.org, alisaidi@amazon.com,
ronenk@amazon.com, barakw@amazon.com, talel@amazon.com,
hanochu@amazon.com, hhhawa@amazon.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
In-Reply-To: <20190718094531.21423-5-jonnyc@amazon.com>
On Thu, Jul 18, 2019 at 10:45:27, Jonathan Chocron <jonnyc@amazon.com>
wrote:
> The Root Port (identified by [1c36:0032]) doesn't support MSI-X. On some
> platforms it is configured to not advertise the capability at all, while
> on others it (mistakenly) does. This causes a panic during
> initialization by the pcieport driver, since it tries to configure the
> MSI-X capability. Specifically, when trying to access the MSI-X table
> a "non-existing addr" exception occurs.
>
> Example stacktrace snippet:
>
> [ 1.632363] SError Interrupt on CPU2, code 0xbf000000 -- SError
> [ 1.632364] CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.2.0-rc1-Jonny-14847-ge76f1d4a1828-dirty #33
> [ 1.632365] Hardware name: Annapurna Labs Alpine V3 EVP (DT)
> [ 1.632365] pstate: 80000005 (Nzcv daif -PAN -UAO)
> [ 1.632366] pc : __pci_enable_msix_range+0x4e4/0x608
> [ 1.632367] lr : __pci_enable_msix_range+0x498/0x608
> [ 1.632367] sp : ffffff80117db700
> [ 1.632368] x29: ffffff80117db700 x28: 0000000000000001
> [ 1.632370] x27: 0000000000000001 x26: 0000000000000000
> [ 1.632372] x25: ffffffd3e9d8c0b0 x24: 0000000000000000
> [ 1.632373] x23: 0000000000000000 x22: 0000000000000000
> [ 1.632375] x21: 0000000000000001 x20: 0000000000000000
> [ 1.632376] x19: ffffffd3e9d8c000 x18: ffffffffffffffff
> [ 1.632378] x17: 0000000000000000 x16: 0000000000000000
> [ 1.632379] x15: ffffff80116496c8 x14: ffffffd3e9844503
> [ 1.632380] x13: ffffffd3e9844502 x12: 0000000000000038
> [ 1.632382] x11: ffffffffffffff00 x10: 0000000000000040
> [ 1.632384] x9 : ffffff801165e270 x8 : ffffff801165e268
> [ 1.632385] x7 : 0000000000000002 x6 : 00000000000000b2
> [ 1.632387] x5 : ffffffd3e9d8c2c0 x4 : 0000000000000000
> [ 1.632388] x3 : 0000000000000000 x2 : 0000000000000000
> [ 1.632390] x1 : 0000000000000000 x0 : ffffffd3e9844680
> [ 1.632392] Kernel panic - not syncing: Asynchronous SError Interrupt
> [ 1.632393] CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.2.0-rc1-Jonny-14847-ge76f1d4a1828-dirty #33
> [ 1.632394] Hardware name: Annapurna Labs Alpine V3 EVP (DT)
> [ 1.632394] Call trace:
> [ 1.632395] dump_backtrace+0x0/0x140
> [ 1.632395] show_stack+0x14/0x20
> [ 1.632396] dump_stack+0xa8/0xcc
> [ 1.632396] panic+0x140/0x334
> [ 1.632397] nmi_panic+0x6c/0x70
> [ 1.632398] arm64_serror_panic+0x74/0x88
> [ 1.632398] __pte_error+0x0/0x28
> [ 1.632399] el1_error+0x84/0xf8
> [ 1.632400] __pci_enable_msix_range+0x4e4/0x608
> [ 1.632400] pci_alloc_irq_vectors_affinity+0xdc/0x150
> [ 1.632401] pcie_port_device_register+0x2b8/0x4e0
> [ 1.632402] pcie_portdrv_probe+0x34/0xf0
>
> Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
> ---
> drivers/pci/quirks.c | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 23672680dba7..11f843aa96b3 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -2925,6 +2925,21 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
> quirk_msi_intx_disable_qca_bug);
> DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
> quirk_msi_intx_disable_qca_bug);
> +
> +/*
> + * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it
> + * should be disabled on platforms where the device (mistakenly) advertises it.
> + *
> + * The 0031 device id is reused for other non Root Port device types,
> + * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
> + */
> +static void quirk_al_msi_disable(struct pci_dev *dev)
> +{
> + dev->no_msi = 1;
> + pci_warn(dev, "Disabling MSI-X\n");
> +}
> +DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
> + PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable);
> #endif /* CONFIG_PCI_MSI */
>
> /*
> --
> 2.17.1
Reviewed-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
^ permalink raw reply
* Re: [PATCHv8 1/5] arm64: dts: qcom: sdm845: Add Coresight support
From: Suzuki K Poulose @ 2019-07-19 9:46 UTC (permalink / raw)
To: saiprakash.ranjan, gregkh, mathieu.poirier, leo.yan,
alexander.shishkin, mike.leach, robh+dt, bjorn.andersson,
devicetree, david.brown, mark.rutland
Cc: rnayak, vivek.gautam, sibis, linux-arm-kernel, linux-kernel,
linux-arm-msm, marc.w.gonzalez
In-Reply-To: <52550ed9bbc10dca860eb1700aef5c97f644327b.1562940244.git.saiprakash.ranjan@codeaurora.org>
Hi Sai,
On 12/07/2019 15:16, Sai Prakash Ranjan wrote:
> Add coresight components found on Qualcomm SDM845 SoC.
>
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 451 +++++++++++++++++++++++++++
> 1 file changed, 451 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 4babff5f19b5..5d7e3f8e0f91 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -1815,6 +1815,457 @@
> clock-names = "xo";
> };
>
> + stm@6002000 {
> + compatible = "arm,coresight-stm", "arm,primecell";
> + reg = <0 0x06002000 0 0x1000>,
> + <0 0x16280000 0 0x180000>;
> + reg-names = "stm-base", "stm-stimulus-base";
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + stm_out: endpoint {
> + remote-endpoint =
> + <&funnel0_in7>;
> + };
> + };
> + };
> + };
> +
> + funnel@6041000 {
> + compatible = "arm,coresight-funnel", "arm,primecell";
We added support for static funnels and have thus updated our DT bindings. And
that implies, the above binding is now obsolete.
As of the coresight/next tree, and thus linux-next, this must be
arm,coresight-dynamic-funnel and same applies everywhere else in the series.
Please could you
update the series ?
Kind regards
Suzuki
^ permalink raw reply
* [v2 2/3] dt/bindings: display: Add optional property node defined for Mali DP500
From: Wen He @ 2019-07-19 9:58 UTC (permalink / raw)
To: linux-kernel, dri-devel, devicetree, mark.rutland, liviu.dudau,
brian.starkey, airlied, daniel, robh+dt
Cc: leoyang.li, Wen He
Add optional property node 'arm,malidp-arqos-value' for the Mali DP500.
This property describe the ARQoS levels of DP500's QoS signaling.
Signed-off-by: Wen He <wen.he_1@nxp.com>
---
Documentation/devicetree/bindings/display/arm,malidp.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/arm,malidp.txt b/Documentation/devicetree/bindings/display/arm,malidp.txt
index 2f7870983ef1..76a0e7251251 100644
--- a/Documentation/devicetree/bindings/display/arm,malidp.txt
+++ b/Documentation/devicetree/bindings/display/arm,malidp.txt
@@ -37,6 +37,8 @@ Optional properties:
Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt)
to be used for the framebuffer; if not present, the framebuffer may
be located anywhere in memory.
+ - arm,malidp-arqos-high-level: integer of u32 value describing the ARQoS
+ levels of DP500's QoS signaling.
Example:
@@ -54,6 +56,7 @@ Example:
clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>;
clock-names = "pxlclk", "mclk", "aclk", "pclk";
arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
+ arm,malidp-arqos-high-level = <&rqosvalue>;
port {
dp0_output: endpoint {
remote-endpoint = <&tda998x_2_input>;
--
2.17.1
^ permalink raw reply related
* [v2 3/3] dts: arm64: ls1028a: Add optional property node for Mali DP500
From: Wen He @ 2019-07-19 9:59 UTC (permalink / raw)
To: linux-kernel, devicetree, mark.rutland, shawnguo, liviu.dudau,
robh+dt
Cc: leoyang.li, Wen He
This patch use the optional property node "arm,malidp-arqos-value" to
can be dynamic configure QoS signaling.
Signed-off-by: Wen He <wen.he_1@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 7975519b4f56..aef5b06a98d5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -554,6 +554,7 @@
clocks = <&dpclk>, <&aclk>, <&aclk>, <&pclk>;
clock-names = "pxlclk", "mclk", "aclk", "pclk";
arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
+ arm,malidp-arqos-value = <0xd000d000>;
port {
dp0_out: endpoint {
--
2.17.1
^ permalink raw reply related
* [v2 1/4] dt-bindings: display: Add DT bindings for LS1028A HDP-TX PHY.
From: Wen He @ 2019-07-19 10:09 UTC (permalink / raw)
To: linux-kernel, dri-devel, devicetree, mark.rutland, shawnguo,
robh+dt
Cc: leoyang.li, Wen He
Add DT bindings documentmation for the HDP-TX PHY controller. The describes
which could be found on NXP Layerscape ls1028a platform.
Signed-off-by: Wen He <wen.he_1@nxp.com>
---
change in v2:
- correction the node name.
.../devicetree/bindings/display/fsl,hdp.txt | 56 +++++++++++++++++++
1 file changed, 56 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/fsl,hdp.txt
diff --git a/Documentation/devicetree/bindings/display/fsl,hdp.txt b/Documentation/devicetree/bindings/display/fsl,hdp.txt
new file mode 100644
index 000000000000..53ca08337587
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/fsl,hdp.txt
@@ -0,0 +1,56 @@
+NXP Layerscpae ls1028a HDP-TX PHY Controller
+============================================
+
+The following bindings describe the Cadence HDP TX PHY on ls1028a that
+offer multi-protocol support of standars such as eDP and Displayport,
+supports for 25-600MHz pixel clock and up to 4k2k at 60MHz resolution.
+The HDP transmitter is a Cadence HDP TX controller IP with a companion
+PHY IP.
+
+Required properties:
+ - compatible: Should be "fsl,ls1028a-dp" for ls1028a.
+ - reg: Physical base address and size of the block of registers used
+ by the processor.
+ - interrupts: HDP hotplug in/out detect interrupt number
+ - clocks: A list of phandle + clock-specifier pairs, one for each entry
+ in 'clock-names'
+ - clock-names: A list of clock names. It should contain:
+ - "clk_ipg": inter-Integrated circuit clock
+ - "clk_core": for the Main Display TX controller clock
+ - "clk_pxl": for the pixel clock feeding the output PLL of the processor
+ - "clk_pxl_mux": for the high PerfPLL bypass clock
+ - "clk_pxl_link": for the link rate pixel clock
+ - "clk_apb": for the APB interface clock
+ - "clk_vif": for the Video pixel clock
+
+Required sub-nodes:
+ - port: The HDP connection to an encoder output port. The connection
+ is modelled using the OF graph bindings specified in
+ Documentation/devicetree/bindings/graph.txt
+
+
+Example:
+
+/ {
+ ...
+
+ hdptx0: display@f200000 {
+ compatible = "fsl,ls1028a-dp";
+ reg = <0x0 0xf1f0000 0x0 0xffff>,
+ <0x0 0xf200000 0x0 0xfffff>;
+ interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sysclk>, <&hdpclk>, <&dpclk>,
+ <&dpclk>, <&dpclk>, <&pclk>, <&dpclk>;
+ clock-names = "clk_ipg", "clk_core", "clk_pxl",
+ "clk_pxl_mux", "clk_pxl_link", "clk_apb",
+ "clk_vif";
+
+ port {
+ dp1_output: endpoint {
+ remote-endpoint = <&dp0_input>;
+ };
+ };
+ };
+
+ ...
+};
--
2.17.1
^ permalink raw reply related
* [v2 2/4] arm64: dts: ls1028a: Add properties for HDP Controller.
From: Wen He @ 2019-07-19 10:09 UTC (permalink / raw)
To: linux-kernel, dri-devel, devicetree, mark.rutland, shawnguo,
robh+dt
Cc: leoyang.li, Wen He
In-Reply-To: <20190719100942.12016-1-wen.he_1@nxp.com>
This patch enables the HDP controller driver on the LS1028A.
Signed-off-by: Alison Wang <aslion.wang@nxp.com>
Signed-off-by: Wen He <wen.he_1@nxp.com>
---
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index aef5b06a98d5..19612ad9a4a1 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -91,6 +91,13 @@
clock-output-names= "pclk";
};
+ hdpclk: clock-hdpcore {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <162500000>;
+ clock-output-names= "hdpclk";
+ };
+
reboot {
compatible ="syscon-reboot";
regmap = <&dcfg>;
@@ -558,7 +565,25 @@
port {
dp0_out: endpoint {
+ remote-endpoint = <&dp1_out>;
+ };
+ };
+ };
+ hdptx0: display@f200000 {
+ compatible = "fsl,ls1028a-dp";
+ reg = <0x0 0xf1f0000 0x0 0xffff>,
+ <0x0 0xf200000 0x0 0xfffff>;
+ interrupts = <0 221 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sysclk>, <&hdpclk>, <&dpclk>,
+ <&dpclk>, <&dpclk>, <&pclk>, <&dpclk>;
+ clock-names = "clk_ipg", "clk_core", "clk_pxl",
+ "clk_pxl_mux", "clk_pxl_link", "clk_apb",
+ "clk_vif";
+
+ port {
+ dp1_out: endpoint {
+ remote-endpoint = <&dp0_out>;
};
};
};
--
2.17.1
^ permalink raw reply related
* [v2 3/4] arm64: ls1028ardb: Add support DP nodes for LS1028ARDB
From: Wen He @ 2019-07-19 10:09 UTC (permalink / raw)
To: linux-kernel, dri-devel, devicetree, mark.rutland, shawnguo,
robh+dt
Cc: leoyang.li, Wen He
In-Reply-To: <20190719100942.12016-1-wen.he_1@nxp.com>
This patch add HDP PHY Controller related nodes on the LS1028ARDB.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Wen He <wen.he_1@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index 9fb911317ecd..a907eb2c000b 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -171,3 +171,15 @@
&sata {
status = "okay";
};
+
+&hdptx0 {
+ fsl,no_edid;
+ resolution = "3840x2160@60",
+ "1920x1080@60",
+ "1280x720@60",
+ "720x480@60";
+ lane_mapping = <0x4e>;
+ edp_link_rate = <0x6>;
+ edp_num_lanes = <0x4>;
+ status = "okay";
+};
--
2.17.1
^ permalink raw reply related
* [v2 4/4] arm64: ls1028aqds: Add support DP nodes for LS1028AQDS
From: Wen He @ 2019-07-19 10:09 UTC (permalink / raw)
To: linux-kernel, dri-devel, devicetree, mark.rutland, shawnguo,
robh+dt
Cc: leoyang.li, Wen He
In-Reply-To: <20190719100942.12016-1-wen.he_1@nxp.com>
This patch add HDP PHY Controller related nodes on the LS1028AQDS.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Wen He <wen.he_1@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index de6ef39f3118..a9af6e8a6517 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -173,3 +173,15 @@
&sata {
status = "okay";
};
+
+&hdptx0 {
+ fsl,no_edid;
+ resolution = "3840x2160@60",
+ "1920x1080@60",
+ "1280x720@60",
+ "720x480@60";
+ lane_mapping = <0x4e>;
+ edp_link_rate = <0x6>;
+ edp_num_lanes = <0x4>;
+ status = "okay";
+};
--
2.17.1
^ permalink raw reply related
* Re: [PATCH 1/3] Revert "usb: usb251xb: Add US lanes inversion dts-bindings"
From: Serge Semin @ 2019-07-19 10:13 UTC (permalink / raw)
To: Lucas Stach
Cc: Richard Leitner, Greg Kroah-Hartman, Rob Herring, Mark Rutland,
linux-usb, devicetree, kernel, patchwork-lst
In-Reply-To: <20190719084407.28041-1-l.stach@pengutronix.de>
Hello Lucas
On Fri, Jul 19, 2019 at 10:44:05AM +0200, Lucas Stach wrote:
> This reverts commit 3342ce35a1, as there is no need for this separate
> property and it breaks compatibility with existing devicetree files
> (arch/arm64/boot/dts/freescale/imx8mq.dtsi).
>
Hmm, didn't know there had been anything staged to merge and touching this
property before submitting the update. We must have done it nearly at the same
time, or your patch hasn't been merged at the time I prepared mine.
Anyway why would you prefer to change the interface again instead of
following the existing way? Firstly It is much easier to fix the dts-file
than to revert the interface back and break dts-files of possible other users.
Secondly the chip documentation doesn't have anything regarding port 0.
It states to swap the Ports from 1 to 4 (usb2514) corresponding to the bits
1 - 4 of the 'PORT SWAP' register, while bit 0 is connected with explicitly
named Upstream Port (without any numbering). Thirdly having a separate
property for US port makes the driver bindings interface a bit better
readable/logical, since in current implementation there is no implicit/unspoken/hidden
rule that port 0 corresponds to the Upstream Port, Port 0 just doesn't exists
(following the chip datasheet text), and the other port-related properties are
only applicable for downstream ports. So the driver code rejects them being
utilized for a port with 0 identifier. The only port-related setting being
exposed by the interface is the swap-port-one and it has a separately bound
property 'swap-us-lanes' for the Upstream port.
As for me, all of this makes more sense than having an implicit Port 0 - Upstream
port binding (as you suggest). Although the final decision of which solution is
better is after the subsystem maintainer after all.
Regards,
-Sergey
> CC: stable@vger.kernel.org #5.2
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> Documentation/devicetree/bindings/usb/usb251xb.txt | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/usb/usb251xb.txt b/Documentation/devicetree/bindings/usb/usb251xb.txt
> index bc7945e9dbfe..17915f64b8ee 100644
> --- a/Documentation/devicetree/bindings/usb/usb251xb.txt
> +++ b/Documentation/devicetree/bindings/usb/usb251xb.txt
> @@ -64,10 +64,8 @@ Optional properties :
> - power-on-time-ms : Specifies the time it takes from the time the host
> initiates the power-on sequence to a port until the port has adequate
> power. The value is given in ms in a 0 - 510 range (default is 100ms).
> - - swap-dx-lanes : Specifies the downstream ports which will swap the
> - differential-pair (D+/D-), default is not-swapped.
> - - swap-us-lanes : Selects the upstream port differential-pair (D+/D-)
> - swapping (boolean, default is not-swapped)
> + - swap-dx-lanes : Specifies the ports which will swap the differential-pair
> + (D+/D-), default is not-swapped.
>
> Examples:
> usb2512b@2c {
> --
> 2.20.1
>
^ permalink raw reply
* Re: [PATCH v3 1/2] arm64: dts: fsl: pico-pi: Add a device tree for the PICO-PI-IMX8M
From: Andra Danciu @ 2019-07-19 10:20 UTC (permalink / raw)
To: Fabio Estevam
Cc: Shawn Guo, Rob Herring, Mark Rutland, Manivannan Sadhasivam,
Andrey Smirnov, Uwe Kleine-König, Dong Aisheng, Li Yang,
sriram.dash, Lucas Stach, pankaj.bansal, Ping Bai, Pramod Kumar,
Bhaskar Upadhaya, Richard Hu,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel
In-Reply-To: <CAOMZO5B-9+JnbfrTWP8GTuc0VcnDDPEZq-iXGbYVx9a6O9gwRg@mail.gmail.com>
Hi Fabio,
Please find my answers inline:
În vin., 19 iul. 2019 la 02:05, Fabio Estevam <festevam@gmail.com> a scris:
>
> Hi Andra,
>
> On Thu, Jul 18, 2019 at 9:16 AM Andra Danciu <andradanciu1997@gmail.com> wrote:
> >
> > From: Richard Hu <richard.hu@technexion.com>
>
> Please put a few words about the board and a link to its webpage, if available.
OK
>
> > The current level of support yields a working console and is able to boot
> > userspace from NFS or init ramdisk.
> >
> > Additional subsystems that are active :
> > - Ethernet
> > - USB
> >
> > Cc: Daniel Baluta <daniel.baluta@nxp.com>
> > Signed-off-by: Richard Hu <richard.hu@technexion.com>
> > Signed-off-by: Andra Danciu <andradanciu1997@gmail.com>
> > ---
> > arch/arm64/boot/dts/freescale/Makefile | 1 +
> > arch/arm64/boot/dts/freescale/pico-pi-8m.dts | 417 +++++++++++++++++++++++++++
> > 2 files changed, 418 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/freescale/pico-pi-8m.dts
> >
> > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> > index c043aca66572..538422903e8a 100644
> > --- a/arch/arm64/boot/dts/freescale/Makefile
> > +++ b/arch/arm64/boot/dts/freescale/Makefile
> > @@ -26,3 +26,4 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
> > dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
> > +dtb-$(CONFIG_ARCH_MXC) += pico-pi-8m.dtb
>
> The convention we use with imx dtbs is to put the SoC name first, so
> that would become:
>
> imx8mq-pico-pi.dtb
Will do.
>
>
> > +&iomuxc {
>
> Please place iomuxc node as the last one.
Will do.
>
> > +&fec1 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_fec1 &pinctrl_enet_3v3>;
> > + phy-mode = "rgmii-id";
> > + pinctrl-assert-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
>
> This property does not exist.
OK, I will remove it.
>
> > + phy-handle = <ðphy0>;
> > + fsl,magic-packet;
> > + status = "okay";
> > +
> > + mdio {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + ethphy0: ethernet-phy@1 {
> > + compatible = "ethernet-phy-ieee802.3-c22";
> > + reg = <1>;
> > + at803x,led-act-blind-workaround;
> > + at803x,eee-disabled;
>
> These two properties do not exist.
OK, I will remove them.
>
> > +&i2c1 {
> > + clock-frequency = <100000>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_i2c1>;
> > + status = "okay";
> > +
> > + pmic: pmic@4b {
> > + reg = <0x4b>;
> > + compatible = "rohm,bd71837";
> > + /* PMIC BD71837 PMIC_nINT GPIO1_IO12 */
> > + pinctrl-0 = <&pinctrl_pmic>;
>
> pinctrl-names = "default" is missing
OK, will add.
>
> > + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
>
> This is not documented.
>
> Please look at Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.txt
> for the valid bindings and also at
> arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts for a
> reference for adding the BD71837 support.
OK, will do.
>
> > +&A53_0 {
> > + operating-points = <
> > + /* kHz uV */
> > + 1500000 1000000
> > + 1300000 1000000
> > + 1000000 900000
> > + 800000 900000
>
> This is not needed as these operating points are already specified at
> imx8mq.dtsi.
OK, I will remove it.
^ permalink raw reply
* Re: [PATCHv8 1/5] arm64: dts: qcom: sdm845: Add Coresight support
From: Sai Prakash Ranjan @ 2019-07-19 10:28 UTC (permalink / raw)
To: Suzuki K Poulose, gregkh, mathieu.poirier, leo.yan,
alexander.shishkin, mike.leach, robh+dt, bjorn.andersson,
devicetree, david.brown, mark.rutland
Cc: rnayak, vivek.gautam, sibis, linux-arm-kernel, linux-kernel,
linux-arm-msm, marc.w.gonzalez
In-Reply-To: <33215f68-1bf9-322a-d889-1d22514bdbdc@arm.com>
Hi Suzuki,
On 7/19/2019 3:16 PM, Suzuki K Poulose wrote:
>
> Hi Sai,
>
>
> On 12/07/2019 15:16, Sai Prakash Ranjan wrote:
>> Add coresight components found on Qualcomm SDM845 SoC.
>>
>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>> ---
>> arch/arm64/boot/dts/qcom/sdm845.dtsi | 451 +++++++++++++++++++++++++++
>> 1 file changed, 451 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> index 4babff5f19b5..5d7e3f8e0f91 100644
>> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> @@ -1815,6 +1815,457 @@
>> clock-names = "xo";
>> };
>> + stm@6002000 {
>> + compatible = "arm,coresight-stm", "arm,primecell";
>> + reg = <0 0x06002000 0 0x1000>,
>> + <0 0x16280000 0 0x180000>;
>> + reg-names = "stm-base", "stm-stimulus-base";
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + stm_out: endpoint {
>> + remote-endpoint =
>> + <&funnel0_in7>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + funnel@6041000 {
>> + compatible = "arm,coresight-funnel", "arm,primecell";
>
> We added support for static funnels and have thus updated our DT
> bindings. And
> that implies, the above binding is now obsolete.
> As of the coresight/next tree, and thus linux-next, this must be
> arm,coresight-dynamic-funnel and same applies everywhere else in the
> series. Please could you
> update the series ?
>
Sure, will update in the next version of the series.
Thanks,
Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply
* [PATCH v2] arm: dts: imx6qdl: add gpio expander pca9535
From: Gilles DOFFE @ 2019-07-19 10:46 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, linux-kernel
Cc: jerome.oufella, rennes, robh+dt, mark.rutland, shawnguo, s.hauer,
kernel, festevam, linux-imx
The pca9535 gpio expander is present on the Rex baseboard, but missing
from the dtsi.
Add the new gpio controller and the associated interrupt line
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16.
Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
---
arch/arm/boot/dts/imx6qdl-rex.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/imx6qdl-rex.dtsi
index 97f1659144ea..b517efb22fcb 100644
--- a/arch/arm/boot/dts/imx6qdl-rex.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-rex.dtsi
@@ -136,6 +136,19 @@
compatible = "atmel,24c02";
reg = <0x57>;
};
+
+ pca9535: gpio8@27 {
+ compatible = "nxp,pca9535";
+ reg = <0x27>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pca9535>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
};
&i2c3 {
@@ -237,6 +250,12 @@
>;
};
+ pinctrl_pca9535: pca9535 {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x00017059
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
--
2.19.1
^ permalink raw reply related
* [PATCH v4 0/2] Add basic support for pico-pi-imx8m
From: andradanciu1997 @ 2019-07-19 10:48 UTC (permalink / raw)
To: shawnguo
Cc: robh+dt, mark.rutland, s.hauer, kernel, festevam, linux-imx,
andrew.smirnov, manivannan.sadhasivam, ping.bai, Michal.Vokac,
leoyang.li, sriram.dash, l.stach, vabhav.sharma, bhaskar.upadhaya,
pramod.kumar_1, pankaj.bansal, aisheng.dong, angus, richard.hu,
andradanciu1997, devicetree, linux-kernel, linux-arm-kernel
Add support for TechNexion PICO-PI-IMX8M based on patches from Richard Hu
Datasheet is at: https://s3.us-east-2.amazonaws.com/technexion/datasheets/picopiimx8m.pdf
Changes since v3:
- renamed pico-pi-8m.dts to imx8mq-pico-pi.dts
- moved iomuxc node as the last one
- removed pinctrl-assert-gpios property from fec1 node
- removed at803x,led-act-blind-workaround, at803x,eee-disabled
properties from mdio node
- added pinctrl-names = "default" to i2c1 node
- changed bd71837 pmic support properties according to
Documentation/devicetree/bindings/regulator/rohm,bd71837-regulator.txt
- removed A53_0 node
Changes since v2:
- changed PICO-PI-8M bord compatible from wand,imx8mq-pico-pi to
technexion,pico-pi-imx8m
- removed bootargs property
- removed regulators node and put fixed regulator directly under root node
- changed node name from usb_otg_vbus to regulator-usb-otg-vbus
- removed pinctrl-names property from iomuxc node
- removed wand-pi-8m container node
- sorted pinctrl nodes alphabetically
- removed tusb320_irqgrp, tusb320_irqgrp nodes because there is no upstream
driver
- changed properties' order in usb_dwc3_1 node
Changes since v1:
- renamed wandboard-pi-8m.dts to pico-pi-8m.dts
- removed pinctrl_csi1, pinctrl_wifi_ctrl
- used generic name for pmic
- removed gpo node
- delete regulator-virtuals node
- remove always-on property from buck1-8 and ldo3-7
- remove pmic-buck-uses-i2c-dvs property for buck1-4
Andra Danciu (1):
dt-bindings: arm: fsl: Add the pico-pi-imx8m board
Richard Hu (1):
arm64: dts: fsl: pico-pi: Add a device tree for the PICO-PI-IMX8M
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts | 417 +++++++++++++++++++++++
3 files changed, 419 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts
--
2.11.0
^ permalink raw reply
* [PATCH v4 1/2] arm64: dts: fsl: pico-pi: Add a device tree for the PICO-PI-IMX8M
From: andradanciu1997 @ 2019-07-19 10:48 UTC (permalink / raw)
To: shawnguo
Cc: robh+dt, mark.rutland, s.hauer, kernel, festevam, linux-imx,
andrew.smirnov, manivannan.sadhasivam, ping.bai, Michal.Vokac,
leoyang.li, sriram.dash, l.stach, vabhav.sharma, bhaskar.upadhaya,
pramod.kumar_1, pankaj.bansal, aisheng.dong, angus, richard.hu,
andradanciu1997, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20190719104802.18070-1-andradanciu1997@gmail.com>
From: Richard Hu <richard.hu@technexion.com>
TechNexion PICO-PI-IMX8M-DEV evaluation and development kit based on
NXP i.MX8M Quad applications processor. Datasheet can be found at:
https://s3.us-east-2.amazonaws.com/technexion/datasheets/picopiimx8m.pdf
The current level of support yields a working console and is able to boot
userspace from NFS or init ramdisk.
Additional subsystems that are active :
- Ethernet
- USB
Cc: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Richard Hu <richard.hu@technexion.com>
Signed-off-by: Andra Danciu <andradanciu1997@gmail.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts | 417 +++++++++++++++++++++++
2 files changed, 418 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index c043aca66572..99627a499a73 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -23,6 +23,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts b/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts
new file mode 100644
index 000000000000..179b213a816f
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts
@@ -0,0 +1,417 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 Wandboard, Org.
+ * Copyright 2017 NXP
+ *
+ * Author: Richard Hu <hakahu@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "imx8mq.dtsi"
+
+/ {
+ model = "TechNexion PICO-PI-8M";
+ compatible = "technexion,pico-pi-imx8m", "fsl,imx8mq";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ pmic_osc: clock-pmic {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "pmic_osc";
+ };
+
+ reg_usb_otg_vbus: regulator-usb-otg-vbus {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_otg_vbus>;
+ compatible = "regulator-fixed";
+ regulator-name = "usb_otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 14 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fec1 &pinctrl_enet_3v3>;
+ phy-mode = "rgmii-id";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ pmic: pmic@4b {
+ reg = <0x4b>;
+ compatible = "rohm,bd71837";
+ /* PMIC BD71837 PMIC_nINT GPIO1_IO12 */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pmic>;
+ clocks = <&pmic_osc>;
+ clock-names = "osc";
+ clock-output-names = "pmic_clk";
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 GPIO_ACTIVE_LOW>;
+ interrupt-names = "irq";
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ buck1: BUCK1 {
+ regulator-name = "buck1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <900000>;
+ rohm,dvs-idle-voltage = <850000>;
+ rohm,dvs-suspend-voltage = <800000>;
+ };
+
+ buck2: BUCK2 {
+ regulator-name = "buck2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-ramp-delay = <1250>;
+ rohm,dvs-run-voltage = <1000000>;
+ rohm,dvs-idle-voltage = <900000>;
+ };
+
+ buck3: BUCK3 {
+ regulator-name = "buck3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ rohm,dvs-run-voltage = <1000000>;
+ };
+
+ buck4: BUCK4 {
+ regulator-name = "buck4";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ rohm,dvs-run-voltage = <1000000>;
+ };
+
+ buck5: BUCK5 {
+ regulator-name = "buck5";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-boot-on;
+ };
+
+ buck6: BUCK6 {
+ regulator-name = "buck6";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+
+ buck7: BUCK7 {
+ regulator-name = "buck7";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ };
+
+ buck8: BUCK8 {
+ regulator-name = "buck8";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ };
+
+ ldo1: LDO1 {
+ regulator-name = "ldo1";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2: LDO2 {
+ regulator-name = "ldo2";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3: LDO3 {
+ regulator-name = "ldo3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+
+ ldo4: LDO4 {
+ regulator-name = "ldo4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
+
+ ldo5: LDO5 {
+ regulator-name = "ldo5";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+
+ ldo6: LDO6 {
+ regulator-name = "ldo6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ };
+
+ ldo7: LDO7 {
+ regulator-name = "ldo7";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&uart1 { /* console */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ bus-width = <4>;
+ cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_enet_3v3: enet3v3grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19
+ >;
+ };
+
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
+ MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
+ MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
+ MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
+ MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
+ MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
+ MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
+ MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
+ MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
+ MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
+ MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
+ MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
+ MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
+ MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
+ MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
+ MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_otg_vbus: otgvbusgrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* USB OTG VBUS Enable */
+ >;
+ };
+
+ pinctrl_pmic: pmicirq {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
+ MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
+ MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
+ MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
+ MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
+ MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
+ MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
+ MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
+ MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
+ MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
+ MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
+ MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
+ MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
+ MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
+ MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
+ MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
+ MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
+ MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
+ MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
+ MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
+ MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
+ >;
+ };
+};
--
2.11.0
^ permalink raw reply related
* [PATCH v4 2/2] dt-bindings: arm: fsl: Add the pico-pi-imx8m board
From: andradanciu1997 @ 2019-07-19 10:48 UTC (permalink / raw)
To: shawnguo
Cc: robh+dt, mark.rutland, s.hauer, kernel, festevam, linux-imx,
andrew.smirnov, manivannan.sadhasivam, ping.bai, Michal.Vokac,
leoyang.li, sriram.dash, l.stach, vabhav.sharma, bhaskar.upadhaya,
pramod.kumar_1, pankaj.bansal, aisheng.dong, angus, richard.hu,
andradanciu1997, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20190719104802.18070-1-andradanciu1997@gmail.com>
From: Andra Danciu <andradanciu1997@gmail.com>
Add an entry for TechNexion PICO-PI-IMX8M board based on i.MX8MQ SoC
Datasheet can be found at:
https://s3.us-east-2.amazonaws.com/technexion/datasheets/picopiimx8m.pdf
Cc: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Andra Danciu <andradanciu1997@gmail.com>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 7294ac36f4c0..54c094341121 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -219,6 +219,7 @@ properties:
- enum:
- fsl,imx8mq-evk # i.MX8MQ EVK Board
- purism,librem5-devkit # Purism Librem5 devkit
+ - technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk
- const: fsl,imx8mq
- description: i.MX8QXP based Boards
--
2.11.0
^ permalink raw reply related
* Re: [PATCH] arm: dts: imx6qdl: add gpio expander pca9535
From: Gilles Doffe @ 2019-07-19 10:51 UTC (permalink / raw)
To: Marco Felsch
Cc: linux-kernel, linux-arm-kernel, devicetree, mark rutland,
festevam, s hauer, robh+dt, linux-imx, kernel, shawnguo
In-Reply-To: <20190712135541.55fgchvyp33cl3uv@pengutronix.de>
Hello Marco,
Thanks for your review.
Corrected in v2.
Regards,
Gilles
----- Le 12 Juil 19, à 15:55, Marco Felsch m.felsch@pengutronix.de a écrit :
Hi,
On 19-07-12 14:45, Gilles DOFFE wrote:
> The pca9535 gpio expander is present on the Rex baseboard, but missing
> from the dtsi.
>
> Add the new gpio controller and the associated interrupt line
> MX6QDL_PAD_NANDF_CS3__GPIO6_IO16.
>
> Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
> ---
> arch/arm/boot/dts/imx6qdl-rex.dtsi | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/imx6qdl-rex.dtsi
> index 97f1659144ea..d5324c6761c1 100644
> --- a/arch/arm/boot/dts/imx6qdl-rex.dtsi
> +++ b/arch/arm/boot/dts/imx6qdl-rex.dtsi
> @@ -136,6 +136,19 @@
> compatible = "atmel,24c02";
> reg = <0x57>;
> };
> +
> + gpio8: pca9535@27 {
Just a nitpick, I would change that to
pca9535: gpio8@27 {
Regards,
Marco
> + compatible = "nxp,pca9535";
> + reg = <0x27>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pca9535>;
> + interrupt-parent = <&gpio6>;
> + interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> };
>
> &i2c3 {
> @@ -237,6 +250,12 @@
> >;
> };
>
> + pinctrl_pca9535: pca9535 {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x00017059
> + >;
> + };
> +
> pinctrl_uart1: uart1grp {
> fsl,pins = <
> MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
> --
> 2.19.1
>
>
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* Re: [RFC PATCH 23/30] of/platform: Export of_platform_device_create_pdata()
From: Kishon Vijay Abraham I @ 2019-07-19 10:55 UTC (permalink / raw)
To: Rob Herring, Lorenzo Pieralisi
Cc: Tom Joseph, Bjorn Helgaas, Mark Rutland, Arnd Bergmann,
Gustavo Pimentel, Greg Kroah-Hartman, Frank Rowand, Jingoo Han,
linux-pci, devicetree, linux-kernel@vger.kernel.org, linux-omap,
open list:ARM/Rockchip SoC...,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <a80c7c33-7091-70d9-cd86-a19fe43d3bc6@ti.com>
Lorenzo,
On 11/06/19 10:08 AM, Kishon Vijay Abraham I wrote:
> Hi Rob,
>
> On 10/06/19 11:13 PM, Rob Herring wrote:
>> On Tue, Jun 4, 2019 at 7:19 AM Kishon Vijay Abraham I <kishon@ti.com> wrote:
>>>
>>> Export of_platform_device_create_pdata() to be used by drivers to
>>> create child devices with the given platform data. This can be used
>>> by platform specific driver to send platform data core driver. For e.g.,
>>> this will be used by TI's J721E SoC specific PCIe driver to send
>>> ->start_link() ops and ->is_link_up() ops to Cadence core PCIe driver.
>>
>> NAK
>>
>> of_platform_device_create_pdata() is purely for legacy handling of
>> auxdata which is something I hope to get rid of someday. Or to put it
>> another way, auxdata use is a sign of platforms not fully converted to
>> DT.
>
> All right. Thanks for letting me know your thoughts.
>
> Lorenzo,
>
> We've modeled Cadence PCIe core as a separate driver and for some of the
> functionalities (for example starting LTSSM or checking link status) it has to
> invoke the wrapper driver functions (The registers for these are present in
> wrapper and not in Cadence Core). In the case of Designware, we modeled DWC
> core as a library which provided APIs to be used by wrapper driver. Now that
> Rob is not inclined for passing platform data from one driver to another (in
> this case TI specific J721E driver to Cadence PCIe driver), should we model
> Cadence core also as a library? If you agree, I can prepare patches for making
> Cadence PCIe core as a library. Please let me know your thoughts.
Can you share your thoughts on this?
Thanks
Kishon
^ permalink raw reply
* [PATCH 1/3] macb: bindings doc: update sifive fu540-c000 binding
From: Yash Shah @ 2019-07-19 11:10 UTC (permalink / raw)
To: davem, robh+dt, paul.walmsley, netdev, devicetree, linux-kernel,
linux-riscv
Cc: mark.rutland, palmer, aou, nicolas.ferre, ynezz, sachin.ghadi,
Yash Shah
As per the discussion with Nicolas Ferre, rename the compatible property
to a more appropriate and specific string.
LINK: https://lkml.org/lkml/2019/7/17/200
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
Documentation/devicetree/bindings/net/macb.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/macb.txt b/Documentation/devicetree/bindings/net/macb.txt
index 63c73fa..0b61a90 100644
--- a/Documentation/devicetree/bindings/net/macb.txt
+++ b/Documentation/devicetree/bindings/net/macb.txt
@@ -15,10 +15,10 @@ Required properties:
Use "atmel,sama5d4-gem" for the GEM IP (10/100) available on Atmel sama5d4 SoCs.
Use "cdns,zynq-gem" Xilinx Zynq-7xxx SoC.
Use "cdns,zynqmp-gem" for Zynq Ultrascale+ MPSoC.
- Use "sifive,fu540-macb" for SiFive FU540-C000 SoC.
+ Use "sifive,fu540-c000-gem" for SiFive FU540-C000 SoC.
Or the generic form: "cdns,emac".
- reg: Address and length of the register set for the device
- For "sifive,fu540-macb", second range is required to specify the
+ For "sifive,fu540-c000-gem", second range is required to specify the
address and length of the registers for GEMGXL Management block.
- interrupts: Should contain macb interrupt
- phy-mode: See ethernet.txt file in the same directory.
--
1.9.1
^ permalink raw reply related
* [PATCH 2/3] macb: Update compatibility string for SiFive FU540-C000
From: Yash Shah @ 2019-07-19 11:10 UTC (permalink / raw)
To: davem, robh+dt, paul.walmsley, netdev, devicetree, linux-kernel,
linux-riscv
Cc: mark.rutland, palmer, aou, nicolas.ferre, ynezz, sachin.ghadi,
Yash Shah
In-Reply-To: <1563534631-15897-1-git-send-email-yash.shah@sifive.com>
Update the compatibility string for SiFive FU540-C000 as per the new
string updated in the binding doc.
Reference: https://lkml.org/lkml/2019/7/17/200
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
drivers/net/ethernet/cadence/macb_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c
index 15d0737..305371c 100644
--- a/drivers/net/ethernet/cadence/macb_main.c
+++ b/drivers/net/ethernet/cadence/macb_main.c
@@ -4112,7 +4112,7 @@ static int fu540_c000_init(struct platform_device *pdev)
{ .compatible = "cdns,emac", .data = &emac_config },
{ .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config},
{ .compatible = "cdns,zynq-gem", .data = &zynq_config },
- { .compatible = "sifive,fu540-macb", .data = &fu540_c000_config },
+ { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, macb_dt_ids);
--
1.9.1
^ permalink raw reply related
* [PATCH 3/3] riscv: dts: Add DT node for SiFive FU540 Ethernet controller driver
From: Yash Shah @ 2019-07-19 11:10 UTC (permalink / raw)
To: davem, robh+dt, paul.walmsley, netdev, devicetree, linux-kernel,
linux-riscv
Cc: mark.rutland, palmer, aou, nicolas.ferre, ynezz, sachin.ghadi,
Yash Shah
In-Reply-To: <1563534631-15897-1-git-send-email-yash.shah@sifive.com>
DT node for SiFive FU540-C000 GEMGXL Ethernet controller driver added
Signed-off-by: Yash Shah <yash.shah@sifive.com>
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 15 +++++++++++++++
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 9 +++++++++
2 files changed, 24 insertions(+)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index cc73522..588669f0 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -231,5 +231,20 @@
#size-cells = <0>;
status = "disabled";
};
+ eth0: ethernet@10090000 {
+ compatible = "sifive,fu540-c000-gem";
+ interrupt-parent = <&plic0>;
+ interrupts = <53>;
+ reg = <0x0 0x10090000 0x0 0x2000
+ 0x0 0x100a0000 0x0 0x1000>;
+ local-mac-address = [00 00 00 00 00 00];
+ clock-names = "pclk", "hclk";
+ clocks = <&prci PRCI_CLK_GEMGXLPLL>,
+ <&prci PRCI_CLK_GEMGXLPLL>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
};
};
diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
index 0b55c53..85c17a7 100644
--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
@@ -76,3 +76,12 @@
disable-wp;
};
};
+
+ð0 {
+ status = "okay";
+ phy-mode = "gmii";
+ phy-handle = <&phy1>;
+ phy1: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
--
1.9.1
^ permalink raw reply related
* Re: [PATCH v4 1/2] arm64: dts: fsl: pico-pi: Add a device tree for the PICO-PI-IMX8M
From: Fabio Estevam @ 2019-07-19 11:19 UTC (permalink / raw)
To: andradanciu1997
Cc: Shawn Guo, Rob Herring, Mark Rutland, Sascha Hauer, Sascha Hauer,
NXP Linux Team, Andrey Smirnov, Manivannan Sadhasivam, Ping Bai,
Michal Vokáč, Li Yang, sriram.dash, Lucas Stach,
Vabhav Sharma, Bhaskar Upadhaya, Pramod Kumar, pankaj.bansal,
Dong Aisheng, Angus Ainslie (Purism), Richard Hu
In-Reply-To: <20190719104802.18070-2-andradanciu1997@gmail.com>
Hi Andra,
On Fri, Jul 19, 2019 at 7:48 AM andradanciu1997
<andradanciu1997@gmail.com> wrote:
> + pmic: pmic@4b {
> + reg = <0x4b>;
> + compatible = "rohm,bd71837";
> + /* PMIC BD71837 PMIC_nINT GPIO1_IO12 */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pmic>;
> + clocks = <&pmic_osc>;
> + clock-names = "osc";
> + clock-output-names = "pmic_clk";
> + interrupt-parent = <&gpio1>;
> + interrupts = <3 GPIO_ACTIVE_LOW>;
> + interrupt-names = "irq";
> +
> + regulators {
> + #address-cells = <1>;
> + #size-cells = <0>;
#address-cells and #size-cells are not needed and they cause warnings with W=1:
DTC arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dtb
arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts:77.14-196.5: Warning
(avoid_unnecessary_addr_size):
/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators: unnecessary
#address-cells/#size-cells without "ranges" or child "reg" property
Please remove them.
^ permalink raw reply
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