* [RFC PATCH v2 2/4] dt-bindings: qcom: Document bindings for new MSM8916 devices
From: Stephan Gerhold @ 2019-07-22 9:22 UTC (permalink / raw)
To: Andy Gross
Cc: Rob Herring, Mark Rutland, linux-arm-msm, devicetree,
linux-kernel, Stephan Gerhold
In-Reply-To: <20190722092211.100586-1-stephan@gerhold.net>
Document the new samsung,a3u/a5u-eur and longcheer,l8150
device tree bindings used in their device trees.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
---
Documentation/devicetree/bindings/arm/qcom.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 54ef6b6b9189..e39d8f02e33c 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -45,6 +45,7 @@ description: |
mtp
sbc
hk01
+ qrd
The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
where the minor number may be omitted when it's zero, i.e. v1.0 is the same
@@ -115,6 +116,13 @@ properties:
- const: qcom,msm8916-mtp
- const: qcom,msm8916
+ - items:
+ - enum:
+ - longcheer,l8150
+ - samsung,a3u-eur
+ - samsung,a5u-eur
+ - const: qcom,msm8916
+
- items:
- const: qcom,msm8996-mtp
--
2.22.0
^ permalink raw reply related
* [RFC PATCH v2 1/4] dt-bindings: vendor-prefixes: Add Longcheer Technology Co., Ltd.
From: Stephan Gerhold @ 2019-07-22 9:22 UTC (permalink / raw)
To: Andy Gross
Cc: Rob Herring, Mark Rutland, linux-arm-msm, devicetree,
linux-kernel, Stephan Gerhold
In-Reply-To: <20190722092211.100586-1-stephan@gerhold.net>
Add the "longcheer" vendor prefix for Longcheer Technology Co., Ltd.,
an "industry-leading service provider of mobile phone design
and product delivery". (http://www.longcheer.com)
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 6992bbbbffab..7bcf340b6f38 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -529,6 +529,8 @@ patternProperties:
description: Linear Technology Corporation
"^logicpd,.*":
description: Logic PD, Inc.
+ "^longcheer,.*":
+ description: Longcheer Technology (Shanghai) Co., Ltd.
"^lsi,.*":
description: LSI Corp. (LSI Logic)
"^lwn,.*":
--
2.22.0
^ permalink raw reply related
* [RFC PATCH v2 0/4] Add initial device tree for MSM8916 A3U/A5U/L8150
From: Stephan Gerhold @ 2019-07-22 9:22 UTC (permalink / raw)
To: Andy Gross
Cc: Rob Herring, Mark Rutland, linux-arm-msm, devicetree,
linux-kernel, Stephan Gerhold
This patch series adds initial device trees for the Samsung Galaxy A3/A5 (2015)
and the Wileyfox Swift (a re-branded Longcheer L8150), three smartphones
based on the MSM8916 SoC. The device trees provde basic support for SDHCI,
USB device mode and regulators.
The idea is to leverage the efforts that went into mainline for
the Dragonboard 410c. So far this is going quite well:
In addition to the functionality provided by the initial device trees,
Display/GPU, touchscreen, sound and sensors also seem to work in initial tests.
Those will be added in future patch sets.
Changes in v2:
- Add initial device tree for Longcheer L8150
- Document new device tree bindings
v1: https://lore.kernel.org/linux-arm-msm/20190624173341.5826-1-stephan@gerhold.net/
Stephan Gerhold (4):
dt-bindings: vendor-prefixes: Add Longcheer Technology Co., Ltd.
dt-bindings: qcom: Document bindings for new MSM8916 devices
arm64: dts: qcom: Add device tree for Samsung Galaxy A3U/A5U
arm64: dts: qcom: Add device tree for Longcheer L8150
.../devicetree/bindings/arm/qcom.yaml | 8 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
arch/arm64/boot/dts/qcom/Makefile | 3 +
.../boot/dts/qcom/msm8916-longcheer-l8150.dts | 228 +++++++++++++++++
.../qcom/msm8916-samsung-a2015-common.dtsi | 236 ++++++++++++++++++
.../boot/dts/qcom/msm8916-samsung-a3u-eur.dts | 10 +
.../boot/dts/qcom/msm8916-samsung-a5u-eur.dts | 10 +
7 files changed, 497 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts
create mode 100644 arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
create mode 100644 arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts
create mode 100644 arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts
--
2.22.0
^ permalink raw reply
* Re: [PATCH] ARM: bcm47094: add missing #cells for mdio-bus-mux
From: Arnd Bergmann @ 2019-07-22 9:13 UTC (permalink / raw)
To: Florian Fainelli
Cc: bcm-kernel-feedback-list, Hauke Mehrtens, Rafał Miłecki,
Rob Herring, Mark Rutland, Vivek Unune, Alexandre TORGUE,
Neil Armstrong, Linux ARM, DTML, Linux Kernel Mailing List
In-Reply-To: <20190709161630.7963-1-f.fainelli@gmail.com>
On Tue, Jul 9, 2019 at 6:16 PM Florian Fainelli <f.fainelli@gmail.com> wrote:
>
> On Wed, 3 Jul 2019 15:22:45 +0200, Arnd Bergmann <arnd@arndb.de> wrote:
> > The mdio-bus-mux has no #address-cells/#size-cells property,
> > which causes a few dtc warnings:
> >
> > arch/arm/boot/dts/bcm47094-linksys-panamera.dts:129.4-18: Warning (reg_format): /mdio-bus-mux/mdio@200:reg: property has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> > arch/arm/boot/dts/bcm47094-linksys-panamera.dtb: Warning (pci_device_bus_num): Failed prerequisite 'reg_format'
> > arch/arm/boot/dts/bcm47094-linksys-panamera.dtb: Warning (i2c_bus_reg): Failed prerequisite 'reg_format'
> > arch/arm/boot/dts/bcm47094-linksys-panamera.dtb: Warning (spi_bus_reg): Failed prerequisite 'reg_format'
> > arch/arm/boot/dts/bcm47094-linksys-panamera.dts:128.22-132.5: Warning (avoid_default_addr_size): /mdio-bus-mux/mdio@200: Relying on default #address-cells value
> > arch/arm/boot/dts/bcm47094-linksys-panamera.dts:128.22-132.5: Warning (avoid_default_addr_size): /mdio-bus-mux/mdio@200: Relying on default #size-cells value
> >
> > Add the normal cell numbers.
> >
> > Fixes: 2bebdfcdcd0f ("ARM: dts: BCM5301X: Add support for Linksys EA9500")
> > Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> > ---
>
> Applied to devicetree/fixes, thanks!
I just noticed this never made it into linux-next or the merge window.
Did it get dropped by accident?
Arnd
^ permalink raw reply
* RE: [PATCH v2 6/8] PCI: al: Add support for DW based driver type
From: Gustavo Pimentel @ 2019-07-22 8:54 UTC (permalink / raw)
To: Chocron, Jonathan, jingoohan1@gmail.com, mark.rutland@arm.com,
lorenzo.pieralisi@arm.com, Gustavo.Pimentel@synopsys.com,
bhelgaas@google.com, robh+dt@kernel.org
Cc: linux-kernel@vger.kernel.org, Woodhouse, David, Hanoch, Uri,
devicetree@vger.kernel.org, Wasserstrom, Barak, Saidi, Ali,
Hawa, Hanna, Shenhar, Talel, Krupnik, Ronen,
linux-pci@vger.kernel.org, benh@kernel.crashing.org
In-Reply-To: <d323007c6bf14cb9f90a497a26b66dac151164fc.camel@amazon.com>
On Sun, Jul 21, 2019 at 16:8:18, Chocron, Jonathan <jonnyc@amazon.com>
wrote:
> On Fri, 2019-07-19 at 08:55 +0000, Gustavo Pimentel wrote:
> > On Thu, Jul 18, 2019 at 10:47:16, Jonathan Chocron <jonnyc@amazon.com
> > >
> > wrote:
> >
> > > This driver is DT based and utilizes the DesignWare APIs.
> > > It allows using a smaller ECAM range for a larger bus range -
> > > usually an entire bus uses 1MB of address space, but the driver
> > > can use it for a larger number of buses.
> > >
> > > All link initializations are handled by the boot FW.
> > >
> > > Signed-off-by: Jonathan Chocron <jonnyc@amazon.com>
> > > ---
> > > drivers/pci/controller/dwc/Kconfig | 12 +
> > > drivers/pci/controller/dwc/pcie-al.c | 373
> > > +++++++++++++++++++++++++++
> > > 2 files changed, 385 insertions(+)
> > >
> > > diff --git a/drivers/pci/controller/dwc/Kconfig
> > > b/drivers/pci/controller/dwc/Kconfig
> > > index 6ea778ae4877..3c6094cbcc3b 100644
> > > --- a/drivers/pci/controller/dwc/Kconfig
> > > +++ b/drivers/pci/controller/dwc/Kconfig
> > > @@ -230,4 +230,16 @@ config PCIE_UNIPHIER
> > > Say Y here if you want PCIe controller support on UniPhier
> > > SoCs.
> > > This driver supports LD20 and PXs3 SoCs.
> > >
> > > +config PCIE_AL
> > > + bool "Amazon Annapurna Labs PCIe controller"
> > > + depends on OF && (ARM64 || COMPILE_TEST)
> > > + depends on PCI_MSI_IRQ_DOMAIN
> > > + select PCIE_DW_HOST
> > > + help
> > > + Say Y here to enable support of the Amazon's Annapurna Labs
> > > PCIe
> > > + controller IP on Amazon SoCs. The PCIe controller uses the
> > > DesignWare
> > > + core plus Annapurna Labs proprietary hardware wrappers. This
> > > is
> > > + required only for DT-based platforms. ACPI platforms with the
> > > + Annapurna Labs PCIe controller don't need to enable this.
> > > +
> > > endmenu
> > > diff --git a/drivers/pci/controller/dwc/pcie-al.c
> > > b/drivers/pci/controller/dwc/pcie-al.c
> > > index 3ab58f0584a8..40555532fb9a 100644
> > > --- a/drivers/pci/controller/dwc/pcie-al.c
> > > +++ b/drivers/pci/controller/dwc/pcie-al.c
> > > @@ -91,3 +91,376 @@ struct pci_ecam_ops al_pcie_ops = {
> > > };
> > >
> > > #endif /* defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS) */
> > > +
> > > +#ifdef CONFIG_PCIE_AL
> > > +
> > > +#include <linux/of_pci.h>
> > > +#include "pcie-designware.h"
> > > +
> > > +#define AL_PCIE_REV_ID_2 2
> > > +#define AL_PCIE_REV_ID_3 3
> > > +#define AL_PCIE_REV_ID_4 4
> > > +
> > > +#define AXI_BASE_OFFSET 0x0
> > > +
> > > +#define DEVICE_ID_OFFSET 0x16c
> > > +
> > > +#define DEVICE_REV_ID 0x0
> > > +#define DEVICE_REV_ID_DEV_ID_MASK GENMASK(31, 16)
> > > +
> > > +#define DEVICE_REV_ID_DEV_ID_X4 0
> > > +#define DEVICE_REV_ID_DEV_ID_X8 2
> > > +#define DEVICE_REV_ID_DEV_ID_X16 4
> > > +
> > > +#define OB_CTRL_REV1_2_OFFSET 0x0040
> > > +#define OB_CTRL_REV3_5_OFFSET 0x0030
> > > +
> > > +#define CFG_TARGET_BUS 0x0
> > > +#define CFG_TARGET_BUS_MASK_MASK GENMASK(7, 0)
> > > +#define CFG_TARGET_BUS_BUSNUM_MASK GENMASK(15, 8)
> > > +
> > > +#define CFG_CONTROL 0x4
> > > +#define CFG_CONTROL_SUBBUS_MASK GENMASK(15, 8)
> > > +#define CFG_CONTROL_SEC_BUS_MASK GENMASK(23, 16)
> > > +
> > > +struct al_pcie_reg_offsets {
> > > + unsigned int ob_ctrl;
> > > +};
> > > +
> > > +struct al_pcie_target_bus_cfg {
> > > + u8 reg_val;
> > > + u8 reg_mask;
> > > + u8 ecam_mask;
> > > +};
> > > +
> > > +struct al_pcie {
> > > + struct dw_pcie *pci;
> > > + void __iomem *controller_base; /* base of PCIe unit (not DW
> > > core) */
> > > + struct device *dev;
> > > + resource_size_t ecam_size;
> > > + unsigned int controller_rev_id;
> > > + struct al_pcie_reg_offsets reg_offsets;
> > > + struct al_pcie_target_bus_cfg target_bus_cfg;
> > > +};
> > > +
> > > +#define PCIE_ECAM_DEVFN(x) (((x) & 0xff) << 12)
> > > +
> > > +#define to_al_pcie(x) dev_get_drvdata((x)->dev)
> > > +
> > > +static int al_pcie_rev_id_get(struct al_pcie *pcie, unsigned int
> > > *rev_id)
> > > +{
> > > + void __iomem *dev_rev_id_addr;
> > > + u32 dev_rev_id;
> > > +
> > > + dev_rev_id_addr = (void __iomem *)((uintptr_t)pcie-
> > > >controller_base +
> > > + AXI_BASE_OFFSET + DEVICE_ID_OFFSET +
> > > DEVICE_REV_ID);
> > > +
> > > + dev_rev_id = FIELD_GET(DEVICE_REV_ID_DEV_ID_MASK,
> > > + readl(dev_rev_id_addr));
> > > + switch (dev_rev_id) {
> > > + case DEVICE_REV_ID_DEV_ID_X4:
> > > + *rev_id = AL_PCIE_REV_ID_2;
> > > + break;
> > > + case DEVICE_REV_ID_DEV_ID_X8:
> > > + *rev_id = AL_PCIE_REV_ID_3;
> > > + break;
> > > + case DEVICE_REV_ID_DEV_ID_X16:
> > > + *rev_id = AL_PCIE_REV_ID_4;
> > > + break;
> > > + default:
> > > + dev_err(pcie->dev, "Unsupported dev_rev_id (0x%x)\n",
> > > + dev_rev_id);
> > > + return -EINVAL;
> > > + }
> > > +
> > > + dev_dbg(pcie->dev, "dev_rev_id: 0x%x\n", dev_rev_id);
> >
> > Consider s/dev_dbg/pci_dbg/g
> >
> There is no struct pci_dev context (the dev belongs to the
> platform_device).
It seems so. It sucks...
Disregard this then.
>
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int al_pcie_reg_offsets_set(struct al_pcie *pcie)
> > > +{
> > > + switch (pcie->controller_rev_id) {
> > > + case AL_PCIE_REV_ID_2:
> > > + pcie->reg_offsets.ob_ctrl = OB_CTRL_REV1_2_OFFSET;
> > > + break;
> > > + case AL_PCIE_REV_ID_3:
> > > + case AL_PCIE_REV_ID_4:
> > > + pcie->reg_offsets.ob_ctrl = OB_CTRL_REV3_5_OFFSET;
> > > + break;
> > > + default:
> > > + dev_err(pcie->dev, "Unsupported controller rev_id:
> > > 0x%x\n",
> > > + pcie->controller_rev_id);
> >
> > Consider s/dev_err/pci_err/g
> >
> Same as above.
>
> > > + return -EINVAL;
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static inline void al_pcie_target_bus_set(struct al_pcie *pcie,
> > > + u8 target_bus,
> > > + u8 mask_target_bus)
> > > +{
> > > + void __iomem *cfg_control_addr;
> > > + u32 reg;
> > > +
> > > + reg = FIELD_PREP(CFG_TARGET_BUS_MASK_MASK, mask_target_bus) |
> > > + FIELD_PREP(CFG_TARGET_BUS_BUSNUM_MASK, target_bus);
> > > +
> > > + cfg_control_addr = (void __iomem *)((uintptr_t)pcie-
> > > >controller_base +
> > > + AXI_BASE_OFFSET + pcie->reg_offsets.ob_ctrl
> > > +
> > > + CFG_TARGET_BUS);
> > > +
> > > + writel(reg, cfg_control_addr);
> >
> > From what I'm seeing you commonly use writel() and readl() with a
> > common
> > base address, such as pcie->controller_base + AXI_BASE_OFFSET.
> > I'd suggest to creating a writel and readl with that offset built-in.
> >
> I prefer to keep it generic, since in future revisions we might want to
> access regs which are not in the AXI region. You think I should add
> wrappers which simply hide the pcie->controller_base part?
I and other developers typically do that, but it's a suggestion. IMHO it
helps to keep the code cleaner and more readable.
>
> > > +}
> > > +
> > > +static void __iomem *al_pcie_conf_addr_map(struct al_pcie *pcie,
> > > + unsigned int busnr,
> > > + unsigned int devfn)
> > > +{
> > > + void __iomem *pci_base_addr;
> >
> > Consider passing this variable declaration to the bottom, following
> > the
> > reverse tree order.
> >
> Done. Moved 'struct pcie_port *pp' as well.
>
> > > + struct pcie_port *pp = &pcie->pci->pp;
> > > + struct al_pcie_target_bus_cfg *target_bus_cfg = &pcie-
> > > >target_bus_cfg;
> > > + unsigned int busnr_ecam = busnr & target_bus_cfg->ecam_mask;
> > > + unsigned int busnr_reg = busnr & target_bus_cfg->reg_mask;
> > > +
> > > + pci_base_addr = (void __iomem *)((uintptr_t)pp->va_cfg0_base +
> > > + (busnr_ecam << 20) +
> > > + PCIE_ECAM_DEVFN(devfn));
> > > +
> > > + if (busnr_reg != target_bus_cfg->reg_val) {
> > > + dev_dbg(pcie->pci->dev, "Changing target bus busnum val
> > > from 0x%x to 0x%x\n",
> > > + target_bus_cfg->reg_val, busnr_reg);
> > > + target_bus_cfg->reg_val = busnr_reg;
> > > + al_pcie_target_bus_set(pcie,
> > > + target_bus_cfg->reg_val,
> > > + target_bus_cfg->reg_mask);
> > > + }
> > > +
> > > + return pci_base_addr;
> > > +}
> > > +
> > > +static int al_pcie_rd_other_conf(struct pcie_port *pp, struct
> > > pci_bus *bus,
> > > + unsigned int devfn, int where, int
> > > size,
> > > + u32 *val)
> > > +{
> > > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > + struct al_pcie *pcie = to_al_pcie(pci);
> > > + unsigned int busnr = bus->number;
> > > + void __iomem *pci_addr;
> > > + int rc;
> > > +
> > > + pci_addr = al_pcie_conf_addr_map(pcie, busnr, devfn);
> > > +
> > > + rc = dw_pcie_read(pci_addr + where, size, val);
> > > +
> > > + dev_dbg(pci->dev, "%d-byte config read from %04x:%02x:%02x.%d
> > > offset 0x%x (pci_addr: 0x%px) - val:0x%x\n",
> > > + size, pci_domain_nr(bus), bus->number,
> > > + PCI_SLOT(devfn), PCI_FUNC(devfn), where,
> > > + (pci_addr + where), *val);
> > > +
> > > + return rc;
> > > +}
> > > +
> > > +static int al_pcie_wr_other_conf(struct pcie_port *pp, struct
> > > pci_bus *bus,
> > > + unsigned int devfn, int where, int
> > > size,
> > > + u32 val)
> > > +{
> > > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > + struct al_pcie *pcie = to_al_pcie(pci);
> > > + unsigned int busnr = bus->number;
> > > + void __iomem *pci_addr;
> > > + int rc;
> > > +
> > > + pci_addr = al_pcie_conf_addr_map(pcie, busnr, devfn);
> > > +
> > > + rc = dw_pcie_write(pci_addr + where, size, val);
> > > +
> > > + dev_err(pci->dev, "%d-byte config write to %04x:%02x:%02x.%d
> > > offset 0x%x (pci_addr: 0x%px) - val:0x%x\n",
> > > + size, pci_domain_nr(bus), bus->number,
> > > + PCI_SLOT(devfn), PCI_FUNC(devfn), where,
> > > + (pci_addr + where), val);
> > > +
> > > + return rc;
> > > +}
> > > +
> > > +static int al_pcie_config_prepare(struct al_pcie *pcie)
> > > +{
> > > + struct al_pcie_target_bus_cfg *target_bus_cfg;
> > > + struct pcie_port *pp = &pcie->pci->pp;
> > > + unsigned int ecam_bus_mask;
> > > + u8 secondary_bus;
> > > + u8 subordinate_bus;
> > > + void __iomem *cfg_control_addr;
> > > + u32 cfg_control;
> > > + u32 reg;
> > > +
> > > + target_bus_cfg = &pcie->target_bus_cfg;
> > > +
> > > + ecam_bus_mask = (pcie->ecam_size >> 20) - 1;
> > > + if (ecam_bus_mask > 255) {
> > > + dev_warn(pcie->dev, "ECAM window size is larger than
> > > 256MB. Cutting off at 256\n");
> > > + ecam_bus_mask = 255;
> > > + }
> > > +
> > > + /* This portion is taken from the transaction address */
> > > + target_bus_cfg->ecam_mask = ecam_bus_mask;
> > > + /* This portion is taken from the cfg_target_bus reg */
> > > + target_bus_cfg->reg_mask = ~target_bus_cfg->ecam_mask;
> > > + target_bus_cfg->reg_val = pp->busn->start & target_bus_cfg-
> > > >reg_mask;
> > > +
> > > + al_pcie_target_bus_set(pcie, target_bus_cfg->reg_val,
> > > + target_bus_cfg->reg_mask);
> > > +
> > > + secondary_bus = pp->busn->start + 1;
> > > + subordinate_bus = pp->busn->end;
> > > +
> > > + /* Set the valid values of secondary and subordinate buses */
> > > + cfg_control_addr = pcie->controller_base + AXI_BASE_OFFSET +
> > > + pcie->reg_offsets.ob_ctrl + CFG_CONTROL;
> > > +
> > > + cfg_control = readl(cfg_control_addr);
> > > +
> > > + reg = cfg_control &
> > > + ~(CFG_CONTROL_SEC_BUS_MASK | CFG_CONTROL_SUBBUS_MASK);
> > > +
> > > + reg |= FIELD_PREP(CFG_CONTROL_SUBBUS_MASK, subordinate_bus) |
> > > + FIELD_PREP(CFG_CONTROL_SEC_BUS_MASK, secondary_bus);
> > > +
> > > + writel(reg, cfg_control_addr);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static int al_pcie_host_init(struct pcie_port *pp)
> > > +{
> > > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> > > + struct al_pcie *pcie = to_al_pcie(pci);
> > > + int link_up;
> > > + int rc;
> > > +
> > > + link_up = dw_pcie_link_up(pci);
> > > + if (!link_up) {
> > > + dev_err(pci->dev, "link is not up!\n");
> > > + return -ENOLINK;
> > > + }
> > > +
> > > + dev_info(pci->dev, "link is up\n");
> >
> > Consider s/dev_info/pci_info/g
> >
> Same as the response above.
>
> > > +
> > > + rc = al_pcie_rev_id_get(pcie, &pcie->controller_rev_id);
> > > + if (rc)
> > > + return rc;
> > > +
> > > + rc = al_pcie_reg_offsets_set(pcie);
> > > + if (rc)
> > > + return rc;
> > > +
> > > + rc = al_pcie_config_prepare(pcie);
> > > + if (rc)
> > > + return rc;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static const struct dw_pcie_host_ops al_pcie_host_ops = {
> > > + .rd_other_conf = al_pcie_rd_other_conf,
> > > + .wr_other_conf = al_pcie_wr_other_conf,
> > > + .host_init = al_pcie_host_init,
> > > +};
> > > +
> > > +static int al_add_pcie_port(struct pcie_port *pp,
> > > + struct platform_device *pdev)
> > > +{
> > > + struct device *dev = &pdev->dev;
> > > + int ret;
> > > +
> > > + pp->ops = &al_pcie_host_ops;
> > > +
> > > + ret = dw_pcie_host_init(pp);
> > > + if (ret) {
> > > + dev_err(dev, "failed to initialize host\n");
> > > + return ret;
> > > + }
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static const struct dw_pcie_ops dw_pcie_ops = {
> > > +};
> > > +
> > > +static int al_pcie_probe(struct platform_device *pdev)
> > > +{
> > > + struct device *dev = &pdev->dev;
> > > + struct al_pcie *al_pcie;
> > > + struct dw_pcie *pci;
> > > + struct resource *dbi_res;
> > > + struct resource *controller_res;
> > > + struct resource *ecam_res;
> > > + int ret;
> >
> > Please sort the variables following the reverse tree order.
> >
> Done.
>
> I'd think that it would make sense to group variables which have a
> common characteristic (e.g. resources read from the DT), even if it
> mildly breaks the convention (as long as the general frame is longest
> to shortest). Does this sound ok?
>
> BTW, I couldn't find any documentation regarding the reverse-tree
> convention, do you have a pointer to some?
There isn't as far as I know, but it's a convention normally used in
several subsystems.
I suppose it's a way to try to keep some organization along with the code
style. IMHO it doesn't harm, but it's just a suggestion. 😊
>
> > > +
> > > + al_pcie = devm_kzalloc(dev, sizeof(*al_pcie), GFP_KERNEL);
> > > + if (!al_pcie)
> > > + return -ENOMEM;
> > > +
> > > + pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
> > > + if (!pci)
> > > + return -ENOMEM;
> > > +
> > > + pci->dev = dev;
> > > + pci->ops = &dw_pcie_ops;
> > > +
> > > + al_pcie->pci = pci;
> > > + al_pcie->dev = dev;
> > > +
> > > + dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > > "dbi");
> > > + pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_res);
> > > + if (IS_ERR(pci->dbi_base)) {
> > > + dev_err(dev, "couldn't remap dbi base %pR\n", dbi_res);
> > > + return PTR_ERR(pci->dbi_base);
> > > + }
> > > +
> > > + ecam_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > > "config");
> > > + if (!ecam_res) {
> > > + dev_err(dev, "couldn't find 'config' reg in DT\n");
> > > + return -ENOENT;
> > > + }
> > > + al_pcie->ecam_size = resource_size(ecam_res);
> > > +
> > > + controller_res = platform_get_resource_byname(pdev,
> > > IORESOURCE_MEM,
> > > + "controller");
> > > + al_pcie->controller_base = devm_ioremap_resource(dev,
> > > controller_res);
> > > + if (IS_ERR(al_pcie->controller_base)) {
> > > + dev_err(dev, "couldn't remap controller base %pR\n",
> > > + controller_res);
> > > + return PTR_ERR(al_pcie->controller_base);
> > > + }
> > > +
> > > + dev_dbg(dev, "From DT: dbi_base: %pR, controller_base: %pR\n",
> > > + dbi_res, controller_res);
> > > +
> > > + platform_set_drvdata(pdev, al_pcie);
> > > +
> > > + ret = al_add_pcie_port(&pci->pp, pdev);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + return 0;
> >
> > Those operations are redundant, aren't they? They can be replaced
> > just
> > by:
> >
> > return ret;
> >
>
> Ack.
Thanks.
>
> > > +}
> > > +
> > > +static const struct of_device_id al_pcie_of_match[] = {
> > > + { .compatible = "amazon,al-pcie",
> > > + },
> > > + {},
> > > +};
> > > +
> > > +static struct platform_driver al_pcie_driver = {
> > > + .driver = {
> > > + .name = "al-pcie",
> > > + .of_match_table = al_pcie_of_match,
> > > + .suppress_bind_attrs = true,
> > > + },
> > > + .probe = al_pcie_probe,
> > > +};
> > > +builtin_platform_driver(al_pcie_driver);
> > > +
> > > +#endif /* CONFIG_PCIE_AL*/
> > > --
> > > 2.17.1
> >
> >
^ permalink raw reply
* [PATCH arm64/dts 2/2] arm64: dts: imx8qxp: add serial alias
From: fugang.duan @ 2019-07-22 8:28 UTC (permalink / raw)
To: festevam, shawnguo
Cc: devicetree, daniel.baluta, fugang.duan, linux-arm-kernel
In-Reply-To: <20190722082824.15022-1-fugang.duan@nxp.com>
From: Fugang Duan <fugang.duan@nxp.com>
Add i.MX8QXP serial alias for lpuart ports.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 21bdd4d..4402b2e 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -30,6 +30,9 @@
mmc2 = &usdhc3;
mu1 = &lsio_mu1;
serial0 = &adma_lpuart0;
+ serial1 = &adma_lpuart1;
+ serial2 = &adma_lpuart2;
+ serial3 = &adma_lpuart3;
};
cpus {
--
2.7.4
^ permalink raw reply related
* [PATCH arm64/dts 1/2] arm64: dts: imx8qxp: add lpuart baud clock
From: fugang.duan @ 2019-07-22 8:28 UTC (permalink / raw)
To: festevam, shawnguo
Cc: devicetree, daniel.baluta, fugang.duan, linux-arm-kernel
In-Reply-To: <20190722082824.15022-1-fugang.duan@nxp.com>
From: Fugang Duan <fugang.duan@nxp.com>
Add imx8qxp lpuart baud clock.
V2:
- separate v1 patch to two patches, one is to add baud clock,
the other is to add serial alias property.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 20 ++++++++++++--------
1 file changed, 12 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 05fa0b7..21bdd4d 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -209,8 +209,9 @@
reg = <0x5a060000 0x1000>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
- clock-names = "ipg";
+ clocks = <&adma_lpcg IMX_ADMA_LPCG_UART0_IPG_CLK>,
+ <&adma_lpcg IMX_ADMA_LPCG_UART0_BAUD_CLK>;
+ clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_0>;
status = "disabled";
};
@@ -220,8 +221,9 @@
reg = <0x5a070000 0x1000>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
- clock-names = "ipg";
+ clocks = <&adma_lpcg IMX_ADMA_LPCG_UART1_IPG_CLK>,
+ <&adma_lpcg IMX_ADMA_LPCG_UART1_BAUD_CLK>;
+ clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_1>;
status = "disabled";
};
@@ -231,8 +233,9 @@
reg = <0x5a080000 0x1000>;
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
- clock-names = "ipg";
+ clocks = <&adma_lpcg IMX_ADMA_LPCG_UART2_IPG_CLK>,
+ <&adma_lpcg IMX_ADMA_LPCG_UART2_BAUD_CLK>;
+ clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_2>;
status = "disabled";
};
@@ -242,8 +245,9 @@
reg = <0x5a090000 0x1000>;
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
- clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
- clock-names = "ipg";
+ clocks = <&adma_lpcg IMX_ADMA_LPCG_UART3_IPG_CLK>,
+ <&adma_lpcg IMX_ADMA_LPCG_UART3_BAUD_CLK>;
+ clock-names = "ipg", "baud";
power-domains = <&pd IMX_SC_R_UART_3>;
status = "disabled";
};
--
2.7.4
^ permalink raw reply related
* [PATCH arm64/dts 0/2] arm64: dts: imx8qxp: add lpuart ports
From: fugang.duan @ 2019-07-22 8:28 UTC (permalink / raw)
To: festevam, shawnguo
Cc: devicetree, daniel.baluta, fugang.duan, linux-arm-kernel
From: Fugang Duan <fugang.duan@nxp.com>
Add lpuart baud clock and add serial alias for imx8qxp lpuart ports,
to let lpuart work on imx8qxp platform.
V2:
- separate v1 patch to two patches, one is to add baud clock,
the other is to add serial alias property.
Fugang Duan (2):
arm64: dts: imx8qxp: add lpuart baud clock
arm64: dts: imx8qxp: add serial alias
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 23 +++++++++++++++--------
1 file changed, 15 insertions(+), 8 deletions(-)
--
2.7.4
^ permalink raw reply
* Re: [PATCH 3/3] riscv: dts: Add DT node for SiFive FU540 Ethernet controller driver
From: Sagar Kadam @ 2019-07-22 8:27 UTC (permalink / raw)
To: Andrew Lunn
Cc: Mark Rutland, devicetree, Albert Ou, netdev, Palmer Dabbelt,
ynezz, Linux Kernel Mailing List, nicolas.ferre, Sachin Ghadi,
Yash Shah, Rob Herring, Paul Walmsley, linux-riscv, davem
In-Reply-To: <20190719132657.GD24930@lunn.ch>
Hello Andrew,
On Fri, Jul 19, 2019 at 6:57 PM Andrew Lunn <andrew@lunn.ch> wrote:
>
> On Fri, Jul 19, 2019 at 05:23:45PM +0530, Sagar Kadam wrote:
> > > +ð0 {
> > > + status = "okay";
> > > + phy-mode = "gmii";
> > > + phy-handle = <&phy1>;
> > > + phy1: ethernet-phy@0 {
> > > + reg = <0>;
> > > + };
>
> Hi Sagar
>
> Is there a good reason to call it phy1? Is there a phy0?
>
Sorry for the delayed response.
There is a single phy, so yes phy0 is a better name.
Thank you for pointing this out.
Thanks & Regards,
Sagar Kadam
> Thanks
>
> Andrew
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply
* [PATCH v2 4/4] media: Add support for Cadence CSI2TX 2.1
From: Jan Kotas @ 2019-07-22 8:22 UTC (permalink / raw)
To: maxime.ripard, mchehab, robh+dt, mark.rutland
Cc: rafalc, linux-media, devicetree, linux-kernel, Jan Kotas
In-Reply-To: <20190722082223.18693-1-jank@cadence.com>
This patch adds support for CSI2TX v2.1 version of the controller.
Signed-off-by: Jan Kotas <jank@cadence.com>
---
drivers/media/platform/cadence/cdns-csi2tx.c | 140 +++++++++++++++++++++------
1 file changed, 111 insertions(+), 29 deletions(-)
diff --git a/drivers/media/platform/cadence/cdns-csi2tx.c b/drivers/media/platform/cadence/cdns-csi2tx.c
index c72c8a065..e4d08acfb 100644
--- a/drivers/media/platform/cadence/cdns-csi2tx.c
+++ b/drivers/media/platform/cadence/cdns-csi2tx.c
@@ -52,6 +52,17 @@
#define CSI2TX_STREAM_IF_CFG_REG(n) (0x100 + (n) * 4)
#define CSI2TX_STREAM_IF_CFG_FILL_LEVEL(n) ((n) & 0x1f)
+/* CSI2TX V2 Registers */
+#define CSI2TX_V2_DPHY_CFG_REG 0x28
+#define CSI2TX_V2_DPHY_CFG_RESET BIT(16)
+#define CSI2TX_V2_DPHY_CFG_CLOCK_MODE BIT(10)
+#define CSI2TX_V2_DPHY_CFG_MODE_MASK GENMASK(9, 8)
+#define CSI2TX_V2_DPHY_CFG_MODE_LPDT (2 << 8)
+#define CSI2TX_V2_DPHY_CFG_MODE_HS (1 << 8)
+#define CSI2TX_V2_DPHY_CFG_MODE_ULPS (0 << 8)
+#define CSI2TX_V2_DPHY_CFG_CLK_ENABLE BIT(4)
+#define CSI2TX_V2_DPHY_CFG_LANE_ENABLE(n) BIT(n)
+
#define CSI2TX_LANES_MAX 4
#define CSI2TX_STREAMS_MAX 4
@@ -70,6 +81,13 @@ struct csi2tx_fmt {
u32 bpp;
};
+struct csi2tx_priv;
+
+/* CSI2TX Variant Operations */
+struct csi2tx_vops {
+ void (*dphy_setup)(struct csi2tx_priv *csi2tx);
+};
+
struct csi2tx_priv {
struct device *dev;
unsigned int count;
@@ -82,6 +100,8 @@ struct csi2tx_priv {
void __iomem *base;
+ struct csi2tx_vops *vops;
+
struct clk *esc_clk;
struct clk *p_clk;
struct clk *pixel_clk[CSI2TX_STREAMS_MAX];
@@ -209,29 +229,44 @@ static const struct v4l2_subdev_pad_ops csi2tx_pad_ops = {
.set_fmt = csi2tx_set_pad_format,
};
-static void csi2tx_reset(struct csi2tx_priv *csi2tx)
+/* Set Wake Up value in the D-PHY */
+static void csi2tx_dphy_set_wakeup(struct csi2tx_priv *csi2tx)
{
- writel(CSI2TX_CONFIG_SRST_REQ, csi2tx->base + CSI2TX_CONFIG_REG);
-
- udelay(10);
+ writel(CSI2TX_DPHY_CLK_WAKEUP_ULPS_CYCLES(32),
+ csi2tx->base + CSI2TX_DPHY_CLK_WAKEUP_REG);
}
-static int csi2tx_start(struct csi2tx_priv *csi2tx)
+/*
+ * Finishes the D-PHY initialization
+ * reg dphy cfg value to be used
+ */
+static void csi2tx_dphy_init_finish(struct csi2tx_priv *csi2tx, u32 reg)
{
- struct media_entity *entity = &csi2tx->subdev.entity;
- struct media_link *link;
unsigned int i;
- u32 reg;
- csi2tx_reset(csi2tx);
+ udelay(10);
- writel(CSI2TX_CONFIG_CFG_REQ, csi2tx->base + CSI2TX_CONFIG_REG);
+ /* Enable our (clock and data) lanes */
+ reg |= CSI2TX_DPHY_CFG_CLK_ENABLE;
+ for (i = 0; i < csi2tx->num_lanes; i++)
+ reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i] - 1);
+ writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);
udelay(10);
- /* Configure our PPI interface with the D-PHY */
- writel(CSI2TX_DPHY_CLK_WAKEUP_ULPS_CYCLES(32),
- csi2tx->base + CSI2TX_DPHY_CLK_WAKEUP_REG);
+ /* Switch to HS mode */
+ reg &= ~CSI2TX_DPHY_CFG_MODE_MASK;
+ writel(reg | CSI2TX_DPHY_CFG_MODE_HS,
+ csi2tx->base + CSI2TX_DPHY_CFG_REG);
+}
+
+/* Configures D-PHY in CSIv1.3 */
+static void csi2tx_dphy_setup(struct csi2tx_priv *csi2tx)
+{
+ u32 reg;
+ unsigned int i;
+
+ csi2tx_dphy_set_wakeup(csi2tx);
/* Put our lanes (clock and data) out of reset */
reg = CSI2TX_DPHY_CFG_CLK_RESET | CSI2TX_DPHY_CFG_MODE_LPDT;
@@ -239,23 +274,47 @@ static int csi2tx_start(struct csi2tx_priv *csi2tx)
reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i] - 1);
writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);
- udelay(10);
+ csi2tx_dphy_init_finish(csi2tx, reg);
+}
- /* Enable our (clock and data) lanes */
- reg |= CSI2TX_DPHY_CFG_CLK_ENABLE;
- for (i = 0; i < csi2tx->num_lanes; i++)
- reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i] - 1);
- writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);
+/* Configures D-PHY in CSIv2 */
+static void csi2tx_v2_dphy_setup(struct csi2tx_priv *csi2tx)
+{
+ u32 reg;
+
+ csi2tx_dphy_set_wakeup(csi2tx);
+
+ /* Put our lanes (clock and data) out of reset */
+ reg = CSI2TX_V2_DPHY_CFG_RESET | CSI2TX_V2_DPHY_CFG_MODE_LPDT;
+ writel(reg, csi2tx->base + CSI2TX_V2_DPHY_CFG_REG);
+
+ csi2tx_dphy_init_finish(csi2tx, reg);
+}
+
+static void csi2tx_reset(struct csi2tx_priv *csi2tx)
+{
+ writel(CSI2TX_CONFIG_SRST_REQ, csi2tx->base + CSI2TX_CONFIG_REG);
udelay(10);
+}
- /* Switch to HS mode */
- reg &= ~CSI2TX_DPHY_CFG_MODE_MASK;
- writel(reg | CSI2TX_DPHY_CFG_MODE_HS,
- csi2tx->base + CSI2TX_DPHY_CFG_REG);
+static int csi2tx_start(struct csi2tx_priv *csi2tx)
+{
+ struct media_entity *entity = &csi2tx->subdev.entity;
+ struct media_link *link;
+ unsigned int i;
+
+ csi2tx_reset(csi2tx);
+
+ writel(CSI2TX_CONFIG_CFG_REQ, csi2tx->base + CSI2TX_CONFIG_REG);
udelay(10);
+ if (csi2tx->vops && csi2tx->vops->dphy_setup) {
+ csi2tx->vops->dphy_setup(csi2tx);
+ udelay(10);
+ }
+
/*
* Create a static mapping between the CSI virtual channels
* and the input streams.
@@ -478,9 +537,35 @@ static int csi2tx_check_lanes(struct csi2tx_priv *csi2tx)
return ret;
}
+static const struct csi2tx_vops csi2tx_vops = {
+ .dphy_setup = csi2tx_dphy_setup,
+};
+
+static const struct csi2tx_vops csi2tx_v2_vops = {
+ .dphy_setup = csi2tx_v2_dphy_setup,
+};
+
+static const struct of_device_id csi2tx_of_table[] = {
+ {
+ .compatible = "cdns,csi2tx",
+ .data = &csi2tx_vops
+ },
+ {
+ .compatible = "cdns,csi2tx-1.3",
+ .data = &csi2tx_vops
+ },
+ {
+ .compatible = "cdns,csi2tx-2.1",
+ .data = &csi2tx_v2_vops
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, csi2tx_of_table);
+
static int csi2tx_probe(struct platform_device *pdev)
{
struct csi2tx_priv *csi2tx;
+ const struct of_device_id *of_id;
unsigned int i;
int ret;
@@ -495,6 +580,9 @@ static int csi2tx_probe(struct platform_device *pdev)
if (ret)
goto err_free_priv;
+ of_id = of_match_node(csi2tx_of_table, pdev->dev.of_node);
+ csi2tx->vops = (struct csi2tx_vops *)of_id->data;
+
v4l2_subdev_init(&csi2tx->subdev, &csi2tx_subdev_ops);
csi2tx->subdev.owner = THIS_MODULE;
csi2tx->subdev.dev = &pdev->dev;
@@ -552,12 +640,6 @@ static int csi2tx_remove(struct platform_device *pdev)
return 0;
}
-static const struct of_device_id csi2tx_of_table[] = {
- { .compatible = "cdns,csi2tx" },
- { },
-};
-MODULE_DEVICE_TABLE(of, csi2tx_of_table);
-
static struct platform_driver csi2tx_driver = {
.probe = csi2tx_probe,
.remove = csi2tx_remove,
--
2.15.0
^ permalink raw reply related
* [PATCH v2 3/4] media: Fix Lane mapping in Cadence CSI2TX
From: Jan Kotas @ 2019-07-22 8:22 UTC (permalink / raw)
To: maxime.ripard, mchehab, robh+dt, mark.rutland
Cc: rafalc, linux-media, devicetree, linux-kernel, Jan Kotas
In-Reply-To: <20190722082223.18693-1-jank@cadence.com>
This patch fixes mapping of lanes in DPHY_CFG register
of the controller. In the register, bit 0 means first data lane.
In Linux we currently assume lane 0 is clock.
Signed-off-by: Jan Kotas <jank@cadence.com>
---
drivers/media/platform/cadence/cdns-csi2tx.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/media/platform/cadence/cdns-csi2tx.c b/drivers/media/platform/cadence/cdns-csi2tx.c
index 232259c71..c72c8a065 100644
--- a/drivers/media/platform/cadence/cdns-csi2tx.c
+++ b/drivers/media/platform/cadence/cdns-csi2tx.c
@@ -236,7 +236,7 @@ static int csi2tx_start(struct csi2tx_priv *csi2tx)
/* Put our lanes (clock and data) out of reset */
reg = CSI2TX_DPHY_CFG_CLK_RESET | CSI2TX_DPHY_CFG_MODE_LPDT;
for (i = 0; i < csi2tx->num_lanes; i++)
- reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i]);
+ reg |= CSI2TX_DPHY_CFG_LANE_RESET(csi2tx->lanes[i] - 1);
writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);
udelay(10);
@@ -244,7 +244,7 @@ static int csi2tx_start(struct csi2tx_priv *csi2tx)
/* Enable our (clock and data) lanes */
reg |= CSI2TX_DPHY_CFG_CLK_ENABLE;
for (i = 0; i < csi2tx->num_lanes; i++)
- reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i]);
+ reg |= CSI2TX_DPHY_CFG_LANE_ENABLE(csi2tx->lanes[i] - 1);
writel(reg, csi2tx->base + CSI2TX_DPHY_CFG_REG);
udelay(10);
--
2.15.0
^ permalink raw reply related
* [PATCH v2 2/4] media: Add lane checks for Cadence CSI2TX
From: Jan Kotas @ 2019-07-22 8:22 UTC (permalink / raw)
To: maxime.ripard, mchehab, robh+dt, mark.rutland
Cc: rafalc, linux-media, devicetree, linux-kernel, Jan Kotas
In-Reply-To: <20190722082223.18693-1-jank@cadence.com>
This patch adds lane checks for CSI2TX, to prevent clock lane
being used as a data lane.
Signed-off-by: Jan Kotas <jank@cadence.com>
---
drivers/media/platform/cadence/cdns-csi2tx.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/media/platform/cadence/cdns-csi2tx.c b/drivers/media/platform/cadence/cdns-csi2tx.c
index 5042d053b..232259c71 100644
--- a/drivers/media/platform/cadence/cdns-csi2tx.c
+++ b/drivers/media/platform/cadence/cdns-csi2tx.c
@@ -2,7 +2,7 @@
/*
* Driver for Cadence MIPI-CSI2 TX Controller
*
- * Copyright (C) 2017-2018 Cadence Design Systems Inc.
+ * Copyright (C) 2017-2019 Cadence Design Systems Inc.
*/
#include <linux/clk.h>
@@ -434,7 +434,7 @@ static int csi2tx_check_lanes(struct csi2tx_priv *csi2tx)
{
struct v4l2_fwnode_endpoint v4l2_ep = { .bus_type = 0 };
struct device_node *ep;
- int ret;
+ int ret, i;
ep = of_graph_get_endpoint_by_regs(csi2tx->dev->of_node, 0, 0);
if (!ep)
@@ -461,6 +461,15 @@ static int csi2tx_check_lanes(struct csi2tx_priv *csi2tx)
goto out;
}
+ for (i = 0; i < csi2tx->num_lanes; i++) {
+ if (v4l2_ep.bus.mipi_csi2.data_lanes[i] < 1) {
+ dev_err(csi2tx->dev, "Invalid lane[%d] number: %u\n",
+ i, v4l2_ep.bus.mipi_csi2.data_lanes[i]);
+ ret = -EINVAL;
+ goto out;
+ }
+ }
+
memcpy(csi2tx->lanes, v4l2_ep.bus.mipi_csi2.data_lanes,
sizeof(csi2tx->lanes));
--
2.15.0
^ permalink raw reply related
* [PATCH v2 1/4] media: dt-bindings: Update bindings for Cadence CSI2TX version 2.1
From: Jan Kotas @ 2019-07-22 8:22 UTC (permalink / raw)
To: maxime.ripard, mchehab, robh+dt, mark.rutland
Cc: rafalc, linux-media, devicetree, linux-kernel, Jan Kotas
In-Reply-To: <20190722082223.18693-1-jank@cadence.com>
This patch adds a DT bindings documentation for
Cadence CSI2TX v2.1 controller.
Signed-off-by: Jan Kotas <jank@cadence.com>
---
Documentation/devicetree/bindings/media/cdns,csi2tx.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/media/cdns,csi2tx.txt b/Documentation/devicetree/bindings/media/cdns,csi2tx.txt
index 459c6e332..751b9edf1 100644
--- a/Documentation/devicetree/bindings/media/cdns,csi2tx.txt
+++ b/Documentation/devicetree/bindings/media/cdns,csi2tx.txt
@@ -5,7 +5,8 @@ The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
4 CSI lanes in output, and up to 4 different pixel streams in input.
Required properties:
- - compatible: must be set to "cdns,csi2tx"
+ - compatible: must be set to "cdns,csi2tx" or "cdns,csi2tx-1.3"
+ for version 1.3 of the controller, "cdns,csi2tx-2.1" for v2.1
- reg: base address and size of the memory mapped region
- clocks: phandles to the clocks driving the controller
- clock-names: must contain:
--
2.15.0
^ permalink raw reply related
* [PATCH v2 0/4] media: Add support for Cadence CSI2TX version 2.1
From: Jan Kotas @ 2019-07-22 8:22 UTC (permalink / raw)
To: maxime.ripard, mchehab, robh+dt, mark.rutland
Cc: rafalc, linux-media, devicetree, linux-kernel, Jan Kotas
This patchset adds support for Cadence CSI2TX controller version 2.1.
Existing compatibility with v1.3 is updated and maintained.
Jan Kotas (4):
media: dt-bindings: Update bindings for Cadence CSI2TX version 2.1
media: Add lane checks for Cadence CSI2TX
media: Fix Lane mapping in Cadence CSI2TX
media: Add support for Cadence CSI2TX 2.1
.../devicetree/bindings/media/cdns,csi2tx.txt | 3 +-
drivers/media/platform/cadence/cdns-csi2tx.c | 155 ++++++++++++++++-----
2 files changed, 125 insertions(+), 33 deletions(-)
--
2.15.0
^ permalink raw reply
* Re: [PATCH] riscv: dts: fu540-c000: Add "status" property to cpu node
From: Mark Rutland @ 2019-07-22 8:18 UTC (permalink / raw)
To: Bin Meng
Cc: devicetree, Albert Ou, Anup Patel, Yash Shah, Rob Herring,
Palmer Dabbelt, Paul Walmsley, linux-riscv
In-Reply-To: <CAEUhbmWdLoRU1QGVZtwmymtYyQw43UMR8WDB17rJRmvXGbuBTg@mail.gmail.com>
On Fri, Jul 05, 2019 at 01:11:01PM +0800, Bin Meng wrote:
> On Fri, Jul 5, 2019 at 11:59 AM Anup Patel <Anup.Patel@wdc.com> wrote:
> >
> >
> >
> > > -----Original Message-----
> > > From: linux-riscv <linux-riscv-bounces@lists.infradead.org> On Behalf Of Bin
> > > Meng
> > > Sent: Friday, July 5, 2019 9:23 AM
> > > To: linux-riscv <linux-riscv@lists.infradead.org>; devicetree
> > > <devicetree@vger.kernel.org>; Rob Herring <robh+dt@kernel.org>; Mark
> > > Rutland <mark.rutland@arm.com>; Albert Ou <aou@eecs.berkeley.edu>;
> > > Paul Walmsley <paul.walmsley@sifive.com>; Palmer Dabbelt
> > > <palmer@sifive.com>; Yash Shah <yash.shah@sifive.com>
> > > Subject: [PATCH] riscv: dts: fu540-c000: Add "status" property to cpu node
> > >
> > > Per device tree spec, the "status" property property shall be present for
> > > nodes representing CPUs in a SMP configuration. This property is currently
> > > missing in cpu 1/2/3/4 node in the fu540-c000.dtsi.
> >
> > We don't need explicit "status = okay" for SOC internal devices
> > (such as PLIC, INTC, etc) which are always enabled by default.
> >
>
> Yes, that's fine because those device bindings do not require them.
>
> > Absence of "status" DT prop is treated as enabled by default.
> >
>
> But per current device tree spec, "status" in cpu node is mandatory.
> (spec uses "shall"). Missing it is a spec violation.
I think this is a spec bug (or at least misleading wording in the spec).
IEEE 1275 says (for status as a generic property):
The absence of this property menas that the operational status is unknown or
okay.
... and I think it's fine to treat that the same as an explicit "okay" here, as
we do generically in Linux.
Thanks,
Mark.
^ permalink raw reply
* [PATCH 11/11] ARM: dts: v3s: Change the timers compatible
From: Maxime Ripard @ 2019-07-22 8:12 UTC (permalink / raw)
To: Mark Rutland, Rob Herring, Frank Rowand, Chen-Yu Tsai,
Maxime Ripard, daniel.lezcano, tglx
Cc: devicetree, linux-arm-kernel
In-Reply-To: <20190722081229.22422-1-maxime.ripard@bootlin.com>
Unlike the A10 that has 6 timers available, the v3s has only three, with only
three interrupts. Let's change the compatible to reflect that, and add the
missing interrupts.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index d7aef128acb3..1fce5b07c65c 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -327,10 +327,11 @@
};
timer@1c20c00 {
- compatible = "allwinner,sun4i-a10-timer";
+ compatible = "allwinner,sun8i-v3s-timer";
reg = <0x01c20c00 0xa0>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
--
2.21.0
^ permalink raw reply related
* [PATCH 10/11] ARM: dts: h3: Change the timers compatible
From: Maxime Ripard @ 2019-07-22 8:12 UTC (permalink / raw)
To: Mark Rutland, Rob Herring, Frank Rowand, Chen-Yu Tsai,
Maxime Ripard, daniel.lezcano, tglx
Cc: devicetree, linux-arm-kernel
In-Reply-To: <20190722081229.22422-1-maxime.ripard@bootlin.com>
Unlike the A10 that has 6 timers available, the H3 has only two, with only
two interrupts, just like the A23. Let's change the compatible to reflect
that.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 84977d4eb97a..fa8bac5aa3ce 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -484,7 +484,7 @@
};
timer@1c20c00 {
- compatible = "allwinner,sun4i-a10-timer";
+ compatible = "allwinner,sun8i-a23-timer";
reg = <0x01c20c00 0xa0>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
--
2.21.0
^ permalink raw reply related
* [PATCH 09/11] ARM: dts: a83t: Change the timers compatible
From: Maxime Ripard @ 2019-07-22 8:12 UTC (permalink / raw)
To: Mark Rutland, Rob Herring, Frank Rowand, Chen-Yu Tsai,
Maxime Ripard, daniel.lezcano, tglx
Cc: devicetree, linux-arm-kernel
In-Reply-To: <20190722081229.22422-1-maxime.ripard@bootlin.com>
Unlike the A10 that has 6 timers available, the A83t has only two, with
only two interrupts, just like the A23. Let's change the compatible to
reflect that.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index ada6d08bc540..b849fbfd3cbf 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -806,7 +806,7 @@
};
timer@1c20c00 {
- compatible = "allwinner,sun4i-a10-timer";
+ compatible = "allwinner,sun8i-a23-timer";
reg = <0x01c20c00 0xa0>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
--
2.21.0
^ permalink raw reply related
* [PATCH 08/11] ARM: dts: a23/a33: Change the timers compatible
From: Maxime Ripard @ 2019-07-22 8:12 UTC (permalink / raw)
To: Mark Rutland, Rob Herring, Frank Rowand, Chen-Yu Tsai,
Maxime Ripard, daniel.lezcano, tglx
Cc: devicetree, linux-arm-kernel
In-Reply-To: <20190722081229.22422-1-maxime.ripard@bootlin.com>
Unlike the A10 that has 6 timers available, the A23 and A33 has only two,
with only two interrupts. Let's change the compatible to reflect that.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
index af2fa694a467..954489b4ec66 100644
--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
@@ -441,7 +441,7 @@
};
timer@1c20c00 {
- compatible = "allwinner,sun4i-a10-timer";
+ compatible = "allwinner,sun8i-a23-timer";
reg = <0x01c20c00 0xa0>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
--
2.21.0
^ permalink raw reply related
* [PATCH 07/11] ARM: dts: sun6i: Add missing timers interrupts
From: Maxime Ripard @ 2019-07-22 8:12 UTC (permalink / raw)
To: Mark Rutland, Rob Herring, Frank Rowand, Chen-Yu Tsai,
Maxime Ripard, daniel.lezcano, tglx
Cc: devicetree, linux-arm-kernel
In-Reply-To: <20190722081229.22422-1-maxime.ripard@bootlin.com>
The timer unit in the A31 has 6 interrupts available. List all of them.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index dcddc3392460..4c1ac7e58ae3 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -736,7 +736,8 @@
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&osc24M>;
};
--
2.21.0
^ permalink raw reply related
* [PATCH 06/11] ARM: dts: sun5i: Add missing timers interrupts
From: Maxime Ripard @ 2019-07-22 8:12 UTC (permalink / raw)
To: Mark Rutland, Rob Herring, Frank Rowand, Chen-Yu Tsai,
Maxime Ripard, daniel.lezcano, tglx
Cc: devicetree, linux-arm-kernel
In-Reply-To: <20190722081229.22422-1-maxime.ripard@bootlin.com>
The timer unit in the sun5i die has 6 interrupts available. List all of
them.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
arch/arm/boot/dts/sun5i.dtsi | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 2fb438c4fe9d..4e725afe7203 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -588,7 +588,12 @@
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0x90>;
- interrupts = <22>;
+ interrupts = <22>,
+ <23>,
+ <24>,
+ <25>,
+ <67>,
+ <68>;
clocks = <&ccu CLK_HOSC>;
};
--
2.21.0
^ permalink raw reply related
* [PATCH 05/11] ARM: dts: sun4i: Add missing timers interrupts
From: Maxime Ripard @ 2019-07-22 8:12 UTC (permalink / raw)
To: Mark Rutland, Rob Herring, Frank Rowand, Chen-Yu Tsai,
Maxime Ripard, daniel.lezcano, tglx
Cc: devicetree, linux-arm-kernel
In-Reply-To: <20190722081229.22422-1-maxime.ripard@bootlin.com>
The timer unit in the A10 has 6 interrupts available. List all of them.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
arch/arm/boot/dts/sun4i-a10.dtsi | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index e88daa4ef1af..077d45c7db6f 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -803,7 +803,12 @@
timer@1c20c00 {
compatible = "allwinner,sun4i-a10-timer";
reg = <0x01c20c00 0x90>;
- interrupts = <22>;
+ interrupts = <22>,
+ <23>,
+ <24>,
+ <25>,
+ <67>,
+ <68>;
clocks = <&osc24M>;
};
--
2.21.0
^ permalink raw reply related
* [PATCH 04/11] dt-bindings: timer: Convert Allwinner A13 HSTimer to a schema
From: Maxime Ripard @ 2019-07-22 8:12 UTC (permalink / raw)
To: Mark Rutland, Rob Herring, Frank Rowand, Chen-Yu Tsai,
Maxime Ripard, daniel.lezcano, tglx
Cc: devicetree, linux-arm-kernel
In-Reply-To: <20190722081229.22422-1-maxime.ripard@bootlin.com>
The newer Allwinner SoCs have a High Speed Timer supported in Linux, with a
matching Device Tree binding.
Now that we have the DT validation in place, let's convert the device tree
bindings for that controller over to a YAML schemas.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
.../timer/allwinner,sun5i-a13-hstimer.txt | 26 ------
.../timer/allwinner,sun5i-a13-hstimer.yaml | 79 +++++++++++++++++++
2 files changed, 79 insertions(+), 26 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
create mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
deleted file mode 100644
index 2c5c1be78360..000000000000
--- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Allwinner SoCs High Speed Timer Controller
-
-Required properties:
-
-- compatible : should be "allwinner,sun5i-a13-hstimer" or
- "allwinner,sun7i-a20-hstimer"
-- reg : Specifies base physical address and size of the registers.
-- interrupts : The interrupts of these timers (2 for the sun5i IP, 4 for the sun7i
- one)
-- clocks: phandle to the source clock (usually the AHB clock)
-
-Optional properties:
-- resets: phandle to a reset controller asserting the timer
-
-Example:
-
-timer@1c60000 {
- compatible = "allwinner,sun7i-a20-hstimer";
- reg = <0x01c60000 0x1000>;
- interrupts = <0 51 1>,
- <0 52 1>,
- <0 53 1>,
- <0 54 1>;
- clocks = <&ahb1_gates 19>;
- resets = <&ahb1rst 19>;
-};
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml
new file mode 100644
index 000000000000..dfa0c41fd261
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/allwinner,sun5i-a13-hstimer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A13 High-Speed Timer Device Tree Bindings
+
+maintainers:
+ - Chen-Yu Tsai <wens@csie.org>
+ - Maxime Ripard <maxime.ripard@bootlin.com>
+
+properties:
+ compatible:
+ oneOf:
+ - const: allwinner,sun5i-a13-hstimer
+ - const: allwinner,sun7i-a20-hstimer
+ - items:
+ - const: allwinner,sun6i-a31-hstimer
+ - const: allwinner,sun7i-a20-hstimer
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 2
+ maxItems: 4
+ items:
+ - description: Timer 0 Interrupt
+ - description: Timer 1 Interrupt
+ - description: Timer 2 Interrupt
+ - description: Timer 3 Interrupt
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+if:
+ properties:
+ compatible:
+ items:
+ const: allwinner,sun5i-a13-hstimer
+
+then:
+ properties:
+ interrupts:
+ minItems: 2
+ maxItems: 2
+
+else:
+ properties:
+ interrupts:
+ minItems: 4
+ maxItems: 4
+
+additionalProperties: false
+
+examples:
+ - |
+ timer@1c60000 {
+ compatible = "allwinner,sun7i-a20-hstimer";
+ reg = <0x01c60000 0x1000>;
+ interrupts = <0 51 1>,
+ <0 52 1>,
+ <0 53 1>,
+ <0 54 1>;
+ clocks = <&ahb1_gates 19>;
+ resets = <&ahb1rst 19>;
+ };
+
+...
--
2.21.0
^ permalink raw reply related
* [PATCH 03/11] clocksource: sun4i: Add missing compatibles
From: Maxime Ripard @ 2019-07-22 8:12 UTC (permalink / raw)
To: Mark Rutland, Rob Herring, Frank Rowand, Chen-Yu Tsai,
Maxime Ripard, daniel.lezcano, tglx
Cc: devicetree, linux-arm-kernel
In-Reply-To: <20190722081229.22422-1-maxime.ripard@bootlin.com>
Newer Allwinner SoCs have different number of interrupts, let's add
different compatibles for all of them to deal with this properly.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
drivers/clocksource/timer-sun4i.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clocksource/timer-sun4i.c b/drivers/clocksource/timer-sun4i.c
index 65f38f6ca714..0ba8155b8287 100644
--- a/drivers/clocksource/timer-sun4i.c
+++ b/drivers/clocksource/timer-sun4i.c
@@ -219,5 +219,9 @@ static int __init sun4i_timer_init(struct device_node *node)
}
TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
sun4i_timer_init);
+TIMER_OF_DECLARE(sun8i_a23, "allwinner,sun8i-a23-timer",
+ sun4i_timer_init);
+TIMER_OF_DECLARE(sun8i_v3s, "allwinner,sun8i-v3s-timer",
+ sun4i_timer_init);
TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer",
sun4i_timer_init);
--
2.21.0
^ permalink raw reply related
* [PATCH 02/11] dt-bindings: timer: Add missing compatibles
From: Maxime Ripard @ 2019-07-22 8:12 UTC (permalink / raw)
To: Mark Rutland, Rob Herring, Frank Rowand, Chen-Yu Tsai,
Maxime Ripard, daniel.lezcano, tglx
Cc: devicetree, linux-arm-kernel
In-Reply-To: <20190722081229.22422-1-maxime.ripard@bootlin.com>
Newer Allwinner SoCs have different number of interrupts, let's add
different compatibles for all of them to deal with this properly.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
.../timer/allwinner,sun4i-a10-timer.yaml | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
index 7292a424092c..20adc1c8e9cc 100644
--- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
@@ -14,6 +14,8 @@ properties:
compatible:
enum:
- allwinner,sun4i-a10-timer
+ - allwinner,sun8i-a23-timer
+ - allwinner,sun8i-v3s-timer
- allwinner,suniv-f1c100s-timer
reg:
@@ -39,6 +41,30 @@ allOf:
minItems: 6
maxItems: 6
+ - if:
+ properties:
+ compatible:
+ items:
+ const: allwinner,sun8i-a23-timer
+
+ then:
+ properties:
+ interrupts:
+ minItems: 2
+ maxItems: 2
+
+ - if:
+ properties:
+ compatible:
+ items:
+ const: allwinner,sun8i-v3s-timer
+
+ then:
+ properties:
+ interrupts:
+ minItems: 3
+ maxItems: 3
+
- if:
properties:
compatible:
--
2.21.0
^ permalink raw reply related
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