* Re: [PATCH 3/3] riscv: dts: Add DT node for SiFive FU540 Ethernet controller driver
From: Paul Walmsley @ 2019-07-22 21:48 UTC (permalink / raw)
To: Yash Shah, davem
Cc: sagar.kadam, robh+dt, netdev, devicetree, linux-kernel,
linux-riscv, mark.rutland, palmer, aou, nicolas.ferre, ynezz,
sachin.ghadi, andrew
In-Reply-To: <1563534631-15897-3-git-send-email-yash.shah@sifive.com>
On Fri, 19 Jul 2019, Yash Shah wrote:
> DT node for SiFive FU540-C000 GEMGXL Ethernet controller driver added
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
Thanks, queuing this one for v5.3-rc with Andrew's suggested change to
change phy1 to phy0.
Am assuming patches 1 and 2 will go in via -net.
- Paul
^ permalink raw reply
* Re: [PATCH 2/3] macb: Update compatibility string for SiFive FU540-C000
From: Paul Walmsley @ 2019-07-22 21:46 UTC (permalink / raw)
To: Yash Shah
Cc: davem, robh+dt, netdev, devicetree, linux-kernel, linux-riscv,
mark.rutland, palmer, aou, nicolas.ferre, ynezz, sachin.ghadi
In-Reply-To: <1563534631-15897-2-git-send-email-yash.shah@sifive.com>
On Fri, 19 Jul 2019, Yash Shah wrote:
> Update the compatibility string for SiFive FU540-C000 as per the new
> string updated in the binding doc.
> Reference: https://lkml.org/lkml/2019/7/17/200
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
Tested-by: Paul Walmsley <paul.walmsley@sifive.com>
- Paul
^ permalink raw reply
* Re: [PATCH 1/5] MIPS: ralink: add dt binding header for mt7621-pll
From: Stephen Boyd @ 2019-07-22 21:40 UTC (permalink / raw)
To: open list:COMMON CLK FRAMEWORK, open list:MIPS,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:STAGING SUBSYSTEM, Chuanhong Guo, open list
Cc: Mark Rutland, Weijie Gao, Greg Kroah-Hartman, James Hogan,
Michael Turquette, Ralf Baechle, Paul Burton, Rob Herring,
John Crispin, NeilBrown, Rob Herring
In-Reply-To: <20190709182018.23193-2-gch981213@gmail.com>
The subject of this patch is confusing. Not sure what it has to do with
"MIPS:" so maybe remove that and prefix it "dt-bindings: clock:"
instead.
Quoting Chuanhong Guo (2019-07-09 11:20:14)
> This patch adds dt binding header for mediatek,mt7621-pll
>
> Signed-off-by: Weijie Gao <hackpascal@gmail.com>
> Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
Otherwise looks ok to me. Should I apply it to clk tree?
> include/dt-bindings/clock/mt7621-clk.h | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
> create mode 100644 include/dt-bindings/clock/mt7621-clk.h
>
^ permalink raw reply
* Re: [PATCH 5/6] clk: imx8mq: Remove CLK_IS_CRITICAL flag for IMX8MQ_CLK_TMU_ROOT
From: Stephen Boyd @ 2019-07-22 21:31 UTC (permalink / raw)
To: Anson.Huang, abel.vesa, agx, andrew.smirnov, angus, ccaione,
daniel.lezcano, devicetree, edubezval, festevam, kernel, l.stach,
leonard.crestez, linux-arm-kernel, linux-clk, linux-kernel,
linux-pm, mark.rutland, mturquette, robh+dt, rui.zhang, s.hauer,
shawnguo
Cc: Linux-imx
In-Reply-To: <20190705045612.27665-5-Anson.Huang@nxp.com>
Quoting Anson.Huang@nxp.com (2019-07-04 21:56:11)
> From: Anson Huang <Anson.Huang@nxp.com>
>
> IMX8MQ_CLK_TMU_ROOT is ONLY used for thermal module, the driver
> should manage this clock, so no need to have CLK_IS_CRITICAL flag
> set.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply
* Re: [PATCH 3/3] MIPS: BMIPS: add clock controller nodes
From: Paul Burton @ 2019-07-22 21:22 UTC (permalink / raw)
To: Jonas Gorski
Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-mips@vger.kernel.org, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, Florian Fainelli,
bcm-kernel-feedback-list@broadcom.com, Kevin Cernekee,
Ralf Baechle, Paul Burton, James Hogan
In-Reply-To: <20190502122657.15577-4-jonas.gorski@gmail.com>
Hello,
Jonas Gorski wrote:
> Now that we have a driver for the clock controller, add nodes to allow
> devices to make use of it.
>
> Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Applied to mips-next.
Thanks,
Paul
[ This message was auto-generated; if you believe anything is incorrect
then please email paul.burton@mips.com to report it. ]
^ permalink raw reply
* Re: [PATCH 2/3] MIPS: DTS: jz4740: Add node for the MMC driver
From: Paul Burton @ 2019-07-22 21:22 UTC (permalink / raw)
Cc: Rob Herring, Mark Rutland, Ralf Baechle, Paul Burton, James Hogan,
Ulf Hansson, Linus Walleij, devicetree@vger.kernel.org,
linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-mmc@vger.kernel.org, Paul Cercueil
In-Reply-To: <20190125200927.21045-2-paul@crapouillou.net>
Hello,
Paul Cercueil wrote:
> Add a devicetree node for the jz4740-mmc driver.
>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Applied to mips-next.
Thanks,
Paul
[ This message was auto-generated; if you believe anything is incorrect
then please email paul.burton@mips.com to report it. ]
^ permalink raw reply
* Re: [PATCH v2] arm64: dts: fsl: pico-pi: Add a device tree for the PICO-PI-IMX8M
From: Daniel Baluta @ 2019-07-22 21:19 UTC (permalink / raw)
To: Vaittinen, Matti
Cc: Shawn Guo, Andra Danciu, robh+dt@kernel.org, mark.rutland@arm.com,
leoyang.li@nxp.com, Fabio Estevam, aisheng.dong@nxp.com,
l.stach@pengutronix.de, angus@akkea.ca, vabhav.sharma@nxp.com,
pankaj.bansal@nxp.com, bhaskar.upadhaya@nxp.com, ping.bai@nxp.com,
Manivannan Sadhasivam, Richard Hu, devicetree@vger.kernel.org,
"linux-kernel@vger.kernel.org" <linux-kern>
In-Reply-To: <042F8805D2046347BB8420BEAE397A40749E9BDA@WILL-MAIL002.REu.RohmEu.com>
On Mon, Jul 22, 2019 at 9:30 PM Vaittinen, Matti
<Matti.Vaittinen@fi.rohmeurope.com> wrote:
>
> Sorry for top posting. I'm replying using mobile phone and outlook web app...
>
> gpio_intr is not needed. Irq must be given using the standard irq property. gpio_intr has been used in an old draft driver - I assume the dts originates from NXP bsp which used the old driver.
Thanks Matti for your observation! We already fixed this as we are now
on v6 of the patches for review :).
yes the dts originates form TechNexion bsp tree which is based on NXP tree :).
Daniel.
^ permalink raw reply
* Re: [PATCH v2 6/8] PCI: al: Add support for DW based driver type
From: Bjorn Helgaas @ 2019-07-22 21:15 UTC (permalink / raw)
To: Chocron, Jonathan
Cc: jingoohan1@gmail.com, mark.rutland@arm.com,
lorenzo.pieralisi@arm.com, Gustavo.Pimentel@synopsys.com,
robh+dt@kernel.org, linux-kernel@vger.kernel.org,
Woodhouse, David, Hanoch, Uri, devicetree@vger.kernel.org,
Wasserstrom, Barak, Saidi, Ali, Hawa, Hanna, Shenhar, Talel,
Krupnik, Ronen, linux-pci@vger.kernel.org,
benh@kernel.crashing.org
In-Reply-To: <d323007c6bf14cb9f90a497a26b66dac151164fc.camel@amazon.com>
On Sun, Jul 21, 2019 at 03:08:18PM +0000, Chocron, Jonathan wrote:
> On Fri, 2019-07-19 at 08:55 +0000, Gustavo Pimentel wrote:
> > On Thu, Jul 18, 2019 at 10:47:16, Jonathan Chocron <jonnyc@amazon.com> wrote:
> > > +static int al_pcie_probe(struct platform_device *pdev)
> > > +{
> > > + struct device *dev = &pdev->dev;
> > > + struct al_pcie *al_pcie;
> > > + struct dw_pcie *pci;
> > > + struct resource *dbi_res;
> > > + struct resource *controller_res;
> > > + struct resource *ecam_res;
> > > + int ret;
> >
> > Please sort the variables following the reverse tree order.
> >
> Done.
>
> I'd think that it would make sense to group variables which have a
> common characteristic (e.g. resources read from the DT), even if it
> mildly breaks the convention (as long as the general frame is longest
> to shortest). Does this sound ok?
>
> BTW, I couldn't find any documentation regarding the reverse-tree
> convention, do you have a pointer to some?
What I personally do is sort declarations in the order they're used.
^ permalink raw reply
* Re: [PATCH] dt-bindings: rtc: Remove the PCF8563 from the trivial RTCs
From: Alexandre Belloni @ 2019-07-22 20:23 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mark Rutland, devicetree, Chen-Yu Tsai, Rob Herring, Frank Rowand,
linux-arm-kernel, linux-rtc
In-Reply-To: <20190722140921.22681-1-maxime.ripard@bootlin.com>
On 22/07/2019 16:09:21+0200, Maxime Ripard wrote:
> The PCF8563 has a binding of its own, with some, clocks related, additional
> properties.
>
> Remove it from the trivial RTC bindings.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
> ---
> Documentation/devicetree/bindings/rtc/trivial-rtc.yaml | 2 --
> 1 file changed, 2 deletions(-)
>
Applied, thanks.
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* [PATCH 4/4] arm64: dts: ti: k3-j721e-main: Add IPC sub-mailbox nodes for all R5Fs & DSPs
From: Suman Anna @ 2019-07-22 20:20 UTC (permalink / raw)
To: Tero Kristo, Nishanth Menon; +Cc: devicetree, linux-arm-kernel
In-Reply-To: <20190722202024.14867-1-s-anna@ti.com>
Add the sub-mailbox nodes that are used to communicate between MPU and
various remote processors present in the J721E SoCs. These include the
R5F remote processors in the dual-R5F cluster (MCU_R5FSS0) in the MCU
domain and the two dual-R5F clusters (MAIN_R5FSS0 & MAIN_R5FSS1) in the
MAIN domain; the two C66x DSP remote processors and the single C71x DSP
remote processor in the MAIN domain. The parent mailbox cluster nodes
are also enabled.
The sub-mailbox nodes utilize the System Mailbox clusters 0 through 4.
These sub-mailbox nodes are added to match the hard-coded mailbox
configuration used within the TI RTOS IPC software packages. The R5F
processor sub-systems are assumed to be running in Split mode, so a
sub-mailbox node is used by each of the R5F cores. The sub-mailbox node
for the first R5F core in each cluster is used in case of Lockstep mode.
NOTE:
The GIC_SPI interrupts to be used are dynamically allocated and managed
by the System Firmware through the ti-sci-intr irqchip driver. So, only
valid interrupts (each cluster's User 0 IRQ output) that are used by the
sub-mailbox devices are enabled. This is done to minimize the number of
NavSS Interrupt Router outputs utilized.
Signed-off-by: Suman Anna <s-anna@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 60 +++++++++++++++++++++--
1 file changed, 55 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 319d423b3440..2985c73154fd 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -102,7 +102,18 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
- status = "disabled";
+ interrupt-parent = <&main_navss_intr>;
+ interrupts = <214 0>;
+
+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
};
mailbox0_cluster1: mailbox@31f81000 {
@@ -111,7 +122,18 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
- status = "disabled";
+ interrupt-parent = <&main_navss_intr>;
+ interrupts = <215 0>;
+
+ mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
};
mailbox0_cluster2: mailbox@31f82000 {
@@ -120,7 +142,18 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
- status = "disabled";
+ interrupt-parent = <&main_navss_intr>;
+ interrupts = <216 0>;
+
+ mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
};
mailbox0_cluster3: mailbox@31f83000 {
@@ -129,7 +162,18 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
- status = "disabled";
+ interrupt-parent = <&main_navss_intr>;
+ interrupts = <217 0>;
+
+ mbox_c66_0: mbox-c66-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
+
+ mbox_c66_1: mbox-c66-1 {
+ ti,mbox-rx = <2 0 0>;
+ ti,mbox-tx = <3 0 0>;
+ };
};
mailbox0_cluster4: mailbox@31f84000 {
@@ -138,7 +182,13 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
- status = "disabled";
+ interrupt-parent = <&main_navss_intr>;
+ interrupts = <218 0>;
+
+ mbox_c71_0: mbox-c71-0 {
+ ti,mbox-rx = <0 0 0>;
+ ti,mbox-tx = <1 0 0>;
+ };
};
mailbox0_cluster5: mailbox@31f85000 {
--
2.22.0
^ permalink raw reply related
* [PATCH 3/4] arm64: dts: ti: k3-j721e-main: Add mailbox cluster nodes
From: Suman Anna @ 2019-07-22 20:20 UTC (permalink / raw)
To: Tero Kristo, Nishanth Menon; +Cc: devicetree, linux-arm-kernel
In-Reply-To: <20190722202024.14867-1-s-anna@ti.com>
The J721E Main NavSS block contains a Mailbox IP instance with
multiple clusters. Each cluster is equivalent to an Mailbox IP
instance on OMAP platforms.
Add all the Mailbox clusters as their own nodes under the MAIN
NavSS cbass_main_navss interconnect node instead of creating an
almost empty parent node for the new K3 mailbox IP and the clusters
as its child nodes. All these nodes are marked as disabled, and
they need to be enabled along with the appropriate child nodes
on a need basis.
NOTE:
The NavSS only has a limited number of interrupts, so all the
interrupts generated by a Mailbox IP are not added by default.
Only the needed interrupts that are targeted towards the A72
GIC will need to be be added later on when some sub-mailbox
child nodes are added.
Signed-off-by: Suman Anna <s-anna@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 108 ++++++++++++++++++++++
1 file changed, 108 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index a2e031f7d88e..319d423b3440 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -95,6 +95,114 @@
reg = <0x00 0x30e00000 0x00 0x1000>;
#hwlock-cells = <1>;
};
+
+ mailbox0_cluster0: mailbox@31f80000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f80000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster1: mailbox@31f81000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f81000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster2: mailbox@31f82000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f82000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster3: mailbox@31f83000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f83000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster4: mailbox@31f84000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f84000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster5: mailbox@31f85000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f85000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster6: mailbox@31f86000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f86000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster7: mailbox@31f87000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f87000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster8: mailbox@31f88000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f88000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster9: mailbox@31f89000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f89000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster10: mailbox@31f8a000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f8a000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster11: mailbox@31f8b000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f8b000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
};
secure_proxy_main: mailbox@32c00000 {
--
2.22.0
^ permalink raw reply related
* [PATCH 2/4] arm64: dts: ti: k3-am65-main: Add IPC sub-mailbox nodes for R5Fs
From: Suman Anna @ 2019-07-22 20:20 UTC (permalink / raw)
To: Tero Kristo, Nishanth Menon; +Cc: devicetree, linux-arm-kernel
In-Reply-To: <20190722202024.14867-1-s-anna@ti.com>
Add the sub-mailbox nodes that are used to communicate between
MPU and the two R5F remote processors present in the MCU domain.
The parent mailbox cluster nodes are enabled and the interrupts
associated with the Mailbox Cluster User interrupt used by the
sub-mailbox nodes are also added. The GIC_SPI interrupt to be
used is dynamically allocated and managed by the System Firmware
through the ti-sci-intr irqchip driver.
The sub-mailbox nodes utilize the System Mailbox clusters 1 and 2.
These sub-mailbox nodes are added to match the hard-coded mailbox
configuration used within the TI RTOS IPC software packages. The
Cortex R5F processor sub-system is assumed to be running in Split
mode, so a sub-mailbox node is used by each of the R5F cores. Only
the sub-mailbox node from cluster 0 is used in case of Lockstep
mode.
Signed-off-by: Suman Anna <s-anna@ti.com>
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 0b3ea2a871ee..317563c995b1 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -426,7 +426,13 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
- status = "disabled";
+ interrupt-parent = <&intr_main_navss>;
+ interrupts = <164 0>;
+
+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+ ti,mbox-tx = <1 0 0>;
+ ti,mbox-rx = <0 0 0>;
+ };
};
mailbox0_cluster1: mailbox@31f81000 {
@@ -435,7 +441,13 @@
#mbox-cells = <1>;
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
- status = "disabled";
+ interrupt-parent = <&intr_main_navss>;
+ interrupts = <165 0>;
+
+ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
+ ti,mbox-tx = <1 0 0>;
+ ti,mbox-rx = <0 0 0>;
+ };
};
mailbox0_cluster2: mailbox@31f82000 {
--
2.22.0
^ permalink raw reply related
* [PATCH 1/4] arm64: dts: ti: k3-am65-main: Add mailbox cluster nodes
From: Suman Anna @ 2019-07-22 20:20 UTC (permalink / raw)
To: Tero Kristo, Nishanth Menon; +Cc: devicetree, linux-arm-kernel
In-Reply-To: <20190722202024.14867-1-s-anna@ti.com>
The AM65x Main NavSS block contains a Mailbox IP instance with
multiple clusters. Each cluster is equivalent to an Mailbox IP
instance on OMAP platforms.
Add all the Mailbox clusters as their own nodes under the MAIN
NavSS cbass_main_navss interconnect node instead of creating an
almost empty parent node for the new K3 mailbox IP and the clusters
as its child nodes. All these nodes are marked as disabled, and
they need to be enabled along with the appropriate child nodes
on a need basis.
NOTE:
The NavSS only has a limited number of interrupts, so all the
interrupts generated by a Mailbox IP are not added by default.
Only the needed interrupts that are targeted towards the A53
GIC will need to be be added later on when some sub-mailbox
child nodes are added.
Signed-off-by: Suman Anna <s-anna@ti.com>
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 108 +++++++++++++++++++++++
1 file changed, 108 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 8413e80f9d3a..0b3ea2a871ee 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -419,6 +419,114 @@
reg = <0x00 0x30e00000 0x00 0x1000>;
#hwlock-cells = <1>;
};
+
+ mailbox0_cluster0: mailbox@31f80000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f80000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster1: mailbox@31f81000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f81000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster2: mailbox@31f82000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f82000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster3: mailbox@31f83000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f83000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster4: mailbox@31f84000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f84000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster5: mailbox@31f85000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f85000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster6: mailbox@31f86000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f86000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster7: mailbox@31f87000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f87000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster8: mailbox@31f88000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f88000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster9: mailbox@31f89000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f89000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster10: mailbox@31f8a000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f8a000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
+
+ mailbox0_cluster11: mailbox@31f8b000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x00 0x31f8b000 0x00 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ status = "disabled";
+ };
};
main_gpio0: main_gpio0@600000 {
--
2.22.0
^ permalink raw reply related
* [PATCH 0/4] Add Mailbox nodes for TI K3 AM65x & J721E SoCs
From: Suman Anna @ 2019-07-22 20:20 UTC (permalink / raw)
To: Tero Kristo, Nishanth Menon; +Cc: devicetree, linux-arm-kernel
Hi Tero,
The following series adds the Mailbox DT nodes and the sub-mailboxes
used to communicate between the main MPU processor running Linux and
the various R5F and DSP remote processors present on the TI K3 AM65x
and J721E SoC families. Patches are based on v5.3-rc1 + the HwSpinlock
DT node series [1], and are intended for the 5.4 merge window.
The bindings and driver support for the same have already been merged
in v5.3-rc1. Functionality is verified using a out-of-tree unit-test
module and some additional loopback test nodes available here [2] for
reference.
regards
Suman
[1] https://patchwork.kernel.org/cover/11053311/
[2] https://github.com/sumananna/mailbox/commits/mbox/test/5.3-rc1-k3
Suman Anna (4):
arm64: dts: ti: k3-am65-main: Add mailbox cluster nodes
arm64: dts: ti: k3-am65-main: Add IPC sub-mailbox nodes for R5Fs
arm64: dts: ti: k3-j721e-main: Add mailbox cluster nodes
arm64: dts: ti: k3-j721e-main: Add IPC sub-mailbox nodes for all R5Fs
& DSPs
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 120 ++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 158 ++++++++++++++++++++++
2 files changed, 278 insertions(+)
--
2.22.0
^ permalink raw reply
* Re: [PATCH] iio: potentiometer: add a driver for Maxim 5432-5435
From: kbuild test robot @ 2019-07-22 20:13 UTC (permalink / raw)
Cc: kbuild-all, Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen,
Rob Herring, linux-iio, devicetree, linux-kernel, Martin Kaiser
In-Reply-To: <20190721175915.27192-1-martin@kaiser.cx>
[-- Attachment #1: Type: text/plain, Size: 2219 bytes --]
Hi Martin,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.3-rc1 next-20190722]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Martin-Kaiser/iio-potentiometer-add-a-driver-for-Maxim-5432-5435/20190723-024214
config: arm64-allmodconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 7.4.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=arm64
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
drivers/iio/potentiometer/max5432.c: In function 'max5432_probe':
>> drivers/iio/potentiometer/max5432.c:99:14: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
data->ohm = (u32)of_device_get_match_data(dev);
^
vim +99 drivers/iio/potentiometer/max5432.c
83
84 static int max5432_probe(
85 struct i2c_client *client, const struct i2c_device_id *id)
86 {
87 struct device *dev = &client->dev;
88 struct iio_dev *indio_dev;
89 struct max5432_data *data;
90
91 indio_dev = devm_iio_device_alloc(dev, sizeof(struct max5432_data));
92 if (!indio_dev)
93 return -ENOMEM;
94
95 i2c_set_clientdata(client, indio_dev);
96
97 data = iio_priv(indio_dev);
98 data->client = client;
> 99 data->ohm = (u32)of_device_get_match_data(dev);
100
101 indio_dev->dev.parent = dev;
102 indio_dev->info = &max5432_info;
103 indio_dev->channels = max5432_channels;
104 indio_dev->num_channels = ARRAY_SIZE(max5432_channels);
105 indio_dev->name = client->name;
106
107 return devm_iio_device_register(dev, indio_dev);
108 }
109
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 66313 bytes --]
^ permalink raw reply
* Re: [PATCH] dt-bindings: hwmon: Add binding for pxe1610
From: Guenter Roeck @ 2019-07-22 20:06 UTC (permalink / raw)
To: Vijay Khemka
Cc: Jean Delvare, Rob Herring, Mark Rutland, Joel Stanley,
Andrew Jeffery, linux-hwmon, devicetree, linux-kernel,
linux-arm-kernel, linux-aspeed, openbmc @ lists . ozlabs . org,
sdasari
In-Reply-To: <20190722192451.1947348-2-vijaykhemka@fb.com>
On Mon, Jul 22, 2019 at 12:24:48PM -0700, Vijay Khemka wrote:
> Added new DT binding document for Infineon PXE1610 devices.
>
> Signed-off-by: Vijay Khemka <vijaykhemka@fb.com>
> ---
> .../devicetree/bindings/hwmon/pxe1610.txt | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/hwmon/pxe1610.txt
>
> diff --git a/Documentation/devicetree/bindings/hwmon/pxe1610.txt b/Documentation/devicetree/bindings/hwmon/pxe1610.txt
> new file mode 100644
> index 000000000000..635daf4955db
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/hwmon/pxe1610.txt
> @@ -0,0 +1,15 @@
> +pxe1610 properties
> +
> +Required properties:
> +- compatible: Must be one of the following:
> + - "infineon,pxe1610" for pxe1610
> + - "infineon,pxe1110" for pxe1610
> + - "infineon,pxm1310" for pxm1310
> +- reg: I2C address
> +
> +Example:
> +
> +vr@48 {
> + compatible = "infineon,pxe1610";
> + reg = <0x48>;
> +};
Wouldn't it be better to add this to
./Documentation/devicetree/bindings/trivial-devices.txt ?
Thanks,
Guenter
^ permalink raw reply
* Re: [PATCH v9 04/18] kunit: test: add kunit_stream a std::stream like logger
From: Stephen Boyd @ 2019-07-22 20:03 UTC (permalink / raw)
To: Brendan Higgins
Cc: Petr Mladek, open list:DOCUMENTATION, Peter Zijlstra,
Amir Goldstein, dri-devel, Sasha Levin, Masahiro Yamada,
Michael Ellerman, open list:KERNEL SELFTEST FRAMEWORK, shuah,
Rob Herring, linux-nvdimm, Frank Rowand, Knut Omang,
Kieran Bingham, wfg-VuQAYsv1563Yd54FQh9/CA, Joel Stanley,
David Rientjes, Jeff Dike, Dan Carpenter, devicetree,
linux-kbuild
In-Reply-To: <20190719000834.GA3228-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
Quoting Brendan Higgins (2019-07-18 17:08:34)
> On Thu, Jul 18, 2019 at 12:22:33PM -0700, Brendan Higgins wrote:
>
> I started poking around with your suggestion while we are waiting. A
> couple early observations:
>
> 1) It is actually easier to do than I previously thought and will probably
> help with getting more of the planned TAP output stuff working.
>
> That being said, this is still a pretty substantial undertaking and
> will likely take *at least* a week to implement and properly review.
> Assuming everything goes extremely well (no unexpected issues on my
> end, very responsive reviewers, etc).
>
> 2) It *will* eliminate the need for kunit_stream.
>
> 3) ...but, it *will not* eliminate the need for string_stream.
>
> Based on my early observations, I do think it is worth doing, but I
> don't think it is worth trying to make it in this patchset (unless I
> have already missed the window, or it is going to be open for a while):
The merge window is over. Typically code needs to be settled a few weeks
before it opens (i.e. around -rc4 or -rc5) for most maintainers to pick
up patches for the next merge window.
> I do think it will make things much cleaner, but I don't think it will
> achieve your desired goal of getting rid of an unstructured
> {kunit|string}_stream style interface; it just adds a layer on top of it
> that makes it harder to misuse.
Ok.
>
> I attached a patch of what I have so far at the end of this email so you
> can see what I am talking about. And of course, if you agree with my
> assessment, so we can start working on it as a future patch.
>
> A couple things in regard to the patch I attached:
>
> 1) I wrote it pretty quickly so there are almost definitely mistakes.
> You should consider it RFC. I did verify it compiles though.
>
> 2) Also, I did use kunit_stream in writing it: all occurences should be
> pretty easy to replace with string_stream; nevertheless, the reason
> for this is just to make it easier to play with the current APIs. I
> wanted to have something working before I went through a big tedious
> refactoring. So sorry if it causes any confusion.
>
> 3) I also based the patch on all the KUnit patches I have queued up
> (includes things like mocking and such) since I want to see how this
> serialization thing will work with mocks and matchers and things like
> that.
Great!
>
> From 53d475d3d56afcf92b452c6d347dbedfa1a17d34 Mon Sep 17 00:00:00 2001
> From: Brendan Higgins <brendanhiggins-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
> Date: Thu, 18 Jul 2019 16:08:52 -0700
> Subject: [PATCH v1] DO NOT MERGE: started playing around with the
> serialization api
>
> ---
> include/kunit/assert.h | 130 ++++++++++++++++++++++++++++++
> include/kunit/mock.h | 4 +
> kunit/Makefile | 3 +-
> kunit/assert.c | 179 +++++++++++++++++++++++++++++++++++++++++
> kunit/mock.c | 6 +-
> 5 files changed, 318 insertions(+), 4 deletions(-)
> create mode 100644 include/kunit/assert.h
> create mode 100644 kunit/assert.c
>
> diff --git a/include/kunit/assert.h b/include/kunit/assert.h
> new file mode 100644
> index 0000000000000..e054fdff4642f
> --- /dev/null
> +++ b/include/kunit/assert.h
> @@ -0,0 +1,130 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Assertion and expectation serialization API.
> + *
> + * Copyright (C) 2019, Google LLC.
> + * Author: Brendan Higgins <brendanhiggins-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
> + */
> +
> +#ifndef _KUNIT_ASSERT_H
> +#define _KUNIT_ASSERT_H
> +
> +#include <kunit/test.h>
> +#include <kunit/mock.h>
> +
> +enum kunit_assert_type {
> + KUNIT_ASSERTION,
> + KUNIT_EXPECTATION,
> +};
> +
> +struct kunit_assert {
> + enum kunit_assert_type type;
> + const char *line;
> + const char *file;
> + struct va_format message;
> + void (*format)(struct kunit_assert *assert,
> + struct kunit_stream *stream);
Would passing in the test help too?
> +};
> +
> +void kunit_base_assert_format(struct kunit_assert *assert,
> + struct kunit_stream *stream);
> +
> +void kunit_assert_print_msg(struct kunit_assert *assert,
> + struct kunit_stream *stream);
> +
> +struct kunit_unary_assert {
> + struct kunit_assert assert;
> + const char *condition;
> + bool expected_true;
> +};
> +
> +void kunit_unary_assert_format(struct kunit_assert *assert,
> + struct kunit_stream *stream);
> +
> +struct kunit_ptr_not_err_assert {
> + struct kunit_assert assert;
> + const char *text;
> + void *value;
> +};
> +
> +void kunit_ptr_not_err_assert_format(struct kunit_assert *assert,
> + struct kunit_stream *stream);
> +
> +struct kunit_binary_assert {
> + struct kunit_assert assert;
> + const char *operation;
> + const char *left_text;
> + long long left_value;
> + const char *right_text;
> + long long right_value;
> +};
> +
> +void kunit_binary_assert_format(struct kunit_assert *assert,
> + struct kunit_stream *stream);
> +
> +struct kunit_binary_ptr_assert {
> + struct kunit_assert assert;
> + const char *operation;
> + const char *left_text;
> + void *left_value;
> + const char *right_text;
> + void *right_value;
> +};
> +
> +void kunit_binary_ptr_assert_format(struct kunit_assert *assert,
> + struct kunit_stream *stream);
> +
> +struct kunit_binary_str_assert {
> + struct kunit_assert assert;
> + const char *operation;
> + const char *left_text;
> + const char *left_value;
> + const char *right_text;
> + const char *right_value;
> +};
> +
> +void kunit_binary_str_assert_format(struct kunit_assert *assert,
> + struct kunit_stream *stream);
> +
> +struct kunit_mock_assert {
> + struct kunit_assert assert;
> +};
> +
> +struct kunit_mock_no_expectations {
> + struct kunit_mock_assert assert;
> +};
What's the purpose of making a wrapper struct with no other members?
Just to make a different struct for some sort of type checking? I guess
it's OK but I don't think it will be very useful in practice.
> +
> +struct kunit_mock_declaration {
> + const char *function_name;
> + const char **type_names;
> + const void **params;
> + int len;
> +};
> +
> +void kunit_mock_declaration_format(struct kunit_mock_declaration *declaration,
> + struct kunit_stream *stream);
> +
> +struct kunit_matcher_result {
> + struct kunit_assert assert;
> +};
> +
> +struct kunit_mock_failed_match {
> + struct list_head node;
> + const char *expectation_text;
> + struct kunit_matcher_result *matcher_list;
Minor nitpick: this code could use some const sprinkling.
> + size_t matcher_list_len;
> +};
> +
> +void kunit_mock_failed_match_format(struct kunit_mock_failed_match *match,
> + struct kunit_stream *stream);
> +
> +struct kunit_mock_no_match {
> + struct kunit_mock_assert assert;
> + struct kunit_mock_declaration declaration;
> + struct list_head failed_match_list;
> +};
> +
> +void kunit_mock_no_match_format(struct kunit_assert *assert,
> + struct kunit_stream *stream);
> +
> +#endif /* _KUNIT_ASSERT_H */
> diff --git a/kunit/assert.c b/kunit/assert.c
> new file mode 100644
> index 0000000000000..75bb6922a994e
> --- /dev/null
> +++ b/kunit/assert.c
> @@ -0,0 +1,179 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Assertion and expectation serialization API.
> + *
> + * Copyright (C) 2019, Google LLC.
> + * Author: Brendan Higgins <brendanhiggins-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
> + */
> +#include <kunit/assert.h>
> +
> +void kunit_base_assert_format(struct kunit_assert *assert,
> + struct kunit_stream *stream)
> +{
> + const char *expect_or_assert;
> +
> + if (assert->type == KUNIT_EXPECTATION)
> + expect_or_assert = "EXPECTATION";
> + else
> + expect_or_assert = "ASSERTION";
Make this is a switch statement so we can have the compiler complain if
an enum is missing.
> +
> + kunit_stream_add(stream, "%s FAILED at %s:%s\n",
> + expect_or_assert, assert->file, assert->line);
> +}
> +
> +void kunit_assert_print_msg(struct kunit_assert *assert,
> + struct kunit_stream *stream)
> +{
> + if (assert->message.fmt)
> + kunit_stream_add(stream, "\n%pV", &assert->message);
> +}
> +
[...]
> +
> +void kunit_mock_failed_match_format(struct kunit_mock_failed_match *match,
> + struct kunit_stream *stream)
> +{
> + struct kunit_matcher_result *result;
> + size_t i;
> +
> + kunit_stream_add(stream,
> + "Tried expectation: %s, but\n",
> + match->expectation_text);
> + for (i = 0; i < match->matcher_list_len; i++) {
> + result = &match->matcher_list[i];
> + kunit_stream_add(stream, "\t");
> + result->assert.format(&result->assert, stream);
> + kunit_stream_add(stream, "\n");
> + }
What's the calling context of the assertions and expectations? I still
don't like the fact that string stream needs to allocate buffers and
throw them into a list somewhere because the calling context matters
there. I'd prefer we just wrote directly to the console/log via printk
instead. That way things are simple because we use the existing
buffering path of printk, but maybe there's some benefit to the string
stream that I don't see? Right now it looks like it builds a string and
then dumps it to printk so I'm sort of lost what the benefit is over
just writing directly with printk.
Maybe it's this part that you wrote up above?
> > Nevertheless, I think the debate over the usefulness of the
> > string_stream and kunit_stream are separate topics. Even if we made
> > kunit_stream more structured, I am pretty sure I would want to use
> > string_stream or some variation for constructing the message.
Why do we need string_stream to construct the message? Can't we just
print it as we process it?
^ permalink raw reply
* Re: [PATCH 2/3] macb: Update compatibility string for SiFive FU540-C000
From: Paul Walmsley @ 2019-07-22 20:02 UTC (permalink / raw)
To: Yash Shah
Cc: davem, robh+dt, netdev, devicetree, linux-kernel, linux-riscv,
mark.rutland, palmer, aou, nicolas.ferre, ynezz, sachin.ghadi
In-Reply-To: <1563534631-15897-2-git-send-email-yash.shah@sifive.com>
On Fri, 19 Jul 2019, Yash Shah wrote:
> Update the compatibility string for SiFive FU540-C000 as per the new
> string updated in the binding doc.
> Reference: https://lkml.org/lkml/2019/7/17/200
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
Reviewed-by: Paul Walmsley <paul.walmsley@sifive.com>
- Paul
^ permalink raw reply
* Re: [PATCH 1/3] macb: bindings doc: update sifive fu540-c000 binding
From: Paul Walmsley @ 2019-07-22 19:59 UTC (permalink / raw)
To: Yash Shah
Cc: davem, robh+dt, netdev, devicetree, linux-kernel, linux-riscv,
mark.rutland, palmer, aou, nicolas.ferre, ynezz, sachin.ghadi
In-Reply-To: <1563534631-15897-1-git-send-email-yash.shah@sifive.com>
On Fri, 19 Jul 2019, Yash Shah wrote:
> As per the discussion with Nicolas Ferre, rename the compatible property
> to a more appropriate and specific string.
> LINK: https://lkml.org/lkml/2019/7/17/200
>
> Signed-off-by: Yash Shah <yash.shah@sifive.com>
Reviewed-by: Paul Walmsley <paul.walmsley@sifive.com>
- Paul
^ permalink raw reply
* [PATCH 5/5] ARM: dts: armada385-wd-mcex2u: Add DTS file for WD My Cloud EX2 Ultra
From: Evgeny Kolesnikov @ 2019-07-22 19:53 UTC (permalink / raw)
Cc: Evgeny Kolesnikov, Sebastian Reichel, Rob Herring, Mark Rutland,
Jason Cooper, Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
linux-pm, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <cover.1563822216.git.evgenyz@gmail.com>
Add the DTS file to describe the Western Digital My Cloud EX2 Ultra NAS.
Signed-off-by: Evgeny Kolesnikov <evgenyz@gmail.com>
---
arch/arm/boot/dts/armada-385-wd-mcex2u.dts | 313 +++++++++++++++++++++
1 file changed, 313 insertions(+)
create mode 100644 arch/arm/boot/dts/armada-385-wd-mcex2u.dts
diff --git a/arch/arm/boot/dts/armada-385-wd-mcex2u.dts b/arch/arm/boot/dts/armada-385-wd-mcex2u.dts
new file mode 100644
index 000000000000..018e66adbb93
--- /dev/null
+++ b/arch/arm/boot/dts/armada-385-wd-mcex2u.dts
@@ -0,0 +1,313 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Device Tree file for Western Digital My Cloud EX2 Ultra
+ * (BVBZ/Ranger Peak)
+ *
+ * Copyright (C) 2019 Evgeny Kolesnikov <evgenyz@gmail.com>
+ *
+ * Based on the code from:
+ *
+ * Copyright (C) 2016 Martin Mueller <mm@sig21.net>
+ * Copyright (C) 2013 Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Copyright (C) 2013 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-385.dtsi"
+
+/ {
+ model = "WD My Cloud EX2 Ultra (BVBZ/Ranger Peak)";
+ compatible = "wd,mcex2u", "marvell,armada385", "marvell,armada380";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ bootargs = "console=ttyS0,115200";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x40000000>; /* 1024 MB */
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
+ MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
+ MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
+
+ internal-regs {
+ timer@c200 {
+ status = "disabled";
+ };
+
+ i2c0: i2c@11000 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ i2c1: i2c@11100 {
+ status = "okay";
+ clock-frequency = <100000>;
+ };
+
+ serial@12000 {
+ status = "okay";
+ };
+
+ /* Connected to Welltrend 6703F-OG240WT MCU
+ * which controls power, fan and other things
+ */
+ serial@12100 {
+ status = "okay";
+ };
+
+ poweroff@12100 {
+ compatible = "uart-poweroff";
+ reg = <0x12100 0x100>;
+ clocks = <&coreclk 0>;
+ baud = <19200>;
+ cmd = [fa 03 03 01 00 00 fb];
+ status = "okay";
+ };
+
+ restart@12100 {
+ compatible = "uart-restart";
+ reg = <0x12100 0x100>;
+ clocks = <&coreclk 0>;
+ baud = <19200>;
+ cmd = [fa 03 03 02 00 00 fb];
+ override;
+ status = "okay";
+ };
+
+ pinctrl@18000 {
+ uart1_pins: uart-pins-1 {
+ marvell,pins = "mpp19";
+ marvell,function = "ua1";
+ };
+
+ xhci0_vbus_pins: xhci0-vbus-pins {
+ marvell,pins = "mpp26";
+ marvell,function = "gpio";
+ };
+
+ xhci1_vbus_pins: xhci1-vbus-pins {
+ marvell,pins = "mpp27";
+ marvell,function = "gpio";
+ };
+
+ sata0_pins: sata-pins-0 {
+ marvell,pins = "mpp55";
+ marvell,function = "sata0";
+ };
+
+ sata1_pins: sata-pins-1 {
+ marvell,pins = "mpp56";
+ marvell,function = "sata1";
+ };
+
+ sata_leds: sata-leds {
+ marvell,pins = "mpp43", "mpp52",
+ "mpp53", "mpp54";
+ marvell,function = "gpio";
+ };
+
+ btn_pins: btn-pins {
+ marvell,pins = "mpp50";
+ marvell,function = "gpio";
+ };
+ };
+
+ ethernet@34000 {
+ phy = <&phy0>;
+ phy-mode = "sgmii";
+ buffer-manager = <&bm>;
+ bm,pool-long = <0>;
+ bm,pool-short = <1>;
+ status = "okay";
+ };
+
+ usb@58000 {
+ status = "okay";
+ };
+
+ mdio@72004 {
+ phy0: ethernet-phy@0 {
+ /* Init ETH LEDs */
+ marvell,reg-init = <3 16 0 0x101e>;
+ reg = <0>;
+ };
+ };
+
+ crypto@9d000 {
+ status = "okay";
+ };
+
+ rtc@a3800 {
+ status = "okay";
+ };
+
+ sata@a8000 {
+ status = "okay";
+ };
+
+ bm@c8000 {
+ status = "okay";
+ };
+
+ nand-controller@d0000 {
+ status = "okay";
+
+ nand: nand@0 {
+ reg = <0>;
+ label = "pxa3xx_nand-0";
+ marvell,nand-keep-config;
+ nand-rb = <0>;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0000000 {
+ label = "U-Boot";
+ reg = <0x00000000 0x00500000>;
+ read-only;
+ };
+ partition@0500000 {
+ label = "kernel";
+ reg = <0x00500000 0x00500000>;
+ };
+ partition@0a00000 {
+ label = "uRamdisk";
+ reg = <0x00a00000 0x00500000>;
+ read-only;
+ };
+ partition@0f00000 {
+ label = "ubi";
+ reg = <0x00f00000 0x0b900000>;
+ };
+ partition@c800000 {
+ label = "Recovery";
+ reg = <0x0c800000 0x00f00000>;
+ read-only;
+ };
+ partition@d700000 {
+ label = "config";
+ reg = <0x0d700000 0x01400000>;
+ };
+ partition@eb00000 {
+ label = "reserve1";
+ reg = <0x0eb00000 0x00a00000>;
+ read-only;
+ };
+ partition@f500000 {
+ label = "reserve2";
+ reg = <0x0f500000 0x00a00000>;
+ read-only;
+ };
+ };
+ };
+ };
+
+ sdhci@d8000 {
+ status = "disabled";
+ };
+
+ usb3@f0000 {
+ usb-phy = <&usb3_0_phy>;
+ status = "okay";
+ };
+
+ usb3@f8000 {
+ usb-phy = <&usb3_1_phy>;
+ status = "okay";
+ };
+ };
+
+ bm-bppi {
+ status = "okay";
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sata_leds>;
+
+ sata1-red-led {
+ label = "wdmcex2u:red:hdd1";
+ gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+ };
+ sata2-red-led {
+ label = "wdmcex2u:red:hdd2";
+ gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
+ };
+ sata1-blue-led {
+ label = "wdmcex2u:blue:hdd1";
+ gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+ sata2-blue-led {
+ label = "wdmcex2u:blue:hdd2";
+ gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&btn_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
+ debounce-interval = <60>;
+ wakeup-source;
+ };
+ };
+
+ usb3_0_phy: usb3_0_phy {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <®_usb3_0_vbus>;
+ };
+
+ usb3_1_phy: usb3_1_phy {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <®_usb3_1_vbus>;
+ };
+
+ reg_usb3_0_vbus: usb3-vbus0 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb3-vbus0";
+ pinctrl-names = "default";
+ pinctrl-0 = <&xhci0_vbus_pins>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_usb3_1_vbus: usb3-vbus1 {
+ compatible = "regulator-fixed";
+ regulator-name = "usb3-vbus1";
+ pinctrl-names = "default";
+ pinctrl-0 = <&xhci1_vbus_pins>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ regulator-always-on;
+ gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>;
+ };
+};
--
2.21.0
^ permalink raw reply related
* [PATCH 4/5] power/reset: Add a restart driver for UART-based PM MCUs
From: Evgeny Kolesnikov @ 2019-07-22 19:53 UTC (permalink / raw)
Cc: Evgeny Kolesnikov, Sebastian Reichel, Rob Herring, Mark Rutland,
Jason Cooper, Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
linux-pm, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <cover.1563822216.git.evgenyz@gmail.com>
This adds the restart driver for power managing
micro controller units that are connected to a board
via the UART interface.
Signed-off-by: Evgeny Kolesnikov <evgenyz@gmail.com>
---
drivers/power/reset/Kconfig | 7 +
drivers/power/reset/Makefile | 1 +
drivers/power/reset/uart-restart.c | 204 +++++++++++++++++++++++++++++
3 files changed, 212 insertions(+)
create mode 100644 drivers/power/reset/uart-restart.c
diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index 02fdf45e3988..4b187af1fba6 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -223,6 +223,13 @@ config POWER_RESET_UART_POWEROFF
Power off support for boards with UART-based PM MCU
such as WD My Cloud NAS, QNAP Turbo NAS, Synology devices.
+config POWER_RESET_UART
+ tristate "UART-based PM MCU restart driver"
+ depends on OF_GPIO
+ help
+ Reboot support for boards with UART-based PM MCU
+ such as WD My Cloud NAS, QNAP Turbo NAS, Synology devices.
+
config POWER_RESET_ZX
tristate "ZTE SoCs reset driver"
depends on ARCH_ZX || COMPILE_TEST
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
index efe8f25f463d..fa8a936d7a1a 100644
--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_POWER_RESET_SYSCON) += syscon-reboot.o
obj-$(CONFIG_POWER_RESET_SYSCON_POWEROFF) += syscon-poweroff.o
obj-$(CONFIG_POWER_RESET_RMOBILE) += rmobile-reset.o
obj-$(CONFIG_POWER_RESET_UART_POWEROFF) += uart-poweroff.o
+obj-$(CONFIG_POWER_RESET_UART) += uart-restart.o
obj-$(CONFIG_POWER_RESET_ZX) += zx-reboot.o
obj-$(CONFIG_REBOOT_MODE) += reboot-mode.o
obj-$(CONFIG_SYSCON_REBOOT_MODE) += syscon-reboot-mode.o
diff --git a/drivers/power/reset/uart-restart.c b/drivers/power/reset/uart-restart.c
new file mode 100644
index 000000000000..be4dcbbb826e
--- /dev/null
+++ b/drivers/power/reset/uart-restart.c
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Restart for boards with UART-based PM MCUs
+ * such as WD My Cloud NAS, QNAP Turbo NAS, Synology devices.
+ *
+ * Copyright (C) 2019 Evgeny Kolesnikov <evgenyz@gmail.com>
+ *
+ * Based on the code from:
+ *
+ * Copyright (C) 2016 Martin Mueller <mm@sig21.net>
+ * Copyright (C) 2012 Andrew Lunn <andrew@lunn.ch>
+ * Copyright (C) 2009 Martin Michlmayr <tbm@cyrius.com>
+ * Copyright (C) 2008 Byron Bradley <byron.bbradley@gmail.com>
+ *
+ */
+
+#include <linux/reboot.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/serial_reg.h>
+#include <linux/kallsyms.h>
+#include <linux/of.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#ifdef CONFIG_ARM
+#include <asm/system_misc.h>
+#endif
+
+#define UART_REG(b, x) (b + ((UART_##x) << 2))
+
+
+struct uart_restart {
+ struct notifier_block restart_handler;
+ const u8 *cmd;
+ int cmd_len;
+ void __iomem *base;
+ unsigned int divisor;
+ u32 byte_delay_ms;
+ u32 timeout_ms;
+ void *pm_restart_org;
+};
+
+static int uart_restart_notify(struct notifier_block *this,
+ unsigned long mode, void *cmd)
+{
+ struct uart_restart *uart_restart =
+ container_of(this, struct uart_restart, restart_handler);
+ int i;
+
+ /* Hijack UART and reset into sane state */
+ writel(0x83, UART_REG(uart_restart->base, LCR));
+ writel(uart_restart->divisor & 0xFF, UART_REG(uart_restart->base, DLL));
+ writel((uart_restart->divisor >> 8) & 0xFF, UART_REG(uart_restart->base, DLM));
+ writel(0x03, UART_REG(uart_restart->base, LCR));
+ writel(0x00, UART_REG(uart_restart->base, IER));
+ writel(0x00, UART_REG(uart_restart->base, FCR));
+ writel(0x00, UART_REG(uart_restart->base, MCR));
+
+ /* Send the command */
+ for (i = 0; i < uart_restart->cmd_len; i++) {
+ writel(uart_restart->cmd[i], UART_REG(uart_restart->base, TX));
+ mdelay(uart_restart->byte_delay_ms);
+ }
+ mdelay(uart_restart->timeout_ms);
+ WARN_ON(1);
+
+ return NOTIFY_DONE;
+}
+
+static int uart_restart_probe(struct platform_device *pdev)
+{
+ struct uart_restart *uart_restart;
+ struct resource *res;
+ void __iomem *base;
+ struct clk *clk;
+ u32 baud;
+ bool override;
+ int err;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "Missing resource\n");
+ return -EINVAL;
+ }
+
+ base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ if (!base) {
+ dev_err(&pdev->dev, "Unable to map resource\n");
+ return -EINVAL;
+ }
+
+ /* We need to know tclk in order to calculate the UART divisor */
+ clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(clk)) {
+ dev_err(&pdev->dev, "Clk missing\n");
+ return PTR_ERR(clk);
+ }
+
+ uart_restart = devm_kzalloc(&pdev->dev, sizeof(*uart_restart),
+ GFP_KERNEL);
+ if (!uart_restart)
+ return -ENOMEM;
+
+ uart_restart->cmd = of_get_property(pdev->dev.of_node, "cmd",
+ &uart_restart->cmd_len);
+ if (uart_restart->cmd == NULL || uart_restart->cmd_len < 1) {
+ dev_err(&pdev->dev, "Cmd is missing or empty\n");
+ return -EINVAL;
+ }
+
+ of_property_read_u32(pdev->dev.of_node, "baud", &baud);
+ if (baud < 75 || baud > 460800) {
+ dev_err(&pdev->dev, "Baud rate is missing or invalid\n");
+ return -EINVAL;
+ }
+
+ uart_restart->restart_handler.notifier_call = uart_restart_notify;
+ uart_restart->restart_handler.priority = 129;
+ uart_restart->base = base;
+ uart_restart->divisor =
+ ((clk_get_rate(clk) + (8 * baud)) / (16 * baud));
+ uart_restart->byte_delay_ms = 5;
+ uart_restart->timeout_ms = 1000;
+ of_property_read_u32(pdev->dev.of_node, "byte-delay",
+ &uart_restart->byte_delay_ms);
+ of_property_read_u32(pdev->dev.of_node, "timeout",
+ &uart_restart->timeout_ms);
+
+ override = of_property_read_bool(pdev->dev.of_node, "override");
+
+ if (override)
+ uart_restart->restart_handler.priority = 192;
+
+ platform_set_drvdata(pdev, uart_restart);
+
+#ifdef CONFIG_ARM
+ char symname[KSYM_NAME_LEN];
+
+ if (arm_pm_restart && !override) {
+ lookup_symbol_name((ulong)arm_pm_restart, symname);
+ dev_err(&pdev->dev,
+ "The arm_pm_restart is already claimed by %s (%p) and override is false",
+ symname, arm_pm_restart);
+ return -EBUSY;
+ }
+#endif
+
+ err = register_restart_handler(&uart_restart->restart_handler);
+ if (err) {
+ dev_err(&pdev->dev,
+ "Unable to register restart handler: %d\n", err);
+ return -ENODEV;
+ }
+
+#ifdef CONFIG_ARM
+ if (arm_pm_restart && override) {
+ uart_restart->pm_restart_org = arm_pm_restart;
+ arm_pm_restart = NULL;
+ }
+#endif
+
+ return 0;
+}
+
+static int uart_restart_remove(struct platform_device *pdev)
+{
+ struct uart_restart *uart_restart = platform_get_drvdata(pdev);
+ int err;
+
+ err = unregister_restart_handler(&uart_restart->restart_handler);
+ if (err) {
+ dev_err(&pdev->dev,
+ "Unable to unregister restart handler, %d\n", err);
+ return -ENODEV;
+ }
+
+#ifdef CONFIG_ARM
+ if (arm_pm_restart == NULL && uart_restart->pm_restart_org != NULL)
+ arm_pm_restart = uart_restart->pm_restart_org;
+#endif
+
+ return 0;
+}
+
+static const struct of_device_id of_uart_restart_match[] = {
+ { .compatible = "uart-restart", },
+ {},
+};
+
+static struct platform_driver uart_restart_driver = {
+ .probe = uart_restart_probe,
+ .remove = uart_restart_remove,
+ .driver = {
+ .name = "uart_restart",
+ .of_match_table = of_uart_restart_match,
+ },
+};
+module_platform_driver(uart_restart_driver);
+
+MODULE_AUTHOR("Evgeny Kolesnikov <evgenyz@gmail.com>");
+MODULE_DESCRIPTION("UART-based PM MCU restart driver");
+MODULE_LICENSE("GPL v2");
--
2.21.0
^ permalink raw reply related
* [PATCH 3/5] power/reset: Add a power off driver for UART-based PM MCUs
From: Evgeny Kolesnikov @ 2019-07-22 19:53 UTC (permalink / raw)
Cc: Evgeny Kolesnikov, Sebastian Reichel, Rob Herring, Mark Rutland,
Jason Cooper, Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
linux-pm, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <cover.1563822216.git.evgenyz@gmail.com>
This adds the poweroff driver for power managing
micro controller units that are connected to a board
via the UART interface.
Signed-off-by: Evgeny Kolesnikov <evgenyz@gmail.com>
---
drivers/power/reset/Kconfig | 7 ++
drivers/power/reset/Makefile | 1 +
drivers/power/reset/uart-poweroff.c | 155 ++++++++++++++++++++++++++++
3 files changed, 163 insertions(+)
create mode 100644 drivers/power/reset/uart-poweroff.c
diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index a564237278ff..02fdf45e3988 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -216,6 +216,13 @@ config POWER_RESET_RMOBILE
help
Reboot support for Renesas R-Mobile and SH-Mobile SoCs.
+config POWER_RESET_UART_POWEROFF
+ tristate "UART-based PM MCU power off driver"
+ depends on OF_GPIO
+ help
+ Power off support for boards with UART-based PM MCU
+ such as WD My Cloud NAS, QNAP Turbo NAS, Synology devices.
+
config POWER_RESET_ZX
tristate "ZTE SoCs reset driver"
depends on ARCH_ZX || COMPILE_TEST
diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile
index 85da3198e4e0..efe8f25f463d 100644
--- a/drivers/power/reset/Makefile
+++ b/drivers/power/reset/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_POWER_RESET_KEYSTONE) += keystone-reset.o
obj-$(CONFIG_POWER_RESET_SYSCON) += syscon-reboot.o
obj-$(CONFIG_POWER_RESET_SYSCON_POWEROFF) += syscon-poweroff.o
obj-$(CONFIG_POWER_RESET_RMOBILE) += rmobile-reset.o
+obj-$(CONFIG_POWER_RESET_UART_POWEROFF) += uart-poweroff.o
obj-$(CONFIG_POWER_RESET_ZX) += zx-reboot.o
obj-$(CONFIG_REBOOT_MODE) += reboot-mode.o
obj-$(CONFIG_SYSCON_REBOOT_MODE) += syscon-reboot-mode.o
diff --git a/drivers/power/reset/uart-poweroff.c b/drivers/power/reset/uart-poweroff.c
new file mode 100644
index 000000000000..8122a6b306d7
--- /dev/null
+++ b/drivers/power/reset/uart-poweroff.c
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Power off for boards with UART-based PM MCUs
+ * such as WD My Cloud NAS, QNAP Turbo NAS, Synology devices.
+ *
+ * Copyright (C) 2019 Evgeny Kolesnikov <evgenyz@gmail.com>
+ *
+ * Based on the code from:
+ *
+ * Copyright (C) 2016 Martin Mueller <mm@sig21.net>
+ * Copyright (C) 2012 Andrew Lunn <andrew@lunn.ch>
+ * Copyright (C) 2009 Martin Michlmayr <tbm@cyrius.com>
+ * Copyright (C) 2008 Byron Bradley <byron.bbradley@gmail.com>
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/serial_reg.h>
+#include <linux/kallsyms.h>
+#include <linux/of.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+
+#define UART_REG(b, x) (b + ((UART_##x) << 2))
+
+struct uart_poweroff {
+ const u8 *cmd;
+ int cmd_len;
+ void __iomem *base;
+ unsigned int divisor;
+ u32 byte_delay_ms;
+ u32 timeout_ms;
+};
+
+static void *pm_power_off_org;
+static struct uart_poweroff uart_poweroff;
+
+static void uart_power_off(void)
+{
+ int i;
+
+ /* Hijack UART and reset into sane state */
+ writel(0x83, UART_REG(uart_poweroff.base, LCR));
+ writel(uart_poweroff.divisor & 0xFF, UART_REG(uart_poweroff.base, DLL));
+ writel((uart_poweroff.divisor >> 8) & 0xFF, UART_REG(uart_poweroff.base, DLM));
+ writel(0x03, UART_REG(uart_poweroff.base, LCR));
+ writel(0x00, UART_REG(uart_poweroff.base, IER));
+ writel(0x00, UART_REG(uart_poweroff.base, FCR));
+ writel(0x00, UART_REG(uart_poweroff.base, MCR));
+
+ /* Send the command */
+ for (i = 0; i < uart_poweroff.cmd_len; i++) {
+ writel(uart_poweroff.cmd[i], UART_REG(uart_poweroff.base, TX));
+ mdelay(uart_poweroff.byte_delay_ms);
+ }
+
+ mdelay(uart_poweroff.timeout_ms);
+ WARN_ON(1);
+}
+
+static int uart_poweroff_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ static void __iomem *base;
+ struct clk *clk;
+ u32 baud;
+ bool override;
+ char symname[KSYM_NAME_LEN];
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "Missing resource\n");
+ return -EINVAL;
+ }
+
+ base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+ if (!base) {
+ dev_err(&pdev->dev, "Unable to map resource\n");
+ return -EINVAL;
+ }
+
+ /* We need to know tclk in order to calculate the UART divisor */
+ clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(clk)) {
+ dev_err(&pdev->dev, "Clk missing\n");
+ return PTR_ERR(clk);
+ }
+
+ uart_poweroff.cmd = of_get_property(pdev->dev.of_node, "cmd",
+ &uart_poweroff.cmd_len);
+ if (uart_poweroff.cmd == NULL || uart_poweroff.cmd_len < 1) {
+ dev_err(&pdev->dev, "Cmd is missing or empty\n");
+ return -EINVAL;
+ }
+
+ of_property_read_u32(pdev->dev.of_node, "baud", &baud);
+ if (baud < 75 || baud > 460800) {
+ dev_err(&pdev->dev, "Baud rate is missing or invalid\n");
+ return -EINVAL;
+ }
+
+ uart_poweroff.base = base;
+ uart_poweroff.divisor =
+ ((clk_get_rate(clk) + (8 * baud)) / (16 * baud));
+ uart_poweroff.byte_delay_ms = 5;
+ uart_poweroff.timeout_ms = 1000;
+ of_property_read_u32(pdev->dev.of_node, "byte-delay",
+ &uart_poweroff.byte_delay_ms);
+ of_property_read_u32(pdev->dev.of_node, "timeout",
+ &uart_poweroff.timeout_ms);
+
+ override = of_property_read_bool(pdev->dev.of_node, "override");
+
+ if (pm_power_off && !override) {
+ lookup_symbol_name((ulong)pm_power_off, symname);
+ dev_err(&pdev->dev,
+ "The pm_power_off is already claimed by %s (%p) and override is false",
+ symname, pm_power_off);
+ return -EBUSY;
+ }
+ pm_power_off_org = pm_power_off;
+ pm_power_off = uart_power_off;
+
+ return 0;
+}
+
+static int uart_poweroff_remove(struct platform_device *pdev)
+{
+ if (pm_power_off == uart_power_off)
+ pm_power_off = pm_power_off_org;
+
+ return 0;
+}
+
+static const struct of_device_id of_uart_poweroff_match[] = {
+ { .compatible = "uart-poweroff", },
+ {},
+};
+
+static struct platform_driver uart_poweroff_driver = {
+ .probe = uart_poweroff_probe,
+ .remove = uart_poweroff_remove,
+ .driver = {
+ .name = "uart_poweroff",
+ .of_match_table = of_uart_poweroff_match,
+ },
+};
+module_platform_driver(uart_poweroff_driver);
+
+MODULE_AUTHOR("Evgeny Kolesnikov <evgenyz@gmail.com>");
+MODULE_DESCRIPTION("UART-based PM MCU power off driver");
+MODULE_LICENSE("GPL v2");
--
2.21.0
^ permalink raw reply related
* [PATCH 2/5] power: reset: Add UART-based MCU restart DT bindings
From: Evgeny Kolesnikov @ 2019-07-22 19:53 UTC (permalink / raw)
Cc: Evgeny Kolesnikov, Sebastian Reichel, Rob Herring, Mark Rutland,
Jason Cooper, Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
linux-pm, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <cover.1563822216.git.evgenyz@gmail.com>
This adds device tree bindings of the restart driver
for power managing micro controller units that are connected
to a board via the UART interface.
Signed-off-by: Evgeny Kolesnikov <evgenyz@gmail.com>
---
.../bindings/power/reset/uart-restart.txt | 39 +++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/reset/uart-restart.txt
diff --git a/Documentation/devicetree/bindings/power/reset/uart-restart.txt b/Documentation/devicetree/bindings/power/reset/uart-restart.txt
new file mode 100644
index 000000000000..bf831d9bdff8
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/uart-restart.txt
@@ -0,0 +1,39 @@
+* UART-based PM MCU restart driver
+
+Some devices have a microcontroller controlling the main power
+supply. This microcontroller is connected to UART of the SoC.
+Sending a sequence of characters tells the MCU to reset the SoC
+and/or MCU itself.
+
+The length of the sequence, baud rate and the timeout to process
+the command may vary from device to device.
+
+This driver could be used for WD My Cloud (Marvell SoCs), QNAP
+(Kirkwood and Orion5x SoCs) and Synology NAS devices.
+
+Required properties:
+- compatible: Should be "uart-restart"
+- reg: Address and length of the register set for UART
+- clocks: The tclk clock
+- cmd: Array of bytes, the command to send to the MCU
+- baud: Baud rate [75..460800]
+
+Optional properties:
+- byte-delay: A delay after each byte of a command, could be useful
+ for sloppy MCUs [ms], default value is 5
+- timeout: A timeout to wait for the MCU to process the command [ms],
+ default value is 1000
+- override: Boolean flag that indicates if the driver should
+ prioritize itself over any existing restart driver,
+ default behaviour is not to interfere
+
+Example:
+ restart@12100 {
+ compatible = "uart-restart";
+ reg = <0x12100 0x100>;
+ clocks = <&coreclk 0>;
+ baud = <19200>;
+ cmd = [fa 03 03 02 00 00 fb];
+ override;
+ status = "okay";
+ };
--
2.21.0
^ permalink raw reply related
* [PATCH 1/5] power: reset: Add UART-based MCU poweroff DT bindings
From: Evgeny Kolesnikov @ 2019-07-22 19:53 UTC (permalink / raw)
Cc: Evgeny Kolesnikov, Sebastian Reichel, Rob Herring, Mark Rutland,
Jason Cooper, Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
linux-pm, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <cover.1563822216.git.evgenyz@gmail.com>
This adds device tree bindings of the poweroff driver
for power managing micro controller units that are connected
to a board via the UART interface.
Signed-off-by: Evgeny Kolesnikov <evgenyz@gmail.com>
---
.../bindings/power/reset/uart-poweroff.txt | 38 +++++++++++++++++++
1 file changed, 38 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/reset/uart-poweroff.txt
diff --git a/Documentation/devicetree/bindings/power/reset/uart-poweroff.txt b/Documentation/devicetree/bindings/power/reset/uart-poweroff.txt
new file mode 100644
index 000000000000..86d036271b51
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/uart-poweroff.txt
@@ -0,0 +1,38 @@
+* UART-based PM MCU power off driver
+
+Some devices have a microcontroller controlling the main power
+supply. This microcontroller is connected to UART of the SoC.
+Sending a sequence of characters tells the MCU to turn
+the power off.
+
+The length of the sequence, baud rate and the timeout to process
+the command may vary from device to device.
+
+This driver could be used for WD My Cloud (Marvell SoCs), QNAP
+(Kirkwood and Orion5x SoCs) and Synology NAS devices.
+
+Required properties:
+- compatible: Should be "uart-poweroff"
+- reg: Address and length of the register set for UART
+- clocks: The tclk clock
+- cmd: Array of bytes, the command to send to the MCU
+- baud: Baud rate [75..460800]
+
+Optional properties:
+- byte-delay: A delay after each byte of a command, could be useful
+ for sloppy MCUs [ms], default value is 5
+- timeout: A timeout to wait for the MCU to process the command [ms],
+ default value is 1000
+- override: Boolean flag that indicates if the driver should
+ prioritize itself over any existing power off driver,
+ default behaviour is not to interfere
+
+Example:
+ poweroff@12100 {
+ compatible = "uart-poweroff";
+ reg = <0x12100 0x100>;
+ clocks = <&coreclk 0>;
+ baud = <19200>;
+ cmd = [fa 03 03 01 00 00 fb];
+ status = "okay";
+ };
--
2.21.0
^ permalink raw reply related
* [PATCH 0/5] Add support for WD MyCloud EX2 Ultra (+ versatile UART-based restart/poweroff drivers)
From: Evgeny Kolesnikov @ 2019-07-22 19:53 UTC (permalink / raw)
Cc: Evgeny Kolesnikov, Sebastian Reichel, Rob Herring, Mark Rutland,
Jason Cooper, Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
linux-pm, devicetree, linux-kernel, linux-arm-kernel
This patchset consists of the DTS, which describes the WD MyCloud EX2 Ultra device,
'poweroff' and 'resert' drivers for power-managing MCUs connected to a board via UART
(these drivers are more versatile than qnap-poweroff and could be used as a substitude),
and DT bindings for these drivers.
The difference between uart-poweroff and qnap-poweroff is small, but important:
uart-poweroff is able to send to an MCU a command of arbitrary length, and the command
itself is defined in a DTS file for a specific device/board, thus making this driver
applicable to wider range of devices.
Evgeny Kolesnikov (5):
power: reset: Add UART-based MCU poweroff DT bindings
power: reset: Add UART-based MCU restart DT bindings
power/reset: Add a power off driver for UART-based PM MCUs
power/reset: Add a restart driver for UART-based PM MCUs
ARM: dts: armada385-wd-mcex2u: Add DTS file for WD My Cloud EX2 Ultra
.../bindings/power/reset/uart-poweroff.txt | 38 +++
.../bindings/power/reset/uart-restart.txt | 39 +++
arch/arm/boot/dts/armada-385-wd-mcex2u.dts | 313 ++++++++++++++++++
drivers/power/reset/Kconfig | 14 +
drivers/power/reset/Makefile | 2 +
drivers/power/reset/uart-poweroff.c | 155 +++++++++
drivers/power/reset/uart-restart.c | 204 ++++++++++++
7 files changed, 765 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/reset/uart-poweroff.txt
create mode 100644 Documentation/devicetree/bindings/power/reset/uart-restart.txt
create mode 100644 arch/arm/boot/dts/armada-385-wd-mcex2u.dts
create mode 100644 drivers/power/reset/uart-poweroff.c
create mode 100644 drivers/power/reset/uart-restart.c
--
2.21.0
^ permalink raw reply
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