* Re: [PATCH 5/5] arm64: dts: qcom: sdm845-cheza: remove macro from unit name
From: Bjorn Andersson @ 2019-07-23 5:41 UTC (permalink / raw)
To: Vinod Koul
Cc: Amit Kucheria, Andy Gross, linux-arm-msm, Rob Herring,
Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, LKML
In-Reply-To: <20190723051426.GZ12733@vkoul-mobl.Dlink>
On Mon 22 Jul 22:14 PDT 2019, Vinod Koul wrote:
> On 23-07-19, 10:38, Amit Kucheria wrote:
> > On Mon, Jul 22, 2019 at 6:06 PM Vinod Koul <vkoul@kernel.org> wrote:
> > >
> > > Unit name is supposed to be a number, using a macro with hex value is
> >
> > /s/name/address?
>
> Right, will fix.
>
> > > not recommended, so add the value in unit name.
> > >
> > > arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi:966.16-969.4: Warning (unit_address_format): /soc@0/spmi@c440000/pmic@0/adc@3100/adc-chan@0x4d: unit name should not have leading "0x"
> > > arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi:971.16-974.4: Warning (unit_address_format): /soc@0/spmi@c440000/pmic@0/adc@3100/adc-chan@0x4e: unit name should not have leading "0x"
> > > arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi:976.16-979.4: Warning (unit_address_format): /soc@0/spmi@c440000/pmic@0/adc@3100/adc-chan@0x4f: unit name should not have leading "0x"
> > > arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi:981.16-984.4: Warning (unit_address_format): /soc@0/spmi@c440000/pmic@0/adc@3100/adc-chan@0x50: unit name should not have leading "0x"
> > > arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi:986.16-989.4: Warning (unit_address_format): /soc@0/spmi@c440000/pmic@0/adc@3100/adc-chan@0x51: unit name should not have leading "0x"
> > >
> > > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > > ---
> > > arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 10 +++++-----
> > > 1 file changed, 5 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
> > > index 1ebbd568dfd7..9b27b8346ba1 100644
> > > --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
> > > @@ -963,27 +963,27 @@ ap_ts_i2c: &i2c14 {
> > > };
> > >
> > > &pm8998_adc {
> > > - adc-chan@ADC5_AMUX_THM1_100K_PU {
> > > + adc-chan@4d {
> > > reg = <ADC5_AMUX_THM1_100K_PU>;
When I read this define I instantly know which channel we're referring
to. The 4d above is simply there for syntactical purposes and needs only
to be cared about if the reg is ever changed.
So I like this form.
> >
> > I'm a little conflicted about this change. If we're replacing the
> > address with actual values, perhaps we should do that same for the reg
> > property to keep them in sync? Admittedly though, it is a bit easier
> > to read the macro name and figure out its meaning.
>
> Well this was how Bjorn suggested, am okay if we do in any
> other way. This fixes warning but keeps it bit readable too
>
> Other way would be to make defines decimal values instead of hex
>
While the ePAPRR states that the unit address must match the first reg,
dtc enforces that the unit address string matches "%x" of the reg.
Regards,
Bjorn
> Any better suggestions :)
>
> --
> ~Vinod
^ permalink raw reply
* Re: [PATCH 1/2] clk: imx8mq: set correct parent for usb ctrl clocks
From: Shawn Guo @ 2019-07-23 5:53 UTC (permalink / raw)
To: jun.li
Cc: mark.rutland, peter.chen, agx, ping.bai, Anson.Huang, ccaione,
sboyd, s.hauer, angus, linux-clk, abel.vesa, andrew.smirnov,
devicetree, robh+dt, linux-imx, kernel, festevam, mturquette,
linux-arm-kernel, l.stach
In-Reply-To: <20190710111917.6615-1-jun.li@nxp.com>
On Wed, Jul 10, 2019 at 07:19:16PM +0800, jun.li@nxp.com wrote:
> From: Li Jun <jun.li@nxp.com>
>
> Per latest imx8mq datasheet of CCM, the parent of usb1_ctrl_root_clk
> and usb2_ctrl_root_clk is usb_bus.
>
> Signed-off-by: Li Jun <jun.li@nxp.com>
Applied both, thanks.
^ permalink raw reply
* Re: [PATCH v5 04/13] media: rc: sunxi: Add RXSTA bits definition
From: Sean Young @ 2019-07-23 6:25 UTC (permalink / raw)
To: Clément Péron
Cc: Mauro Carvalho Chehab, Maxime Ripard, Rob Herring, Mark Rutland,
Chen-Yu Tsai, devicetree, linux-kernel, linux-sunxi,
linux-arm-kernel, linux-media
In-Reply-To: <20190715121244.2vrsw6qa4fgp72fn@gofer.mess.org>
Hi,
On Mon, Jul 15, 2019 at 01:12:45PM +0100, Sean Young wrote:
> On Sun, Jul 14, 2019 at 04:32:22PM +0200, Clément Péron wrote:
> > Hi Sean,
> >
> > You acked the whole v3 series but this patch has been introduced in v5
> > could you ack this one too?
>
> Acked-by: Sean Young <sean@mess.org>
So who's tree should this series go through? It seems mostly device tree.
Alternatively I'm happy to try it get merged via the media tree.
Thanks
Sean
^ permalink raw reply
* Re: [PATCH v2 0/2] arm64: dts: imx8mq: Add DT node for the Mixel MIPI D-PHY
From: Shawn Guo @ 2019-07-23 6:32 UTC (permalink / raw)
To: Guido Günther
Cc: Rob Herring, Mark Rutland, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, NXP Linux Team, Pavel Machek,
Angus Ainslie (Purism), Lucas Stach, Abel Vesa, Anson Huang,
Carlo Caione, Andrey Smirnov, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <cover.1563187253.git.agx@sigxcpu.org>
On Mon, Jul 15, 2019 at 12:43:04PM +0200, Guido G�nther wrote:
> Now that the driver is in linux-next as of 20190624 let's have a DT node
> for the i.MX8MQ and enable it on the Librem 5 devkit.
>
> Changes from v1:
> - Add Acked-by: form Angus, thanks!
You do not need to send a new version for just collecting ack/review
tags. I did that when applying v1.
Shawn
>
> Guido G�nther (2):
> arm64: dts: imx8mq: Add MIPI D-PHY
> arm64: dts: imx8mq-librem5: Enable MIPI D-PHY
>
> .../boot/dts/freescale/imx8mq-librem5-devkit.dts | 4 ++++
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 13 +++++++++++++
> 2 files changed, 17 insertions(+)
>
> --
> 2.20.1
>
^ permalink raw reply
* Re: [PATCH 2/3] ath10k: Move regulator config to driver private data
From: Govind Singh @ 2019-07-23 6:43 UTC (permalink / raw)
To: Bjorn Andersson; +Cc: linux-arm-msm, linux-wireless, ath10k, devicetree
In-Reply-To: <20190722235735.GA5828@builder>
On 2019-07-23 05:27, Bjorn Andersson wrote:
> On Tue 02 Jul 20:57 PDT 2019, Govind Singh wrote:
>
>> WCN3990 Regulator config is varying b/w different MSM platforms.
>> In order to have scalable config, move regulator config to driver
>> private data.
>>
>
> Regulators supplying clients with fixed voltage requirements should be
> specified in the board devicetree with these required voltage values,
> rather than in the driver. So the appropriate solution is not to add
> and adjust these values but rather to drop this code from the driver.
>
> I was about to send a patch that does this, because I have an SDM845
> device where the voltage constraints specified on board level does not
> meet the ranges specified here in the driver.
>
Thanks Bjorn for the feedback.
I will resend the qcs404 specific changes(dt) on top of your changes
once available.
> Regards,
> Bjorn
>
>> Signed-off-by: Govind Singh <govinds@codeaurora.org>
>> ---
>> drivers/net/wireless/ath/ath10k/snoc.c | 38
>> +++++++++++++++++++++-----
>> drivers/net/wireless/ath/ath10k/snoc.h | 23 +++++++++-------
>> 2 files changed, 44 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/net/wireless/ath/ath10k/snoc.c
>> b/drivers/net/wireless/ath/ath10k/snoc.c
>> index ca1186ec4129..bd7d97924fe0 100644
>> --- a/drivers/net/wireless/ath/ath10k/snoc.c
>> +++ b/drivers/net/wireless/ath/ath10k/snoc.c
>> @@ -36,13 +36,20 @@ static char *const ce_name[] = {
>> "WLAN_CE_11",
>> };
>>
>> -static struct ath10k_vreg_info vreg_cfg[] = {
>> +static struct ath10k_vreg_info sdm845_reg_cfg[] = {
>> {NULL, "vdd-0.8-cx-mx", 800000, 850000, 0, 0, false},
>> {NULL, "vdd-1.8-xo", 1800000, 1850000, 0, 0, false},
>> {NULL, "vdd-1.3-rfa", 1300000, 1350000, 0, 0, false},
>> {NULL, "vdd-3.3-ch0", 3300000, 3350000, 0, 0, false},
>> };
>>
>> +static struct ath10k_vreg_info qcs40x_reg_cfg[] = {
>> + {NULL, "vdd-0.8-cx-mx", 1224000, 1224000, 0, 0, false},
>> + {NULL, "vdd-1.8-xo", 1800000, 1850000, 0, 0, false},
>> + {NULL, "vdd-1.3-rfa", 1300000, 1350000, 0, 0, false},
>> + {NULL, "vdd-3.3-ch0", 3300000, 3350000, 0, 0, false},
>> +};
>> +
>> static struct ath10k_clk_info clk_cfg[] = {
>> {NULL, "cxo_ref_clk_pin", 0, false},
>> };
>> @@ -54,10 +61,20 @@ static void ath10k_snoc_htt_rx_cb(struct
>> ath10k_ce_pipe *ce_state);
>> static void ath10k_snoc_htt_htc_rx_cb(struct ath10k_ce_pipe
>> *ce_state);
>> static void ath10k_snoc_pktlog_rx_cb(struct ath10k_ce_pipe
>> *ce_state);
>>
>> -static const struct ath10k_snoc_drv_priv drv_priv = {
>> +static const struct ath10k_snoc_drv_priv sdm845_wcn39xx_drv_priv = {
>> + .hw_rev = ATH10K_HW_WCN3990,
>> + .dma_mask = DMA_BIT_MASK(35),
>> + .msa_size = 0x100000,
>> + .vreg_cfg = sdm845_reg_cfg,
>> + .vreg_count = ARRAY_SIZE(sdm845_reg_cfg),
>> +};
>> +
>> +static const struct ath10k_snoc_drv_priv qcs40x_wcn39xx_drv_priv = {
>> .hw_rev = ATH10K_HW_WCN3990,
>> .dma_mask = DMA_BIT_MASK(35),
>> .msa_size = 0x100000,
>> + .vreg_cfg = qcs40x_reg_cfg,
>> + .vreg_count = ARRAY_SIZE(qcs40x_reg_cfg),
>> };
>>
>> #define WCN3990_SRC_WR_IDX_OFFSET 0x3C
>> @@ -1465,7 +1482,7 @@ static int ath10k_snoc_vreg_on(struct ath10k
>> *ar)
>> int ret = 0;
>> int i;
>>
>> - for (i = 0; i < ARRAY_SIZE(vreg_cfg); i++) {
>> + for (i = 0; i < ar_snoc->vreg_count; i++) {
>> vreg_info = &ar_snoc->vreg[i];
>>
>> if (!vreg_info->reg)
>> @@ -1498,7 +1515,7 @@ static int ath10k_snoc_vreg_off(struct ath10k
>> *ar)
>> int ret = 0;
>> int i;
>>
>> - for (i = ARRAY_SIZE(vreg_cfg) - 1; i >= 0; i--) {
>> + for (i = ar_snoc->vreg_count - 1; i >= 0; i--) {
>> vreg_info = &ar_snoc->vreg[i];
>>
>> if (!vreg_info->reg)
>> @@ -1616,7 +1633,13 @@ static int ath10k_hw_power_off(struct ath10k
>> *ar)
>>
>> static const struct of_device_id ath10k_snoc_dt_match[] = {
>> { .compatible = "qcom,wcn3990-wifi",
>> - .data = &drv_priv,
>> + .data = &sdm845_wcn39xx_drv_priv,
>> + },
>> + { .compatible = "qcom,sdm845-wcn39xx-wifi",
>> + .data = &sdm845_wcn39xx_drv_priv,
>> + },
>> + { .compatible = "qcom,qcs40x-wcn39xx-wifi",
>> + .data = &qcs40x_wcn39xx_drv_priv,
>> },
>> { }
>> };
>> @@ -1680,8 +1703,9 @@ static int ath10k_snoc_probe(struct
>> platform_device *pdev)
>> goto err_release_resource;
>> }
>>
>> - ar_snoc->vreg = vreg_cfg;
>> - for (i = 0; i < ARRAY_SIZE(vreg_cfg); i++) {
>> + ar_snoc->vreg = drv_data->vreg_cfg;
>> + ar_snoc->vreg_count = drv_data->vreg_count;
>> + for (i = 0; i < ar_snoc->vreg_count; i++) {
>> ret = ath10k_get_vreg_info(ar, dev, &ar_snoc->vreg[i]);
>> if (ret)
>> goto err_free_irq;
>> diff --git a/drivers/net/wireless/ath/ath10k/snoc.h
>> b/drivers/net/wireless/ath/ath10k/snoc.h
>> index d62f53501fbb..0bdada11985c 100644
>> --- a/drivers/net/wireless/ath/ath10k/snoc.h
>> +++ b/drivers/net/wireless/ath/ath10k/snoc.h
>> @@ -10,10 +10,22 @@
>> #include "ce.h"
>> #include "qmi.h"
>>
>> +struct ath10k_vreg_info {
>> + struct regulator *reg;
>> + const char *name;
>> + u32 min_v;
>> + u32 max_v;
>> + u32 load_ua;
>> + unsigned long settle_delay;
>> + bool required;
>> +};
>> +
>> struct ath10k_snoc_drv_priv {
>> enum ath10k_hw_rev hw_rev;
>> u64 dma_mask;
>> u32 msa_size;
>> + struct ath10k_vreg_info *vreg_cfg;
>> + u8 vreg_count;
>> };
>>
>> struct snoc_state {
>> @@ -42,16 +54,6 @@ struct ath10k_snoc_ce_irq {
>> u32 irq_line;
>> };
>>
>> -struct ath10k_vreg_info {
>> - struct regulator *reg;
>> - const char *name;
>> - u32 min_v;
>> - u32 max_v;
>> - u32 load_ua;
>> - unsigned long settle_delay;
>> - bool required;
>> -};
>> -
>> struct ath10k_clk_info {
>> struct clk *handle;
>> const char *name;
>> @@ -77,6 +79,7 @@ struct ath10k_snoc {
>> struct ath10k_ce ce;
>> struct timer_list rx_post_retry;
>> struct ath10k_vreg_info *vreg;
>> + u8 vreg_count;
>> struct ath10k_clk_info *clk;
>> struct ath10k_qmi *qmi;
>> unsigned long flags;
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
>> Forum,
>> a Linux Foundation Collaborative Project
>>
BR,
Govind
^ permalink raw reply
* Re: [PATCH v4 1/2] dt-bindings: arm: nxp: Add device tree binding for ls1046a-frwy board
From: Shawn Guo @ 2019-07-23 6:50 UTC (permalink / raw)
To: Pramod Kumar
Cc: robh+dt@kernel.org, mark.rutland@arm.com,
manivannan.sadhasivam@linaro.org, Aisheng Dong,
Michal.Vokac@ysoft.com, Leo Li, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Vabhav Sharma
In-Reply-To: <1563284586-29928-2-git-send-email-pramod.kumar_1@nxp.com>
On Tue, Jul 16, 2019 at 01:43:27PM +0000, Pramod Kumar wrote:
> Add "fsl,ls1046a-frwy" bindings for ls1046afrwy board based on ls1046a SoC
>
> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
Applied, thanks.
^ permalink raw reply
* Re: [PATCH v4 2/2] arm64: dts: nxp: add ls1046a-frwy board support
From: Shawn Guo @ 2019-07-23 6:52 UTC (permalink / raw)
To: Pramod Kumar
Cc: robh+dt@kernel.org, mark.rutland@arm.com,
manivannan.sadhasivam@linaro.org, Aisheng Dong,
Michal.Vokac@ysoft.com, Leo Li, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Vabhav Sharma
In-Reply-To: <1563284586-29928-3-git-send-email-pramod.kumar_1@nxp.com>
On Tue, Jul 16, 2019 at 01:43:31PM +0000, Pramod Kumar wrote:
> ls1046afrwy board is based on nxp ls1046a SoC.
> Board support's 4GB ddr memory, i2c, microSD card,
> serial console,qspi nor flash,ifc nand flash,qsgmii network interface,
> usb 3.0 and serdes interface to support two x1gen3 pcie interface.
>
> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
> Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts | 156 +++++++++++++++++++++
> 2 files changed, 157 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 0bd122f..1211531 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts
> new file mode 100644
> index 0000000..cda4998
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts
> @@ -0,0 +1,156 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
> + *
> + * Copyright 2019 NXP.
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include "fsl-ls1046a.dtsi"
> +
> +/ {
> + model = "LS1046A FRWY Board";
> + compatible = "fsl,ls1046a-frwy", "fsl,ls1046a";
> +
> + aliases {
> + serial0 = &duart0;
> + serial1 = &duart1;
> + serial2 = &duart2;
> + serial3 = &duart3;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + sb_3v3: regulator-sb3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "LT8642SEV-3.3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +};
> +
> +&duart0 {
> + status = "okay";
> +};
> +
> +&duart1 {
> + status = "okay";
> +};
> +
> +&duart2 {
> + status = "okay";
> +};
> +
> +&duart3 {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + status = "okay";
> +
> + i2c-mux@77 {
> + compatible = "nxp,pca9546";
> + reg = <0x77>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + i2c@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> +
> + power-monitor@40 {
> + compatible = "ti,ina220";
> + reg = <0x40>;
> + shunt-resistor = <1000>;
> + };
> +
> +
One newline is good enough. I fixed it up and applied the patch.
Shawn
> + temperature-sensor@4c {
> + compatible = "nxp,sa56004";
> + reg = <0x4c>;
> + vcc-supply = <&sb_3v3>;
> + };
> +
> + rtc@51 {
> + compatible = "nxp,pcf2129";
> + reg = <0x51>;
> + };
> +
> + eeprom@52 {
> + compatible = "atmel,24c512";
> + reg = <0x52>;
> + };
> +
> + eeprom@53 {
> + compatible = "atmel,24c512";
> + reg = <0x53>;
> + };
> +
> + };
> + };
> +};
> +
> +&ifc {
> + #address-cells = <2>;
> + #size-cells = <1>;
> + /* NAND Flash */
> + ranges = <0x0 0x0 0x0 0x7e800000 0x00010000>;
> + status = "okay";
> +
> + nand@0,0 {
> + compatible = "fsl,ifc-nand";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x0 0x0 0x10000>;
> + };
> +
> +};
> +
> +#include "fsl-ls1046-post.dtsi"
> +
> +&fman0 {
> + ethernet@e0000 {
> + phy-handle = <&qsgmii_phy4>;
> + phy-connection-type = "qsgmii";
> + };
> +
> + ethernet@e8000 {
> + phy-handle = <&qsgmii_phy2>;
> + phy-connection-type = "qsgmii";
> + };
> +
> + ethernet@ea000 {
> + phy-handle = <&qsgmii_phy1>;
> + phy-connection-type = "qsgmii";
> + };
> +
> + ethernet@f2000 {
> + phy-handle = <&qsgmii_phy3>;
> + phy-connection-type = "qsgmii";
> + };
> +
> + mdio@fd000 {
> + qsgmii_phy1: ethernet-phy@1c {
> + reg = <0x1c>;
> + };
> +
> + qsgmii_phy2: ethernet-phy@1d {
> + reg = <0x1d>;
> + };
> +
> + qsgmii_phy3: ethernet-phy@1e {
> + reg = <0x1e>;
> + };
> +
> + qsgmii_phy4: ethernet-phy@1f {
> + reg = <0x1f>;
> + };
> + };
> +};
> --
> 2.7.4
>
^ permalink raw reply
* Re: [Letux-kernel] [PATCH v3 0/5] drm/panel-simple: Add panel parameters for ortustech-com37h3m05dtc/99dtc and sharp-lq070y3dg3b
From: H. Nikolaus Schaller @ 2019-07-23 6:59 UTC (permalink / raw)
To: Sam Ravnborg
Cc: Mark Rutland, devicetree, David Airlie, Belisko Marek,
Tomi Valkeinen, Linux Kernel Mailing List, dri-devel, Rob Herring,
Thierry Reding, Linux-OMAP, Discussions about the Letux Kernel
In-Reply-To: <20190717181455.GB6522@ravnborg.org>
Hi Sam,
> Am 17.07.2019 um 20:14 schrieb Sam Ravnborg <sam@ravnborg.org>:
>
> Hi Nikolaus.
>
>>>>>> BTW: should also be applied to 5.2
>>>>> The drm bits are reviewed. The DT bits needs OK from DT people.
>>>>> When we have OK from DT people we can apply them all to drm-misc-next.
>>>>
>>>> I got OK on irc from Rob to process these.
>>>> All patches are now applied to drm-misc-next.
>>>
>>> Thanks for taking care of this!
>>
>> I have checked but it seems they are still not merged into linux-next.
>
> They will appear in next merge window. They were to late to hit current
> merge window, as the cut-of time is around .rc5 in the drm subsystem.
> And this is not really a fix so not stable material.
have finally arrived. I just wasn't patient enough :)
BR and thanks,
Nikolaus
^ permalink raw reply
* Re: [PATCH v5 04/13] media: rc: sunxi: Add RXSTA bits definition
From: Maxime Ripard @ 2019-07-23 7:04 UTC (permalink / raw)
To: Sean Young
Cc: Clément Péron, Mauro Carvalho Chehab, Rob Herring,
Mark Rutland, Chen-Yu Tsai, devicetree, linux-kernel, linux-sunxi,
linux-arm-kernel, linux-media-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20190723062557.hnbi6hgrg4ecawkn-3XSxi2G4b3iXFJAUJl40Xg@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1248 bytes --]
Hi Sean,
On Tue, Jul 23, 2019 at 07:25:57AM +0100, Sean Young wrote:
> On Mon, Jul 15, 2019 at 01:12:45PM +0100, Sean Young wrote:
> > On Sun, Jul 14, 2019 at 04:32:22PM +0200, Clément Péron wrote:
> > > Hi Sean,
> > >
> > > You acked the whole v3 series but this patch has been introduced in v5
> > > could you ack this one too?
> >
> > Acked-by: Sean Young <sean-hENCXIMQXOg@public.gmane.org>
>
> So who's tree should this series go through? It seems mostly device tree.
> Alternatively I'm happy to try it get merged via the media tree.
Ideally the media bits should go through the media tree, the DT bits
will go through arm-soc
So you can apply the patches 1-4, 7 and 10, I'll apply the rest.
Does that work for you?
Thanks!
Maxime
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply
* Re: [RFC, v3 9/9] media: platform: Add Mediatek ISP P1 shared memory device
From: Tomasz Figa @ 2019-07-23 7:20 UTC (permalink / raw)
To: Jungo Lin
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
Sean Cheng (鄭昇弘), Mauro Carvalho Chehab,
Rynn Wu (吳育恩), srv_heupstream, Rob Herring,
Ryan Yu (余孟修),
Frankie Chiu (邱文凱), Hans Verkuil,
Matthias Brugger, Sj Huang,
moderated list:ARM/Mediatek SoC support, Laurent Pinchart,
ddavenport-F7+t8E8rja9g9hUCZPvPmw,
Frederic Chen (陳俊元)
In-Reply-To: <1562313579.1212.73.camel@mtksdccf07>
Hi Jungo,
On Fri, Jul 5, 2019 at 4:59 PM Jungo Lin <jungo.lin-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
>
> Hi Tomasz:
>
> On Fri, 2019-07-05 at 13:22 +0900, Tomasz Figa wrote:
> > Hi Jungo,
> >
> > On Fri, Jul 5, 2019 at 12:33 PM Jungo Lin <jungo.lin-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org> wrote:
> > >
> > > Hi Tomasz,
>
> [snip]
>
> > > After applying your suggestion in SCP device driver, we could remove
> > > mtk_cam-smem.h/c. Currently, we use dma_alloc_coherent with SCP device
> > > to get SCP address. We could touch the buffer with this SCP address in
> > > SCP processor.
> > >
> > > After that, we use dma_map_page_attrs with P1 device which supports
> > > IOMMU domain to get IOVA address. For this address, we will assign
> > > it to our ISP HW device to proceed.
> > >
> > > Below is the snippet for ISP P1 compose buffer initialization.
> > >
> > > ptr = dma_alloc_coherent(p1_dev->cam_dev.smem_dev,
> > > MAX_COMPOSER_SIZE, &addr, GFP_KERNEL);
> > > if (!ptr) {
> > > dev_err(dev, "failed to allocate compose memory\n");
> > > return -ENOMEM;
> > > }
> > > isp_ctx->scp_mem_pa = addr;
> >
> > addr contains a DMA address, not a physical address. Could we call it
> > scp_mem_dma instead?
> >
> > > dev_dbg(dev, "scp addr:%pad\n", &addr);
> > >
> > > /* get iova address */
> > > addr = dma_map_page_attrs(dev, phys_to_page(addr), 0,
> >
> > addr is a DMA address, so phys_to_page() can't be called on it. The
> > simplest thing here would be to use dma_map_single() with ptr as the
> > CPU address expected.
> >
>
> We have changed to use ma_map_single() with ptr, but encounter IOMMU
> error. From the debug log of iommu_dma_map_page[3], we got
> 0x0000000054800000 instead of expected address: 0x0000000050800000[2].
> There is a address offset(0x4000000). If we change to use
> dma_map_page_attrs with phys_to_page(addr), the address is correct as we
> expected[2]. Do you have any suggestion on this issue? Do we miss
> something?
Sorry for the late reply. Could you show me the code changes you made
to use dma_map_single()? It would sound like the virtual address
passed to dma_map_single() isn't correct.
Best regards,
Tomasz
>
> [1]
> [ 1.344786] __dma_alloc_from_coherent: 0x800000 PAGE_SHIFT:12
> device_base:0x0000000050000000 dma:0x0000000050800000
> virt_base:ffffff8014000000 va:ffffff8014800000
>
> [ 1.346890] mtk-cam 1a000000.camisp: scp addr:0x0000000050800000
> va:ffffff8014800000
>
> [ 1.347864] iommu_dma_map_page:0x0000000054800000 offset:0
> [ 1.348562] mtk-cam 1a000000.camisp: iova addr:0x00000000fde00000
>
> [2]
> [ 1.346738] __dma_alloc_from_coherent: 0x800000 PAGE_SHIFT:12
> device_base:0x0000000050000000 dma:0x0000000050800000
> virt_base:ffffff8014000000 va:ffffff8014800000
> [ 1.348841] mtk-cam 1a000000.camisp: scp addr:0x0000000050800000
> va:ffffff8014800000
> [ 1.349816] iommu_dma_map_page:0x0000000050800000 offset:0
> [ 1.350514] mtk-cam 1a000000.camisp: iova addr:0x00000000fde00000
>
>
> [3]
> dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page,
> unsigned long offset, size_t size, int prot)
> {
> phys_addr_t phys = page_to_phys(page);
> pr_err("iommu_dma_map_page:%pa offset:%lu\n", &phys, offset);
>
> return __iommu_dma_map(dev, page_to_phys(page) + offset, size, prot,
> iommu_get_dma_domain(dev));
> }
>
> [snip]
>
> Best regards,
>
> Jungo
>
^ permalink raw reply
* [PATCH] ARM: dts: Fix incomplete dts data for am3 and am4 mmc
From: Tony Lindgren @ 2019-07-23 7:29 UTC (permalink / raw)
To: linux-omap; +Cc: Benoît Cousson, devicetree, David Lechner
Commit 4e27f752ab8c ("ARM: OMAP2+: Drop mmc platform data for am330x and
am43xx") dropped legacy mmc platform data for am3 and am4, but missed the
fact that we never updated the dts files for mmc3 that is directly on l3
interconnect instead of l4 interconnect. This leads to a situation with
no legacy platform data and incomplete dts data.
Let's update the mmc instances on l3 interconnect to probe properly with
ti-sysc interconnect target module driver to make mmc3 work again. Let's
still keep legacy "ti,hwmods" property around for v5.2 kernel and only
drop it later on.
Note that there is no need to use property status = "disabled" for mmc3.
The default for dts is enabled, and runtime PM will idle unused instances
just fine.
Fixes: 4e27f752ab8c ("ARM: OMAP2+: Drop mmc platform data for am330x and am43xx")
Reported-by: David Lechner <david@lechnology.com>
Tested-by: David Lechner <david@lechnology.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/boot/dts/am33xx.dtsi | 32 ++++++++++++++++++++++++++------
arch/arm/boot/dts/am4372.dtsi | 32 ++++++++++++++++++++++++++------
2 files changed, 52 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -234,13 +234,33 @@
interrupt-names = "edma3_tcerrint";
};
- mmc3: mmc@47810000 {
- compatible = "ti,omap4-hsmmc";
+ target-module@47810000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "mmc3";
- ti,needs-special-reset;
- interrupts = <29>;
- reg = <0x47810000 0x1000>;
- status = "disabled";
+ reg = <0x478102fc 0x4>,
+ <0x47810110 0x4>,
+ <0x47810114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x47810000 0x1000>;
+
+ mmc3: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ ti,needs-special-reset;
+ interrupts = <29>;
+ reg = <0x0 0x1000>;
+ };
};
usb: usb@47400000 {
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -228,13 +228,33 @@
interrupt-names = "edma3_tcerrint";
};
- mmc3: mmc@47810000 {
- compatible = "ti,omap4-hsmmc";
- reg = <0x47810000 0x1000>;
+ target-module@47810000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "mmc3";
- ti,needs-special-reset;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
+ reg = <0x478102fc 0x4>,
+ <0x47810110 0x4>,
+ <0x47810114 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
+ SYSC_OMAP2_ENAWAKEUP |
+ SYSC_OMAP2_SOFTRESET |
+ SYSC_OMAP2_AUTOIDLE)>;
+ ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+ <SYSC_IDLE_NO>,
+ <SYSC_IDLE_SMART>;
+ ti,syss-mask = <1>;
+ clocks = <&l3s_clkctrl AM4_L3S_MMC3_CLKCTRL 0>;
+ clock-names = "fck";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x47810000 0x1000>;
+
+ mmc3: mmc@0 {
+ compatible = "ti,omap4-hsmmc";
+ ti,needs-special-reset;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x1000>;
+ };
};
sham: sham@53100000 {
--
2.21.0
^ permalink raw reply
* Re: [PATCH] arm64: dts: imx8mq: fix SAI compatible
From: Shawn Guo @ 2019-07-23 7:33 UTC (permalink / raw)
To: Lucas Stach, Daniel Baluta
Cc: devicetree, patchwork-lst, NXP Linux Team, kernel, Fabio Estevam,
linux-arm-kernel
In-Reply-To: <20190717095436.28154-1-l.stach@pengutronix.de>
Add Daniel for comment.
On Wed, Jul 17, 2019 at 11:54:36AM +0200, Lucas Stach wrote:
> The i.MX8M SAI block is not compatible with the i.MX6SX one, as the
> register layout has changed due to two version registers being added
> at the beginning of the address map. Remove the bogus compatible.
>
> Fixes: 8c61538dc945 "arm64: dts: imx8mq: Add SAI2 node"
The format should be the following. I can fix it when applying though.
Fixes: 8c61538dc945 ("arm64: dts: imx8mq: Add SAI2 node")
Shawn
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 9326bd4150a3..0c533c66b340 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -718,8 +718,7 @@
>
> sai2: sai@308b0000 {
> #sound-dai-cells = <0>;
> - compatible = "fsl,imx8mq-sai",
> - "fsl,imx6sx-sai";
> + compatible = "fsl,imx8mq-sai";
> reg = <0x308b0000 0x10000>;
> interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&clk IMX8MQ_CLK_SAI2_IPG>,
> --
> 2.20.1
>
^ permalink raw reply
* [PATCH 0/3][V4] iio: imu: Add support for the ADIS16460 IMU
From: Alexandru Ardelean @ 2019-07-23 7:36 UTC (permalink / raw)
To: linux-iio, linux-spi, devicetree, linux-kernel
Cc: jic23, robh+dt, mark.rutland, broonie, Alexandru Ardelean
This changeset adds support for the ADIS16460.
The default CS change delay is 10 uS, while the ADIS16460 requires a
minimum of 16 uS.
As it turns out, the SPI framework support already has support for this
feature, which is currently present in the for-next branch:
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git/commit/?h=0ff2de8bb163551ec4230a5a6f3c40c1f6adec4f
This changeset now makes use of that feature, to allow longer CS change
times (as needed) for ADIS16460.
The SPI patch is present in the iio/testing branch, but not present in the
iio/togreg branch.
Changelog v3 -> v4:
* for SPI: no change
* for ADIS lib: use existing `cs_change_delay` feature (from SPI)
* for DT: no change
Changelog v2 -> v3:
* for SPI:
* used `cs_change_delay` instead of `cs_change_delay_usecs` (i.e. removed
`_usecs` suffix
* used SPI specific subject line for SPI patch
* for ADIS lib:
* updated to use the `cs_change_delay`
* for DT:
* added Rob's `Reviewed-by` tag
Changelog v1 -> v2:
* for SPI:
* renamed `cs_change_stall_delay_us` -> `cs_change_delay_usecs`
initial recommendation was `cs_change_delay`, but decided to name this
`cs_change_delay_usecs`, since the convention for these delays seems
to add the `_usecs` suffix
* for ADIS lib:
* renamed `stall_delay` -> `cs_change_delay`
* removed some assignments of `cs_change_delay`
where `cs_change` is not set
* for ADIS16460 driver:
* fixed license
* adjusted to new `cs_change_delay[_usecs]`
Alexandru Ardelean (3):
iio: imu: adis: Add support for SPI transfer cs_change_delay
iio: imu: Add support for the ADIS16460 IMU
dt-bindings: iio: imu: add bindings for ADIS16460
.../bindings/iio/imu/adi,adis16460.yaml | 53 ++
MAINTAINERS | 8 +
drivers/iio/imu/Kconfig | 12 +
drivers/iio/imu/Makefile | 1 +
drivers/iio/imu/adis.c | 12 +
drivers/iio/imu/adis16460.c | 489 ++++++++++++++++++
include/linux/iio/imu/adis.h | 2 +
7 files changed, 577 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml
create mode 100644 drivers/iio/imu/adis16460.c
--
2.20.1
^ permalink raw reply
* [PATCH 1/3][V4] iio: imu: adis: Add support for SPI transfer cs_change_delay
From: Alexandru Ardelean @ 2019-07-23 7:36 UTC (permalink / raw)
To: linux-iio, linux-spi, devicetree, linux-kernel
Cc: jic23, robh+dt, mark.rutland, broonie, Alexandru Ardelean,
Michael Hennerich
In-Reply-To: <20190723073641.27801-1-alexandru.ardelean@analog.com>
The ADIS16460 requires a higher delay before the next transfer. Since the
SPI framework supports configuring the delay before the next transfer, this
driver will become the first user of it.
The support for this functionality in ADIS16460 requires an addition to the
ADIS lib to support the `cs_change_delay` functionality from the SPI
subsystem.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
drivers/iio/imu/adis.c | 12 ++++++++++++
include/linux/iio/imu/adis.h | 2 ++
2 files changed, 14 insertions(+)
diff --git a/drivers/iio/imu/adis.c b/drivers/iio/imu/adis.c
index 30281e91dbf9..1631c255deab 100644
--- a/drivers/iio/imu/adis.c
+++ b/drivers/iio/imu/adis.c
@@ -39,18 +39,24 @@ int adis_write_reg(struct adis *adis, unsigned int reg,
.len = 2,
.cs_change = 1,
.delay_usecs = adis->data->write_delay,
+ .cs_change_delay = adis->data->cs_change_delay,
+ .cs_change_delay_unit = SPI_DELAY_UNIT_USECS,
}, {
.tx_buf = adis->tx + 2,
.bits_per_word = 8,
.len = 2,
.cs_change = 1,
.delay_usecs = adis->data->write_delay,
+ .cs_change_delay = adis->data->cs_change_delay,
+ .cs_change_delay_unit = SPI_DELAY_UNIT_USECS,
}, {
.tx_buf = adis->tx + 4,
.bits_per_word = 8,
.len = 2,
.cs_change = 1,
.delay_usecs = adis->data->write_delay,
+ .cs_change_delay = adis->data->cs_change_delay,
+ .cs_change_delay_unit = SPI_DELAY_UNIT_USECS,
}, {
.tx_buf = adis->tx + 6,
.bits_per_word = 8,
@@ -133,12 +139,16 @@ int adis_read_reg(struct adis *adis, unsigned int reg,
.len = 2,
.cs_change = 1,
.delay_usecs = adis->data->write_delay,
+ .cs_change_delay = adis->data->cs_change_delay,
+ .cs_change_delay_unit = SPI_DELAY_UNIT_USECS,
}, {
.tx_buf = adis->tx + 2,
.bits_per_word = 8,
.len = 2,
.cs_change = 1,
.delay_usecs = adis->data->read_delay,
+ .cs_change_delay = adis->data->cs_change_delay,
+ .cs_change_delay_unit = SPI_DELAY_UNIT_USECS,
}, {
.tx_buf = adis->tx + 4,
.rx_buf = adis->rx,
@@ -146,6 +156,8 @@ int adis_read_reg(struct adis *adis, unsigned int reg,
.len = 2,
.cs_change = 1,
.delay_usecs = adis->data->read_delay,
+ .cs_change_delay = adis->data->cs_change_delay,
+ .cs_change_delay_unit = SPI_DELAY_UNIT_USECS,
}, {
.rx_buf = adis->rx + 2,
.bits_per_word = 8,
diff --git a/include/linux/iio/imu/adis.h b/include/linux/iio/imu/adis.h
index 3428d06b2f44..4c53815bb729 100644
--- a/include/linux/iio/imu/adis.h
+++ b/include/linux/iio/imu/adis.h
@@ -26,6 +26,7 @@ struct adis_burst;
* struct adis_data - ADIS chip variant specific data
* @read_delay: SPI delay for read operations in us
* @write_delay: SPI delay for write operations in us
+ * @cs_change_delay: SPI delay between CS changes in us
* @glob_cmd_reg: Register address of the GLOB_CMD register
* @msc_ctrl_reg: Register address of the MSC_CTRL register
* @diag_stat_reg: Register address of the DIAG_STAT register
@@ -35,6 +36,7 @@ struct adis_burst;
struct adis_data {
unsigned int read_delay;
unsigned int write_delay;
+ unsigned int cs_change_delay;
unsigned int glob_cmd_reg;
unsigned int msc_ctrl_reg;
--
2.20.1
^ permalink raw reply related
* [PATCH 2/3][V4] iio: imu: Add support for the ADIS16460 IMU
From: Alexandru Ardelean @ 2019-07-23 7:36 UTC (permalink / raw)
To: linux-iio, linux-spi, devicetree, linux-kernel
Cc: jic23, robh+dt, mark.rutland, broonie, Alexandru Ardelean,
Dragos Bogdan, Michael Hennerich
In-Reply-To: <20190723073641.27801-1-alexandru.ardelean@analog.com>
The ADIS16460 device is a complete inertial system that includes a triaxial
gyroscope and a triaxial accelerometer. It's more simplified design than
that of the ADIS16480, and does not offer the triaxial magnetometers &
pressure sensors. It does also have a temperature sensor (like the
ADIS16480).
Since it is part of the ADIS16XXX family, it re-uses parts of the ADIS
library.
Naturally, the register map is different and much more simplified than the
ADIS16480 subfamily, so it cannot be integrated into that driver. A major
difference is that the registers are not paged.
One thing that is particularly special about it, is that it requires a
higher delay between CS changes (i.e. when CS goes up, the spec recommends
that it be brought down after a minimum of 16 uS).
Other ADIS chips require (via spec) a minimum of 2 uS between CS changes.
The kernel's 10 uS default should be fine for those other chips; they
haven't been tested with lower CS change delays yet.
Datasheet:
https://www.analog.com/media/en/technical-documentation/data-sheets/adis16460.pdf
Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
MAINTAINERS | 7 +
drivers/iio/imu/Kconfig | 12 +
drivers/iio/imu/Makefile | 1 +
drivers/iio/imu/adis16460.c | 489 ++++++++++++++++++++++++++++++++++++
4 files changed, 509 insertions(+)
create mode 100644 drivers/iio/imu/adis16460.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 783569e3c4b4..f7de89e82e35 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -945,6 +945,13 @@ L: linux-iio@vger.kernel.org
F: include/linux/iio/imu/adis.h
F: drivers/iio/imu/adis.c
+ANALOG DEVICES INC ADIS16460 DRIVER
+M: Dragos Bogdan <dragos.bogdan@analog.com>
+S: Supported
+L: linux-iio@vger.kernel.org
+W: http://ez.analog.com/community/linux-device-drivers
+F: drivers/iio/imu/adis16460.c
+
ANALOG DEVICES INC ADP5061 DRIVER
M: Stefan Popa <stefan.popa@analog.com>
L: linux-pm@vger.kernel.org
diff --git a/drivers/iio/imu/Kconfig b/drivers/iio/imu/Kconfig
index 4957e6df447e..f3c7282321a8 100644
--- a/drivers/iio/imu/Kconfig
+++ b/drivers/iio/imu/Kconfig
@@ -17,6 +17,18 @@ config ADIS16400
adis16365, adis16400 and adis16405 triaxial inertial sensors
(adis16400 series also have magnetometers).
+config ADIS16460
+ tristate "Analog Devices ADIS16460 and similar IMU driver"
+ depends on SPI
+ select IIO_ADIS_LIB
+ select IIO_ADIS_LIB_BUFFER if IIO_BUFFER
+ help
+ Say yes here to build support for Analog Devices ADIS16460 inertial
+ sensor.
+
+ To compile this driver as a module, choose M here: the module will be
+ called adis16460.
+
config ADIS16480
tristate "Analog Devices ADIS16480 and similar IMU driver"
depends on SPI
diff --git a/drivers/iio/imu/Makefile b/drivers/iio/imu/Makefile
index 9e452fce1aaf..4a6958865504 100644
--- a/drivers/iio/imu/Makefile
+++ b/drivers/iio/imu/Makefile
@@ -5,6 +5,7 @@
# When adding new entries keep the list in alphabetical order
obj-$(CONFIG_ADIS16400) += adis16400.o
+obj-$(CONFIG_ADIS16460) += adis16460.o
obj-$(CONFIG_ADIS16480) += adis16480.o
adis_lib-y += adis.o
diff --git a/drivers/iio/imu/adis16460.c b/drivers/iio/imu/adis16460.c
new file mode 100644
index 000000000000..db713cba75a2
--- /dev/null
+++ b/drivers/iio/imu/adis16460.c
@@ -0,0 +1,489 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * ADIS16460 IMU driver
+ *
+ * Copyright 2019 Analog Devices Inc.
+ */
+
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/spi/spi.h>
+
+#include <linux/iio/iio.h>
+#include <linux/iio/imu/adis.h>
+
+#include <linux/debugfs.h>
+
+#define ADIS16460_REG_FLASH_CNT 0x00
+#define ADIS16460_REG_DIAG_STAT 0x02
+#define ADIS16460_REG_X_GYRO_LOW 0x04
+#define ADIS16460_REG_X_GYRO_OUT 0x06
+#define ADIS16460_REG_Y_GYRO_LOW 0x08
+#define ADIS16460_REG_Y_GYRO_OUT 0x0A
+#define ADIS16460_REG_Z_GYRO_LOW 0x0C
+#define ADIS16460_REG_Z_GYRO_OUT 0x0E
+#define ADIS16460_REG_X_ACCL_LOW 0x10
+#define ADIS16460_REG_X_ACCL_OUT 0x12
+#define ADIS16460_REG_Y_ACCL_LOW 0x14
+#define ADIS16460_REG_Y_ACCL_OUT 0x16
+#define ADIS16460_REG_Z_ACCL_LOW 0x18
+#define ADIS16460_REG_Z_ACCL_OUT 0x1A
+#define ADIS16460_REG_SMPL_CNTR 0x1C
+#define ADIS16460_REG_TEMP_OUT 0x1E
+#define ADIS16460_REG_X_DELT_ANG 0x24
+#define ADIS16460_REG_Y_DELT_ANG 0x26
+#define ADIS16460_REG_Z_DELT_ANG 0x28
+#define ADIS16460_REG_X_DELT_VEL 0x2A
+#define ADIS16460_REG_Y_DELT_VEL 0x2C
+#define ADIS16460_REG_Z_DELT_VEL 0x2E
+#define ADIS16460_REG_MSC_CTRL 0x32
+#define ADIS16460_REG_SYNC_SCAL 0x34
+#define ADIS16460_REG_DEC_RATE 0x36
+#define ADIS16460_REG_FLTR_CTRL 0x38
+#define ADIS16460_REG_GLOB_CMD 0x3E
+#define ADIS16460_REG_X_GYRO_OFF 0x40
+#define ADIS16460_REG_Y_GYRO_OFF 0x42
+#define ADIS16460_REG_Z_GYRO_OFF 0x44
+#define ADIS16460_REG_X_ACCL_OFF 0x46
+#define ADIS16460_REG_Y_ACCL_OFF 0x48
+#define ADIS16460_REG_Z_ACCL_OFF 0x4A
+#define ADIS16460_REG_LOT_ID1 0x52
+#define ADIS16460_REG_LOT_ID2 0x54
+#define ADIS16460_REG_PROD_ID 0x56
+#define ADIS16460_REG_SERIAL_NUM 0x58
+#define ADIS16460_REG_CAL_SGNTR 0x60
+#define ADIS16460_REG_CAL_CRC 0x62
+#define ADIS16460_REG_CODE_SGNTR 0x64
+#define ADIS16460_REG_CODE_CRC 0x66
+
+struct adis16460_chip_info {
+ unsigned int num_channels;
+ const struct iio_chan_spec *channels;
+ unsigned int gyro_max_val;
+ unsigned int gyro_max_scale;
+ unsigned int accel_max_val;
+ unsigned int accel_max_scale;
+};
+
+struct adis16460 {
+ const struct adis16460_chip_info *chip_info;
+ struct adis adis;
+};
+
+#ifdef CONFIG_DEBUG_FS
+
+static int adis16460_show_serial_number(void *arg, u64 *val)
+{
+ struct adis16460 *adis16460 = arg;
+ u16 serial;
+ int ret;
+
+ ret = adis_read_reg_16(&adis16460->adis, ADIS16460_REG_SERIAL_NUM,
+ &serial);
+ if (ret < 0)
+ return ret;
+
+ *val = serial;
+
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(adis16460_serial_number_fops,
+ adis16460_show_serial_number, NULL, "0x%.4llx\n");
+
+static int adis16460_show_product_id(void *arg, u64 *val)
+{
+ struct adis16460 *adis16460 = arg;
+ u16 prod_id;
+ int ret;
+
+ ret = adis_read_reg_16(&adis16460->adis, ADIS16460_REG_PROD_ID,
+ &prod_id);
+ if (ret < 0)
+ return ret;
+
+ *val = prod_id;
+
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(adis16460_product_id_fops,
+ adis16460_show_product_id, NULL, "%llu\n");
+
+static int adis16460_show_flash_count(void *arg, u64 *val)
+{
+ struct adis16460 *adis16460 = arg;
+ u32 flash_count;
+ int ret;
+
+ ret = adis_read_reg_32(&adis16460->adis, ADIS16460_REG_FLASH_CNT,
+ &flash_count);
+ if (ret < 0)
+ return ret;
+
+ *val = flash_count;
+
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(adis16460_flash_count_fops,
+ adis16460_show_flash_count, NULL, "%lld\n");
+
+static int adis16460_debugfs_init(struct iio_dev *indio_dev)
+{
+ struct adis16460 *adis16460 = iio_priv(indio_dev);
+
+ debugfs_create_file("serial_number", 0400, indio_dev->debugfs_dentry,
+ adis16460, &adis16460_serial_number_fops);
+ debugfs_create_file("product_id", 0400, indio_dev->debugfs_dentry,
+ adis16460, &adis16460_product_id_fops);
+ debugfs_create_file("flash_count", 0400, indio_dev->debugfs_dentry,
+ adis16460, &adis16460_flash_count_fops);
+
+ return 0;
+}
+
+#else
+
+static int adis16460_debugfs_init(struct iio_dev *indio_dev)
+{
+ return 0;
+}
+
+#endif
+
+static int adis16460_set_freq(struct iio_dev *indio_dev, int val, int val2)
+{
+ struct adis16460 *st = iio_priv(indio_dev);
+ unsigned int t;
+
+ t = val * 1000 + val2 / 1000;
+ if (t <= 0)
+ return -EINVAL;
+
+ t = 2048000 / t;
+ if (t > 2048)
+ t = 2048;
+
+ if (t != 0)
+ t--;
+
+ return adis_write_reg_16(&st->adis, ADIS16460_REG_DEC_RATE, t);
+}
+
+static int adis16460_get_freq(struct iio_dev *indio_dev, int *val, int *val2)
+{
+ struct adis16460 *st = iio_priv(indio_dev);
+ uint16_t t;
+ int ret;
+ unsigned int freq;
+
+ ret = adis_read_reg_16(&st->adis, ADIS16460_REG_DEC_RATE, &t);
+ if (ret < 0)
+ return ret;
+
+ freq = 2048000 / (t + 1);
+ *val = freq / 1000;
+ *val2 = (freq % 1000) * 1000;
+
+ return IIO_VAL_INT_PLUS_MICRO;
+}
+
+static int adis16460_read_raw(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan, int *val, int *val2, long info)
+{
+ struct adis16460 *st = iio_priv(indio_dev);
+
+ switch (info) {
+ case IIO_CHAN_INFO_RAW:
+ return adis_single_conversion(indio_dev, chan, 0, val);
+ case IIO_CHAN_INFO_SCALE:
+ switch (chan->type) {
+ case IIO_ANGL_VEL:
+ *val = st->chip_info->gyro_max_scale;
+ *val2 = st->chip_info->gyro_max_val;
+ return IIO_VAL_FRACTIONAL;
+ case IIO_ACCEL:
+ *val = st->chip_info->accel_max_scale;
+ *val2 = st->chip_info->accel_max_val;
+ return IIO_VAL_FRACTIONAL;
+ case IIO_TEMP:
+ *val = 50; /* 50 milli degrees Celsius/LSB */
+ return IIO_VAL_INT;
+ default:
+ return -EINVAL;
+ }
+ case IIO_CHAN_INFO_OFFSET:
+ *val = 500; /* 25 degrees Celsius = 0x0000 */
+ return IIO_VAL_INT;
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ return adis16460_get_freq(indio_dev, val, val2);
+ default:
+ return -EINVAL;
+ }
+}
+
+static int adis16460_write_raw(struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan, int val, int val2, long info)
+{
+ switch (info) {
+ case IIO_CHAN_INFO_SAMP_FREQ:
+ return adis16460_set_freq(indio_dev, val, val2);
+ default:
+ return -EINVAL;
+ }
+}
+
+enum {
+ ADIS16460_SCAN_GYRO_X,
+ ADIS16460_SCAN_GYRO_Y,
+ ADIS16460_SCAN_GYRO_Z,
+ ADIS16460_SCAN_ACCEL_X,
+ ADIS16460_SCAN_ACCEL_Y,
+ ADIS16460_SCAN_ACCEL_Z,
+ ADIS16460_SCAN_TEMP,
+};
+
+#define ADIS16460_MOD_CHANNEL(_type, _mod, _address, _si, _bits) \
+ { \
+ .type = (_type), \
+ .modified = 1, \
+ .channel2 = (_mod), \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
+ .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
+ .address = (_address), \
+ .scan_index = (_si), \
+ .scan_type = { \
+ .sign = 's', \
+ .realbits = (_bits), \
+ .storagebits = (_bits), \
+ .endianness = IIO_BE, \
+ }, \
+ }
+
+#define ADIS16460_GYRO_CHANNEL(_mod) \
+ ADIS16460_MOD_CHANNEL(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \
+ ADIS16460_REG_ ## _mod ## _GYRO_LOW, ADIS16460_SCAN_GYRO_ ## _mod, \
+ 32)
+
+#define ADIS16460_ACCEL_CHANNEL(_mod) \
+ ADIS16460_MOD_CHANNEL(IIO_ACCEL, IIO_MOD_ ## _mod, \
+ ADIS16460_REG_ ## _mod ## _ACCL_LOW, ADIS16460_SCAN_ACCEL_ ## _mod, \
+ 32)
+
+#define ADIS16460_TEMP_CHANNEL() { \
+ .type = IIO_TEMP, \
+ .indexed = 1, \
+ .channel = 0, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
+ BIT(IIO_CHAN_INFO_SCALE) | \
+ BIT(IIO_CHAN_INFO_OFFSET), \
+ .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
+ .address = ADIS16460_REG_TEMP_OUT, \
+ .scan_index = ADIS16460_SCAN_TEMP, \
+ .scan_type = { \
+ .sign = 's', \
+ .realbits = 16, \
+ .storagebits = 16, \
+ .endianness = IIO_BE, \
+ }, \
+ }
+
+static const struct iio_chan_spec adis16460_channels[] = {
+ ADIS16460_GYRO_CHANNEL(X),
+ ADIS16460_GYRO_CHANNEL(Y),
+ ADIS16460_GYRO_CHANNEL(Z),
+ ADIS16460_ACCEL_CHANNEL(X),
+ ADIS16460_ACCEL_CHANNEL(Y),
+ ADIS16460_ACCEL_CHANNEL(Z),
+ ADIS16460_TEMP_CHANNEL(),
+ IIO_CHAN_SOFT_TIMESTAMP(7)
+};
+
+static const struct adis16460_chip_info adis16460_chip_info = {
+ .channels = adis16460_channels,
+ .num_channels = ARRAY_SIZE(adis16460_channels),
+ /*
+ * storing the value in rad/degree and the scale in degree
+ * gives us the result in rad and better precession than
+ * storing the scale directly in rad.
+ */
+ .gyro_max_val = IIO_RAD_TO_DEGREE(200 << 16),
+ .gyro_max_scale = 1,
+ .accel_max_val = IIO_M_S_2_TO_G(20000 << 16),
+ .accel_max_scale = 5,
+};
+
+static const struct iio_info adis16460_info = {
+ .read_raw = &adis16460_read_raw,
+ .write_raw = &adis16460_write_raw,
+ .update_scan_mode = adis_update_scan_mode,
+ .debugfs_reg_access = adis_debugfs_reg_access,
+};
+
+static int adis16460_enable_irq(struct adis *adis, bool enable)
+{
+ /*
+ * There is no way to gate the data-ready signal internally inside the
+ * ADIS16460 :(
+ */
+ if (enable)
+ enable_irq(adis->spi->irq);
+ else
+ disable_irq(adis->spi->irq);
+
+ return 0;
+}
+
+static int adis16460_initial_setup(struct iio_dev *indio_dev)
+{
+ struct adis16460 *st = iio_priv(indio_dev);
+ uint16_t prod_id;
+ unsigned int device_id;
+ int ret;
+
+ adis_reset(&st->adis);
+ msleep(222);
+
+ ret = adis_write_reg_16(&st->adis, ADIS16460_REG_GLOB_CMD, BIT(1));
+ if (ret)
+ return ret;
+ msleep(75);
+
+ ret = adis_check_status(&st->adis);
+ if (ret)
+ return ret;
+
+ ret = adis_read_reg_16(&st->adis, ADIS16460_REG_PROD_ID, &prod_id);
+ if (ret)
+ return ret;
+
+ ret = sscanf(indio_dev->name, "adis%u\n", &device_id);
+ if (ret != 1)
+ return -EINVAL;
+
+ if (prod_id != device_id)
+ dev_warn(&indio_dev->dev, "Device ID(%u) and product ID(%u) do not match.",
+ device_id, prod_id);
+
+ return 0;
+}
+
+#define ADIS16460_DIAG_STAT_IN_CLK_OOS 7
+#define ADIS16460_DIAG_STAT_FLASH_MEM 6
+#define ADIS16460_DIAG_STAT_SELF_TEST 5
+#define ADIS16460_DIAG_STAT_OVERRANGE 4
+#define ADIS16460_DIAG_STAT_SPI_COMM 3
+#define ADIS16460_DIAG_STAT_FLASH_UPT 2
+
+static const char * const adis16460_status_error_msgs[] = {
+ [ADIS16460_DIAG_STAT_IN_CLK_OOS] = "Input clock out of sync",
+ [ADIS16460_DIAG_STAT_FLASH_MEM] = "Flash memory failure",
+ [ADIS16460_DIAG_STAT_SELF_TEST] = "Self test diagnostic failure",
+ [ADIS16460_DIAG_STAT_OVERRANGE] = "Sensor overrange",
+ [ADIS16460_DIAG_STAT_SPI_COMM] = "SPI communication failure",
+ [ADIS16460_DIAG_STAT_FLASH_UPT] = "Flash update failure",
+};
+
+static const struct adis_data adis16460_data = {
+ .diag_stat_reg = ADIS16460_REG_DIAG_STAT,
+ .glob_cmd_reg = ADIS16460_REG_GLOB_CMD,
+ .has_paging = false,
+ .read_delay = 5,
+ .write_delay = 5,
+ .cs_change_delay = 16,
+ .status_error_msgs = adis16460_status_error_msgs,
+ .status_error_mask = BIT(ADIS16460_DIAG_STAT_IN_CLK_OOS) |
+ BIT(ADIS16460_DIAG_STAT_FLASH_MEM) |
+ BIT(ADIS16460_DIAG_STAT_SELF_TEST) |
+ BIT(ADIS16460_DIAG_STAT_OVERRANGE) |
+ BIT(ADIS16460_DIAG_STAT_SPI_COMM) |
+ BIT(ADIS16460_DIAG_STAT_FLASH_UPT),
+ .enable_irq = adis16460_enable_irq,
+};
+
+static int adis16460_probe(struct spi_device *spi)
+{
+ struct iio_dev *indio_dev;
+ struct adis16460 *st;
+ int ret;
+
+ indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
+ if (indio_dev == NULL)
+ return -ENOMEM;
+
+ spi_set_drvdata(spi, indio_dev);
+
+ st = iio_priv(indio_dev);
+
+ st->chip_info = &adis16460_chip_info;
+ indio_dev->dev.parent = &spi->dev;
+ indio_dev->name = spi_get_device_id(spi)->name;
+ indio_dev->channels = st->chip_info->channels;
+ indio_dev->num_channels = st->chip_info->num_channels;
+ indio_dev->info = &adis16460_info;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+
+ ret = adis_init(&st->adis, indio_dev, spi, &adis16460_data);
+ if (ret)
+ return ret;
+
+ ret = adis_setup_buffer_and_trigger(&st->adis, indio_dev, NULL);
+ if (ret)
+ return ret;
+
+ adis16460_enable_irq(&st->adis, 0);
+
+ ret = adis16460_initial_setup(indio_dev);
+ if (ret)
+ goto error_cleanup_buffer;
+
+ ret = iio_device_register(indio_dev);
+ if (ret)
+ goto error_cleanup_buffer;
+
+ adis16460_debugfs_init(indio_dev);
+
+ return 0;
+
+error_cleanup_buffer:
+ adis_cleanup_buffer_and_trigger(&st->adis, indio_dev);
+ return ret;
+}
+
+static int adis16460_remove(struct spi_device *spi)
+{
+ struct iio_dev *indio_dev = spi_get_drvdata(spi);
+ struct adis16460 *st = iio_priv(indio_dev);
+
+ iio_device_unregister(indio_dev);
+
+ adis_cleanup_buffer_and_trigger(&st->adis, indio_dev);
+
+ return 0;
+}
+
+static const struct spi_device_id adis16460_ids[] = {
+ { "adis16460", 0 },
+ {}
+};
+MODULE_DEVICE_TABLE(spi, adis16460_id);
+
+static const struct of_device_id adis16460_of_match[] = {
+ { .compatible = "adi,adis16460" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, adis16460_of_match);
+
+static struct spi_driver adis16460_driver = {
+ .driver = {
+ .name = "adis16460",
+ .of_match_table = adis16460_of_match,
+ },
+ .id_table = adis16460_ids,
+ .probe = adis16460_probe,
+ .remove = adis16460_remove,
+};
+module_spi_driver(adis16460_driver);
+
+MODULE_AUTHOR("Dragos Bogdan <dragos.bogdan@analog.com>");
+MODULE_DESCRIPTION("Analog Devices ADIS16460 IMU driver");
+MODULE_LICENSE("GPL");
--
2.20.1
^ permalink raw reply related
* [PATCH 3/3][V4] dt-bindings: iio: imu: add bindings for ADIS16460
From: Alexandru Ardelean @ 2019-07-23 7:36 UTC (permalink / raw)
To: linux-iio, linux-spi, devicetree, linux-kernel
Cc: jic23, robh+dt, mark.rutland, broonie, Alexandru Ardelean,
Rob Herring
In-Reply-To: <20190723073641.27801-1-alexandru.ardelean@analog.com>
This change adds device-tree bindings for the ADIS16460.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
.../bindings/iio/imu/adi,adis16460.yaml | 53 +++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 54 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml
diff --git a/Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml b/Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml
new file mode 100644
index 000000000000..0c53009ba7d6
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/imu/adi,adis16460.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices ADIS16460 and similar IMUs
+
+maintainers:
+ - Dragos Bogdan <dragos.bogdan@analog.com>
+
+description: |
+ Analog Devices ADIS16460 and similar IMUs
+ https://www.analog.com/media/en/technical-documentation/data-sheets/ADIS16460.pdf
+
+properties:
+ compatible:
+ enum:
+ - adi,adis16460
+
+ reg:
+ maxItems: 1
+
+ spi-cpha: true
+
+ spi-cpol: true
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ spi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ imu@0 {
+ compatible = "adi,adis16460";
+ reg = <0>;
+ spi-max-frequency = <5000000>;
+ spi-cpol;
+ spi-cpha;
+ interrupt-parent = <&gpio0>;
+ interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index f7de89e82e35..07105e43ea1e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -951,6 +951,7 @@ S: Supported
L: linux-iio@vger.kernel.org
W: http://ez.analog.com/community/linux-device-drivers
F: drivers/iio/imu/adis16460.c
+F: Documentation/devicetree/bindings/iio/imu/adi,adis16460.yaml
ANALOG DEVICES INC ADP5061 DRIVER
M: Stefan Popa <stefan.popa@analog.com>
--
2.20.1
^ permalink raw reply related
* Re: [PATCH] arm64: dts: imx8mq: fix SAI compatible
From: Daniel Baluta @ 2019-07-23 7:37 UTC (permalink / raw)
To: l.stach@pengutronix.de, shawnguo@kernel.org
Cc: devicetree@vger.kernel.org, patchwork-lst@pengutronix.de,
dl-linux-imx, kernel@pengutronix.de, festevam@gmail.com,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190723073342.GG15632@dragon>
On Tue, 2019-07-23 at 15:33 +0800, Shawn Guo wrote:
> Add Daniel for comment.
>
> On Wed, Jul 17, 2019 at 11:54:36AM +0200, Lucas Stach wrote:
> > The i.MX8M SAI block is not compatible with the i.MX6SX one, as the
> > register layout has changed due to two version registers being
> > added
> > at the beginning of the address map. Remove the bogus compatible.
> >
> > Fixes: 8c61538dc945 "arm64: dts: imx8mq: Add SAI2 node"
>
> The format should be the following. I can fix it when applying
> though.
>
> Fixes: 8c61538dc945 ("arm64: dts: imx8mq: Add SAI2 node")
>
> Shawn
>
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
^ permalink raw reply
* Re: [PATCH] arm64: dts: imx8mq: fix SAI compatible
From: Shawn Guo @ 2019-07-23 7:38 UTC (permalink / raw)
To: Lucas Stach
Cc: devicetree, patchwork-lst, NXP Linux Team, kernel, Fabio Estevam,
linux-arm-kernel
In-Reply-To: <20190717095436.28154-1-l.stach@pengutronix.de>
On Wed, Jul 17, 2019 at 11:54:36AM +0200, Lucas Stach wrote:
> The i.MX8M SAI block is not compatible with the i.MX6SX one, as the
> register layout has changed due to two version registers being added
> at the beginning of the address map. Remove the bogus compatible.
>
> Fixes: 8c61538dc945 "arm64: dts: imx8mq: Add SAI2 node"
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Applied, thanks.
^ permalink raw reply
* Re: [RFC,V2,1/2] media: dt-bindings: media: i2c: Add bindings for OV02A10
From: Sakari Ailus @ 2019-07-23 7:41 UTC (permalink / raw)
To: dongchun.zhu
Cc: mark.rutland, devicetree, srv_heupstream, shengnan.wang,
--to=drinkcat, tfiga, louis.kuo, sj.huang, robh+dt,
linux-mediatek, matthias.bgg, bingbu.cao, mchehab,
linux-arm-kernel, linux-media
In-Reply-To: <20190704084651.3105-2-dongchun.zhu@mediatek.com>
Hi Dongchun,
On Thu, Jul 04, 2019 at 04:46:50PM +0800, dongchun.zhu@mediatek.com wrote:
> From: Dongchun Zhu <dongchun.zhu@mediatek.com>
>
> Add device tree binding documentation for the OV02A10 camera sensor.
>
> Signed-off-by: Dongchun Zhu <dongchun.zhu@mediatek.com>
> ---
> .../devicetree/bindings/media/i2c/ov02a10.txt | 43 ++++++++++++++++++++++
> MAINTAINERS | 7 ++++
> 2 files changed, 50 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/i2c/ov02a10.txt
>
> diff --git a/Documentation/devicetree/bindings/media/i2c/ov02a10.txt b/Documentation/devicetree/bindings/media/i2c/ov02a10.txt
> new file mode 100644
> index 0000000..d40aa87
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/i2c/ov02a10.txt
> @@ -0,0 +1,43 @@
> +* Omnivision OV02A10 MIPI CSI-2 sensor
> +
> +Required Properties:
> +- compatible: shall be "ovti,ov02a10"
> +- clocks: reference to the xvclk input clock
> +- clock-names: shall be "xvclk"
> +- avdd-supply: Analog voltage supply, 2.8 volts
> +- dovdd-supply: Digital I/O voltage supply, 1.8 volts
> +- dvdd-supply: Digital core voltage supply, 1.8 volts
> +- reset-gpios: Low active reset gpio
> +
> +The device node shall contain one 'port' child node with an
> +'endpoint' subnode for its digital output video port,
> +in accordance with the video interface bindings defined in
> +Documentation/devicetree/bindings/media/video-interfaces.txt.
> +The endpoint optional property 'data-lanes' shall be "<1>".
How many lanes does the module (or the sensor) have?
> +
> +Example:
> +&i2c4 {
> + ov02a10: camera-sensor@3d {
> + compatible = "ovti,ov02a10";
> + reg = <0x3d>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&camera_pins_cam1_mclk_on>;
> +
> + clocks = <&topckgen CLK_TOP_MUX_CAMTG2>,
> + <&topckgen CLK_TOP_UNIVP_192M_D8>;
> + clock-names = "xvclk", "freq_mux";
> +
> + avdd-supply = <&mt6358_vcama1_reg>;
> + dvdd-supply = <&mt6358_vcn18_reg>;
> + dovdd-supply = <&mt6358_vcamio_reg>;
> + pwdn-gpios = <&pio 107 1>;
> + reset-gpios = <&pio 109 1>;
> +
> + port {
> + ov02a10_core: endpoint {
> + remote-endpoint = <&ov02a10_0>;
Indentation is still wrong. :-(
> + data-lanes = <1>;
> + };
> + };
> + };
> +};
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 5cfbea4..62b81ff 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -11571,6 +11571,13 @@ T: git git://linuxtv.org/media_tree.git
> S: Maintained
> F: drivers/media/i2c/ov13858.c
>
> +OMNIVISION OV02A10 SENSOR DRIVER
> +M: Dongchun Zhu <dongchun.zhu@mediatek.com>
> +L: linux-media@vger.kernel.org
> +T: git git://linuxtv.org/media_tree.git
> +S: Maintained
> +F: Documentation/devicetree/bindings/media/i2c/ov02a10.txt
> +
> OMNIVISION OV2680 SENSOR DRIVER
> M: Rui Miguel Silva <rmfrfs@gmail.com>
> L: linux-media@vger.kernel.org
--
Kind regards,
Sakari Ailus
sakari.ailus@linux.intel.com
^ permalink raw reply
* Re: [PATCH v2 02/10] iio: document bindings for mounting matrices
From: Linus Walleij @ 2019-07-23 7:42 UTC (permalink / raw)
To: H. Nikolaus Schaller
Cc: Jonathan Cameron, Rob Herring, Mark Rutland, Andy Shevchenko,
Charles Keepax, Song Qiang, Jean-Baptiste Maneyrol, Martin Kelly,
Jonathan Marek, Brian Masney, Stephan Gerhold,
Discussions about the Letux Kernel, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, linux-iio,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
In-Reply-To: <32025b2a8ccc97cc01f8115ee962529eb5990f00.1550768574.git.hns@goldelico.com>
Hi H. Nikolaus,
On Thu, Feb 21, 2019 at 6:03 PM H. Nikolaus Schaller <hns@goldelico.com> wrote:
> From: Linus Walleij <linus.walleij@linaro.org>
It is fair for you to change authorship to yourself at this point.
Just keeping my Signed-off-by is sufficient.
> The mounting matrix for sensors was introduced in
> commit dfc57732ad38 ("iio:core: mounting matrix support")
>
> However the device tree bindings are very terse and since this is
> a widely applicable property, we need a proper binding for it
> that the other bindings can reference. This will also be useful
> for other operating systems and sensor engineering at large.
>
> I think all 3D sensors should support it, the current situation
> is probably that the mounting information is confined in magic
> userspace components rather than using the mounting matrix, which
> is not good for portability and reuse.
>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Gregor Boirie <gregor.boirie@parrot.com>
> Cc: Sebastian Reichel <sre@kernel.org>
> Cc: Samu Onkalo <samu.onkalo@intel.com>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
Did this patch fall off somewhere? I think it's really neat, even in this
form it is great help for developers. If you want I can try picking up the
comments and resend it.
Linus Walleij
^ permalink raw reply
* Re: [PATCH 1/4] ARM: dts: imx6sx: move GIC to right location in DT
From: Shawn Guo @ 2019-07-23 7:48 UTC (permalink / raw)
To: Anson.Huang
Cc: robh+dt, mark.rutland, s.hauer, kernel, festevam, devicetree,
linux-arm-kernel, linux-kernel, Linux-imx
In-Reply-To: <20190718091508.3248-1-Anson.Huang@nxp.com>
On Thu, Jul 18, 2019 at 05:15:05PM +0800, Anson.Huang@nxp.com wrote:
> From: Anson Huang <Anson.Huang@nxp.com>
>
> GIC is inside of SoC from architecture perspective, it should
> be located inside of soc node in DT.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Applied all, thanks.
^ permalink raw reply
* Re: [PATCH 1/3] clk: imx8: Add DSP related clocks
From: Shawn Guo @ 2019-07-23 7:59 UTC (permalink / raw)
To: Daniel Baluta
Cc: robh+dt, mark.rutland, s.hauer, kernel, festevam, linux-imx,
shengjiu.wang, paul.olaru, aisheng.dong, leonard.crestez,
anson.huang, peng.fan, Frank.Li, devicetree, linux-arm-kernel,
linux-kernel, sound-open-firmware
In-Reply-To: <20190718151346.3523-2-daniel.baluta@nxp.com>
On Thu, Jul 18, 2019 at 06:13:44PM +0300, Daniel Baluta wrote:
> i.MX8QXP contains Hifi4 DSP. There are four clocks
> associated with DSP:
> * dsp_lpcg_core_clk
> * dsp_lpcg_ipg_clk
> * dsp_lpcg_adb_aclk
> * ocram_lpcg_ipg_clk
>
> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
I already picked this one up, so you do not need to include it in the
series any more.
Shawn
^ permalink raw reply
* Re: [PATCH v2] arm: dts: imx6qdl: add gpio expander pca9535
From: Shawn Guo @ 2019-07-23 8:02 UTC (permalink / raw)
To: Marco Felsch
Cc: Gilles DOFFE, mark.rutland, devicetree, s.hauer, rennes,
linux-kernel, robh+dt, linux-imx, kernel, jerome.oufella,
festevam, linux-arm-kernel
In-Reply-To: <20190722075341.e4ve45rneusiogtk@pengutronix.de>
On Mon, Jul 22, 2019 at 09:53:41AM +0200, Marco Felsch wrote:
> Hi Gilles,
>
> can you adapt the patch title, I assumed that the base dtsi is adding a
> gpio-expander which makes no sense.
More specifically, the prefix should be something like:
'ARM: dts: imx6qdl-rex: ...'
Shawn
^ permalink raw reply
* Re: [PATCH v2 3/3] arm64: dts: freescale: Add support for i.MX8QXP AI_ML board
From: Shawn Guo @ 2019-07-23 8:10 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: s.hauer, robh+dt, kernel, festevam, linux-imx, devicetree,
linux-arm-kernel, linux-kernel, Darshak.Patel, kinjan.patel,
prajose.john
In-Reply-To: <20190719070926.29114-4-manivannan.sadhasivam@linaro.org>
On Fri, Jul 19, 2019 at 12:39:26PM +0530, Manivannan Sadhasivam wrote:
> Add support for i.MX8QXP AI_ML board from Einfochips. This board is one
> of the Consumer Edition boards of the 96Boards family based on i.MX8QXP
> SoC from NXP/Freescale.
>
> The initial support includes following peripherals which are tested and
> known to be working:
>
> 1. Debug serial via UART2
> 2. uSD
> 3. WiFi
> 4. Ethernet
>
> More information about this board can be found in Arrow website:
> https://www.arrow.com/en/products/imx8-ai-ml/arrow-development-tools
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> .../boot/dts/freescale/imx8qxp-ai_ml.dts | 249 ++++++++++++++++++
> 2 files changed, 250 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 0bd122f60549..bd8460549d1a 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -24,4 +24,5 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
> new file mode 100644
> index 000000000000..3dc8757d9c42
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
> @@ -0,0 +1,249 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 Einfochips
> + * Copyright 2019 Linaro Ltd.
> + */
> +
> +/dts-v1/;
> +
> +#include "imx8qxp.dtsi"
> +
> +/ {
> + model = "Einfochips i.MX8QXP AI_ML";
> + compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp";
> +
> + aliases {
> + serial1 = &adma_lpuart1;
> + serial2 = &adma_lpuart2;
> + serial3 = &adma_lpuart3;
> + };
> +
> + chosen {
> + stdout-path = &adma_lpuart2;
> + };
> +
> + memory@80000000 {
> + device_type = "memory";
> + reg = <0x00000000 0x80000000 0 0x80000000>;
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_leds>;
> +
> + user_led1 {
> + label = "green:user1";
> + gpios = <&lsio_gpio4 16 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "heartbeat";
> + };
> +
> + user_led2 {
> + label = "green:user2";
> + gpios = <&lsio_gpio0 6 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "none";
> + };
> +
> + user_led3 {
> + label = "green:user3";
> + gpios = <&lsio_gpio0 7 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "mmc1";
> + default-state = "off";
> + };
> +
> + user_led4 {
> + label = "green:user4";
> + gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
> + panic-indicator;
> + linux,default-trigger = "none";
> + };
> +
> + wlan_active_led {
> + label = "yellow:wlan";
> + gpios = <&lsio_gpio4 17 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "phy0tx";
> + default-state = "off";
> + };
> +
> + bt_active_led {
We prefer to use hyphen over underscore in node names. I fixed them up
and applied the series.
Shawn
> + label = "blue:bt";
> + gpios = <&lsio_gpio4 18 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "hci0-power";
> + default-state = "off";
> + };
> + };
> +
> + sdio_pwrseq: sdio-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wifi_reg_on>;
> + reset-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_LOW>;
> + };
> +};
> +
> +/* BT */
> +&adma_lpuart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lpuart0>;
> + uart-has-rtscts;
> + status = "okay";
> +};
> +
> +/* LS-UART0 */
> +&adma_lpuart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lpuart1>;
> + status = "okay";
> +};
> +
> +/* Debug */
> +&adma_lpuart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lpuart2>;
> + status = "okay";
> +};
> +
> +/* PCI-E UART */
> +&adma_lpuart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_lpuart3>;
> + status = "okay";
> +};
> +
> +&fec1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_fec1>;
> + phy-mode = "rgmii-id";
> + phy-handle = <ðphy0>;
> + fsl,magic-packet;
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy0: ethernet-phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + };
> + };
> +};
> +
> +/* WiFi */
> +&usdhc1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + bus-width = <4>;
> + no-sd;
> + non-removable;
> + mmc-pwrseq = <&sdio_pwrseq>;
> + status = "okay";
> +
> + brcmf: wifi@1 {
> + reg = <1>;
> + compatible = "brcm,bcm4329-fmac";
> + };
> +};
> +
> +/* SD */
> +&usdhc2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc2>;
> + bus-width = <4>;
> + cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
> + status = "okay";
> +};
> +
> +&iomuxc {
> + pinctrl_fec1: fec1grp {
> + fsl,pins = <
> + IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
> + IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
> + IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
> + IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
> + IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
> + IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
> + IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
> + IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
> + IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
> + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
> + IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
> + IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
> + IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
> + IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
> + >;
> + };
> +
> + pinctrl_leds: ledsgrp{
> + fsl,pins = <
> + IMX8QXP_ESAI0_TX2_RX3_LSIO_GPIO0_IO06 0x00000021
> + IMX8QXP_ESAI0_TX3_RX2_LSIO_GPIO0_IO07 0x00000021
> + IMX8QXP_EMMC0_DATA7_LSIO_GPIO4_IO16 0x00000021
> + IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021
> + IMX8QXP_EMMC0_STROBE_LSIO_GPIO4_IO17 0x00000021
> + IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18 0x00000021
> + >;
> + };
> +
> + pinctrl_lpuart0: lpuart0grp {
> + fsl,pins = <
> + IMX8QXP_UART0_RX_ADMA_UART0_RX 0X06000020
> + IMX8QXP_UART0_TX_ADMA_UART0_TX 0X06000020
> + IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020
> + IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020
> + >;
> + };
> +
> + pinctrl_lpuart1: lpuart1grp {
> + fsl,pins = <
> + IMX8QXP_UART1_RX_ADMA_UART1_RX 0X06000020
> + IMX8QXP_UART1_TX_ADMA_UART1_TX 0X06000020
> + >;
> + };
> +
> + pinctrl_lpuart2: lpuart2grp {
> + fsl,pins = <
> + IMX8QXP_UART2_RX_ADMA_UART2_RX 0X06000020
> + IMX8QXP_UART2_TX_ADMA_UART2_TX 0X06000020
> + >;
> + };
> +
> + pinctrl_lpuart3: lpuart3grp {
> + fsl,pins = <
> + IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0X06000020
> + IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0X06000020
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
> + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
> + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
> + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
> + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
> + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
> + >;
> + };
> +
> + pinctrl_usdhc2: usdhc2grp {
> + fsl,pins = <
> + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
> + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
> + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
> + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
> + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
> + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
> + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
> + IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021
> + >;
> + };
> +
> + pinctrl_wifi_reg_on: wifiregongrp {
> + fsl,pins = <
> + IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x00000021
> + >;
> + };
> +};
> --
> 2.17.1
>
^ permalink raw reply
* Re: [v2 3/3] dts: arm64: ls1028a: Add optional property node for Mali DP500
From: Shawn Guo @ 2019-07-23 8:12 UTC (permalink / raw)
To: Wen He
Cc: linux-kernel, devicetree, mark.rutland, liviu.dudau, robh+dt,
leoyang.li
In-Reply-To: <20190719095956.11774-1-wen.he_1@nxp.com>
On Fri, Jul 19, 2019 at 05:59:56PM +0800, Wen He wrote:
> This patch use the optional property node "arm,malidp-arqos-value" to
> can be dynamic configure QoS signaling.
>
> Signed-off-by: Wen He <wen.he_1@nxp.com>
Applied, thanks.
^ permalink raw reply
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