* Re: [PATCH 3/5] arm64: dts: qcom: sdm845: remove unit name for thermal trip points
From: Stephen Boyd @ 2019-07-23 14:47 UTC (permalink / raw)
To: Andy Gross
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, Rob Herring,
Mark Rutland, devicetree, linux-kernel
In-Reply-To: <20190722123422.4571-4-vkoul@kernel.org>
Quoting Vinod Koul (2019-07-22 05:34:20)
> The thermal trip points have unit name but no reg property, so we can
> remove them
>
> arch/arm64/boot/dts/qcom/sdm845.dtsi:2824.31-2828.7: Warning (unit_address_vs_reg): /thermal-zones/cpu0-thermal/trips/trip-point@0: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:2830.31-2834.7: Warning (unit_address_vs_reg): /thermal-zones/cpu0-thermal/trips/trip-point@1: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:2868.31-2872.7: Warning (unit_address_vs_reg): /thermal-zones/cpu1-thermal/trips/trip-point@0: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:2874.31-2878.7: Warning (unit_address_vs_reg): /thermal-zones/cpu1-thermal/trips/trip-point@1: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:2912.31-2916.7: Warning (unit_address_vs_reg): /thermal-zones/cpu2-thermal/trips/trip-point@0: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:2918.31-2922.7: Warning (unit_address_vs_reg): /thermal-zones/cpu2-thermal/trips/trip-point@1: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:2956.31-2960.7: Warning (unit_address_vs_reg): /thermal-zones/cpu3-thermal/trips/trip-point@0: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:2962.31-2966.7: Warning (unit_address_vs_reg): /thermal-zones/cpu3-thermal/trips/trip-point@1: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:3000.31-3004.7: Warning (unit_address_vs_reg): /thermal-zones/cpu4-thermal/trips/trip-point@0: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:3006.31-3010.7: Warning (unit_address_vs_reg): /thermal-zones/cpu4-thermal/trips/trip-point@1: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:3044.31-3048.7: Warning (unit_address_vs_reg): /thermal-zones/cpu5-thermal/trips/trip-point@0: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:3050.31-3054.7: Warning (unit_address_vs_reg): /thermal-zones/cpu5-thermal/trips/trip-point@1: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:3088.31-3092.7: Warning (unit_address_vs_reg): /thermal-zones/cpu6-thermal/trips/trip-point@0: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:3094.31-3098.7: Warning (unit_address_vs_reg): /thermal-zones/cpu6-thermal/trips/trip-point@1: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:3132.31-3136.7: Warning (unit_address_vs_reg): /thermal-zones/cpu7-thermal/trips/trip-point@0: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:3138.31-3142.7: Warning (unit_address_vs_reg): /thermal-zones/cpu7-thermal/trips/trip-point@1: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:3176.32-3180.7: Warning (unit_address_vs_reg): /thermal-zones/aoss0-thermal/trips/trip-point@0: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:3191.35-3195.7: Warning (unit_address_vs_reg): /thermal-zones/cluster0-thermal/trips/trip-point@0: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:3211.35-3215.7: Warning (unit_address_vs_reg): /thermal-zones/cluster1-thermal/trips/trip-point@0: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:3231.31-3235.7: Warning (unit_address_vs_reg): /thermal-zones/gpu-thermal-top/trips/trip-point@0: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:3246.31-3250.7: Warning (unit_address_vs_reg): /thermal-zones/gpu-thermal-bottom/trips/trip-point@0: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:3261.32-3265.7: Warning (unit_address_vs_reg): /thermal-zones/aoss1-thermal/trips/trip-point@0: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:3276.35-3280.7: Warning (unit_address_vs_reg): /thermal-zones/q6-modem-thermal/trips/trip-point@0: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:3291.30-3295.7: Warning (unit_address_vs_reg): /thermal-zones/mem-thermal/trips/trip-point@0: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:3306.31-3310.7: Warning (unit_address_vs_reg): /thermal-zones/wlan-thermal/trips/trip-point@0: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:3321.33-3325.7: Warning (unit_address_vs_reg): /thermal-zones/q6-hvx-thermal/trips/trip-point@0: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:3336.33-3340.7: Warning (unit_address_vs_reg): /thermal-zones/camera-thermal/trips/trip-point@0: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:3351.32-3355.7: Warning (unit_address_vs_reg): /thermal-zones/video-thermal/trips/trip-point@0: node has a unit name, but no reg property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:3366.32-3370.7: Warning (unit_address_vs_reg): /thermal-zones/modem-thermal/trips/trip-point@0: node has a unit name, but no reg property
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
^ permalink raw reply
* Re: [PATCH 3/4] ARM: dts: am33xx: Add nodes for eQEP
From: David Lechner @ 2019-07-23 14:45 UTC (permalink / raw)
To: Tony Lindgren
Cc: linux-iio, linux-omap, devicetree, Rob Herring, Mark Rutland,
Benoît Cousson, William Breathitt Gray, Thierry Reding,
linux-kernel, linux-pwm
In-Reply-To: <20190723084213.GR5447@atomide.com>
On 7/23/19 3:42 AM, Tony Lindgren wrote:
> * David Lechner <david@lechnology.com> [190722 15:46]:
>> This adds new nodes for the Texas Instruments Enhanced Quadrature
>> Encoder Pulse (eQEP) module in the PWM subsystem on AM33XX.
>>
>> Signed-off-by: David Lechner <david@lechnology.com>
>> ---
>> arch/arm/boot/dts/am33xx-l4.dtsi | 27 +++++++++++++++++++++++++++
>> 1 file changed, 27 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi
>> index 3b1fb2ba4dff..7fdc2f61c553 100644
>> --- a/arch/arm/boot/dts/am33xx-l4.dtsi
>> +++ b/arch/arm/boot/dts/am33xx-l4.dtsi
>> @@ -1908,6 +1908,15 @@
>> status = "disabled";
>> };
>>
>> + eqep0: eqep@180 {
>> + compatible = "ti,am3352-eqep";
>> + reg = <0x180 0x80>;
>> + clocks = <&l4ls_gclk>;
>> + clock-names = "fck";
>> + interrupts = <79>;
>> + status = "disabled";
>> + };
>> +
>
> You probably no longer need to map any clocks here as this> is now a child of the interconnect target module managed
> by ti-sysc driver. I have not checked but probably l4ls_gclk
> is same as clocks = <&l4ls_clkctrl AM3_L4LS_EPWMSS0_CLKCTRL 0>
> already managed by ti-sysc. If so, then just using runtime PM
> calls in any of the child device drivers will keep it enabled.
>
> If l4ls_gclk is a separate functional clock, then it still
> needs to be managed by the child device driver directly.
The clock is included so that we can get the clock rate for
the timing aspects of the eQEP, not for power management.
I chose to use the "fck" name to be consistent with the
sibling EHRPWM and ECAP nodes that already have the same
bindings for the same clock.
^ permalink raw reply
* Re: [PATCH 2/5] arm64: dts: qcom: sdm845: remove unnecessary properties for dsi nodes
From: Stephen Boyd @ 2019-07-23 14:45 UTC (permalink / raw)
To: Andy Gross
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, Rob Herring,
Mark Rutland, devicetree, linux-kernel
In-Reply-To: <20190722123422.4571-3-vkoul@kernel.org>
Quoting Vinod Koul (2019-07-22 05:34:19)
> We get a warning about unnecessary properties of
>
> arch/arm64/boot/dts/qcom/sdm845.dtsi:2211.22-2257.6: Warning (avoid_unnecessary_addr_size): /soc/mdss@ae00000/dsi@ae94000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
> arch/arm64/boot/dts/qcom/sdm845.dtsi:2278.22-2324.6: Warning (avoid_unnecessary_addr_size): /soc/mdss@ae00000/dsi@ae96000: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property
>
> So, remove these properties
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
^ permalink raw reply
* Re: [PATCH V13 12/12] PCI: tegra: Add Tegra194 PCIe support
From: Vidya Sagar @ 2019-07-23 14:44 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: bhelgaas, robh+dt, mark.rutland, thierry.reding, jonathanh,
kishon, catalin.marinas, will.deacon, jingoohan1,
gustavo.pimentel, digetx, mperttunen, linux-pci, devicetree,
linux-tegra, linux-kernel, linux-arm-kernel, kthota, mmaddireddy,
sagar.tv
In-Reply-To: <20190716112225.GA24335@e121166-lin.cambridge.arm.com>
On 7/16/2019 4:52 PM, Lorenzo Pieralisi wrote:
> On Sat, Jul 13, 2019 at 12:34:34PM +0530, Vidya Sagar wrote:
>
> [...]
>
>>>>>> +static int tegra_pcie_bpmp_set_ctrl_state(struct tegra_pcie_dw *pcie,
>>>>>> + bool enable)
>>>>>> +{
>>>>>> + struct mrq_uphy_response resp;
>>>>>> + struct tegra_bpmp_message msg;
>>>>>> + struct mrq_uphy_request req;
>>>>>> + int err;
>>>>>> +
>>>>>> + if (pcie->cid == 5)
>>>>>> + return 0;
>>>>>
>>>>> What's wrong with cid == 5 ? Explain please.
>>>> Controller with ID=5 doesn't need any programming to enable it which is
>>>> done here through calling firmware API.
>>>>
>>>>>
>>>>>> + memset(&req, 0, sizeof(req));
>>>>>> + memset(&resp, 0, sizeof(resp));
>>>>>> +
>>>>>> + req.cmd = CMD_UPHY_PCIE_CONTROLLER_STATE;
>>>>>> + req.controller_state.pcie_controller = pcie->cid;
>>>>>> + req.controller_state.enable = enable;
>>>>>> +
>>>>>> + memset(&msg, 0, sizeof(msg));
>>>>>> + msg.mrq = MRQ_UPHY;
>>>>>> + msg.tx.data = &req;
>>>>>> + msg.tx.size = sizeof(req);
>>>>>> + msg.rx.data = &resp;
>>>>>> + msg.rx.size = sizeof(resp);
>>>>>> +
>>>>>> + if (irqs_disabled())
>>>>>
>>>>> Can you explain to me what this check is meant to achieve please ?
>>>> Firmware interface provides different APIs to be called when there are
>>>> no interrupts enabled in the system (noirq context) and otherwise
>>>> hence checking that situation here and calling appropriate API.
>>>
>>> That's what I am questioning. Being called from {suspend/resume}_noirq()
>>> callbacks (if that's the code path this check caters for) does not mean
>>> irqs_disabled() == true.
>> Agree.
>> Actually, I got a hint of having this check from the following.
>> Both tegra_bpmp_transfer_atomic() and tegra_bpmp_transfer() are indirectly
>> called by APIs registered with .master_xfer() and .master_xfer_atomic() hooks of
>> struct i2c_algorithm and the decision to call which one of these is made using the
>> following check in i2c-core.h file.
>> static inline bool i2c_in_atomic_xfer_mode(void)
>> {
>> return system_state > SYSTEM_RUNNING && irqs_disabled();
>> }
>> I think I should use this condition as is IIUC.
>> Please let me know if there are any concerns with this.
>
> It is not a concern, it is just that I don't understand how this code
> can be called with IRQs disabled, if you can give me an execution path I
> am happy to leave the check there. On top of that, when called from
> suspend NOIRQ context, it is likely to use the blocking API (because
> IRQs aren't disabled at CPU level) behind which there is most certainly
> an IRQ required to wake the thread up and if the IRQ in question was
> disabled in the suspend NOIRQ phase this code is likely to deadlock.
>
> I want to make sure we can justify adding this check, I do not
> want to add it because we think it can be needed when it may not
> be needed at all (and it gets copy and pasted over and over again
> in other drivers).
I had a discussion internally about this and the prescribed usage of these APIs
seem to be that
use tegra_bpmp_transfer() in .probe() and other paths where interrupts are
enabled as this API needs interrupts to be enabled for its working.
Use tegra_bpmp_transfer_atomic() surrounded by local_irq_save()/local_irq_restore()
in other paths where interrupt servicing is disabled.
I'll go ahead and make next patch series with this if this looks fine to you.
>
>>> Actually, if tegra_bpmp_transfer() requires IRQs to be enabled you may
>>> even end up in a situation where that blocking call does not wake up
>>> because the IRQ in question was disabled in the NOIRQ suspend/resume
>>> phase.
>>>
>>> [...]
>>>
>>>>>> +static int tegra_pcie_dw_probe(struct platform_device *pdev)
>>>>>> +{
>>>>>> + const struct tegra_pcie_soc *data;
>>>>>> + struct device *dev = &pdev->dev;
>>>>>> + struct resource *atu_dma_res;
>>>>>> + struct tegra_pcie_dw *pcie;
>>>>>> + struct resource *dbi_res;
>>>>>> + struct pcie_port *pp;
>>>>>> + struct dw_pcie *pci;
>>>>>> + struct phy **phys;
>>>>>> + char *name;
>>>>>> + int ret;
>>>>>> + u32 i;
>>>>>> +
>>>>>> + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
>>>>>> + if (!pcie)
>>>>>> + return -ENOMEM;
>>>>>> +
>>>>>> + pci = &pcie->pci;
>>>>>> + pci->dev = &pdev->dev;
>>>>>> + pci->ops = &tegra_dw_pcie_ops;
>>>>>> + pp = &pci->pp;
>>>>>> + pcie->dev = &pdev->dev;
>>>>>> +
>>>>>> + data = (struct tegra_pcie_soc *)of_device_get_match_data(dev);
>>>>>> + if (!data)
>>>>>> + return -EINVAL;
>>>>>> + pcie->mode = (enum dw_pcie_device_mode)data->mode;
>>>>>> +
>>>>>> + ret = tegra_pcie_dw_parse_dt(pcie);
>>>>>> + if (ret < 0) {
>>>>>> + dev_err(dev, "Failed to parse device tree: %d\n", ret);
>>>>>> + return ret;
>>>>>> + }
>>>>>> +
>>>>>> + pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl");
>>>>>> + if (IS_ERR(pcie->pex_ctl_supply)) {
>>>>>> + dev_err(dev, "Failed to get regulator: %ld\n",
>>>>>> + PTR_ERR(pcie->pex_ctl_supply));
>>>>>> + return PTR_ERR(pcie->pex_ctl_supply);
>>>>>> + }
>>>>>> +
>>>>>> + pcie->core_clk = devm_clk_get(dev, "core");
>>>>>> + if (IS_ERR(pcie->core_clk)) {
>>>>>> + dev_err(dev, "Failed to get core clock: %ld\n",
>>>>>> + PTR_ERR(pcie->core_clk));
>>>>>> + return PTR_ERR(pcie->core_clk);
>>>>>> + }
>>>>>> +
>>>>>> + pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
>>>>>> + "appl");
>>>>>> + if (!pcie->appl_res) {
>>>>>> + dev_err(dev, "Failed to find \"appl\" region\n");
>>>>>> + return PTR_ERR(pcie->appl_res);
>>>>>> + }
>>>>>> + pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res);
>>>>>> + if (IS_ERR(pcie->appl_base))
>>>>>> + return PTR_ERR(pcie->appl_base);
>>>>>> +
>>>>>> + pcie->core_apb_rst = devm_reset_control_get(dev, "apb");
>>>>>> + if (IS_ERR(pcie->core_apb_rst)) {
>>>>>> + dev_err(dev, "Failed to get APB reset: %ld\n",
>>>>>> + PTR_ERR(pcie->core_apb_rst));
>>>>>> + return PTR_ERR(pcie->core_apb_rst);
>>>>>> + }
>>>>>> +
>>>>>> + phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL);
>>>>>> + if (!phys)
>>>>>> + return PTR_ERR(phys);
>>>>>> +
>>>>>> + for (i = 0; i < pcie->phy_count; i++) {
>>>>>> + name = kasprintf(GFP_KERNEL, "p2u-%u", i);
>>>>>> + if (!name) {
>>>>>> + dev_err(dev, "Failed to create P2U string\n");
>>>>>> + return -ENOMEM;
>>>>>> + }
>>>>>> + phys[i] = devm_phy_get(dev, name);
>>>>>> + kfree(name);
>>>>>> + if (IS_ERR(phys[i])) {
>>>>>> + ret = PTR_ERR(phys[i]);
>>>>>> + dev_err(dev, "Failed to get PHY: %d\n", ret);
>>>>>> + return ret;
>>>>>> + }
>>>>>> + }
>>>>>> +
>>>>>> + pcie->phys = phys;
>>>>>> +
>>>>>> + dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
>>>>>> + if (!dbi_res) {
>>>>>> + dev_err(dev, "Failed to find \"dbi\" region\n");
>>>>>> + return PTR_ERR(dbi_res);
>>>>>> + }
>>>>>> + pcie->dbi_res = dbi_res;
>>>>>> +
>>>>>> + pci->dbi_base = devm_ioremap_resource(dev, dbi_res);
>>>>>> + if (IS_ERR(pci->dbi_base))
>>>>>> + return PTR_ERR(pci->dbi_base);
>>>>>> +
>>>>>> + /* Tegra HW locates DBI2 at a fixed offset from DBI */
>>>>>> + pci->dbi_base2 = pci->dbi_base + 0x1000;
>>>>>> +
>>>>>> + atu_dma_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
>>>>>> + "atu_dma");
>>>>>> + if (!atu_dma_res) {
>>>>>> + dev_err(dev, "Failed to find \"atu_dma\" region\n");
>>>>>> + return PTR_ERR(atu_dma_res);
>>>>>> + }
>>>>>> + pcie->atu_dma_res = atu_dma_res;
>>>>>> + pci->atu_base = devm_ioremap_resource(dev, atu_dma_res);
>>>>>> + if (IS_ERR(pci->atu_base))
>>>>>> + return PTR_ERR(pci->atu_base);
>>>>>> +
>>>>>> + pcie->core_rst = devm_reset_control_get(dev, "core");
>>>>>> + if (IS_ERR(pcie->core_rst)) {
>>>>>> + dev_err(dev, "Failed to get core reset: %ld\n",
>>>>>> + PTR_ERR(pcie->core_rst));
>>>>>> + return PTR_ERR(pcie->core_rst);
>>>>>> + }
>>>>>> +
>>>>>> + pp->irq = platform_get_irq_byname(pdev, "intr");
>>>>>> + if (!pp->irq) {
>>>>>> + dev_err(dev, "Failed to get \"intr\" interrupt\n");
>>>>>> + return -ENODEV;
>>>>>> + }
>>>>>> +
>>>>>> + ret = devm_request_irq(dev, pp->irq, tegra_pcie_irq_handler,
>>>>>> + IRQF_SHARED, "tegra-pcie-intr", pcie);
>>>>>> + if (ret) {
>>>>>> + dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, ret);
>>>>>> + return ret;
>>>>>> + }
>>>>>> +
>>>>>> + pcie->bpmp = tegra_bpmp_get(dev);
>>>>>> + if (IS_ERR(pcie->bpmp))
>>>>>> + return PTR_ERR(pcie->bpmp);
>>>>>> +
>>>>>> + platform_set_drvdata(pdev, pcie);
>>>>>> +
>>>>>> + if (pcie->mode == DW_PCIE_RC_TYPE) {
>>>>>> + ret = tegra_pcie_config_rp(pcie);
>>>>>> + if (ret && ret != -ENOMEDIUM)
>>>>>> + goto fail;
>>>>>> + else
>>>>>> + return 0;
>>>>>
>>>>> So if the link is not up we still go ahead and make probe
>>>>> succeed. What for ?
>>>> We may need root port to be available to support hot-plugging of
>>>> endpoint devices, so, we don't fail the probe.
>>>
>>> We need it or we don't. If you do support hotplugging of endpoint
>>> devices point me at the code, otherwise link up failure means
>>> failure to probe.
>> Currently hotplugging of endpoint is not supported, but it is one of
>> the use cases that we may add support for in future.
>
> You should elaborate on this, I do not understand what you mean,
> either the root port(s) supports hotplug or it does not.
>
>> But, why should we fail probe if link up doesn't happen? As such,
>> nothing went wrong in terms of root port initialization right? I
>> checked other DWC based implementations and following are not failing
>> the probe pci-dra7xx.c, pcie-armada8k.c, pcie-artpec6.c, pcie-histb.c,
>> pcie-kirin.c, pcie-spear13xx.c, pci-exynos.c, pci-imx6.c,
>> pci-keystone.c, pci-layerscape.c
>>
>> Although following do fail the probe if link is not up. pcie-qcom.c,
>> pcie-uniphier.c, pci-meson.c
>>
>> So, to me, it looks more like a choice we can make whether to fail the
>> probe or not and in this case we are choosing not to fail.
>
> I disagree. I had an offline chat with Bjorn and whether link-up should
> fail the probe or not depends on whether the root port(s) is hotplug
> capable or not and this in turn relies on the root port "Slot
> implemented" bit in the PCI Express capabilities register.
>
> It is a choice but it should be based on evidence.
>
> Lorenzo
With Bjorn's latest comment on top of this, I think we are good not to fail
the probe here.
- Vidya Sagar
>
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: interconnect: Update Qualcomm SDM845 DT bindings
From: Stephen Boyd @ 2019-07-23 14:42 UTC (permalink / raw)
To: bjorn.andersson, georgi.djakov, robh+dt
Cc: David Dai, evgreen, ilina, seansw, elder, linux-kernel,
devicetree, linux-arm-msm, linux-pm
In-Reply-To: <1563568344-1274-2-git-send-email-daidavid1@codeaurora.org>
Quoting David Dai (2019-07-19 13:32:23)
> Redefine the Network-on-Chip devices to more accurately describe
> the interconnect topology on Qualcomm's SDM845 platform. Each
> interconnect device can communicate with different instances of the
> RPMh hardware which are described as RSCs(Resource State Coordinators).
>
> Signed-off-by: David Dai <daidavid1@codeaurora.org>
> ---
> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.txt b/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.txt
> new file mode 100644
> index 0000000..2cf7da2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,bcm-voter.txt
> @@ -0,0 +1,32 @@
> +Qualcomm BCM-Voter interconnect driver binding
> +-----------------------------------------------------------
> +
> +The Bus Clock Manager (BCM) is a dedicated hardware accelerator
> +that manages shared system resources by aggregating requests
> +from multiple Resource State Coordinators (RSC). Interconnect
> +providers are able to vote for aggregated thresholds values from
> +consumers by communicating through their respective RSCs.
> +
> +Required properties :
> +- compatible : shall contain only one of the following:
> + "qcom,sdm845-bcm-voter",
> +
> +Examples:
> +
> +apps_rsc: rsc@179c0000 {
But there isn't a reg property.
> + label = "apps_rsc";
Is label required?
> + compatible = "qcom,rpmh-rsc";
> +
> + apps_bcm_voter: bcm_voter {
> + compatible = "qcom,sdm845-bcm-voter";
> + };
> +}
> +
> +disp_rsc: rsc@179d0000 {
> + label = "disp_rsc";
> + compatible = "qcom,rpmh-rsc";
> +
> + disp_bcm_voter: bcm_voter {
> + compatible = "qcom,sdm845-bcm-voter";
> + };
> +}
> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sdm845.txt b/Documentation/devicetree/bindings/interconnect/qcom,sdm845.txt
> index 5c4f1d9..27f9ed9 100644
> --- a/Documentation/devicetree/bindings/interconnect/qcom,sdm845.txt
> +++ b/Documentation/devicetree/bindings/interconnect/qcom,sdm845.txt
> @@ -4,21 +4,43 @@ Qualcomm SDM845 Network-On-Chip interconnect driver binding
> SDM845 interconnect providers support system bandwidth requirements through
> RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is
> able to communicate with the BCM through the Resource State Coordinator (RSC)
> -associated with each execution environment. Provider nodes must reside within
> -an RPMh device node pertaining to their RSC and each provider maps to a single
> -RPMh resource.
> +associated with each execution environment. Provider nodes must point to at
> +least one RPMh device child node pertaining to their RSC and each provider
> +can map to multiple RPMh resources.
>
> Required properties :
> - compatible : shall contain only one of the following:
> - "qcom,sdm845-rsc-hlos"
> + "qcom,sdm845-aggre1_noc",
> + "qcom,sdm845-aggre2_noc",
> + "qcom,sdm845-config_noc",
> + "qcom,sdm845-dc_noc",
> + "qcom,sdm845-gladiator_noc",
> + "qcom,sdm845-mem_noc",
> + "qcom,sdm845-mmss_noc",
> + "qcom,sdm845-system_noc",
> - #interconnect-cells : should contain 1
> +- reg : shall contain base register location and length
> +- qcom,bcm-voter : shall contain phandles to bcm voters
>
> Examples:
>
> -apps_rsc: rsc {
> - rsc_hlos: interconnect {
> - compatible = "qcom,sdm845-rsc-hlos";
> - #interconnect-cells = <1>;
> - };
> +aggre1_noc: interconnect@16e0000 {
> + compatible = "qcom,sdm845-aggre1_noc";
> + reg = <0x16e0000 0xd080>;
> + interconnect-cells = <1>;
> + qcom,bcm-voter = <&apps_bcm_voter>;
> };
>
> +mmss_noc: interconnect@1740000 {
> + compatible = "qcom,sdm845-mmss_noc";
> + reg = <0x1740000 0x1c1000>;
> + interconnect-cells = <1>;
> + qcom,bcm-voter = <&apps_bcm_voter>, <&disp_bcm_voter>;
> +};
> +
> +mem_noc: interconnect@1380000 {
> + compatible = "qcom,sdm845-mem_noc";
> + reg = <0 0x1380000 0 0x27200>;
> + #interconnect-cells = <1>;
> + qcom,bcm-voter = <&apps_bcm_voter>, <&disp_bcm_voter>;
> +};
How does a consumer target a particular RSC? For example, how can
display decide to use the disp_bcm_voter node from mem_noc here? Maybe
you can add that consumer to the example?
^ permalink raw reply
* Re: [PATCH v4 2/3] dt-bindings: rng: add bindings for MediaTek ARMv8 SoCs
From: Rob Herring @ 2019-07-23 14:35 UTC (permalink / raw)
To: Neal Liu
Cc: Mark Rutland, devicetree@vger.kernel.org, Herbert Xu,
wsd_upstream, Sean Wang, linux-kernel@vger.kernel.org,
Crystal Guo (郭晶), linux-crypto@vger.kernel.org,
Matt Mackall, Matthias Brugger,
linux-mediatek@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <1563848465.31451.4.camel@mtkswgap22>
On Mon, Jul 22, 2019 at 8:21 PM Neal Liu <neal.liu@mediatek.com> wrote:
>
Please don't top post to lists.
> Dear Rob,
> You can check my driver for detail:
> http://patchwork.kernel.org/patch/11012475/ or patchset 3/3
I could, or you could just answer my question.
>
> This driver is registered as hardware random number generator, and
> combines with rng-core.
> We want to add one rng hw based on the dts. Is this proper or do you
> have other suggestion to meet this requirement?
It depends. There doesn't appear to be any resource configuration, so
why does it need to be in DT. DT is not the only way instantiate
drivers.
Rob
>
> Thanks
>
>
> On Tue, 2019-07-23 at 01:13 +0800, Rob Herring wrote:
> > On Mon, Jun 24, 2019 at 03:24:11PM +0800, Neal Liu wrote:
> > > Document the binding used by the MediaTek ARMv8 SoCs random
> > > number generator with TrustZone enabled.
> > >
> > > Signed-off-by: Neal Liu <neal.liu@mediatek.com>
> > > ---
> > > .../devicetree/bindings/rng/mtk-sec-rng.txt | 10 ++++++++++
> > > 1 file changed, 10 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/rng/mtk-sec-rng.txt
> > >
> > > diff --git a/Documentation/devicetree/bindings/rng/mtk-sec-rng.txt b/Documentation/devicetree/bindings/rng/mtk-sec-rng.txt
> > > new file mode 100644
> > > index 0000000..c04ce15
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/rng/mtk-sec-rng.txt
> > > @@ -0,0 +1,10 @@
> > > +MediaTek random number generator with TrustZone enabled
> > > +
> > > +Required properties:
> > > +- compatible : Should be "mediatek,mtk-sec-rng"
> >
> > What's the interface to access this?
> >
> > A node with a 'compatible' and nothing else is a sign of something that
> > a parent device should instantiate and doesn't need to be in DT. IOW,
> > what do complete bindings for firmware functions look like?
> >
> > > +
> > > +Example:
> > > +
> > > +hwrng: hwrng {
> > > + compatible = "mediatek,mtk-sec-rng";
> > > +}
> > > --
> > > 1.7.9.5
> > >
> >
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek
>
>
^ permalink raw reply
* Re: [RESEND PATCH 01/10] dt-bindings: crypto: k3: Add sa2ul bindings documentation
From: Rob Herring @ 2019-07-23 14:29 UTC (permalink / raw)
To: Keerthy
Cc: Peter Ujfalusi, Herbert Xu, David Miller,
linux-kernel@vger.kernel.org,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
devicetree, Tero Kristo,
open list:HARDWARE RANDOM NUMBER GENERATOR CORE, Nishanth Menon
In-Reply-To: <b8712fe4-4590-fdda-8a24-bf0f135ad567@ti.com>
On Mon, Jul 22, 2019 at 10:10 PM Keerthy <j-keerthy@ti.com> wrote:
>
>
>
> On 22/07/19 11:59 PM, Rob Herring wrote:
> > On Fri, Jun 28, 2019 at 09:57:36AM +0530, Keerthy wrote:
> >> The series adds Crypto hardware accelerator support for SA2UL.
> >> SA2UL stands for security accelerator ultra lite.
> >>
> >> The Security Accelerator (SA2_UL) subsystem provides hardware
> >> cryptographic acceleration for the following use cases:
> >> • Encryption and authentication for secure boot
> >> • Encryption and authentication of content in applications
> >> requiring DRM (digital rights management) and
> >> content/asset protection
> >> The device includes one instantiation of SA2_UL named SA2_UL0
> >>
> >> SA2UL needs on tx channel and a pair of rx dma channels.
> >>
> >> Signed-off-by: Keerthy <j-keerthy@ti.com>
> >> ---
> >> .../devicetree/bindings/crypto/sa2ul.txt | 47 +++++++++++++++++++
> >> 1 file changed, 47 insertions(+)
> >> create mode 100644 Documentation/devicetree/bindings/crypto/sa2ul.txt
> >>
> >> diff --git a/Documentation/devicetree/bindings/crypto/sa2ul.txt b/Documentation/devicetree/bindings/crypto/sa2ul.txt
> >> new file mode 100644
> >> index 000000000000..81cc039673b4
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/crypto/sa2ul.txt
> >> @@ -0,0 +1,47 @@
> >> +K3 SoC SA2UL crypto module
> >> +
> >> +Required properties:
> >> +
> >> +- compatible : Should be:
> >> + - "ti,sa2ul-crypto"
> >
> > Needs to be SoC specific.
>
> okay
>
> >
> >> +- reg : Offset and length of the register set for the module
> >> +
> >> +- dmas: DMA specifiers for tx and rx dma. sa2ul needs one tx channel
> >> + and 2 rx channels. First rx channel for < 256 bytes and
> >> + the other one for >=256 bytes. See the DMA client binding,
> >> + Documentation/devicetree/bindings/dma/dma.txt
> >> +- dma-names: DMA request names has to have one tx and 2 rx names
> >> + corresponding to dmas abive.
> >> +- ti,psil-config* - UDMA PSIL native Peripheral using packet mode.
> >> + SA2UL must have EPIB(Extended protocal information block)
> >> + and PSDATA(protocol specific data) properties.
> >
> > If ti,needs-epib is required, then why do you need to specify it in DT?
> > In any case, this all seems like channel config info that should be part
> > of the #dma-cells.
>
> ti,needs-epib is the udma client(Here sa2ul) conveying the udma layer.
> Not every udma client needs epib.
Right, but if sa2ul always needs it, then it can be implied and set by the driver.
^ permalink raw reply
* RE: [PATCH V13 12/12] PCI: tegra: Add Tegra194 PCIe support
From: Vidya Sagar @ 2019-07-23 14:28 UTC (permalink / raw)
To: Bjorn Helgaas, Lorenzo Pieralisi
Cc: robh+dt@kernel.org, mark.rutland@arm.com,
thierry.reding@gmail.com, Jonathan Hunter, kishon@ti.com,
catalin.marinas@arm.com, will.deacon@arm.com,
jingoohan1@gmail.com, gustavo.pimentel@synopsys.com,
digetx@gmail.com, Mikko Perttunen, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-arm-kernel
In-Reply-To: <20190716190013.GB4470@google.com>
> -----Original Message-----
> From: devicetree-owner@vger.kernel.org <devicetree-owner@vger.kernel.org>
> On Behalf Of Bjorn Helgaas
> Sent: Wednesday, July 17, 2019 12:30 AM
> To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Vidya Sagar <vidyas@nvidia.com>; robh+dt@kernel.org;
> mark.rutland@arm.com; thierry.reding@gmail.com; Jonathan Hunter
> <jonathanh@nvidia.com>; kishon@ti.com; catalin.marinas@arm.com;
> will.deacon@arm.com; jingoohan1@gmail.com;
> gustavo.pimentel@synopsys.com; digetx@gmail.com; Mikko Perttunen
> <mperttunen@nvidia.com>; linux-pci@vger.kernel.org;
> devicetree@vger.kernel.org; linux-tegra@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Krishna Thota
> <kthota@nvidia.com>; Manikanta Maddireddy <mmaddireddy@nvidia.com>;
> sagar.tv@gmail.com
> Subject: Re: [PATCH V13 12/12] PCI: tegra: Add Tegra194 PCIe support
>
> On Tue, Jul 16, 2019 at 12:22:25PM +0100, Lorenzo Pieralisi wrote:
> > On Sat, Jul 13, 2019 at 12:34:34PM +0530, Vidya Sagar wrote:
>
> > > > > > So if the link is not up we still go ahead and make probe
> > > > > > succeed. What for ?
> > > > > We may need root port to be available to support hot-plugging of
> > > > > endpoint devices, so, we don't fail the probe.
> > > >
> > > > We need it or we don't. If you do support hotplugging of endpoint
> > > > devices point me at the code, otherwise link up failure means
> > > > failure to probe.
> > > Currently hotplugging of endpoint is not supported, but it is one of
> > > the use cases that we may add support for in future.
> >
> > You should elaborate on this, I do not understand what you mean,
> > either the root port(s) supports hotplug or it does not.
> >
> > > But, why should we fail probe if link up doesn't happen? As such,
> > > nothing went wrong in terms of root port initialization right? I
> > > checked other DWC based implementations and following are not
> > > failing the probe pci-dra7xx.c, pcie-armada8k.c, pcie-artpec6.c,
> > > pcie-histb.c, pcie-kirin.c, pcie-spear13xx.c, pci-exynos.c,
> > > pci-imx6.c, pci-keystone.c, pci-layerscape.c
> > >
> > > Although following do fail the probe if link is not up.
> > > pcie-qcom.c, pcie-uniphier.c, pci-meson.c
> > >
> > > So, to me, it looks more like a choice we can make whether to fail
> > > the probe or not and in this case we are choosing not to fail.
> >
> > I disagree. I had an offline chat with Bjorn and whether link-up
> > should fail the probe or not depends on whether the root port(s) is
> > hotplug capable or not and this in turn relies on the root port "Slot
> > implemented" bit in the PCI Express capabilities register.
>
> There might be a little more we can talk about in this regard. I did bring up the
> "Slot implemented" bit, but after thinking about it more, I don't really think the
> host bridge driver should be looking at that.
> That's a PCIe concept, and it's really *downstream* from the host bridge itself.
> The host bridge is logically a device on the CPU bus, not the PCI bus.
>
> I'm starting to think that the host bridge driver probe should be disconnected
> from question of whether the root port links are up.
>
> Logically, the host bridge driver connects the CPU bus to a PCI root bus, so it
> converts CPU-side accesses to PCI config, memory, or I/O port transactions.
> Given that, the PCI core can enumerate devices on the root bus and downstream
> buses.
>
> Devices on the root bus typically include Root Ports, but might also include
> endpoints, Root Complex Integrated Endpoints, Root Complex Event Collectors,
> etc. I think in principle, we would want the host bridge probe to succeed so we
> can use these devices even if none of the Root Ports have a link.
>
> If a Root Port is present, I think users will expect to see it in the "lspci" output,
> even if its downstream link is not up. That will enable things like manually
> poking the Root Port via "setpci" for debug. And if it has a connector, the
> generic pciehp should be able to handle hot-add events without any special help
> from the host bridge driver.
>
> On ACPI systems there is no concept of the host bridge driver probe failing
> because of lack of link on a Root Port. If a Root Port doesn't have an
> operational link, we still keep the pci_root.c driver, and we'll enumerate the
> Root Port itself. So I tend to think DT systems should behave the same way, i.e.,
> the driver probe should succeed unless it fails to allocate resources or something
> similar. I think this is analogous to a NIC or USB adapter driver, where the probe
> succeeds even if there's no network cable or USB device attached.
>
> Bjorn
Thanks Bjorn for your valuable inputs. I hope we are good here to not power down host
even if there are no endpoints detected.
- Vidya Sagar
^ permalink raw reply
* Re: [PATCH V6 16/21] soc/tegra: pmc: Add pmc wake support for tegra210
From: Dmitry Osipenko @ 2019-07-23 14:27 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <a58de350-f6ce-9308-1ae0-885e732b575d@gmail.com>
23.07.2019 6:43, Dmitry Osipenko пишет:
> 23.07.2019 6:31, Sowjanya Komatineni пишет:
>>
>> On 7/22/19 8:25 PM, Dmitry Osipenko wrote:
>>> 23.07.2019 6:09, Sowjanya Komatineni пишет:
>>>> On 7/22/19 8:03 PM, Dmitry Osipenko wrote:
>>>>> 23.07.2019 4:52, Sowjanya Komatineni пишет:
>>>>>> On 7/22/19 6:41 PM, Dmitry Osipenko wrote:
>>>>>>> 23.07.2019 4:08, Dmitry Osipenko пишет:
>>>>>>>> 23.07.2019 3:58, Dmitry Osipenko пишет:
>>>>>>>>> 21.07.2019 22:40, Sowjanya Komatineni пишет:
>>>>>>>>>> This patch implements PMC wakeup sequence for Tegra210 and defines
>>>>>>>>>> common used RTC alarm wake event.
>>>>>>>>>>
>>>>>>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>>>>>>> ---
>>>>>>>>>> drivers/soc/tegra/pmc.c | 111
>>>>>>>>>> ++++++++++++++++++++++++++++++++++++++++++++++++
>>>>>>>>>> 1 file changed, 111 insertions(+)
>>>>>>>>>>
>>>>>>>>>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>>>>>>>>>> index 91c84d0e66ae..c556f38874e1 100644
>>>>>>>>>> --- a/drivers/soc/tegra/pmc.c
>>>>>>>>>> +++ b/drivers/soc/tegra/pmc.c
>>>>>>>>>> @@ -57,6 +57,12 @@
>>>>>>>>>> #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock
>>>>>>>>>> enable */
>>>>>>>>>> #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk
>>>>>>>>>> polarity */
>>>>>>>>>> #define PMC_CNTRL_MAIN_RST BIT(4)
>>>>>>>>>> +#define PMC_CNTRL_LATCH_WAKEUPS BIT(5)
>>>>>>>> Please follow the TRM's bits naming.
>>>>>>>>
>>>>>>>> PMC_CNTRL_LATCHWAKE_EN
>>>>>>>>
>>>>>>>>>> +#define PMC_WAKE_MASK 0x0c
>>>>>>>>>> +#define PMC_WAKE_LEVEL 0x10
>>>>>>>>>> +#define PMC_WAKE_STATUS 0x14
>>>>>>>>>> +#define PMC_SW_WAKE_STATUS 0x18
>>>>>>>>>> #define DPD_SAMPLE 0x020
>>>>>>>>>> #define DPD_SAMPLE_ENABLE BIT(0)
>>>>>>>>>> @@ -87,6 +93,11 @@
>>>>>>>>>> #define PMC_SCRATCH41 0x140
>>>>>>>>>> +#define PMC_WAKE2_MASK 0x160
>>>>>>>>>> +#define PMC_WAKE2_LEVEL 0x164
>>>>>>>>>> +#define PMC_WAKE2_STATUS 0x168
>>>>>>>>>> +#define PMC_SW_WAKE2_STATUS 0x16c
>>>>>>>>>> +
>>>>>>>>>> #define PMC_SENSOR_CTRL 0x1b0
>>>>>>>>>> #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
>>>>>>>>>> #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
>>>>>>>>>> @@ -1922,6 +1933,55 @@ static const struct irq_domain_ops
>>>>>>>>>> tegra_pmc_irq_domain_ops = {
>>>>>>>>>> .alloc = tegra_pmc_irq_alloc,
>>>>>>>>>> };
>>>>>>>>>> +static int tegra210_pmc_irq_set_wake(struct irq_data *data,
>>>>>>>>>> unsigned int on)
>>>>>>>>>> +{
>>>>>>>>>> + struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
>>>>>>>>>> + unsigned int offset, bit;
>>>>>>>>>> + u32 value;
>>>>>>>>>> +
>>>>>>>>>> + if (data->hwirq == ULONG_MAX)
>>>>>>>>>> + return 0;
>>>>>>>>>> +
>>>>>>>>>> + offset = data->hwirq / 32;
>>>>>>>>>> + bit = data->hwirq % 32;
>>>>>>>>>> +
>>>>>>>>>> + /*
>>>>>>>>>> + * Latch wakeups to SW_WAKE_STATUS register to capture events
>>>>>>>>>> + * that would not make it into wakeup event register during
>>>>>>>>>> LP0 exit.
>>>>>>>>>> + */
>>>>>>>>>> + value = tegra_pmc_readl(pmc, PMC_CNTRL);
>>>>>>>>>> + value |= PMC_CNTRL_LATCH_WAKEUPS;
>>>>>>>>>> + tegra_pmc_writel(pmc, value, PMC_CNTRL);
>>>>>>>>>> + udelay(120);
>>>>>>>>> Why it takes so much time to latch the values? Shouldn't some
>>>>>>>>> status-bit
>>>>>>>>> be polled for the completion of latching?
>>>>>>>>>
>>>>>>>>> Is this register-write really getting buffered in the PMC?
>>>>>>>>>
>>>>>>>>>> + value &= ~PMC_CNTRL_LATCH_WAKEUPS;
>>>>>>>>>> + tegra_pmc_writel(pmc, value, PMC_CNTRL);
>>>>>>>>>> + udelay(120);
>>>>>>>>> 120 usecs to remove latching, really?
>>>>>>>>>
>>>>>>>>>> + tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
>>>>>>>>>> + tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
>>>>>>>>>> +
>>>>>>>>>> + tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
>>>>>>>>>> + tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
>>>>>>>>>> +
>>>>>>>>>> + /* enable PMC wake */
>>>>>>>>>> + if (data->hwirq >= 32)
>>>>>>>>>> + offset = PMC_WAKE2_MASK;
>>>>>>>>>> + else
>>>>>>>>>> + offset = PMC_WAKE_MASK;
>>>>>>>>>> +
>>>>>>>>>> + value = tegra_pmc_readl(pmc, offset);
>>>>>>>>>> +
>>>>>>>>>> + if (on)
>>>>>>>>>> + value |= 1 << bit;
>>>>>>>>>> + else
>>>>>>>>>> + value &= ~(1 << bit);
>>>>>>>>>> +
>>>>>>>>>> + tegra_pmc_writel(pmc, value, offset);
>>>>>>>>> Why the latching is done *before* writing into the WAKE registers?
>>>>>>>>> What
>>>>>>>>> it is latching then?
>>>>>>>> I'm looking at the TRM doc and it says that latching should be done
>>>>>>>> *after* writing to the WAKE_MASK / LEVEL registers.
>>>>>>>>
>>>>>>>> Secondly it says that it's enough to do:
>>>>>>>>
>>>>>>>> value = tegra_pmc_readl(pmc, PMC_CNTRL);
>>>>>>>> value |= PMC_CNTRL_LATCH_WAKEUPS;
>>>>>>>> tegra_pmc_writel(pmc, value, PMC_CNTRL);
>>>>>>>>
>>>>>>>> in order to latch. There is no need for the delay and to remove the
>>>>>>>> "LATCHWAKE_EN" bit, it should be a oneshot action.
>>>>>>> Although, no. TRM says "stops latching on transition from 1
>>>>>>> to 0 (sequence - set to 1,set to 0)", so it's not a oneshot action.
>>>>>>>
>>>>>>> Have you tested this code at all? I'm wondering how it happens to
>>>>>>> work
>>>>>>> without a proper latching.
>>>>>> Yes, ofcourse its tested and this sequence to do transition is
>>>>>> recommendation from Tegra designer.
>>>>>> Will check if TRM doesn't have update properly or will re-confirm
>>>>>> internally on delay time...
>>>>>>
>>>>>> On any of the wake event PMC wakeup happens and WAKE_STATUS register
>>>>>> will have bits set for all events that triggered wake.
>>>>>> After wakeup PMC doesn't update SW_WAKE_STATUS register as per PMC
>>>>>> design.
>>>>>> SW latch register added in design helps to provide a way to capture
>>>>>> those events that happen right during wakeup time and didnt make it to
>>>>>> SW_WAKE_STATUS register.
>>>>>> So before next suspend entry, latching all prior wake events into SW
>>>>>> WAKE_STATUS and then clearing them.
>>>>> I'm now wondering whether the latching cold be turned ON permanently
>>>>> during of the PMC's probe, for simplicity.
>>>> latching should be done on suspend-resume cycle as wake events gets
>>>> generates on every suspend-resume cycle.
>>> You're saying that PMC "doesn't update SW_WAKE_STATUS" after wake-up,
>>> then I don't quite understand what's the point of disabling the latching
>>> at all.
>> When latch wake enable is set, events are latched and during 1 to 0
>> transition latching is disabled.
>>
>> This is to avoid sw_wake_status and wake_status showing diff events.
>
> Okay.
>
>> Currently driver is not relying on SW_WAKE_STATUS but its good to latch
>> and clear so even at some point for some reason when SW_WAKE_STATUS is
>> used, this wlil not cause mismatch with wake_status.
>
> Then the latching need to be enabled on suspend and disabled early on
> resume to get a proper WAKE status.
Actually, it will be better to simply not implement the latching until
it will become really needed. In general you shouldn't add into the
patchset anything that is unused.
^ permalink raw reply
* Re: [PATCH v3 1/6] dt-bindings: opp: Introduce opp-peak-KBps and opp-avg-KBps bindings
From: Rob Herring @ 2019-07-23 14:26 UTC (permalink / raw)
To: Saravana Kannan
Cc: Sibi Sankar, Georgi Djakov, Mark Rutland, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Rafael J. Wysocki, Vincent Guittot,
Sweeney, Sean, daidavid1, Rajendra Nayak, Bjorn Andersson,
Evan Green, Android Kernel Team, Linux PM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, LKML
In-Reply-To: <CAGETcx9GzQj0ZHNF+uR2cGHUkQ5sOPYEwyXKK1dJ2sJbHVSVyw@mail.gmail.com>
On Mon, Jul 22, 2019 at 5:41 PM Saravana Kannan <saravanak@google.com> wrote:
>
> On Mon, Jul 22, 2019 at 4:35 PM Rob Herring <robh@kernel.org> wrote:
> >
> > On Tue, Jul 16, 2019 at 11:58:08AM -0700, Saravana Kannan wrote:
> > > On Tue, Jul 16, 2019 at 10:25 AM Sibi Sankar <sibis@codeaurora.org> wrote:
> > > >
> > > > Hey Saravana,
> > > >
> > > > https://patchwork.kernel.org/patch/10850815/
> > > > There was already a discussion ^^ on how bandwidth bindings were to be
> > > > named.
> > >
> > > Yes, I'm aware of that series. That series is trying to define a BW
> > > mapping for an existing frequency OPP table. This patch is NOT about
> > > adding a mapping to an existing table. This patch is about adding the
> > > notion of BW OPP tables where BW is the "key" instead of "frequency".
> > >
> > > So let's not mixed up these two series.
> >
> > Maybe different reasons, but in the end we'd end up with 2 bandwidth
> > properties. We need to sort out how they'd overlap/coexist.
>
> Oh, I totally agree! My point is that the other mapping isn't the
> right approach because it doesn't handle a whole swath of use cases.
> The one I'm proposing can act as a super set of the other (as in, can
> handle that use case too).
>
> > The same comment in that series about defining a standard unit suffix
> > also applies to this one.
>
> I thought I read that whole series and I don't remember reading about
> the unit suffix. But I'll take a closer look. I've chosen to keep the
> DT units at least as "high of a resolution" as what the APIs accept
> today. The APIs take KB/s. So I make sure DT can capture KB/s
> differences. If we all agree that KB/s is "too accurate" then I think
> we should change everything to MB/s.
Either one is fine with me, but trying to align to what the OS picked
doesn't work. What does BSD use for example? More important is
aligning across DT properties so we don't have folks picking whatever
random unit they like. We generally try to go with the smallest units
that will have enough (32-bit) range for everyone, so that's probably
KB/s here.
Rob
^ permalink raw reply
* [PATCH v5 5/5] arm64: dts: qcs404: Add interconnect provider DT nodes
From: Georgi Djakov @ 2019-07-23 14:23 UTC (permalink / raw)
To: robh+dt, bjorn.andersson, agross, georgi.djakov
Cc: vkoul, evgreen, daidavid1, linux-pm, devicetree, linux-arm-msm
In-Reply-To: <20190723142339.27772-1-georgi.djakov@linaro.org>
Add the DT nodes for the network-on-chip interconnect buses found
on qcs404-based platforms.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
v5:
- Rebased to v5.3-rc1
v4:
- Insert the NoC DT nodes after rng@ to keep the nodes sorted by address.
- Pick Bjorn's r-b.
v3:
- Update according to the new binding: add reg property and moved under the
"soc" node.
arch/arm64/boot/dts/qcom/qcs404.dtsi | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 3d0789775009..8b9352347622 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, Linaro Limited
+#include <dt-bindings/interconnect/qcom,qcs404.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-qcs404.h>
#include <dt-bindings/clock/qcom,turingcc-qcs404.h>
@@ -273,6 +274,15 @@
clock-names = "core";
};
+ bimc: interconnect@400000 {
+ reg = <0x00400000 0x80000>;
+ compatible = "qcom,qcs404-bimc";
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
+ <&rpmcc RPM_SMD_BIMC_A_CLK>;
+ };
+
tsens: thermal-sensor@4a9000 {
compatible = "qcom,qcs404-tsens", "qcom,tsens-v1";
reg = <0x004a9000 0x1000>, /* TM */
@@ -283,6 +293,24 @@
#thermal-sensor-cells = <1>;
};
+ pcnoc: interconnect@500000 {
+ reg = <0x00500000 0x15080>;
+ compatible = "qcom,qcs404-pcnoc";
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
+ <&rpmcc RPM_SMD_PNOC_A_CLK>;
+ };
+
+ snoc: interconnect@580000 {
+ reg = <0x00580000 0x23080>;
+ compatible = "qcom,qcs404-snoc";
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
+ <&rpmcc RPM_SMD_SNOC_A_CLK>;
+ };
+
remoteproc_cdsp: remoteproc@b00000 {
compatible = "qcom,qcs404-cdsp-pas";
reg = <0x00b00000 0x4040>;
^ permalink raw reply related
* [PATCH v5 4/5] interconnect: qcom: Add QCS404 interconnect provider driver
From: Georgi Djakov @ 2019-07-23 14:23 UTC (permalink / raw)
To: robh+dt, bjorn.andersson, agross, georgi.djakov
Cc: vkoul, evgreen, daidavid1, linux-pm, devicetree, linux-arm-msm
In-Reply-To: <20190723142339.27772-1-georgi.djakov@linaro.org>
From: Bjorn Andersson <bjorn.andersson@linaro.org>
Add driver for the interconnect buses found in Qualcomm QCS404-based
platforms. The topology consists of three NoCs that are controlled by
a remote processor. This remote processor collects the aggregated
bandwidth for each master-slave pairs.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
v5:
- Remove the _clk suffix from the clock names.
v4:
- Select INTERCONNECT_QCOM_SMD_RPM from this driver.
- Move the DT header to the dt-bindings patch.
- Move this patch later in the series.
v3:
- Convert the #defines into enum. (Bjorn)
- Move the rpm-smd part into a separate interconnect proxy driver.
v2:
- Use the clk_bulk API. (Bjorn)
- Move the port IDs into the provider file. (Bjorn)
- Use ARRAY_SIZE in the macro to automagically count the num_links. (Bjorn)
- Improve code readability. (Bjorn)
drivers/interconnect/qcom/Kconfig | 9 +
drivers/interconnect/qcom/Makefile | 2 +
drivers/interconnect/qcom/qcs404.c | 539 +++++++++++++++++++++++++++++
3 files changed, 550 insertions(+)
create mode 100644 drivers/interconnect/qcom/qcs404.c
diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig
index 03fd67173494..339e8f10d4f3 100644
--- a/drivers/interconnect/qcom/Kconfig
+++ b/drivers/interconnect/qcom/Kconfig
@@ -5,6 +5,15 @@ config INTERCONNECT_QCOM
help
Support for Qualcomm's Network-on-Chip interconnect hardware.
+config INTERCONNECT_QCOM_QCS404
+ tristate "Qualcomm QCS404 interconnect driver"
+ depends on INTERCONNECT_QCOM
+ depends on QCOM_SMD_RPM || COMPILE_TEST
+ select INTERCONNECT_QCOM_SMD_RPM
+ help
+ This is a driver for the Qualcomm Network-on-Chip on qcs404-based
+ platforms.
+
config INTERCONNECT_QCOM_SDM845
tristate "Qualcomm SDM845 interconnect driver"
depends on INTERCONNECT_QCOM
diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile
index a600cf6cc272..67dafb783dec 100644
--- a/drivers/interconnect/qcom/Makefile
+++ b/drivers/interconnect/qcom/Makefile
@@ -1,7 +1,9 @@
# SPDX-License-Identifier: GPL-2.0
+qnoc-qcs404-objs := qcs404.o
qnoc-sdm845-objs := sdm845.o
icc-smd-rpm-objs := smd-rpm.o
+obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o
diff --git a/drivers/interconnect/qcom/qcs404.c b/drivers/interconnect/qcom/qcs404.c
new file mode 100644
index 000000000000..089a6f88a621
--- /dev/null
+++ b/drivers/interconnect/qcom/qcs404.c
@@ -0,0 +1,539 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Linaro Ltd
+ */
+
+#include <dt-bindings/interconnect/qcom,qcs404.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/interconnect-provider.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "smd-rpm.h"
+
+#define RPM_BUS_MASTER_REQ 0x73616d62
+#define RPM_BUS_SLAVE_REQ 0x766c7362
+
+enum {
+ QCS404_MASTER_AMPSS_M0 = 1,
+ QCS404_MASTER_GRAPHICS_3D,
+ QCS404_MASTER_MDP_PORT0,
+ QCS404_SNOC_BIMC_1_MAS,
+ QCS404_MASTER_TCU_0,
+ QCS404_MASTER_SPDM,
+ QCS404_MASTER_BLSP_1,
+ QCS404_MASTER_BLSP_2,
+ QCS404_MASTER_XM_USB_HS1,
+ QCS404_MASTER_CRYPTO_CORE0,
+ QCS404_MASTER_SDCC_1,
+ QCS404_MASTER_SDCC_2,
+ QCS404_SNOC_PNOC_MAS,
+ QCS404_MASTER_QPIC,
+ QCS404_MASTER_QDSS_BAM,
+ QCS404_BIMC_SNOC_MAS,
+ QCS404_PNOC_SNOC_MAS,
+ QCS404_MASTER_QDSS_ETR,
+ QCS404_MASTER_EMAC,
+ QCS404_MASTER_PCIE,
+ QCS404_MASTER_USB3,
+ QCS404_PNOC_INT_0,
+ QCS404_PNOC_INT_2,
+ QCS404_PNOC_INT_3,
+ QCS404_PNOC_SLV_0,
+ QCS404_PNOC_SLV_1,
+ QCS404_PNOC_SLV_2,
+ QCS404_PNOC_SLV_3,
+ QCS404_PNOC_SLV_4,
+ QCS404_PNOC_SLV_6,
+ QCS404_PNOC_SLV_7,
+ QCS404_PNOC_SLV_8,
+ QCS404_PNOC_SLV_9,
+ QCS404_PNOC_SLV_10,
+ QCS404_PNOC_SLV_11,
+ QCS404_SNOC_QDSS_INT,
+ QCS404_SNOC_INT_0,
+ QCS404_SNOC_INT_1,
+ QCS404_SNOC_INT_2,
+ QCS404_SLAVE_EBI_CH0,
+ QCS404_BIMC_SNOC_SLV,
+ QCS404_SLAVE_SPDM_WRAPPER,
+ QCS404_SLAVE_PDM,
+ QCS404_SLAVE_PRNG,
+ QCS404_SLAVE_TCSR,
+ QCS404_SLAVE_SNOC_CFG,
+ QCS404_SLAVE_MESSAGE_RAM,
+ QCS404_SLAVE_DISPLAY_CFG,
+ QCS404_SLAVE_GRAPHICS_3D_CFG,
+ QCS404_SLAVE_BLSP_1,
+ QCS404_SLAVE_TLMM_NORTH,
+ QCS404_SLAVE_PCIE_1,
+ QCS404_SLAVE_EMAC_CFG,
+ QCS404_SLAVE_BLSP_2,
+ QCS404_SLAVE_TLMM_EAST,
+ QCS404_SLAVE_TCU,
+ QCS404_SLAVE_PMIC_ARB,
+ QCS404_SLAVE_SDCC_1,
+ QCS404_SLAVE_SDCC_2,
+ QCS404_SLAVE_TLMM_SOUTH,
+ QCS404_SLAVE_USB_HS,
+ QCS404_SLAVE_USB3,
+ QCS404_SLAVE_CRYPTO_0_CFG,
+ QCS404_PNOC_SNOC_SLV,
+ QCS404_SLAVE_APPSS,
+ QCS404_SLAVE_WCSS,
+ QCS404_SNOC_BIMC_1_SLV,
+ QCS404_SLAVE_OCIMEM,
+ QCS404_SNOC_PNOC_SLV,
+ QCS404_SLAVE_QDSS_STM,
+ QCS404_SLAVE_CATS_128,
+ QCS404_SLAVE_OCMEM_64,
+ QCS404_SLAVE_LPASS,
+};
+
+#define to_qcom_provider(_provider) \
+ container_of(_provider, struct qcom_icc_provider, provider)
+
+static const struct clk_bulk_data bus_clocks[] = {
+ { .id = "bus" },
+ { .id = "bus_a" },
+};
+
+/**
+ * struct qcom_icc_provider - Qualcomm specific interconnect provider
+ * @provider: generic interconnect provider
+ * @bus_clks: the clk_bulk_data table of bus clocks
+ * @num_clks: the total number of clk_bulk_data entries
+ */
+struct qcom_icc_provider {
+ struct icc_provider provider;
+ struct clk_bulk_data *bus_clks;
+ int num_clks;
+};
+
+#define QCS404_MAX_LINKS 12
+
+/**
+ * struct qcom_icc_node - Qualcomm specific interconnect nodes
+ * @name: the node name used in debugfs
+ * @id: a unique node identifier
+ * @links: an array of nodes where we can go next while traversing
+ * @num_links: the total number of @links
+ * @buswidth: width of the interconnect between a node and the bus (bytes)
+ * @mas_rpm_id: RPM id for devices that are bus masters
+ * @slv_rpm_id: RPM id for devices that are bus slaves
+ * @rate: current bus clock rate in Hz
+ */
+struct qcom_icc_node {
+ unsigned char *name;
+ u16 id;
+ u16 links[QCS404_MAX_LINKS];
+ u16 num_links;
+ u16 buswidth;
+ int mas_rpm_id;
+ int slv_rpm_id;
+ u64 rate;
+};
+
+struct qcom_icc_desc {
+ struct qcom_icc_node **nodes;
+ size_t num_nodes;
+};
+
+#define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \
+ ...) \
+ static struct qcom_icc_node _name = { \
+ .name = #_name, \
+ .id = _id, \
+ .buswidth = _buswidth, \
+ .mas_rpm_id = _mas_rpm_id, \
+ .slv_rpm_id = _slv_rpm_id, \
+ .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \
+ .links = { __VA_ARGS__ }, \
+ }
+
+DEFINE_QNODE(mas_apps_proc, QCS404_MASTER_AMPSS_M0, 8, 0, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV);
+DEFINE_QNODE(mas_oxili, QCS404_MASTER_GRAPHICS_3D, 8, 6, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV);
+DEFINE_QNODE(mas_mdp, QCS404_MASTER_MDP_PORT0, 8, 8, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV);
+DEFINE_QNODE(mas_snoc_bimc_1, QCS404_SNOC_BIMC_1_MAS, 8, 76, -1, QCS404_SLAVE_EBI_CH0);
+DEFINE_QNODE(mas_tcu_0, QCS404_MASTER_TCU_0, 8, -1, -1, QCS404_SLAVE_EBI_CH0, QCS404_BIMC_SNOC_SLV);
+DEFINE_QNODE(mas_spdm, QCS404_MASTER_SPDM, 4, -1, -1, QCS404_PNOC_INT_3);
+DEFINE_QNODE(mas_blsp_1, QCS404_MASTER_BLSP_1, 4, 41, -1, QCS404_PNOC_INT_3);
+DEFINE_QNODE(mas_blsp_2, QCS404_MASTER_BLSP_2, 4, 39, -1, QCS404_PNOC_INT_3);
+DEFINE_QNODE(mas_xi_usb_hs1, QCS404_MASTER_XM_USB_HS1, 8, 138, -1, QCS404_PNOC_INT_0);
+DEFINE_QNODE(mas_crypto, QCS404_MASTER_CRYPTO_CORE0, 8, 23, -1, QCS404_PNOC_SNOC_SLV, QCS404_PNOC_INT_2);
+DEFINE_QNODE(mas_sdcc_1, QCS404_MASTER_SDCC_1, 8, 33, -1, QCS404_PNOC_INT_0);
+DEFINE_QNODE(mas_sdcc_2, QCS404_MASTER_SDCC_2, 8, 35, -1, QCS404_PNOC_INT_0);
+DEFINE_QNODE(mas_snoc_pcnoc, QCS404_SNOC_PNOC_MAS, 8, 77, -1, QCS404_PNOC_INT_2);
+DEFINE_QNODE(mas_qpic, QCS404_MASTER_QPIC, 4, -1, -1, QCS404_PNOC_INT_0);
+DEFINE_QNODE(mas_qdss_bam, QCS404_MASTER_QDSS_BAM, 4, -1, -1, QCS404_SNOC_QDSS_INT);
+DEFINE_QNODE(mas_bimc_snoc, QCS404_BIMC_SNOC_MAS, 8, 21, -1, QCS404_SLAVE_OCMEM_64, QCS404_SLAVE_CATS_128, QCS404_SNOC_INT_0, QCS404_SNOC_INT_1);
+DEFINE_QNODE(mas_pcnoc_snoc, QCS404_PNOC_SNOC_MAS, 8, 29, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_2, QCS404_SNOC_INT_0);
+DEFINE_QNODE(mas_qdss_etr, QCS404_MASTER_QDSS_ETR, 8, -1, -1, QCS404_SNOC_QDSS_INT);
+DEFINE_QNODE(mas_emac, QCS404_MASTER_EMAC, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1);
+DEFINE_QNODE(mas_pcie, QCS404_MASTER_PCIE, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1);
+DEFINE_QNODE(mas_usb3, QCS404_MASTER_USB3, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1);
+DEFINE_QNODE(pcnoc_int_0, QCS404_PNOC_INT_0, 8, 85, 114, QCS404_PNOC_SNOC_SLV, QCS404_PNOC_INT_2);
+DEFINE_QNODE(pcnoc_int_2, QCS404_PNOC_INT_2, 8, 124, 184, QCS404_PNOC_SLV_10, QCS404_SLAVE_TCU, QCS404_PNOC_SLV_11, QCS404_PNOC_SLV_2, QCS404_PNOC_SLV_3, QCS404_PNOC_SLV_0, QCS404_PNOC_SLV_1, QCS404_PNOC_SLV_6, QCS404_PNOC_SLV_7, QCS404_PNOC_SLV_4, QCS404_PNOC_SLV_8, QCS404_PNOC_SLV_9);
+DEFINE_QNODE(pcnoc_int_3, QCS404_PNOC_INT_3, 8, 125, 185, QCS404_PNOC_SNOC_SLV);
+DEFINE_QNODE(pcnoc_s_0, QCS404_PNOC_SLV_0, 4, 89, 118, QCS404_SLAVE_PRNG, QCS404_SLAVE_SPDM_WRAPPER, QCS404_SLAVE_PDM);
+DEFINE_QNODE(pcnoc_s_1, QCS404_PNOC_SLV_1, 4, 90, 119, QCS404_SLAVE_TCSR);
+DEFINE_QNODE(pcnoc_s_2, QCS404_PNOC_SLV_2, 4, -1, -1, QCS404_SLAVE_GRAPHICS_3D_CFG);
+DEFINE_QNODE(pcnoc_s_3, QCS404_PNOC_SLV_3, 4, 92, 121, QCS404_SLAVE_MESSAGE_RAM);
+DEFINE_QNODE(pcnoc_s_4, QCS404_PNOC_SLV_4, 4, 93, 122, QCS404_SLAVE_SNOC_CFG);
+DEFINE_QNODE(pcnoc_s_6, QCS404_PNOC_SLV_6, 4, 94, 123, QCS404_SLAVE_BLSP_1, QCS404_SLAVE_TLMM_NORTH, QCS404_SLAVE_EMAC_CFG);
+DEFINE_QNODE(pcnoc_s_7, QCS404_PNOC_SLV_7, 4, 95, 124, QCS404_SLAVE_TLMM_SOUTH, QCS404_SLAVE_DISPLAY_CFG, QCS404_SLAVE_SDCC_1, QCS404_SLAVE_PCIE_1, QCS404_SLAVE_SDCC_2);
+DEFINE_QNODE(pcnoc_s_8, QCS404_PNOC_SLV_8, 4, 96, 125, QCS404_SLAVE_CRYPTO_0_CFG);
+DEFINE_QNODE(pcnoc_s_9, QCS404_PNOC_SLV_9, 4, 97, 126, QCS404_SLAVE_BLSP_2, QCS404_SLAVE_TLMM_EAST, QCS404_SLAVE_PMIC_ARB);
+DEFINE_QNODE(pcnoc_s_10, QCS404_PNOC_SLV_10, 4, 157, -1, QCS404_SLAVE_USB_HS);
+DEFINE_QNODE(pcnoc_s_11, QCS404_PNOC_SLV_11, 4, 158, 246, QCS404_SLAVE_USB3);
+DEFINE_QNODE(qdss_int, QCS404_SNOC_QDSS_INT, 8, -1, -1, QCS404_SNOC_BIMC_1_SLV, QCS404_SNOC_INT_1);
+DEFINE_QNODE(snoc_int_0, QCS404_SNOC_INT_0, 8, 99, 130, QCS404_SLAVE_LPASS, QCS404_SLAVE_APPSS, QCS404_SLAVE_WCSS);
+DEFINE_QNODE(snoc_int_1, QCS404_SNOC_INT_1, 8, 100, 131, QCS404_SNOC_PNOC_SLV, QCS404_SNOC_INT_2);
+DEFINE_QNODE(snoc_int_2, QCS404_SNOC_INT_2, 8, 134, 197, QCS404_SLAVE_QDSS_STM, QCS404_SLAVE_OCIMEM);
+DEFINE_QNODE(slv_ebi, QCS404_SLAVE_EBI_CH0, 8, -1, 0, 0);
+DEFINE_QNODE(slv_bimc_snoc, QCS404_BIMC_SNOC_SLV, 8, -1, 2, QCS404_BIMC_SNOC_MAS);
+DEFINE_QNODE(slv_spdm, QCS404_SLAVE_SPDM_WRAPPER, 4, -1, -1, 0);
+DEFINE_QNODE(slv_pdm, QCS404_SLAVE_PDM, 4, -1, 41, 0);
+DEFINE_QNODE(slv_prng, QCS404_SLAVE_PRNG, 4, -1, 44, 0);
+DEFINE_QNODE(slv_tcsr, QCS404_SLAVE_TCSR, 4, -1, 50, 0);
+DEFINE_QNODE(slv_snoc_cfg, QCS404_SLAVE_SNOC_CFG, 4, -1, 70, 0);
+DEFINE_QNODE(slv_message_ram, QCS404_SLAVE_MESSAGE_RAM, 4, -1, 55, 0);
+DEFINE_QNODE(slv_disp_ss_cfg, QCS404_SLAVE_DISPLAY_CFG, 4, -1, -1, 0);
+DEFINE_QNODE(slv_gpu_cfg, QCS404_SLAVE_GRAPHICS_3D_CFG, 4, -1, -1, 0);
+DEFINE_QNODE(slv_blsp_1, QCS404_SLAVE_BLSP_1, 4, -1, 39, 0);
+DEFINE_QNODE(slv_tlmm_north, QCS404_SLAVE_TLMM_NORTH, 4, -1, 214, 0);
+DEFINE_QNODE(slv_pcie, QCS404_SLAVE_PCIE_1, 4, -1, -1, 0);
+DEFINE_QNODE(slv_ethernet, QCS404_SLAVE_EMAC_CFG, 4, -1, -1, 0);
+DEFINE_QNODE(slv_blsp_2, QCS404_SLAVE_BLSP_2, 4, -1, 37, 0);
+DEFINE_QNODE(slv_tlmm_east, QCS404_SLAVE_TLMM_EAST, 4, -1, 213, 0);
+DEFINE_QNODE(slv_tcu, QCS404_SLAVE_TCU, 8, -1, -1, 0);
+DEFINE_QNODE(slv_pmic_arb, QCS404_SLAVE_PMIC_ARB, 4, -1, 59, 0);
+DEFINE_QNODE(slv_sdcc_1, QCS404_SLAVE_SDCC_1, 4, -1, 31, 0);
+DEFINE_QNODE(slv_sdcc_2, QCS404_SLAVE_SDCC_2, 4, -1, 33, 0);
+DEFINE_QNODE(slv_tlmm_south, QCS404_SLAVE_TLMM_SOUTH, 4, -1, -1, 0);
+DEFINE_QNODE(slv_usb_hs, QCS404_SLAVE_USB_HS, 4, -1, 40, 0);
+DEFINE_QNODE(slv_usb3, QCS404_SLAVE_USB3, 4, -1, 22, 0);
+DEFINE_QNODE(slv_crypto_0_cfg, QCS404_SLAVE_CRYPTO_0_CFG, 4, -1, 52, 0);
+DEFINE_QNODE(slv_pcnoc_snoc, QCS404_PNOC_SNOC_SLV, 8, -1, 45, QCS404_PNOC_SNOC_MAS);
+DEFINE_QNODE(slv_kpss_ahb, QCS404_SLAVE_APPSS, 4, -1, -1, 0);
+DEFINE_QNODE(slv_wcss, QCS404_SLAVE_WCSS, 4, -1, 23, 0);
+DEFINE_QNODE(slv_snoc_bimc_1, QCS404_SNOC_BIMC_1_SLV, 8, -1, 104, QCS404_SNOC_BIMC_1_MAS);
+DEFINE_QNODE(slv_imem, QCS404_SLAVE_OCIMEM, 8, -1, 26, 0);
+DEFINE_QNODE(slv_snoc_pcnoc, QCS404_SNOC_PNOC_SLV, 8, -1, 28, QCS404_SNOC_PNOC_MAS);
+DEFINE_QNODE(slv_qdss_stm, QCS404_SLAVE_QDSS_STM, 4, -1, 30, 0);
+DEFINE_QNODE(slv_cats_0, QCS404_SLAVE_CATS_128, 16, -1, -1, 0);
+DEFINE_QNODE(slv_cats_1, QCS404_SLAVE_OCMEM_64, 8, -1, -1, 0);
+DEFINE_QNODE(slv_lpass, QCS404_SLAVE_LPASS, 4, -1, -1, 0);
+
+static struct qcom_icc_node *qcs404_bimc_nodes[] = {
+ [MASTER_AMPSS_M0] = &mas_apps_proc,
+ [MASTER_OXILI] = &mas_oxili,
+ [MASTER_MDP_PORT0] = &mas_mdp,
+ [MASTER_SNOC_BIMC_1] = &mas_snoc_bimc_1,
+ [MASTER_TCU_0] = &mas_tcu_0,
+ [SLAVE_EBI_CH0] = &slv_ebi,
+ [SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
+};
+
+static struct qcom_icc_desc qcs404_bimc = {
+ .nodes = qcs404_bimc_nodes,
+ .num_nodes = ARRAY_SIZE(qcs404_bimc_nodes),
+};
+
+static struct qcom_icc_node *qcs404_pcnoc_nodes[] = {
+ [MASTER_SPDM] = &mas_spdm,
+ [MASTER_BLSP_1] = &mas_blsp_1,
+ [MASTER_BLSP_2] = &mas_blsp_2,
+ [MASTER_XI_USB_HS1] = &mas_xi_usb_hs1,
+ [MASTER_CRYPT0] = &mas_crypto,
+ [MASTER_SDCC_1] = &mas_sdcc_1,
+ [MASTER_SDCC_2] = &mas_sdcc_2,
+ [MASTER_SNOC_PCNOC] = &mas_snoc_pcnoc,
+ [MASTER_QPIC] = &mas_qpic,
+ [PCNOC_INT_0] = &pcnoc_int_0,
+ [PCNOC_INT_2] = &pcnoc_int_2,
+ [PCNOC_INT_3] = &pcnoc_int_3,
+ [PCNOC_S_0] = &pcnoc_s_0,
+ [PCNOC_S_1] = &pcnoc_s_1,
+ [PCNOC_S_2] = &pcnoc_s_2,
+ [PCNOC_S_3] = &pcnoc_s_3,
+ [PCNOC_S_4] = &pcnoc_s_4,
+ [PCNOC_S_6] = &pcnoc_s_6,
+ [PCNOC_S_7] = &pcnoc_s_7,
+ [PCNOC_S_8] = &pcnoc_s_8,
+ [PCNOC_S_9] = &pcnoc_s_9,
+ [PCNOC_S_10] = &pcnoc_s_10,
+ [PCNOC_S_11] = &pcnoc_s_11,
+ [SLAVE_SPDM] = &slv_spdm,
+ [SLAVE_PDM] = &slv_pdm,
+ [SLAVE_PRNG] = &slv_prng,
+ [SLAVE_TCSR] = &slv_tcsr,
+ [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
+ [SLAVE_MESSAGE_RAM] = &slv_message_ram,
+ [SLAVE_DISP_SS_CFG] = &slv_disp_ss_cfg,
+ [SLAVE_GPU_CFG] = &slv_gpu_cfg,
+ [SLAVE_BLSP_1] = &slv_blsp_1,
+ [SLAVE_BLSP_2] = &slv_blsp_2,
+ [SLAVE_TLMM_NORTH] = &slv_tlmm_north,
+ [SLAVE_PCIE] = &slv_pcie,
+ [SLAVE_ETHERNET] = &slv_ethernet,
+ [SLAVE_TLMM_EAST] = &slv_tlmm_east,
+ [SLAVE_TCU] = &slv_tcu,
+ [SLAVE_PMIC_ARB] = &slv_pmic_arb,
+ [SLAVE_SDCC_1] = &slv_sdcc_1,
+ [SLAVE_SDCC_2] = &slv_sdcc_2,
+ [SLAVE_TLMM_SOUTH] = &slv_tlmm_south,
+ [SLAVE_USB_HS] = &slv_usb_hs,
+ [SLAVE_USB3] = &slv_usb3,
+ [SLAVE_CRYPTO_0_CFG] = &slv_crypto_0_cfg,
+ [SLAVE_PCNOC_SNOC] = &slv_pcnoc_snoc,
+};
+
+static struct qcom_icc_desc qcs404_pcnoc = {
+ .nodes = qcs404_pcnoc_nodes,
+ .num_nodes = ARRAY_SIZE(qcs404_pcnoc_nodes),
+};
+
+static struct qcom_icc_node *qcs404_snoc_nodes[] = {
+ [MASTER_QDSS_BAM] = &mas_qdss_bam,
+ [MASTER_BIMC_SNOC] = &mas_bimc_snoc,
+ [MASTER_PCNOC_SNOC] = &mas_pcnoc_snoc,
+ [MASTER_QDSS_ETR] = &mas_qdss_etr,
+ [MASTER_EMAC] = &mas_emac,
+ [MASTER_PCIE] = &mas_pcie,
+ [MASTER_USB3] = &mas_usb3,
+ [QDSS_INT] = &qdss_int,
+ [SNOC_INT_0] = &snoc_int_0,
+ [SNOC_INT_1] = &snoc_int_1,
+ [SNOC_INT_2] = &snoc_int_2,
+ [SLAVE_KPSS_AHB] = &slv_kpss_ahb,
+ [SLAVE_WCSS] = &slv_wcss,
+ [SLAVE_SNOC_BIMC_1] = &slv_snoc_bimc_1,
+ [SLAVE_IMEM] = &slv_imem,
+ [SLAVE_SNOC_PCNOC] = &slv_snoc_pcnoc,
+ [SLAVE_QDSS_STM] = &slv_qdss_stm,
+ [SLAVE_CATS_0] = &slv_cats_0,
+ [SLAVE_CATS_1] = &slv_cats_1,
+ [SLAVE_LPASS] = &slv_lpass,
+};
+
+static struct qcom_icc_desc qcs404_snoc = {
+ .nodes = qcs404_snoc_nodes,
+ .num_nodes = ARRAY_SIZE(qcs404_snoc_nodes),
+};
+
+static int qcom_icc_aggregate(struct icc_node *node, u32 avg_bw, u32 peak_bw,
+ u32 *agg_avg, u32 *agg_peak)
+{
+ *agg_avg += avg_bw;
+ *agg_peak = max(*agg_peak, peak_bw);
+
+ return 0;
+}
+
+static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
+{
+ struct qcom_icc_provider *qp;
+ struct qcom_icc_node *qn;
+ struct icc_provider *provider;
+ struct icc_node *n;
+ u64 sum_bw;
+ u64 max_peak_bw;
+ u64 rate;
+ u32 agg_avg = 0;
+ u32 agg_peak = 0;
+ int ret, i;
+
+ qn = src->data;
+ provider = src->provider;
+ qp = to_qcom_provider(provider);
+
+ list_for_each_entry(n, &provider->nodes, node_list)
+ qcom_icc_aggregate(n, n->avg_bw, n->peak_bw,
+ &agg_avg, &agg_peak);
+
+ sum_bw = icc_units_to_bps(agg_avg);
+ max_peak_bw = icc_units_to_bps(agg_peak);
+
+ /* send bandwidth request message to the RPM processor */
+ if (qn->mas_rpm_id != -1) {
+ ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
+ RPM_BUS_MASTER_REQ,
+ qn->mas_rpm_id,
+ sum_bw);
+ if (ret) {
+ pr_err("qcom_icc_rpm_smd_send mas %d error %d\n",
+ qn->mas_rpm_id, ret);
+ return ret;
+ }
+ }
+
+ if (qn->slv_rpm_id != -1) {
+ ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
+ RPM_BUS_SLAVE_REQ,
+ qn->slv_rpm_id,
+ sum_bw);
+ if (ret) {
+ pr_err("qcom_icc_rpm_smd_send slv error %d\n",
+ ret);
+ return ret;
+ }
+ }
+
+ rate = max(sum_bw, max_peak_bw);
+
+ do_div(rate, qn->buswidth);
+
+ if (qn->rate == rate)
+ return 0;
+
+ for (i = 0; i < qp->num_clks; i++) {
+ ret = clk_set_rate(qp->bus_clks[i].clk, rate);
+ if (ret) {
+ pr_err("%s clk_set_rate error: %d\n",
+ qp->bus_clks[i].id, ret);
+ return ret;
+ }
+ }
+
+ qn->rate = rate;
+
+ return 0;
+}
+
+static int qnoc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct qcom_icc_desc *desc;
+ struct icc_onecell_data *data;
+ struct icc_provider *provider;
+ struct qcom_icc_node **qnodes;
+ struct qcom_icc_provider *qp;
+ struct icc_node *node;
+ size_t num_nodes, i;
+ int ret;
+
+ /* wait for the RPM proxy */
+ if (!qcom_icc_rpm_smd_available())
+ return -EPROBE_DEFER;
+
+ desc = of_device_get_match_data(dev);
+ if (!desc)
+ return -EINVAL;
+
+ qnodes = desc->nodes;
+ num_nodes = desc->num_nodes;
+
+ qp = devm_kzalloc(dev, sizeof(*qp), GFP_KERNEL);
+ if (!qp)
+ return -ENOMEM;
+
+ data = devm_kcalloc(dev, num_nodes, sizeof(*node), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ qp->bus_clks = devm_kmemdup(dev, bus_clocks, sizeof(bus_clocks),
+ GFP_KERNEL);
+ if (!qp->bus_clks)
+ return -ENOMEM;
+
+ qp->num_clks = ARRAY_SIZE(bus_clocks);
+ ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks);
+ if (ret)
+ return ret;
+
+ ret = clk_bulk_prepare_enable(qp->num_clks, qp->bus_clks);
+ if (ret)
+ return ret;
+
+ provider = &qp->provider;
+ INIT_LIST_HEAD(&provider->nodes);
+ provider->dev = dev;
+ provider->set = qcom_icc_set;
+ provider->aggregate = qcom_icc_aggregate;
+ provider->xlate = of_icc_xlate_onecell;
+ provider->data = data;
+
+ ret = icc_provider_add(provider);
+ if (ret) {
+ dev_err(dev, "error adding interconnect provider: %d\n", ret);
+ clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
+ return ret;
+ }
+
+ for (i = 0; i < num_nodes; i++) {
+ size_t j;
+
+ node = icc_node_create(qnodes[i]->id);
+ if (IS_ERR(node)) {
+ ret = PTR_ERR(node);
+ goto err;
+ }
+
+ node->name = qnodes[i]->name;
+ node->data = qnodes[i];
+ icc_node_add(node, provider);
+
+ dev_dbg(dev, "registered node %s\n", node->name);
+
+ /* populate links */
+ for (j = 0; j < qnodes[i]->num_links; j++)
+ icc_link_create(node, qnodes[i]->links[j]);
+
+ data->nodes[i] = node;
+ }
+ data->num_nodes = num_nodes;
+
+ platform_set_drvdata(pdev, qp);
+
+ return 0;
+err:
+ list_for_each_entry(node, &provider->nodes, node_list) {
+ icc_node_del(node);
+ icc_node_destroy(node->id);
+ }
+ clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
+ icc_provider_del(provider);
+
+ return ret;
+}
+
+static int qnoc_remove(struct platform_device *pdev)
+{
+ struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
+ struct icc_provider *provider = &qp->provider;
+ struct icc_node *n;
+
+ list_for_each_entry(n, &provider->nodes, node_list) {
+ icc_node_del(n);
+ icc_node_destroy(n->id);
+ }
+ clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
+
+ return icc_provider_del(provider);
+}
+
+static const struct of_device_id qcs404_noc_of_match[] = {
+ { .compatible = "qcom,qcs404-bimc", .data = &qcs404_bimc },
+ { .compatible = "qcom,qcs404-pcnoc", .data = &qcs404_pcnoc },
+ { .compatible = "qcom,qcs404-snoc", .data = &qcs404_snoc },
+ { },
+};
+MODULE_DEVICE_TABLE(of, qcs404_noc_of_match);
+
+static struct platform_driver qcs404_noc_driver = {
+ .probe = qnoc_probe,
+ .remove = qnoc_remove,
+ .driver = {
+ .name = "qnoc-qcs404",
+ .of_match_table = qcs404_noc_of_match,
+ },
+};
+module_platform_driver(qcs404_noc_driver);
+MODULE_DESCRIPTION("Qualcomm QCS404 NoC driver");
+MODULE_LICENSE("GPL v2");
^ permalink raw reply related
* [PATCH v5 3/5] interconnect: qcom: Add interconnect SMD over SMD driver
From: Georgi Djakov @ 2019-07-23 14:23 UTC (permalink / raw)
To: robh+dt, bjorn.andersson, agross, georgi.djakov
Cc: vkoul, evgreen, daidavid1, linux-pm, devicetree, linux-arm-msm
In-Reply-To: <20190723142339.27772-1-georgi.djakov@linaro.org>
On some Qualcomm SoCs, there is a remote processor, which controls some of
the Network-On-Chip interconnect resources. Other CPUs express their needs
by communicating with this processor. Add a driver to handle communication
with this remote processor.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
v5:
- Use the more succinct return !!icc_smd_rpm;
- Picked Bjorn's r-b.
v4:
- Hide the driver from config menu. It will be selected by other driver.
- Add remove() function to zero out the rpm handle.
v3:
- New patch.
drivers/interconnect/qcom/Kconfig | 3 ++
drivers/interconnect/qcom/Makefile | 2 +
drivers/interconnect/qcom/smd-rpm.c | 77 +++++++++++++++++++++++++++++
drivers/interconnect/qcom/smd-rpm.h | 15 ++++++
4 files changed, 97 insertions(+)
create mode 100644 drivers/interconnect/qcom/smd-rpm.c
create mode 100644 drivers/interconnect/qcom/smd-rpm.h
diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/Kconfig
index d5e70ebc2410..03fd67173494 100644
--- a/drivers/interconnect/qcom/Kconfig
+++ b/drivers/interconnect/qcom/Kconfig
@@ -12,3 +12,6 @@ config INTERCONNECT_QCOM_SDM845
help
This is a driver for the Qualcomm Network-on-Chip on sdm845-based
platforms.
+
+config INTERCONNECT_QCOM_SMD_RPM
+ tristate
diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom/Makefile
index 1c1cea690f92..a600cf6cc272 100644
--- a/drivers/interconnect/qcom/Makefile
+++ b/drivers/interconnect/qcom/Makefile
@@ -1,5 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
qnoc-sdm845-objs := sdm845.o
+icc-smd-rpm-objs := smd-rpm.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
+obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o
diff --git a/drivers/interconnect/qcom/smd-rpm.c b/drivers/interconnect/qcom/smd-rpm.c
new file mode 100644
index 000000000000..dc8ff8d133a9
--- /dev/null
+++ b/drivers/interconnect/qcom/smd-rpm.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * RPM over SMD communication wrapper for interconnects
+ *
+ * Copyright (C) 2019 Linaro Ltd
+ * Author: Georgi Djakov <georgi.djakov@linaro.org>
+ */
+
+#include <linux/interconnect-provider.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/soc/qcom/smd-rpm.h>
+
+#include "smd-rpm.h"
+
+#define RPM_KEY_BW 0x00007762
+
+static struct qcom_smd_rpm *icc_smd_rpm;
+
+struct icc_rpm_smd_req {
+ __le32 key;
+ __le32 nbytes;
+ __le32 value;
+};
+
+bool qcom_icc_rpm_smd_available(void)
+{
+ return !!icc_smd_rpm;
+}
+EXPORT_SYMBOL_GPL(qcom_icc_rpm_smd_available);
+
+int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val)
+{
+ struct icc_rpm_smd_req req = {
+ .key = cpu_to_le32(RPM_KEY_BW),
+ .nbytes = cpu_to_le32(sizeof(u32)),
+ .value = cpu_to_le32(val),
+ };
+
+ return qcom_rpm_smd_write(icc_smd_rpm, ctx, rsc_type, id, &req,
+ sizeof(req));
+}
+EXPORT_SYMBOL_GPL(qcom_icc_rpm_smd_send);
+
+static int qcom_icc_rpm_smd_remove(struct platform_device *pdev)
+{
+ icc_smd_rpm = NULL;
+
+ return 0;
+}
+
+static int qcom_icc_rpm_smd_probe(struct platform_device *pdev)
+{
+ icc_smd_rpm = dev_get_drvdata(pdev->dev.parent);
+
+ if (!icc_smd_rpm) {
+ dev_err(&pdev->dev, "unable to retrieve handle to RPM\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static struct platform_driver qcom_interconnect_rpm_smd_driver = {
+ .driver = {
+ .name = "icc_smd_rpm",
+ },
+ .probe = qcom_icc_rpm_smd_probe,
+ .remove = qcom_icc_rpm_smd_remove,
+};
+module_platform_driver(qcom_interconnect_rpm_smd_driver);
+MODULE_AUTHOR("Georgi Djakov <georgi.djakov@linaro.org>");
+MODULE_DESCRIPTION("Qualcomm SMD RPM interconnect proxy driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:icc_smd_rpm");
diff --git a/drivers/interconnect/qcom/smd-rpm.h b/drivers/interconnect/qcom/smd-rpm.h
new file mode 100644
index 000000000000..ca9d0327b8ac
--- /dev/null
+++ b/drivers/interconnect/qcom/smd-rpm.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019, Linaro Ltd.
+ * Author: Georgi Djakov <georgi.djakov@linaro.org>
+ */
+
+#ifndef __DRIVERS_INTERCONNECT_QCOM_SMD_RPM_H
+#define __DRIVERS_INTERCONNECT_QCOM_SMD_RPM_H
+
+#include <linux/soc/qcom/smd-rpm.h>
+
+bool qcom_icc_rpm_smd_available(void);
+int qcom_icc_rpm_smd_send(int ctx, int rsc_type, int id, u32 val);
+
+#endif
^ permalink raw reply related
* [PATCH v5 2/5] soc: qcom: smd-rpm: Create RPM interconnect proxy child device
From: Georgi Djakov @ 2019-07-23 14:23 UTC (permalink / raw)
To: robh+dt, bjorn.andersson, agross, georgi.djakov
Cc: vkoul, evgreen, daidavid1, linux-pm, devicetree, linux-arm-msm
In-Reply-To: <20190723142339.27772-1-georgi.djakov@linaro.org>
Register a platform device to handle the communication of bus bandwidth
requests with the remote processor. The interconnect proxy device is part
of this remote processor (RPM) hardware. Let's create a icc-smd-rpm proxy
child device to represent the bus throughput functionality that is provided
by the RPM.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
v5:
- Picked Bjorn's r-b.
v4:
- Return error if platform_device_register_data() fails
- Remove platform_set_drvdata() on the child device.
v3:
- New patch.
drivers/soc/qcom/smd-rpm.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/qcom/smd-rpm.c b/drivers/soc/qcom/smd-rpm.c
index fa9dd12b5e39..34cdd638a6c1 100644
--- a/drivers/soc/qcom/smd-rpm.c
+++ b/drivers/soc/qcom/smd-rpm.c
@@ -19,12 +19,14 @@
/**
* struct qcom_smd_rpm - state of the rpm device driver
* @rpm_channel: reference to the smd channel
+ * @icc: interconnect proxy device
* @ack: completion for acks
* @lock: mutual exclusion around the send/complete pair
* @ack_status: result of the rpm request
*/
struct qcom_smd_rpm {
struct rpmsg_endpoint *rpm_channel;
+ struct platform_device *icc;
struct device *dev;
struct completion ack;
@@ -193,6 +195,7 @@ static int qcom_smd_rpm_callback(struct rpmsg_device *rpdev,
static int qcom_smd_rpm_probe(struct rpmsg_device *rpdev)
{
struct qcom_smd_rpm *rpm;
+ int ret;
rpm = devm_kzalloc(&rpdev->dev, sizeof(*rpm), GFP_KERNEL);
if (!rpm)
@@ -205,11 +208,23 @@ static int qcom_smd_rpm_probe(struct rpmsg_device *rpdev)
rpm->rpm_channel = rpdev->ept;
dev_set_drvdata(&rpdev->dev, rpm);
- return of_platform_populate(rpdev->dev.of_node, NULL, NULL, &rpdev->dev);
+ rpm->icc = platform_device_register_data(&rpdev->dev, "icc_smd_rpm", -1,
+ NULL, 0);
+ if (IS_ERR(rpm->icc))
+ return PTR_ERR(rpm->icc);
+
+ ret = of_platform_populate(rpdev->dev.of_node, NULL, NULL, &rpdev->dev);
+ if (ret)
+ platform_device_unregister(rpm->icc);
+
+ return ret;
}
static void qcom_smd_rpm_remove(struct rpmsg_device *rpdev)
{
+ struct qcom_smd_rpm *rpm = dev_get_drvdata(&rpdev->dev);
+
+ platform_device_unregister(rpm->icc);
of_platform_depopulate(&rpdev->dev);
}
^ permalink raw reply related
* [PATCH v5 1/5] dt-bindings: interconnect: Add Qualcomm QCS404 DT bindings
From: Georgi Djakov @ 2019-07-23 14:23 UTC (permalink / raw)
To: robh+dt, bjorn.andersson, agross, georgi.djakov
Cc: vkoul, evgreen, daidavid1, linux-pm, devicetree, linux-arm-msm
In-Reply-To: <20190723142339.27772-1-georgi.djakov@linaro.org>
The Qualcomm QCS404 platform has several buses that could be controlled
and tuned according to the bandwidth demand.
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
v5:
- Make reg and clocks DT properties required.
- Remove the _clk suffix from clock names.
v4:
- Add the DT header into this patch.
- Pick Bjorn's r-b.
v3:
- Add a reg property and move the interconnect nodes under the "soc" node.
v2:
- No changes.
.../bindings/interconnect/qcom,qcs404.txt | 45 ++++++++++
.../dt-bindings/interconnect/qcom,qcs404.h | 88 +++++++++++++++++++
2 files changed, 133 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,qcs404.txt
create mode 100644 include/dt-bindings/interconnect/qcom,qcs404.h
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,qcs404.txt b/Documentation/devicetree/bindings/interconnect/qcom,qcs404.txt
new file mode 100644
index 000000000000..c07d89812b73
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/qcom,qcs404.txt
@@ -0,0 +1,45 @@
+Qualcomm QCS404 Network-On-Chip interconnect driver binding
+-----------------------------------------------------------
+
+Required properties :
+- compatible : shall contain only one of the following:
+ "qcom,qcs404-bimc"
+ "qcom,qcs404-pcnoc"
+ "qcom,qcs404-snoc"
+- #interconnect-cells : should contain 1
+
+reg : specifies the physical base address and size of registers
+clocks : list of phandles and specifiers to all interconnect bus clocks
+clock-names : clock names should include both "bus" and "bus_a"
+
+Example:
+
+soc {
+ ...
+ bimc: interconnect@400000 {
+ reg = <0x00400000 0x80000>;
+ compatible = "qcom,qcs404-bimc";
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
+ <&rpmcc RPM_SMD_BIMC_A_CLK>;
+ };
+
+ pnoc: interconnect@500000 {
+ reg = <0x00500000 0x15080>;
+ compatible = "qcom,qcs404-pcnoc";
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
+ <&rpmcc RPM_SMD_PNOC_A_CLK>;
+ };
+
+ snoc: interconnect@580000 {
+ reg = <0x00580000 0x23080>;
+ compatible = "qcom,qcs404-snoc";
+ #interconnect-cells = <1>;
+ clock-names = "bus", "bus_a";
+ clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
+ <&rpmcc RPM_SMD_SNOC_A_CLK>;
+ };
+};
diff --git a/include/dt-bindings/interconnect/qcom,qcs404.h b/include/dt-bindings/interconnect/qcom,qcs404.h
new file mode 100644
index 000000000000..960f6e39c5f2
--- /dev/null
+++ b/include/dt-bindings/interconnect/qcom,qcs404.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Qualcomm interconnect IDs
+ *
+ * Copyright (c) 2019, Linaro Ltd.
+ * Author: Georgi Djakov <georgi.djakov@linaro.org>
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QCS404_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_QCS404_H
+
+#define MASTER_AMPSS_M0 0
+#define MASTER_OXILI 1
+#define MASTER_MDP_PORT0 2
+#define MASTER_SNOC_BIMC_1 3
+#define MASTER_TCU_0 4
+#define SLAVE_EBI_CH0 5
+#define SLAVE_BIMC_SNOC 6
+
+#define MASTER_SPDM 0
+#define MASTER_BLSP_1 1
+#define MASTER_BLSP_2 2
+#define MASTER_XI_USB_HS1 3
+#define MASTER_CRYPT0 4
+#define MASTER_SDCC_1 5
+#define MASTER_SDCC_2 6
+#define MASTER_SNOC_PCNOC 7
+#define MASTER_QPIC 8
+#define PCNOC_INT_0 9
+#define PCNOC_INT_2 10
+#define PCNOC_INT_3 11
+#define PCNOC_S_0 12
+#define PCNOC_S_1 13
+#define PCNOC_S_2 14
+#define PCNOC_S_3 15
+#define PCNOC_S_4 16
+#define PCNOC_S_6 17
+#define PCNOC_S_7 18
+#define PCNOC_S_8 19
+#define PCNOC_S_9 20
+#define PCNOC_S_10 21
+#define PCNOC_S_11 22
+#define SLAVE_SPDM 23
+#define SLAVE_PDM 24
+#define SLAVE_PRNG 25
+#define SLAVE_TCSR 26
+#define SLAVE_SNOC_CFG 27
+#define SLAVE_MESSAGE_RAM 28
+#define SLAVE_DISP_SS_CFG 29
+#define SLAVE_GPU_CFG 30
+#define SLAVE_BLSP_1 31
+#define SLAVE_BLSP_2 32
+#define SLAVE_TLMM_NORTH 33
+#define SLAVE_PCIE 34
+#define SLAVE_ETHERNET 35
+#define SLAVE_TLMM_EAST 36
+#define SLAVE_TCU 37
+#define SLAVE_PMIC_ARB 38
+#define SLAVE_SDCC_1 39
+#define SLAVE_SDCC_2 40
+#define SLAVE_TLMM_SOUTH 41
+#define SLAVE_USB_HS 42
+#define SLAVE_USB3 43
+#define SLAVE_CRYPTO_0_CFG 44
+#define SLAVE_PCNOC_SNOC 45
+
+#define MASTER_QDSS_BAM 0
+#define MASTER_BIMC_SNOC 1
+#define MASTER_PCNOC_SNOC 2
+#define MASTER_QDSS_ETR 3
+#define MASTER_EMAC 4
+#define MASTER_PCIE 5
+#define MASTER_USB3 6
+#define QDSS_INT 7
+#define SNOC_INT_0 8
+#define SNOC_INT_1 9
+#define SNOC_INT_2 10
+#define SLAVE_KPSS_AHB 11
+#define SLAVE_WCSS 12
+#define SLAVE_SNOC_BIMC_1 13
+#define SLAVE_IMEM 14
+#define SLAVE_SNOC_PCNOC 15
+#define SLAVE_QDSS_STM 16
+#define SLAVE_CATS_0 17
+#define SLAVE_CATS_1 18
+#define SLAVE_LPASS 19
+
+#endif
^ permalink raw reply related
* [PATCH v5 0/5] Add QCS404 interconnect provider driver
From: Georgi Djakov @ 2019-07-23 14:23 UTC (permalink / raw)
To: robh+dt, bjorn.andersson, agross, georgi.djakov
Cc: vkoul, evgreen, daidavid1, linux-pm, devicetree, linux-arm-msm
Add drivers to support scaling of the on-chip interconnects on QCS404-based
platforms. Also add the necessary device-tree nodes, so that the driver for
each NoC can probe and register as interconnect-provider.
The plan is to get patches 2,5 through the Qcom/ARM tree and the rest
through the interconnect tree.
v5:
- Make reg and clocks DT properties required. (Bjorn)
- Remove _clk suffix from clock names. (Bjorn)
- Use the more succinct return !!icc_smd_rpm; (Bjorn)
v4: https://lore.kernel.org/lkml/20190613151323.10850-1-georgi.djakov@linaro.org/
- Move DT headers into the dt-bindings patch (Bjorn)
- Pick Bjorn's r-b on some patches.
- Return error if platform_device_register_data() fails (Bjorn)
- Use platform_set_drvdata() only in the child device. (Bjorn)
- Hide the smd-rpm proxy driver from config menu. (Bjorn)
- Add remove() function to zero out the rpm handle. (Bjorn)
- Move move the qcs404 driver patch later in the serie. (Bjorn)
- Insert the DT nodes after rng to keep the list sorted by address. (Bjorn)
v3: https://lore.kernel.org/lkml/20190611164157.24656-1-georgi.djakov@linaro.org/
- Drop the patch introducing the qcom,qos DT property.
- Add two new patches to create an interconnect proxy device. This device is
part of the RPM hardware and handles the communication of the bus bandwidth
requests.
- Add a DT reg property and move the interconnect nodes under the "soc" node.
v2: https://lore.kernel.org/lkml/20190415104357.5305-1-georgi.djakov@linaro.org/
- Use the clk_bulk API. (Bjorn)
- Move the port IDs into the provider file. (Bjorn)
- Use ARRAY_SIZE in the macro to automagically count the num_links. (Bjorn)
- Improve code readability. (Bjorn)
- Add patch [4/4] introducing a qcom,qos DT property to represent the link to
the MMIO QoS registers HW block.
v1: https://lore.kernel.org/lkml/20190405035446.31886-1-georgi.djakov@linaro.org/
Bjorn Andersson (1):
interconnect: qcom: Add QCS404 interconnect provider driver
Georgi Djakov (4):
dt-bindings: interconnect: Add Qualcomm QCS404 DT bindings
soc: qcom: smd-rpm: Create RPM interconnect proxy child device
interconnect: qcom: Add interconnect SMD over SMD driver
arm64: dts: qcs404: Add interconnect provider DT nodes
.../bindings/interconnect/qcom,qcs404.txt | 45 ++
arch/arm64/boot/dts/qcom/qcs404.dtsi | 28 +
drivers/interconnect/qcom/Kconfig | 12 +
drivers/interconnect/qcom/Makefile | 4 +
drivers/interconnect/qcom/qcs404.c | 539 ++++++++++++++++++
drivers/interconnect/qcom/smd-rpm.c | 77 +++
drivers/interconnect/qcom/smd-rpm.h | 15 +
drivers/soc/qcom/smd-rpm.c | 17 +-
.../dt-bindings/interconnect/qcom,qcs404.h | 88 +++
9 files changed, 824 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,qcs404.txt
create mode 100644 drivers/interconnect/qcom/qcs404.c
create mode 100644 drivers/interconnect/qcom/smd-rpm.c
create mode 100644 drivers/interconnect/qcom/smd-rpm.h
create mode 100644 include/dt-bindings/interconnect/qcom,qcs404.h
^ permalink raw reply
* Re: [PATCH v2 1/9] soc: samsung: Add exynos chipid driver support
From: Bartlomiej Zolnierkiewicz @ 2019-07-23 14:10 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Sylwester Nawrocki, robh+dt, vireshk, devicetree, kgene,
pankaj.dubey, linux-samsung-soc@vger.kernel.org, linux-arm-kernel,
linux-kernel, linux-pm, Marek Szyprowski
In-Reply-To: <CAJKOXPfLBif-=09B9jZ3qN1kWdTAcrBQZGvZ+A-MUifXK4si9Q@mail.gmail.com>
Hi Krzysztof,
On 7/23/19 2:57 PM, Krzysztof Kozlowski wrote:
> On Thu, 18 Jul 2019 at 16:31, Sylwester Nawrocki <s.nawrocki@samsung.com> wrote:
>>
>> From: Pankaj Dubey <pankaj.dubey@samsung.com>
>>
>> Exynos SoCs have Chipid, for identification of product IDs and SoC
>> revisions. This patch intends to provide initialization code for all
>> these functionalities, at the same time it provides some sysfs entries
>> for accessing these information to user-space.
>>
>> This driver uses existing binding for exynos-chipid.
>>
>> Changes by Bartlomiej:
>> - fixed return values on errors
>> - removed bogus kfree_const()
>> - added missing Exynos4210 EVT0 id
>> - converted code to use EXYNOS_MASK define
>> - fixed np use after of_node_put()
>> - fixed too early use of dev_info()
>> - made driver fail for unknown SoC-s
>> - added SPDX tag
>> - updated Copyrights
>>
>> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
>> [m.szyprowski: for suggestion and code snippet of product_id_to_soc_id]
>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
>> [s.nawrocki: updated copyright date]
>> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
>> ---
>> drivers/soc/samsung/Kconfig | 5 ++
>> drivers/soc/samsung/Makefile | 2 +
>> drivers/soc/samsung/exynos-chipid.c | 111 ++++++++++++++++++++++++++++
>> 3 files changed, 118 insertions(+)
>> create mode 100644 drivers/soc/samsung/exynos-chipid.c
>>
>> diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig
>> index 2186285fda92..2905f5262197 100644
>> --- a/drivers/soc/samsung/Kconfig
>> +++ b/drivers/soc/samsung/Kconfig
>> @@ -7,6 +7,11 @@ menuconfig SOC_SAMSUNG
>>
>> if SOC_SAMSUNG
>>
>> +config EXYNOS_CHIPID
>> + bool "Exynos Chipid controller driver" if COMPILE_TEST
>> + depends on ARCH_EXYNOS || COMPILE_TEST
>> + select SOC_BUS
>> +
>> config EXYNOS_PMU
>> bool "Exynos PMU controller driver" if COMPILE_TEST
>> depends on ARCH_EXYNOS || ((ARM || ARM64) && COMPILE_TEST)
>> diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile
>> index 29f294baac6e..3b6a8797416c 100644
>> --- a/drivers/soc/samsung/Makefile
>> +++ b/drivers/soc/samsung/Makefile
>> @@ -1,4 +1,6 @@
>> # SPDX-License-Identifier: GPL-2.0
>> +
>> +obj-$(CONFIG_EXYNOS_CHIPID) += exynos-chipid.o
>> obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o
>>
>> obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS) += exynos3250-pmu.o exynos4-pmu.o \
>> diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c
>> new file mode 100644
>> index 000000000000..78b123ee60c0
>> --- /dev/null
>> +++ b/drivers/soc/samsung/exynos-chipid.c
>> @@ -0,0 +1,111 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (c) 2019 Samsung Electronics Co., Ltd.
>> + * http://www.samsung.com/
>> + *
>> + * EXYNOS - CHIP ID support
>> + * Author: Pankaj Dubey <pankaj.dubey@samsung.com>
>> + * Author: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
>> + */
>> +
>> +#include <linux/io.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/platform_device.h>
>
> Any changes here from my previous comments?
>
> I have also one more new thought later.
>
>> +#include <linux/slab.h>
>> +#include <linux/sys_soc.h>
>> +
>> +#define EXYNOS_SUBREV_MASK (0xF << 4)
>> +#define EXYNOS_MAINREV_MASK (0xF << 0)
>> +#define EXYNOS_REV_MASK (EXYNOS_SUBREV_MASK | EXYNOS_MAINREV_MASK)
>> +#define EXYNOS_MASK 0xFFFFF000
>> +
>> +static const struct exynos_soc_id {
>> + const char *name;
>> + unsigned int id;
>> +} soc_ids[] = {
>> + { "EXYNOS3250", 0xE3472000 },
>> + { "EXYNOS4210", 0x43200000 }, /* EVT0 revision */
>> + { "EXYNOS4210", 0x43210000 },
>> + { "EXYNOS4212", 0x43220000 },
>> + { "EXYNOS4412", 0xE4412000 },
>> + { "EXYNOS5250", 0x43520000 },
>> + { "EXYNOS5260", 0xE5260000 },
>> + { "EXYNOS5410", 0xE5410000 },
>> + { "EXYNOS5420", 0xE5420000 },
>> + { "EXYNOS5440", 0xE5440000 },
>> + { "EXYNOS5800", 0xE5422000 },
>> + { "EXYNOS7420", 0xE7420000 },
>> + { "EXYNOS5433", 0xE5433000 },
>> +};
>> +
>> +static const char * __init product_id_to_soc_id(unsigned int product_id)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < ARRAY_SIZE(soc_ids); i++)
>> + if ((product_id & EXYNOS_MASK) == soc_ids[i].id)
>> + return soc_ids[i].name;
>> + return NULL;
>> +}
>> +
>> +int __init exynos_chipid_early_init(void)
>> +{
>> + struct soc_device_attribute *soc_dev_attr;
>> + void __iomem *exynos_chipid_base;
>> + struct soc_device *soc_dev;
>> + struct device_node *root;
>> + struct device_node *np;
>> + u32 product_id;
>> + u32 revision;
>> +
>> + /* look up for chipid node */
>> + np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
>> + if (!np)
>> + return -ENODEV;
>> +
>> + exynos_chipid_base = of_iomap(np, 0);
>> + of_node_put(np);
>> +
>> + if (!exynos_chipid_base) {
>> + pr_err("Failed to map SoC chipid\n");
>> + return -ENXIO;
>> + }
>> +
>> + product_id = readl_relaxed(exynos_chipid_base);
>> + revision = product_id & EXYNOS_REV_MASK;
>> + iounmap(exynos_chipid_base);
>> +
>> + soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
>> + if (!soc_dev_attr)
>> + return -ENOMEM;
>> +
>> + soc_dev_attr->family = "Samsung Exynos";
>> +
>> + root = of_find_node_by_path("/");
>> + of_property_read_string(root, "model", &soc_dev_attr->machine);
>> + of_node_put(root);
>> +
>> + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%x", revision);
>> + soc_dev_attr->soc_id = product_id_to_soc_id(product_id);
>> + if (!soc_dev_attr->soc_id) {
>> + pr_err("Unknown SoC\n");
>
> In case of running old kernel on unknown SoC (new revision of existing
> one or older design not longer supported like 4415), the device will
> not bind. This was added by Bartlomiej. Why? I imagine that soc driver
> could be still matched and just report "Unknown". I am not sure if
> this changes anything, though.
I was thinking that we shouldn't be pretending that we know how to
handle unsupported SoCs, i.e. that we know how to correctly read its
product_id and revision.
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
> Best regards,
> Krzysztof
>
>
>> + return -ENODEV;
>> + }
>> +
>> + /* please note that the actual registration will be deferred */
>> + soc_dev = soc_device_register(soc_dev_attr);
>> + if (IS_ERR(soc_dev)) {
>> + kfree(soc_dev_attr->revision);
>> + kfree(soc_dev_attr);
>> + return PTR_ERR(soc_dev);
>> + }
>> +
>> + /* it is too early to use dev_info() here (soc_dev is NULL) */
>> + pr_info("soc soc0: Exynos: CPU[%s] PRO_ID[0x%x] REV[0x%x] Detected\n",
>> + soc_dev_attr->soc_id, product_id, revision);
>> +
>> + return 0;
>> +}
>> +early_initcall(exynos_chipid_early_init);
>> --
>> 2.17.1
^ permalink raw reply
* Re: [PATCH 5/5] ARM: dts: armada385-wd-mcex2u: Add DTS file for WD My Cloud EX2 Ultra
From: Andrew Lunn @ 2019-07-23 13:48 UTC (permalink / raw)
To: Evgeny Kolesnikov
Cc: Sebastian Reichel, Rob Herring, Mark Rutland, Jason Cooper,
Gregory Clement, Sebastian Hesselbarth, linux-pm, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <fd2a97d627c21a7e92a9a1aa15cf26c608d1e383.1563822216.git.evgenyz@gmail.com>
> + internal-regs {
> + timer@c200 {
> + status = "disabled";
> + };
> +
> + i2c0: i2c@11000 {
> + status = "okay";
> + clock-frequency = <100000>;
> + };
> +
> + i2c1: i2c@11100 {
> + status = "okay";
> + clock-frequency = <100000>;
> + };
It is a bit unusual to enable i2c busses when there is nothing on
them.
> + ethernet@34000 {
> + phy = <&phy0>;
phy has been deprecated. Please use phy-handle.
Andrew
^ permalink raw reply
* Re: [PATCH v2 3/9] soc: samsung: Add Exynos Adaptive Supply Voltage driver
From: Krzysztof Kozlowski @ 2019-07-23 13:38 UTC (permalink / raw)
To: Sylwester Nawrocki
Cc: robh+dt, vireshk, devicetree, kgene, pankaj.dubey,
linux-samsung-soc@vger.kernel.org, linux-arm-kernel, linux-kernel,
linux-pm, Bartłomiej Żołnierkiewicz,
Marek Szyprowski
In-Reply-To: <20190718143044.25066-4-s.nawrocki@samsung.com>
On Thu, 18 Jul 2019 at 16:31, Sylwester Nawrocki <s.nawrocki@samsung.com> wrote:
>
> The Adaptive Supply Voltage (ASV) driver adjusts CPU cluster operating
> points depending on exact revision of an SoC retrieved from the CHIPID
> block or the OTP memory. This allows for some power saving as for some
> CPU clock frequencies we can lower CPU cluster supply voltage comparing
> to safe values common to the all chip revisions.
>
> This patch adds support for Exynos5422/5800 SoC, it is partially based
> on code from https://github.com/hardkernel/linux repository,
> branch odroidxu4-4.14.y, files: arch/arm/mach-exynos/exynos5422-asv.[ch].
>
> Tested on Odroid XU3, XU4, XU3 Lite.
>
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> ---
> Changes since v1 (RFC):
> - removed code for parsing the ASV OPP tables from DT, the ASV OPP tables
> moved to the driver;
> - converted to use the regmap API;
> - converted to normal platform driver.
> ---
> drivers/soc/samsung/Kconfig | 11 +
> drivers/soc/samsung/Makefile | 3 +
> drivers/soc/samsung/exynos-asv.c | 185 ++++++++++
> drivers/soc/samsung/exynos-asv.h | 82 +++++
> drivers/soc/samsung/exynos5422-asv.c | 499 +++++++++++++++++++++++++++
> drivers/soc/samsung/exynos5422-asv.h | 25 ++
> 6 files changed, 805 insertions(+)
> create mode 100644 drivers/soc/samsung/exynos-asv.c
> create mode 100644 drivers/soc/samsung/exynos-asv.h
> create mode 100644 drivers/soc/samsung/exynos5422-asv.c
> create mode 100644 drivers/soc/samsung/exynos5422-asv.h
>
> diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig
> index 2905f5262197..539cd95dd176 100644
> --- a/drivers/soc/samsung/Kconfig
> +++ b/drivers/soc/samsung/Kconfig
> @@ -7,6 +7,17 @@ menuconfig SOC_SAMSUNG
>
> if SOC_SAMSUNG
>
> +config EXYNOS_ASV
> + bool "Exynos Adaptive Supply Voltage support" if COMPILE_TEST
> + depends on ARCH_EXYNOS || COMPILE_TEST
> + depends on EXYNOS_CHIPID
(ARCH_EXYNOS && EXYNOS_CHIPID) || COMPILE_TEST
> + select EXYNOS_ASV_ARM if ARM && ARCH_EXYNOS
> +
> +# There is no need to enable these drivers for ARMv8
> +config EXYNOS_ASV_ARM
> + bool "Exynos ASV ARMv7-specific driver extensions" if COMPILE_TEST
> + depends on EXYNOS_ASV
> +
> config EXYNOS_CHIPID
> bool "Exynos Chipid controller driver" if COMPILE_TEST
> depends on ARCH_EXYNOS || COMPILE_TEST
> diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile
> index 3b6a8797416c..edd1d6ea064d 100644
> --- a/drivers/soc/samsung/Makefile
> +++ b/drivers/soc/samsung/Makefile
> @@ -1,5 +1,8 @@
> # SPDX-License-Identifier: GPL-2.0
>
> +obj-$(CONFIG_EXYNOS_ASV) += exynos-asv.o
> +obj-$(CONFIG_EXYNOS_ASV_ARM) += exynos5422-asv.o
> +
> obj-$(CONFIG_EXYNOS_CHIPID) += exynos-chipid.o
> obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o
>
> diff --git a/drivers/soc/samsung/exynos-asv.c b/drivers/soc/samsung/exynos-asv.c
> new file mode 100644
> index 000000000000..b1a7e0ba8870
> --- /dev/null
> +++ b/drivers/soc/samsung/exynos-asv.c
> @@ -0,0 +1,185 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com/
> + * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
> + *
> + * Samsung Exynos SoC Adaptive Supply Voltage support
> + */
> +
> +#include <linux/cpu.h>
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/errno.h>
> +#include <linux/init.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_opp.h>
> +#include <linux/regmap.h>
> +#include <linux/slab.h>
> +#include <linux/soc/samsung/exynos-chipid.h>
> +
> +#include "exynos-asv.h"
> +#include "exynos5422-asv.h"
> +
> +#define MHZ 1000000U
> +
> +static int exynos_asv_update_cpu_opps(struct exynos_asv *asv,
> + struct device *cpu)
> +{
> + struct exynos_asv_subsys *subsys = NULL;
> + struct dev_pm_opp *opp;
> + unsigned int opp_freq;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(asv->subsys); i++) {
> + if (of_device_is_compatible(cpu->of_node,
> + asv->subsys[i].cpu_dt_compat)) {
> + subsys = &asv->subsys[i];
> + break;
> + }
> + }
> + if (!subsys)
> + return -EINVAL;
> +
> + for (i = 0; i < subsys->table.num_rows; i++) {
> + unsigned int new_voltage;
> + unsigned int voltage;
> + int timeout = 1000;
> + int err;
> +
> + opp_freq = exynos_asv_opp_get_frequency(subsys, i);
> +
> + opp = dev_pm_opp_find_freq_exact(cpu, opp_freq * MHZ, true);
> + if (IS_ERR(opp)) {
> + dev_info(asv->dev, "cpu%d opp%d, freq: %u missing\n",
> + cpu->id, i, opp_freq);
> +
> + continue;
> + }
> +
> + voltage = dev_pm_opp_get_voltage(opp);
> + new_voltage = asv->opp_get_voltage(subsys, i, voltage);
> + dev_pm_opp_put(opp);
> +
> + opp_freq *= MHZ;
> + dev_pm_opp_remove(cpu, opp_freq);
> +
> + while (--timeout) {
> + opp = dev_pm_opp_find_freq_exact(cpu, opp_freq, true);
> + if (IS_ERR(opp))
> + break;
> + dev_pm_opp_put(opp);
> + msleep(1);
> + }
> +
> + err = dev_pm_opp_add(cpu, opp_freq, new_voltage);
> + if (err < 0)
> + dev_err(asv->dev,
> + "Failed to add OPP %u Hz/%u uV for cpu%d\n",
> + opp_freq, new_voltage, cpu->id);
> + }
> +
> + return 0;
> +}
> +
> +static int exynos_asv_update_opps(struct exynos_asv *asv)
> +{
> + struct opp_table *last_opp_table = NULL;
> + struct device *cpu;
> + int ret, cpuid;
> +
> + for_each_possible_cpu(cpuid) {
> + struct opp_table *opp_table;
> +
> + cpu = get_cpu_device(cpuid);
> + if (!cpu)
> + continue;
> +
> + opp_table = dev_pm_opp_get_opp_table(cpu);
> + if (IS_ERR(opp_table))
> + continue;
> +
> + if (!last_opp_table || opp_table != last_opp_table) {
> + last_opp_table = opp_table;
> +
> + ret = exynos_asv_update_cpu_opps(asv, cpu);
> + if (ret < 0)
> + dev_err(asv->dev, "Couldn't udate OPPs for cpu%d\n",
> + cpuid);
> + }
> +
> + dev_pm_opp_put_opp_table(opp_table);
> + }
> +
> + return 0;
> +}
> +
> +static int exynos_asv_probe(struct platform_device *pdev)
> +{
> + int (*probe_func)(struct exynos_asv *asv);
> + struct exynos_asv *asv;
> + struct device *cpu_dev;
> + u32 product_id = 0;
> + int ret, i;
> +
> + cpu_dev = get_cpu_device(0);
> + ret = dev_pm_opp_get_opp_count(cpu_dev);
> + if (ret < 0)
> + return -EPROBE_DEFER;
> +
> + asv = kcalloc(1, sizeof(*asv), GFP_KERNEL);
> + if (!asv)
> + return -ENOMEM;
> +
> + asv->chipid_regmap = syscon_node_to_regmap(pdev->dev.of_node);
> + if (IS_ERR(asv->chipid_regmap)) {
> + dev_err(&pdev->dev, "Could not find syscon regmap\n");
Here and in following error-paths - kfree().
> + return PTR_ERR(asv->chipid_regmap);
> + }
> +
> + regmap_read(asv->chipid_regmap, EXYNOS_CHIPID_REG_PRO_ID, &product_id);
> +
> + switch (product_id & EXYNOS_MASK) {
> + case 0xE5422000:
> + probe_func = exynos5422_asv_init;
> + break;
> + default:
> + dev_err(&pdev->dev, "Unsupported product ID: %#x", product_id);
> + return -ENODEV;
> + }
> +
> + ret = of_property_read_u32(pdev->dev.of_node, "samsung,asv-bin",
> + &asv->of_bin);
> + if (ret < 0)
> + asv->of_bin = -EINVAL;
> +
> + asv->dev = &pdev->dev;
> + dev_set_drvdata(&pdev->dev, asv);
> +
> + for (i = 0; i < ARRAY_SIZE(asv->subsys); i++)
> + asv->subsys[i].asv = asv;
> +
> + ret = probe_func(asv);
> + if (ret < 0)
> + return ret;
> +
> + return exynos_asv_update_opps(asv);
> +}
> +
> +static const struct of_device_id exynos_asv_of_device_ids[] = {
> + { .compatible = "samsung,exynos4210-chipid" },
> + {}
> +};
> +
> +static struct platform_driver exynos_asv_driver = {
> + .driver = {
> + .name = "exynos-asv",
> + .of_match_table = exynos_asv_of_device_ids,
> + },
> + .probe = exynos_asv_probe,
> +};
> +module_platform_driver(exynos_asv_driver);
> diff --git a/drivers/soc/samsung/exynos-asv.h b/drivers/soc/samsung/exynos-asv.h
> new file mode 100644
> index 000000000000..d0a5d603093d
> --- /dev/null
> +++ b/drivers/soc/samsung/exynos-asv.h
> @@ -0,0 +1,82 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2019 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com/
> + * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
> + *
> + * Samsung Exynos SoC Adaptive Supply Voltage support
> + */
> +#ifndef _EXYNOS_ASV_H
> +#define _EXYNOS_ASV_H
Here and in other header use prefix:
__LINUX_SOC_
(just like the existing exynos-pmu.h)
> +
> +enum {
> + EXYNOS_ASV_SUBSYS_ID_ARM,
> + EXYNOS_ASV_SUBSYS_ID_EGL = EXYNOS_ASV_SUBSYS_ID_ARM,
> + EXYNOS_ASV_SUBSYS_ID_KFC,
> + EXYNOS_ASV_SUBSYS_ID_INT,
> + EXYNOS_ASV_SUBSYS_ID_MIF,
> + EXYNOS_ASV_SUBSYS_ID_G3D,
> + EXYNOS_ASV_SUBSYS_ID_CAM,
> + EXYNOS_ASV_SUBSYS_ID_MAX
> +};
> +
> +struct regmap;
> +
> +/* HPM, IDS values to select target group */
> +struct asv_limit_entry {
> + unsigned int hpm;
> + unsigned int ids;
> +};
> +
> +struct exynos_asv_table {
> + unsigned int num_rows;
> + unsigned int num_cols;
> + u32 *buf;
> +};
> +
> +struct exynos_asv_subsys {
> + struct exynos_asv *asv;
> + char *cpu_dt_compat;
const char *
> + int id;
> + struct exynos_asv_table table;
> +
> + unsigned int base_volt;
> + unsigned int offset_volt_h;
> + unsigned int offset_volt_l;
> +};
> +
> +struct exynos_asv {
> + struct device *dev;
> + struct regmap *chipid_regmap;
> + struct exynos_asv_subsys subsys[2];
> +
> + int (*opp_get_voltage)(struct exynos_asv_subsys *subs, int level,
> + unsigned int voltage);
> + unsigned int group;
> + unsigned int table;
> +
> + /* True if SG fields from PKG_ID register should be used */
> + bool use_sg;
> + /* ASV bin read from DT */
> + int of_bin;
> +};
> +
> +static inline u32 __asv_get_table_entry(struct exynos_asv_table *table,
> + unsigned int row, unsigned int col)
> +{
> + return table->buf[row * (table->num_cols) + col];
> +}
> +
> +static inline u32 exynos_asv_opp_get_voltage(struct exynos_asv_subsys *subsys,
> + unsigned int level, unsigned int group)
> +{
> + return __asv_get_table_entry(&subsys->table, level, group + 1);
> +}
> +
> +static inline u32 exynos_asv_opp_get_frequency(struct exynos_asv_subsys *subsys,
> + unsigned int level)
> +{
> + return __asv_get_table_entry(&subsys->table, level, 0);
> +}
> +
> +#endif /* _EXYNOS_ASV_H */
> diff --git a/drivers/soc/samsung/exynos5422-asv.c b/drivers/soc/samsung/exynos5422-asv.c
> new file mode 100644
> index 000000000000..5fd673a6a733
> --- /dev/null
> +++ b/drivers/soc/samsung/exynos5422-asv.c
> @@ -0,0 +1,499 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com/
> + *
> + * Samsung Exynos 5422 SoC Adaptive Supply Voltage support
> + */
> +
> +#include <linux/bitrev.h>
> +#include <linux/device.h>
> +#include <linux/errno.h>
> +#include <linux/init.h>
Looks unused.
> +#include <linux/of.h>
> +#include <linux/regmap.h>
> +#include <linux/soc/samsung/exynos-chipid.h>
> +#include <linux/slab.h>
> +
> +#include "exynos-asv.h"
> +
> +#define ASV_GROUPS_NUM 14
> +#define ASV_ARM_DVFS_NUM 20
> +#define ASV_ARM_BIN2_DVFS_NUM 17
> +#define ASV_KFC_DVFS_NUM 14
> +#define ASV_KFC_BIN2_DVFS_NUM 12
> +
> +static const u32 asv_arm_table[][ASV_ARM_DVFS_NUM][ASV_GROUPS_NUM + 1] = {
> +{
> + /* ARM 0, 1 */
> + { 2100, 1362500, 1362500, 1350000, 1337500, 1325000, 1312500, 1300000,
> + 1275000, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000 },
> + { 2000, 1312500, 1312500, 1300000, 1287500, 1275000, 1262500, 1250000,
> + 1237500, 1225000, 1237500, 1225000, 1212500, 1200000, 1187500 },
> + { 1900, 1250000, 1237500, 1225000, 1212500, 1200000, 1187500, 1175000,
> + 1162500, 1150000, 1162500, 1150000, 1137500, 1125000, 1112500 },
> + { 1800, 1200000, 1187500, 1175000, 1162500, 1150000, 1137500, 1125000,
> + 1112500, 1100000, 1112500, 1100000, 1087500, 1075000, 1062500 },
> + { 1700, 1162500, 1150000, 1137500, 1125000, 1112500, 1100000, 1087500,
> + 1075000, 1062500, 1075000, 1062500, 1050000, 1037500, 1025000 },
> + { 1600, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500, 1050000,
> + 1037500, 1025000, 1037500, 1025000, 1012500, 1000000, 987500 },
> + { 1500, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500,
> + 1000000, 987500, 1000000, 987500, 975000, 962500, 950000 },
> + { 1400, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, 987500,
> + 975000, 962500, 975000, 962500, 950000, 937500, 925000 },
> + { 1300, 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 975000,
> + 962500, 950000, 962500, 950000, 937500, 925000, 912500 },
> + { 1200, 1025000, 1012500, 1000000, 987500, 975000, 962500, 950000,
> + 937500, 925000, 937500, 925000, 912500, 900000, 900000 },
> + { 1100, 1000000, 987500, 975000, 962500, 950000, 937500, 925000,
> + 912500, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 1000, 975000, 962500, 950000, 937500, 925000, 912500, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 900, 950000, 937500, 925000, 912500, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 800, 925000, 912500, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 700, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 600, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 500, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 400, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 300, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 200, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> +}, {
> + /* ARM 2 */
> + { 2100, 1362500, 1362500, 1350000, 1337500, 1325000, 1312500, 1300000,
> + 1275000, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000 },
> + { 2000, 1312500, 1312500, 1312500, 1300000, 1275000, 1262500, 1250000,
> + 1237500, 1225000, 1237500, 1225000, 1212500, 1200000, 1187500 },
> + { 1900, 1262500, 1250000, 1250000, 1237500, 1212500, 1200000, 1187500,
> + 1175000, 1162500, 1175000, 1162500, 1150000, 1137500, 1125000 },
> + { 1800, 1212500, 1200000, 1187500, 1175000, 1162500, 1150000, 1137500,
> + 1125000, 1112500, 1125000, 1112500, 1100000, 1087500, 1075000 },
> + { 1700, 1175000, 1162500, 1150000, 1137500, 1125000, 1112500, 1100000,
> + 1087500, 1075000, 1087500, 1075000, 1062500, 1050000, 1037500 },
> + { 1600, 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500,
> + 1050000, 1037500, 1050000, 1037500, 1025000, 1012500, 1000000 },
> + { 1500, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000,
> + 1012500, 1000000, 1012500, 1000000, 987500, 975000, 962500 },
> + { 1400, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000,
> + 987500, 975000, 987500, 975000, 962500, 950000, 937500 },
> + { 1300, 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 975000,
> + 962500, 950000, 962500, 950000, 937500, 925000, 912500 },
> + { 1200, 1025000, 1012500, 1000000, 987500, 975000, 962500, 950000,
> + 937500, 925000, 937500, 925000, 912500, 900000, 900000 },
> + { 1100, 1000000, 987500, 975000, 962500, 950000, 937500, 925000,
> + 912500, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 1000, 975000, 962500, 950000, 937500, 925000, 912500, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 900, 950000, 937500, 925000, 912500, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 800, 925000, 912500, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 700, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 600, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 500, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 400, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 300, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 200, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> +}, {
> + /* ARM 3 */
> + { 2100, 1362500, 1362500, 1350000, 1337500, 1325000, 1312500, 1300000,
> + 1275000, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000 },
> + { 2000, 1312500, 1312500, 1300000, 1287500, 1275000, 1262500, 1250000,
> + 1237500, 1225000, 1237500, 1225000, 1212500, 1200000, 1187500 },
> + { 1900, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000, 1187500,
> + 1175000, 1162500, 1175000, 1162500, 1150000, 1137500, 1125000 },
> + { 1800, 1212500, 1200000, 1187500, 1175000, 1162500, 1150000, 1137500,
> + 1125000, 1112500, 1125000, 1112500, 1100000, 1087500, 1075000 },
> + { 1700, 1175000, 1162500, 1150000, 1137500, 1125000, 1112500, 1100000,
> + 1087500, 1075000, 1087500, 1075000, 1062500, 1050000, 1037500 },
> + { 1600, 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500,
> + 1050000, 1037500, 1050000, 1037500, 1025000, 1012500, 1000000 },
> + { 1500, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000,
> + 1012500, 1000000, 1012500, 1000000, 987500, 975000, 962500 },
> + { 1400, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000,
> + 987500, 975000, 987500, 975000, 962500, 950000, 937500 },
> + { 1300, 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 975000,
> + 962500, 950000, 962500, 950000, 937500, 925000, 912500 },
> + { 1200, 1025000, 1012500, 1000000, 987500, 975000, 962500, 950000,
> + 937500, 925000, 937500, 925000, 912500, 900000, 900000 },
> + { 1100, 1000000, 987500, 975000, 962500, 950000, 937500, 925000,
> + 912500, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 1000, 975000, 962500, 950000, 937500, 925000, 912500, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 900, 950000, 937500, 925000, 912500, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 800, 925000, 912500, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 700, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 600, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 500, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 400, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 300, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 200, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> +}, {
> + /* ARM bin 2 */
> + { 1800, 1237500, 1225000, 1212500, 1200000, 1187500, 1175000, 1162500,
> + 1150000, 1137500, 1150000, 1137500, 1125000, 1112500, 1100000 },
> + { 1700, 1200000, 1187500, 1175000, 1162500, 1150000, 1137500, 1125000,
> + 1112500, 1100000, 1112500, 1100000, 1087500, 1075000, 1062500 },
> + { 1600, 1162500, 1150000, 1137500, 1125000, 1112500, 1100000, 1087500,
> + 1075000, 1062500, 1075000, 1062500, 1050000, 1037500, 1025000 },
> + { 1500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500, 1050000,
> + 1037500, 1025000, 1037500, 1025000, 1012500, 1000000, 987500 },
> + { 1400, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000,
> + 1012500, 1000000, 1012500, 1000000, 987500, 975000, 962500 },
> + { 1300, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500,
> + 1000000, 987500, 1000000, 987500, 975000, 962500, 950000 },
> + { 1200, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, 987500,
> + 975000, 962500, 975000, 962500, 950000, 937500, 925000 },
> + { 1100, 1037500, 1025000, 1012500, 1000000, 987500, 975000, 962500,
> + 950000, 937500, 950000, 937500, 925000, 912500, 900000 },
> + { 1000, 1012500, 1000000, 987500, 975000, 962500, 950000, 937500,
> + 925000, 912500, 925000, 912500, 900000, 900000, 900000 },
> + { 900, 987500, 975000, 962500, 950000, 937500, 925000, 912500,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 800, 962500, 950000, 937500, 925000, 912500, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 700, 937500, 925000, 912500, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 600, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 500, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 400, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 300, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 200, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> +}
> +};
> +
> +static const u32 asv_kfc_table[][ASV_KFC_DVFS_NUM][ASV_GROUPS_NUM + 1] = {
> +{
> + /* KFC 0, 1 */
> + { 1500000, 1300000, 1300000, 1300000, 1287500, 1287500, 1287500, 1275000,
> + 1262500, 1250000, 1237500, 1225000, 1212500, 1200000, 1187500 },
> + { 1400000, 1275000, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000,
> + 1187500, 1175000, 1162500, 1150000, 1137500, 1125000, 1112500 },
> + { 1300000, 1225000, 1212500, 1200000, 1187500, 1175000, 1162500, 1150000,
> + 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500 },
> + { 1200000, 1175000, 1162500, 1150000, 1137500, 1125000, 1112500, 1100000,
> + 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500 },
> + { 1100000, 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500,
> + 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 975000 },
> + { 1000000, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000,
> + 1012500, 1000000, 987500, 975000, 962500, 950000, 937500 },
> + { 900000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, 987500,
> + 975000, 962500, 950000, 937500, 925000, 912500, 900000 },
> + { 800000, 1025000, 1012500, 1000000, 987500, 975000, 962500, 950000,
> + 937500, 925000, 912500, 900000, 900000, 900000, 900000 },
> + { 700000, 987500, 975000, 962500, 950000, 937500, 925000, 912500,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 600000, 950000, 937500, 925000, 912500, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 500000, 912500, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 400000, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 300000, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 200000, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> +}, {
> + /* KFC 2 */
> + { 1500, 1300000, 1300000, 1300000, 1287500, 1287500, 1287500, 1275000,
> + 1262500, 1250000, 1237500, 1225000, 1212500, 1200000, 1187500 },
> + { 1400, 1275000, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000,
> + 1187500, 1175000, 1162500, 1150000, 1137500, 1125000, 1112500 },
> + { 1300, 1225000, 1212500, 1200000, 1187500, 1175000, 1162500, 1150000,
> + 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500 },
> + { 1200, 1175000, 1162500, 1150000, 1137500, 1125000, 1112500, 1100000,
> + 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500 },
> + { 1100, 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500,
> + 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 975000 },
> + { 1000, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000,
> + 1012500, 1000000, 987500, 975000, 962500, 950000, 937500 },
> + { 900, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, 987500,
> + 975000, 962500, 950000, 937500, 925000, 912500, 900000 },
> + { 800, 1025000, 1012500, 1000000, 987500, 975000, 962500, 950000,
> + 937500, 925000, 912500, 900000, 900000, 900000, 900000 },
> + { 700, 987500, 975000, 962500, 950000, 937500, 925000, 912500,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 600, 950000, 937500, 925000, 912500, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 500, 912500, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 400, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 300, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 200, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> +}, {
> + /* KFC 3 */
> + { 1500, 1300000, 1300000, 1300000, 1287500, 1287500, 1287500, 1275000,
> + 1262500, 1250000, 1237500, 1225000, 1212500, 1200000, 1187500 },
> + { 1400, 1275000, 1262500, 1250000, 1237500, 1225000, 1212500, 1200000,
> + 1187500, 1175000, 1162500, 1150000, 1137500, 1125000, 1112500 },
> + { 1300, 1225000, 1212500, 1200000, 1187500, 1175000, 1162500, 1150000,
> + 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500 },
> + { 1200, 1175000, 1162500, 1150000, 1137500, 1125000, 1112500, 1100000,
> + 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500 },
> + { 1100, 1137500, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500,
> + 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 975000 },
> + { 1000, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000,
> + 1012500, 1000000, 987500, 975000, 962500, 950000, 937500 },
> + { 900, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000, 987500,
> + 975000, 962500, 950000, 937500, 925000, 912500, 900000 },
> + { 800, 1025000, 1012500, 1000000, 987500, 975000, 962500, 950000,
> + 937500, 925000, 912500, 900000, 900000, 900000, 900000 },
> + { 700, 987500, 975000, 962500, 950000, 937500, 925000, 912500,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 600, 950000, 937500, 925000, 912500, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 500, 912500, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 400, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 300, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 200, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> +}, {
> + /* KFC bin 2 */
> + { 1300, 1250000, 1237500, 1225000, 1212500, 1200000, 1187500, 1175000,
> + 1162500, 1150000, 1137500, 1125000, 1112500, 1100000, 1087500 },
> + { 1200, 1200000, 1187500, 1175000, 1162500, 1150000, 1137500, 1125000,
> + 1112500, 1100000, 1087500, 1075000, 1062500, 1050000, 1037500 },
> + { 1100, 1162500, 1150000, 1137500, 1125000, 1112500, 1100000, 1087500,
> + 1075000, 1062500, 1050000, 1037500, 1025000, 1012500, 1000000 },
> + { 1000, 1125000, 1112500, 1100000, 1087500, 1075000, 1062500, 1050000,
> + 1037500, 1025000, 1012500, 1000000, 987500, 975000, 962500 },
> + { 900, 1087500, 1075000, 1062500, 1050000, 1037500, 1025000, 1012500,
> + 1000000, 987500, 975000, 962500, 950000, 937500, 925000 },
> + { 800, 1050000, 1037500, 1025000, 1012500, 1000000, 987500, 975000,
> + 962500, 950000, 937500, 925000, 912500, 900000, 900000 },
> + { 700, 1012500, 1000000, 987500, 975000, 962500, 950000, 937500,
> + 925000, 912500, 900000, 900000, 900000, 900000, 900000 },
> + { 600, 975000, 962500, 950000, 937500, 925000, 912500, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 500, 937500, 925000, 912500, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 400, 925000, 912500, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 300, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> + { 200, 900000, 900000, 900000, 900000, 900000, 900000, 900000,
> + 900000, 900000, 900000, 900000, 900000, 900000, 900000 },
> +}
> +};
> +
> +static const struct asv_limit_entry __asv_limits[ASV_GROUPS_NUM] = {
> + { 13, 55 },
> + { 21, 65 },
> + { 25, 69 },
> + { 30, 72 },
> + { 36, 74 },
> + { 43, 76 },
> + { 51, 78 },
> + { 65, 80 },
> + { 81, 82 },
> + { 98, 84 },
> + { 119, 87 },
> + { 135, 89 },
> + { 150, 92 },
> + { 999, 999 },
> +};
> +
> +static int exynos5422_asv_get_group(struct exynos_asv *asv)
> +{
> + unsigned int pkgid_reg, auxi_reg;
> + int hpm, ids, i;
> +
> + regmap_read(asv->chipid_regmap, EXYNOS_CHIPID_REG_PKG_ID, &pkgid_reg);
> + regmap_read(asv->chipid_regmap, EXYNOS_CHIPID_REG_AUX_INFO, &auxi_reg);
> +
> + if (asv->use_sg) {
> + u32 sga = (pkgid_reg >> EXYNOS5422_SG_A_OFFSET) &
> + EXYNOS5422_SG_A_MASK;
> +
> + u32 sgb = (pkgid_reg >> EXYNOS5422_SG_B_OFFSET) &
> + EXYNOS5422_SG_B_MASK;
> +
> + if ((pkgid_reg >> EXYNOS5422_SG_BSIGN_OFFSET) &
> + EXYNOS5422_SG_BSIGN_MASK)
> + return sga + sgb;
> + else
> + return sga - sgb;
> + }
> +
> + hpm = (auxi_reg >> EXYNOS5422_TMCB_OFFSET) & EXYNOS5422_TMCB_MASK;
> + ids = (pkgid_reg >> EXYNOS5422_IDS_OFFSET) & EXYNOS5422_IDS_MASK;
> +
> + for (i = 0; i < ASV_GROUPS_NUM; i++) {
> + if (ids <= __asv_limits[i].ids)
> + break;
> + if (hpm <= __asv_limits[i].hpm)
> + break;
> + }
> + if (i < ASV_GROUPS_NUM)
> + return i;
> +
> + return 0;
> +}
> +
> +static int __asv_offset_voltage(unsigned int index)
> +{
> + switch (index) {
> + case 1:
> + return 12500;
> + case 2:
> + return 50000;
> + case 3:
> + return 25000;
> + default:
> + return 0;
> + };
> +}
> +
> +static void exynos5422_asv_offset_voltage_setup(struct exynos_asv *asv)
> +{
> + struct exynos_asv_subsys *subsys;
> + unsigned int reg, value;
> +
> + regmap_read(asv->chipid_regmap, EXYNOS_CHIPID_REG_AUX_INFO, ®);
> +
> + /* ARM offset voltage setup */
> + subsys = &asv->subsys[EXYNOS_ASV_SUBSYS_ID_ARM];
> +
> + subsys->base_volt = 1000000;
> +
> + value = (reg >> EXYNOS5422_ARM_UP_OFFSET) & EXYNOS5422_ARM_UP_MASK;
> + subsys->offset_volt_h = __asv_offset_voltage(value);
> +
> + value = (reg >> EXYNOS5422_ARM_DN_OFFSET) & EXYNOS5422_ARM_DN_MASK;
> + subsys->offset_volt_l = __asv_offset_voltage(value);
> +
> + /* KFC offset voltage setup */
> + subsys = &asv->subsys[EXYNOS_ASV_SUBSYS_ID_KFC];
> +
> + subsys->base_volt = 1000000;
> +
> + value = (reg >> EXYNOS5422_KFC_UP_OFFSET) & EXYNOS5422_KFC_UP_MASK;
> + subsys->offset_volt_h = __asv_offset_voltage(value);
> +
> + value = (reg >> EXYNOS5422_KFC_DN_OFFSET) & EXYNOS5422_KFC_DN_MASK;
> + subsys->offset_volt_l = __asv_offset_voltage(value);
> +}
> +
> +static int exynos5422_asv_opp_get_voltage(struct exynos_asv_subsys *subsys,
> + int level, unsigned int volt)
> +{
> + unsigned int asv_volt;
> +
> + if (level >= subsys->table.num_rows)
> + return volt;
> +
> + asv_volt = exynos_asv_opp_get_voltage(subsys, level,
> + subsys->asv->group);
> +
> + if (volt > subsys->base_volt)
> + asv_volt += subsys->offset_volt_h;
> + else
> + asv_volt += subsys->offset_volt_l;
> +
> + return asv_volt;
> +}
> +
> +static unsigned int exynos5422_asv_parse_table(struct exynos_asv *asv,
> + unsigned int pkg_id)
> +{
> + return (pkg_id >> EXYNOS5422_TABLE_OFFSET) & EXYNOS5422_TABLE_MASK;
> +}
> +
> +static bool exynos5422_asv_parse_bin2(struct exynos_asv *asv,
> + unsigned int pkg_id)
> +{
> + return (pkg_id >> EXYNOS5422_BIN2_OFFSET) & EXYNOS5422_BIN2_MASK;
return !!() for converting to boolean.
> +}
> +
> +static bool exynos5422_asv_parse_sg(struct exynos_asv *asv,
> + unsigned int pkg_id)
> +{
> + return ((pkg_id >> EXYNOS5422_USESG_OFFSET) & EXYNOS5422_USESG_MASK);
Unneeded () over entire statement.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH 2/2] dt-bindings: irq: Convert Allwinner NMI Controller to a schema
From: Maxime Ripard @ 2019-07-23 13:26 UTC (permalink / raw)
To: Mark Rutland, Rob Herring, Frank Rowand, tglx, jason, maz
Cc: Maxime Ripard, devicetree, Chen-Yu Tsai, linux-arm-kernel
In-Reply-To: <20190723132658.5068-1-maxime.ripard@bootlin.com>
The Allwinner SoCs have an interrupt controller called NMI supported in
Linux, with a matching Device Tree binding.
Now that we have the DT validation in place, let's convert the device tree
bindings for that controller over to a YAML schemas.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
.../allwinner,sun7i-a20-sc-nmi.yaml | 83 +++++++++++++++++++
.../allwinner,sunxi-nmi.txt | 29 -------
2 files changed, 83 insertions(+), 29 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
new file mode 100644
index 000000000000..cb8077b0c8dd
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A20 Non-Maskable Interrupt Controller Device Tree Bindings
+
+maintainers:
+ - Chen-Yu Tsai <wens@csie.org>
+ - Maxime Ripard <maxime.ripard@bootlin.com>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - allwinner,sun6i-a31-r-intc
+ - allwinner,sun7i-a20-sc-nmi
+ - allwinner,sun9i-a80-sc-nmi
+
+ # Deprecated
+ - allwinner,sun6i-a31-sc-nmi
+
+ required:
+ - compatible
+
+properties:
+ "#interrupt-cells":
+ const: 2
+ description:
+ The first cell is the IRQ number, the second cell the trigger
+ type as defined in interrupt.txt in this directory.
+
+ compatible:
+ oneOf:
+ - const: allwinner,sun6i-a31-r-intc
+ - const: allwinner,sun7i-a20-sc-nmi
+ - items:
+ - const: allwinner,sun8i-a83t-r-intc
+ - const: allwinner,sun6i-a31-r-intc
+ - const: allwinner,sun9i-a80-sc-nmi
+ - items:
+ - const: allwinner,sun50i-a64-r-intc
+ - const: allwinner,sun6i-a31-r-intc
+ - items:
+ - const: allwinner,sun50i-h6-r-intc
+ - const: allwinner,sun6i-a31-r-intc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+required:
+ - "#interrupt-cells"
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+
+# FIXME: We should set it, but it would report all the generic
+# properties as additional properties.
+# additionalProperties: false
+
+examples:
+ - |
+ interrupt-controller@1c00030 {
+ compatible = "allwinner,sun7i-a20-sc-nmi";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x01c00030 0x0c>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 0 4>;
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt
deleted file mode 100644
index 24beadf7ba83..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-Allwinner Sunxi NMI Controller
-==============================
-
-Required properties:
-
-- compatible : should be one of the following:
- - "allwinner,sun7i-a20-sc-nmi"
- - "allwinner,sun6i-a31-sc-nmi" (deprecated)
- - "allwinner,sun6i-a31-r-intc"
- - "allwinner,sun9i-a80-nmi"
-- reg : Specifies base physical address and size of the registers.
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
- interrupt source. The value shall be 2. The first cell is the IRQ number, the
- second cell the trigger type as defined in interrupt.txt in this directory.
-- interrupts: Specifies the interrupt line (NMI) which is handled by
- the interrupt controller in the parent controller's notation. This value
- shall be the NMI.
-
-Example:
-
-sc-nmi-intc@1c00030 {
- compatible = "allwinner,sun7i-a20-sc-nmi";
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x01c00030 0x0c>;
- interrupt-parent = <&gic>;
- interrupts = <0 0 4>;
-};
--
2.21.0
^ permalink raw reply related
* [PATCH 1/2] dt-bindings: irq: Convert Allwinner IRQ Controller to a schema
From: Maxime Ripard @ 2019-07-23 13:26 UTC (permalink / raw)
To: Mark Rutland, Rob Herring, Frank Rowand, tglx, jason, maz
Cc: Maxime Ripard, devicetree, Chen-Yu Tsai, linux-arm-kernel
The Allwinner SoCs have an interrupt controller supported in Linux, with a
matching Device Tree binding.
Now that we have the DT validation in place, let's convert the device tree
bindings for that controller over to a YAML schemas.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
---
.../allwinner,sun4i-a10-ic.yaml | 49 +++++++++++++++++++
.../allwinner,sun4i-ic.txt | 20 --------
2 files changed, 49 insertions(+), 20 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-a10-ic.yaml
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-a10-ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-a10-ic.yaml
new file mode 100644
index 000000000000..806cf4770f75
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-a10-ic.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun4i-a10-ic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A10 Interrupt Controller Device Tree Bindings
+
+maintainers:
+ - Chen-Yu Tsai <wens@csie.org>
+ - Maxime Ripard <maxime.ripard@bootlin.com>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ "#interrupt-cells":
+ const: 1
+
+ compatible:
+ enum:
+ - allwinner,sun4i-a10-ic
+ - allwinner,suniv-f1c100s-ic
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+required:
+ - "#interrupt-cells"
+ - compatible
+ - reg
+ - interrupt-controller
+
+# FIXME: We should set it, but it would report all the generic
+# properties as additional properties.
+# additionalProperties: false
+
+examples:
+ - |
+ intc: interrupt-controller {
+ compatible = "allwinner,sun4i-a10-ic";
+ reg = <0x01c20400 0x400>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
deleted file mode 100644
index 404352524c3a..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Allwinner Sunxi Interrupt Controller
-
-Required properties:
-
-- compatible : should be one of the following:
- "allwinner,sun4i-a10-ic"
- "allwinner,suniv-f1c100s-ic"
-- reg : Specifies base physical address and size of the registers.
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
- interrupt source. The value shall be 1.
-
-Example:
-
-intc: interrupt-controller {
- compatible = "allwinner,sun4i-a10-ic";
- reg = <0x01c20400 0x400>;
- interrupt-controller;
- #interrupt-cells = <1>;
-};
--
2.21.0
^ permalink raw reply related
* Re: [PATCH v2 2/9] soc: samsung: Convert exynos-chipid driver to use the regmap API
From: Krzysztof Kozlowski @ 2019-07-23 13:01 UTC (permalink / raw)
To: Sylwester Nawrocki
Cc: robh+dt, vireshk, devicetree, kgene, pankaj.dubey,
linux-samsung-soc@vger.kernel.org, linux-arm-kernel, linux-kernel,
linux-pm, Bartłomiej Żołnierkiewicz,
Marek Szyprowski
In-Reply-To: <20190718143044.25066-3-s.nawrocki@samsung.com>
On Thu, 18 Jul 2019 at 16:31, Sylwester Nawrocki <s.nawrocki@samsung.com> wrote:
>
> Convert the driver to use regmap API in order to allow other
> drivers, like ASV, to access the CHIPID registers.
>
> This patch adds definition of selected CHIPID register offsets
> and register bit fields for Exynos5422 SoC.
>
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> ---
> Changes since v1 (RFC):
> - new patch
> ---
> drivers/soc/samsung/exynos-chipid.c | 33 ++++++----------
> include/linux/soc/samsung/exynos-chipid.h | 48 +++++++++++++++++++++++
> 2 files changed, 61 insertions(+), 20 deletions(-)
> create mode 100644 include/linux/soc/samsung/exynos-chipid.h
>
> diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c
> index 78b123ee60c0..594b00488013 100644
> --- a/drivers/soc/samsung/exynos-chipid.c
> +++ b/drivers/soc/samsung/exynos-chipid.c
> @@ -9,18 +9,16 @@
> */
>
> #include <linux/io.h>
> +#include <linux/mfd/syscon.h>
> #include <linux/of.h>
> #include <linux/of_address.h>
> #include <linux/of_platform.h>
> #include <linux/platform_device.h>
> +#include <linux/regmap.h>
> #include <linux/slab.h>
> +#include <linux/soc/samsung/exynos-chipid.h>
> #include <linux/sys_soc.h>
>
> -#define EXYNOS_SUBREV_MASK (0xF << 4)
> -#define EXYNOS_MAINREV_MASK (0xF << 0)
> -#define EXYNOS_REV_MASK (EXYNOS_SUBREV_MASK | EXYNOS_MAINREV_MASK)
> -#define EXYNOS_MASK 0xFFFFF000
> -
> static const struct exynos_soc_id {
> const char *name;
> unsigned int id;
> @@ -53,29 +51,24 @@ static const char * __init product_id_to_soc_id(unsigned int product_id)
> int __init exynos_chipid_early_init(void)
> {
> struct soc_device_attribute *soc_dev_attr;
> - void __iomem *exynos_chipid_base;
> struct soc_device *soc_dev;
> struct device_node *root;
> - struct device_node *np;
> + struct regmap *regmap;
> u32 product_id;
> u32 revision;
> + int ret;
>
> - /* look up for chipid node */
> - np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
> - if (!np)
> - return -ENODEV;
> -
> - exynos_chipid_base = of_iomap(np, 0);
> - of_node_put(np);
> -
> - if (!exynos_chipid_base) {
> - pr_err("Failed to map SoC chipid\n");
> - return -ENXIO;
> + regmap = syscon_regmap_lookup_by_compatible("samsung,exynos4210-chipid");
> + if (IS_ERR(regmap)) {
> + pr_err("%s: failed to get regmap\n", __func__);
Other places do not use __func__ prefix so make it consistent. Add it
in patch #1?
> + return PTR_ERR(regmap);
> }
>
> - product_id = readl_relaxed(exynos_chipid_base);
> + ret = regmap_read(regmap, EXYNOS_CHIPID_REG_PRO_ID, &product_id);
> + if (ret < 0)
> + return ret;
> +
> revision = product_id & EXYNOS_REV_MASK;
> - iounmap(exynos_chipid_base);
>
> soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
> if (!soc_dev_attr)
> diff --git a/include/linux/soc/samsung/exynos-chipid.h b/include/linux/soc/samsung/exynos-chipid.h
> new file mode 100644
> index 000000000000..25359d70d617
> --- /dev/null
> +++ b/include/linux/soc/samsung/exynos-chipid.h
> @@ -0,0 +1,48 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2018 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com/
> + *
> + * Exynos - CHIPID support
> + */
> +
> +#define EXYNOS_CHIPID_REG_PRO_ID 0x00
> + #define EXYNOS_SUBREV_MASK (0xf << 4)
" #define" is unusual syntax. I think not used anywhere else. Stick to
regular one.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v2 1/9] soc: samsung: Add exynos chipid driver support
From: Krzysztof Kozlowski @ 2019-07-23 12:57 UTC (permalink / raw)
To: Sylwester Nawrocki
Cc: robh+dt, vireshk, devicetree, kgene, pankaj.dubey,
linux-samsung-soc@vger.kernel.org, linux-arm-kernel, linux-kernel,
linux-pm, Bartłomiej Żołnierkiewicz,
Marek Szyprowski
In-Reply-To: <20190718143044.25066-2-s.nawrocki@samsung.com>
On Thu, 18 Jul 2019 at 16:31, Sylwester Nawrocki <s.nawrocki@samsung.com> wrote:
>
> From: Pankaj Dubey <pankaj.dubey@samsung.com>
>
> Exynos SoCs have Chipid, for identification of product IDs and SoC
> revisions. This patch intends to provide initialization code for all
> these functionalities, at the same time it provides some sysfs entries
> for accessing these information to user-space.
>
> This driver uses existing binding for exynos-chipid.
>
> Changes by Bartlomiej:
> - fixed return values on errors
> - removed bogus kfree_const()
> - added missing Exynos4210 EVT0 id
> - converted code to use EXYNOS_MASK define
> - fixed np use after of_node_put()
> - fixed too early use of dev_info()
> - made driver fail for unknown SoC-s
> - added SPDX tag
> - updated Copyrights
>
> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
> [m.szyprowski: for suggestion and code snippet of product_id_to_soc_id]
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> [s.nawrocki: updated copyright date]
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> ---
> drivers/soc/samsung/Kconfig | 5 ++
> drivers/soc/samsung/Makefile | 2 +
> drivers/soc/samsung/exynos-chipid.c | 111 ++++++++++++++++++++++++++++
> 3 files changed, 118 insertions(+)
> create mode 100644 drivers/soc/samsung/exynos-chipid.c
>
> diff --git a/drivers/soc/samsung/Kconfig b/drivers/soc/samsung/Kconfig
> index 2186285fda92..2905f5262197 100644
> --- a/drivers/soc/samsung/Kconfig
> +++ b/drivers/soc/samsung/Kconfig
> @@ -7,6 +7,11 @@ menuconfig SOC_SAMSUNG
>
> if SOC_SAMSUNG
>
> +config EXYNOS_CHIPID
> + bool "Exynos Chipid controller driver" if COMPILE_TEST
> + depends on ARCH_EXYNOS || COMPILE_TEST
> + select SOC_BUS
> +
> config EXYNOS_PMU
> bool "Exynos PMU controller driver" if COMPILE_TEST
> depends on ARCH_EXYNOS || ((ARM || ARM64) && COMPILE_TEST)
> diff --git a/drivers/soc/samsung/Makefile b/drivers/soc/samsung/Makefile
> index 29f294baac6e..3b6a8797416c 100644
> --- a/drivers/soc/samsung/Makefile
> +++ b/drivers/soc/samsung/Makefile
> @@ -1,4 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> +
> +obj-$(CONFIG_EXYNOS_CHIPID) += exynos-chipid.o
> obj-$(CONFIG_EXYNOS_PMU) += exynos-pmu.o
>
> obj-$(CONFIG_EXYNOS_PMU_ARM_DRIVERS) += exynos3250-pmu.o exynos4-pmu.o \
> diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c
> new file mode 100644
> index 000000000000..78b123ee60c0
> --- /dev/null
> +++ b/drivers/soc/samsung/exynos-chipid.c
> @@ -0,0 +1,111 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2019 Samsung Electronics Co., Ltd.
> + * http://www.samsung.com/
> + *
> + * EXYNOS - CHIP ID support
> + * Author: Pankaj Dubey <pankaj.dubey@samsung.com>
> + * Author: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> + */
> +
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
Any changes here from my previous comments?
I have also one more new thought later.
> +#include <linux/slab.h>
> +#include <linux/sys_soc.h>
> +
> +#define EXYNOS_SUBREV_MASK (0xF << 4)
> +#define EXYNOS_MAINREV_MASK (0xF << 0)
> +#define EXYNOS_REV_MASK (EXYNOS_SUBREV_MASK | EXYNOS_MAINREV_MASK)
> +#define EXYNOS_MASK 0xFFFFF000
> +
> +static const struct exynos_soc_id {
> + const char *name;
> + unsigned int id;
> +} soc_ids[] = {
> + { "EXYNOS3250", 0xE3472000 },
> + { "EXYNOS4210", 0x43200000 }, /* EVT0 revision */
> + { "EXYNOS4210", 0x43210000 },
> + { "EXYNOS4212", 0x43220000 },
> + { "EXYNOS4412", 0xE4412000 },
> + { "EXYNOS5250", 0x43520000 },
> + { "EXYNOS5260", 0xE5260000 },
> + { "EXYNOS5410", 0xE5410000 },
> + { "EXYNOS5420", 0xE5420000 },
> + { "EXYNOS5440", 0xE5440000 },
> + { "EXYNOS5800", 0xE5422000 },
> + { "EXYNOS7420", 0xE7420000 },
> + { "EXYNOS5433", 0xE5433000 },
> +};
> +
> +static const char * __init product_id_to_soc_id(unsigned int product_id)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(soc_ids); i++)
> + if ((product_id & EXYNOS_MASK) == soc_ids[i].id)
> + return soc_ids[i].name;
> + return NULL;
> +}
> +
> +int __init exynos_chipid_early_init(void)
> +{
> + struct soc_device_attribute *soc_dev_attr;
> + void __iomem *exynos_chipid_base;
> + struct soc_device *soc_dev;
> + struct device_node *root;
> + struct device_node *np;
> + u32 product_id;
> + u32 revision;
> +
> + /* look up for chipid node */
> + np = of_find_compatible_node(NULL, NULL, "samsung,exynos4210-chipid");
> + if (!np)
> + return -ENODEV;
> +
> + exynos_chipid_base = of_iomap(np, 0);
> + of_node_put(np);
> +
> + if (!exynos_chipid_base) {
> + pr_err("Failed to map SoC chipid\n");
> + return -ENXIO;
> + }
> +
> + product_id = readl_relaxed(exynos_chipid_base);
> + revision = product_id & EXYNOS_REV_MASK;
> + iounmap(exynos_chipid_base);
> +
> + soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
> + if (!soc_dev_attr)
> + return -ENOMEM;
> +
> + soc_dev_attr->family = "Samsung Exynos";
> +
> + root = of_find_node_by_path("/");
> + of_property_read_string(root, "model", &soc_dev_attr->machine);
> + of_node_put(root);
> +
> + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%x", revision);
> + soc_dev_attr->soc_id = product_id_to_soc_id(product_id);
> + if (!soc_dev_attr->soc_id) {
> + pr_err("Unknown SoC\n");
In case of running old kernel on unknown SoC (new revision of existing
one or older design not longer supported like 4415), the device will
not bind. This was added by Bartlomiej. Why? I imagine that soc driver
could be still matched and just report "Unknown". I am not sure if
this changes anything, though.
Best regards,
Krzysztof
> + return -ENODEV;
> + }
> +
> + /* please note that the actual registration will be deferred */
> + soc_dev = soc_device_register(soc_dev_attr);
> + if (IS_ERR(soc_dev)) {
> + kfree(soc_dev_attr->revision);
> + kfree(soc_dev_attr);
> + return PTR_ERR(soc_dev);
> + }
> +
> + /* it is too early to use dev_info() here (soc_dev is NULL) */
> + pr_info("soc soc0: Exynos: CPU[%s] PRO_ID[0x%x] REV[0x%x] Detected\n",
> + soc_dev_attr->soc_id, product_id, revision);
> +
> + return 0;
> +}
> +early_initcall(exynos_chipid_early_init);
> --
> 2.17.1
>
^ permalink raw reply
* [RFC PATCH 11/11] drm: exynos: mixer: Add interconnect support
From: Artur Świgoń @ 2019-07-23 12:20 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel,
linux-pm, dri-devel
Cc: krzk, cw00.choi, myungjoo.ham, inki.dae, sw0312.kim,
georgi.djakov, m.szyprowski
In-Reply-To: <20190723122016.30279-1-a.swigon@partner.samsung.com>
From: Marek Szyprowski <m.szyprowski@samsung.com>
This patch adds interconnect support to exynos-mixer. Please note that the
mixer works the same as before when CONFIG_INTERCONNECT is 'n'.
Co-developed-by: Artur Świgoń <a.swigon@partner.samsung.com>
Signed-off-by: Artur Świgoń <a.swigon@partner.samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
drivers/gpu/drm/exynos/exynos_mixer.c | 68 +++++++++++++++++++++++++--
1 file changed, 63 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index 7b24338fad3c..fb763854b300 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -13,6 +13,7 @@
#include <linux/component.h>
#include <linux/delay.h>
#include <linux/i2c.h>
+#include <linux/interconnect.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/kernel.h>
@@ -97,6 +98,7 @@ struct mixer_context {
struct exynos_drm_crtc *crtc;
struct exynos_drm_plane planes[MIXER_WIN_NR];
unsigned long flags;
+ struct icc_path *soc_path;
int irq;
void __iomem *mixer_regs;
@@ -931,6 +933,37 @@ static void mixer_disable_vblank(struct exynos_drm_crtc *crtc)
mixer_reg_writemask(mixer_ctx, MXR_INT_EN, 0, MXR_INT_EN_VSYNC);
}
+static void mixer_set_memory_bandwidth(struct exynos_drm_crtc *crtc)
+{
+ struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
+ struct mixer_context *ctx = crtc->ctx;
+ unsigned long bw, bandwidth = 0;
+ int i, j, sub;
+
+ for (i = 0; i < MIXER_WIN_NR; i++) {
+ struct drm_plane *plane = &ctx->planes[i].base;
+ const struct drm_format_info *format;
+
+ if (plane->state && plane->state->crtc && plane->state->fb) {
+ format = plane->state->fb->format;
+ bw = mode->hdisplay * mode->vdisplay *
+ drm_mode_vrefresh(mode);
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+ bw /= 2;
+ for (j = 0; j < format->num_planes; j++) {
+ sub = j ? (format->vsub * format->hsub) : 1;
+ bandwidth += format->cpp[j] * bw / sub;
+ }
+ }
+ }
+
+ /* add 20% safety margin */
+ bandwidth = 5UL * bandwidth / 4;
+
+ pr_info("exynos-mixer: safe bandwidth %ld Bps\n", bandwidth);
+ icc_set_bw(ctx->soc_path, 0, Bps_to_icc(bandwidth));
+}
+
static void mixer_atomic_begin(struct exynos_drm_crtc *crtc)
{
struct mixer_context *ctx = crtc->ctx;
@@ -982,6 +1015,7 @@ static void mixer_atomic_flush(struct exynos_drm_crtc *crtc)
if (!test_bit(MXR_BIT_POWERED, &mixer_ctx->flags))
return;
+ mixer_set_memory_bandwidth(crtc);
mixer_enable_sync(mixer_ctx);
exynos_crtc_handle_event(crtc);
}
@@ -1029,6 +1063,7 @@ static void mixer_disable(struct exynos_drm_crtc *crtc)
for (i = 0; i < MIXER_WIN_NR; i++)
mixer_disable_plane(crtc, &ctx->planes[i]);
+ mixer_set_memory_bandwidth(crtc);
exynos_drm_pipe_clk_enable(crtc, false);
pm_runtime_put(ctx->dev);
@@ -1220,12 +1255,22 @@ static int mixer_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
const struct mixer_drv_data *drv;
struct mixer_context *ctx;
+ struct icc_path *path;
int ret;
+ /*
+ * Returns NULL if CONFIG_INTERCONNECT is disabled.
+ * May return ERR_PTR(-EPROBE_DEFER).
+ */
+ path = of_icc_get(dev, NULL);
+ if (IS_ERR(path))
+ return PTR_ERR(path);
+
ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
if (!ctx) {
DRM_DEV_ERROR(dev, "failed to alloc mixer context.\n");
- return -ENOMEM;
+ ret = -ENOMEM;
+ goto err;
}
drv = of_device_get_match_data(dev);
@@ -1233,6 +1278,7 @@ static int mixer_probe(struct platform_device *pdev)
ctx->pdev = pdev;
ctx->dev = dev;
ctx->mxr_ver = drv->version;
+ ctx->soc_path = path;
if (drv->is_vp_enabled)
__set_bit(MXR_BIT_VP_ENABLED, &ctx->flags);
@@ -1242,17 +1288,29 @@ static int mixer_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, ctx);
ret = component_add(&pdev->dev, &mixer_component_ops);
- if (!ret)
- pm_runtime_enable(dev);
+ if (ret < 0)
+ goto err;
+
+ pm_runtime_enable(dev);
+
+ return 0;
+
+err:
+ icc_put(path);
return ret;
}
static int mixer_remove(struct platform_device *pdev)
{
- pm_runtime_disable(&pdev->dev);
+ struct device *dev = &pdev->dev;
+ struct mixer_context *ctx = dev_get_drvdata(dev);
- component_del(&pdev->dev, &mixer_component_ops);
+ pm_runtime_disable(dev);
+
+ component_del(dev, &mixer_component_ops);
+
+ icc_put(ctx->soc_path);
return 0;
}
--
2.17.1
^ permalink raw reply related
* [RFC PATCH 10/11] arm: dts: exynos: Add interconnects to Exynos4412 mixer
From: Artur Świgoń @ 2019-07-23 12:20 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel,
linux-pm, dri-devel
Cc: krzk, cw00.choi, myungjoo.ham, inki.dae, sw0312.kim,
georgi.djakov, m.szyprowski
In-Reply-To: <20190723122016.30279-1-a.swigon@partner.samsung.com>
This patch adds an 'interconnects' property to Exynos4412 DTS in order to
declare the interconnect path used by the mixer. Please note that the
'interconnect-names' property is not needed when there is only one path in
'interconnects', in which case calling of_icc_get() with a NULL name simply
returns the right path.
Signed-off-by: Artur Świgoń <a.swigon@partner.samsung.com>
---
arch/arm/boot/dts/exynos4412.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index a70a671acacd..faaec6c40412 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -789,6 +789,7 @@
clock-names = "mixer", "hdmi", "sclk_hdmi", "vp";
clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
<&clock CLK_SCLK_HDMI>, <&clock CLK_VP>;
+ interconnects = <&bus_display &bus_dmc>;
};
&pmu {
--
2.17.1
^ permalink raw reply related
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