* RE: [PATCH net-next 1/3] enetc: Add mdio bus driver for the PCIe MDIO endpoint
From: Claudiu Manoil @ 2019-07-24 12:57 UTC (permalink / raw)
To: Claudiu Manoil, Andrew Lunn
Cc: devicetree@vger.kernel.org, netdev@vger.kernel.org,
Alexandru Marginean, linux-kernel@vger.kernel.org, Leo Li,
Rob Herring, David S . Miller,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <VI1PR04MB4880DAE881769F6DC845CEEF96C60@VI1PR04MB4880.eurprd04.prod.outlook.com>
>-----Original Message-----
>From: netdev-owner@vger.kernel.org <netdev-owner@vger.kernel.org> On
>Behalf Of Claudiu Manoil
>Sent: Wednesday, July 24, 2019 12:53 PM
>To: Andrew Lunn <andrew@lunn.ch>
>Cc: David S . Miller <davem@davemloft.net>; devicetree@vger.kernel.org;
>netdev@vger.kernel.org; Alexandru Marginean
><alexandru.marginean@nxp.com>; linux-kernel@vger.kernel.org; Leo Li
><leoyang.li@nxp.com>; Rob Herring <robh+dt@kernel.org>; linux-arm-
>kernel@lists.infradead.org
>Subject: RE: [PATCH net-next 1/3] enetc: Add mdio bus driver for the PCIe MDIO
>endpoint
>
>>-----Original Message-----
>>From: Andrew Lunn <andrew@lunn.ch>
>>Sent: Wednesday, July 24, 2019 1:25 AM
>>To: Claudiu Manoil <claudiu.manoil@nxp.com>
>>Cc: David S . Miller <davem@davemloft.net>; devicetree@vger.kernel.org;
>>netdev@vger.kernel.org; Alexandru Marginean
>><alexandru.marginean@nxp.com>; linux-kernel@vger.kernel.org; Leo Li
>><leoyang.li@nxp.com>; Rob Herring <robh+dt@kernel.org>; linux-arm-
>>kernel@lists.infradead.org
>>Subject: Re: [PATCH net-next 1/3] enetc: Add mdio bus driver for the
>>PCIe MDIO endpoint
>>
>>> + bus = mdiobus_alloc_size(sizeof(u32 *));
>>> + if (!bus)
>>> + return -ENOMEM;
>>> +
>>
>>> + bus->priv = pci_iomap_range(pdev, 0, ENETC_MDIO_REG_OFFSET, 0);
>>
>>This got me confused for a while. You allocate space for a u32 pointer.
>>bus->priv will point to this space. However, you are not using this
>>space, you {ab}use the pointer to directly hold the return from
>>pci_iomap_range(). This works, but sparse is probably unhappy, and you
>>are wasting the space the u32 pointer takes.
>>
>
>Thanks Andrew,
>This is not what I wanted to do, don't ask me how I got to this, it's confusing
>indeed.
>What's needed here is mdiobus_alloc() or better, devm_mdiobus_alloc().
>I've got to do some cleanup in the local mdio bus probing too.
>Will send v2.
>
This is tricky actually, mdiobus_alloc won't do it, I still need to allocate space
for the pointer.
So it's not ok to store the register space pointer directly into priv
(even if iomap returns void *), it's unusual.
Looks like I will have to use double pointers!
^ permalink raw reply
* Re: [PATCH v6 0/5] media: Allwinner A10 CSI support
From: Maxime Ripard @ 2019-07-24 12:39 UTC (permalink / raw)
To: Sakari Ailus
Cc: Hans Verkuil, Thomas Petazzoni, Laurent Pinchart, linux-media,
Chen-Yu Tsai, linux-kernel, linux-arm-kernel, devicetree,
Mark Rutland, Rob Herring, Frank Rowand, Mauro Carvalho Chehab
In-Reply-To: <cover.34bcd988943a26671681eaf849aacab51fab1cfe.1562847292.git-series.maxime.ripard@bootlin.com>
[-- Attachment #1: Type: text/plain, Size: 7167 bytes --]
Hi,
On Thu, Jul 11, 2019 at 02:15:02PM +0200, Maxime Ripard wrote:
> Hi,
>
> Here is a series introducing the support for the A10 (and SoCs of the same
> generation) CMOS Sensor Interface (called CSI, not to be confused with
> MIPI-CSI, which isn't support by that IP).
>
> That interface is pretty straightforward, but the driver has a few issues
> that I wanted to bring up:
>
> * The only board I've been testing this with has an ov5640 sensor
> attached, which doesn't work with the upstream driver. Copying the
> Allwinner init sequence works though, and this is how it has been
> tested. Testing with a second sensor would allow to see if it's an
> issue on the CSI side or the sensor side.
> * We don't have support for the ISP at the moment, but this can be added
> eventually.
>
> Here is the v4l2-compliance output (commit f61132e81d79 of v4l-utils), and
> after running media-ctl -d /dev/media1 -v --set-v4l2 "'ov5640 1-0021':0
> [fmt:YUYV8_2X8/640x4 80 field:none]"
>
> Compliance test for device /dev/video1:
>
> Driver Info:
> Driver name : sun4i_csi
> Card type : sun4i-csi
> Bus info : platform:1c09000.csi
> Driver version : 5.2.0
> Capabilities : 0x84201000
> Video Capture Multiplanar
> Streaming
> Extended Pix Format
> Device Capabilities
> Device Caps : 0x04201000
> Video Capture Multiplanar
> Streaming
> Extended Pix Format
> Media Driver Info:
> Driver name : sun4i-csi
> Model : Allwinner Video Capture Device
> Serial :
> Bus info :
> Media version : 5.2.0
> Hardware revision: 0x00000000 (0)
> Driver version : 5.2.0
> Interface Info:
> ID : 0x03000008
> Type : V4L Video
> Entity Info:
> ID : 0x00000006 (6)
> Name : sun4i_csi
> Function : V4L2 I/O
> Pad 0x01000007 : 0: Sink, Must Connect
> Link 0x0200000a: from remote pad 0x1000005 of entity 'sun4i-csi-0': Data, Enabled, Immutable
>
> Required ioctls:
> test MC information (see 'Media Driver Info' above): OK
> test VIDIOC_QUERYCAP: OK
>
> Allow for multiple opens:
> test second /dev/video1 open: OK
> test VIDIOC_QUERYCAP: OK
> test VIDIOC_G/S_PRIORITY: OK
> test for unlimited opens: OK
>
> Debug ioctls:
> test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
> test VIDIOC_LOG_STATUS: OK (Not Supported)
>
> Input ioctls:
> test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
> test VIDIOC_ENUMAUDIO: OK (Not Supported)
> test VIDIOC_G/S/ENUMINPUT: OK
> test VIDIOC_G/S_AUDIO: OK (Not Supported)
> Inputs: 1 Audio Inputs: 0 Tuners: 0
>
> Output ioctls:
> test VIDIOC_G/S_MODULATOR: OK (Not Supported)
> test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
> test VIDIOC_ENUMAUDOUT: OK (Not Supported)
> test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
> test VIDIOC_G/S_AUDOUT: OK (Not Supported)
> Outputs: 0 Audio Outputs: 0 Modulators: 0
>
> Input/Output configuration ioctls:
> test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
> test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
> test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
> test VIDIOC_G/S_EDID: OK (Not Supported)
>
> Control ioctls (Input 0):
> test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK (Not Supported)
> test VIDIOC_QUERYCTRL: OK (Not Supported)
> test VIDIOC_G/S_CTRL: OK (Not Supported)
> test VIDIOC_G/S/TRY_EXT_CTRLS: OK (Not Supported)
> test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK (Not Supported)
> test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
> Standard Controls: 0 Private Controls: 0
>
> Format ioctls (Input 0):
> test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
> test VIDIOC_G/S_PARM: OK (Not Supported)
> test VIDIOC_G_FBUF: OK (Not Supported)
> test VIDIOC_G_FMT: OK
> test VIDIOC_TRY_FMT: OK
> test VIDIOC_S_FMT: OK
> test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
> test Cropping: OK (Not Supported)
> test Composing: OK (Not Supported)
> test Scaling: OK
>
> Codec ioctls (Input 0):
> test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
> test VIDIOC_G_ENC_INDEX: OK (Not Supported)
> test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
>
> Buffer ioctls (Input 0):
> test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
> test VIDIOC_EXPBUF: OK
>
> Test input 0:
>
> Streaming ioctls:
> test read/write: OK (Not Supported)
> test blocking wait: OK
> test MMAP: OK
> test USERPTR: OK (Not Supported)
> test DMABUF: OK (Not Supported)
>
> Total: 49, Succeeded: 49, Failed: 0, Warnings: 0
As requested by Sakari, here is the media-ctl -p output, both at boot,
and after the link setup.
# media-ctl -p -d /dev/media1
Media controller API version 5.2.0
Media device information
------------------------
driver sun4i-csi
model Allwinner Video Capture Device
serial
bus info
hw revision 0x0
driver version 5.2.0
Device topology
- entity 1: ov5640 1-0021 (1 pad, 1 link)
type V4L2 subdev subtype Sensor flags 0
device node name /dev/v4l-subdev0
pad0: Source
[fmt:UYVY8_2X8/640x480@1/30 field:none colorspace:srgb xfer:srgb ycbcr:601 quantization:full-range]
-> "sun4i-csi-0":0 [ENABLED,IMMUTABLE]
- entity 3: sun4i-csi-0 (2 pads, 2 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev1
pad0: Sink
<- "ov5640 1-0021":0 [ENABLED,IMMUTABLE]
pad1: Source
[fmt:unknown/0x0]
-> "sun4i_csi":0 [ENABLED,IMMUTABLE]
- entity 6: sun4i_csi (1 pad, 1 link)
type Node subtype V4L flags 0
device node name /dev/video1
pad0: Sink
<- "sun4i-csi-0":1 [ENABLED,IMMUTABLE]
# media-ctl -d /dev/media1 -v --set-v4l2 "'ov5640 1-0021':0 [fmt:YUYV8_2X8/640x4
80 field:none]"
Opening media device /dev/media1
Enumerating entities
Found 3 entities
Enumerating pads and links
Setting up format YUYV8_2X8 640x480 on pad ov5640 1-0021/0
Format set: YUYV8_2X8 640x480
Setting up format YUYV8_2X8 640x480 on pad sun4i-csi-0/0
Format set: YUYV8_2X8 640x480
# media-ctl -p -d /dev/media1
Media controller API version 5.2.0
Media device information
------------------------
driver sun4i-csi
model Allwinner Video Capture Device
serial
bus info
hw revision 0x0
driver version 5.2.0
Device topology
- entity 1: ov5640 1-0021 (1 pad, 1 link)
type V4L2 subdev subtype Sensor flags 0
device node name /dev/v4l-subdev0
pad0: Source
[fmt:YUYV8_2X8/640x480@1/30 field:none colorspace:srgb xfer:srgb ycbcr:601 quantization:full-range]
-> "sun4i-csi-0":0 [ENABLED,IMMUTABLE]
- entity 3: sun4i-csi-0 (2 pads, 2 links)
type V4L2 subdev subtype Unknown flags 0
device node name /dev/v4l-subdev1
pad0: Sink
<- "ov5640 1-0021":0 [ENABLED,IMMUTABLE]
pad1: Source
[fmt:YUYV8_2X8/640x480]
-> "sun4i_csi":0 [ENABLED,IMMUTABLE]
- entity 6: sun4i_csi (1 pad, 1 link)
type Node subtype V4L flags 0
device node name /dev/video1
pad0: Sink
<- "sun4i-csi-0":1 [ENABLED,IMMUTABLE]
--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply
* [RFCv3 3/3] PM / devfreq: Add imx perf event support
From: Leonard Crestez @ 2019-07-24 12:38 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Will Deacon, Stephen Boyd
Cc: Michael Turquette, Jacky Bai, Anson Huang, Abel Vesa,
Dong Aisheng, Viresh Kumar, Georgi Djakov, Alexandre Bailon,
Chanwoo Choi, Mark Rutland, Frank Li, Rob Herring, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, linux-pm, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <cover.1563971855.git.leonard.crestez@nxp.com>
The imx8m ddrc has a performance monitoring block attached which can be
used to measure bandwidth usage automatically adjust frequency.
There is already a perf driver for that block so instead of implementing
a devfreq events driver use the in-kernel perf API to fetch read/write
bandwidth values and sum them.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
---
drivers/devfreq/imx-devfreq.c | 135 ++++++++++++++++++++++++++++++++++
1 file changed, 135 insertions(+)
diff --git a/drivers/devfreq/imx-devfreq.c b/drivers/devfreq/imx-devfreq.c
index 3ee2d37883c6..fd4c8ffb8b4a 100644
--- a/drivers/devfreq/imx-devfreq.c
+++ b/drivers/devfreq/imx-devfreq.c
@@ -11,14 +11,28 @@
#include <linux/of_device.h>
#include <linux/pm_opp.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
+#include <asm/perf_event.h>
+#include <linux/perf_event.h>
+
struct imx_devfreq {
struct devfreq_dev_profile profile;
struct devfreq *devfreq;
struct clk *clk;
+
+ struct platform_device* pmu_pdev;
+ struct pmu *pmu;
+
+ struct perf_event_attr rd_event_attr;
+ struct perf_event_attr wr_event_attr;
+ struct perf_event *rd_event;
+ struct perf_event *wr_event;
+
+ u64 last_rd_val, last_rd_ena, last_rd_run;
+ u64 last_wr_val, last_wr_ena, last_wr_run;
};
static int imx_devfreq_target(struct device *dev, unsigned long *freq, u32 flags)
{
struct imx_devfreq *priv = dev_get_drvdata(dev);
@@ -64,22 +78,131 @@ static int imx_devfreq_get_dev_status(struct device *dev,
stat->busy_time = 0;
stat->total_time = 0;
stat->current_frequency = clk_get_rate(priv->clk);
+ if (priv->rd_event && priv->wr_event) {
+ u64 rd_delta, rd_val, rd_ena, rd_run;
+ u64 wr_delta, wr_val, wr_ena, wr_run;
+
+ rd_val = perf_event_read_value(priv->rd_event, &rd_ena, &rd_run);
+ wr_val = perf_event_read_value(priv->wr_event, &wr_ena, &wr_run);
+
+ rd_delta = (rd_val - priv->last_rd_val) * (rd_ena - priv->last_rd_ena) / (rd_run - priv->last_rd_run);
+ priv->last_rd_val = rd_val;
+ priv->last_rd_ena = rd_ena;
+ priv->last_rd_run = rd_run;
+ wr_delta = (wr_val - priv->last_wr_val) * (wr_ena - priv->last_wr_ena) / (wr_run - priv->last_wr_run);
+ priv->last_wr_val = wr_val;
+ priv->last_wr_ena = wr_ena;
+ priv->last_wr_run = wr_run;
+
+ /* magic numbers, possibly wrong */
+ stat->busy_time = 4 * (rd_delta + wr_delta);
+ stat->total_time = stat->current_frequency;
+
+ dev_dbg(dev, "perf load %02lu%% read=%lu write=%lu freq=%lu\n",
+ 100 * stat->busy_time / stat->total_time,
+ rd_delta, wr_delta, stat->current_frequency);
+ }
+
+ return 0;
+}
+
+static int imx_devfreq_perf_disable(struct imx_devfreq *priv)
+{
+ /* release and set to NULL */
+ if (!IS_ERR_OR_NULL(priv->rd_event))
+ perf_event_release_kernel(priv->rd_event);
+ if (!IS_ERR_OR_NULL(priv->wr_event))
+ perf_event_release_kernel(priv->wr_event);
+ priv->rd_event = NULL;
+ priv->wr_event = NULL;
+
+ return 0;
+}
+
+static int imx_devfreq_perf_enable(struct imx_devfreq *priv)
+{
+ int ret;
+
+ priv->rd_event_attr.size = sizeof(priv->rd_event_attr);
+ priv->rd_event_attr.type = priv->pmu->type;
+ priv->rd_event_attr.config = 0x2a;
+
+ priv->rd_event = perf_event_create_kernel_counter(
+ &priv->rd_event_attr, 0, NULL, NULL, NULL);
+ if (IS_ERR(priv->rd_event)) {
+ ret = PTR_ERR(priv->rd_event);
+ goto err;
+ }
+
+ priv->wr_event_attr.size = sizeof(priv->wr_event_attr);
+ priv->wr_event_attr.type = priv->pmu->type;
+ priv->wr_event_attr.config = 0x2b;
+
+ priv->wr_event = perf_event_create_kernel_counter(
+ &priv->wr_event_attr, 0, NULL, NULL, NULL);
+ if (IS_ERR(priv->wr_event)) {
+ ret = PTR_ERR(priv->wr_event);
+ goto err;
+ }
+
return 0;
+
+err:
+ imx_devfreq_perf_disable(priv);
+ return ret;
+}
+
+static int imx_devfreq_init_events(struct device *dev,
+ struct device_node* events_node)
+{
+ struct imx_devfreq *priv = dev_get_drvdata(dev);
+ struct device_driver *driver;
+
+ /*
+ * We need pmu->type for perf_event_attr but there is no API for
+ * mapping device_node to pmu. Fetch private data for imx-ddr-pmu and
+ * cast that to a struct pmu instead.
+ */
+ priv->pmu_pdev = of_find_device_by_node(events_node);
+ if (!priv->pmu_pdev)
+ return -ENOENT;
+ driver = priv->pmu_pdev->dev.driver;
+ if (!driver)
+ return -ENOENT;
+ if (strcmp(driver->name, "imx-ddr-pmu")) {
+ dev_warn(dev, "devfreq-events node %pOF has unexpected driver %s\n",
+ events_node, driver->name);
+ return -ENODEV;
+ }
+
+ priv->pmu = platform_get_drvdata(priv->pmu_pdev);
+ if (!priv->pmu)
+ return -EPROBE_DEFER;
+
+ dev_info(dev, "events from pmu %s\n", priv->pmu->name);
+
+ return imx_devfreq_perf_enable(priv);
}
static void imx_devfreq_exit(struct device *dev)
{
+ struct imx_devfreq *priv = dev_get_drvdata(dev);
+
+ imx_devfreq_perf_disable(priv);
+ platform_device_put(priv->pmu_pdev);
+
return dev_pm_opp_of_remove_table(dev);
}
static int imx_devfreq_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct imx_devfreq *priv;
+ struct device_node *events_node;
const char *gov = DEVFREQ_GOV_USERSPACE;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
@@ -104,10 +227,20 @@ static int imx_devfreq_probe(struct platform_device *pdev)
priv->profile.get_dev_status = imx_devfreq_get_dev_status;
priv->profile.exit = imx_devfreq_exit;
priv->profile.get_cur_freq = imx_devfreq_get_cur_freq;
priv->profile.initial_freq = clk_get_rate(priv->clk);
+ /* Handle devfreq-events */
+ events_node = of_parse_phandle(dev->of_node, "devfreq-events", 0);
+ if (events_node) {
+ ret = imx_devfreq_init_events(dev, events_node);
+ of_node_put(events_node);
+ if (ret)
+ goto err;
+ gov = DEVFREQ_GOV_SIMPLE_ONDEMAND;
+ }
+
priv->devfreq = devm_devfreq_add_device(dev, &priv->profile,
gov, NULL);
if (IS_ERR(priv->devfreq)) {
ret = PTR_ERR(priv->devfreq);
dev_err(dev, "failed to add devfreq device: %d\n", ret);
@@ -115,10 +248,12 @@ static int imx_devfreq_probe(struct platform_device *pdev)
}
return 0;
err:
+ imx_devfreq_perf_disable(priv);
+ platform_device_put(priv->pmu_pdev);
dev_pm_opp_of_remove_table(dev);
return ret;
}
static const struct of_device_id imx_devfreq_of_match[] = {
--
2.17.1
^ permalink raw reply related
* [RFCv3 2/3] PM / devfreq: Add imx driver
From: Leonard Crestez @ 2019-07-24 12:38 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Will Deacon, Stephen Boyd
Cc: Michael Turquette, Jacky Bai, Anson Huang, Abel Vesa,
Dong Aisheng, Viresh Kumar, Georgi Djakov, Alexandre Bailon,
Chanwoo Choi, Mark Rutland, Frank Li, Rob Herring, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, linux-pm, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <cover.1563971855.git.leonard.crestez@nxp.com>
Add initial support for frequency switching on pieces of the imx
interconnect fabric.
Uses clk_set_min_rate so that other subsytems can also impose minimum
rate requests.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
---
drivers/devfreq/Kconfig | 10 +++
drivers/devfreq/Makefile | 1 +
drivers/devfreq/imx-devfreq.c | 143 ++++++++++++++++++++++++++++++++++
3 files changed, 154 insertions(+)
create mode 100644 drivers/devfreq/imx-devfreq.c
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index defe1d438710..dc3311ead538 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -90,10 +90,20 @@ config ARM_EXYNOS_BUS_DEVFREQ
Each memory bus group could contain many memoby bus block. It reads
PPMU counters of memory controllers by using DEVFREQ-event device
and adjusts the operating frequencies and voltages with OPP support.
This does not yet operate with optimal voltages.
+config ARM_IMX_DEVFREQ
+ tristate "i.MX DEVFREQ Driver"
+ depends on ARCH_MXC || COMPILE_TEST
+ select DEVFREQ_GOV_USERSPACE
+ select PM_OPP
+ help
+ This adds the DEVFREQ driver for the i.MX family of SoCs.
+ It allows adjusting frequencies for DDRC (DDR Controller) and various
+ NICs and NOCs which form the SOC interconnect fabric
+
config ARM_TEGRA_DEVFREQ
tristate "NVIDIA Tegra30/114/124/210 DEVFREQ Driver"
depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_114_SOC || \
ARCH_TEGRA_132_SOC || ARCH_TEGRA_124_SOC || \
ARCH_TEGRA_210_SOC || \
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index 338ae8440db6..c2463ed4c934 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -7,10 +7,11 @@ obj-$(CONFIG_DEVFREQ_GOV_POWERSAVE) += governor_powersave.o
obj-$(CONFIG_DEVFREQ_GOV_USERSPACE) += governor_userspace.o
obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o
# DEVFREQ Drivers
obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
+obj-$(CONFIG_ARM_IMX_DEVFREQ) += imx-devfreq.o
obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
obj-$(CONFIG_ARM_TEGRA20_DEVFREQ) += tegra20-devfreq.o
# DEVFREQ Event Drivers
diff --git a/drivers/devfreq/imx-devfreq.c b/drivers/devfreq/imx-devfreq.c
new file mode 100644
index 000000000000..3ee2d37883c6
--- /dev/null
+++ b/drivers/devfreq/imx-devfreq.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 NXP
+ */
+
+#include <linux/clk.h>
+#include <linux/devfreq.h>
+#include <linux/devfreq-event.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/pm_opp.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+struct imx_devfreq {
+ struct devfreq_dev_profile profile;
+ struct devfreq *devfreq;
+ struct clk *clk;
+};
+
+static int imx_devfreq_target(struct device *dev, unsigned long *freq, u32 flags)
+{
+ struct imx_devfreq *priv = dev_get_drvdata(dev);
+ struct dev_pm_opp *new_opp;
+ unsigned long new_freq;
+ int ret;
+
+ new_opp = devfreq_recommended_opp(dev, freq, flags);
+ if (IS_ERR(new_opp)) {
+ ret = PTR_ERR(new_opp);
+ dev_err(dev, "failed to get recommended opp: %d\n", ret);
+ return ret;
+ }
+ new_freq = dev_pm_opp_get_freq(new_opp);
+ dev_pm_opp_put(new_opp);
+
+ ret = clk_set_min_rate(priv->clk, new_freq);
+ if (ret)
+ return ret;
+
+ ret = clk_set_rate(priv->clk, 0);
+ if (ret) {
+ clk_set_min_rate(priv->clk, priv->devfreq->previous_freq);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int imx_devfreq_get_cur_freq(struct device *dev, unsigned long *freq)
+{
+ struct imx_devfreq *priv = dev_get_drvdata(dev);
+
+ *freq = clk_get_rate(priv->clk);
+
+ return 0;
+}
+
+static int imx_devfreq_get_dev_status(struct device *dev,
+ struct devfreq_dev_status *stat)
+{
+ struct imx_devfreq *priv = dev_get_drvdata(dev);
+
+ stat->busy_time = 0;
+ stat->total_time = 0;
+ stat->current_frequency = clk_get_rate(priv->clk);
+
+ return 0;
+}
+
+static void imx_devfreq_exit(struct device *dev)
+{
+ return dev_pm_opp_of_remove_table(dev);
+}
+
+static int imx_devfreq_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct imx_devfreq *priv;
+ const char *gov = DEVFREQ_GOV_USERSPACE;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->devfreq)) {
+ ret = PTR_ERR(priv->devfreq);
+ dev_err(dev, "failed to fetch clk: %d\n", ret);
+ return ret;
+ }
+ platform_set_drvdata(pdev, priv);
+
+ ret = dev_pm_opp_of_add_table(dev);
+ if (ret < 0) {
+ dev_err(dev, "failed to get OPP table\n");
+ return ret;
+ }
+
+ priv->profile.polling_ms = 1000;
+ priv->profile.target = imx_devfreq_target;
+ priv->profile.get_dev_status = imx_devfreq_get_dev_status;
+ priv->profile.exit = imx_devfreq_exit;
+ priv->profile.get_cur_freq = imx_devfreq_get_cur_freq;
+ priv->profile.initial_freq = clk_get_rate(priv->clk);
+
+ priv->devfreq = devm_devfreq_add_device(dev, &priv->profile,
+ gov, NULL);
+ if (IS_ERR(priv->devfreq)) {
+ ret = PTR_ERR(priv->devfreq);
+ dev_err(dev, "failed to add devfreq device: %d\n", ret);
+ goto err;
+ }
+
+ return 0;
+
+err:
+ dev_pm_opp_of_remove_table(dev);
+ return ret;
+}
+
+static const struct of_device_id imx_devfreq_of_match[] = {
+ { .compatible = "fsl,imx8m-ddrc", },
+ { .compatible = "fsl,imx8m-noc", },
+ { .compatible = "fsl,imx8m-nic", },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, imx_devfreq_of_match);
+
+static struct platform_driver imx_devfreq_platdrv = {
+ .probe = imx_devfreq_probe,
+ .driver = {
+ .name = "imx-devfreq",
+ .of_match_table = of_match_ptr(imx_devfreq_of_match),
+ },
+};
+module_platform_driver(imx_devfreq_platdrv);
+
+MODULE_DESCRIPTION("Generic i.MX bus frequency driver");
+MODULE_AUTHOR("Leonard Crestez <leonard.crestez@nxp.com>");
+MODULE_LICENSE("GPL v2");
--
2.17.1
^ permalink raw reply related
* [RFCv3 1/3] dt-bindings: devfreq: Add initial bindings for i.MX
From: Leonard Crestez @ 2019-07-24 12:38 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Will Deacon, Stephen Boyd
Cc: Michael Turquette, Jacky Bai, Anson Huang, Abel Vesa,
Dong Aisheng, Viresh Kumar, Georgi Djakov, Alexandre Bailon,
Chanwoo Choi, Mark Rutland, Frank Li, Rob Herring, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, linux-pm, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <cover.1563971855.git.leonard.crestez@nxp.com>
Add initial dt bindings for the interconnects inside i.MX chips.
Multiple external IPs are involved but SOC integration means the
software controllable interfaces are very similar.
This is initially only for imx8mm but add an "fsl,imx-bus" fallback
similar to exynos-bus.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
---
.../devicetree/bindings/devfreq/imx.yaml | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/devfreq/imx.yaml
diff --git a/Documentation/devicetree/bindings/devfreq/imx.yaml b/Documentation/devicetree/bindings/devfreq/imx.yaml
new file mode 100644
index 000000000000..87f90cddfd29
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/imx.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/devfreq/imx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic i.MX bus frequency device
+
+maintainers:
+ - Leonard Crestez <leonard.crestez@nxp.com>
+
+description: |
+ The i.MX SoC family has multiple buses for which clock frequency (and sometimes
+ voltage) can be adjusted.
+
+ Some of those buses expose register areas mentioned in the memory maps as GPV
+ ("Global Programmers View") but not all. Access to this area might be denied for
+ normal world.
+
+ The buses are based on externally licensed IPs such as ARM NIC-301 and Arteris
+ FlexNOC but DT bindings are specific to the integration of these bus
+ interconnect IPs into imx SOCs.
+
+properties:
+ reg:
+ maxItems: 1
+ description: GPV area
+
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8m-noc
+ - fsl,imx8m-nic
+ - fsl,imx8m-ddrc
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8mm-clock.h>
+ ddrc: dram-controller@3d400000 {
+ compatible = "fsl,imx8mm-ddrc";
+ reg = <0x3d400000 0x400000>;
+ clocks = <&clk IMX8MM_CLK_DRAM>;
+ operating-points-v2 = <&ddrc_opp_table>;
+ };
+
+ - |
+ noc: noc@32700000 {
+ compatible = "fsl,imx8mm-noc";
+ reg = <0x32700000 0x100000>;
+ clocks = <&clk IMX8MM_CLK_NOC>;
+ operating-points-v2 = <&noc_opp_table>;
+ };
--
2.17.1
^ permalink raw reply related
* [RFCv2 0/3] PM / devfreq: Add imx driver
From: Leonard Crestez @ 2019-07-24 12:38 UTC (permalink / raw)
To: MyungJoo Ham, Kyungmin Park, Will Deacon, Stephen Boyd
Cc: Michael Turquette, Jacky Bai, Anson Huang, Abel Vesa,
Dong Aisheng, Viresh Kumar, Georgi Djakov, Alexandre Bailon,
Chanwoo Choi, Mark Rutland, Frank Li, Rob Herring, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, linux-pm, devicetree, linux-arm-kernel,
linux-kernel
This series attempts to add devfreq support for imx8mm, covering dynamic
scaling of internal buses and dram.
Actual scaling is performed through the clk framework: The NOC and main
NICs are driven by composite clks and a new 'imx8m-dram' clk is used for
scaling dram using firmware calls.
Frequency target is set via "clk_set_min_rate", this allows an unrelated
subsystem (for example interconnect) to also request minimum rates as a
form for proactive scaling.
The dram controller (DDRC) has a performance monitoring block attached
for which a perf driver already exists. Instead of reimplementing that
as devfreq-events the perf in-kernel API is used.
Changes since v2:
* Solve review comments
* Add yaml binding doc
* Add perf event support
Link to v2: https://patchwork.kernel.org/patch/11021571/
DRAM frequency switching through clk framework is here:
* https://patchwork.kernel.org/patch/11049429/
That part might not be accepted in clk and it might have to be moved to
devfreq also.
Leonard Crestez (3):
dt-bindings: devfreq: Add initial bindings for i.MX
PM / devfreq: Add imx driver
PM / devfreq: Add imx perf event support
.../devicetree/bindings/devfreq/imx.yaml | 59 ++++
drivers/devfreq/Kconfig | 10 +
drivers/devfreq/Makefile | 1 +
drivers/devfreq/imx-devfreq.c | 278 ++++++++++++++++++
4 files changed, 348 insertions(+)
create mode 100644 Documentation/devicetree/bindings/devfreq/imx.yaml
create mode 100644 drivers/devfreq/imx-devfreq.c
--
2.17.1
^ permalink raw reply
* [PATCH 1/1] ARM: dts: am335x: Fix UARTs length
From: Emmanuel Vadot @ 2019-07-24 12:23 UTC (permalink / raw)
To: bcousson, tony, robh+dt, mark.rutland, linux-omap
Cc: devicetree, linux-kernel, Emmanuel Vadot
In-Reply-To: <20190724122329.21231-1-manu@freebsd.org>
As seen on the AM335x TRM all the UARTs controller only are 0x1000 in size.
Fix this in the DTS.
Signed-off-by: Emmanuel Vadot <manu@freebsd.org>
---
arch/arm/boot/dts/am33xx-l4.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi
index ced1a19d5f89..a20b04b72be4 100644
--- a/arch/arm/boot/dts/am33xx-l4.dtsi
+++ b/arch/arm/boot/dts/am33xx-l4.dtsi
@@ -185,7 +185,7 @@
uart0: serial@0 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
clock-frequency = <48000000>;
- reg = <0x0 0x2000>;
+ reg = <0x0 0x1000>;
interrupts = <72>;
status = "disabled";
dmas = <&edma 26 0>, <&edma 27 0>;
@@ -934,7 +934,7 @@
uart1: serial@0 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
clock-frequency = <48000000>;
- reg = <0x0 0x2000>;
+ reg = <0x0 0x1000>;
interrupts = <73>;
status = "disabled";
dmas = <&edma 28 0>, <&edma 29 0>;
@@ -966,7 +966,7 @@
uart2: serial@0 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
clock-frequency = <48000000>;
- reg = <0x0 0x2000>;
+ reg = <0x0 0x1000>;
interrupts = <74>;
status = "disabled";
dmas = <&edma 30 0>, <&edma 31 0>;
@@ -1614,7 +1614,7 @@
uart3: serial@0 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
clock-frequency = <48000000>;
- reg = <0x0 0x2000>;
+ reg = <0x0 0x1000>;
interrupts = <44>;
status = "disabled";
};
@@ -1644,7 +1644,7 @@
uart4: serial@0 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
clock-frequency = <48000000>;
- reg = <0x0 0x2000>;
+ reg = <0x0 0x1000>;
interrupts = <45>;
status = "disabled";
};
@@ -1674,7 +1674,7 @@
uart5: serial@0 {
compatible = "ti,am3352-uart", "ti,omap3-uart";
clock-frequency = <48000000>;
- reg = <0x0 0x2000>;
+ reg = <0x0 0x1000>;
interrupts = <46>;
status = "disabled";
};
--
2.22.0
^ permalink raw reply related
* [PATCH 0/1] ARM: dts: am335x: Fix UARTs length
From: Emmanuel Vadot @ 2019-07-24 12:23 UTC (permalink / raw)
To: bcousson, tony, robh+dt, mark.rutland, linux-omap
Cc: devicetree, linux-kernel, Emmanuel Vadot
For some reason the uart region size were set to 0x2000 while the TRM clearly
specify that the size is 0x1000.
I guess this is not a problem on Linux but for FreeBSD the resource manager will
not allow the mapping when the region declared in the parents is less that the one
declared in the child.
Emmanuel Vadot (1):
ARM: dts: am335x: Fix UARTs length
arch/arm/boot/dts/am33xx-l4.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
--
2.22.0
^ permalink raw reply
* [PATCH 4/4] dt-bindings: i2c: riic: Rename bindings documentation file
From: Simon Horman @ 2019-07-24 12:15 UTC (permalink / raw)
To: Wolfram Sang, Chris Brandt
Cc: Rob Herring, Mark Rutland, Magnus Damm, linux-i2c, devicetree,
linux-renesas-soc, Simon Horman
In-Reply-To: <20190724121559.19079-1-horms+renesas@verge.net.au>
Rename the bindings documentation file for Renesas EMEV2 IIC controller
from i2c-emev2.txt to renesas,iic-emev2.txt.
This is part of an ongoing effort to name bindings documentation files for
Renesas IP blocks consistently, in line with the compat strings they
document.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
.../devicetree/bindings/i2c/{i2c-emev2.txt => renesas,iic-emev2.txt} | 0
MAINTAINERS | 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)
rename Documentation/devicetree/bindings/i2c/{i2c-emev2.txt => renesas,iic-emev2.txt} (100%)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-emev2.txt b/Documentation/devicetree/bindings/i2c/renesas,iic-emev2.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/i2c-emev2.txt
rename to Documentation/devicetree/bindings/i2c/renesas,iic-emev2.txt
diff --git a/MAINTAINERS b/MAINTAINERS
index fc3ed4fe0ba5..e751ebb1a0ed 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13628,7 +13628,7 @@ F: drivers/clk/renesas/
RENESAS EMEV2 I2C DRIVER
M: Wolfram Sang <wsa+renesas@sang-engineering.com>
S: Supported
-F: Documentation/devicetree/bindings/i2c/i2c-emev2.txt
+F: Documentation/devicetree/bindings/i2c/renesas,iic-emev2.txt
F: drivers/i2c/busses/i2c-emev2.c
RENESAS ETHERNET DRIVERS
--
2.11.0
^ permalink raw reply related
* [PATCH 3/4] dt-bindings: i2c: riic: Rename bindings documentation file
From: Simon Horman @ 2019-07-24 12:15 UTC (permalink / raw)
To: Wolfram Sang, Chris Brandt
Cc: Rob Herring, Mark Rutland, Magnus Damm, linux-i2c, devicetree,
linux-renesas-soc, Simon Horman
In-Reply-To: <20190724121559.19079-1-horms+renesas@verge.net.au>
Rename the bindings documentation file for RIIC controller
from i2c-riic.txt to renesas,riic.txt.
This is part of an ongoing effort to name bindings documentation files for
Renesas IP blocks consistently, in line with the compat strings they
document.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
.../devicetree/bindings/i2c/{i2c-riic.txt => renesas,riic.txt} | 0
MAINTAINERS | 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)
rename Documentation/devicetree/bindings/i2c/{i2c-riic.txt => renesas,riic.txt} (100%)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-riic.txt b/Documentation/devicetree/bindings/i2c/renesas,riic.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/i2c-riic.txt
rename to Documentation/devicetree/bindings/i2c/renesas,riic.txt
diff --git a/MAINTAINERS b/MAINTAINERS
index b8c1181baea9..fc3ed4fe0ba5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13658,7 +13658,7 @@ F: drivers/i2c/busses/i2c-sh_mobile.c
RENESAS RIIC DRIVER
M: Chris Brandt <chris.brandt@renesas.com>
S: Supported
-F: Documentation/devicetree/bindings/i2c/i2c-riic.txt
+F: Documentation/devicetree/bindings/i2c/renesas,riic.txt
F: drivers/i2c/busses/i2c-riic.c
RENESAS USB PHY DRIVER
--
2.11.0
^ permalink raw reply related
* [PATCH 2/4] dt-bindings: i2c: rcar: Rename bindings documentation file
From: Simon Horman @ 2019-07-24 12:15 UTC (permalink / raw)
To: Wolfram Sang, Chris Brandt
Cc: Rob Herring, Mark Rutland, Magnus Damm, linux-i2c, devicetree,
linux-renesas-soc, Simon Horman
In-Reply-To: <20190724121559.19079-1-horms+renesas@verge.net.au>
Rename the bindings documentation file for R-Car I2C controller
from i2c-rcar.txt to renesas,rcar.txt.
This is part of an ongoing effort to name bindings documentation files for
Renesas IP blocks consistently, in line with the compat strings they
document.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
Documentation/devicetree/bindings/i2c/{i2c-rcar.txt => renesas,i2c.txt} | 0
MAINTAINERS | 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)
rename Documentation/devicetree/bindings/i2c/{i2c-rcar.txt => renesas,i2c.txt} (100%)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt b/Documentation/devicetree/bindings/i2c/renesas,i2c.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/i2c-rcar.txt
rename to Documentation/devicetree/bindings/i2c/renesas,i2c.txt
diff --git a/MAINTAINERS b/MAINTAINERS
index 4c8262837da9..b8c1181baea9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13650,7 +13650,7 @@ F: drivers/iio/adc/rcar-gyroadc.c
RENESAS R-CAR I2C DRIVERS
M: Wolfram Sang <wsa+renesas@sang-engineering.com>
S: Supported
-F: Documentation/devicetree/bindings/i2c/i2c-rcar.txt
+F: Documentation/devicetree/bindings/i2c/renesas,i2c.txt
F: Documentation/devicetree/bindings/i2c/renesas,iic.txt
F: drivers/i2c/busses/i2c-rcar.c
F: drivers/i2c/busses/i2c-sh_mobile.c
--
2.11.0
^ permalink raw reply related
* [PATCH 1/4] dt-bindings: i2c: sh_mobile: Rename bindings documentation file
From: Simon Horman @ 2019-07-24 12:15 UTC (permalink / raw)
To: Wolfram Sang, Chris Brandt
Cc: Rob Herring, Mark Rutland, Magnus Damm, linux-i2c, devicetree,
linux-renesas-soc, Simon Horman
In-Reply-To: <20190724121559.19079-1-horms+renesas@verge.net.au>
Rename the bindings documentation file for sh_mobile I2C controller
from i2c-sh_mobile.txt to renesas,iic.txt.
This is part of an ongoing effort to name bindings documentation files for
Renesas IP blocks consistently, in line with the compat strings they
document.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
.../devicetree/bindings/i2c/{i2c-sh_mobile.txt => renesas,iic.txt} | 0
MAINTAINERS | 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)
rename Documentation/devicetree/bindings/i2c/{i2c-sh_mobile.txt => renesas,iic.txt} (100%)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt b/Documentation/devicetree/bindings/i2c/renesas,iic.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
rename to Documentation/devicetree/bindings/i2c/renesas,iic.txt
diff --git a/MAINTAINERS b/MAINTAINERS
index 783569e3c4b4..4c8262837da9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13651,7 +13651,7 @@ RENESAS R-CAR I2C DRIVERS
M: Wolfram Sang <wsa+renesas@sang-engineering.com>
S: Supported
F: Documentation/devicetree/bindings/i2c/i2c-rcar.txt
-F: Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
+F: Documentation/devicetree/bindings/i2c/renesas,iic.txt
F: drivers/i2c/busses/i2c-rcar.c
F: drivers/i2c/busses/i2c-sh_mobile.c
--
2.11.0
^ permalink raw reply related
* [PATCH 0/4] dt-bindings: i2c: renesas: Rename bindings documentation files
From: Simon Horman @ 2019-07-24 12:15 UTC (permalink / raw)
To: Wolfram Sang, Chris Brandt
Cc: Rob Herring, Mark Rutland, Magnus Damm, linux-i2c, devicetree,
linux-renesas-soc, Simon Horman
Rename the bindings documentation file for Renesas I2C controllers.
This is part of an ongoing effort to name bindings documentation files for
Renesas IP blocks consistently, in line with the compat strings they
document.
Based on v5.3-rc1
Simon Horman (4):
dt-bindings: i2c: sh_mobile: Rename bindings documentation file
dt-bindings: i2c: rcar: Rename bindings documentation file
dt-bindings: i2c: riic: Rename bindings documentation file
dt-bindings: i2c: riic: Rename bindings documentation file
.../devicetree/bindings/i2c/{i2c-rcar.txt => renesas,i2c.txt} | 0
.../bindings/i2c/{i2c-emev2.txt => renesas,iic-emev2.txt} | 0
.../bindings/i2c/{i2c-sh_mobile.txt => renesas,iic.txt} | 0
.../devicetree/bindings/i2c/{i2c-riic.txt => renesas,riic.txt} | 0
MAINTAINERS | 8 ++++----
5 files changed, 4 insertions(+), 4 deletions(-)
rename Documentation/devicetree/bindings/i2c/{i2c-rcar.txt => renesas,i2c.txt} (100%)
rename Documentation/devicetree/bindings/i2c/{i2c-emev2.txt => renesas,iic-emev2.txt} (100%)
rename Documentation/devicetree/bindings/i2c/{i2c-sh_mobile.txt => renesas,iic.txt} (100%)
rename Documentation/devicetree/bindings/i2c/{i2c-riic.txt => renesas,riic.txt} (100%)
--
2.11.0
^ permalink raw reply
* [PATCH v2 2/2] dt-bindings: arm: Document Armadeus SoM and Dev boards devicetree binding
From: Sébastien Szymanski @ 2019-07-24 12:06 UTC (permalink / raw)
To: Shawn Guo
Cc: Mark Rutland, devicetree, Sascha Hauer, Rob Herring,
NXP Linux Team, Pengutronix Kernel Team, Fabio Estevam,
linux-arm-kernel
In-Reply-To: <20190724120623.2385-1-sebastien.szymanski@armadeus.com>
Document the following Armadeus SoM and Dev boards devicetree binding
already supported:
- armadeus,imx27-apf27 and armadeus,imx27-apf27dev
- armadeus,imx28-apf28 and armadeus,imx28-apf28dev
- armadeus,imx51-apf51 and armadeus,imx51-apf51dev
- armadeus,imx6{q,dl}-apf6 and armadeus,imx{q,dl}-apf6dev
- armadeus,imx6{ul,ull}-opos6ul and armadeus,imx{ul,ull}-opos6uldev
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
---
Changes for v2:
- new patch
Documentation/devicetree/bindings/arm/fsl.yaml | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 7294ac36f4c0..9ba3a3be82d1 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -38,12 +38,16 @@ properties:
- description: i.MX27 Product Development Kit
items:
- enum:
+ - armadeus,imx27-apf27 # APF27 SoM
+ - armadeus,imx27-apf27dev # APF27 SoM on APF27Dev board
- fsl,imx27-pdk
- const: fsl,imx27
- description: i.MX28 based Boards
items:
- enum:
+ - armadeus,imx28-apf28 # APF28 SoM
+ - armadeus,imx28-apf28dev # APF28 SoM on APF28Dev board
- fsl,imx28-evk
- i2se,duckbill
- i2se,duckbill-2
@@ -87,7 +91,8 @@ properties:
- description: i.MX51 Babbage Board
items:
- enum:
- - armadeus,imx51-apf51
+ - armadeus,imx51-apf51 # APF51 SoM
+ - armadeus,imx51-apf51dev # APF51 SoM on APF51Dev board
- fsl,imx51-babbage
- technologic,imx51-ts4800
- const: fsl,imx51
@@ -106,6 +111,8 @@ properties:
- description: i.MX6Q based Boards
items:
- enum:
+ - armadeus,imx6q-apf6 # APF6 (Quad/Dual) SoM
+ - armadeus,imx6q-apf6dev # APF6 (Quad/Dual) SoM on APF6Dev board
- emtrion,emcon-mx6 # emCON-MX6D or emCON-MX6Q SoM
- emtrion,emcon-mx6-avari # emCON-MX6D or emCON-MX6Q SoM on Avari Base
- fsl,imx6q-arm2
@@ -126,6 +133,8 @@ properties:
- description: i.MX6DL based Boards
items:
- enum:
+ - armadeus,imx6dl-apf6 # APF6 (Solo) SoM
+ - armadeus,imx6dl-apf6dldev # APF6 (Solo) SoM on APF6Dev board
- eckelmann,imx6dl-ci4x10
- emtrion,emcon-mx6 # emCON-MX6S or emCON-MX6DL SoM
- emtrion,emcon-mx6-avari # emCON-MX6S or emCON-MX6DL SoM on Avari Base
@@ -160,12 +169,16 @@ properties:
- description: i.MX6UL based Boards
items:
- enum:
+ - armadeus,imx6ul-opos6ul # OPOS6UL (i.MX6UL) SoM
+ - armadeus,imx6ul-opos6uldev # OPOS6UL (i.MX6UL) SoM on OPOS6ULDev board
- fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board
- const: fsl,imx6ul
- description: i.MX6ULL based Boards
items:
- enum:
+ - armadeus,imx6ull-opos6ul # OPOS6UL (i.MX6ULL) SoM
+ - armadeus,imx6ull-opos6uldev # OPOS6UL (i.MX6ULL) SoM on OPOS6ULDev board
- fsl,imx6ull-14x14-evk # i.MX6 UltraLiteLite 14x14 EVK Board
- const: fsl,imx6ull
--
2.21.0
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^ permalink raw reply related
* [PATCH v2 1/2] ARM: dts: opos6ul/opos6uldev: rework device tree to support i.MX6ULL
From: Sébastien Szymanski @ 2019-07-24 12:06 UTC (permalink / raw)
To: Shawn Guo
Cc: Mark Rutland, devicetree, Sascha Hauer, Rob Herring,
NXP Linux Team, Pengutronix Kernel Team, Fabio Estevam,
linux-arm-kernel
Rework the device trees of the OPOS6UL and OPOS6ULDev boards to support
the OPOS6UL SoM with an i.MX6ULL SoC. The device trees are now as
following:
- imx6ul-imx6ull-opos6ul.dtsi
common for both i.MX6UL and i.MX6ULL OPOS6UL SoM.
- imx6ul-opos6ul.dtsi
for i.MX6UL OPOS6UL SoM. It includes imx6ul.dtsi and
imx6ul-imx6ull-opos6ul.dtsi.
- imx6ull-opos6ul.dtsi
for i.MX6ULL OPOS6UL SoM. It includes imx6ull.dtsi and
imx6ul-imx6ull-opos6ul.dtsi.
- imx6ul-imx6ull-opos6uldev.dtsi
OPOS6ULDev base device tree.
- imx6ul-opos6uldev.dts
OPOS6ULDev board with an i.MX6UL OPOS6UL SoM. It includes
imx6ul-opos6ul.dtsi and imx6ul-imx6ull-opos6uldevdtsi.
- imx6ull-opos6uldev.dts
OPOS6ULDev board with an i.MX6ULL OPOS6UL SoM. It includes
imx6ull-opos6ul.dtsi and imx6ul-imx6ull-opos6uldevdtsi.
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
---
Changes for v2:
- explain the file hierarchy in the commit log
- use MIT license instead of X11
- Change compatible properties to "armadeus,imx6{ul,ull}-opos6ul" and
"armadeus,imx6{ul,ull}-opos6uldev" to follow the bindings of the
Armadeus boards already supported.
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6ul-imx6ull-opos6ul.dtsi | 148 +++++++
.../boot/dts/imx6ul-imx6ull-opos6uldev.dtsi | 338 ++++++++++++++++
arch/arm/boot/dts/imx6ul-opos6ul.dtsi | 195 +--------
arch/arm/boot/dts/imx6ul-opos6uldev.dts | 382 +-----------------
arch/arm/boot/dts/imx6ull-opos6ul.dtsi | 6 +
arch/arm/boot/dts/imx6ull-opos6uldev.dts | 42 ++
7 files changed, 547 insertions(+), 565 deletions(-)
create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-opos6ul.dtsi
create mode 100644 arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-opos6ul.dtsi
create mode 100644 arch/arm/boot/dts/imx6ull-opos6uldev.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9159fa2cea90..067724c86bc4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -580,6 +580,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-eval-v3.dtb \
imx6ull-colibri-wifi-eval-v3.dtb \
+ imx6ull-opos6uldev.dtb \
imx6ulz-14x14-evk.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-opos6ul.dtsi b/arch/arm/boot/dts/imx6ul-imx6ull-opos6ul.dtsi
new file mode 100644
index 000000000000..f2386dcb9ff2
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-imx6ull-opos6ul.dtsi
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2019 Armadeus Systems <support@armadeus.com>
+
+/ {
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0>; /* will be filled by U-Boot */
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ usdhc3_pwrseq: usdhc3-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-reset-duration = <1>;
+ phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+ phy-handle = <ðphy1>;
+ phy-supply = <®_3v3>;
+ status = "okay";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+ status = "okay";
+ };
+ };
+};
+
+/* Bluetooth */
+&uart8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart8>;
+ uart-has-rtscts;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+ status = "okay";
+};
+
+/* WiFi */
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ mmc-pwrseq = <&usdhc3_pwrseq>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brcmf: wifi@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "host-wake";
+ };
+};
+
+&iomuxc {
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x130b0
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x130b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ /* INT# */
+ MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0
+ /* RST# */
+ MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x130b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
+ >;
+ };
+
+ pinctrl_uart8: uart8grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x1b0b0
+ MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x1b0b0
+ /* BT_REG_ON */
+ MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
+ MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
+ MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
+ MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x1b0b0
+ MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x100b0
+ MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x1b0b0
+ MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x1b0b0
+ MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x1b0b0
+ MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x1b0b0
+ /* WL_REG_ON */
+ MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x130b0
+ /* WL_IRQ */
+ MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi b/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi
new file mode 100644
index 000000000000..18966350bfd8
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-imx6ull-opos6uldev.dtsi
@@ -0,0 +1,338 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2019 Armadeus Systems <support@armadeus.com>
+
+/ {
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm3 0 191000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ power-supply = <®_5v>;
+ status = "okay";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ user-button {
+ label = "User button";
+ gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_MISC>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ user-led {
+ label = "User";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led>;
+ gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ onewire {
+ compatible = "w1-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_w1>;
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ panel: panel {
+ compatible = "armadeus,st0700-adapt";
+ power-supply = <®_3v3>;
+ backlight = <&backlight>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&lcdif_out>;
+ };
+ };
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usbotg1_vbus: regulator-usbotg1vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usbotg1vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_vbus>;
+ gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usbotg2_vbus: regulator-usbotg2vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usbotg2vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg2_vbus>;
+ gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&adc1 {
+ vref-supply = <®_3v3>;
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <®_5v>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <®_5v>;
+ status = "okay";
+};
+
+&ecspi4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi4>;
+ cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ spidev0: spi@0 {
+ compatible = "spidev";
+ reg = <0>;
+ spi-max-frequency = <5000000>;
+ };
+
+ spidev1: spi@1 {
+ compatible = "spidev";
+ reg = <1>;
+ spi-max-frequency = <5000000>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif>;
+ status = "okay";
+
+ port {
+ lcdif_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&snvs_pwrkey {
+ status = "disabled";
+};
+
+&tsc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tsc>;
+ xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ measure-delay-time = <0xffff>;
+ pre-charge-time = <0xffff>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_id>;
+ vbus-supply = <®_usbotg1_vbus>;
+ dr_mode = "otg";
+ disable-over-current;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <®_usbotg2_vbus>;
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpios>;
+
+ pinctrl_ecspi4: ecspi4grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x1b0b0
+ MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x1b0b0
+ MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x1b0b0
+ MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x1b0b0
+ MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
+ MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
+ MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
+ >;
+ };
+
+ pinctrl_gpios: gpiosgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0b0b0
+ MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x0b0b0
+ MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x0b0b0
+ MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0b0b0
+ MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x0b0b0
+ MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0b0b0
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0b0b0
+ MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x0b0b0
+ >;
+ };
+
+ pinctrl_gpio_keys: gpiokeysgrp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+ >;
+ };
+
+ pinctrl_lcdif: lcdifgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x100b1
+ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x100b1
+ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x100b1
+ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x100b1
+ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x100b1
+ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x100b1
+ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x100b1
+ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x100b1
+ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x100b1
+ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x100b1
+ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x100b1
+ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x100b1
+ MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x100b1
+ MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x100b1
+ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x100b1
+ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x100b1
+ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x100b1
+ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x100b1
+ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x100b1
+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x100b1
+ MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x100b1
+ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x100b1
+ >;
+ };
+
+ pinctrl_led: ledgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0
+ >;
+ };
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_ALE__PWM3_OUT 0x1b0b0
+ >;
+ };
+
+ pinctrl_tsc: tscgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1_id: usbotg1idgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x1b0b0
+ >;
+ };
+
+ pinctrl_usbotg1_vbus: usbotg1vbusgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ul-opos6ul.dtsi b/arch/arm/boot/dts/imx6ul-opos6ul.dtsi
index cf7faf4b9c47..6ce84f92b027 100644
--- a/arch/arm/boot/dts/imx6ul-opos6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul-opos6ul.dtsi
@@ -1,193 +1,6 @@
-/*
- * Copyright 2017 Armadeus Systems <support@armadeus.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2017 Armadeus Systems <support@armadeus.com>
#include "imx6ul.dtsi"
-
-/ {
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0>; /* will be filled by U-Boot */
- };
-
- reg_3v3: regulator-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- usdhc3_pwrseq: usdhc3-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
- };
-};
-
-&fec1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_enet1>;
- phy-mode = "rmii";
- phy-reset-duration = <1>;
- phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
- phy-handle = <ðphy1>;
- phy-supply = <®_3v3>;
- status = "okay";
-
- mdio: mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy1: ethernet-phy@1 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <1>;
- interrupt-parent = <&gpio4>;
- interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
- status = "okay";
- };
- };
-};
-
-/* Bluetooth */
-&uart8 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart8>;
- uart-has-rtscts;
- status = "okay";
-};
-
-/* eMMC */
-&usdhc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
- bus-width = <8>;
- no-1-8-v;
- non-removable;
- status = "okay";
-};
-
-/* WiFi */
-&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
- bus-width = <4>;
- no-1-8-v;
- non-removable;
- mmc-pwrseq = <&usdhc3_pwrseq>;
- status = "okay";
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- brcmf: wifi@1 {
- compatible = "brcm,bcm4329-fmac";
- reg = <1>;
- interrupt-parent = <&gpio2>;
- interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "host-wake";
- };
-};
-
-&iomuxc {
- pinctrl_enet1: enet1grp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
- MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
- MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x130b0
- MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x130b0
- MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0
- MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0
- MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
- MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
- MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
- /* INT# */
- MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0
- /* RST# */
- MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x130b0
- MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
- >;
- };
-
- pinctrl_uart8: uart8grp {
- fsl,pins = <
- MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b0
- MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b0
- MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x1b0b0
- MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x1b0b0
- /* BT_REG_ON */
- MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
- MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
- MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
- MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
- MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
- MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
- MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
- MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
- MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
- MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x1b0b0
- MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x100b0
- MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x1b0b0
- MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x1b0b0
- MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x1b0b0
- MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x1b0b0
- /* WL_REG_ON */
- MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x130b0
- /* WL_IRQ */
- MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0
- >;
- };
-};
+#include "imx6ul-imx6ull-opos6ul.dtsi"
diff --git a/arch/arm/boot/dts/imx6ul-opos6uldev.dts b/arch/arm/boot/dts/imx6ul-opos6uldev.dts
index 8ecdb9ad2b2e..375b98d7205a 100644
--- a/arch/arm/boot/dts/imx6ul-opos6uldev.dts
+++ b/arch/arm/boot/dts/imx6ul-opos6uldev.dts
@@ -1,293 +1,21 @@
-/*
- * Copyright 2017 Armadeus Systems <support@armadeus.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public
- * License along with this file; if not, write to the Free
- * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2017 Armadeus Systems <support@armadeus.com>
/dts-v1/;
#include "imx6ul-opos6ul.dtsi"
+#include "imx6ul-imx6ull-opos6uldev.dtsi"
/ {
- model = "Armadeus Systems OPOS6UL SoM on OPOS6ULDev board";
- compatible = "armadeus,opos6uldev", "armadeus,opos6ul", "fsl,imx6ul";
-
- chosen {
- stdout-path = &uart1;
- };
-
- backlight: backlight {
- compatible = "pwm-backlight";
- pwms = <&pwm3 0 191000>;
- brightness-levels = <0 4 8 16 32 64 128 255>;
- default-brightness-level = <7>;
- power-supply = <®_5v>;
- status = "okay";
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_keys>;
-
- user-button {
- label = "User button";
- gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_MISC>;
- wakeup-source;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- user-led {
- label = "User";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_led>;
- gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
- };
-
- onewire {
- compatible = "w1-gpio";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_w1>;
- gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
- };
-
- panel: panel {
- compatible = "armadeus,st0700-adapt";
- power-supply = <®_3v3>;
- backlight = <&backlight>;
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&lcdif_out>;
- };
- };
- };
-
- reg_5v: regulator-5v {
- compatible = "regulator-fixed";
- regulator-name = "5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- reg_usbotg1_vbus: regulator-usbotg1vbus {
- compatible = "regulator-fixed";
- regulator-name = "usbotg1vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg1_vbus>;
- gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
- reg_usbotg2_vbus: regulator-usbotg2vbus {
- compatible = "regulator-fixed";
- regulator-name = "usbotg2vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg2_vbus>;
- gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-};
-
-&adc1 {
- vref-supply = <®_3v3>;
- status = "okay";
-};
-
-&can1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1>;
- xceiver-supply = <®_5v>;
- status = "okay";
-};
-
-&can2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2>;
- xceiver-supply = <®_5v>;
- status = "okay";
-};
-
-&ecspi4 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ecspi4>;
- cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>;
- status = "okay";
-
- spidev0: spi@0 {
- compatible = "spidev";
- reg = <0>;
- spi-max-frequency = <5000000>;
- };
-
- spidev1: spi@1 {
- compatible = "spidev";
- reg = <1>;
- spi-max-frequency = <5000000>;
- };
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
- clock_frequency = <400000>;
- status = "okay";
-};
-
-&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2>;
- clock_frequency = <400000>;
- status = "okay";
-};
-
-&lcdif {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lcdif>;
- status = "okay";
-
- port {
- lcdif_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
-};
-
-&pwm3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_pwm3>;
- status = "okay";
-};
-
-&snvs_pwrkey {
- status = "disabled";
-};
-
-&tsc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_tsc>;
- xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
- measure-delay-time = <0xffff>;
- pre-charge-time = <0xffff>;
- status = "okay";
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart1>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-&usbotg1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg1_id>;
- vbus-supply = <®_usbotg1_vbus>;
- dr_mode = "otg";
- disable-over-current;
- status = "okay";
-};
-
-&usbotg2 {
- vbus-supply = <®_usbotg2_vbus>;
- dr_mode = "host";
- disable-over-current;
- status = "okay";
+ model = "Armadeus Systems OPOS6UL SoM (i.MX6UL) on OPOS6ULDev board";
+ compatible = "armadeus,imx6ul-opos6uldev", "armadeus,imx6ul-opos6ul", "fsl,imx6ul";
};
&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpios>;
+ pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_tamper_gpios>;
- pinctrl_ecspi4: ecspi4grp {
+ pinctrl_tamper_gpios: tampergpiosgrp {
fsl,pins = <
- MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x1b0b0
- MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x1b0b0
- MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x1b0b0
- MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x1b0b0
- MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x1b0b0
- >;
- };
-
- pinctrl_flexcan1: flexcan1grp {
- fsl,pins = <
- MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
- MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
- >;
- };
-
- pinctrl_flexcan2: flexcan2grp {
- fsl,pins = <
- MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
- MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
- >;
- };
-
- pinctrl_gpios: gpiosgrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0b0b0
- MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x0b0b0
- MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x0b0b0
- MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0b0b0
- MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x0b0b0
- MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0b0b0
- MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0b0b0
- MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x0b0b0
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0
@@ -299,100 +27,6 @@
>;
};
- pinctrl_gpio_keys: gpiokeysgrp {
- fsl,pins = <
- MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0b0b0
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
- MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
- >;
- };
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
- MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
- >;
- };
-
- pinctrl_lcdif: lcdifgrp {
- fsl,pins = <
- MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x100b1
- MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x100b1
- MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x100b1
- MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x100b1
- MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x100b1
- MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x100b1
- MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x100b1
- MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x100b1
- MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x100b1
- MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x100b1
- MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x100b1
- MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x100b1
- MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x100b1
- MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x100b1
- MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x100b1
- MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x100b1
- MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x100b1
- MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x100b1
- MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x100b1
- MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x100b1
- MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x100b1
- MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x100b1
- >;
- };
-
- pinctrl_led: ledgrp {
- fsl,pins = <
- MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0
- >;
- };
-
- pinctrl_pwm3: pwm3grp {
- fsl,pins = <
- MX6UL_PAD_NAND_ALE__PWM3_OUT 0x1b0b0
- >;
- };
-
- pinctrl_tsc: tscgrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
- MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
- MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
- MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
- MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
- >;
- };
-
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
- MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
- >;
- };
-
- pinctrl_usbotg1_id: usbotg1idgrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x1b0b0
- >;
- };
-
- pinctrl_usbotg1_vbus: usbotg1vbusgrp {
- fsl,pins = <
- MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b0b0
- >;
- };
-
pinctrl_usbotg2_vbus: usbotg2vbusgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
diff --git a/arch/arm/boot/dts/imx6ull-opos6ul.dtsi b/arch/arm/boot/dts/imx6ull-opos6ul.dtsi
new file mode 100644
index 000000000000..155f941f2811
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-opos6ul.dtsi
@@ -0,0 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2019 Armadeus Systems <support@armadeus.com>
+
+#include "imx6ull.dtsi"
+#include "imx6ul-imx6ull-opos6ul.dtsi"
diff --git a/arch/arm/boot/dts/imx6ull-opos6uldev.dts b/arch/arm/boot/dts/imx6ull-opos6uldev.dts
new file mode 100644
index 000000000000..198fdb72641b
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-opos6uldev.dts
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+//
+// Copyright 2019 Armadeus Systems <support@armadeus.com>
+
+/dts-v1/;
+#include "imx6ull-opos6ul.dtsi"
+#include "imx6ul-imx6ull-opos6uldev.dtsi"
+
+/ {
+ model = "Armadeus Systems OPOS6UL SoM (i.MX6ULL) on OPOS6ULDev board";
+ compatible = "armadeus,imx6ull-opos6uldev", "armadeus,imx6ull-opos6ul", "fsl,imx6ull";
+};
+
+&iomuxc_snvs {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tamper_gpios>;
+
+ pinctrl_tamper_gpios: tampergpiosgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0
+ MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0
+ MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0
+ MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0
+ MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0
+ MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0
+ MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0
+ MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0b0b0
+ >;
+ };
+
+ pinctrl_usbotg2_vbus: usbotg2vbusgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
+ >;
+ };
+
+ pinctrl_w1: w1grp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0b0b0
+ >;
+ };
+};
--
2.21.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v2 3/3] dt-bindings: IDU-intc: Add support for edge-triggered interrupts
From: Mischa Jonker @ 2019-07-24 12:04 UTC (permalink / raw)
To: Alexey.Brodkin, Vineet.Gupta1, kstewart, tglx, robh+dt,
linux-snps-arc, linux-kernel, devicetree
Cc: Mischa Jonker
In-Reply-To: <20190724120436.8537-1-mischa.jonker@synopsys.com>
This updates the documentation for supporting an optional extra interrupt
cell to specify edge vs level triggered.
Signed-off-by: Mischa Jonker <mischa.jonker@synopsys.com>
---
.../interrupt-controller/snps,archs-idu-intc.txt | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt
index c5a1c7b..a5c1db9 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt
@@ -8,11 +8,20 @@ Properties:
- compatible: "snps,archs-idu-intc"
- interrupt-controller: This is an interrupt controller.
-- #interrupt-cells: Must be <1>.
-
- Value of the cell specifies the "common" IRQ from peripheral to IDU. Number N
- of the particular interrupt line of IDU corresponds to the line N+24 of the
- core interrupt controller.
+- #interrupt-cells: Must be <1> or <2>.
+
+ Value of the first cell specifies the "common" IRQ from peripheral to IDU.
+ Number N of the particular interrupt line of IDU corresponds to the line N+24
+ of the core interrupt controller.
+
+ The (optional) second cell specifies any of the following flags:
+ - bits[3:0] trigger type and level flags
+ 1 = low-to-high edge triggered
+ 2 = NOT SUPPORTED (high-to-low edge triggered)
+ 4 = active high level-sensitive <<< DEFAULT
+ 8 = NOT SUPPORTED (active low level-sensitive)
+ When no second cell is specified, the interrupt is assumed to be level
+ sensitive.
The interrupt controller is accessed via the special ARC AUX register
interface, hence "reg" property is not specified.
--
2.8.3
^ permalink raw reply related
* [PATCH v2 2/3] dt-bindings: IDU-intc: Clean up documentation
From: Mischa Jonker @ 2019-07-24 12:04 UTC (permalink / raw)
To: Alexey.Brodkin, Vineet.Gupta1, kstewart, tglx, robh+dt,
linux-snps-arc, linux-kernel, devicetree
Cc: Mischa Jonker
In-Reply-To: <20190724120436.8537-1-mischa.jonker@synopsys.com>
* Some lines exceeded 80 characters.
* Clarified statement about AUX register interface
Signed-off-by: Mischa Jonker <mischa.jonker@synopsys.com>
---
.../bindings/interrupt-controller/snps,archs-idu-intc.txt | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt
index 09fc02b..c5a1c7b 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/snps,archs-idu-intc.txt
@@ -1,7 +1,8 @@
* ARC-HS Interrupt Distribution Unit
- This optional 2nd level interrupt controller can be used in SMP configurations for
- dynamic IRQ routing, load balancing of common/external IRQs towards core intc.
+ This optional 2nd level interrupt controller can be used in SMP configurations
+ for dynamic IRQ routing, load balancing of common/external IRQs towards core
+ intc.
Properties:
@@ -13,8 +14,8 @@ Properties:
of the particular interrupt line of IDU corresponds to the line N+24 of the
core interrupt controller.
- intc accessed via the special ARC AUX register interface, hence "reg" property
- is not specified.
+ The interrupt controller is accessed via the special ARC AUX register
+ interface, hence "reg" property is not specified.
Example:
core_intc: core-interrupt-controller {
--
2.8.3
^ permalink raw reply related
* [PATCH v2 1/3] ARCv2: IDU-intc: Add support for edge-triggered interrupts
From: Mischa Jonker @ 2019-07-24 12:04 UTC (permalink / raw)
To: Alexey.Brodkin, Vineet.Gupta1, kstewart, tglx, robh+dt,
linux-snps-arc, linux-kernel, devicetree
Cc: Mischa Jonker
In-Reply-To: <CY4PR1201MB0120EDD4173511912A9FC99EA1C60@CYPR1201MB0120.namprd12.prod.outlook.com>
This adds support for an optional extra interrupt cell to specify edge
vs level triggered. It is backward compatible with dts files with only
one cell, and will default to level-triggered in such a case.
Note that I had to make a change to idu_irq_set_affinity as well, as
this function was setting the interrupt type to "level" unconditionally,
since this was the only type supported previously.
Signed-off-by: Mischa Jonker <mischa.jonker@synopsys.com>
---
arch/arc/kernel/mcip.c | 60 +++++++++++++++++++++++++++++++++++++++++++++-----
include/soc/arc/mcip.h | 11 +++++++++
2 files changed, 65 insertions(+), 6 deletions(-)
diff --git a/arch/arc/kernel/mcip.c b/arch/arc/kernel/mcip.c
index 18b493d..abf9398 100644
--- a/arch/arc/kernel/mcip.c
+++ b/arch/arc/kernel/mcip.c
@@ -202,8 +202,8 @@ static void idu_set_dest(unsigned int cmn_irq, unsigned int cpu_mask)
__mcip_cmd_data(CMD_IDU_SET_DEST, cmn_irq, cpu_mask);
}
-static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl,
- unsigned int distr)
+static void idu_set_mode(unsigned int cmn_irq, bool set_lvl, unsigned int lvl,
+ bool set_distr, unsigned int distr)
{
union {
unsigned int word;
@@ -212,8 +212,11 @@ static void idu_set_mode(unsigned int cmn_irq, unsigned int lvl,
};
} data;
- data.distr = distr;
- data.lvl = lvl;
+ data.word = __mcip_cmd_read(CMD_IDU_READ_MODE, cmn_irq);
+ if (set_distr)
+ data.distr = distr;
+ if (set_lvl)
+ data.lvl = lvl;
__mcip_cmd_data(CMD_IDU_SET_MODE, cmn_irq, data.word);
}
@@ -240,6 +243,25 @@ static void idu_irq_unmask(struct irq_data *data)
raw_spin_unlock_irqrestore(&mcip_lock, flags);
}
+static void idu_irq_ack(struct irq_data *data)
+{
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&mcip_lock, flags);
+ __mcip_cmd(CMD_IDU_ACK_CIRQ, data->hwirq);
+ raw_spin_unlock_irqrestore(&mcip_lock, flags);
+}
+
+static void idu_irq_mask_ack(struct irq_data *data)
+{
+ unsigned long flags;
+
+ raw_spin_lock_irqsave(&mcip_lock, flags);
+ __mcip_cmd_data(CMD_IDU_SET_MASK, data->hwirq, 1);
+ __mcip_cmd(CMD_IDU_ACK_CIRQ, data->hwirq);
+ raw_spin_unlock_irqrestore(&mcip_lock, flags);
+}
+
static int
idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask,
bool force)
@@ -263,13 +285,36 @@ idu_irq_set_affinity(struct irq_data *data, const struct cpumask *cpumask,
else
distribution_mode = IDU_M_DISTRI_RR;
- idu_set_mode(data->hwirq, IDU_M_TRIG_LEVEL, distribution_mode);
+ idu_set_mode(data->hwirq, false, 0, true, distribution_mode);
raw_spin_unlock_irqrestore(&mcip_lock, flags);
return IRQ_SET_MASK_OK;
}
+static int idu_irq_set_type(struct irq_data *data, u32 type)
+{
+ unsigned long flags;
+
+ /*
+ * ARCv2 IDU HW does not support inverse polarity, so these are the
+ * only interrupt types supported.
+ */
+ if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH))
+ return -EINVAL;
+
+ raw_spin_lock_irqsave(&mcip_lock, flags);
+
+ idu_set_mode(data->hwirq, true,
+ type & IRQ_TYPE_EDGE_RISING ? IDU_M_TRIG_EDGE :
+ IDU_M_TRIG_LEVEL,
+ false, 0);
+
+ raw_spin_unlock_irqrestore(&mcip_lock, flags);
+
+ return 0;
+}
+
static void idu_irq_enable(struct irq_data *data)
{
/*
@@ -289,7 +334,10 @@ static struct irq_chip idu_irq_chip = {
.name = "MCIP IDU Intc",
.irq_mask = idu_irq_mask,
.irq_unmask = idu_irq_unmask,
+ .irq_ack = idu_irq_ack,
+ .irq_mask_ack = idu_irq_mask_ack,
.irq_enable = idu_irq_enable,
+ .irq_set_type = idu_irq_set_type,
#ifdef CONFIG_SMP
.irq_set_affinity = idu_irq_set_affinity,
#endif
@@ -317,7 +365,7 @@ static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t
}
static const struct irq_domain_ops idu_irq_ops = {
- .xlate = irq_domain_xlate_onecell,
+ .xlate = irq_domain_xlate_onetwocell,
.map = idu_irq_map,
};
diff --git a/include/soc/arc/mcip.h b/include/soc/arc/mcip.h
index 50f49e0..d1a93c7 100644
--- a/include/soc/arc/mcip.h
+++ b/include/soc/arc/mcip.h
@@ -46,7 +46,9 @@ struct mcip_cmd {
#define CMD_IDU_ENABLE 0x71
#define CMD_IDU_DISABLE 0x72
#define CMD_IDU_SET_MODE 0x74
+#define CMD_IDU_READ_MODE 0x75
#define CMD_IDU_SET_DEST 0x76
+#define CMD_IDU_ACK_CIRQ 0x79
#define CMD_IDU_SET_MASK 0x7C
#define IDU_M_TRIG_LEVEL 0x0
@@ -119,4 +121,13 @@ static inline void __mcip_cmd_data(unsigned int cmd, unsigned int param,
__mcip_cmd(cmd, param);
}
+/*
+ * Read MCIP register
+ */
+static inline unsigned int __mcip_cmd_read(unsigned int cmd, unsigned int param)
+{
+ __mcip_cmd(cmd, param);
+ return read_aux_reg(ARC_REG_MCIP_READBACK);
+}
+
#endif
--
2.8.3
^ permalink raw reply related
* [PATCH] dt-bindings: shdma: Rename bindings documentation file
From: Simon Horman @ 2019-07-24 11:49 UTC (permalink / raw)
To: Vinod Koul
Cc: Rob Herring, Mark Rutland, Geert Uytterhoeven, Magnus Damm,
dmaengine, devicetree, linux-renesas-soc, Simon Horman
Rename the bindings documentation file for shdma
from shdma.txt to renesas,shdma.txt.
This is part of an ongoing effort to name bindings documentation files for
Renesas IP blocks consistently, in line with the compat strings they
document.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
Based on v5.3-rc1
---
Documentation/devicetree/bindings/dma/{shdma.txt => renesas,shdma.txt} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/dma/{shdma.txt => renesas,shdma.txt} (100%)
diff --git a/Documentation/devicetree/bindings/dma/shdma.txt b/Documentation/devicetree/bindings/dma/renesas,shdma.txt
similarity index 100%
rename from Documentation/devicetree/bindings/dma/shdma.txt
rename to Documentation/devicetree/bindings/dma/renesas,shdma.txt
--
2.11.0
^ permalink raw reply
* Re: [PATCH v12 3/9] drivers: memory: extend of_memory by LPDDR3 support
From: Krzysztof Kozlowski @ 2019-07-24 11:39 UTC (permalink / raw)
To: Lukasz Luba
Cc: devicetree, linux-kernel, linux-pm,
linux-samsung-soc@vger.kernel.org, linux-clk, mturquette, sboyd,
Bartłomiej Żołnierkiewicz, kgene, mark.rutland,
robh+dt, Chanwoo Choi, kyungmin.park, Marek Szyprowski,
s.nawrocki, myungjoo.ham, keescook, tony, jroedel, treding,
digetx, gregkh, willy.mh.wolff.ml
In-Reply-To: <20190722094646.13342-4-l.luba@partner.samsung.com>
On Mon, 22 Jul 2019 at 11:47, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> The patch adds AC timings information needed to support LPDDR3 and memory
> controllers. The structure is used in of_memory and currently in Exynos
> 5422 DMC. Add parsing data needed for LPDDR3 support.
> It is currently used in Exynos5422 Dynamic Memory Controller.
>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
> drivers/memory/jedec_ddr.h | 61 +++++++++++++++
> drivers/memory/of_memory.c | 154 +++++++++++++++++++++++++++++++++++++
> drivers/memory/of_memory.h | 18 +++++
> 3 files changed, 233 insertions(+)
>
> diff --git a/drivers/memory/jedec_ddr.h b/drivers/memory/jedec_ddr.h
> index 4a21b5044ff8..38e26d461bdb 100644
> --- a/drivers/memory/jedec_ddr.h
> +++ b/drivers/memory/jedec_ddr.h
> @@ -29,6 +29,7 @@
> #define DDR_TYPE_LPDDR2_S4 3
> #define DDR_TYPE_LPDDR2_S2 4
> #define DDR_TYPE_LPDDR2_NVM 5
> +#define DDR_TYPE_LPDDR3 6
>
> /* DDR IO width */
> #define DDR_IO_WIDTH_4 1
> @@ -169,4 +170,64 @@ extern const struct lpddr2_timings
> lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES];
> extern const struct lpddr2_min_tck lpddr2_jedec_min_tck;
>
> +/*
> + * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields.
> + * All parameters are in pico seconds(ps) unless explicitly indicated
> + * with a suffix like tRAS_max_ns below
> + */
> +struct lpddr3_timings {
> + u32 max_freq;
> + u32 min_freq;
> + u32 tRFC;
> + u32 tRRD;
> + u32 tRPab;
> + u32 tRPpb;
> + u32 tRCD;
> + u32 tRC;
> + u32 tRAS;
> + u32 tWTR;
> + u32 tWR;
> + u32 tRTP;
> + u32 tW2W_C2C;
> + u32 tR2R_C2C;
> + u32 tWL;
> + u32 tDQSCK;
> + u32 tRL;
> + u32 tFAW;
> + u32 tXSR;
> + u32 tXP;
> + u32 tCKE;
> + u32 tCKESR;
> + u32 tMRD;
> +};
> +
> +/*
> + * Min value for some parameters in terms of number of tCK cycles(nCK)
> + * Please set to zero parameters that are not valid for a given memory
> + * type
> + */
> +struct lpddr3_min_tck {
> + u32 tRFC;
> + u32 tRRD;
> + u32 tRPab;
> + u32 tRPpb;
> + u32 tRCD;
> + u32 tRC;
> + u32 tRAS;
> + u32 tWTR;
> + u32 tWR;
> + u32 tRTP;
> + u32 tW2W_C2C;
> + u32 tR2R_C2C;
> + u32 tWL;
> + u32 tDQSCK;
> + u32 tRL;
> + u32 tFAW;
> + u32 tXSR;
> + u32 tXP;
> + u32 tCKE;
> + u32 tCKESR;
> + u32 tMRD;
> +};
> +
> #endif /* __JEDEC_DDR_H */
> diff --git a/drivers/memory/of_memory.c b/drivers/memory/of_memory.c
> index 46539b27a3fb..4f5b8c81669f 100644
> --- a/drivers/memory/of_memory.c
> +++ b/drivers/memory/of_memory.c
> @@ -3,6 +3,12 @@
> * OpenFirmware helpers for memory drivers
> *
> * Copyright (C) 2012 Texas Instruments, Inc.
> + * Copyright (C) 2019 Samsung Electronics Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
What's this?
Please, get a independent review or ack for this patch.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v12 3/9] drivers: memory: extend of_memory by LPDDR3 support
From: Krzysztof Kozlowski @ 2019-07-24 11:31 UTC (permalink / raw)
To: Lukasz Luba
Cc: devicetree, linux-kernel, linux-pm,
linux-samsung-soc@vger.kernel.org, linux-clk, mturquette, sboyd,
Bartłomiej Żołnierkiewicz, kgene, mark.rutland,
robh+dt, Chanwoo Choi, kyungmin.park, Marek Szyprowski,
s.nawrocki, myungjoo.ham, keescook, tony, jroedel, treding,
digetx, gregkh, willy.mh.wolff.ml
In-Reply-To: <20190722094646.13342-4-l.luba@partner.samsung.com>
On Mon, 22 Jul 2019 at 11:47, Lukasz Luba <l.luba@partner.samsung.com> wrote:
>
> The patch adds AC timings information needed to support LPDDR3 and memory
> controllers. The structure is used in of_memory and currently in Exynos
> 5422 DMC. Add parsing data needed for LPDDR3 support.
> It is currently used in Exynos5422 Dynamic Memory Controller.
>
> Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
> Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
> ---
> drivers/memory/jedec_ddr.h | 61 +++++++++++++++
> drivers/memory/of_memory.c | 154 +++++++++++++++++++++++++++++++++++++
> drivers/memory/of_memory.h | 18 +++++
> 3 files changed, 233 insertions(+)
>
> diff --git a/drivers/memory/jedec_ddr.h b/drivers/memory/jedec_ddr.h
> index 4a21b5044ff8..38e26d461bdb 100644
> --- a/drivers/memory/jedec_ddr.h
> +++ b/drivers/memory/jedec_ddr.h
> @@ -29,6 +29,7 @@
> #define DDR_TYPE_LPDDR2_S4 3
> #define DDR_TYPE_LPDDR2_S2 4
> #define DDR_TYPE_LPDDR2_NVM 5
> +#define DDR_TYPE_LPDDR3 6
>
> /* DDR IO width */
> #define DDR_IO_WIDTH_4 1
> @@ -169,4 +170,64 @@ extern const struct lpddr2_timings
> lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES];
> extern const struct lpddr2_min_tck lpddr2_jedec_min_tck;
>
> +/*
> + * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields.
> + * All parameters are in pico seconds(ps) unless explicitly indicated
> + * with a suffix like tRAS_max_ns below
To which tRAS_max_ns are you referring?
> + */
> +struct lpddr3_timings {
> + u32 max_freq;
> + u32 min_freq;
> + u32 tRFC;
> + u32 tRRD;
> + u32 tRPab;
> + u32 tRPpb;
> + u32 tRCD;
> + u32 tRC;
> + u32 tRAS;
> + u32 tWTR;
> + u32 tWR;
> + u32 tRTP;
> + u32 tW2W_C2C;
> + u32 tR2R_C2C;
> + u32 tWL;
> + u32 tDQSCK;
> + u32 tRL;
> + u32 tFAW;
> + u32 tXSR;
> + u32 tXP;
> + u32 tCKE;
> + u32 tCKESR;
> + u32 tMRD;
> +};
> +
> +/*
> + * Min value for some parameters in terms of number of tCK cycles(nCK)
> + * Please set to zero parameters that are not valid for a given memory
> + * type
> + */
> +struct lpddr3_min_tck {
> + u32 tRFC;
> + u32 tRRD;
> + u32 tRPab;
> + u32 tRPpb;
> + u32 tRCD;
> + u32 tRC;
> + u32 tRAS;
> + u32 tWTR;
> + u32 tWR;
> + u32 tRTP;
> + u32 tW2W_C2C;
> + u32 tR2R_C2C;
> + u32 tWL;
> + u32 tDQSCK;
> + u32 tRL;
> + u32 tFAW;
> + u32 tXSR;
> + u32 tXP;
> + u32 tCKE;
> + u32 tCKESR;
> + u32 tMRD;
> +};
> +
> #endif /* __JEDEC_DDR_H */
> diff --git a/drivers/memory/of_memory.c b/drivers/memory/of_memory.c
> index 46539b27a3fb..4f5b8c81669f 100644
> --- a/drivers/memory/of_memory.c
> +++ b/drivers/memory/of_memory.c
> @@ -3,6 +3,12 @@
> * OpenFirmware helpers for memory drivers
> *
> * Copyright (C) 2012 Texas Instruments, Inc.
> + * Copyright (C) 2019 Samsung Electronics Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> */
>
> #include <linux/device.h>
> @@ -149,3 +155,151 @@ const struct lpddr2_timings *of_get_ddr_timings(struct device_node *np_ddr,
> return lpddr2_jedec_timings;
> }
> EXPORT_SYMBOL(of_get_ddr_timings);
> +
> +/**
> + * of_lpddr3_get_min_tck() - extract min timing values for lpddr3
> + * @np: pointer to ddr device tree node
> + * @device: device requesting for min timing values
> + *
> + * Populates the lpddr3_min_tck structure by extracting data
> + * from device tree node. Returns a pointer to the populated
> + * structure. If any error in populating the structure, returns NULL.
> + */
> +const struct lpddr3_min_tck *of_lpddr3_get_min_tck(struct device_node *np,
> + struct device *dev)
> +{
> + int ret = 0;
> + struct lpddr3_min_tck *min;
> +
> + min = devm_kzalloc(dev, sizeof(*min), GFP_KERNEL);
> + if (!min)
> + goto default_min_tck;
> +
> + ret |= of_property_read_u32(np, "tRFC-min-tck", &min->tRFC);
> + ret |= of_property_read_u32(np, "tRRD-min-tck", &min->tRRD);
> + ret |= of_property_read_u32(np, "tRPab-min-tck", &min->tRPab);
> + ret |= of_property_read_u32(np, "tRPpb-min-tck", &min->tRPpb);
> + ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD);
> + ret |= of_property_read_u32(np, "tRC-min-tck", &min->tRC);
> + ret |= of_property_read_u32(np, "tRAS-min-tck", &min->tRAS);
> + ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR);
> + ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR);
> + ret |= of_property_read_u32(np, "tRTP-min-tck", &min->tRTP);
> + ret |= of_property_read_u32(np, "tW2W-C2C-min-tck", &min->tW2W_C2C);
> + ret |= of_property_read_u32(np, "tR2R-C2C-min-tck", &min->tR2R_C2C);
> + ret |= of_property_read_u32(np, "tWL-min-tck", &min->tWL);
> + ret |= of_property_read_u32(np, "tDQSCK-min-tck", &min->tDQSCK);
> + ret |= of_property_read_u32(np, "tRL-min-tck", &min->tRL);
> + ret |= of_property_read_u32(np, "tFAW-min-tck", &min->tFAW);
> + ret |= of_property_read_u32(np, "tXSR-min-tck", &min->tXSR);
> + ret |= of_property_read_u32(np, "tXP-min-tck", &min->tXP);
> + ret |= of_property_read_u32(np, "tCKE-min-tck", &min->tCKE);
> + ret |= of_property_read_u32(np, "tCKESR-min-tck", &min->tCKESR);
> + ret |= of_property_read_u32(np, "tMRD-min-tck", &min->tMRD);
> +
> + if (ret) {
> + dev_warn(dev, "%s: errors while parsing min-tck values\n",
> + __func__);
> + devm_kfree(dev, min);
> + goto default_min_tck;
> + }
> +
> + return min;
> +
> +default_min_tck:
> + dev_warn(dev, "%s: using default min-tck values\n", __func__);
Here and later - you return NULL, not default values. Your driver -
consumer - also behaves like with error condition, not like with
default values. Print just that you cannot get timings, I guess.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: msm8998: Node ordering, address cleanups
From: Marc Gonzalez @ 2019-07-24 11:16 UTC (permalink / raw)
To: Jeffrey Hugo, Andy Gross, Bjorn Andersson
Cc: Rob Herring, Mark Rutland, MSM, DT, LKML
In-Reply-To: <20190722165823.21539-1-jeffrey.l.hugo@gmail.com>
On 22/07/2019 18:58, Jeffrey Hugo wrote:
> DT nodes should be ordered by address, then node name, and finally label.
> The msm8998 dtsi does not follow this, so clean it up by reordering the
> nodes. While we are at it, extend the addresses to be fully 32-bits wide
> so that ordering is easy to determine when adding new nodes. Also, two
> or so nodes had the wrong address value in their node name (did not match
> the reg property), so fix those up as well.
>
> Hopefully going forward, things can be maintained so that a cleanup like
> this is not needed.
>
> Signed-off-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com>
> ---
> arch/arm64/boot/dts/qcom/msm8998.dtsi | 254 +++++++++++++-------------
> 1 file changed, 127 insertions(+), 127 deletions(-)
LGTM.
Reviewed-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Rob, Mark: when there are multiple reg properties, why is the convention
to use the *first* address in the node's name, rather than the lowest
address?
e.g.
spmi_bus: spmi@800f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0800f000 0x1000>,
<0x08400000 0x1000000>,
<0x09400000 0x1000000>,
<0x0a400000 0x220000>,
<0x0800a000 0x3000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
"spmi@800f000" instead of "spmi@800a000"
Especially, since the reg props could be in any order here, given the
lookup by name.
Regards.
^ permalink raw reply
* Re: [PATCH 7/7] clocksource/drivers/sh_cmt: Document "cmt-48" as deprecated
From: Simon Horman @ 2019-07-24 11:13 UTC (permalink / raw)
To: Magnus Damm
Cc: linux-kernel, mark.rutland, devicetree, geert+renesas,
daniel.lezcano, linux-renesas-soc, robh+dt, tglx
In-Reply-To: <156345033835.5307.9206628986166423962.sendpatchset@octo>
On Thu, Jul 18, 2019 at 08:45:38PM +0900, Magnus Damm wrote:
> From: Magnus Damm <damm+renesas@opensource.se>
>
> Update the CMT driver to mark "renesas,cmt-48" as deprecated.
>
> Instead of documenting a theoretical hardware device based on current software
> support level, define DT bindings top-down based on available data sheet
> information and make use of part numbers in the DT compat string.
>
> In case of the only in-tree users r8a7740 and sh73a0 the compat strings
> "renesas,r8a7740-cmt1" and "renesas,sh73a0-cmt1" may be used instead.
>
> Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply
* Re: [PATCH 5/7] dt-bindings: timer: renesas, cmt: Update R-Car Gen3 CMT1 usage
From: Simon Horman @ 2019-07-24 11:13 UTC (permalink / raw)
To: Magnus Damm
Cc: linux-kernel, mark.rutland, devicetree, geert+renesas,
daniel.lezcano, linux-renesas-soc, robh+dt, tglx
In-Reply-To: <156345031152.5307.4388075759256453367.sendpatchset@octo>
On Thu, Jul 18, 2019 at 08:45:11PM +0900, Magnus Damm wrote:
> From: Magnus Damm <damm+renesas@opensource.se>
>
> The R-Car Gen3 SoCs so far come with a total for 4 on-chip CMT devices:
> - CMT0
> - CMT1
> - CMT2
> - CMT3
>
> CMT0 includes two rather basic 32-bit timer channels. The rest of the on-chip
> CMT devices support 48-bit counters and have 8 channels each.
>
> Based on the data sheet information "CMT2/3 are exactly same as CMT1"
> it seems that CMT2 and CMT3 now use the CMT1 compat string in the DTSI.
>
> Clarify this in the DT binding documentation by describing R-Car Gen3 and
> RZ/G2 CMT1 as "48-bit CMT devices".
>
> Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply
* Re: [PATCH 4/7] dt-bindings: timer: renesas, cmt: Add CMT0 and CMT1 to r8a77995
From: Simon Horman @ 2019-07-24 11:13 UTC (permalink / raw)
To: Magnus Damm
Cc: linux-kernel, mark.rutland, devicetree, geert+renesas,
daniel.lezcano, linux-renesas-soc, robh+dt, tglx
In-Reply-To: <156345029298.5307.13303613183227788698.sendpatchset@octo>
On Thu, Jul 18, 2019 at 08:44:53PM +0900, Magnus Damm wrote:
> From: Magnus Damm <damm+renesas@opensource.se>
>
> This patch adds DT binding documentation for the CMT devices on
> the R-Car Gen3 D3 (r8a77995) SoC.
>
> Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply
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