* Re: [PATCH v3] arm64: dts: imx8mq: Init rates and parents configs for clocks
From: Angus Ainslie @ 2019-07-28 14:53 UTC (permalink / raw)
To: Daniel Baluta
Cc: shawnguo, s.hauer, festevam, linux-imx, l.stach, ccaione,
abel.vesa, baruch, andrew.smirnov, devicetree, linux-arm-kernel,
linux-kernel, shengjiu.wang, agx, Anson.Huang, linux-kernel-owner
In-Reply-To: <20190728141218.12702-1-daniel.baluta@nxp.com>
Hi Daniel,
On 2019-07-28 07:12, Daniel Baluta wrote:
> From: Abel Vesa <abel.vesa@nxp.com>
>
> Add the initial configuration for clocks that need default parent and
> rate
> setting. This is based on the vendor tree clock provider parents and
> rates
> configuration except this is doing the setup in dts rather then using
> clock
> consumer API in a clock provider driver.
>
> Note that by adding the initial rate setting for audio_pll1/audio_pll
> setting we need to remove it from imx8mq-librem5-devkit.dts
> imx8mq-librem5-devkit.dts
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
This works with our board. One small nit below
Tested-by: Angus Ainslie (Purism) <angus@akkea.ca>
> ---
> Changes since v2:
> - set rate for audio_pll1/audio_pll2 in the dtsi file and
> remove the setting from imx8mq-librem5-devkit.dts
>
> .../dts/freescale/imx8mq-librem5-devkit.dts | 5 -----
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 21 +++++++++++++++++++
> 2 files changed, 21 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
> b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
> index 683a11035643..c702ccc82867 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
> @@ -169,11 +169,6 @@
> };
> };
>
> -&clk {
> - assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
> - assigned-clock-rates = <786432000>, <722534400>;
> -};
> -
> &dphy {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 02fbd0625318..c67625a881a4 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -494,6 +494,27 @@
> clock-names = "ckil", "osc_25m", "osc_27m",
> "clk_ext1", "clk_ext2",
> "clk_ext3", "clk_ext4";
> + assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1>,
> + <&clk IMX8MQ_AUDIO_PLL1>,
> + <&clk IMX8MQ_AUDIO_PLL2>,
> + <&clk IMX8MQ_CLK_AHB>,
> + <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
> + <&clk IMX8MQ_CLK_AUDIO_AHB>,
> + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
> + <&clk IMX8MQ_CLK_NOC>;
> + assigned-clock-parents = <0>,
> + <0>,
> + <0>,
> + <&clk IMX8MQ_SYS1_PLL_133M>,
> + <&clk IMX8MQ_SYS1_PLL_266M>,
> + <&clk IMX8MQ_SYS2_PLL_500M>,
> + <&clk IMX8MQ_CLK_27M>,
> + <&clk IMX8MQ_SYS1_PLL_800M>;
> + assigned-clock-rates = <593999999>,
> + <786432000>,
> + <722534400>;
> +
> +
Extra whitespace
Angus
> };
>
> src: reset-controller@30390000 {
^ permalink raw reply
* [PATCH] ARM: dts: sun8i: a83t: Enable HDMI output on Cubietruck Plus
From: Chen-Yu Tsai @ 2019-07-28 14:59 UTC (permalink / raw)
To: Maxime Ripard; +Cc: devicetree, Chen-Yu Tsai, linux-kernel, linux-arm-kernel
From: Chen-Yu Tsai <wens@csie.org>
The Cubietruck Plus has an HDMI connector tied to the HDMI output of the
SoC.
Enables display output via HDMI on the Cubietruck Plus. The connector
device node is named "hdmi-connector" as there is also a display port
connector, which is tied to the MIPI DSI output of the SoC through a
MIPI-DSI-to-DP bridge. This part is not supported yet.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
.../boot/dts/sun8i-a83t-cubietruck-plus.dts | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
index ea299d3d84d0..fb928503ad45 100644
--- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
@@ -60,6 +60,17 @@
stdout-path = "serial0:115200n8";
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -153,6 +164,10 @@
cpu-supply = <®_dcdc3>;
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
/* GL830 USB-to-SATA bridge here */
status = "okay";
@@ -172,6 +187,16 @@
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&mdio {
rgmii_phy: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
--
2.20.1
^ permalink raw reply related
* [PATCH v4] arm64: dts: imx8mq: Init rates and parents configs for clocks
From: Daniel Baluta @ 2019-07-28 15:20 UTC (permalink / raw)
To: shawnguo
Cc: s.hauer, festevam, linux-imx, l.stach, ccaione, abel.vesa, baruch,
andrew.smirnov, devicetree, linux-arm-kernel, linux-kernel,
shengjiu.wang, angus, agx, Anson.Huang, Daniel Baluta
From: Abel Vesa <abel.vesa@nxp.com>
Add the initial configuration for clocks that need default parent and rate
setting. This is based on the vendor tree clock provider parents and rates
configuration except this is doing the setup in dts rather then using clock
consumer API in a clock provider driver.
Note that by adding the initial rate setting for audio_pll1/audio_pll
setting we need to remove it from imx8mq-librem5-devkit.dts
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Tested-by: Angus Ainslie (Purism) <angus@akkea.ca>
---
Changes since v3:
- fix extra new lines
.../dts/freescale/imx8mq-librem5-devkit.dts | 5 -----
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 19 +++++++++++++++++++
2 files changed, 19 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
index 683a11035643..c702ccc82867 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
@@ -169,11 +169,6 @@
};
};
-&clk {
- assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
- assigned-clock-rates = <786432000>, <722534400>;
-};
-
&dphy {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 02fbd0625318..a55d72ba2e05 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -494,6 +494,25 @@
clock-names = "ckil", "osc_25m", "osc_27m",
"clk_ext1", "clk_ext2",
"clk_ext3", "clk_ext4";
+ assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1>,
+ <&clk IMX8MQ_AUDIO_PLL1>,
+ <&clk IMX8MQ_AUDIO_PLL2>,
+ <&clk IMX8MQ_CLK_AHB>,
+ <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
+ <&clk IMX8MQ_CLK_AUDIO_AHB>,
+ <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
+ <&clk IMX8MQ_CLK_NOC>;
+ assigned-clock-parents = <0>,
+ <0>,
+ <0>,
+ <&clk IMX8MQ_SYS1_PLL_133M>,
+ <&clk IMX8MQ_SYS1_PLL_266M>,
+ <&clk IMX8MQ_SYS2_PLL_500M>,
+ <&clk IMX8MQ_CLK_27M>,
+ <&clk IMX8MQ_SYS1_PLL_800M>;
+ assigned-clock-rates = <593999999>,
+ <786432000>,
+ <722534400>;
};
src: reset-controller@30390000 {
--
2.17.1
^ permalink raw reply related
* Re: [PATCH v2] arm64: dts: imx8mq: Init rates and parents configs for clocks
From: Daniel Baluta @ 2019-07-28 15:24 UTC (permalink / raw)
To: Abel Vesa
Cc: Mark Rutland, Rob Herring, Devicetree List,
Linux Kernel Mailing List, NXP Linux Team, Sascha Hauer,
Leonard Crestez, Shawn Guo, linux-arm-kernel, Lucas Stach
In-Reply-To: <CAEnQRZBK7EYVhbGpFeC79HxU=h0OcXU_SSeaMWbp+Qk=rf=14g@mail.gmail.com>
On Wed, Jul 3, 2019 at 4:05 PM Daniel Baluta <daniel.baluta@gmail.com> wrote:
>
> On Wed, Jul 3, 2019 at 3:03 PM Abel Vesa <abel.vesa@nxp.com> wrote:
> >
> > Add the initial configuration for clocks that need default parent and rate
> > setting. This is based on the vendor tree clock provider parents and rates
> > configuration except this is doing the setup in dts rather then using clock
> > consumer API in a clock provider driver.
> >
> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
>
> For audio related clock:
> Acked-by: Daniel Baluta <daniel.baluta@nxp.com>
Shawn,
Please ignore this patch. I've added some improvements.
New patch is:
[PATCH v4] arm64: dts: imx8mq: Init rates and parents configs for clocks
^ permalink raw reply
* Re: [PATCH 5/6] clk: imx8mq: Remove CLK_IS_CRITICAL flag for IMX8MQ_CLK_TMU_ROOT
From: Fabio Estevam @ 2019-07-28 15:24 UTC (permalink / raw)
To: Guido Günther
Cc: Daniel Baluta, Anson Huang, Mark Rutland, Carlo Caione,
Angus Ainslie (Purism), Leonard Crestez, linux-clk, Abel Vesa,
Andrey Smirnov, Daniel Lezcano, dl-linux-imx, rui.zhang,
Michael Turquette, Devicetree List, linux-pm, Sascha Hauer,
Eduardo Valentin, Rob Herring, linux-arm-kernel, Ste
In-Reply-To: <20190728075858.GA15144@bogon.m.sigxcpu.org>
Hi Guido,
On Sun, Jul 28, 2019 at 4:59 AM Guido Günther <agx@sigxcpu.org> wrote:
> Yes, this fixes it for me, thanks!
Thanks for testing it.
I will send a formal patch tomorrow.
Regards,
Fabio Estevam
^ permalink raw reply
* Re: [PATCH v3] arm64: dts: imx8mq: Init rates and parents configs for clocks
From: Daniel Baluta @ 2019-07-28 15:25 UTC (permalink / raw)
To: Angus Ainslie
Cc: Daniel Baluta, Shawn Guo, Sascha Hauer, Fabio Estevam,
dl-linux-imx, Lucas Stach, Carlo Caione, Abel Vesa, baruch,
Andrey Smirnov, Devicetree List, linux-arm-kernel,
Linux Kernel Mailing List, S.j. Wang, Guido Günther,
Anson Huang, linux-kernel-owner
In-Reply-To: <b6506f6579f823e4c1e26ef3a7d1eed2@akkea.ca>
On Sun, Jul 28, 2019 at 5:53 PM Angus Ainslie <angus@akkea.ca> wrote:
>
> Hi Daniel,
>
> On 2019-07-28 07:12, Daniel Baluta wrote:
> > From: Abel Vesa <abel.vesa@nxp.com>
> >
> > Add the initial configuration for clocks that need default parent and
> > rate
> > setting. This is based on the vendor tree clock provider parents and
> > rates
> > configuration except this is doing the setup in dts rather then using
> > clock
> > consumer API in a clock provider driver.
> >
> > Note that by adding the initial rate setting for audio_pll1/audio_pll
> > setting we need to remove it from imx8mq-librem5-devkit.dts
> > imx8mq-librem5-devkit.dts
> >
> > Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> > Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
>
> This works with our board. One small nit below
>
> Tested-by: Angus Ainslie (Purism) <angus@akkea.ca>
>
> > ---
> > Changes since v2:
> > - set rate for audio_pll1/audio_pll2 in the dtsi file and
> > remove the setting from imx8mq-librem5-devkit.dts
> >
> > .../dts/freescale/imx8mq-librem5-devkit.dts | 5 -----
> > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 21 +++++++++++++++++++
> > 2 files changed, 21 insertions(+), 5 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
> > b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
> > index 683a11035643..c702ccc82867 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
> > @@ -169,11 +169,6 @@
> > };
> > };
> >
> > -&clk {
> > - assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
> > - assigned-clock-rates = <786432000>, <722534400>;
> > -};
> > -
> > &dphy {
> > status = "okay";
> > };
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > index 02fbd0625318..c67625a881a4 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > @@ -494,6 +494,27 @@
> > clock-names = "ckil", "osc_25m", "osc_27m",
> > "clk_ext1", "clk_ext2",
> > "clk_ext3", "clk_ext4";
> > + assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1>,
> > + <&clk IMX8MQ_AUDIO_PLL1>,
> > + <&clk IMX8MQ_AUDIO_PLL2>,
> > + <&clk IMX8MQ_CLK_AHB>,
> > + <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
> > + <&clk IMX8MQ_CLK_AUDIO_AHB>,
> > + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
> > + <&clk IMX8MQ_CLK_NOC>;
> > + assigned-clock-parents = <0>,
> > + <0>,
> > + <0>,
> > + <&clk IMX8MQ_SYS1_PLL_133M>,
> > + <&clk IMX8MQ_SYS1_PLL_266M>,
> > + <&clk IMX8MQ_SYS2_PLL_500M>,
> > + <&clk IMX8MQ_CLK_27M>,
> > + <&clk IMX8MQ_SYS1_PLL_800M>;
> > + assigned-clock-rates = <593999999>,
> > + <786432000>,
> > + <722534400>;
> > +
> > +
>
> Extra whitespace
Thanks Angus for testing. Fixed in v4.
^ permalink raw reply
* Add Ingenic JZ4760 and X1000 and X1500 irqchip support v4.
From: Zhou Yanjie @ 2019-07-28 17:34 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, devicetree, robh+dt, paul.burton, tglx,
mark.rutland, jason, marc.zyngier
In-Reply-To: <1548517123-60058-1-git-send-email-zhouyanjie@zoho.com>
v1->v2: Replace "__fls(pending)" with "bit" in function "generic_handle_irq".
v2->v3: Add support for probing irq-ingenic driver on JZ4760 and X1500 Soc.
v3->v4: Combined with patches 5 and 7, combined with patches 4, 6 and 8.
^ permalink raw reply
* [PATCH 1/4 v4] irqchip: Ingenic: Change interrupt handling form cascade to chained_irq.
From: Zhou Yanjie @ 2019-07-28 17:34 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, devicetree, robh+dt, paul.burton, tglx,
mark.rutland, jason, marc.zyngier
In-Reply-To: <1564335273-22931-1-git-send-email-zhouyanjie@zoho.com>
The interrupt handling method is changed from old-style cascade to
chained_irq which is more appropriate. Also, it can process the
corner situation that more than one irq is coming to a single
chip at the same time.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
drivers/irqchip/irq-ingenic.c | 37 +++++++++++++++++++++++--------------
1 file changed, 23 insertions(+), 14 deletions(-)
diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index f126255..49f7685 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
- * JZ4740 platform IRQ support
+ * Ingenic XBurst platform IRQ support
*/
#include <linux/errno.h>
@@ -10,6 +10,7 @@
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
#include <linux/irqchip/ingenic.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
@@ -32,22 +33,34 @@ struct ingenic_intc_data {
#define JZ_REG_INTC_PENDING 0x10
#define CHIP_SIZE 0x20
-static irqreturn_t intc_cascade(int irq, void *data)
+static void ingenic_chained_handle_irq(struct irq_desc *desc)
{
- struct ingenic_intc_data *intc = irq_get_handler_data(irq);
- uint32_t irq_reg;
+ struct ingenic_intc_data *intc = irq_desc_get_handler_data(desc);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ bool have_irq = false;
+ uint32_t pending;
unsigned i;
+ chained_irq_enter(chip, desc);
for (i = 0; i < intc->num_chips; i++) {
- irq_reg = readl(intc->base + (i * CHIP_SIZE) +
+ pending = readl(intc->base + (i * CHIP_SIZE) +
JZ_REG_INTC_PENDING);
- if (!irq_reg)
+ if (!pending)
continue;
- generic_handle_irq(__fls(irq_reg) + (i * 32) + JZ4740_IRQ_BASE);
+ have_irq = true;
+ while (pending) {
+ int bit = __fls(pending);
+
+ generic_handle_irq(bit + (i * 32) + JZ4740_IRQ_BASE);
+ pending &= ~BIT(bit);
+ }
}
- return IRQ_HANDLED;
+ if (!have_irq)
+ spurious_interrupt();
+
+ chained_irq_exit(chip, desc);
}
static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
@@ -70,11 +83,6 @@ void ingenic_intc_irq_resume(struct irq_data *data)
intc_irq_set_mask(gc, gc->mask_cache);
}
-static struct irqaction intc_cascade_action = {
- .handler = intc_cascade,
- .name = "SoC intc cascade interrupt",
-};
-
static int __init ingenic_intc_of_init(struct device_node *node,
unsigned num_chips)
{
@@ -139,7 +147,8 @@ static int __init ingenic_intc_of_init(struct device_node *node,
if (!domain)
pr_warn("unable to register IRQ domain\n");
- setup_irq(parent_irq, &intc_cascade_action);
+ irq_set_chained_handler_and_data(parent_irq,
+ ingenic_chained_handle_irq, intc);
return 0;
out_unmap_irq:
--
2.7.4
^ permalink raw reply related
* [PATCH 2/4 v4] irqchip: Ingenic: Unify the function name prefix to "ingenic_intc_".
From: Zhou Yanjie @ 2019-07-28 17:34 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, devicetree, robh+dt, paul.burton, tglx,
mark.rutland, jason, marc.zyngier
In-Reply-To: <1564335273-22931-1-git-send-email-zhouyanjie@zoho.com>
For the sake of uniform style, function "intc_irq_set_mask" is
changed to "ingenic_intc_intc_irq_set_mask".
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
drivers/irqchip/irq-ingenic.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 49f7685..8430f5a 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -63,7 +63,8 @@ static void ingenic_chained_handle_irq(struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
-static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
+static void ingenic_intc_irq_set_mask(struct irq_chip_generic *gc,
+ uint32_t mask)
{
struct irq_chip_regs *regs = &gc->chip_types->regs;
@@ -74,13 +75,13 @@ static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask)
void ingenic_intc_irq_suspend(struct irq_data *data)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
- intc_irq_set_mask(gc, gc->wake_active);
+ ingenic_intc_irq_set_mask(gc, gc->wake_active);
}
void ingenic_intc_irq_resume(struct irq_data *data)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
- intc_irq_set_mask(gc, gc->mask_cache);
+ ingenic_intc_irq_set_mask(gc, gc->mask_cache);
}
static int __init ingenic_intc_of_init(struct device_node *node,
--
2.7.4
^ permalink raw reply related
* [PATCH 3/4 v4] dt-bindings: interrupt-controller: Add new Ingenic Socs bindings.
From: Zhou Yanjie @ 2019-07-28 17:34 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, devicetree, robh+dt, paul.burton, tglx,
mark.rutland, jason, marc.zyngier
In-Reply-To: <1564335273-22931-1-git-send-email-zhouyanjie@zoho.com>
Add the interrupt-controller bindings for the JZ4760/JZ4760B and
the X1000/X1000E and the X1500 Socs from Ingenic.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
.../devicetree/bindings/interrupt-controller/ingenic,intc.txt | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
index d4373d0..a96e120 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
@@ -5,9 +5,14 @@ Required properties:
- compatible : should be "ingenic,<socname>-intc". Valid strings are:
ingenic,jz4740-intc
ingenic,jz4725b-intc
+ ingenic,jz4760-intc
+ ingenic,jz4760b-intc
ingenic,jz4770-intc
ingenic,jz4775-intc
ingenic,jz4780-intc
+ ingenic,x1000-intc
+ ingenic,x1000e-intc
+ ingenic,x1500-intc
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Specifies the number of cells needed to encode an
--
2.7.4
^ permalink raw reply related
* [PATCH 4/4 v4] irqchip: Ingenic: Add support for new Ingenic Socs.
From: Zhou Yanjie @ 2019-07-28 17:34 UTC (permalink / raw)
To: linux-mips
Cc: linux-kernel, devicetree, robh+dt, paul.burton, tglx,
mark.rutland, jason, marc.zyngier
In-Reply-To: <1564335273-22931-1-git-send-email-zhouyanjie@zoho.com>
Add support for probing the irq-ingenic driver on the JZ4760/JZ4760B
and the X1000/X1000E and the X1500 Socs from Ingenic.
Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
---
drivers/irqchip/irq-ingenic.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/irqchip/irq-ingenic.c b/drivers/irqchip/irq-ingenic.c
index 8430f5a..b72430c 100644
--- a/drivers/irqchip/irq-ingenic.c
+++ b/drivers/irqchip/irq-ingenic.c
@@ -173,6 +173,11 @@ static int __init intc_2chip_of_init(struct device_node *node,
{
return ingenic_intc_of_init(node, 2);
}
+IRQCHIP_DECLARE(jz4760_intc, "ingenic,jz4760-intc", intc_2chip_of_init);
+IRQCHIP_DECLARE(jz4760b_intc, "ingenic,jz4760b-intc", intc_2chip_of_init);
IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);
+IRQCHIP_DECLARE(x1000_intc, "ingenic,x1000-intc", intc_2chip_of_init);
+IRQCHIP_DECLARE(x1000e_intc, "ingenic,x1000e-intc", intc_2chip_of_init);
+IRQCHIP_DECLARE(x1500_intc, "ingenic,x1500-intc", intc_2chip_of_init);
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v3 3/8] dt-bindings: interrupt-controller: Add JZ4760 and JZ4760B bindings.
From: Zhou Yanjie @ 2019-07-28 17:39 UTC (permalink / raw)
To: Marc Zyngier
Cc: linux-mips, linux-kernel, devicetree, paul.burton, tglx, robh+dt,
mark.rutland, jason
In-Reply-To: <865znoor2n.wl-marc.zyngier@arm.com>
Hi Marc,
These patches has been combined in v4.
Thanks
On 2019年07月26日 21:36, Marc Zyngier wrote:
> On Mon, 15 Jul 2019 13:09:50 +0100,
> Zhou Yanjie <zhouyanjie@zoho.com> wrote:
>> Add the interrupt-controller bindings for the JZ4760 Soc and
>> the JZ4760B Soc from Ingenic.
>>
>> Signed-off-by: Zhou Yanjie <zhouyanjie@zoho.com>
>> ---
>> Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt | 2 ++
>> 1 file changed, 2 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
>> index d4373d0..fa1ad54 100644
>> --- a/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
>> +++ b/Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt
>> @@ -5,6 +5,8 @@ Required properties:
>> - compatible : should be "ingenic,<socname>-intc". Valid strings are:
>> ingenic,jz4740-intc
>> ingenic,jz4725b-intc
>> + ingenic,jz4760-intc
>> + ingenic,jz4760b-intc
>> ingenic,jz4770-intc
>> ingenic,jz4775-intc
>> ingenic,jz4780-intc
>> --
>> 2.7.4
>>
>>
> This should be combined with patches 5 and 7. I don't see the need for
> multiple patches. Same thing should happen with patches 4, 6 and 8.
>
> Thanks,
>
> M.
>
^ permalink raw reply
* Re: [PATCH v3 4/5] iio: imu: st_lsm6dsx: add support for accel/gyro unit of lsm9sd1
From: Lorenzo Bianconi @ 2019-07-28 17:52 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Martin Kepplinger, lorenzo.bianconi83, knaack.h, lars, pmeerw,
linux-iio, devicetree, linux-kernel
In-Reply-To: <20190728093414.5d3ca94d@archlinux>
[-- Attachment #1: Type: text/plain, Size: 3161 bytes --]
> On Sun, 28 Jul 2019 08:04:51 +0200
> Martin Kepplinger <martin.kepplinger@puri.sm> wrote:
>
> > On 27.07.19 19:48, Jonathan Cameron wrote:
> > > On Thu, 25 Jul 2019 07:31:31 +0200
> > > Martin Kepplinger <martin.kepplinger@puri.sm> wrote:
> > >
> > >> The LSM9DS1's accelerometer / gyroscope unit and it's magnetometer (separately
> > >> supported in iio/magnetometer/st_magn*) are located on a separate i2c addresses
> > >> on the bus.
> > >>
> > >> For the datasheet, see https://www.st.com/resource/en/datasheet/lsm9ds1.pdf
> > >>
> > >> Treat it just like the LSM6* devices and, despite it's name, hook it up
> > >> to the st_lsm6dsx driver, using it's basic functionality.
> > >>
> > >> Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm>
> > > I'm a little confused on this hardware.
> > >
> > > How does buffered output work if these are independently clocked?
> > >
> > > I took a quick look at the datasheet, and 'suspect' the answer is that
> > > it runs at the gyro frequencies if both are enable. Is that right?
> > >
> >
> > Thanks for reviewing, Jonathan,
> >
> > Correct. It says so in chapter 7.12. But that's a "problem" with all
> > these imu devices, not specific to this addition right?
> It's not a problem as such, but there is a related difference in this
> device to the others supported by this driver.
>
> The other parts seem to allow for independent data rate setting, with
> streaming to the buffer that isn't in 'lock step'. I.e you can get
>
> Ax_1, Ay_1, Az_1, Gx_1, Gy_1, Gz_1, Gx_2, Gy_2, Gz_2, Ax_2, Ay_2, Az_2, Gy_3...
correct
>
> That required us to split them up into two devices and means that, to fuse
> data from these two source, userspace has to do the harder job of
> aligning the two datasets.
>
> For this device, things are simpler in that you always a 'scan' that goes
> across both accelerometer and gyroscope channels. That allows us to
> represent it as a single IIO device with a single buffer.
>
> I'm not seeing any reference in the lsm9ds1 to the pattern registers
> that are used to handle difference in frequency for the other
> parts by letting us know what is actually present in each data set
> in the fifo.
>
> Now, that doesn't meant we can't still handle them separately given
> we already do that for other parts.
what about reusing st_lsm6dsx_read_fifo() for lsm6ds0/lsm9ds1 but setting hw->sip to:
- hw->sip = 1 (acc_sip = 1, gyro_sip = 0) when just the acc is enabled
- hw->sip = 2 (acc_sip = 1, gyro_sip = 1) when both devices are enabled
I guess it is just a matter of adding a 'bool fixed_pattern' in
st_lsm6dsx_settings. What do you think?
Regards,
Lorenzo
>
> Anyhow, is my understanding correct?
>
> Jonathan
>
> >
> > Sidenote: I thought about renaming things to "lsm6ds0" here just because
> > of the name and because the registers are (almost) the same as for my
> > lsm9ds1. But I'm not a fan of blindly doing that without being able to
> > test. When the current patchset looks good to you, let's keep it that way.
> >
> > martin
>
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^ permalink raw reply
* Re: [PATCH 0/4] crypto: add amlogic crypto offloader driver
From: Eric Biggers @ 2019-07-28 18:48 UTC (permalink / raw)
To: Corentin Labbe
Cc: davem, herbert, khilman, mark.rutland, robh+dt, devicetree,
linux-amlogic, linux-arm-kernel, linux-crypto, linux-kernel,
baylibre-upstreaming
In-Reply-To: <1564083776-20540-1-git-send-email-clabbe@baylibre.com>
Hi Corentin,
On Thu, Jul 25, 2019 at 07:42:52PM +0000, Corentin Labbe wrote:
> Hello
>
> This serie adds support for the crypto offloader present on amlogic GXL
> SoCs.
>
> Tested on meson-gxl-s905x-khadas-vim and meson-gxl-s905x-libretech-cc
>
> Regards
>
Does this new driver pass all the crypto self-tests?
Including with CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y?
- Eric
^ permalink raw reply
* [PATCH v2 0/7] Add support for new SAI IP version
From: Daniel Baluta @ 2019-07-28 19:24 UTC (permalink / raw)
To: broonie
Cc: l.stach, mihai.serban, alsa-devel, viorel.suman, timur,
shengjiu.wang, angus, tiwai, nicoleotsuka, linux-imx, kernel,
festevam, linux-kernel, devicetree, robh, Daniel Baluta
So far SAI IPs integrated with imx6 only supported one data line.
Starting with imx7 and imx8 SAI integration support up to 8 data
lines.
New SAI IP version introduces two new registers (Version and Parmeter
registers) which are placed at the beginning of register address space.
For this reason we need to fix the register's address.
Changes since v1:
- removed patches from Lucas as they were already accepted
- addressed comments from Lucas and Nicolin regarding
device tree property naming
- removed comment saying that "datalines" must be always
consecutively enabled (this is not true, checked with IP owner)
- added new patch to document newly introduced compatbile
strings
- removed patch introducing combined mode as I will still need
some time to figure out how to properly allow users to set it.
Nicolin,
Unfortunately I couldn't find any clean solution on handling registers
address shifts. As mentioned in patch 5/7 Tx/Rx data registers and
Tx/Rx FIFO registers keep their addresses while others are shifted
by 8 bytes.
Even if I could create two regmaps as suggested I will still need
to update each call of regmap_functions.
Daniel Baluta (7):
ASoC: fsl_sai: Add registers definition for multiple datalines
ASoC: fsl_sai: Update Tx/Rx channel enable mask
ASoC: fsl_sai: Add support to enable multiple data lines
ASoC: dt-bindings: Document dl-mask property
ASoC: fsl_sai: Add support for SAI new version
ASoC: fsl_sai: Add support for imx7ulp/imx8mq
ASoC: dt-bindings: Introduce compatible strings for 7ULP and 8MQ
.../devicetree/bindings/sound/fsl-sai.txt | 10 +-
sound/soc/fsl/fsl_sai.c | 331 ++++++++++++------
sound/soc/fsl/fsl_sai.h | 82 +++--
3 files changed, 293 insertions(+), 130 deletions(-)
--
2.17.1
^ permalink raw reply
* [PATCH v2 1/7] ASoC: fsl_sai: Add registers definition for multiple datalines
From: Daniel Baluta @ 2019-07-28 19:24 UTC (permalink / raw)
To: broonie
Cc: l.stach, mihai.serban, alsa-devel, viorel.suman, timur,
shengjiu.wang, angus, tiwai, nicoleotsuka, linux-imx, kernel,
festevam, linux-kernel, devicetree, robh, Daniel Baluta
In-Reply-To: <20190728192429.1514-1-daniel.baluta@nxp.com>
SAI IP supports up to 8 data lines. The configuration of
supported number of data lines is decided at SoC integration
time.
This patch adds definitions for all related data TX/RX registers:
* TDR0..7, Transmit data register
* TFR0..7, Transmit FIFO register
* RDR0..7, Receive data register
* RFR0..7, Receive FIFO register
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
---
sound/soc/fsl/fsl_sai.c | 76 +++++++++++++++++++++++++++++++++++------
sound/soc/fsl/fsl_sai.h | 36 ++++++++++++++++---
2 files changed, 98 insertions(+), 14 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 6d3c6c8d50ce..17b0aff4ee8b 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -685,7 +685,14 @@ static struct reg_default fsl_sai_reg_defaults[] = {
{FSL_SAI_TCR3, 0},
{FSL_SAI_TCR4, 0},
{FSL_SAI_TCR5, 0},
- {FSL_SAI_TDR, 0},
+ {FSL_SAI_TDR0, 0},
+ {FSL_SAI_TDR1, 0},
+ {FSL_SAI_TDR2, 0},
+ {FSL_SAI_TDR3, 0},
+ {FSL_SAI_TDR4, 0},
+ {FSL_SAI_TDR5, 0},
+ {FSL_SAI_TDR6, 0},
+ {FSL_SAI_TDR7, 0},
{FSL_SAI_TMR, 0},
{FSL_SAI_RCR1, 0},
{FSL_SAI_RCR2, 0},
@@ -704,7 +711,14 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
case FSL_SAI_TCR3:
case FSL_SAI_TCR4:
case FSL_SAI_TCR5:
- case FSL_SAI_TFR:
+ case FSL_SAI_TFR0:
+ case FSL_SAI_TFR1:
+ case FSL_SAI_TFR2:
+ case FSL_SAI_TFR3:
+ case FSL_SAI_TFR4:
+ case FSL_SAI_TFR5:
+ case FSL_SAI_TFR6:
+ case FSL_SAI_TFR7:
case FSL_SAI_TMR:
case FSL_SAI_RCSR:
case FSL_SAI_RCR1:
@@ -712,8 +726,22 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
case FSL_SAI_RCR3:
case FSL_SAI_RCR4:
case FSL_SAI_RCR5:
- case FSL_SAI_RDR:
- case FSL_SAI_RFR:
+ case FSL_SAI_RDR0:
+ case FSL_SAI_RDR1:
+ case FSL_SAI_RDR2:
+ case FSL_SAI_RDR3:
+ case FSL_SAI_RDR4:
+ case FSL_SAI_RDR5:
+ case FSL_SAI_RDR6:
+ case FSL_SAI_RDR7:
+ case FSL_SAI_RFR0:
+ case FSL_SAI_RFR1:
+ case FSL_SAI_RFR2:
+ case FSL_SAI_RFR3:
+ case FSL_SAI_RFR4:
+ case FSL_SAI_RFR5:
+ case FSL_SAI_RFR6:
+ case FSL_SAI_RFR7:
case FSL_SAI_RMR:
return true;
default:
@@ -726,9 +754,30 @@ static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
switch (reg) {
case FSL_SAI_TCSR:
case FSL_SAI_RCSR:
- case FSL_SAI_TFR:
- case FSL_SAI_RFR:
- case FSL_SAI_RDR:
+ case FSL_SAI_TFR0:
+ case FSL_SAI_TFR1:
+ case FSL_SAI_TFR2:
+ case FSL_SAI_TFR3:
+ case FSL_SAI_TFR4:
+ case FSL_SAI_TFR5:
+ case FSL_SAI_TFR6:
+ case FSL_SAI_TFR7:
+ case FSL_SAI_RFR0:
+ case FSL_SAI_RFR1:
+ case FSL_SAI_RFR2:
+ case FSL_SAI_RFR3:
+ case FSL_SAI_RFR4:
+ case FSL_SAI_RFR5:
+ case FSL_SAI_RFR6:
+ case FSL_SAI_RFR7:
+ case FSL_SAI_RDR0:
+ case FSL_SAI_RDR1:
+ case FSL_SAI_RDR2:
+ case FSL_SAI_RDR3:
+ case FSL_SAI_RDR4:
+ case FSL_SAI_RDR5:
+ case FSL_SAI_RDR6:
+ case FSL_SAI_RDR7:
return true;
default:
return false;
@@ -744,7 +793,14 @@ static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
case FSL_SAI_TCR3:
case FSL_SAI_TCR4:
case FSL_SAI_TCR5:
- case FSL_SAI_TDR:
+ case FSL_SAI_TDR0:
+ case FSL_SAI_TDR1:
+ case FSL_SAI_TDR2:
+ case FSL_SAI_TDR3:
+ case FSL_SAI_TDR4:
+ case FSL_SAI_TDR5:
+ case FSL_SAI_TDR6:
+ case FSL_SAI_TDR7:
case FSL_SAI_TMR:
case FSL_SAI_RCSR:
case FSL_SAI_RCR1:
@@ -885,8 +941,8 @@ static int fsl_sai_probe(struct platform_device *pdev)
MCLK_DIR(index));
}
- sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
- sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
+ sai->dma_params_rx.addr = res->start + FSL_SAI_RDR0;
+ sai->dma_params_tx.addr = res->start + FSL_SAI_TDR0;
sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index 7c1ef671da28..4bb478041d67 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -20,8 +20,22 @@
#define FSL_SAI_TCR3 0x0c /* SAI Transmit Configuration 3 */
#define FSL_SAI_TCR4 0x10 /* SAI Transmit Configuration 4 */
#define FSL_SAI_TCR5 0x14 /* SAI Transmit Configuration 5 */
-#define FSL_SAI_TDR 0x20 /* SAI Transmit Data */
-#define FSL_SAI_TFR 0x40 /* SAI Transmit FIFO */
+#define FSL_SAI_TDR0 0x20 /* SAI Transmit Data 0 */
+#define FSL_SAI_TDR1 0x24 /* SAI Transmit Data 1 */
+#define FSL_SAI_TDR2 0x28 /* SAI Transmit Data 2 */
+#define FSL_SAI_TDR3 0x2C /* SAI Transmit Data 3 */
+#define FSL_SAI_TDR4 0x30 /* SAI Transmit Data 4 */
+#define FSL_SAI_TDR5 0x34 /* SAI Transmit Data 5 */
+#define FSL_SAI_TDR6 0x38 /* SAI Transmit Data 6 */
+#define FSL_SAI_TDR7 0x3C /* SAI Transmit Data 7 */
+#define FSL_SAI_TFR0 0x40 /* SAI Transmit FIFO 0 */
+#define FSL_SAI_TFR1 0x44 /* SAI Transmit FIFO 1 */
+#define FSL_SAI_TFR2 0x48 /* SAI Transmit FIFO 2 */
+#define FSL_SAI_TFR3 0x4C /* SAI Transmit FIFO 3 */
+#define FSL_SAI_TFR4 0x50 /* SAI Transmit FIFO 4 */
+#define FSL_SAI_TFR5 0x54 /* SAI Transmit FIFO 5 */
+#define FSL_SAI_TFR6 0x58 /* SAI Transmit FIFO 6 */
+#define FSL_SAI_TFR7 0x5C /* SAI Transmit FIFO 7 */
#define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */
#define FSL_SAI_RCSR 0x80 /* SAI Receive Control */
#define FSL_SAI_RCR1 0x84 /* SAI Receive Configuration 1 */
@@ -29,8 +43,22 @@
#define FSL_SAI_RCR3 0x8c /* SAI Receive Configuration 3 */
#define FSL_SAI_RCR4 0x90 /* SAI Receive Configuration 4 */
#define FSL_SAI_RCR5 0x94 /* SAI Receive Configuration 5 */
-#define FSL_SAI_RDR 0xa0 /* SAI Receive Data */
-#define FSL_SAI_RFR 0xc0 /* SAI Receive FIFO */
+#define FSL_SAI_RDR0 0xa0 /* SAI Receive Data 0 */
+#define FSL_SAI_RDR1 0xa4 /* SAI Receive Data 1 */
+#define FSL_SAI_RDR2 0xa8 /* SAI Receive Data 2 */
+#define FSL_SAI_RDR3 0xac /* SAI Receive Data 3 */
+#define FSL_SAI_RDR4 0xb0 /* SAI Receive Data 4 */
+#define FSL_SAI_RDR5 0xb4 /* SAI Receive Data 5 */
+#define FSL_SAI_RDR6 0xb8 /* SAI Receive Data 6 */
+#define FSL_SAI_RDR7 0xbc /* SAI Receive Data 7 */
+#define FSL_SAI_RFR0 0xc0 /* SAI Receive FIFO 0 */
+#define FSL_SAI_RFR1 0xc4 /* SAI Receive FIFO 1 */
+#define FSL_SAI_RFR2 0xc8 /* SAI Receive FIFO 2 */
+#define FSL_SAI_RFR3 0xcc /* SAI Receive FIFO 3 */
+#define FSL_SAI_RFR4 0xd0 /* SAI Receive FIFO 4 */
+#define FSL_SAI_RFR5 0xd4 /* SAI Receive FIFO 5 */
+#define FSL_SAI_RFR6 0xd8 /* SAI Receive FIFO 6 */
+#define FSL_SAI_RFR7 0xdc /* SAI Receive FIFO 7 */
#define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */
#define FSL_SAI_xCSR(tx) (tx ? FSL_SAI_TCSR : FSL_SAI_RCSR)
--
2.17.1
^ permalink raw reply related
* [PATCH v2 2/7] ASoC: fsl_sai: Update Tx/Rx channel enable mask
From: Daniel Baluta @ 2019-07-28 19:24 UTC (permalink / raw)
To: broonie
Cc: l.stach, mihai.serban, alsa-devel, viorel.suman, timur,
shengjiu.wang, angus, tiwai, nicoleotsuka, linux-imx, kernel,
festevam, linux-kernel, devicetree, robh, Daniel Baluta
In-Reply-To: <20190728192429.1514-1-daniel.baluta@nxp.com>
Tx channel enable (TCE) / Rx channel enable (RCE) bits
enable corresponding data channel for Tx/Rx operation.
Because SAI supports up the 8 channels TCE/RCE occupy
up the 8 bits inside TCR3/RCR3 registers we need to extend
the mask to reflect this.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
---
sound/soc/fsl/fsl_sai.c | 6 ++++--
sound/soc/fsl/fsl_sai.h | 1 +
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 17b0aff4ee8b..637b1d12a575 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -599,7 +599,8 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream,
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
int ret;
- regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
+ regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx),
+ FSL_SAI_CR3_TRCE_MASK,
FSL_SAI_CR3_TRCE);
ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
@@ -614,7 +615,8 @@ static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
- regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0);
+ regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx),
+ FSL_SAI_CR3_TRCE_MASK, 0);
}
static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index 4bb478041d67..20c5b9b1e8bc 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -110,6 +110,7 @@
/* SAI Transmit and Receive Configuration 3 Register */
#define FSL_SAI_CR3_TRCE BIT(16)
+#define FSL_SAI_CR3_TRCE_MASK GENMASK(23, 16)
#define FSL_SAI_CR3_WDFL(x) (x)
#define FSL_SAI_CR3_WDFL_MASK 0x1f
--
2.17.1
^ permalink raw reply related
* [PATCH v2 3/7] ASoC: fsl_sai: Add support to enable multiple data lines
From: Daniel Baluta @ 2019-07-28 19:24 UTC (permalink / raw)
To: broonie
Cc: l.stach, mihai.serban, alsa-devel, viorel.suman, timur,
shengjiu.wang, angus, tiwai, nicoleotsuka, linux-imx, kernel,
festevam, linux-kernel, devicetree, robh, Daniel Baluta
In-Reply-To: <20190728192429.1514-1-daniel.baluta@nxp.com>
SAI supports up to 8 Rx/Tx data lines which can be enabled
using TCE/RCE bits of TCR3/RCR3 registers.
Data lines to be enabled are read from DT fsl,dl-mask property.
By default (if no DT entry is provided) only data line 0 is enabled.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
---
sound/soc/fsl/fsl_sai.c | 11 ++++++++++-
sound/soc/fsl/fsl_sai.h | 4 +++-
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 637b1d12a575..5e7cb7fd29f5 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -601,7 +601,7 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream,
regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx),
FSL_SAI_CR3_TRCE_MASK,
- FSL_SAI_CR3_TRCE);
+ FSL_SAI_CR3_TRCE(sai->soc_data->dl_mask[tx]);
ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
@@ -888,6 +888,15 @@ static int fsl_sai_probe(struct platform_device *pdev)
}
}
+ /*
+ * active data lines mask for TX/RX, defaults to 1 (only the first
+ * data line is enabled
+ */
+ sai->dl_mask[RX] = 1;
+ sai->dl_mask[TX] = 1;
+ of_property_read_u32_index(np, "fsl,dl-mask", RX, &sai->dl_mask[RX]);
+ of_property_read_u32_index(np, "fsl,dl-mask", TX, &sai->dl_mask[TX]);
+
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index 20c5b9b1e8bc..6d32f0950ec5 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -109,7 +109,7 @@
#define FSL_SAI_CR2_DIV_MASK 0xff
/* SAI Transmit and Receive Configuration 3 Register */
-#define FSL_SAI_CR3_TRCE BIT(16)
+#define FSL_SAI_CR3_TRCE(x) ((x) << 16)
#define FSL_SAI_CR3_TRCE_MASK GENMASK(23, 16)
#define FSL_SAI_CR3_WDFL(x) (x)
#define FSL_SAI_CR3_WDFL_MASK 0x1f
@@ -176,6 +176,8 @@ struct fsl_sai {
unsigned int slots;
unsigned int slot_width;
+ unsigned int dl_mask[2];
+
const struct fsl_sai_soc_data *soc_data;
struct snd_dmaengine_dai_dma_data dma_params_rx;
struct snd_dmaengine_dai_dma_data dma_params_tx;
--
2.17.1
^ permalink raw reply related
* [PATCH v2 4/7] ASoC: dt-bindings: Document dl-mask property
From: Daniel Baluta @ 2019-07-28 19:24 UTC (permalink / raw)
To: broonie
Cc: l.stach, mihai.serban, alsa-devel, viorel.suman, timur,
shengjiu.wang, angus, tiwai, nicoleotsuka, linux-imx, kernel,
festevam, linux-kernel, devicetree, robh, Daniel Baluta
In-Reply-To: <20190728192429.1514-1-daniel.baluta@nxp.com>
SAI supports up to 8 data lines. This property let the user
configure how many data lines should be used per transfer
direction (Tx/Rx).
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
---
Documentation/devicetree/bindings/sound/fsl-sai.txt | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt
index 2e726b983845..2b38036a4883 100644
--- a/Documentation/devicetree/bindings/sound/fsl-sai.txt
+++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt
@@ -49,6 +49,13 @@ Optional properties:
- big-endian : Boolean property, required if all the SAI
registers are big-endian rather than little-endian.
+ - fsl,dl-mask : list of two integers (bitmask, first for RX, second
+ for TX) representing enabled datalines. Bit 0
+ represents first data line, bit 1 represents second
+ data line and so on. Data line is enabled if
+ corresponding bit is set to 1. By default, if property
+ not present, only dataline 0 is enabled for both
+ directions.
Optional properties (for mx6ul):
--
2.17.1
^ permalink raw reply related
* [PATCH v2 5/7] ASoC: fsl_sai: Add support for SAI new version
From: Daniel Baluta @ 2019-07-28 19:24 UTC (permalink / raw)
To: broonie
Cc: l.stach, mihai.serban, alsa-devel, viorel.suman, timur,
shengjiu.wang, angus, tiwai, nicoleotsuka, linux-imx, kernel,
festevam, linux-kernel, devicetree, robh, Daniel Baluta,
Mihai Serban
In-Reply-To: <20190728192429.1514-1-daniel.baluta@nxp.com>
New IP version introduces Version ID and Parameter registers
and optionally added Timestamp feature.
VERID and PARAM registers are placed at the top of registers
address space and some registers are shifted according to
the following table:
Tx/Rx data registers and Tx/Rx FIFO registers keep their
addresses, all other registers are shifted by 8.
SAI Memory map is described in chapter 13.10.4.1.1 I2S Memory map
of the Reference Manual [1].
In order to make as less changes as possible we attach an offset
to each register offset to each changed register definition. The
offset is read from each board private data.
[1]https://cache.nxp.com/secured/assets/documents/en/reference-manual/IMX8MDQLQRM.pdf?__gda__=1563728701_38bea7f0f726472cc675cb141b91bec7&fileExt=.pdf
Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
[initial coding in the NXP internal tree]
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
[bugfixing and cleanups]
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
[adapted to linux-next]
---
sound/soc/fsl/fsl_sai.c | 230 ++++++++++++++++++++++++----------------
sound/soc/fsl/fsl_sai.h | 41 +++----
2 files changed, 157 insertions(+), 114 deletions(-)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 5e7cb7fd29f5..54e5e9abae01 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -40,6 +40,7 @@ static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
static irqreturn_t fsl_sai_isr(int irq, void *devid)
{
struct fsl_sai *sai = (struct fsl_sai *)devid;
+ unsigned int ofs = sai->soc_data->reg_offset;
struct device *dev = &sai->pdev->dev;
u32 flags, xcsr, mask;
bool irq_none = true;
@@ -52,7 +53,7 @@ static irqreturn_t fsl_sai_isr(int irq, void *devid)
mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
/* Tx IRQ */
- regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
+ regmap_read(sai->regmap, FSL_SAI_TCSR(ofs), &xcsr);
flags = xcsr & mask;
if (flags)
@@ -82,11 +83,11 @@ static irqreturn_t fsl_sai_isr(int irq, void *devid)
xcsr &= ~FSL_SAI_CSR_xF_MASK;
if (flags)
- regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr);
+ regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), flags | xcsr);
irq_rx:
/* Rx IRQ */
- regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr);
+ regmap_read(sai->regmap, FSL_SAI_RCSR(ofs), &xcsr);
flags = xcsr & mask;
if (flags)
@@ -116,7 +117,7 @@ static irqreturn_t fsl_sai_isr(int irq, void *devid)
xcsr &= ~FSL_SAI_CSR_xF_MASK;
if (flags)
- regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr);
+ regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), flags | xcsr);
out:
if (irq_none)
@@ -140,6 +141,7 @@ static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
int clk_id, unsigned int freq, int fsl_dir)
{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
+ unsigned int ofs = sai->soc_data->reg_offset;
bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
u32 val_cr2 = 0;
@@ -160,7 +162,7 @@ static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
return -EINVAL;
}
- regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
+ regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
FSL_SAI_CR2_MSEL_MASK, val_cr2);
return 0;
@@ -193,6 +195,7 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
unsigned int fmt, int fsl_dir)
{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
+ unsigned int ofs = sai->soc_data->reg_offset;
bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
u32 val_cr2 = 0, val_cr4 = 0;
@@ -287,9 +290,9 @@ static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
return -EINVAL;
}
- regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
+ regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
- regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
+ regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
@@ -316,6 +319,7 @@ static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
+ unsigned int ofs = sai->soc_data->reg_offset;
unsigned long clk_rate;
u32 savediv = 0, ratio, savesub = freq;
u32 id;
@@ -378,17 +382,17 @@ static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
*/
if ((sai->synchronous[TX] && !sai->synchronous[RX]) ||
(!tx && !sai->synchronous[RX])) {
- regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
+ regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs),
FSL_SAI_CR2_MSEL_MASK,
FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
- regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
+ regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs),
FSL_SAI_CR2_DIV_MASK, savediv - 1);
} else if ((sai->synchronous[RX] && !sai->synchronous[TX]) ||
(tx && !sai->synchronous[TX])) {
- regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
+ regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs),
FSL_SAI_CR2_MSEL_MASK,
FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
- regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
+ regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs),
FSL_SAI_CR2_DIV_MASK, savediv - 1);
}
@@ -403,6 +407,7 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
+ unsigned int ofs = sai->soc_data->reg_offset;
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
unsigned int channels = params_channels(params);
u32 word_width = params_width(params);
@@ -455,19 +460,19 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
if (!sai->is_slave_mode) {
if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
- regmap_update_bits(sai->regmap, FSL_SAI_TCR4,
+ regmap_update_bits(sai->regmap, FSL_SAI_TCR4(ofs),
FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
val_cr4);
- regmap_update_bits(sai->regmap, FSL_SAI_TCR5,
+ regmap_update_bits(sai->regmap, FSL_SAI_TCR5(ofs),
FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
FSL_SAI_CR5_FBT_MASK, val_cr5);
regmap_write(sai->regmap, FSL_SAI_TMR,
~0UL - ((1 << channels) - 1));
} else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
- regmap_update_bits(sai->regmap, FSL_SAI_RCR4,
+ regmap_update_bits(sai->regmap, FSL_SAI_RCR4(ofs),
FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
val_cr4);
- regmap_update_bits(sai->regmap, FSL_SAI_RCR5,
+ regmap_update_bits(sai->regmap, FSL_SAI_RCR5(ofs),
FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
FSL_SAI_CR5_FBT_MASK, val_cr5);
regmap_write(sai->regmap, FSL_SAI_RMR,
@@ -475,10 +480,10 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
}
}
- regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
+ regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx, ofs),
FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
val_cr4);
- regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx),
+ regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, ofs),
FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
FSL_SAI_CR5_FBT_MASK, val_cr5);
regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
@@ -506,6 +511,8 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
struct snd_soc_dai *cpu_dai)
{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
+ unsigned int ofs = sai->soc_data->reg_offset;
+
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
u32 xcsr, count = 100;
@@ -514,9 +521,9 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
* Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
* Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
*/
- regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC,
- sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
- regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
+ regmap_update_bits(sai->regmap, FSL_SAI_TCR2(ofs), FSL_SAI_CR2_SYNC,
+ sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
+ regmap_update_bits(sai->regmap, FSL_SAI_RCR2(ofs), FSL_SAI_CR2_SYNC,
sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
/*
@@ -527,43 +534,44 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
case SNDRV_PCM_TRIGGER_START:
case SNDRV_PCM_TRIGGER_RESUME:
case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
- regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
+ regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
- regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
+ regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs),
FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
- regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
+ regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
- regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
+ regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
break;
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
- regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
+ regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
FSL_SAI_CSR_FRDE, 0);
- regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
+ regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
FSL_SAI_CSR_xIE_MASK, 0);
/* Check if the opposite FRDE is also disabled */
- regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr);
+ regmap_read(sai->regmap, FSL_SAI_xCSR(!tx, ofs), &xcsr);
if (!(xcsr & FSL_SAI_CSR_FRDE)) {
/* Disable both directions and reset their FIFOs */
- regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
+ regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
FSL_SAI_CSR_TERE, 0);
- regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
+ regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs),
FSL_SAI_CSR_TERE, 0);
/* TERE will remain set till the end of current frame */
do {
udelay(10);
- regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr);
+ regmap_read(sai->regmap,
+ FSL_SAI_xCSR(tx, ofs), &xcsr);
} while (--count && xcsr & FSL_SAI_CSR_TERE);
- regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
+ regmap_update_bits(sai->regmap, FSL_SAI_TCSR(ofs),
FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
- regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
+ regmap_update_bits(sai->regmap, FSL_SAI_RCSR(ofs),
FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
/*
@@ -575,13 +583,13 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
*/
if (!sai->is_slave_mode) {
/* Software Reset for both Tx and Rx */
- regmap_write(sai->regmap,
- FSL_SAI_TCSR, FSL_SAI_CSR_SR);
- regmap_write(sai->regmap,
- FSL_SAI_RCSR, FSL_SAI_CSR_SR);
+ regmap_write(sai->regmap, FSL_SAI_TCSR(ofs),
+ FSL_SAI_CSR_SR);
+ regmap_write(sai->regmap, FSL_SAI_RCSR(ofs),
+ FSL_SAI_CSR_SR);
/* Clear SR bit to finish the reset */
- regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
- regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
+ regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
+ regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
}
}
break;
@@ -596,12 +604,13 @@ static int fsl_sai_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
+ unsigned int ofs = sai->soc_data->reg_offset;
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
int ret;
- regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx),
+ regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
FSL_SAI_CR3_TRCE_MASK,
- FSL_SAI_CR3_TRCE(sai->soc_data->dl_mask[tx]);
+ FSL_SAI_CR3_TRCE(sai->dl_mask[tx]));
ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
@@ -613,9 +622,10 @@ static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
+ unsigned int ofs = sai->soc_data->reg_offset;
bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
- regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx),
+ regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx, ofs),
FSL_SAI_CR3_TRCE_MASK, 0);
}
@@ -633,18 +643,20 @@ static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
{
struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
+ unsigned int ofs = sai->soc_data->reg_offset;
/* Software Reset for both Tx and Rx */
- regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
- regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
+ regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
+ regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
/* Clear SR bit to finish the reset */
- regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
- regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
+ regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
+ regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
- regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
+ regmap_update_bits(sai->regmap, FSL_SAI_TCR1(ofs),
+ FSL_SAI_CR1_RFW_MASK,
sai->soc_data->fifo_depth - FSL_SAI_MAXBURST_TX);
- regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
- FSL_SAI_MAXBURST_RX - 1);
+ regmap_update_bits(sai->regmap, FSL_SAI_RCR1(ofs),
+ FSL_SAI_CR1_RFW_MASK, FSL_SAI_MAXBURST_RX - 1);
snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
&sai->dma_params_rx);
@@ -681,12 +693,12 @@ static const struct snd_soc_component_driver fsl_component = {
.name = "fsl-sai",
};
-static struct reg_default fsl_sai_reg_defaults[] = {
- {FSL_SAI_TCR1, 0},
- {FSL_SAI_TCR2, 0},
- {FSL_SAI_TCR3, 0},
- {FSL_SAI_TCR4, 0},
- {FSL_SAI_TCR5, 0},
+static struct reg_default fsl_sai_reg_defaults_ofs0[] = {
+ {FSL_SAI_TCR1(0), 0},
+ {FSL_SAI_TCR2(0), 0},
+ {FSL_SAI_TCR3(0), 0},
+ {FSL_SAI_TCR4(0), 0},
+ {FSL_SAI_TCR5(0), 0},
{FSL_SAI_TDR0, 0},
{FSL_SAI_TDR1, 0},
{FSL_SAI_TDR2, 0},
@@ -695,24 +707,50 @@ static struct reg_default fsl_sai_reg_defaults[] = {
{FSL_SAI_TDR5, 0},
{FSL_SAI_TDR6, 0},
{FSL_SAI_TDR7, 0},
- {FSL_SAI_TMR, 0},
- {FSL_SAI_RCR1, 0},
- {FSL_SAI_RCR2, 0},
- {FSL_SAI_RCR3, 0},
- {FSL_SAI_RCR4, 0},
- {FSL_SAI_RCR5, 0},
- {FSL_SAI_RMR, 0},
+ {FSL_SAI_TMR, 0},
+ {FSL_SAI_RCR1(0), 0},
+ {FSL_SAI_RCR2(0), 0},
+ {FSL_SAI_RCR3(0), 0},
+ {FSL_SAI_RCR4(0), 0},
+ {FSL_SAI_RCR5(0), 0},
+ {FSL_SAI_RMR, 0},
+};
+
+static struct reg_default fsl_sai_reg_defaults_ofs8[] = {
+ {FSL_SAI_TCR1(8), 0},
+ {FSL_SAI_TCR2(8), 0},
+ {FSL_SAI_TCR3(8), 0},
+ {FSL_SAI_TCR4(8), 0},
+ {FSL_SAI_TCR5(8), 0},
+ {FSL_SAI_TDR0, 0},
+ {FSL_SAI_TDR1, 0},
+ {FSL_SAI_TDR2, 0},
+ {FSL_SAI_TDR3, 0},
+ {FSL_SAI_TDR4, 0},
+ {FSL_SAI_TDR5, 0},
+ {FSL_SAI_TDR6, 0},
+ {FSL_SAI_TDR7, 0},
+ {FSL_SAI_TMR, 0},
+ {FSL_SAI_RCR1(8), 0},
+ {FSL_SAI_RCR2(8), 0},
+ {FSL_SAI_RCR3(8), 0},
+ {FSL_SAI_RCR4(8), 0},
+ {FSL_SAI_RCR5(8), 0},
+ {FSL_SAI_RMR, 0},
};
static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
{
+ struct fsl_sai *sai = dev_get_drvdata(dev);
+ unsigned int ofs = sai->soc_data->reg_offset;
+
+ if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
+ return true;
+
+ if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
+ return true;
+
switch (reg) {
- case FSL_SAI_TCSR:
- case FSL_SAI_TCR1:
- case FSL_SAI_TCR2:
- case FSL_SAI_TCR3:
- case FSL_SAI_TCR4:
- case FSL_SAI_TCR5:
case FSL_SAI_TFR0:
case FSL_SAI_TFR1:
case FSL_SAI_TFR2:
@@ -722,12 +760,6 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
case FSL_SAI_TFR6:
case FSL_SAI_TFR7:
case FSL_SAI_TMR:
- case FSL_SAI_RCSR:
- case FSL_SAI_RCR1:
- case FSL_SAI_RCR2:
- case FSL_SAI_RCR3:
- case FSL_SAI_RCR4:
- case FSL_SAI_RCR5:
case FSL_SAI_RDR0:
case FSL_SAI_RDR1:
case FSL_SAI_RDR2:
@@ -753,9 +785,13 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
{
+ struct fsl_sai *sai = dev_get_drvdata(dev);
+ unsigned int ofs = sai->soc_data->reg_offset;
+
+ if (reg == FSL_SAI_TCSR(ofs) || reg == FSL_SAI_RCSR(ofs))
+ return true;
+
switch (reg) {
- case FSL_SAI_TCSR:
- case FSL_SAI_RCSR:
case FSL_SAI_TFR0:
case FSL_SAI_TFR1:
case FSL_SAI_TFR2:
@@ -788,13 +824,16 @@ static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
{
+ struct fsl_sai *sai = dev_get_drvdata(dev);
+ unsigned int ofs = sai->soc_data->reg_offset;
+
+ if (reg >= FSL_SAI_TCSR(ofs) && reg <= FSL_SAI_TCR5(ofs))
+ return true;
+
+ if (reg >= FSL_SAI_RCSR(ofs) && reg <= FSL_SAI_RCR5(ofs))
+ return true;
+
switch (reg) {
- case FSL_SAI_TCSR:
- case FSL_SAI_TCR1:
- case FSL_SAI_TCR2:
- case FSL_SAI_TCR3:
- case FSL_SAI_TCR4:
- case FSL_SAI_TCR5:
case FSL_SAI_TDR0:
case FSL_SAI_TDR1:
case FSL_SAI_TDR2:
@@ -804,12 +843,6 @@ static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
case FSL_SAI_TDR6:
case FSL_SAI_TDR7:
case FSL_SAI_TMR:
- case FSL_SAI_RCSR:
- case FSL_SAI_RCR1:
- case FSL_SAI_RCR2:
- case FSL_SAI_RCR3:
- case FSL_SAI_RCR4:
- case FSL_SAI_RCR5:
case FSL_SAI_RMR:
return true;
default:
@@ -817,15 +850,15 @@ static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
}
}
-static const struct regmap_config fsl_sai_regmap_config = {
+static struct regmap_config fsl_sai_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
.val_bits = 32,
.fast_io = true,
.max_register = FSL_SAI_RMR,
- .reg_defaults = fsl_sai_reg_defaults,
- .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults),
+ .reg_defaults = fsl_sai_reg_defaults_ofs0,
+ .num_reg_defaults = ARRAY_SIZE(fsl_sai_reg_defaults_ofs0),
.readable_reg = fsl_sai_readable_reg,
.volatile_reg = fsl_sai_volatile_reg,
.writeable_reg = fsl_sai_writeable_reg,
@@ -857,6 +890,12 @@ static int fsl_sai_probe(struct platform_device *pdev)
if (IS_ERR(base))
return PTR_ERR(base);
+ if (sai->soc_data->reg_offset == 8) {
+ fsl_sai_regmap_config.reg_defaults = fsl_sai_reg_defaults_ofs8;
+ fsl_sai_regmap_config.num_reg_defaults =
+ ARRAY_SIZE(fsl_sai_reg_defaults_ofs8);
+ }
+
sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
"bus", base, &fsl_sai_regmap_config);
@@ -982,11 +1021,13 @@ static int fsl_sai_remove(struct platform_device *pdev)
static const struct fsl_sai_soc_data fsl_sai_vf610_data = {
.use_imx_pcm = false,
.fifo_depth = 32,
+ .reg_offset = 0,
};
static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
.use_imx_pcm = true,
.fifo_depth = 32,
+ .reg_offset = 0,
};
static const struct of_device_id fsl_sai_ids[] = {
@@ -1019,6 +1060,7 @@ static int fsl_sai_runtime_suspend(struct device *dev)
static int fsl_sai_runtime_resume(struct device *dev)
{
struct fsl_sai *sai = dev_get_drvdata(dev);
+ unsigned int ofs = sai->soc_data->reg_offset;
int ret;
ret = clk_prepare_enable(sai->bus_clk);
@@ -1040,11 +1082,11 @@ static int fsl_sai_runtime_resume(struct device *dev)
}
regcache_cache_only(sai->regmap, false);
- regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
- regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
+ regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), FSL_SAI_CSR_SR);
+ regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), FSL_SAI_CSR_SR);
usleep_range(1000, 2000);
- regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
- regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
+ regmap_write(sai->regmap, FSL_SAI_TCSR(ofs), 0);
+ regmap_write(sai->regmap, FSL_SAI_RCSR(ofs), 0);
ret = regcache_sync(sai->regmap);
if (ret)
diff --git a/sound/soc/fsl/fsl_sai.h b/sound/soc/fsl/fsl_sai.h
index 6d32f0950ec5..0e61e1a01506 100644
--- a/sound/soc/fsl/fsl_sai.h
+++ b/sound/soc/fsl/fsl_sai.h
@@ -14,12 +14,12 @@
SNDRV_PCM_FMTBIT_S32_LE)
/* SAI Register Map Register */
-#define FSL_SAI_TCSR 0x00 /* SAI Transmit Control */
-#define FSL_SAI_TCR1 0x04 /* SAI Transmit Configuration 1 */
-#define FSL_SAI_TCR2 0x08 /* SAI Transmit Configuration 2 */
-#define FSL_SAI_TCR3 0x0c /* SAI Transmit Configuration 3 */
-#define FSL_SAI_TCR4 0x10 /* SAI Transmit Configuration 4 */
-#define FSL_SAI_TCR5 0x14 /* SAI Transmit Configuration 5 */
+#define FSL_SAI_TCSR(ofs) (0x00 + ofs) /* SAI Transmit Control */
+#define FSL_SAI_TCR1(ofs) (0x04 + ofs) /* SAI Transmit Configuration 1 */
+#define FSL_SAI_TCR2(ofs) (0x08 + ofs) /* SAI Transmit Configuration 2 */
+#define FSL_SAI_TCR3(ofs) (0x0c + ofs) /* SAI Transmit Configuration 3 */
+#define FSL_SAI_TCR4(ofs) (0x10 + ofs) /* SAI Transmit Configuration 4 */
+#define FSL_SAI_TCR5(ofs) (0x14 + ofs) /* SAI Transmit Configuration 5 */
#define FSL_SAI_TDR0 0x20 /* SAI Transmit Data 0 */
#define FSL_SAI_TDR1 0x24 /* SAI Transmit Data 1 */
#define FSL_SAI_TDR2 0x28 /* SAI Transmit Data 2 */
@@ -37,12 +37,12 @@
#define FSL_SAI_TFR6 0x58 /* SAI Transmit FIFO 6 */
#define FSL_SAI_TFR7 0x5C /* SAI Transmit FIFO 7 */
#define FSL_SAI_TMR 0x60 /* SAI Transmit Mask */
-#define FSL_SAI_RCSR 0x80 /* SAI Receive Control */
-#define FSL_SAI_RCR1 0x84 /* SAI Receive Configuration 1 */
-#define FSL_SAI_RCR2 0x88 /* SAI Receive Configuration 2 */
-#define FSL_SAI_RCR3 0x8c /* SAI Receive Configuration 3 */
-#define FSL_SAI_RCR4 0x90 /* SAI Receive Configuration 4 */
-#define FSL_SAI_RCR5 0x94 /* SAI Receive Configuration 5 */
+#define FSL_SAI_RCSR(ofs) (0x80 + ofs) /* SAI Receive Control */
+#define FSL_SAI_RCR1(ofs) (0x84 + ofs)/* SAI Receive Configuration 1 */
+#define FSL_SAI_RCR2(ofs) (0x88 + ofs) /* SAI Receive Configuration 2 */
+#define FSL_SAI_RCR3(ofs) (0x8c + ofs) /* SAI Receive Configuration 3 */
+#define FSL_SAI_RCR4(ofs) (0x90 + ofs) /* SAI Receive Configuration 4 */
+#define FSL_SAI_RCR5(ofs) (0x94 + ofs) /* SAI Receive Configuration 5 */
#define FSL_SAI_RDR0 0xa0 /* SAI Receive Data 0 */
#define FSL_SAI_RDR1 0xa4 /* SAI Receive Data 1 */
#define FSL_SAI_RDR2 0xa8 /* SAI Receive Data 2 */
@@ -61,14 +61,14 @@
#define FSL_SAI_RFR7 0xdc /* SAI Receive FIFO 7 */
#define FSL_SAI_RMR 0xe0 /* SAI Receive Mask */
-#define FSL_SAI_xCSR(tx) (tx ? FSL_SAI_TCSR : FSL_SAI_RCSR)
-#define FSL_SAI_xCR1(tx) (tx ? FSL_SAI_TCR1 : FSL_SAI_RCR1)
-#define FSL_SAI_xCR2(tx) (tx ? FSL_SAI_TCR2 : FSL_SAI_RCR2)
-#define FSL_SAI_xCR3(tx) (tx ? FSL_SAI_TCR3 : FSL_SAI_RCR3)
-#define FSL_SAI_xCR4(tx) (tx ? FSL_SAI_TCR4 : FSL_SAI_RCR4)
-#define FSL_SAI_xCR5(tx) (tx ? FSL_SAI_TCR5 : FSL_SAI_RCR5)
-#define FSL_SAI_xDR(tx) (tx ? FSL_SAI_TDR : FSL_SAI_RDR)
-#define FSL_SAI_xFR(tx) (tx ? FSL_SAI_TFR : FSL_SAI_RFR)
+#define FSL_SAI_xCSR(tx, ofs) (tx ? FSL_SAI_TCSR(ofs) : FSL_SAI_RCSR(ofs))
+#define FSL_SAI_xCR1(tx, ofs) (tx ? FSL_SAI_TCR1(ofs) : FSL_SAI_RCR1(ofs))
+#define FSL_SAI_xCR2(tx, ofs) (tx ? FSL_SAI_TCR2(ofs) : FSL_SAI_RCR2(ofs))
+#define FSL_SAI_xCR3(tx, ofs) (tx ? FSL_SAI_TCR3(ofs) : FSL_SAI_RCR3(ofs))
+#define FSL_SAI_xCR4(tx, ofs) (tx ? FSL_SAI_TCR4(ofs) : FSL_SAI_RCR4(ofs))
+#define FSL_SAI_xCR5(tx, ofs) (tx ? FSL_SAI_TCR5(ofs) : FSL_SAI_RCR5(ofs))
+#define FSL_SAI_xDR(tx, ofs) (tx ? FSL_SAI_TDR(ofs) : FSL_SAI_RDR(ofs))
+#define FSL_SAI_xFR(tx, ofs) (tx ? FSL_SAI_TFR(ofs) : FSL_SAI_RFR(ofs))
#define FSL_SAI_xMR(tx) (tx ? FSL_SAI_TMR : FSL_SAI_RMR)
/* SAI Transmit/Receive Control Register */
@@ -158,6 +158,7 @@
struct fsl_sai_soc_data {
bool use_imx_pcm;
unsigned int fifo_depth;
+ unsigned int reg_offset;
};
struct fsl_sai {
--
2.17.1
^ permalink raw reply related
* [PATCH v2 6/7] ASoC: fsl_sai: Add support for imx7ulp/imx8mq
From: Daniel Baluta @ 2019-07-28 19:24 UTC (permalink / raw)
To: broonie
Cc: l.stach, mihai.serban, alsa-devel, viorel.suman, timur,
shengjiu.wang, angus, tiwai, nicoleotsuka, linux-imx, kernel,
festevam, linux-kernel, devicetree, robh, Daniel Baluta
In-Reply-To: <20190728192429.1514-1-daniel.baluta@nxp.com>
SAI module on imx7ulp/imx8m features 2 new registers (VERID and PARAM)
at the beginning of register address space.
On imx7ulp FIFOs can held up to 16 x 32 bit samples.
On imx8mq FIFOs can held up to 128 x 32 bit samples.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
---
sound/soc/fsl/fsl_sai.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c
index 54e5e9abae01..0fb6750fefd5 100644
--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c
@@ -1030,10 +1030,24 @@ static const struct fsl_sai_soc_data fsl_sai_imx6sx_data = {
.reg_offset = 0,
};
+static const struct fsl_sai_soc_data fsl_sai_imx7ulp_data = {
+ .use_imx_pcm = true,
+ .fifo_depth = 16,
+ .reg_offset = 8,
+};
+
+static const struct fsl_sai_soc_data fsl_sai_imx8mq_data = {
+ .use_imx_pcm = true,
+ .fifo_depth = 128,
+ .reg_offset = 8,
+};
+
static const struct of_device_id fsl_sai_ids[] = {
{ .compatible = "fsl,vf610-sai", .data = &fsl_sai_vf610_data },
{ .compatible = "fsl,imx6sx-sai", .data = &fsl_sai_imx6sx_data },
{ .compatible = "fsl,imx6ul-sai", .data = &fsl_sai_imx6sx_data },
+ { .compatible = "fsl,imx7ulp-sai", .data = &fsl_sai_imx7ulp_data },
+ { .compatible = "fsl,imx8mq-sai", .data = &fsl_sai_imx8mq_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, fsl_sai_ids);
--
2.17.1
^ permalink raw reply related
* [PATCH v2 7/7] ASoC: dt-bindings: Introduce compatible strings for 7ULP and 8MQ
From: Daniel Baluta @ 2019-07-28 19:24 UTC (permalink / raw)
To: broonie
Cc: l.stach, mihai.serban, alsa-devel, viorel.suman, timur,
shengjiu.wang, angus, tiwai, nicoleotsuka, linux-imx, kernel,
festevam, linux-kernel, devicetree, robh, Daniel Baluta
In-Reply-To: <20190728192429.1514-1-daniel.baluta@nxp.com>
For i.MX7ULP and i.MX8MQ register map is changed. Add two new compatbile
strings to differentiate this.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
---
Documentation/devicetree/bindings/sound/fsl-sai.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt
index 2b38036a4883..b008e9cfedc1 100644
--- a/Documentation/devicetree/bindings/sound/fsl-sai.txt
+++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt
@@ -8,7 +8,8 @@ codec/DSP interfaces.
Required properties:
- compatible : Compatible list, contains "fsl,vf610-sai",
- "fsl,imx6sx-sai" or "fsl,imx6ul-sai"
+ "fsl,imx6sx-sai", "fsl,imx6ul-sai",
+ "fsl,imx7ulp-sai", "fsl,imx8mq-sai".
- reg : Offset and length of the register set for the device.
--
2.17.1
^ permalink raw reply related
* Re: [PATCH 0/4] crypto: add amlogic crypto offloader driver
From: LABBE Corentin @ 2019-07-28 19:42 UTC (permalink / raw)
To: davem, herbert, khilman, mark.rutland, robh+dt, devicetree,
linux-amlogic, linux-arm-kernel, linux-crypto, linux-kernel,
baylibre-upstreaming
In-Reply-To: <20190728184803.GA14920@sol.localdomain>
On Sun, Jul 28, 2019 at 11:48:03AM -0700, Eric Biggers wrote:
> Hi Corentin,
>
> On Thu, Jul 25, 2019 at 07:42:52PM +0000, Corentin Labbe wrote:
> > Hello
> >
> > This serie adds support for the crypto offloader present on amlogic GXL
> > SoCs.
> >
> > Tested on meson-gxl-s905x-khadas-vim and meson-gxl-s905x-libretech-cc
> >
> > Regards
> >
>
> Does this new driver pass all the crypto self-tests?
> Including with CONFIG_CRYPTO_MANAGER_EXTRA_TESTS=y?
>
Yes it pass all extra self-tests.
I forgot to write it in the cover letter.
Regards
^ permalink raw reply
* [PATCH 0/2] Amazon Annapurna Labs Alpine v3 device-tree
From: Ronen Krupnik @ 2019-07-28 19:51 UTC (permalink / raw)
To: robh+dt, mark.rutland
Cc: devicetree, linux-kernel, barakw, dwmw, benh, jonnyc, talel,
hhhawa, hanochu, Ronen Krupnik
This series introduces the device tree for Amazon Annapurna Labs Alpine v3
SoC and Evaluation Board.
Ronen Krupnik (2):
dt-bindings: amazon: add Amazon Annapurna Labs Alpine support
arm64: dts: amazon: add Amazon Annapurna Labs Alpine v3 support
.../devicetree/bindings/arm/amazon,alpine.txt | 23 ++
arch/arm64/boot/dts/Makefile | 1 +
arch/arm64/boot/dts/amazon/Makefile | 1 +
arch/arm64/boot/dts/amazon/alpine-v3-evp.dts | 23 ++
arch/arm64/boot/dts/amazon/alpine-v3.dtsi | 371 ++++++++++++++++++
5 files changed, 419 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/amazon,alpine.txt
create mode 100644 arch/arm64/boot/dts/amazon/Makefile
create mode 100644 arch/arm64/boot/dts/amazon/alpine-v3-evp.dts
create mode 100644 arch/arm64/boot/dts/amazon/alpine-v3.dtsi
--
2.21.0
^ permalink raw reply
* [PATCH 1/2] dt-bindings: amazon: add Amazon Annapurna Labs Alpine support
From: Ronen Krupnik @ 2019-07-28 19:51 UTC (permalink / raw)
To: robh+dt, mark.rutland
Cc: devicetree, linux-kernel, barakw, dwmw, benh, jonnyc, talel,
hhhawa, hanochu, Ronen Krupnik
In-Reply-To: <20190728195135.12661-1-ronenk@amazon.com>
This patch adds DT bindings info for Amazon Annapurna Labs Alpine SOC
and related reference boards.
Signed-off-by: Ronen Krupnik <ronenk@amazon.com>
---
.../devicetree/bindings/arm/amazon,alpine.txt | 23 +++++++++++++++++++
1 file changed, 23 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/amazon,alpine.txt
diff --git a/Documentation/devicetree/bindings/arm/amazon,alpine.txt b/Documentation/devicetree/bindings/arm/amazon,alpine.txt
new file mode 100644
index 000000000000..58817208421b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/amazon,alpine.txt
@@ -0,0 +1,23 @@
+Amazon Annapurna Labs Alpine v3 Platform Device Tree Bindings
+---------------------------------------------------------------
+
+Platforms based on Amazon Annapurna Labs Alpine SoC architecture
+shall follow the following scheme:
+
+SoCs
+----
+
+Each device tree root node must specify which exact SoC in alpine
+architecture it uses, using one of the following compatible values:
+
+- alpine v3
+ compatible = "amazon,alpine-v3";
+
+Boards
+------
+
+Each device tree must specify which one or more of the following
+board-specific compatible values:
+
+- alpine-v3 Evaluation Platform (EVP)
+ compatible = "amazon,alpine-v3-evp";
--
2.21.0
^ permalink raw reply related
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