* [PATCH v3 2/2] dt-bindings: iio: potentiometer: add max5432.yaml binding
From: Martin Kaiser @ 2019-07-29 11:45 UTC (permalink / raw)
To: Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen, Rob Herring
Cc: linux-iio, devicetree, linux-kernel, Martin Kaiser
In-Reply-To: <20190729114531.12386-1-martin@kaiser.cx>
Add a binding for the Maxim Integrated MAX5432-MAX5435 family of digital
potentiometers.
Signed-off-by: Martin Kaiser <martin@kaiser.cx>
---
changes in v3
- split dt bindings and driver code into separate patches
- use yaml format for dt bindings
- fix formatting of parameter lists
changes in v2
- use MAX5432_ prefix for all defines
- fix indentation
- convert void * to unsigned long, not to u32
(warning from kbuild test robot)
.../bindings/iio/potentiometer/max5432.yaml | 35 ++++++++++++++++++++++
1 file changed, 35 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/potentiometer/max5432.yaml
diff --git a/Documentation/devicetree/bindings/iio/potentiometer/max5432.yaml b/Documentation/devicetree/bindings/iio/potentiometer/max5432.yaml
new file mode 100644
index 000000000000..448781b80f39
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/potentiometer/max5432.yaml
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/potentiometer/max5432.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim Integrated MAX5432-MAX5435 Digital Potentiometers
+
+maintainers:
+ - Martin Kaiser <martin@kaiser.cx>
+
+description: |
+ Maxim Integrated MAX5432-MAX5435 Digital Potentiometers connected via I2C
+
+ Datasheet:
+ https://datasheets.maximintegrated.com/en/ds/MAX5432-MAX5435.pdf
+
+properties:
+ compatible:
+ enum:
+ - maxim,max5432
+ - maxim,max5433
+ - maxim,max5434
+ - maxim,max5435
+
+examples:
+ - |
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ max5434@28 {
+ compatible = "maxim,max5434";
+ reg = <0x28>;
+ };
+ };
--
2.11.0
^ permalink raw reply related
* Re: [PATCH 4/4] dt-bindings: i2c: riic: Rename bindings documentation file
From: Geert Uytterhoeven @ 2019-07-29 11:46 UTC (permalink / raw)
To: Simon Horman
Cc: Wolfram Sang, Chris Brandt, Rob Herring, Mark Rutland,
Magnus Damm, Linux I2C,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas
In-Reply-To: <20190724121559.19079-5-horms+renesas@verge.net.au>
Hi Simon,
The subject line is identical to the one for PATCH 3/4.
Probably you intended s/riic/iic-emev2/?
On Wed, Jul 24, 2019 at 3:25 PM Simon Horman <horms+renesas@verge.net.au> wrote:
>
> Rename the bindings documentation file for Renesas EMEV2 IIC controller
> from i2c-emev2.txt to renesas,iic-emev2.txt.
>
> This is part of an ongoing effort to name bindings documentation files for
> Renesas IP blocks consistently, in line with the compat strings they
> document.
>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [RFC PATCH V2 4/4] platform: mtk-isp: Add Mediatek FD driver
From: Jerry-ch Chen @ 2019-07-29 11:58 UTC (permalink / raw)
To: Tomasz Figa
Cc: laurent.pinchart+renesas@ideasonboard.com,
Rynn Wu (吳育恩),
Po-Yang Huang (黃柏陽), suleiman@chromium.org,
jerry-ch.chen, Jungo Lin (林明俊),
hans.verkuil@cisco.com, Sakari Ailus,
Frederic Chen (陳俊元),
linux-media@vger.kernel.org, devicetree@vger.kernel.org,
Sj Huang (黃信璋), yuzhao@chromium.org
In-Reply-To: <CAAFQd5A0Qi==m4O9L2W3Qmdx4g8acs-kjBtHjLBNCBpoGd5ZSw@mail.gmail.com>
Hi Tomasz,
On Mon, 2019-07-29 at 17:57 +0800, Tomasz Figa wrote:
> On Mon, Jul 29, 2019 at 3:01 PM Jerry-ch Chen
> <Jerry-ch.Chen@mediatek.com> wrote:
> >
> > Hi Enrico,
> >
> > On Tue, 2019-07-09 at 18:56 +0800, Enrico Weigelt, metux IT consult
> > wrote:
> > > On 09.07.19 10:41, Jerry-ch Chen wrote:
> > >
> > > Hi,
> > >
> > >
> > > > diff --git a/drivers/media/platform/mtk-isp/fd/mtk_fd.h b/drivers/media/platform/mtk-isp/fd/mtk_fd.h
> > > > new file mode 100644
> > > > index 0000000..289999b
> > > > --- /dev/null
> > > > +++ b/drivers/media/platform/mtk-isp/fd/mtk_fd.h
> > > > @@ -0,0 +1,157 @@
> > > > +/* SPDX-License-Identifier: GPL-2.0 */
> > > > +//
> > > > +// Copyright (c) 2018 MediaTek Inc.
> > > > +
> > > > +#ifndef __MTK_FD_HW_H__
> > > > +#define __MTK_FD_HW_H__
> > > > +
> > > > +#include <linux/io.h>
> > > > +#include <linux/types.h>
> > > > +#include <linux/platform_device.h>
> > > > +#include <media/v4l2-ctrls.h>
> > > > +#include <media/v4l2-device.h>
> > > > +#include <media/videobuf2-v4l2.h>
> > > > +
> > > > +#define MTK_FD_OUTPUT_MIN_WIDTH 26U
> > > > +#define MTK_FD_OUTPUT_MIN_HEIGHT 26U
> > > > +#define MTK_FD_OUTPUT_MAX_WIDTH 640U
> > > > +#define MTK_FD_OUTPUT_MAX_HEIGHT 480U
> > > > +
> > > > +/* Control the user defined image widths and heights
> > > > + * to be scaled and performed face detection in FD HW.
> > > > + * MTK FD support up to 14 user defined image sizes to perform face detection.
> > > > + */
> > > > +#define V4L2_CID_MTK_FD_SCALE_IMG_WIDTH (V4L2_CID_USER_MTK_FD_BASE + 1)
> > > > +#define V4L2_CID_MTK_FD_SCALE_IMG_HEIGHT (V4L2_CID_USER_MTK_FD_BASE + 2)
> > >
> > > I've got a *really* bad feeling about introducing chip specific
> > > uapi stuff. (by the way: uapi stuff belongs into include/uapi/...)
> > >
> > Thanks for your comments,
> >
> > If we remain chip-specific control IDs, I will move the uapi stuff into
> > inlcude/uapi/mtk_fd.h (filename TBD)
> >
> > > Maybe you could tell us what that's *really* about, so we can find some
> > > standard / chip-independent api for these things. That's one of the
> > > major point of the kernel: hardware abstraction.
> > >
> > I am not sure if it is possible for us to add some standard
> > v4l2-controls for face detection, a further explanations of controls are
> > listed below.
> >
> > In v4l2-controls, there exists V4L2_CID_DETECT_CLASS, but I haven't
> > found the standards or api that can be used for face detection yet.
> > https://elixir.bootlin.com/linux/latest/source/include/uapi/linux/v4l2-controls.h#L1092
> >
> > For detecting certain face angle and head direction, we would need
> > V4L2_CID_DETECT_ANGLE, V4L2_CID_DETECT_DIRECTION controls for user to
> > specify the angle and direction to be detected.
> > In MTK FD driver, we support the following angles and directions to be
> > selected by user, and they are both multiple selected .
> > FD_angle_table[] = {-90, -45, 0 , 45, 90}
> > FD_direction_table[] = {0, 30, 60, 90, 120, 150, ..., 330}
> >
> > Assuming these v4l2-controls are array of V4L2_CTRL_TYPE_U16 with
> > dimension 5 and 12.
> > User can select the desired angle and directions to be detected into
> > arrays and bring it to driver by these controls, however, the more they
> > select, the longer execution time needed by HW.
> >
>
> Sounds like we need some kind of a menu bitmask control here, but I
> don't see V4L2 having anything like that.
>
> Hans, Sakari, any ideas?
>
> > For detecting different sizes of faces and increase the detection speed,
> > FD driver might need to scales down the input image into different
> > smaller sizes
>
> Do you mean the FD hardware would do the scaling or the driver code
> itself? It would be undesirable to do such scaling in a kernel driver,
> so if that's not something handled by the hardware, the downscaled
> image might need to be provided from the userspace.
>
Thanks for your comments.
Yes, FD hardware will do the scaling itself, so driver could set the
sizes.
> >, besides driver default values, user or proprietary
> > algorithm library can manually set the desired image sizes, therefore,
> > we would need the following controls:
> > V4L2_CID_DETECT_SCALE_DOWN_IMG_WIDTH and
> > V4L2_CID_DETECT_SCALE_DOWN_IMG_HEIGHT.
> > In MTK FD driver, we implement these controls as array of
> > V4L2_CTRL_TYPE_U16 with the dimension 15.
>
> Why 15?
>
It consists of one input image size and 14 down-scaled image sizes,
the amount 15 (or say 14) is defined by the MTK FD algo library,
therefore I remain the number of 15 here for communicate with the
library.
Maybe it should be defined as following?
MTK_FD_MAX_SCALE_SIZE_NUM 14
and
MTK_FD_SCALE_ARR_NUM 15
> >
> > For controlling detection speed, we would need the
> > V4L2_CID_DETECT_SPEED, the faster speedup implies the lower accuracy of
> > detection, In MTK FD driver, the max level of speedup is 7, and default
> > value is 0.
> >
> > For MTK FD algorithm user library, they would need select extra
> > detection features(models) used in HW, we need
> > V4L2_CID_MTK_FD_EXTRA_MODEL, this will be set to 1 for using extra
> > model. However, we are considering make this control more
> > chip-independent and can be added into standard.
> > for example, V4L2_CID_DETECTION_FD_MODEL or ...FD_ALGO,
> > drivers can define the detection algorithm or detection model to be used
> > for users to select. How do you think?
>
> Sounds like something that could be a menu control, so it could vary
> between drivers.
>
Ok, and maybe it should be created by v4l2_ctrl_new_int_menu(...)?
> >
> > In short, I summery the control IDs as following:
> > V4L2_CID_DETECT_ANGLE: set the angle of face in degrees. 90 ~ -90
> > degrees.
> > V4L2_CID_DETECT_DIRECTION: set the rotation of the head in degrees.
> > 0~330 degrees.
> > V4L2_CID_DETECT_SCALE_DOWN_IMG_WIDTH: set the image widths for an input
> > image to be scaled down for face detection
> > V4L2_CID_DETECT_SCALE_DOWN_IMG_HEIGHT: set the image heights for an
> > input image to be scaled down for face detection
> > V4L2_CID_DETECT_SPEED: set the detection speed, usually reducing
> > accuracy.
> > V4L2_CID_DETECTION_FD_MODEL: select the detection model or algorithm to
> > be used by face detection driver.
> >
> > > > +#define ENABLE_FD 0x111
> > > > +#define FD_HW_ENABLE 0x4
> > > > +#define FD_INT_EN 0x15c
> > > > +#define FD_INT 0x168
> > > > +#define FD_RESULT 0x178
> > > > +#define FD_IRQ_MASK 0x001
> > > > +
> > > > +#define RS_MAX_BUF_SIZE 2288788
> > > > +#define FD_MAX_SPEEDUP 7
> > > > +#define FD_MAX_POSE_VAL 0xfffffffffffffff
> > > > +#define FD_DEF_POSE_VAL 0x3ff
> > > > +#define MAX_FD_SEL_NUM 1026
> > >
> > > If that file is supposed to be included by anything beyond the driver
> > > itself, we need proper prefixing. (same for anything else in here)
> > >
> > I will fix it as following:
> >
> > #define FD_ENABLE 0x111
> >
> > #define FD_REG_OFFSET_HW_ENABLE 0x4
> > #define FD_REG_OFFSET_INT_EN 0x15c
> > #define FD_REG_OFFSET_INT_VAL 0x168
> > #define FD_REG_OFFSET_RESULT 0x178
> >
> > #define FD_IRQ_MASK 1
> > #define FD_MAX_RS_BUF_SIZE 2288788
> > #define FD_MAX_SPEEDUP 7
> > #define FD_MAX_RESULT_NUM 1026
> >
>
> I'd suggest the MTK_FD_ prefix.
>
Ok, I will use MTK_FD_ prefix.
> > > > diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h
> > > > index 3dcfc61..eae876e 100644
> > > > --- a/include/uapi/linux/v4l2-controls.h
> > > > +++ b/include/uapi/linux/v4l2-controls.h
> > > > @@ -192,6 +192,10 @@ enum v4l2_colorfx {
> > > > * We reserve 16 controls for this driver. */
> > > > #define V4L2_CID_USER_IMX_BASE (V4L2_CID_USER_BASE + 0x10b0)
> > > >
> > > > +/* The base for the mediatek FD driver controls */
> > > > +/* We reserve 16 controls for this driver. */
> > > > +#define V4L2_CID_USER_MTK_FD_BASE (V4L2_CID_USER_BASE + 0x10d0)
> > >
> > > Why only the base, but not the actual IDs in uapi ?
> > >
> > I will put actual IDs in uapi/ for user to reference.
> >
> > >
> > > --mtx
> > >
> >
>
> Best regards,
> Tomasz
Best regards,
Jerry
^ permalink raw reply
* [PATCH 0/6] Add support for Qualcomm SM8150 and SC7180 SoCs
From: Sibi Sankar @ 2019-07-29 12:06 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, vkoul, aneela
Cc: mark.rutland, agross, linux-kernel, linux-arm-msm, devicetree,
jassisinghbrar, clew, Sibi Sankar
This patch series adds SCM, APSS shared mailbox and QMP AOSS PD/clock
support on SM8150 and SC7180 SoCs.
Sibi Sankar (6):
soc: qcom: smem: Update max processor count
dt-bindings: firmware: scm: Add SM8150 and SC7180 support
dt-bindings: mailbox: Add APSS shared for SM8150 and SC7180 SoCs
mailbox: qcom: Add support for Qualcomm SM8150 and SC7180 SoCs
dt-bindings: soc: qcom: aoss: Add SM8150 and SC7180 support
soc: qcom: aoss: Add AOSS QMP support
Documentation/devicetree/bindings/firmware/qcom,scm.txt | 2 ++
.../devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt | 2 ++
Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt | 5 ++++-
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 2 ++
drivers/soc/qcom/qcom_aoss.c | 2 ++
drivers/soc/qcom/smem.c | 2 +-
6 files changed, 13 insertions(+), 2 deletions(-)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH 1/6] soc: qcom: smem: Update max processor count
From: Sibi Sankar @ 2019-07-29 12:06 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, vkoul, aneela
Cc: mark.rutland, agross, linux-kernel, linux-arm-msm, devicetree,
jassisinghbrar, clew, Sibi Sankar
In-Reply-To: <20190729120633.20451-1-sibis@codeaurora.org>
Update max processor count to reflect the number of
co-processors on SC7180 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/soc/qcom/smem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c
index f27c00d82ae49..bef8502625f96 100644
--- a/drivers/soc/qcom/smem.c
+++ b/drivers/soc/qcom/smem.c
@@ -84,7 +84,7 @@
#define SMEM_GLOBAL_HOST 0xfffe
/* Max number of processors/hosts in a system */
-#define SMEM_HOST_COUNT 10
+#define SMEM_HOST_COUNT 11
/**
* struct smem_proc_comm - proc_comm communication struct (legacy)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH 2/6] dt-bindings: firmware: scm: Add SM8150 and SC7180 support
From: Sibi Sankar @ 2019-07-29 12:06 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, vkoul, aneela
Cc: mark.rutland, agross, linux-kernel, linux-arm-msm, devicetree,
jassisinghbrar, clew, Sibi Sankar
In-Reply-To: <20190729120633.20451-1-sibis@codeaurora.org>
Add compatible for SM8150 and SC7180 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
Documentation/devicetree/bindings/firmware/qcom,scm.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
index 41f133a4e2fa7..5282ad3fc79d0 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
@@ -17,6 +17,8 @@ Required properties:
* "qcom,scm-msm8998"
* "qcom,scm-ipq4019"
* "qcom,scm-sdm845"
+ * "qcom,scm-sm8150"
+ * "qcom,scm-sc7180"
and:
* "qcom,scm"
- clocks: Specifies clocks needed by the SCM interface, if any:
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH 3/6] dt-bindings: mailbox: Add APSS shared for SM8150 and SC7180 SoCs
From: Sibi Sankar @ 2019-07-29 12:06 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, vkoul, aneela
Cc: mark.rutland, agross, linux-kernel, linux-arm-msm, devicetree,
jassisinghbrar, clew, Sibi Sankar
In-Reply-To: <20190729120633.20451-1-sibis@codeaurora.org>
Add SM8150 and SC7180 APSS shared to the list of possible bindings.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
.../devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
index 1232fc9fc709c..1e081dc3f2dae 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.txt
@@ -13,6 +13,8 @@ platforms.
"qcom,msm8998-apcs-hmss-global"
"qcom,qcs404-apcs-apps-global"
"qcom,sdm845-apss-shared"
+ "qcom,sm8150-apss-shared"
+ "qcom,sc7180-apss-shared"
- reg:
Usage: required
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH 4/6] mailbox: qcom: Add support for Qualcomm SM8150 and SC7180 SoCs
From: Sibi Sankar @ 2019-07-29 12:06 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, vkoul, aneela
Cc: mark.rutland, agross, linux-kernel, linux-arm-msm, devicetree,
jassisinghbrar, clew, Sibi Sankar
In-Reply-To: <20190729120633.20451-1-sibis@codeaurora.org>
Add the corresponding APSS shared offset for SM8150 and SC7180 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/mailbox/qcom-apcs-ipc-mailbox.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
index 705e17a5479cc..d5dbfd5f8417f 100644
--- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
+++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
@@ -119,6 +119,8 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = {
{ .compatible = "qcom,msm8998-apcs-hmss-global", .data = (void *)8 },
{ .compatible = "qcom,qcs404-apcs-apps-global", .data = (void *)8 },
{ .compatible = "qcom,sdm845-apss-shared", .data = (void *)12 },
+ { .compatible = "qcom,sm8150-apss-shared", .data = (void *)12 },
+ { .compatible = "qcom,sc7180-apss-shared", .data = (void *)12 },
{}
};
MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH 5/6] dt-bindings: soc: qcom: aoss: Add SM8150 and SC7180 support
From: Sibi Sankar @ 2019-07-29 12:06 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, vkoul, aneela
Cc: mark.rutland, agross, linux-kernel, linux-arm-msm, devicetree,
jassisinghbrar, clew, Sibi Sankar
In-Reply-To: <20190729120633.20451-1-sibis@codeaurora.org>
Add SM8150 and SC7180 AOSS QMP to the list of possible bindings.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt
index 954ffee0a9c45..91b972c1fee57 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.txt
@@ -15,7 +15,10 @@ power-domains.
- compatible:
Usage: required
Value type: <string>
- Definition: must be "qcom,sdm845-aoss-qmp"
+ Definition: must be one of:
+ "qcom,sdm845-aoss-qmp"
+ "qcom,sm8150-aoss-qmp"
+ "qcom,sc7180-aoss-qmp"
- reg:
Usage: required
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH 6/6] soc: qcom: aoss: Add AOSS QMP support
From: Sibi Sankar @ 2019-07-29 12:06 UTC (permalink / raw)
To: bjorn.andersson, robh+dt, vkoul, aneela
Cc: mark.rutland, agross, linux-kernel, linux-arm-msm, devicetree,
jassisinghbrar, clew, Sibi Sankar
In-Reply-To: <20190729120633.20451-1-sibis@codeaurora.org>
Add AOSS QMP support for SM8150 and SC7180 SoCs.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
drivers/soc/qcom/qcom_aoss.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c
index 5f885196f4d0f..e2f8c7c9a5a0a 100644
--- a/drivers/soc/qcom/qcom_aoss.c
+++ b/drivers/soc/qcom/qcom_aoss.c
@@ -462,6 +462,8 @@ static int qmp_remove(struct platform_device *pdev)
static const struct of_device_id qmp_dt_match[] = {
{ .compatible = "qcom,sdm845-aoss-qmp", },
+ { .compatible = "qcom,sm8150-aoss-qmp", },
+ { .compatible = "qcom,sc7180-aoss-qmp", },
{}
};
MODULE_DEVICE_TABLE(of, qmp_dt_match);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* Re: [PATCH V2 3/4] dt-bindings: thermal: qoriq: Add optional clocks property
From: Fabio Estevam @ 2019-07-29 12:21 UTC (permalink / raw)
To: Yongcai Huang
Cc: rui.zhang, Eduardo Valentin, Daniel Lezcano, Rob Herring,
Mark Rutland, linux-pm,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel, NXP Linux Team
In-Reply-To: <20190729083915.4855-3-Anson.Huang@nxp.com>
Hi Anson,
On Mon, Jul 29, 2019 at 6:04 AM <Anson.Huang@nxp.com> wrote:
>
> From: Anson Huang <Anson.Huang@nxp.com>
>
> Some platforms have clock control for TMU, add optional
> clocks property to the binding doc.
Please add a note that this is needed for i.MX8M.
^ permalink raw reply
* [PATCH v5 0/3] soc: ti: k3: Allow for exclusive and shared device requests
From: Lokesh Vutla @ 2019-07-29 12:24 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Rob Herring
Cc: Lokesh Vutla, Device Tree Mailing List, Sekhar Nori,
Linux ARM Mailing List
Sysfw provides an option for requesting exclusive access for a
device using the flags MSG_FLAG_DEVICE_EXCLUSIVE. If this flag is
not used, the device is meant to be shared across hosts. Once a device
is requested from a host with this flag set, any request to this
device from a different host will be nacked by sysfw.
Current tisci firmware and pm drivers always requests for device with
exclusive permissions set. But this is not be true for certain devices
that are expcted to be shared across different host contexts.
So add support for getting the shared or exclusive permissions from DT
and request firmware accordingly.
Changes since v4: https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=148371
- Split the driver and arch changes into a separate series.
- Added Reviewed-by from Nishanth M
- Rebased on top of v5.3-rc2
Lokesh Vutla (3):
firmware: ti_sci: Allow for device shared and exclusive requests
dt-bindings: ti_sci_pm_domains: Add support for exclusive and shared
access
soc: ti: ti_sci_pm_domains: Add support for exclusive and shared
access
.../bindings/soc/ti/sci-pm-domain.txt | 11 ++++-
MAINTAINERS | 1 +
drivers/firmware/ti_sci.c | 45 ++++++++++++++++++-
drivers/soc/ti/ti_sci_pm_domains.c | 23 +++++++++-
include/dt-bindings/soc/ti,sci_pm_domain.h | 9 ++++
include/linux/soc/ti/ti_sci_protocol.h | 3 ++
6 files changed, 86 insertions(+), 6 deletions(-)
create mode 100644 include/dt-bindings/soc/ti,sci_pm_domain.h
--
2.21.0
^ permalink raw reply
* [PATCH v5 1/3] firmware: ti_sci: Allow for device shared and exclusive requests
From: Lokesh Vutla @ 2019-07-29 12:24 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Rob Herring
Cc: Lokesh Vutla, Device Tree Mailing List, Sekhar Nori,
Linux ARM Mailing List
In-Reply-To: <20190729122453.32252-1-lokeshvutla@ti.com>
Sysfw provides an option for requesting exclusive access for a
device using the flags MSG_FLAG_DEVICE_EXCLUSIVE. If this flag is
not used, the device is meant to be shared across hosts. Once a device
is requested from a host with this flag set, any request to this
device from a different host will be nacked by sysfw. Current tisci
driver enables this flag for every device requests. But this may not
be true for all the devices. So provide a separate commands in driver
for exclusive and shared device requests.
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
drivers/firmware/ti_sci.c | 45 ++++++++++++++++++++++++--
include/linux/soc/ti/ti_sci_protocol.h | 3 ++
2 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index cdee0b45943d..4126be9e3216 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -635,6 +635,7 @@ static int ti_sci_get_device_state(const struct ti_sci_handle *handle,
/**
* ti_sci_cmd_get_device() - command to request for device managed by TISCI
+ * that can be shared with other hosts.
* @handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
* @id: Device Identifier
*
@@ -642,11 +643,29 @@ static int ti_sci_get_device_state(const struct ti_sci_handle *handle,
* usage count by balancing get_device with put_device. No refcounting is
* managed by driver for that purpose.
*
- * NOTE: The request is for exclusive access for the processor.
- *
* Return: 0 if all went fine, else return appropriate error.
*/
static int ti_sci_cmd_get_device(const struct ti_sci_handle *handle, u32 id)
+{
+ return ti_sci_set_device_state(handle, id, 0,
+ MSG_DEVICE_SW_STATE_ON);
+}
+
+/**
+ * ti_sci_cmd_get_device_exclusive() - command to request for device managed by
+ * TISCI that is exclusively owned by the
+ * requesting host.
+ * @handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
+ * @id: Device Identifier
+ *
+ * Request for the device - NOTE: the client MUST maintain integrity of
+ * usage count by balancing get_device with put_device. No refcounting is
+ * managed by driver for that purpose.
+ *
+ * Return: 0 if all went fine, else return appropriate error.
+ */
+static int ti_sci_cmd_get_device_exclusive(const struct ti_sci_handle *handle,
+ u32 id)
{
return ti_sci_set_device_state(handle, id,
MSG_FLAG_DEVICE_EXCLUSIVE,
@@ -665,6 +684,26 @@ static int ti_sci_cmd_get_device(const struct ti_sci_handle *handle, u32 id)
* Return: 0 if all went fine, else return appropriate error.
*/
static int ti_sci_cmd_idle_device(const struct ti_sci_handle *handle, u32 id)
+{
+ return ti_sci_set_device_state(handle, id, 0,
+ MSG_DEVICE_SW_STATE_RETENTION);
+}
+
+/**
+ * ti_sci_cmd_idle_device_exclusive() - Command to idle a device managed by
+ * TISCI that is exclusively owned by
+ * requesting host.
+ * @handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
+ * @id: Device Identifier
+ *
+ * Request for the device - NOTE: the client MUST maintain integrity of
+ * usage count by balancing get_device with put_device. No refcounting is
+ * managed by driver for that purpose.
+ *
+ * Return: 0 if all went fine, else return appropriate error.
+ */
+static int ti_sci_cmd_idle_device_exclusive(const struct ti_sci_handle *handle,
+ u32 id)
{
return ti_sci_set_device_state(handle, id,
MSG_FLAG_DEVICE_EXCLUSIVE,
@@ -2894,7 +2933,9 @@ static void ti_sci_setup_ops(struct ti_sci_info *info)
core_ops->reboot_device = ti_sci_cmd_core_reboot;
dops->get_device = ti_sci_cmd_get_device;
+ dops->get_device_exclusive = ti_sci_cmd_get_device_exclusive;
dops->idle_device = ti_sci_cmd_idle_device;
+ dops->idle_device_exclusive = ti_sci_cmd_idle_device_exclusive;
dops->put_device = ti_sci_cmd_put_device;
dops->is_valid = ti_sci_cmd_dev_is_valid;
diff --git a/include/linux/soc/ti/ti_sci_protocol.h b/include/linux/soc/ti/ti_sci_protocol.h
index 6c610e188a44..9531ec823298 100644
--- a/include/linux/soc/ti/ti_sci_protocol.h
+++ b/include/linux/soc/ti/ti_sci_protocol.h
@@ -97,7 +97,10 @@ struct ti_sci_core_ops {
*/
struct ti_sci_dev_ops {
int (*get_device)(const struct ti_sci_handle *handle, u32 id);
+ int (*get_device_exclusive)(const struct ti_sci_handle *handle, u32 id);
int (*idle_device)(const struct ti_sci_handle *handle, u32 id);
+ int (*idle_device_exclusive)(const struct ti_sci_handle *handle,
+ u32 id);
int (*put_device)(const struct ti_sci_handle *handle, u32 id);
int (*is_valid)(const struct ti_sci_handle *handle, u32 id);
int (*get_context_loss_count)(const struct ti_sci_handle *handle,
--
2.21.0
^ permalink raw reply related
* [PATCH v5 2/3] dt-bindings: ti_sci_pm_domains: Add support for exclusive and shared access
From: Lokesh Vutla @ 2019-07-29 12:24 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Rob Herring
Cc: Lokesh Vutla, Device Tree Mailing List, Sekhar Nori,
Linux ARM Mailing List
In-Reply-To: <20190729122453.32252-1-lokeshvutla@ti.com>
TISCI protocol supports for enabling the device either with exclusive
permissions for the requesting host or with sharing across the hosts.
There are certain devices which are exclusive to Linux context and
there are certain devices that are shared across different host contexts.
So add support for getting this information from DT by increasing
the power-domain cells to 2.
Acked-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
.../devicetree/bindings/soc/ti/sci-pm-domain.txt | 11 +++++++++--
MAINTAINERS | 1 +
include/dt-bindings/soc/ti,sci_pm_domain.h | 9 +++++++++
3 files changed, 19 insertions(+), 2 deletions(-)
create mode 100644 include/dt-bindings/soc/ti,sci_pm_domain.h
diff --git a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
index f7b00a7c0f68..f541d1f776a2 100644
--- a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+++ b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
@@ -19,8 +19,15 @@ child of the pmmc node.
Required Properties:
--------------------
- compatible: should be "ti,sci-pm-domain"
-- #power-domain-cells: Must be 1 so that an id can be provided in each
- device node.
+- #power-domain-cells: Can be one of the following:
+ 1: Containing the device id of each node
+ 2: First entry should be device id
+ Second entry should be one of the floowing:
+ TI_SCI_PD_EXCLUSIVE: To allow device to be
+ exclusively controlled by
+ the requesting hosts.
+ TI_SCI_PD_SHARED: To allow device to be shared
+ by multiple hosts.
Example (K2G):
-------------
diff --git a/MAINTAINERS b/MAINTAINERS
index 6426db5198f0..fe7406427023 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15853,6 +15853,7 @@ F: drivers/firmware/ti_sci*
F: include/linux/soc/ti/ti_sci_protocol.h
F: Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
F: drivers/soc/ti/ti_sci_pm_domains.c
+F: include/dt-bindings/soc/ti,sci_pm_domain.h
F: Documentation/devicetree/bindings/reset/ti,sci-reset.txt
F: Documentation/devicetree/bindings/clock/ti,sci-clk.txt
F: drivers/clk/keystone/sci-clk.c
diff --git a/include/dt-bindings/soc/ti,sci_pm_domain.h b/include/dt-bindings/soc/ti,sci_pm_domain.h
new file mode 100644
index 000000000000..8f2a7360b65e
--- /dev/null
+++ b/include/dt-bindings/soc/ti,sci_pm_domain.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __DT_BINDINGS_TI_SCI_PM_DOMAIN_H
+#define __DT_BINDINGS_TI_SCI_PM_DOMAIN_H
+
+#define TI_SCI_PD_EXCLUSIVE 1
+#define TI_SCI_PD_SHARED 0
+
+#endif /* __DT_BINDINGS_TI_SCI_PM_DOMAIN_H */
--
2.21.0
^ permalink raw reply related
* [PATCH v5 3/3] soc: ti: ti_sci_pm_domains: Add support for exclusive and shared access
From: Lokesh Vutla @ 2019-07-29 12:24 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Rob Herring
Cc: Lokesh Vutla, Device Tree Mailing List, Sekhar Nori,
Linux ARM Mailing List
In-Reply-To: <20190729122453.32252-1-lokeshvutla@ti.com>
TISCI protocol supports for enabling the device either with exclusive
permissions for the requesting host or with sharing across the hosts.
There are certain devices which are exclusive to Linux context and
there are certain devices that are shared across different host contexts.
So add support for getting this information from DT by increasing
the power-domain cells to 2.
For keeping the DT backward compatibility intact, defaulting the
device permissions to set the exclusive flag set. In this case the
power-domain-cells is 1.
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
drivers/soc/ti/ti_sci_pm_domains.c | 23 +++++++++++++++++++++--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/ti/ti_sci_pm_domains.c b/drivers/soc/ti/ti_sci_pm_domains.c
index 97817dd7ba24..8c2a2f23982c 100644
--- a/drivers/soc/ti/ti_sci_pm_domains.c
+++ b/drivers/soc/ti/ti_sci_pm_domains.c
@@ -15,15 +15,19 @@
#include <linux/pm_domain.h>
#include <linux/slab.h>
#include <linux/soc/ti/ti_sci_protocol.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
/**
* struct ti_sci_genpd_dev_data: holds data needed for every device attached
* to this genpd
* @idx: index of the device that identifies it with the system
* control processor.
+ * @exclusive: Permissions for exclusive request or shared request of the
+ * device.
*/
struct ti_sci_genpd_dev_data {
int idx;
+ u8 exclusive;
};
/**
@@ -55,6 +59,14 @@ static int ti_sci_dev_id(struct device *dev)
return sci_dev_data->idx;
}
+static u8 is_ti_sci_dev_exclusive(struct device *dev)
+{
+ struct generic_pm_domain_data *genpd_data = dev_gpd_data(dev);
+ struct ti_sci_genpd_dev_data *sci_dev_data = genpd_data->data;
+
+ return sci_dev_data->exclusive;
+}
+
/**
* ti_sci_dev_to_sci_handle(): get pointer to ti_sci_handle
* @dev: pointer to device associated with this genpd
@@ -79,7 +91,10 @@ static int ti_sci_dev_start(struct device *dev)
const struct ti_sci_handle *ti_sci = ti_sci_dev_to_sci_handle(dev);
int idx = ti_sci_dev_id(dev);
- return ti_sci->ops.dev_ops.get_device(ti_sci, idx);
+ if (is_ti_sci_dev_exclusive(dev))
+ return ti_sci->ops.dev_ops.get_device_exclusive(ti_sci, idx);
+ else
+ return ti_sci->ops.dev_ops.get_device(ti_sci, idx);
}
/**
@@ -110,7 +125,7 @@ static int ti_sci_pd_attach_dev(struct generic_pm_domain *domain,
if (ret < 0)
return ret;
- if (pd_args.args_count != 1)
+ if (pd_args.args_count != 1 && pd_args.args_count != 2)
return -EINVAL;
idx = pd_args.args[0];
@@ -128,6 +143,10 @@ static int ti_sci_pd_attach_dev(struct generic_pm_domain *domain,
return -ENOMEM;
sci_dev_data->idx = idx;
+ /* Enable the exclusive permissions by default */
+ sci_dev_data->exclusive = TI_SCI_PD_EXCLUSIVE;
+ if (pd_args.args_count == 2)
+ sci_dev_data->exclusive = pd_args.args[1] & 0x1;
genpd_data = dev_gpd_data(dev);
genpd_data->data = sci_dev_data;
--
2.21.0
^ permalink raw reply related
* [PATCH v5 0/2] arm64: dts: ti: k3: Update the power-domain cells
From: Lokesh Vutla @ 2019-07-29 12:30 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Rob Herring
Cc: Lokesh Vutla, Device Tree Mailing List, Sekhar Nori,
Linux ARM Mailing List
Update the power-domains cells on all K3 based devices to reflect
exclusive and shared permissions in each device.
Changes since v4: https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=148371
- Split the dts changes into a separate series.
- Added Reviewed-by from Nishanth M
- Rebased on top of v5.3-rc2
Lokesh Vutla (2):
arm64: dts: ti: k3-am654: Update the power domain cells
arm64: dts: ti: k3-j721e: Update the power domain cells
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 44 +++++++++----------
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 10 ++---
arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 6 +--
arch/arm64/boot/dts/ti/k3-am65.dtsi | 1 +
.../arm64/boot/dts/ti/k3-am654-base-board.dts | 1 +
.../dts/ti/k3-j721e-common-proc-board.dts | 4 ++
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 20 ++++-----
.../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 6 +--
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 +
9 files changed, 50 insertions(+), 43 deletions(-)
--
2.22.0
^ permalink raw reply
* [PATCH v5 1/2] arm64: dts: ti: k3-am654: Update the power domain cells
From: Lokesh Vutla @ 2019-07-29 12:30 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Rob Herring
Cc: Lokesh Vutla, Device Tree Mailing List, Sekhar Nori,
Linux ARM Mailing List
In-Reply-To: <20190729123023.32702-1-lokeshvutla@ti.com>
Update the power-domain cells to 2 and mark all devices as
exclusive. Main uart 0 is the debug console for based boards
and it is used by different software entities like u-boot, atf,
linux. So just mark main_uart0 as shared device for base board.
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 44 +++++++++----------
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 10 ++---
arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 6 +--
arch/arm64/boot/dts/ti/k3-am65.dtsi | 1 +
.../arm64/boot/dts/ti/k3-am654-base-board.dts | 1 +
5 files changed, 32 insertions(+), 30 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index ca70ff73f171..12a977f1ab87 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -67,7 +67,7 @@
reg = <0x0 0x900000 0x0 0x2000>;
reg-names = "serdes";
#phy-cells = <2>;
- power-domains = <&k3_pds 153>;
+ power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
@@ -82,7 +82,7 @@
reg = <0x0 0x910000 0x0 0x2000>;
reg-names = "serdes";
#phy-cells = <2>;
- power-domains = <&k3_pds 154>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
@@ -100,7 +100,7 @@
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 146>;
+ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
};
main_uart1: serial@2810000 {
@@ -110,7 +110,7 @@
reg-io-width = <4>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- power-domains = <&k3_pds 147>;
+ power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
};
main_uart2: serial@2820000 {
@@ -120,7 +120,7 @@
reg-io-width = <4>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
- power-domains = <&k3_pds 148>;
+ power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
};
main_pmx0: pinmux@11c000 {
@@ -147,7 +147,7 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 110 1>;
- power-domains = <&k3_pds 110>;
+ power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c1: i2c@2010000 {
@@ -158,7 +158,7 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 111 1>;
- power-domains = <&k3_pds 111>;
+ power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c2: i2c@2020000 {
@@ -169,7 +169,7 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 112 1>;
- power-domains = <&k3_pds 112>;
+ power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
};
main_i2c3: i2c@2030000 {
@@ -180,14 +180,14 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 113 1>;
- power-domains = <&k3_pds 113>;
+ power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
};
ecap0: pwm@3100000 {
compatible = "ti,am654-ecap", "ti,am3352-ecap";
#pwm-cells = <3>;
reg = <0x0 0x03100000 0x0 0x60>;
- power-domains = <&k3_pds 39>;
+ power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 39 0>;
clock-names = "fck";
};
@@ -197,7 +197,7 @@
reg = <0x0 0x2100000 0x0 0x400>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 137 1>;
- power-domains = <&k3_pds 137>;
+ power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
@@ -207,7 +207,7 @@
reg = <0x0 0x2110000 0x0 0x400>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 138 1>;
- power-domains = <&k3_pds 138>;
+ power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
assigned-clocks = <&k3_clks 137 1>;
@@ -219,7 +219,7 @@
reg = <0x0 0x2120000 0x0 0x400>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 139 1>;
- power-domains = <&k3_pds 139>;
+ power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
@@ -229,7 +229,7 @@
reg = <0x0 0x2130000 0x0 0x400>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 140 1>;
- power-domains = <&k3_pds 140>;
+ power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
@@ -239,7 +239,7 @@
reg = <0x0 0x2140000 0x0 0x400>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 141 1>;
- power-domains = <&k3_pds 141>;
+ power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
@@ -247,7 +247,7 @@
sdhci0: sdhci@4f80000 {
compatible = "ti,am654-sdhci-5.1";
reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
- power-domains = <&k3_pds 47>;
+ power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
clock-names = "clk_ahb", "clk_xin";
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
@@ -306,7 +306,7 @@
ranges = <0x0 0x0 0x4000000 0x20000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
- power-domains = <&k3_pds 151>;
+ power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
<&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
@@ -345,7 +345,7 @@
ranges = <0x0 0x0 0x4020000 0x20000>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
- power-domains = <&k3_pds 152>;
+ power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
assigned-clocks = <&k3_clks 152 2>;
assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
@@ -451,7 +451,7 @@
compatible = "ti,am654-pcie-rc";
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
reg-names = "app", "dbics", "config", "atu";
- power-domains = <&k3_pds 120>;
+ power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000
@@ -470,7 +470,7 @@
compatible = "ti,am654-pcie-ep";
reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
reg-names = "app", "dbics", "addr_space", "atu";
- power-domains = <&k3_pds 120>;
+ power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
ti,syscon-pcie-mode = <&pcie0_mode>;
num-ib-windows = <16>;
num-ob-windows = <16>;
@@ -483,7 +483,7 @@
compatible = "ti,am654-pcie-rc";
reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
reg-names = "app", "dbics", "config", "atu";
- power-domains = <&k3_pds 121>;
+ power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000
@@ -502,7 +502,7 @@
compatible = "ti,am654-pcie-ep";
reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
reg-names = "app", "dbics", "addr_space", "atu";
- power-domains = <&k3_pds 121>;
+ power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>;
ti,syscon-pcie-mode = <&pcie1_mode>;
num-ib-windows = <16>;
num-ob-windows = <16>;
diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
index afc29eaa2638..7bdf5342f58f 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
@@ -14,7 +14,7 @@
interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 149>;
+ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
};
mcu_ram: sram@41c00000 {
@@ -33,7 +33,7 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 114 1>;
- power-domains = <&k3_pds 114>;
+ power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
};
mcu_spi0: spi@40300000 {
@@ -41,7 +41,7 @@
reg = <0x0 0x40300000 0x0 0x400>;
interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 142 1>;
- power-domains = <&k3_pds 142>;
+ power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
@@ -51,7 +51,7 @@
reg = <0x0 0x40310000 0x0 0x400>;
interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 143 1>;
- power-domains = <&k3_pds 143>;
+ power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
@@ -61,7 +61,7 @@
reg = <0x0 0x40320000 0x0 0x400>;
interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&k3_clks 144 1>;
- power-domains = <&k3_pds 144>;
+ power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
};
diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
index 9cf2c0849a24..f4227e2743f2 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
@@ -20,7 +20,7 @@
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
- #power-domain-cells = <1>;
+ #power-domain-cells = <2>;
};
k3_clks: clocks {
@@ -50,7 +50,7 @@
interrupts = <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 150>;
+ power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
};
wkup_i2c0: i2c@42120000 {
@@ -61,7 +61,7 @@
#size-cells = <0>;
clock-names = "fck";
clocks = <&k3_clks 115 1>;
- power-domains = <&k3_pds 115>;
+ power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
};
intr_wkup_gpio: interrupt-controller2 {
diff --git a/arch/arm64/boot/dts/ti/k3-am65.dtsi b/arch/arm64/boot/dts/ti/k3-am65.dtsi
index 82edf10b2378..6dfccd5d56c8 100644
--- a/arch/arm64/boot/dts/ti/k3-am65.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
/ {
model = "Texas Instruments K3 AM654 SoC";
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index 52c245d36db9..1102b84f853d 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -151,6 +151,7 @@
&main_uart0 {
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
+ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};
&wkup_i2c0 {
--
2.22.0
^ permalink raw reply related
* [PATCH v5 2/2] arm64: dts: ti: k3-j721e: Update the power domain cells
From: Lokesh Vutla @ 2019-07-29 12:30 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Rob Herring
Cc: Lokesh Vutla, Device Tree Mailing List, Sekhar Nori,
Linux ARM Mailing List
In-Reply-To: <20190729123023.32702-1-lokeshvutla@ti.com>
Update the power-domain cells to 2 and mark all devices as
exclusive. Main uart 0 is the debug console for processor boards
and it is used by different software entities like u-boot, atf,
linux simultaneously. So just mark main_uart0 as shared device
for common processor board.
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
.../dts/ti/k3-j721e-common-proc-board.dts | 4 ++++
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 20 +++++++++----------
.../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 6 +++---
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 +
4 files changed, 18 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index c680123f067c..63b47b839388 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -19,6 +19,10 @@
status = "disabled";
};
+&main_uart0 {
+ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
+};
+
&main_uart3 {
/* UART not brought out */
status = "disabled";
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index a01308142f77..01661c22c39d 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -119,7 +119,7 @@
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 146>;
+ power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 146 0>;
clock-names = "fclk";
};
@@ -132,7 +132,7 @@
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 278>;
+ power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 278 0>;
clock-names = "fclk";
};
@@ -145,7 +145,7 @@
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 279>;
+ power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 279 0>;
clock-names = "fclk";
};
@@ -158,7 +158,7 @@
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 280>;
+ power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 280 0>;
clock-names = "fclk";
};
@@ -171,7 +171,7 @@
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 281>;
+ power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 281 0>;
clock-names = "fclk";
};
@@ -184,7 +184,7 @@
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 282>;
+ power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 282 0>;
clock-names = "fclk";
};
@@ -197,7 +197,7 @@
interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 283>;
+ power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 283 0>;
clock-names = "fclk";
};
@@ -210,7 +210,7 @@
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 284>;
+ power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 284 0>;
clock-names = "fclk";
};
@@ -223,7 +223,7 @@
interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 285>;
+ power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 285 0>;
clock-names = "fclk";
};
@@ -236,7 +236,7 @@
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 286>;
+ power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 286 0>;
clock-names = "fclk";
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index 07b58eeebceb..e616c2481f51 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -20,7 +20,7 @@
k3_pds: power-controller {
compatible = "ti,sci-pm-domain";
- #power-domain-cells = <1>;
+ #power-domain-cells = <2>;
};
k3_clks: clocks {
@@ -59,7 +59,7 @@
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 287>;
+ power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 287 0>;
clock-names = "fclk";
};
@@ -72,7 +72,7 @@
interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <96000000>;
current-speed = <115200>;
- power-domains = <&k3_pds 149>;
+ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 149 0>;
clock-names = "fclk";
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index f8dd74b17bfb..43ea1ba97922 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/soc/ti,sci_pm_domain.h>
/ {
model = "Texas Instruments K3 J721E SoC";
--
2.22.0
^ permalink raw reply related
* Re: [PATCH V2 4/4] thermal: qoriq: Add clock operations
From: Fabio Estevam @ 2019-07-29 12:30 UTC (permalink / raw)
To: Yongcai Huang
Cc: rui.zhang, Eduardo Valentin, Daniel Lezcano, Rob Herring,
Mark Rutland, linux-pm,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel, NXP Linux Team
In-Reply-To: <20190729083915.4855-4-Anson.Huang@nxp.com>
Hi Anson,
On Mon, Jul 29, 2019 at 6:04 AM <Anson.Huang@nxp.com> wrote:
>
> From: Anson Huang <Anson.Huang@nxp.com>
>
> Some platforms like i.MX8MQ has clock control for this module,
> need to add clock operations to make sure the driver is working
> properly.
I haven't seen this series earlier, and I have sent a similar patch
for Guido to test.
Since this patch solves a hang problem, I would suggest that this one
becomes the first of the series.
Also, the "clk: imx8mq: Remove CLK_IS_CRITICAL flag for
IMX8MQ_CLK_TMU_ROOT" should only be applied after this one in order to
avoid the hang.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> Reviewed-by: Guido Günther <agx@sigxcpu.org>
> ---
> Changes since V1:
> - use devm_clk_get_optional() instead of devm_clk_get().
> ---
> drivers/thermal/qoriq_thermal.c | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/drivers/thermal/qoriq_thermal.c b/drivers/thermal/qoriq_thermal.c
> index 2b2f79b..0ae45c0 100644
> --- a/drivers/thermal/qoriq_thermal.c
> +++ b/drivers/thermal/qoriq_thermal.c
> @@ -2,6 +2,7 @@
> //
> // Copyright 2016 Freescale Semiconductor, Inc.
>
> +#include <linux/clk.h>
> #include <linux/module.h>
> #include <linux/platform_device.h>
> #include <linux/err.h>
> @@ -72,6 +73,7 @@ struct qoriq_sensor {
>
> struct qoriq_tmu_data {
> struct qoriq_tmu_regs __iomem *regs;
> + struct clk *clk;
> bool little_endian;
> struct qoriq_sensor *sensor[SITES_MAX];
> };
> @@ -208,6 +210,16 @@ static int qoriq_tmu_probe(struct platform_device *pdev)
> return PTR_ERR(data->regs);
> }
>
> + data->clk = devm_clk_get_optional(&pdev->dev, NULL);
> + if (IS_ERR(data->clk))
> + return PTR_ERR(data->clk);
> +
> + ret = clk_prepare_enable(data->clk);
> + if (ret) {
> + dev_err(&pdev->dev, "Failed to enable clock\n");
> + return ret;
> + }
> +
> qoriq_tmu_init_device(data); /* TMU initialization */
>
> ret = qoriq_tmu_calibration(pdev); /* TMU calibration */
In case of failure the TMU clock should be disabled in the error path.
Thanks
^ permalink raw reply
* Re: [PATCH V2 3/4] dt-bindings: thermal: qoriq: Add optional clocks property
From: Daniel Baluta @ 2019-07-29 12:31 UTC (permalink / raw)
To: linux-kernel@vger.kernel.org, robh+dt@kernel.org,
rui.zhang@intel.com, edubezval@gmail.com,
devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
daniel.lezcano@linaro.org, mark.rutland@arm.com, Anson Huang
Cc: dl-linux-imx
In-Reply-To: <20190729083915.4855-3-Anson.Huang@nxp.com>
On Mon, 2019-07-29 at 16:39 +0800, Anson.Huang@nxp.com wrote:
> From: Anson Huang <Anson.Huang@nxp.com>
>
> Some platforms have clock control for TMU, add optional
> clocks property to the binding doc.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Please also pick Rob's Reviewed-by from last revision.
> ---
> No changes.
> ---
> Documentation/devicetree/bindings/thermal/qoriq-thermal.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/thermal/qoriq-
> thermal.txt b/Documentation/devicetree/bindings/thermal/qoriq-
> thermal.txt
> index 04cbb90..28f2cba 100644
> --- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.txt
> @@ -23,6 +23,7 @@ Required properties:
> Optional property:
> - little-endian : If present, the TMU registers are little endian.
> If absent,
> the default is big endian.
> +- clocks : the clock for clocking the TMU silicon.
>
> Example:
>
^ permalink raw reply
* Re: [PATCH] dt-bindings: imx: i.MX8MN: Use space instead of tab
From: Fabio Estevam @ 2019-07-29 12:44 UTC (permalink / raw)
To: Guido Günther
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, NXP Linux Team,
linux-clk,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
linux-kernel
In-Reply-To: <35f999387bca037731dd963a5901909d6e6d0a17.1564226824.git.agx@sigxcpu.org>
Hi Guido,
On Sat, Jul 27, 2019 at 8:29 AM Guido Günther <agx@sigxcpu.org> wrote:
>
> This fixes 'make dt_binding_check'
>
> Signed-off-by: Guido Günther <agx@sigxcpu.org>
Thanks for the patch, but Anson has already submitted a fix for this issue:
https://patchwork.kernel.org/patch/11057815/
^ permalink raw reply
* Re: [PATCH v4] arm64: dts: imx8mq: Init rates and parents configs for clocks
From: Guido Günther @ 2019-07-29 12:48 UTC (permalink / raw)
To: Daniel Baluta
Cc: shawnguo, devicetree, baruch, abel.vesa, Anson.Huang, ccaione,
andrew.smirnov, s.hauer, angus, linux-kernel, linux-imx, festevam,
shengjiu.wang, linux-arm-kernel, l.stach
In-Reply-To: <20190728152040.15323-1-daniel.baluta@nxp.com>
Hi,
On Sun, Jul 28, 2019 at 06:20:40PM +0300, Daniel Baluta wrote:
> From: Abel Vesa <abel.vesa@nxp.com>
>
> Add the initial configuration for clocks that need default parent and rate
> setting. This is based on the vendor tree clock provider parents and rates
> configuration except this is doing the setup in dts rather then using clock
> consumer API in a clock provider driver.
>
> Note that by adding the initial rate setting for audio_pll1/audio_pll
> setting we need to remove it from imx8mq-librem5-devkit.dts
>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
> Tested-by: Angus Ainslie (Purism) <angus@akkea.ca>
> ---
> Changes since v3:
> - fix extra new lines
>
> .../dts/freescale/imx8mq-librem5-devkit.dts | 5 -----
> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 19 +++++++++++++++++++
> 2 files changed, 19 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
> index 683a11035643..c702ccc82867 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
> @@ -169,11 +169,6 @@
> };
> };
>
> -&clk {
> - assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>;
> - assigned-clock-rates = <786432000>, <722534400>;
> -};
> -
> &dphy {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> index 02fbd0625318..a55d72ba2e05 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -494,6 +494,25 @@
> clock-names = "ckil", "osc_25m", "osc_27m",
> "clk_ext1", "clk_ext2",
> "clk_ext3", "clk_ext4";
> + assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1>,
> + <&clk IMX8MQ_AUDIO_PLL1>,
> + <&clk IMX8MQ_AUDIO_PLL2>,
> + <&clk IMX8MQ_CLK_AHB>,
> + <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,
> + <&clk IMX8MQ_CLK_AUDIO_AHB>,
> + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
> + <&clk IMX8MQ_CLK_NOC>;
> + assigned-clock-parents = <0>,
> + <0>,
> + <0>,
> + <&clk IMX8MQ_SYS1_PLL_133M>,
> + <&clk IMX8MQ_SYS1_PLL_266M>,
> + <&clk IMX8MQ_SYS2_PLL_500M>,
> + <&clk IMX8MQ_CLK_27M>,
> + <&clk IMX8MQ_SYS1_PLL_800M>;
> + assigned-clock-rates = <593999999>,
> + <786432000>,
> + <722534400>;
> };
>
> src: reset-controller@30390000 {
Tested-by: Guido Günther <agx@sigxcpu.org>
Cheers,
-- Guido
^ permalink raw reply
* Re: [PATCH 2/3] arm64: dts: meson-gx: add video decoder entry
From: Neil Armstrong @ 2019-07-29 13:05 UTC (permalink / raw)
To: Maxime Jourdan, Kevin Hilman
Cc: linux-amlogic, linux-kernel, linux-arm-kernel, devicetree
In-Reply-To: <20190726124639.7713-3-mjourdan@baylibre.com>
On 26/07/2019 14:46, Maxime Jourdan wrote:
> Add the base video decoder node compatible with the meson vdec driver,
> for GX* chips.
>
> Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
> ---
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> index 74d03fc706be..86e26ed551e0 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> @@ -437,6 +437,20 @@
> };
> };
>
> + vdec: video-codec@c8820000 {
> + compatible = "amlogic,gx-vdec";
> + reg = <0x0 0xc8820000 0x0 0x10000>,
> + <0x0 0xc110a580 0x0 0xe4>;
> + reg-names = "dos", "esparser";
> +
> + interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>;
> + interrupt-names = "vdec", "esparser";
> +
> + amlogic,ao-sysctrl = <&sysctrl_AO>;
> + amlogic,canvas = <&canvas>;
> + };
> +
> periphs: periphs@c8834000 {
> compatible = "simple-bus";
> reg = <0x0 0xc8834000 0x0 0x2000>;
>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
^ permalink raw reply
* Re: [PATCH 3/3] arm64: dts: meson: add video decoder entries
From: Neil Armstrong @ 2019-07-29 13:05 UTC (permalink / raw)
To: Maxime Jourdan, Kevin Hilman
Cc: linux-amlogic, linux-kernel, linux-arm-kernel, devicetree
In-Reply-To: <20190726124639.7713-4-mjourdan@baylibre.com>
On 26/07/2019 14:46, Maxime Jourdan wrote:
> This enables the video decoder for GXBB, GXL and GXM chips
>
> Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
> ---
> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 11 +++++++++++
> arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 11 +++++++++++
> arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 4 ++++
> 3 files changed, 26 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> index f734faaf7b78..0cb40326b0d3 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
> @@ -845,3 +845,14 @@
> compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
> power-domains = <&pwrc_vpu>;
> };
> +
> +&vdec {
> + compatible = "amlogic,gxbb-vdec", "amlogic,gx-vdec";
> + clocks = <&clkc CLKID_DOS_PARSER>,
> + <&clkc CLKID_DOS>,
> + <&clkc CLKID_VDEC_1>,
> + <&clkc CLKID_VDEC_HEVC>;
> + clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
> + resets = <&reset RESET_PARSER>;
> + reset-names = "esparser";
> +};
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
> index c959456bacc6..a09c53aaa0e8 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
> @@ -848,3 +848,14 @@
> compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
> power-domains = <&pwrc_vpu>;
> };
> +
> +&vdec {
> + compatible = "amlogic,gxl-vdec", "amlogic,gx-vdec";
> + clocks = <&clkc CLKID_DOS_PARSER>,
> + <&clkc CLKID_DOS>,
> + <&clkc CLKID_VDEC_1>,
> + <&clkc CLKID_VDEC_HEVC>;
> + clock-names = "dos_parser", "dos", "vdec_1", "vdec_hevc";
> + resets = <&reset RESET_PARSER>;
> + reset-names = "esparser";
> +};
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
> index 7a85a82bf65d..a0e677d5a8f7 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
> @@ -144,3 +144,7 @@
> &dwc3 {
> phys = <&usb3_phy>, <&usb2_phy0>, <&usb2_phy1>, <&usb2_phy2>;
> };
> +
> +&vdec {
> + compatible = "amlogic,gxm-vdec", "amlogic,gx-vdec";
> +};
>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: media: amlogic,vdec: add default compatible
From: Neil Armstrong @ 2019-07-29 13:06 UTC (permalink / raw)
To: Maxime Jourdan, Kevin Hilman
Cc: linux-amlogic, linux-kernel, linux-arm-kernel, devicetree
In-Reply-To: <20190726124639.7713-2-mjourdan@baylibre.com>
On 26/07/2019 14:46, Maxime Jourdan wrote:
> The first version of the bindings is missing a generic compatible that
> is used by the base node (GX), and then extended by the SoC device trees
> (GXBB, GXL, GXM)
>
> Also change the example to use "video-codec" instead of "video-decoder",
> as the former is the one used in almost all cases when it comes to video
> decode/encode accelerators.
>
> Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
> ---
> Documentation/devicetree/bindings/media/amlogic,vdec.txt | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/media/amlogic,vdec.txt b/Documentation/devicetree/bindings/media/amlogic,vdec.txt
> index aabdd01bcf32..9b6aace86ca7 100644
> --- a/Documentation/devicetree/bindings/media/amlogic,vdec.txt
> +++ b/Documentation/devicetree/bindings/media/amlogic,vdec.txt
> @@ -26,6 +26,7 @@ Required properties:
> - GXBB (S905) : "amlogic,gxbb-vdec"
> - GXL (S905X, S905D) : "amlogic,gxl-vdec"
> - GXM (S912) : "amlogic,gxm-vdec"
> + followed by the common "amlogic,gx-vdec"
> - reg: base address and size of he following memory-mapped regions :
> - dos
> - esparser
> @@ -47,8 +48,8 @@ Required properties:
>
> Example:
>
> -vdec: video-decoder@c8820000 {
> - compatible = "amlogic,gxbb-vdec";
> +vdec: video-codec@c8820000 {
> + compatible = "amlogic,gxbb-vdec", "amlogic,gx-vdec";
> reg = <0x0 0xc8820000 0x0 0x10000>,
> <0x0 0xc110a580 0x0 0xe4>;
> reg-names = "dos", "esparser";
>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
^ permalink raw reply
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