* [PATCH 5/6] arm64: dts: amlogic: odroid-n2: add minimal thermal zone
From: Guillaume La Roque @ 2019-07-31 12:14 UTC (permalink / raw)
To: daniel.lezcano, khilman
Cc: linux-pm, devicetree, linux-amlogic, linux-kernel,
linux-arm-kernel
In-Reply-To: <20190731121409.17285-1-glaroque@baylibre.com>
Add minimal thermal zone for DDR and CPU sensor
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
---
.../arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts
index 81780ffcc7f0..4bd8d6d0c972 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-g12b-odroid-n2.dts
@@ -20,6 +20,19 @@
ethernet0 = ðmac;
};
+ thermal-zones {
+ soc_thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ thermal-sensors = <&cpu_temp 0>;
+ };
+ ddr_thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ thermal-sensors = <&ddr_temp 1>;
+ };
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
--
2.17.1
^ permalink raw reply related
* [PATCH 4/6] arm64: dts: meson: sei510: Add minimal thermal zone
From: Guillaume La Roque @ 2019-07-31 12:14 UTC (permalink / raw)
To: daniel.lezcano, khilman
Cc: linux-pm, devicetree, linux-amlogic, linux-kernel,
linux-arm-kernel
In-Reply-To: <20190731121409.17285-1-glaroque@baylibre.com>
Add minimal thermal zone for DDR and CPU sensor
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts
index c7a87368850b..79ae514e238d 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts
@@ -33,6 +33,19 @@
ethernet0 = ðmac;
};
+ thermal-zones {
+ soc_thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ thermal-sensors = <&cpu_temp 0>;
+ };
+ ddr_thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <100>;
+ thermal-sensors = <&ddr_temp 1>;
+ };
+ };
+
mono_dac: audio-codec-0 {
compatible = "maxim,max98357a";
#sound-dai-cells = <0>;
--
2.17.1
^ permalink raw reply related
* [PATCH 3/6] arm64: dts: amlogic: g12: add temperature sensor
From: Guillaume La Roque @ 2019-07-31 12:14 UTC (permalink / raw)
To: daniel.lezcano, khilman
Cc: linux-pm, devicetree, linux-amlogic, linux-kernel,
linux-arm-kernel
In-Reply-To: <20190731121409.17285-1-glaroque@baylibre.com>
Add cpu and ddr temperature sensors for G12 Socs
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
---
.../boot/dts/amlogic/meson-g12-common.dtsi | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
index 06e186ca41e3..e10aba5c9270 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
@@ -1353,6 +1353,28 @@
};
};
+ cpu_temp: temperature-sensor@34800 {
+ compatible = "amlogic,g12-cpu-thermal",
+ "amlogic,g12-thermal";
+ reg = <0x0 0x34800 0x0 0x50>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc CLKID_TS>;
+ status = "okay";
+ #thermal-sensor-cells = <1>;
+ amlogic,ao-secure = <&sec_AO>;
+ };
+
+ ddr_temp: temperature-sensor@34c00 {
+ compatible = "amlogic,g12-ddr-thermal",
+ "amlogic,g12-thermal";
+ reg = <0x0 0x34c00 0x0 0x50>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&clkc CLKID_TS>;
+ status = "okay";
+ #thermal-sensor-cells = <1>;
+ amlogic,ao-secure = <&sec_AO>;
+ };
+
usb2_phy0: phy@36000 {
compatible = "amlogic,g12a-usb2-phy";
reg = <0x0 0x36000 0x0 0x2000>;
--
2.17.1
^ permalink raw reply related
* [PATCH 2/6] thermal: amlogic: Add thermal driver to support G12 SoCs
From: Guillaume La Roque @ 2019-07-31 12:14 UTC (permalink / raw)
To: daniel.lezcano, khilman
Cc: devicetree, linux-amlogic, linux-kernel, linux-arm-kernel,
linux-pm
In-Reply-To: <20190731121409.17285-1-glaroque@baylibre.com>
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
---
drivers/thermal/Kconfig | 12 +-
drivers/thermal/Makefile | 1 +
drivers/thermal/amlogic_thermal.c | 335 ++++++++++++++++++++++++++++++
3 files changed, 347 insertions(+), 1 deletion(-)
create mode 100644 drivers/thermal/amlogic_thermal.c
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 9966364a6deb..2332ef1bfafc 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -1,4 +1,3 @@
-# SPDX-License-Identifier: GPL-2.0-only
#
# Generic thermal sysfs drivers configuration
#
@@ -348,6 +347,17 @@ config MTK_THERMAL
Enable this option if you want to have support for thermal management
controller present in Mediatek SoCs
+config AMLOGIC_THERMAL
+ tristate "Amlogic Thermal Support"
+ default ARCH_MESON
+ depends on OF && ARCH_MESON
+ help
+ If you say yes here you get support for Amlogic Thermal
+ for G12 SoC Family.
+
+ This driver can also be built as a module. If so, the module will
+ be called amlogic_thermal.
+
menu "Intel thermal drivers"
depends on X86 || X86_INTEL_QUARK || COMPILE_TEST
source "drivers/thermal/intel/Kconfig"
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index 74a37c7f847a..baeb70bf0568 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -54,3 +54,4 @@ obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o
obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o
obj-$(CONFIG_ZX2967_THERMAL) += zx2967_thermal.o
obj-$(CONFIG_UNIPHIER_THERMAL) += uniphier_thermal.o
+obj-$(CONFIG_AMLOGIC_THERMAL) += amlogic_thermal.o
diff --git a/drivers/thermal/amlogic_thermal.c b/drivers/thermal/amlogic_thermal.c
new file mode 100644
index 000000000000..6b6d62326725
--- /dev/null
+++ b/drivers/thermal/amlogic_thermal.c
@@ -0,0 +1,335 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Amlogic Meson Thermal Sensor Driver
+ *
+ * Copyright (C) 2017 Huan Biao <huan.biao@amlogic.com>
+ * Copyright (C) 2019 Guillaume La Roque <glaroque@baylibre.com>
+ *
+ * Register value to celsius temperature formulas:
+ * Read_Val m * U
+ * U = ---------, Uptat = ---------
+ * 2^16 1 + n * U
+ *
+ * Temperature = A * ( Uptat + u_efuse / 2^16 )- B
+ *
+ * A B m n : calibration parameters
+ * u_efuse : fused calibration value, it's a signed 16 bits value
+ */
+
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/thermal.h>
+
+#include "thermal_core.h"
+
+#define TSENSOR_CFG_REG1 0x4
+ #define TSENSOR_CFG_REG1_RSET_VBG BIT(12)
+ #define TSENSOR_CFG_REG1_RSET_ADC BIT(11)
+ #define TSENSOR_CFG_REG1_VCM_EN BIT(10)
+ #define TSENSOR_CFG_REG1_VBG_EN BIT(9)
+ #define TSENSOR_CFG_REG1_OUT_CTL BIT(6)
+ #define TSENSOR_CFG_REG1_FILTER_EN BIT(5)
+ #define TSENSOR_CFG_REG1_DEM_EN BIT(3)
+ #define TSENSOR_CFG_REG1_CH_SEL GENMASK(1, 0)
+ #define TSENSOR_CFG_REG1_ENABLE \
+ (TSENSOR_CFG_REG1_FILTER_EN | \
+ TSENSOR_CFG_REG1_VCM_EN | \
+ TSENSOR_CFG_REG1_VBG_EN | \
+ TSENSOR_CFG_REG1_DEM_EN | \
+ TSENSOR_CFG_REG1_CH_SEL)
+
+#define TSENSOR_STAT0 0x40
+
+#define TSENSOR_STAT9 0x64
+
+#define TSENSOR_READ_TEMP_MASK GENMASK(15, 0)
+#define TSENSOR_TEMP_MASK GENMASK(11, 0)
+
+#define TSENSOR_TRIM_SIGN_MASK BIT(15)
+#define TSENSOR_TRIM_TEMP_MASK GENMASK(14, 0)
+#define TSENSOR_TRIM_VERSION_MASK GENMASK(31, 24)
+
+#define TSENSOR_TRIM_VERSION(_version) \
+ FIELD_GET(TSENSOR_TRIM_VERSION_MASK, _version)
+
+#define TSENSOR_TRIM_CALIB_VALID_MASK (GENMASK(3, 2) | BIT(7))
+
+#define TSENSOR_CALIB_OFFSET 1
+#define TSENSOR_CALIB_SHIFT 4
+
+/**
+ * struct amlogic_thermal_soc_data
+ * @A, B, m, n: calibration parameters
+ * This structure is required for configuration of amlogic thermal driver.
+ */
+struct amlogic_thermal_soc_data {
+ int A;
+ int B;
+ int m;
+ int n;
+};
+
+/**
+ * struct amlogic_thermal_data
+ * @u_efuse_off: register offset to read fused calibration value
+ * @soc: calibration parameters structure pointer
+ * @regmap_config: regmap config for the device
+ * This structure is required for configuration of amlogic thermal driver.
+ */
+struct amlogic_thermal_data {
+ int id;
+ int u_efuse_off;
+ const struct amlogic_thermal_soc_data *soc;
+ const struct regmap_config *regmap_config;
+};
+
+struct amlogic_thermal {
+ struct platform_device *pdev;
+ const struct amlogic_thermal_data *data;
+ struct regmap *regmap;
+ struct regmap *sec_ao_map;
+ struct clk *clk;
+ struct thermal_zone_device *tzd;
+ u32 trim_info;
+ void __iomem *base;
+};
+
+/*
+ * Calculate a temperature value from a temperature code.
+ * The unit of the temperature is degree Celsius.
+ */
+static int code_to_temp(struct amlogic_thermal *pdata, int temp_code)
+{
+ const struct amlogic_thermal_soc_data *param = pdata->data->soc;
+ int temp;
+ s64 factor, Uptat, uefuse;
+
+ uefuse = pdata->trim_info & TSENSOR_TRIM_SIGN_MASK ?
+ ~(pdata->trim_info & TSENSOR_TRIM_TEMP_MASK) + 1 :
+ (pdata->trim_info & TSENSOR_TRIM_TEMP_MASK);
+
+ factor = param->n * temp_code;
+ factor = div_s64(factor, 100);
+
+ Uptat = temp_code * param->m;
+ Uptat = div_s64(Uptat, 100);
+ Uptat = Uptat * BIT(16);
+ Uptat = div_s64(Uptat, BIT(16) + factor);
+
+ temp = (Uptat + uefuse) * param->A;
+ temp = div_s64(temp, BIT(16));
+ temp = (temp - param->B) * 100;
+
+ return temp;
+}
+
+static int amlogic_thermal_initialize(struct amlogic_thermal *pdata)
+{
+ int ret = 0;
+ int ver;
+
+ regmap_read(pdata->sec_ao_map, pdata->data->u_efuse_off,
+ &pdata->trim_info);
+
+ ver = TSENSOR_TRIM_VERSION(pdata->trim_info);
+
+ if ((ver & TSENSOR_TRIM_CALIB_VALID_MASK) == 0) {
+ ret = -EINVAL;
+ dev_err(&pdata->pdev->dev,
+ "tsensor thermal calibration not supported: 0x%x!\n",
+ ver);
+ }
+
+ return ret;
+}
+
+static int amlogic_thermal_enable(struct amlogic_thermal *data)
+{
+ clk_prepare_enable(data->clk);
+ regmap_update_bits(data->regmap, TSENSOR_CFG_REG1,
+ TSENSOR_CFG_REG1_ENABLE, TSENSOR_CFG_REG1_ENABLE);
+
+ return 0;
+}
+
+static int amlogic_thermal_disable(struct amlogic_thermal *data)
+{
+ regmap_update_bits(data->regmap, TSENSOR_CFG_REG1,
+ TSENSOR_CFG_REG1_ENABLE, 0);
+ clk_disable(data->clk);
+
+ return 0;
+}
+
+static int amlogic_thermal_get_temp(void *data, int *temp)
+{
+ unsigned int tvalue;
+ struct amlogic_thermal *pdata = data;
+
+ if (!data)
+ return -EINVAL;
+
+ regmap_read(pdata->regmap, TSENSOR_STAT0, &tvalue);
+ *temp = code_to_temp(pdata,
+ tvalue & TSENSOR_READ_TEMP_MASK);
+
+ return 0;
+}
+
+static const struct thermal_zone_of_device_ops amlogic_thermal_ops = {
+ .get_temp = amlogic_thermal_get_temp,
+};
+
+static const struct regmap_config amlogic_thermal_regmap_config_g12 = {
+ .reg_bits = 8,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = TSENSOR_STAT9,
+};
+
+static const struct amlogic_thermal_soc_data amlogic_thermal_g12 = {
+ .A = 9411,
+ .B = 3159,
+ .m = 424,
+ .n = 324,
+};
+
+static const struct amlogic_thermal_data amlogic_thermal_g12_cpu_param = {
+ .id = 0,
+ .u_efuse_off = 0x128,
+ .soc = &amlogic_thermal_g12,
+ .regmap_config = &amlogic_thermal_regmap_config_g12,
+};
+
+static const struct amlogic_thermal_data amlogic_thermal_g12_ddr_param = {
+ .id = 1,
+ .u_efuse_off = 0xF0,
+ .soc = &amlogic_thermal_g12,
+ .regmap_config = &amlogic_thermal_regmap_config_g12,
+};
+
+static const struct of_device_id of_amlogic_thermal_match[] = {
+ {
+ .compatible = "amlogic,g12-ddr-thermal",
+ .data = &amlogic_thermal_g12_ddr_param,
+ },
+ {
+ .compatible = "amlogic,g12-cpu-thermal",
+ .data = &amlogic_thermal_g12_cpu_param,
+ },
+ { /* end */ }
+};
+MODULE_DEVICE_TABLE(of, of_amlogic_thermal_match);
+
+static int amlogic_thermal_probe(struct platform_device *pdev)
+{
+ struct amlogic_thermal *pdata;
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ int ret;
+
+ pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+
+ pdata->data = of_device_get_match_data(dev);
+ pdata->pdev = pdev;
+ platform_set_drvdata(pdev, pdata);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ pdata->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(pdata->base)) {
+ dev_err(dev, "failed to get io address\n");
+ return PTR_ERR(pdata->base);
+ }
+
+ pdata->regmap = devm_regmap_init_mmio(dev, pdata->base,
+ pdata->data->regmap_config);
+ if (IS_ERR(pdata->regmap))
+ return PTR_ERR(pdata->regmap);
+
+ pdata->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(pdata->clk)) {
+ if (PTR_ERR(pdata->clk) != -EPROBE_DEFER)
+ dev_err(dev, "failed to get clock\n");
+ return PTR_ERR(pdata->clk);
+ }
+
+ pdata->sec_ao_map = syscon_regmap_lookup_by_phandle
+ (pdev->dev.of_node, "amlogic,ao-secure");
+ if (IS_ERR(pdata->sec_ao_map)) {
+ dev_err(dev, "syscon regmap lookup failed.\n");
+ return PTR_ERR(pdata->sec_ao_map);
+ }
+
+ pdata->tzd = devm_thermal_zone_of_sensor_register
+ (&pdev->dev,
+ pdata->data->id,
+ pdata,
+ &amlogic_thermal_ops);
+ if (IS_ERR(pdata->tzd)) {
+ ret = PTR_ERR(pdata->tzd);
+ dev_err(dev, "Failed to register tsensor: %d\n", ret);
+ return PTR_ERR(pdata->tzd);
+ }
+
+ ret = amlogic_thermal_initialize(pdata);
+ if (ret)
+ return ret;
+
+ ret = amlogic_thermal_enable(pdata);
+ if (ret)
+ clk_unprepare(pdata->clk);
+
+ return ret;
+}
+
+static int amlogic_thermal_remove(struct platform_device *pdev)
+{
+ struct amlogic_thermal *data = platform_get_drvdata(pdev);
+
+ return amlogic_thermal_disable(data);
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int amlogic_thermal_suspend(struct device *dev)
+{
+ struct amlogic_thermal *data = dev_get_drvdata(dev);
+
+ return amlogic_thermal_disable(data);
+}
+
+static int amlogic_thermal_resume(struct device *dev)
+{
+ struct amlogic_thermal *data = dev_get_drvdata(dev);
+
+ return amlogic_thermal_enable(data);
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(amlogic_thermal_pm_ops,
+ amlogic_thermal_suspend, amlogic_thermal_resume);
+
+static struct platform_driver amlogic_thermal_driver = {
+ .driver = {
+ .name = "amlogic_thermal",
+ .pm = &amlogic_thermal_pm_ops,
+ .of_match_table = of_amlogic_thermal_match,
+ },
+ .probe = amlogic_thermal_probe,
+ .remove = amlogic_thermal_remove,
+};
+
+module_platform_driver(amlogic_thermal_driver);
+
+MODULE_AUTHOR("Guillaume La Roque <glaroque@baylibre.com>");
+MODULE_DESCRIPTION("Amlogic thermal driver");
+MODULE_LICENSE("GPL v2");
--
2.17.1
^ permalink raw reply related
* [PATCH 1/6] dt-bindings: thermal: Add DT bindings documentation for Amlogic Thermal
From: Guillaume La Roque @ 2019-07-31 12:14 UTC (permalink / raw)
To: daniel.lezcano, khilman
Cc: linux-pm, devicetree, linux-amlogic, linux-kernel,
linux-arm-kernel
In-Reply-To: <20190731121409.17285-1-glaroque@baylibre.com>
Adding the devicetree binding documentation for the Amlogic temperature
sensor found in the Amlogic Meson G12 SoCs.
the G12A and G12B SoCs are supported.
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
---
.../bindings/thermal/amlogic,thermal.yaml | 58 +++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml
diff --git a/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml b/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml
new file mode 100644
index 000000000000..1e2fe84da13d
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/amlogic,thermal.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic Thermal Driver
+
+maintainers:
+ - Guillaume La Roque <glaroque@baylibre.com>
+
+description: Amlogic Thermal driver
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - amlogic,g12-cpu-thermal
+ - amlogic,g12-ddr-thermal
+ - enum:
+ - amlogic,g12-thermal
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ amlogic,ao-secure:
+ description: phandle to the ao-secure syscon
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - amlogic,ao-secure
+
+examples:
+ - |
+ cpu_temp: temperature-sensor@ff634800 {
+ compatible = "amlogic,g12-cpu-thermal",
+ "amlogic,g12-thermal";
+ reg = <0x0 0xff634800 0x0 0x50>;
+ interrupts = <0x0 0x24 0x0>;
+ clocks = <&clk 164>;
+ status = "okay";
+ #thermal-sensor-cells = <1>;
+ amlogic,ao-secure = <&sec_AO>;
+ };
+...
\ No newline at end of file
--
2.17.1
^ permalink raw reply related
* [PATCH 0/6] Add support of New Amlogic temperature sensor for G12 SoCs
From: Guillaume La Roque @ 2019-07-31 12:14 UTC (permalink / raw)
To: daniel.lezcano, khilman
Cc: linux-pm, devicetree, linux-amlogic, linux-kernel,
linux-arm-kernel
This patchs series add support of New Amlogic temperature sensor and minimal
thermal zone for SEI510 and ODROID-N2 boards.
First implementation was doing on IIO[1] but after comments i move on thermal framework.
Formulas and calibration values come from amlogic.
Dependencies :
- patch 3: depends on Neil's patchs :
- missing dwc2 phy-names[1]
- rework on G12 DT[2]
[1] https://lore.kernel.org/linux-amlogic/20190604144714.2009-1-glaroque@baylibre.com/
[2] https://lore.kernel.org/linux-amlogic/20190625123647.26117-1-narmstrong@baylibre.com/
[3] https://lore.kernel.org/linux-amlogic/20190729132622.7566-2-narmstrong@baylibre.com/
Guillaume La Roque (6):
dt-bindings: thermal: Add DT bindings documentation for Amlogic
Thermal
thermal: amlogic: Add thermal driver to support G12 SoCs
arm64: dts: amlogic: g12: add temperature sensor
arm64: dts: meson: sei510: Add minimal thermal zone
arm64: dts: amlogic: odroid-n2: add minimal thermal zone
MAINTAINERS: add entry for Amlogic Thermal driver
.../bindings/thermal/amlogic,thermal.yaml | 58 +++
MAINTAINERS | 9 +
.../boot/dts/amlogic/meson-g12-common.dtsi | 22 ++
.../boot/dts/amlogic/meson-g12a-sei510.dts | 13 +
.../boot/dts/amlogic/meson-g12b-odroid-n2.dts | 13 +
drivers/thermal/Kconfig | 12 +-
drivers/thermal/Makefile | 1 +
drivers/thermal/amlogic_thermal.c | 335 ++++++++++++++++++
8 files changed, 462 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml
create mode 100644 drivers/thermal/amlogic_thermal.c
--
2.17.1
^ permalink raw reply
* [PATCH v2] arm64: dts: qcom: qcs404: Add wifi rails in QCS404 dt node for proxy votes
From: Govind Singh @ 2019-07-31 12:07 UTC (permalink / raw)
To: bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
ath10k-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: linux-wireless-u79uwXL29TY76Z2rM5mHXA, Govind Singh
Add wifi regulators in qcs404 dt node for proxy vote. Proxy votes are
required for handling driver recovery scenarios to prevent
un-clocked register access during driver recovery.
Signed-off-by: Govind Singh <govinds-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
index 11c0a7137823..2289b01ee9f0 100644
--- a/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
@@ -270,6 +270,9 @@
&wifi {
status = "okay";
+ vdd-0.8-cx-mx-supply = <&vreg_l2_1p275>;
+ vdd-1.8-xo-supply = <&vreg_l5_1p8>;
+ vdd-1.3-rfa-supply = <&vreg_l1_1p3>;
};
/* PINCTRL - additions to nodes defined in qcs404.dtsi */
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* Re: [patch v4 1/5] AST2500 DMA UART driver
From: Greg KH @ 2019-07-31 11:42 UTC (permalink / raw)
To: sudheer v
Cc: Jiri Slaby, Joel Stanley, Andrew Jeffery, Benjamin Herrenschmidt,
Rob Herring, Mark Rutland, ShivahShankar Shakarnarayan rao,
Sudheer V, sudheer veliseti, linux-kernel, linux-serial,
devicetree, linux-aspeed
In-Reply-To: <CAE-5=DQ8p9WAhjrmZ8ye8GjoHrcxkHkjJPRNRFtvgeF5SdqwVQ@mail.gmail.com>
On Wed, Jul 31, 2019 at 05:06:08PM +0530, sudheer v wrote:
> Hi Greg,
> After modifying [ patch v4 1/5 ] , should i submit whole patchset as v5 ?
Yes please.
thanks,
greg k-h
^ permalink raw reply
* [PATCH v2] dt-bindings: arm-boards: Update pointer to ARM CPU bindings
From: Geert Uytterhoeven @ 2019-07-31 11:42 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: Linus Walleij, linux-arm-kernel, devicetree, linux-kernel,
Geert Uytterhoeven
The ARM CPU DT bindings were converted from plain text to YAML, but not
all referrers were updated.
Fixes: 672951cbd1b70a9e ("dt-bindings: arm: Convert cpu binding to json-schema")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
v2:
- Add Acked-by.
---
Documentation/devicetree/bindings/arm/arm-boards | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/arm-boards b/Documentation/devicetree/bindings/arm/arm-boards
index 6758ece324b1c259..b2a9f9f8430bacf4 100644
--- a/Documentation/devicetree/bindings/arm/arm-boards
+++ b/Documentation/devicetree/bindings/arm/arm-boards
@@ -199,7 +199,7 @@ The description for the board must include:
A detailed description of the bindings used for "psci" nodes is present
in the psci.yaml file.
- a "cpus" node describing the available cores and their associated
- "enable-method"s. For more details see cpus.txt file.
+ "enable-method"s. For more details see cpus.yaml file.
Example:
--
2.17.1
^ permalink raw reply related
* Re: [PATCH 15/22] ARM: dts: apalis-imx6: Add some optional I2C devices
From: Philippe Schenker @ 2019-07-31 11:37 UTC (permalink / raw)
To: festevam@gmail.com
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
kernel@pengutronix.de, Marcel Ziswiler, s.hauer@pengutronix.de,
linux-kernel@vger.kernel.org, stefan@agner.ch, robh+dt@kernel.org,
linux-imx@nxp.com, Max Krummenacher, shawnguo@kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <CAOMZO5BqbUzBi5nR33TOpgnR4CFAwxF34m+oKtRZ6rtMaMVu9g@mail.gmail.com>
On Tue, 2019-07-30 at 17:43 -0300, Fabio Estevam wrote:
> Hi Philippe,
>
> On Tue, Jul 30, 2019 at 11:57 AM Philippe Schenker <dev@pschenker.ch> wrote:
>
> > +&mipi_csi {
> > + ipu_id = <0>;
> > + csi_id = <1>;
> > + v_channel = <0>;
> > + lanes = <2>;
>
> None of these properties are valid upstream.
Will drop that one too.
^ permalink raw reply
* Re: [PATCH 14/22] ARM: dts: apalis-imx6: Add some example I2C devices
From: Philippe Schenker @ 2019-07-31 11:36 UTC (permalink / raw)
To: festevam@gmail.com
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
kernel@pengutronix.de, Marcel Ziswiler, s.hauer@pengutronix.de,
linux-kernel@vger.kernel.org, stefan@agner.ch, robh+dt@kernel.org,
linux-imx@nxp.com, Max Krummenacher, shawnguo@kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <CAOMZO5BtXFR7kDuiHedsDA0AaNZqsO_L2x9d3u9ZuULkovChoQ@mail.gmail.com>
On Tue, 2019-07-30 at 17:53 -0300, Fabio Estevam wrote:
> On Tue, Jul 30, 2019 at 11:57 AM Philippe Schenker <dev@pschenker.ch> wrote:
>
> > &backlight {
> > @@ -204,6 +228,77 @@
> > */
> > &i2c3 {
> > status = "okay";
> > +
> > + adv7280: adv7280@21 {
> > + compatible = "adv7280";
> > + reg = <0x21>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>;
> > + clocks = <&clks 200>;
>
> Please replace this 200 with a proper clock label.
>
> > + clock-names = "csi_mclk";
> > + DOVDD-supply = <®_3p3v>;
> > + AVDD-supply = <®_3p3v>;
> > + DVDD-supply = <®_3p3v>;
> > + PVDD-supply = <®_3p3v>;
> > + csi_id = <0>;
>
> This is not a valid property upstream.
>
> It seems you just ported it from a downstream vendor kernel. Please
> make sure you test with the dt-bindings from mainline.
>
> > + mclk = <24000000>;
> > + mclk_source = <1>;
> > + status = "okay";
> > + };
> > +
> > + /* Video ADC on Analog Camera Module */
> > + adv7180: adv7180@21 {
> > + compatible = "adv,adv7180";
> > + reg = <0x21>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>;
> > + clocks = <&clks 200>;
>
> clock label, please.
>
> > + clock-names = "csi_mclk";
> > + DOVDD-supply = <®_3p3v>; /* 3.3v */
> > + AVDD-supply = <®_3p3v>; /* 1.8v */
> > + DVDD-supply = <®_3p3v>; /* 1.8v */
> > + PVDD-supply = <®_3p3v>; /* 1.8v */
> > + csi_id = <0>;
>
> Same here
>
> > + mclk = <24000000>;
> > + mclk_source = <1>;
> > + cvbs = <1>;
> > + status = "disabled";
> > + };
> > +
> > + max9526: max9526@20 {
> > + compatible = "maxim,max9526";
>
> This is not documented in mainline.
Yeah, too much downstream stuff in here. I will drop that patch for now...
^ permalink raw reply
* Re: [PATCH 2/2] ARM: dts: at91: add support for Arietta G25
From: Ludovic Desroches @ 2019-07-31 11:36 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Mark Rutland, devicetree, Alexandre Belloni, Rob Herring, info,
linux-arm-kernel
In-Reply-To: <20190728210403.2730-3-uwe@kleine-koenig.org>
On Sun, Jul 28, 2019 at 11:04:03PM +0200, Uwe Kleine-König wrote:
>
> The Arietta G25 is a SBC powered by a AT91SAMG25 running at 400 MHz.
> See https://www.acmesystems.it/arietta for more details.
>
> Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
> ---
> arch/arm/boot/dts/at91sam9g25-arietta.dts | 86 +++++++++++++++++++++++
> 1 file changed, 86 insertions(+)
> create mode 100644 arch/arm/boot/dts/at91sam9g25-arietta.dts
>
> diff --git a/arch/arm/boot/dts/at91sam9g25-arietta.dts b/arch/arm/boot/dts/at91sam9g25-arietta.dts
> new file mode 100644
> index 000000000000..6c20e02f0ea9
> --- /dev/null
> +++ b/arch/arm/boot/dts/at91sam9g25-arietta.dts
> @@ -0,0 +1,86 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Arietta - System On Module
> + * https://www.acmesystems.it/arietta
> + */
> +
> +/dts-v1/;
> +#include "at91sam9g25.dtsi"
> +
> +/ {
> + model = "Acme Systems Arietta G25";
> + compatible = "acme,ariettag25", "atmel,at91sam9x5", "atmel,at91sam9";
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory {
> + reg = <0x20000000 0x8000000>;
> + };
> +
> + clocks {
> + slow_xtal {
> + clock-frequency = <32768>;
> + };
> +
> + main_xtal {
> + clock-frequency = <12000000>;
> + };
> + };
> +
> + ahb {
> + apb {
> + rtc@fffffeb0 {
> + status = "okay";
> + };
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + arietta_led {
> + label = "arietta_led";
> + gpios = <&pioB 8 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "heartbeat";
> + };
> + };
> +};
> +
> +&dbgu {
> + status = "okay";
> +};
> +
> +&mmc0 {
> + pinctrl-0 = <
> + &pinctrl_mmc0_slot0_clk_cmd_dat0
> + &pinctrl_mmc0_slot0_dat1_3>;
> + status = "okay";
> +
> + slot@0 {
> + reg = <0>;
> + bus-width = <4>;
> + };
> +};
> +
> +&usart0 {
> + status ="okay";
> +};
> +
> +&usart1 {
> + status ="okay";
> +};
> +
> +&usb0 {
> + status = "okay";
> + num-ports = <3>;
> +};
> +
> +&usb1 {
> + status = "okay";
> +};
> +
> +&usb2 {
> + status = "okay";
> +};
> --
> 2.20.1
>
^ permalink raw reply
* Re: [patch v4 1/5] AST2500 DMA UART driver
From: sudheer v @ 2019-07-31 11:36 UTC (permalink / raw)
To: Greg KH
Cc: Jiri Slaby, Joel Stanley, Andrew Jeffery, Benjamin Herrenschmidt,
Rob Herring, Mark Rutland, ShivahShankar Shakarnarayan rao,
Sudheer V, sudheer veliseti, linux-kernel, linux-serial,
devicetree, linux-aspeed
In-Reply-To: <20190730154759.GA26425@kroah.com>
[-- Attachment #1: Type: text/plain, Size: 10668 bytes --]
Hi Greg,
After modifying [ patch v4 1/5 ] , should i submit whole patchset as v5 ?
or replying with this single patch modified will be enough?
how is this done in linux community ?.
Regards
Sudheer
On Tue, Jul 30, 2019 at 9:18 PM Greg KH <gregkh@linuxfoundation.org> wrote:
> On Fri, Jul 26, 2019 at 06:57:16PM +0530, sudheer.v wrote:
> > From: sudheer veliseti <sudheer.open@gmail.com>
> >
> > UART driver for Aspeed's bmc chip AST2500
> >
> > Design approch:
> > AST2500 has dedicated Uart DMA controller which has 12 sets of Tx and RX
> channels
> > connected to UART controller directly.
> > Since the DMA controller have dedicated buffers and registers,
> > there would be little benifit in adding DMA framework overhead.
> > So the software for DMA controller is included within the UART driver
> itself.
> >
> > implementation details:
> > 'struct ast_uart_port' is populated and registered with uart_core.
> > code is organised into two layers UART-layer and DMA-Layer,both of them
> are
> > in the same file.UART-layer requests Rx and Tx dma channels
> > and registers callbacks with DMA controller software Layer
> > Interrupt service routine for DMA controller is the crucial one for
> Handling all
> > the tx and rx data. ISRs installed for individual uarts are just
> dummy,and are helpful
> > only to report any spurious interrupts in hardware.
> >
> >
> > Signed-off-by: sudheer veliseti <sudheer.open@gmail.com>
> > ---
> >
> > Changes from v3->v4:
> > - per port uart structures are registerd directly with uart core
> > Instead of registering through 8250 Frame work,
> > ast_uart_port is registered using uart_add_one_port
> > -SDMA_RX_FIX macro replaced with CONFIG_AST_UART_DMA_RX_INTERRUPT
> > -ast_uart_sdma_isr : DMA interrupt handler code is improvised
> > -replaced pr_debug with ftrace wherever appropriate
> > -dev_err is used in all error return cases
> > -uart driver structure ast25xx_uart_reg is modified
> > -driver name changed to ast2500-uart-dma-drv
> > -rx_timer initialisation and callback fn modified
> >
> > Changes from v2->v3:
> > -custom debug replaced by in kerenl dynamic debug: pr_debug
> > -change-logs added
> >
> >
> > .../tty/serial/8250/8250_ast2500_uart_dma.c | 1901 +++++++++++++++++
> > 1 file changed, 1901 insertions(+)
> > create mode 100644 drivers/tty/serial/8250/8250_ast2500_uart_dma.c
> >
> > diff --git a/drivers/tty/serial/8250/8250_ast2500_uart_dma.c
> b/drivers/tty/serial/8250/8250_ast2500_uart_dma.c
> > new file mode 100644
> > index 000000000000..bc830d605372
> > --- /dev/null
> > +++ b/drivers/tty/serial/8250/8250_ast2500_uart_dma.c
> > @@ -0,0 +1,1901 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * DMA UART Driver for ASPEED BMC chip: AST2500
> > + *
> > + * Copyright (C) 2019 sudheer Kumar veliseti, Aspeed technology Inc.
> > + * <open.sudheer@gmail.com>
>
> What was the copyright on the file you copied? Please properly
> attribute that here.
>
>
> > + *
> > + */
> > +#include <linux/clk.h>
> > +#include <linux/dma-mapping.h>
> > +#include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/tty.h>
> > +#include <linux/tty_flip.h>
> > +#include "8250.h"
> > +
> > +#define SERIAL8250_CONSOLE NULL
> > +#define TTY_AST_MAJOR 204
> > +#define TTY_AST_MINOR 68
>
> Where did you get this minor number from?
>
> > +
> > +#define DMA_BUFF_SIZE 0x1000
> > +#define SDMA_RX_BUFF_SIZE 0x10000
> > +#define PASS_LIMIT 256
> > +#define UART_DMA_NR CONFIG_AST_NR_DMA_UARTS
> > +#define AST_UART_SDMA_CH 12
> > +
> > +/* enum ast_uart_chan_op
> > + * operation codes passed to the DMA code by the user, and also used
> > + * to inform the current channel owner of any changes to the system
> state
> > + */
> > +enum ast_uart_chan_op {
> > + AST_UART_DMAOP_TRIGGER,
> > + AST_UART_DMAOP_STOP,
> > + AST_UART_DMAOP_PAUSE,
> > +};
> > +
> > +/* ast_uart_dma_cbfn: buffer callback routinei type */
> > +typedef void (*ast_uart_dma_cbfn)(void *dev_id, u16 len);
> > +
> > +struct ast_sdma_info {
> > + u8 ch_no;
> > + u8 direction;
> > + u8 enable;
> > + void *priv;
> > + char *sdma_virt_addr;
> > + dma_addr_t dma_phy_addr;
> > + /* cdriver callbacks */
> > + ast_uart_dma_cbfn callback_fn; /* buffer done callback */
> > +};
> > +
> > +struct ast_sdma_ch {
> > + struct ast_sdma_info tx_dma_info[AST_UART_SDMA_CH];
> > + struct ast_sdma_info rx_dma_info[AST_UART_SDMA_CH];
> > +};
> > +
> > +struct ast_sdma {
> > + void __iomem *reg_base;
> > + int dma_irq;
> > + struct ast_sdma_ch *dma_ch;
> > + struct regmap *map;
> > +};
> > +
> > +#define UART_TX_SDMA_EN 0x00
> > +#define UART_RX_SDMA_EN 0x04
> > +#define UART_SDMA_CONF 0x08 /* Misc, Buffer size */
> > +#define UART_SDMA_TIMER 0x0C
> > +#define UART_TX_SDMA_REST 0x20
> > +#define UART_RX_SDMA_REST 0x24
> > +#define UART_TX_SDMA_IER 0x30
> > +#define UART_TX_SDMA_ISR 0x34
> > +#define UART_RX_SDMA_IER 0x38
> > +#define UART_RX_SDMA_ISR 0x3C
> > +#define UART_TX_R_POINT(x) (0x40 + ((x) * 0x20))
> > +#define UART_TX_W_POINT(x) (0x44 + ((x) * 0x20))
> > +#define UART_TX_SDMA_ADDR(x) (0x48 + ((x) * 0x20))
> > +#define UART_RX_R_POINT(x) (0x50 + ((x) * 0x20))
> > +#define UART_RX_W_POINT(x) (0x54 + ((x) * 0x20))
> > +#define UART_RX_SDMA_ADDR(x) (0x58 + ((x) * 0x20))
> > +#define SDMA_CH_EN(x) BIT(x)
> > +
> > +#define SDMA_TX_BUFF_SIZE_MASK (0x3)
> > +#define SDMA_SET_TX_BUFF_SIZE(x)(x)
> > +#define SDMA_BUFF_SIZE_1KB (0x0)
> > +#define SDMA_BUFF_SIZE_4KB (0x1)
> > +#define SDMA_BUFF_SIZE_16KB (0x2)
> > +#define SDMA_BUFF_SIZE_64KB (0x3)
> > +#define SDMA_RX_BUFF_SIZE_MASK (0x3 << 2)
> > +#define SDMA_SET_RX_BUFF_SIZE(x)((x) << 2)
> > +#define SDMA_TIMEOUT_DIS BIT(4)
> > +
> > +#define UART_SDMA11_INT BIT(11)
> > +#define UART_SDMA10_INT BIT(10)
> > +#define UART_SDMA9_INT BIT(9)
> > +#define UART_SDMA8_INT BIT(8)
> > +#define UART_SDMA7_INT BIT(7)
> > +#define UART_SDMA6_INT BIT(6)
> > +#define UART_SDMA5_INT BIT(5)
> > +#define UART_SDMA4_INT BIT(4)
> > +#define UART_SDMA3_INT BIT(3)
> > +#define UART_SDMA2_INT BIT(2)
> > +#define UART_SDMA1_INT BIT(1)
> > +#define UART_SDMA0_INT BIT(0)
> > +
> > +/*
> > + * Configuration:
> > + * share_irqs - whether we pass IRQF_SHARED to request_irq().
> > + * This option is unsafe when used on edge-triggered interrupts.
> > + */
> > +static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
> > +
> > +static unsigned int nr_uarts = CONFIG_AST_RUNTIME_DMA_UARTS;
> > +
> > +struct ast_uart_port {
> > + struct uart_port port;
> > + unsigned short capabilities; /* port capabilities */
> > + unsigned short bugs; /* port bugs */
> > + unsigned int tx_loadsz; /* transmit fifo load size */
> > + unsigned char acr;
> > + unsigned char ier;
> > + unsigned char lcr;
> > + unsigned char mcr;
> > + unsigned char mcr_mask; /* mask of user bits */
> > + unsigned char mcr_force; /* mask of forced bits */
> > + struct circ_buf rx_dma_buf;
> > + struct circ_buf tx_dma_buf;
> > + unsigned char dma_channel;
> > + dma_addr_t dma_rx_addr; /* Mapped ADMA descr. table */
> > + dma_addr_t dma_tx_addr; /* Mapped ADMA descr. table */
> > +#ifdef CONFIG_AST_UART_DMA_RX_INTERRUPT
> > + struct tasklet_struct rx_tasklet;
> > +#else
> > + struct timer_list rx_timer;
> > + unsigned int workaround;
> > +#endif
> > + struct tasklet_struct tx_tasklet;
> > + spinlock_t lock;
> > + int tx_done;
> > + int tx_count;
> > + struct platform_device *ast_uart_pdev;
> > +/*
> > + * Some bits in registers are cleared on a read, so they must
> > + * be saved whenever the register is read but the bits will not
> > + * be immediately processed.
> > + */
> > +#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
> > + unsigned char lsr_saved_flags;
> > +#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
> > + unsigned char msr_saved_flags;
> > +
> > + /*
> > + * We provide a per-port pm hook.
> > + */
> > + void (*pm)(struct uart_port *port, unsigned int state,
> > + unsigned int old);
> > +};
> > +
> > +static struct ast_uart_port ast_uart_ports[UART_DMA_NR];
> > +
> > +#define GET_DEV(ast_uart_port_priv_ptr)\
> > + (ast_uart_port_priv_ptr->ast_uart_pdev->dev)
> > +
> > +static inline struct ast_uart_port *
> > +to_ast_dma_uart_port(struct uart_port *uart) {
> > + return container_of(uart, struct ast_uart_port, port);
> > +}
> > +
> > +struct irq_info {
> > + spinlock_t lock;
> > + struct ast_uart_port *up;
> > +};
> > +
> > +static struct irq_info ast_uart_irq[1];
> > +static DEFINE_MUTEX(ast_uart_mutex);
> > +
> > +/*
> > + * Here we define the default xmit fifo size used for each type of UART.
> > + */
> > +static const struct serial8250_config uart_config[] = {
> > + [PORT_UNKNOWN] = {
> > + .name = "unknown",
> > + .fifo_size = 1,
> > + .tx_loadsz = 1,
> > + },
> > + [PORT_8250] = {
> > + .name = "8250",
> > + .fifo_size = 1,
> > + .tx_loadsz = 1,
> > + },
> > + [PORT_16450] = {
> > + .name = "16450",
> > + .fifo_size = 1,
> > + .tx_loadsz = 1,
> > + },
> > + [PORT_16550] = {
> > + .name = "16550",
> > + .fifo_size = 1,
> > + .tx_loadsz = 1,
> > + },
> > + [PORT_16550A] = {
> > + .name = "16550A",
> > + .fifo_size = 16,
> > + .tx_loadsz = 16,
> > + .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10
> > + |
> UART_FCR_DMA_SELECT,
> > + .flags = UART_CAP_FIFO,
> > + },
> > +};
>
> I doubt you need all of these port types, right? You only have one type
> of device, please strip out _ALL_ of the unneeded code in here. You did
> a wholesale copy of the old driver, to get away with that you then need
> to customize it to work properly with your hardware _AND_ take away all
> code that is not needed for your hardware.
>
> Lots of this file can be removed, please do so.
>
> thanks,
>
> greg k-h
>
[-- Attachment #2: Type: text/html, Size: 13599 bytes --]
^ permalink raw reply
* Re: [PATCH 1/2] dts: add vendor prefix "acme" for "Acme Systems srl"
From: Ludovic Desroches @ 2019-07-31 11:34 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Mark Rutland, devicetree, Alexandre Belloni, Rob Herring, info,
linux-arm-kernel
In-Reply-To: <20190728210403.2730-2-uwe@kleine-koenig.org>
On Sun, Jul 28, 2019 at 11:04:02PM +0200, Uwe Kleine-König wrote:
>
> Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
As I can confirm it's not an April fool!
Reviwed-by: Ludovic Desroches <ludovic.desroches@microchip.com>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index 6992bbbbffab..85965e3446bf 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -27,6 +27,8 @@ patternProperties:
> description: Abilis Systems
> "^abracon,.*":
> description: Abracon Corporation
> + "^acme,.*":
> + description: Acme Systems srl
> "^actions,.*":
> description: Actions Semiconductor Co., Ltd.
> "^active-semi,.*":
> --
> 2.20.1
>
^ permalink raw reply
* Applied "ASoC: meson: g12a-tohdmitx: override codec2codec params" to the asoc tree
From: Mark Brown @ 2019-07-31 11:29 UTC (permalink / raw)
To: Jerome Brunet
Cc: alsa-devel, devicetree, Kevin Hilman, Liam Girdwood,
linux-amlogic, linux-kernel, Mark Brown
In-Reply-To: <20190729080139.32068-1-jbrunet@baylibre.com>
The patch
ASoC: meson: g12a-tohdmitx: override codec2codec params
has been applied to the asoc tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-5.4
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
>From 2c4956bc1e9062e5e3c5ea7612294f24e6d4fbdd Mon Sep 17 00:00:00 2001
From: Jerome Brunet <jbrunet@baylibre.com>
Date: Mon, 29 Jul 2019 10:01:39 +0200
Subject: [PATCH] ASoC: meson: g12a-tohdmitx: override codec2codec params
So far, forwarding the hw_params of the input to output relied on the
.hw_params() callback of the cpu side of the codec2codec link to be called
first. This is a bit weak.
Instead, override the stream params of the codec2codec to link to set it up
correctly.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20190729080139.32068-1-jbrunet@baylibre.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
sound/soc/meson/g12a-tohdmitx.c | 34 ++++++++++++++++-----------------
1 file changed, 16 insertions(+), 18 deletions(-)
diff --git a/sound/soc/meson/g12a-tohdmitx.c b/sound/soc/meson/g12a-tohdmitx.c
index 707ccb192e4c..9943c807ec5d 100644
--- a/sound/soc/meson/g12a-tohdmitx.c
+++ b/sound/soc/meson/g12a-tohdmitx.c
@@ -28,7 +28,7 @@
#define CTRL0_SPDIF_CLK_SEL BIT(0)
struct g12a_tohdmitx_input {
- struct snd_pcm_hw_params params;
+ struct snd_soc_pcm_stream params;
unsigned int fmt;
};
@@ -225,26 +225,17 @@ static int g12a_tohdmitx_input_hw_params(struct snd_pcm_substream *substream,
{
struct g12a_tohdmitx_input *data = dai->playback_dma_data;
- /* Save the stream params for the downstream link */
- memcpy(&data->params, params, sizeof(*params));
+ data->params.rates = snd_pcm_rate_to_rate_bit(params_rate(params));
+ data->params.rate_min = params_rate(params);
+ data->params.rate_max = params_rate(params);
+ data->params.formats = 1 << params_format(params);
+ data->params.channels_min = params_channels(params);
+ data->params.channels_max = params_channels(params);
+ data->params.sig_bits = dai->driver->playback.sig_bits;
return 0;
}
-static int g12a_tohdmitx_output_hw_params(struct snd_pcm_substream *substream,
- struct snd_pcm_hw_params *params,
- struct snd_soc_dai *dai)
-{
- struct g12a_tohdmitx_input *in_data =
- g12a_tohdmitx_get_input_data(dai->capture_widget);
-
- if (!in_data)
- return -ENODEV;
-
- memcpy(params, &in_data->params, sizeof(*params));
-
- return 0;
-}
static int g12a_tohdmitx_input_set_fmt(struct snd_soc_dai *dai,
unsigned int fmt)
@@ -266,6 +257,14 @@ static int g12a_tohdmitx_output_startup(struct snd_pcm_substream *substream,
if (!in_data)
return -ENODEV;
+ if (WARN_ON(!rtd->dai_link->params)) {
+ dev_warn(dai->dev, "codec2codec link expected\n");
+ return -EINVAL;
+ }
+
+ /* Replace link params with the input params */
+ rtd->dai_link->params = &in_data->params;
+
if (!in_data->fmt)
return 0;
@@ -278,7 +277,6 @@ static const struct snd_soc_dai_ops g12a_tohdmitx_input_ops = {
};
static const struct snd_soc_dai_ops g12a_tohdmitx_output_ops = {
- .hw_params = g12a_tohdmitx_output_hw_params,
.startup = g12a_tohdmitx_output_startup,
};
--
2.20.1
^ permalink raw reply related
* Applied "dt-bindings: sound: Add bindings for UDA1334 codec" to the asoc tree
From: Mark Brown @ 2019-07-31 11:29 UTC (permalink / raw)
To: Andra Danciu; +Cc: alsa-devel, anders.roxell, broonie, ckeepax, Daniel Baluta
In-Reply-To: <20190731111930.20230-2-andradanciu1997@gmail.com>
The patch
dt-bindings: sound: Add bindings for UDA1334 codec
has been applied to the asoc tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-5.4
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
>From d6de65fde51644f6ed6b1c0c05fef6a2da5ff768 Mon Sep 17 00:00:00 2001
From: Andra Danciu <andradanciu1997@gmail.com>
Date: Wed, 31 Jul 2019 14:19:29 +0300
Subject: [PATCH] dt-bindings: sound: Add bindings for UDA1334 codec
The UDA1334 is an NXP audio codec, supports the I2S-bus data format
and has basic features such as de-emphasis (at 44.1 kHz sampling
rate) and mute. Product information can be found at:
https://www.nxp.com/pages/low-power-audio-dac-with-pll:UDA1334
Cc: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Andra Danciu <andradanciu1997@gmail.com>
Link: https://lore.kernel.org/r/20190731111930.20230-2-andradanciu1997@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
.../devicetree/bindings/sound/uda1334.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/uda1334.txt
diff --git a/Documentation/devicetree/bindings/sound/uda1334.txt b/Documentation/devicetree/bindings/sound/uda1334.txt
new file mode 100644
index 000000000000..f64071b25e8d
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/uda1334.txt
@@ -0,0 +1,17 @@
+UDA1334 audio CODEC
+
+This device uses simple GPIO pins for controlling codec settings.
+
+Required properties:
+
+ - compatible : "nxp,uda1334"
+ - nxp,mute-gpios: a GPIO spec for the MUTE pin.
+ - nxp,deemph-gpios: a GPIO spec for the De-emphasis pin
+
+Example:
+
+uda1334: audio-codec {
+ compatible = "nxp,uda1334";
+ nxp,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+ nxp,deemph-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
+};
--
2.20.1
^ permalink raw reply related
* Applied "ASoC: codecs: Add uda1334 codec driver" to the asoc tree
From: Mark Brown @ 2019-07-31 11:29 UTC (permalink / raw)
To: Andra Danciu; +Cc: alsa-devel, anders.roxell, broonie, ckeepax, Daniel Baluta
In-Reply-To: <20190731111930.20230-3-andradanciu1997@gmail.com>
The patch
ASoC: codecs: Add uda1334 codec driver
has been applied to the asoc tree at
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-5.4
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
>From caa918ef14065b812737f3ee4ac349dcfff196e6 Mon Sep 17 00:00:00 2001
From: Andra Danciu <andradanciu1997@gmail.com>
Date: Wed, 31 Jul 2019 14:19:30 +0300
Subject: [PATCH] ASoC: codecs: Add uda1334 codec driver
The UDA1334BTS supports the I2S-bus data format with word lengths of up
to 24 bits serial data format and has basic features such as de-emphasis
(at 44.1 kHz sampling rate) and mute.
Datasheet can be found at:
https://www.nxp.com/docs/en/data-sheet/UDA1334BTS.pdf
Cc: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Andra Danciu <andradanciu1997@gmail.com>
Link: https://lore.kernel.org/r/20190731111930.20230-3-andradanciu1997@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
---
sound/soc/codecs/Kconfig | 9 ++
sound/soc/codecs/Makefile | 2 +
sound/soc/codecs/uda1334.c | 295 +++++++++++++++++++++++++++++++++++++
3 files changed, 306 insertions(+)
create mode 100644 sound/soc/codecs/uda1334.c
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index da4c1ae89742..89238343e34d 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -199,6 +199,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_TS3A227E if I2C
select SND_SOC_TWL4030 if TWL4030_CORE
select SND_SOC_TWL6040 if TWL6040_CORE
+ select SND_SOC_UDA1334 if GPIOLIB
select SND_SOC_UDA134X
select SND_SOC_UDA1380 if I2C
select SND_SOC_WCD9335 if SLIMBUS
@@ -1207,6 +1208,14 @@ config SND_SOC_TWL4030
config SND_SOC_TWL6040
tristate
+config SND_SOC_UDA1334
+ tristate "NXP UDA1334 DAC"
+ depends on GPIOLIB
+ help
+ The UDA1334 is an NXP audio codec, supports the I2S-bus data format
+ and has basic features such as de-emphasis (at 44.1 kHz sampling
+ rate) and mute.
+
config SND_SOC_UDA134X
tristate
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 9230016b0f9f..c498373dcc5f 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -212,6 +212,7 @@ snd-soc-tscs454-objs := tscs454.o
snd-soc-ts3a227e-objs := ts3a227e.o
snd-soc-twl4030-objs := twl4030.o
snd-soc-twl6040-objs := twl6040.o
+snd-soc-uda1334-objs := uda1334.o
snd-soc-uda134x-objs := uda134x.o
snd-soc-uda1380-objs := uda1380.o
snd-soc-wcd9335-objs := wcd-clsh-v2.o wcd9335.o
@@ -494,6 +495,7 @@ obj-$(CONFIG_SND_SOC_TSCS454) += snd-soc-tscs454.o
obj-$(CONFIG_SND_SOC_TS3A227E) += snd-soc-ts3a227e.o
obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o
obj-$(CONFIG_SND_SOC_TWL6040) += snd-soc-twl6040.o
+obj-$(CONFIG_SND_SOC_UDA1334) += snd-soc-uda1334.o
obj-$(CONFIG_SND_SOC_UDA134X) += snd-soc-uda134x.o
obj-$(CONFIG_SND_SOC_UDA1380) += snd-soc-uda1380.o
obj-$(CONFIG_SND_SOC_WCD9335) += snd-soc-wcd9335.o
diff --git a/sound/soc/codecs/uda1334.c b/sound/soc/codecs/uda1334.c
new file mode 100644
index 000000000000..21ab8c5487ba
--- /dev/null
+++ b/sound/soc/codecs/uda1334.c
@@ -0,0 +1,295 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// uda1334.c -- UDA1334 ALSA SoC Audio driver
+//
+// Based on WM8523 ALSA SoC Audio driver written by Mark Brown
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/gpio/consumer.h>
+#include <linux/of_device.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/initval.h>
+
+#define UDA1334_NUM_RATES 6
+
+/* codec private data */
+struct uda1334_priv {
+ struct gpio_desc *mute;
+ struct gpio_desc *deemph;
+ unsigned int sysclk;
+ unsigned int rate_constraint_list[UDA1334_NUM_RATES];
+ struct snd_pcm_hw_constraint_list rate_constraint;
+};
+
+static const struct snd_soc_dapm_widget uda1334_dapm_widgets[] = {
+SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
+SND_SOC_DAPM_OUTPUT("LINEVOUTL"),
+SND_SOC_DAPM_OUTPUT("LINEVOUTR"),
+};
+
+static const struct snd_soc_dapm_route uda1334_dapm_routes[] = {
+ { "LINEVOUTL", NULL, "DAC" },
+ { "LINEVOUTR", NULL, "DAC" },
+};
+
+static int uda1334_put_deemph(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
+ struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
+ int deemph = ucontrol->value.integer.value[0];
+
+ if (deemph > 1)
+ return -EINVAL;
+
+ gpiod_set_value_cansleep(uda1334->deemph, deemph);
+
+ return 0;
+};
+
+static int uda1334_get_deemph(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
+ struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
+ int ret;
+
+ ret = gpiod_get_value_cansleep(uda1334->deemph);
+ if (ret < 0)
+ return -EINVAL;
+
+ ucontrol->value.integer.value[0] = ret;
+
+ return 0;
+};
+
+static const struct snd_kcontrol_new uda1334_snd_controls[] = {
+ SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
+ uda1334_get_deemph, uda1334_put_deemph),
+};
+
+static const struct {
+ int value;
+ int ratio;
+} lrclk_ratios[UDA1334_NUM_RATES] = {
+ { 1, 128 },
+ { 2, 192 },
+ { 3, 256 },
+ { 4, 384 },
+ { 5, 512 },
+ { 6, 768 },
+};
+
+static int uda1334_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_component *component = dai->component;
+ struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
+
+ /*
+ * The set of sample rates that can be supported depends on the
+ * MCLK supplied to the CODEC - enforce this.
+ */
+ if (!uda1334->sysclk) {
+ dev_err(component->dev,
+ "No MCLK configured, call set_sysclk() on init\n");
+ return -EINVAL;
+ }
+
+ snd_pcm_hw_constraint_list(substream->runtime, 0,
+ SNDRV_PCM_HW_PARAM_RATE,
+ &uda1334->rate_constraint);
+
+ gpiod_set_value_cansleep(uda1334->mute, 1);
+
+ return 0;
+}
+
+static void uda1334_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_component *component = dai->component;
+ struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
+
+ gpiod_set_value_cansleep(uda1334->mute, 0);
+}
+
+static int uda1334_set_dai_sysclk(struct snd_soc_dai *codec_dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ struct snd_soc_component *component = codec_dai->component;
+ struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
+ unsigned int val;
+ int i, j = 0;
+
+ uda1334->sysclk = freq;
+
+ uda1334->rate_constraint.count = 0;
+ for (i = 0; i < ARRAY_SIZE(lrclk_ratios); i++) {
+ val = freq / lrclk_ratios[i].ratio;
+ /*
+ * Check that it's a standard rate since core can't
+ * cope with others and having the odd rates confuses
+ * constraint matching.
+ */
+
+ switch (val) {
+ case 8000:
+ case 32000:
+ case 44100:
+ case 48000:
+ case 64000:
+ case 88200:
+ case 96000:
+ dev_dbg(component->dev, "Supported sample rate: %dHz\n",
+ val);
+ uda1334->rate_constraint_list[j++] = val;
+ uda1334->rate_constraint.count++;
+ break;
+ default:
+ dev_dbg(component->dev, "Skipping sample rate: %dHz\n",
+ val);
+ }
+ }
+
+ /* Need at least one supported rate... */
+ if (uda1334->rate_constraint.count == 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int uda1334_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
+{
+ fmt &= (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_INV_MASK |
+ SND_SOC_DAIFMT_MASTER_MASK);
+
+ if (fmt != (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+ SND_SOC_DAIFMT_CBS_CFS)) {
+ dev_err(codec_dai->dev, "Invalid DAI format\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int uda1334_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
+{
+ struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(dai->component);
+
+ if (uda1334->mute)
+ gpiod_set_value_cansleep(uda1334->mute, mute);
+
+ return 0;
+}
+
+#define UDA1334_RATES SNDRV_PCM_RATE_8000_96000
+
+#define UDA1334_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
+
+static const struct snd_soc_dai_ops uda1334_dai_ops = {
+ .startup = uda1334_startup,
+ .shutdown = uda1334_shutdown,
+ .set_sysclk = uda1334_set_dai_sysclk,
+ .set_fmt = uda1334_set_fmt,
+ .mute_stream = uda1334_mute_stream,
+};
+
+static struct snd_soc_dai_driver uda1334_dai = {
+ .name = "uda1334-hifi",
+ .playback = {
+ .stream_name = "Playback",
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = UDA1334_RATES,
+ .formats = UDA1334_FORMATS,
+ },
+ .ops = &uda1334_dai_ops,
+};
+
+static int uda1334_probe(struct snd_soc_component *component)
+{
+ struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
+
+ uda1334->rate_constraint.list = &uda1334->rate_constraint_list[0];
+ uda1334->rate_constraint.count =
+ ARRAY_SIZE(uda1334->rate_constraint_list);
+
+ return 0;
+}
+
+static const struct snd_soc_component_driver soc_component_dev_uda1334 = {
+ .probe = uda1334_probe,
+ .controls = uda1334_snd_controls,
+ .num_controls = ARRAY_SIZE(uda1334_snd_controls),
+ .dapm_widgets = uda1334_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(uda1334_dapm_widgets),
+ .dapm_routes = uda1334_dapm_routes,
+ .num_dapm_routes = ARRAY_SIZE(uda1334_dapm_routes),
+ .idle_bias_on = 1,
+ .use_pmdown_time = 1,
+ .endianness = 1,
+ .non_legacy_dai_naming = 1,
+};
+
+static const struct of_device_id uda1334_of_match[] = {
+ { .compatible = "nxp,uda1334" },
+ { /* sentinel*/ }
+};
+MODULE_DEVICE_TABLE(of, uda1334_of_match);
+
+static int uda1334_codec_probe(struct platform_device *pdev)
+{
+ struct uda1334_priv *uda1334;
+ int ret;
+
+ uda1334 = devm_kzalloc(&pdev->dev, sizeof(struct uda1334_priv),
+ GFP_KERNEL);
+ if (!uda1334)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, uda1334);
+
+ uda1334->mute = devm_gpiod_get(&pdev->dev, "nxp,mute", GPIOD_OUT_LOW);
+ if (IS_ERR(uda1334->mute)) {
+ ret = PTR_ERR(uda1334->mute);
+ dev_err(&pdev->dev, "Failed to get mute line: %d\n", ret);
+ return ret;
+ }
+
+ uda1334->deemph = devm_gpiod_get(&pdev->dev, "nxp,deemph", GPIOD_OUT_LOW);
+ if (IS_ERR(uda1334->deemph)) {
+ ret = PTR_ERR(uda1334->deemph);
+ dev_err(&pdev->dev, "Failed to get deemph line: %d\n", ret);
+ return ret;
+ }
+
+ ret = devm_snd_soc_register_component(&pdev->dev,
+ &soc_component_dev_uda1334,
+ &uda1334_dai, 1);
+ if (ret < 0)
+ dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
+
+ return ret;
+}
+
+static struct platform_driver uda1334_codec_driver = {
+ .probe = uda1334_codec_probe,
+ .driver = {
+ .name = "uda1334-codec",
+ .of_match_table = uda1334_of_match,
+ },
+};
+module_platform_driver(uda1334_codec_driver);
+
+MODULE_DESCRIPTION("ASoC UDA1334 driver");
+MODULE_AUTHOR("Andra Danciu <andradanciu1997@gmail.com>");
+MODULE_ALIAS("platform:uda1334-codec");
+MODULE_LICENSE("GPL v2");
--
2.20.1
^ permalink raw reply related
* [PATCH 2/2] ASoC: codecs: Add uda1334 codec driver
From: Andra Danciu @ 2019-07-31 11:19 UTC (permalink / raw)
To: broonie
Cc: lgirdwood, robh+dt, mark.rutland, perex, tiwai, ckeepax, rf,
srinivas.kandagatla, piotrs, paul, kmarinushkin, anders.roxell,
jbrunet, m.felsch, vkoul, nh6z, alsa-devel, devicetree,
linux-kernel, daniel.baluta
In-Reply-To: <20190731111930.20230-1-andradanciu1997@gmail.com>
The UDA1334BTS supports the I2S-bus data format with word lengths of up
to 24 bits serial data format and has basic features such as de-emphasis
(at 44.1 kHz sampling rate) and mute.
Datasheet can be found at:
https://www.nxp.com/docs/en/data-sheet/UDA1334BTS.pdf
Cc: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Andra Danciu <andradanciu1997@gmail.com>
---
sound/soc/codecs/Kconfig | 9 ++
sound/soc/codecs/Makefile | 2 +
sound/soc/codecs/uda1334.c | 295 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 306 insertions(+)
create mode 100644 sound/soc/codecs/uda1334.c
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index da4c1ae89742..89238343e34d 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -199,6 +199,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_TS3A227E if I2C
select SND_SOC_TWL4030 if TWL4030_CORE
select SND_SOC_TWL6040 if TWL6040_CORE
+ select SND_SOC_UDA1334 if GPIOLIB
select SND_SOC_UDA134X
select SND_SOC_UDA1380 if I2C
select SND_SOC_WCD9335 if SLIMBUS
@@ -1207,6 +1208,14 @@ config SND_SOC_TWL4030
config SND_SOC_TWL6040
tristate
+config SND_SOC_UDA1334
+ tristate "NXP UDA1334 DAC"
+ depends on GPIOLIB
+ help
+ The UDA1334 is an NXP audio codec, supports the I2S-bus data format
+ and has basic features such as de-emphasis (at 44.1 kHz sampling
+ rate) and mute.
+
config SND_SOC_UDA134X
tristate
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 9230016b0f9f..c498373dcc5f 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -212,6 +212,7 @@ snd-soc-tscs454-objs := tscs454.o
snd-soc-ts3a227e-objs := ts3a227e.o
snd-soc-twl4030-objs := twl4030.o
snd-soc-twl6040-objs := twl6040.o
+snd-soc-uda1334-objs := uda1334.o
snd-soc-uda134x-objs := uda134x.o
snd-soc-uda1380-objs := uda1380.o
snd-soc-wcd9335-objs := wcd-clsh-v2.o wcd9335.o
@@ -494,6 +495,7 @@ obj-$(CONFIG_SND_SOC_TSCS454) += snd-soc-tscs454.o
obj-$(CONFIG_SND_SOC_TS3A227E) += snd-soc-ts3a227e.o
obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o
obj-$(CONFIG_SND_SOC_TWL6040) += snd-soc-twl6040.o
+obj-$(CONFIG_SND_SOC_UDA1334) += snd-soc-uda1334.o
obj-$(CONFIG_SND_SOC_UDA134X) += snd-soc-uda134x.o
obj-$(CONFIG_SND_SOC_UDA1380) += snd-soc-uda1380.o
obj-$(CONFIG_SND_SOC_WCD9335) += snd-soc-wcd9335.o
diff --git a/sound/soc/codecs/uda1334.c b/sound/soc/codecs/uda1334.c
new file mode 100644
index 000000000000..21ab8c5487ba
--- /dev/null
+++ b/sound/soc/codecs/uda1334.c
@@ -0,0 +1,295 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// uda1334.c -- UDA1334 ALSA SoC Audio driver
+//
+// Based on WM8523 ALSA SoC Audio driver written by Mark Brown
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/gpio/consumer.h>
+#include <linux/of_device.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/initval.h>
+
+#define UDA1334_NUM_RATES 6
+
+/* codec private data */
+struct uda1334_priv {
+ struct gpio_desc *mute;
+ struct gpio_desc *deemph;
+ unsigned int sysclk;
+ unsigned int rate_constraint_list[UDA1334_NUM_RATES];
+ struct snd_pcm_hw_constraint_list rate_constraint;
+};
+
+static const struct snd_soc_dapm_widget uda1334_dapm_widgets[] = {
+SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
+SND_SOC_DAPM_OUTPUT("LINEVOUTL"),
+SND_SOC_DAPM_OUTPUT("LINEVOUTR"),
+};
+
+static const struct snd_soc_dapm_route uda1334_dapm_routes[] = {
+ { "LINEVOUTL", NULL, "DAC" },
+ { "LINEVOUTR", NULL, "DAC" },
+};
+
+static int uda1334_put_deemph(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
+ struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
+ int deemph = ucontrol->value.integer.value[0];
+
+ if (deemph > 1)
+ return -EINVAL;
+
+ gpiod_set_value_cansleep(uda1334->deemph, deemph);
+
+ return 0;
+};
+
+static int uda1334_get_deemph(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
+ struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
+ int ret;
+
+ ret = gpiod_get_value_cansleep(uda1334->deemph);
+ if (ret < 0)
+ return -EINVAL;
+
+ ucontrol->value.integer.value[0] = ret;
+
+ return 0;
+};
+
+static const struct snd_kcontrol_new uda1334_snd_controls[] = {
+ SOC_SINGLE_BOOL_EXT("Playback Deemphasis Switch", 0,
+ uda1334_get_deemph, uda1334_put_deemph),
+};
+
+static const struct {
+ int value;
+ int ratio;
+} lrclk_ratios[UDA1334_NUM_RATES] = {
+ { 1, 128 },
+ { 2, 192 },
+ { 3, 256 },
+ { 4, 384 },
+ { 5, 512 },
+ { 6, 768 },
+};
+
+static int uda1334_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_component *component = dai->component;
+ struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
+
+ /*
+ * The set of sample rates that can be supported depends on the
+ * MCLK supplied to the CODEC - enforce this.
+ */
+ if (!uda1334->sysclk) {
+ dev_err(component->dev,
+ "No MCLK configured, call set_sysclk() on init\n");
+ return -EINVAL;
+ }
+
+ snd_pcm_hw_constraint_list(substream->runtime, 0,
+ SNDRV_PCM_HW_PARAM_RATE,
+ &uda1334->rate_constraint);
+
+ gpiod_set_value_cansleep(uda1334->mute, 1);
+
+ return 0;
+}
+
+static void uda1334_shutdown(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_component *component = dai->component;
+ struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
+
+ gpiod_set_value_cansleep(uda1334->mute, 0);
+}
+
+static int uda1334_set_dai_sysclk(struct snd_soc_dai *codec_dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ struct snd_soc_component *component = codec_dai->component;
+ struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
+ unsigned int val;
+ int i, j = 0;
+
+ uda1334->sysclk = freq;
+
+ uda1334->rate_constraint.count = 0;
+ for (i = 0; i < ARRAY_SIZE(lrclk_ratios); i++) {
+ val = freq / lrclk_ratios[i].ratio;
+ /*
+ * Check that it's a standard rate since core can't
+ * cope with others and having the odd rates confuses
+ * constraint matching.
+ */
+
+ switch (val) {
+ case 8000:
+ case 32000:
+ case 44100:
+ case 48000:
+ case 64000:
+ case 88200:
+ case 96000:
+ dev_dbg(component->dev, "Supported sample rate: %dHz\n",
+ val);
+ uda1334->rate_constraint_list[j++] = val;
+ uda1334->rate_constraint.count++;
+ break;
+ default:
+ dev_dbg(component->dev, "Skipping sample rate: %dHz\n",
+ val);
+ }
+ }
+
+ /* Need at least one supported rate... */
+ if (uda1334->rate_constraint.count == 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int uda1334_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
+{
+ fmt &= (SND_SOC_DAIFMT_FORMAT_MASK | SND_SOC_DAIFMT_INV_MASK |
+ SND_SOC_DAIFMT_MASTER_MASK);
+
+ if (fmt != (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
+ SND_SOC_DAIFMT_CBS_CFS)) {
+ dev_err(codec_dai->dev, "Invalid DAI format\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int uda1334_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
+{
+ struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(dai->component);
+
+ if (uda1334->mute)
+ gpiod_set_value_cansleep(uda1334->mute, mute);
+
+ return 0;
+}
+
+#define UDA1334_RATES SNDRV_PCM_RATE_8000_96000
+
+#define UDA1334_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE)
+
+static const struct snd_soc_dai_ops uda1334_dai_ops = {
+ .startup = uda1334_startup,
+ .shutdown = uda1334_shutdown,
+ .set_sysclk = uda1334_set_dai_sysclk,
+ .set_fmt = uda1334_set_fmt,
+ .mute_stream = uda1334_mute_stream,
+};
+
+static struct snd_soc_dai_driver uda1334_dai = {
+ .name = "uda1334-hifi",
+ .playback = {
+ .stream_name = "Playback",
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = UDA1334_RATES,
+ .formats = UDA1334_FORMATS,
+ },
+ .ops = &uda1334_dai_ops,
+};
+
+static int uda1334_probe(struct snd_soc_component *component)
+{
+ struct uda1334_priv *uda1334 = snd_soc_component_get_drvdata(component);
+
+ uda1334->rate_constraint.list = &uda1334->rate_constraint_list[0];
+ uda1334->rate_constraint.count =
+ ARRAY_SIZE(uda1334->rate_constraint_list);
+
+ return 0;
+}
+
+static const struct snd_soc_component_driver soc_component_dev_uda1334 = {
+ .probe = uda1334_probe,
+ .controls = uda1334_snd_controls,
+ .num_controls = ARRAY_SIZE(uda1334_snd_controls),
+ .dapm_widgets = uda1334_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(uda1334_dapm_widgets),
+ .dapm_routes = uda1334_dapm_routes,
+ .num_dapm_routes = ARRAY_SIZE(uda1334_dapm_routes),
+ .idle_bias_on = 1,
+ .use_pmdown_time = 1,
+ .endianness = 1,
+ .non_legacy_dai_naming = 1,
+};
+
+static const struct of_device_id uda1334_of_match[] = {
+ { .compatible = "nxp,uda1334" },
+ { /* sentinel*/ }
+};
+MODULE_DEVICE_TABLE(of, uda1334_of_match);
+
+static int uda1334_codec_probe(struct platform_device *pdev)
+{
+ struct uda1334_priv *uda1334;
+ int ret;
+
+ uda1334 = devm_kzalloc(&pdev->dev, sizeof(struct uda1334_priv),
+ GFP_KERNEL);
+ if (!uda1334)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, uda1334);
+
+ uda1334->mute = devm_gpiod_get(&pdev->dev, "nxp,mute", GPIOD_OUT_LOW);
+ if (IS_ERR(uda1334->mute)) {
+ ret = PTR_ERR(uda1334->mute);
+ dev_err(&pdev->dev, "Failed to get mute line: %d\n", ret);
+ return ret;
+ }
+
+ uda1334->deemph = devm_gpiod_get(&pdev->dev, "nxp,deemph", GPIOD_OUT_LOW);
+ if (IS_ERR(uda1334->deemph)) {
+ ret = PTR_ERR(uda1334->deemph);
+ dev_err(&pdev->dev, "Failed to get deemph line: %d\n", ret);
+ return ret;
+ }
+
+ ret = devm_snd_soc_register_component(&pdev->dev,
+ &soc_component_dev_uda1334,
+ &uda1334_dai, 1);
+ if (ret < 0)
+ dev_err(&pdev->dev, "Failed to register component: %d\n", ret);
+
+ return ret;
+}
+
+static struct platform_driver uda1334_codec_driver = {
+ .probe = uda1334_codec_probe,
+ .driver = {
+ .name = "uda1334-codec",
+ .of_match_table = uda1334_of_match,
+ },
+};
+module_platform_driver(uda1334_codec_driver);
+
+MODULE_DESCRIPTION("ASoC UDA1334 driver");
+MODULE_AUTHOR("Andra Danciu <andradanciu1997@gmail.com>");
+MODULE_ALIAS("platform:uda1334-codec");
+MODULE_LICENSE("GPL v2");
--
2.11.0
^ permalink raw reply related
* [PATCH 1/2] dt-bindings: sound: Add bindings for UDA1334 codec
From: Andra Danciu @ 2019-07-31 11:19 UTC (permalink / raw)
To: broonie
Cc: lgirdwood, robh+dt, mark.rutland, perex, tiwai, ckeepax, rf,
srinivas.kandagatla, piotrs, paul, kmarinushkin, anders.roxell,
jbrunet, m.felsch, vkoul, nh6z, alsa-devel, devicetree,
linux-kernel, daniel.baluta
In-Reply-To: <20190731111930.20230-1-andradanciu1997@gmail.com>
The UDA1334 is an NXP audio codec, supports the I2S-bus data format
and has basic features such as de-emphasis (at 44.1 kHz sampling
rate) and mute. Product information can be found at:
https://www.nxp.com/pages/low-power-audio-dac-with-pll:UDA1334
Cc: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Andra Danciu <andradanciu1997@gmail.com>
---
Documentation/devicetree/bindings/sound/uda1334.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/uda1334.txt
diff --git a/Documentation/devicetree/bindings/sound/uda1334.txt b/Documentation/devicetree/bindings/sound/uda1334.txt
new file mode 100644
index 000000000000..f64071b25e8d
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/uda1334.txt
@@ -0,0 +1,17 @@
+UDA1334 audio CODEC
+
+This device uses simple GPIO pins for controlling codec settings.
+
+Required properties:
+
+ - compatible : "nxp,uda1334"
+ - nxp,mute-gpios: a GPIO spec for the MUTE pin.
+ - nxp,deemph-gpios: a GPIO spec for the De-emphasis pin
+
+Example:
+
+uda1334: audio-codec {
+ compatible = "nxp,uda1334";
+ nxp,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+ nxp,deemph-gpios = <&gpio3 3 GPIO_ACTIVE_LOW>;
+};
--
2.11.0
^ permalink raw reply related
* [PATCH 0/2] ASoC: Add uda1334 codec driver
From: Andra Danciu @ 2019-07-31 11:19 UTC (permalink / raw)
To: broonie
Cc: lgirdwood, robh+dt, mark.rutland, perex, tiwai, ckeepax, rf,
srinivas.kandagatla, piotrs, paul, kmarinushkin, anders.roxell,
jbrunet, m.felsch, vkoul, nh6z, alsa-devel, devicetree,
linux-kernel, daniel.baluta
The first patch contains uda1334 documentation.
The second patch contains the codec driver.
Andra Danciu (2):
dt-bindings: sound: Add bindings for UDA1334 codec
ASoC: codecs: Add uda1334 codec driver
.../devicetree/bindings/sound/uda1334.txt | 17 ++
sound/soc/codecs/Kconfig | 9 +
sound/soc/codecs/Makefile | 2 +
sound/soc/codecs/uda1334.c | 295 +++++++++++++++++++++
4 files changed, 323 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/uda1334.txt
create mode 100644 sound/soc/codecs/uda1334.c
--
2.11.0
^ permalink raw reply
* Re: [PATCH v7 11/20] cpufreq: tegra124: Add suspend and resume support
From: Dmitry Osipenko @ 2019-07-31 11:14 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <98aae4b7-d95a-90ba-0d55-7512b3712f54@gmail.com>
31.07.2019 13:23, Dmitry Osipenko пишет:
> 31.07.2019 3:20, Sowjanya Komatineni пишет:
>> This patch adds suspend and resume pm ops for cpufreq driver.
>>
>> PLLP is the safe clock source for CPU during system suspend and
>> resume as PLLP rate is below the CPU Fmax at Vmin.
>>
>> CPUFreq driver suspend switches the CPU clock source to PLLP and
>> disables the DFLL clock.
>>
>> During system resume, warmboot code powers up the CPU with PLLP
>> clock source. So CPUFreq driver resume enabled DFLL clock and
>> switches CPU back to DFLL clock source.
>>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> ---
>> drivers/cpufreq/tegra124-cpufreq.c | 60 ++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 60 insertions(+)
>>
>> diff --git a/drivers/cpufreq/tegra124-cpufreq.c b/drivers/cpufreq/tegra124-cpufreq.c
>> index 4f0c637b3b49..e979a3370988 100644
>> --- a/drivers/cpufreq/tegra124-cpufreq.c
>> +++ b/drivers/cpufreq/tegra124-cpufreq.c
>> @@ -6,6 +6,7 @@
>> #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
>>
>> #include <linux/clk.h>
>> +#include <linux/cpufreq.h>
>> #include <linux/err.h>
>> #include <linux/init.h>
>> #include <linux/kernel.h>
>> @@ -128,8 +129,67 @@ static int tegra124_cpufreq_probe(struct platform_device *pdev)
>> return ret;
>> }
>>
>> +static int __maybe_unused tegra124_cpufreq_suspend(struct device *dev)
>> +{
>> + struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev);
>> + int err;
>> +
>> + /*
>> + * PLLP rate 408Mhz is below the CPU Fmax at Vmin and is safe to
>> + * use during suspend and resume. So, switch the CPU clock source
>> + * to PLLP and disable DFLL.
>> + */
>> + err = clk_set_parent(priv->cpu_clk, priv->pllp_clk);
>> + if (err < 0) {
>> + dev_err(dev, "failed to reparent to PLLP: %d\n", err);
>> + return err;
>> + }
>> +
>> + /* disable DFLL clock */
>> + clk_disable_unprepare(priv->dfll_clk);
>> +
>> + return 0;
>> +}
>> +
>> +static int __maybe_unused tegra124_cpufreq_resume(struct device *dev)
>> +{
>> + struct tegra124_cpufreq_priv *priv = dev_get_drvdata(dev);
>> + int err;
>> +
>> + /*
>> + * Warmboot code powers up the CPU with PLLP clock source.
>> + * Enable DFLL clock and switch CPU clock source back to DFLL.
>> + */
>> + err = clk_prepare_enable(priv->dfll_clk);
>> + if (err < 0) {
>> + dev_err(dev, "failed to enable DFLL clock for CPU: %d\n", err);
>> + goto disable_cpufreq;
>> + }
>> +
>> + err = clk_set_parent(priv->cpu_clk, priv->dfll_clk);
>> + if (err < 0) {
>> + dev_err(dev, "failed to reparent to DFLL clock: %d\n", err);
>> + goto disable_dfll;
>> + }
>> +
>> + return 0;
>> +
>> +disable_dfll:
>> + clk_disable_unprepare(priv->dfll_clk);
>> +disable_cpufreq:
>> + disable_cpufreq();
>> +
>> + return err;
>> +}
>> +
>> +static const struct dev_pm_ops tegra124_cpufreq_pm_ops = {
>> + SET_SYSTEM_SLEEP_PM_OPS(tegra124_cpufreq_suspend,
>> + tegra124_cpufreq_resume)
>> +};
>> +
>> static struct platform_driver tegra124_cpufreq_platdrv = {
>> .driver.name = "cpufreq-tegra124",
>> + .driver.pm = &tegra124_cpufreq_pm_ops,
>> .probe = tegra124_cpufreq_probe,
>> };
>>
>>
>
> Looks good,
>
> Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
>
BTW, you should also CC the CPUFreq maintainers because this patch can't
be applied without theirs ACK.
^ permalink raw reply
* Re: [PATCH 11/22] ARM: dts: imx6: Add sleep state to can interfaces
From: Philippe Schenker @ 2019-07-31 11:13 UTC (permalink / raw)
To: stefan@agner.ch, Marcel Ziswiler, Max Krummenacher,
mark.rutland@arm.com, devicetree@vger.kernel.org,
michal.vokac@ysoft.com, shawnguo@kernel.org, robh+dt@kernel.org
Cc: festevam@gmail.com, linux-arm-kernel@lists.infradead.org,
kernel@pengutronix.de, s.hauer@pengutronix.de,
linux-kernel@vger.kernel.org, linux-imx@nxp.com
In-Reply-To: <86f1e50b-97d6-5bdb-7cc2-e7dc162d147a@ysoft.com>
On Wed, 2019-07-31 at 09:14 +0200, Michal Vokáč wrote:
> On 30. 07. 19 16:46, Philippe Schenker wrote:
> > From: Philippe Schenker <philippe.schenker@toradex.com>
> >
> > This patch prepares the devicetree for the new Ixora V1.2 where we are
> > able to turn off the supply of the can transceiver. This implies to use
> > a sleep state on transmission pins in order to prevent backfeeding.
> >
> > Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
> > ---
>
> What about "ARM: dts: imx6qdl-apalis: " for the subject?
> To be clear that this is not related to the imx6 SoC itself.
Thanks for your comments Michal! Will takte those into account for v2.
>
> > arch/arm/boot/dts/imx6qdl-apalis.dtsi | 27 +++++++++++++++++++++------
> > 1 file changed, 21 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> > b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> > index 7c4ad541c3f5..59ed2e4a1fd1 100644
> > --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> > +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
> > @@ -148,14 +148,16 @@
> > };
> >
> > &can1 {
> > - pinctrl-names = "default";
> > - pinctrl-0 = <&pinctrl_flexcan1>;
> > + pinctrl-names = "default", "sleep";
> > + pinctrl-0 = <&pinctrl_flexcan1_default>;
> > + pinctrl-1 = <&pinctrl_flexcan1_sleep>;
> > status = "disabled";
> > };
> >
> > &can2 {
> > - pinctrl-names = "default";
> > - pinctrl-0 = <&pinctrl_flexcan2>;
> > + pinctrl-names = "default", "sleep";
> > + pinctrl-0 = <&pinctrl_flexcan2_default>;
> > + pinctrl-1 = <&pinctrl_flexcan2_sleep>;
> > status = "disabled";
> > };
> >
> > @@ -599,19 +601,32 @@
> > >;
> > };
> >
> > - pinctrl_flexcan1: flexcan1grp {
> > + pinctrl_flexcan1_default: flexcan1defgrp {
> > fsl,pins = <
> > MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
> > MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
> > >;
> > };
> >
> > - pinctrl_flexcan2: flexcan2grp {
> > + pinctrl_flexcan1_sleep: flexcan1slpgrp {
> > + fsl,pins = <
> > + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0
> > + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0
> > + >;
> > + };
> > +
> > + pinctrl_flexcan2_default: flexcan2defgrp {
> > fsl,pins = <
> > MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
> > MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
> > >;
> > };
> > + pinctrl_flexcan2_sleep: flexcan2slpgrp {
> > + fsl,pins = <
> > + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0
> > + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0
> > + >;
> > + };
> >
> > pinctrl_gpio_bl_on: gpioblon {
> > fsl,pins = <
> >
^ permalink raw reply
* Re: [PATCH v7 06/20] clk: tegra: Support for OSC context save and restore
From: Dmitry Osipenko @ 2019-07-31 11:11 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <1564532424-10449-7-git-send-email-skomatineni@nvidia.com>
31.07.2019 3:20, Sowjanya Komatineni пишет:
> This patch adds support for saving OSC clock frequency and the
> drive-strength during OSC clock init and creates an API to restore
> OSC control register value from the saved context.
>
> This API is invoked by Tegra210 clock driver during system resume
> to restore the OSC clock settings.
>
> Acked-by: Thierry Reding <treding@nvidia.com>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/clk/tegra/clk-tegra-fixed.c | 15 +++++++++++++++
> drivers/clk/tegra/clk.h | 1 +
> 2 files changed, 16 insertions(+)
>
> diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c
> index 8d91b2b191cf..7c6c8abfcde6 100644
> --- a/drivers/clk/tegra/clk-tegra-fixed.c
> +++ b/drivers/clk/tegra/clk-tegra-fixed.c
> @@ -17,6 +17,10 @@
> #define OSC_CTRL 0x50
> #define OSC_CTRL_OSC_FREQ_SHIFT 28
> #define OSC_CTRL_PLL_REF_DIV_SHIFT 26
> +#define OSC_CTRL_MASK (0x3f2 | \
> + (0xf << OSC_CTRL_OSC_FREQ_SHIFT))
> +
> +static u32 osc_ctrl_ctx;
>
> int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
> unsigned long *input_freqs, unsigned int num,
> @@ -29,6 +33,7 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
> unsigned osc_idx;
>
> val = readl_relaxed(clk_base + OSC_CTRL);
> + osc_ctrl_ctx = val & OSC_CTRL_MASK;
> osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
>
> if (osc_idx < num)
> @@ -96,3 +101,13 @@ void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
> *dt_clk = clk;
> }
> }
> +
> +void tegra_clk_osc_resume(void __iomem *clk_base)
> +{
> + u32 val;
> +
> + val = readl_relaxed(clk_base + OSC_CTRL) & ~OSC_CTRL_MASK;
> + val |= osc_ctrl_ctx;
> + writel_relaxed(val, clk_base + OSC_CTRL);
Why a full raw u32 OSC_CTRL value couldn't be simply saved and restored?
> + fence_udelay(2, clk_base);
> +}
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index f1ef6ae8c979..abba6d8a04cd 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -842,6 +842,7 @@ u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
> int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);
> int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
> u8 frac_width, u8 flags);
> +void tegra_clk_osc_resume(void __iomem *clk_base);
>
>
> /* Combined read fence with delay */
>
^ permalink raw reply
* Re: [PATCH v7 16/20] arm64: tegra: Enable wake from deep sleep on RTC alarm
From: Dmitry Osipenko @ 2019-07-31 11:04 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <1564532424-10449-17-git-send-email-skomatineni@nvidia.com>
31.07.2019 3:20, Sowjanya Komatineni пишет:
> This patch updates device tree for RTC and PMC to allow system wake
> from deep sleep on RTC alarm.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> index 659753118e96..30a7c48385a2 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
> @@ -768,7 +768,8 @@
> rtc@7000e000 {
> compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
> reg = <0x0 0x7000e000 0x0 0x100>;
> - interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&pmc>;
> clocks = <&tegra_car TEGRA210_CLK_RTC>;
> clock-names = "rtc";
> };
> @@ -778,6 +779,8 @@
> reg = <0x0 0x7000e400 0x0 0x400>;
> clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
> clock-names = "pclk", "clk32k_in";
> + #interrupt-cells = <2>;
> + interrupt-controller;
>
> powergates {
> pd_audio: aud {
>
Is this a backwards-compatible change? Or it's not really worth to care
about the compatibility with older kernel versions, I'm not sure about
overall state of T210 in the upstream kernel.
^ permalink raw reply
* Re: [PATCH v7 03/20] clk: tegra: divider: Save and restore divider rate
From: Dmitry Osipenko @ 2019-07-31 10:49 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree
In-Reply-To: <1564532424-10449-4-git-send-email-skomatineni@nvidia.com>
31.07.2019 3:20, Sowjanya Komatineni пишет:
> This patch implements context restore for clock divider.
>
> During system suspend, core power goes off and looses the settings
> of the Tegra CAR controller registers.
>
> So on resume, clock dividers are restored back for normal operation.
>
> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
> ---
> drivers/clk/tegra/clk-divider.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
> index e76731fb7d69..ca0de5f11f84 100644
> --- a/drivers/clk/tegra/clk-divider.c
> +++ b/drivers/clk/tegra/clk-divider.c
> @@ -109,10 +109,21 @@ static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate,
> return 0;
> }
>
> +static void clk_divider_restore_context(struct clk_hw *hw)
> +{
> + struct clk_hw *parent = clk_hw_get_parent(hw);
> + unsigned long parent_rate = clk_hw_get_rate(parent);
> + unsigned long rate = clk_hw_get_rate(hw);
> +
> + if (clk_frac_div_set_rate(hw, rate, parent_rate) < 0)
> + WARN_ON(1);
> +}
> +
> const struct clk_ops tegra_clk_frac_div_ops = {
> .recalc_rate = clk_frac_div_recalc_rate,
> .set_rate = clk_frac_div_set_rate,
> .round_rate = clk_frac_div_round_rate,
> + .restore_context = clk_divider_restore_context,
> };
>
> struct clk *tegra_clk_register_divider(const char *name,
>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
^ permalink raw reply
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