* Re: [PATCH 2/4 v2] drm/panel: simple: Add TI nspire panel bindings
From: Rob Herring @ 2019-08-05 15:28 UTC (permalink / raw)
To: Linus Walleij
Cc: Fabian Vogt, Daniel Tang, dri-devel,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
devicetree
In-Reply-To: <20190805085847.25554-3-linus.walleij@linaro.org>
On Mon, Aug 5, 2019 at 2:59 AM Linus Walleij <linus.walleij@linaro.org> wrote:
>
> Add bindings for the TI NSPIRE simple display panels.
>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> ChangeLog v1->v2:
> - New patch as bindings are required
> - Let's use YAML
> ---
> .../bindings/display/panel/ti,nspire.yaml | 36 +++++++++++++++++++
> 1 file changed, 36 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/panel/ti,nspire.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/panel/ti,nspire.yaml b/Documentation/devicetree/bindings/display/panel/ti,nspire.yaml
> new file mode 100644
> index 000000000000..fa81602a922a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/panel/ti,nspire.yaml
> @@ -0,0 +1,36 @@
> +# SPDX-License-Identifier: (GPL-2.0+ OR X11)
I think you want MIT rather than X11. However, the preference on new
bindings is (GPL-2.0-only OR BSD-2-Clause).
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/panel/ti,nspire.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Texas Instruments NSPIRE Display Panels
> +
> +maintainers:
> + - Linus Walleij <linus.walleij@linaro.org>
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
You can drop this. Just 'enum' is sufficient.
> + - enum:
> + - ti,nspire-cx-lcd-panel
> + - ti,nspire-classic-lcd-panel
> +
> +required:
> + - compatible
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + panel {
> + compatible = "ti,nspire-cx-lcd-panel";
> + ports {
> + port {
You need to capture that there's a single port in the schema. There's
not really a lot of examples for this yet, but you should add:
allOf:
- $ref: panel-common.yaml#
With a single port, you can drop 'ports' or you can keep it. If you do
the latter, then you need to define 'ports' and then 'port' in your
schema. The common schema is only sufficient if you have a single
'port' node otherwise you need to define what's under 'ports'.
Rob
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCH 14/16] net: phy: adin: make sure down-speed auto-neg is enabled
From: Andrew Lunn @ 2019-08-05 15:22 UTC (permalink / raw)
To: Alexandru Ardelean
Cc: netdev, devicetree, linux-kernel, davem, robh+dt, mark.rutland,
f.fainelli, hkallweit1
In-Reply-To: <20190805165453.3989-15-alexandru.ardelean@analog.com>
On Mon, Aug 05, 2019 at 07:54:51PM +0300, Alexandru Ardelean wrote:
> Down-speed auto-negotiation may not always be enabled, in which case the
> PHY won't down-shift to 100 or 10 during auto-negotiation.
Please look at how the marvell driver enables and configures this
feature. Ideally we want all PHY drivers to use the same configuration
API for features like this.
Andrew
^ permalink raw reply
* Re: [PATCH 12/16] net: phy: adin: read EEE setting from device-tree
From: Andrew Lunn @ 2019-08-05 15:19 UTC (permalink / raw)
To: Alexandru Ardelean
Cc: netdev, devicetree, linux-kernel, davem, robh+dt, mark.rutland,
f.fainelli, hkallweit1
In-Reply-To: <20190805165453.3989-13-alexandru.ardelean@analog.com>
On Mon, Aug 05, 2019 at 07:54:49PM +0300, Alexandru Ardelean wrote:
> By default, EEE is not advertised on system init. This change allows the
> user to specify a device property to enable EEE advertisements when the PHY
> initializes.
This patch is not required. If EEE is not being advertised when it
should, it means there is a MAC driver bug.
Andrew
^ permalink raw reply
* Re: [PATCH 01/16] net: phy: adin: add support for Analog Devices PHYs
From: Andrew Lunn @ 2019-08-05 15:17 UTC (permalink / raw)
To: Alexandru Ardelean
Cc: netdev, devicetree, linux-kernel, davem, robh+dt, mark.rutland,
f.fainelli, hkallweit1
In-Reply-To: <20190805165453.3989-2-alexandru.ardelean@analog.com>
> +static struct phy_driver adin_driver[] = {
> + {
> + .phy_id = PHY_ID_ADIN1200,
> + .name = "ADIN1200",
> + .phy_id_mask = 0xfffffff0,
> + .features = PHY_BASIC_FEATURES,
Do you need this? If the device implements the registers correctly,
phylib can determine this from the registers.
> + .config_init = adin_config_init,
> + .config_aneg = genphy_config_aneg,
> + .read_status = genphy_read_status,
> + },
> + {
> + .phy_id = PHY_ID_ADIN1300,
> + .name = "ADIN1300",
> + .phy_id_mask = 0xfffffff0,
> + .features = PHY_GBIT_FEATURES,
same here.
> + .config_init = adin_config_init,
> + .config_aneg = genphy_config_aneg,
> + .read_status = genphy_read_status,
> + },
> +};
> +
> +module_phy_driver(adin_driver);
> +
> +static struct mdio_device_id __maybe_unused adin_tbl[] = {
> + { PHY_ID_ADIN1200, 0xfffffff0 },
> + { PHY_ID_ADIN1300, 0xfffffff0 },
PHY_ID_MATCH_VENDOR().
Andrew
^ permalink raw reply
* Re: [PATCH 11/16] net: phy: adin: PHY reset mechanisms
From: Andrew Lunn @ 2019-08-05 15:15 UTC (permalink / raw)
To: Alexandru Ardelean
Cc: netdev, devicetree, linux-kernel, davem, robh+dt, mark.rutland,
f.fainelli, hkallweit1
In-Reply-To: <20190805165453.3989-12-alexandru.ardelean@analog.com>
On Mon, Aug 05, 2019 at 07:54:48PM +0300, Alexandru Ardelean wrote:
> The ADIN PHYs supports 4 types of reset:
> 1. The standard PHY reset via BMCR_RESET bit in MII_BMCR reg
> 2. Reset via GPIO
> 3. Reset via reg GeSftRst (0xff0c) & reload previous pin configs
> 4. Reset via reg GeSftRst (0xff0c) & request new pin configs
>
> Resets 2 & 4 are almost identical, with the exception that the crystal
> oscillator is available during reset for 2.
>
> Resetting via GeSftRst or via GPIO is useful when doing a warm reboot. If
> doing various settings via phytool or ethtool, the sub-system registers
> don't reset just via BMCR_RESET.
>
> This change implements resetting the entire PHY subsystem during probe.
> During PHY HW init (phy_hw_init() logic) the PHY core regs will be reset
> again via BMCR_RESET. This will also need to happen during a PM resume.
phylib already has support for GPIO reset. So if possible, you should
not repeat that code here.
What is the difference between a GPIO reset, and a GPIO reset followed
by a subsystem soft reset?
Andrew
^ permalink raw reply
* Re: [PATCH v1 1/1] dt-bindings: Add Vendor prefix for Beiqi
From: Rob Herring @ 2019-08-05 15:11 UTC (permalink / raw)
To: Elon Zhang
Cc: Mark Rutland, Manivannan Sadhasivam, linux-kernel@vger.kernel.org,
devicetree, luowz
In-Reply-To: <20190805023953.11231-1-zhangzj@rock-chips.com>
On Sun, Aug 4, 2019 at 8:40 PM Elon Zhang <zhangzj@rock-chips.com> wrote:
>
> Add devicetree vendor prefix for Beiqi.
> http://www.beiqicloud.com/
>
> Signed-off-by: Elon Zhang <zhangzj@rock-chips.com>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v4 1/6] dt-bindings: soc: qcom: add On Chip MEMory (OCMEM) bindings
From: Rob Herring @ 2019-08-05 15:10 UTC (permalink / raw)
To: Brian Masney
Cc: Andy Gross, Rob Clark, Sean Paul, Bjorn Andersson, David Airlie,
Daniel Vetter, Mark Rutland, Jonathan Marek, linux-arm-msm,
linux-kernel@vger.kernel.org, dri-devel, freedreno, devicetree,
Jordan Crouse
In-Reply-To: <20190803142026.9647-2-masneyb@onstation.org>
On Sat, Aug 3, 2019 at 8:20 AM Brian Masney <masneyb@onstation.org> wrote:
>
> Add device tree bindings for the On Chip Memory (OCMEM) that is present
> on some Qualcomm Snapdragon SoCs.
>
> Signed-off-by: Brian Masney <masneyb@onstation.org>
> ---
> Changes since v3
> - add ranges property
> - remove unnecessary literal block |
> - add #address-cells and #size-cells to binding
> - rename path devicetree/bindings/sram/qcom/ to devicetree/bindings/sram/ since
> this is the only qcom binding in the sram namespace. That was a holdover from
> when I originally put this in the soc namespace.
>
> Changes since v2:
> - Add *-sram node and gmu-sram to example.
>
> Changes since v1:
> - Rename qcom,ocmem-msm8974 to qcom,msm8974-ocmem
> - Renamed reg-names to ctrl and mem
> - update hardware description
> - moved from soc to sram namespace in the device tree bindings
>
> .../devicetree/bindings/sram/qcom,ocmem.yaml | 96 +++++++++++++++++++
> 1 file changed, 96 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
>
> diff --git a/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml b/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
> new file mode 100644
> index 000000000000..1bb386fffa01
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml
> @@ -0,0 +1,96 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/sram/qcom/qcom,ocmem.yaml#
Need to update the path here too.
With that,
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 3/5] MIPS: lantiq: add an irq_domain and irq_chip for EBU
From: Marc Zyngier @ 2019-08-05 15:03 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: tglx, jason, ralf, paul.burton, jhogan, robh+dt, linux-mips,
devicetree, linux-kernel, mark.rutland, john, Hauke Mehrtens
In-Reply-To: <CAFBinCDRBmG39Pa4XBa2Bu8K6GH7iz_YyKoJ795XKTnEz2b4VQ@mail.gmail.com>
On 03/08/2019 18:33, Martin Blumenstingl wrote:
> Hi Marc,
>
> On Sat, Aug 3, 2019 at 11:12 AM Marc Zyngier <maz@kernel.org> wrote:
>>
>> Hi Martin,
>>
>> On Thu, 01 Aug 2019 18:42:42 +0100,
>> Martin Blumenstingl <martin.blumenstingl@googlemail.com> wrote:
>>
>> [...]
>>
>>>>> +static void ltq_ebu_irq_handler(struct irq_desc *desc)
>>>>> +{
>>>>> + struct irq_domain *domain = irq_desc_get_handler_data(desc);
>>>>> + struct irq_chip *irqchip = irq_desc_get_chip(desc);
>>>>> +
>>>>> + chained_irq_enter(irqchip, desc);
>>>>> +
>>>>> + generic_handle_irq(irq_find_mapping(domain, 0));
>>>>
>>>> Having an irqdomain for a single interrupt is a bit over the top... Is
>>>> that for the convenience of the DT infrastructure?
>>> yes, I did it to get DT support
>>> please let me know if there's a "better" way (preferably with another
>>> driver as example)
>>
>> To be honest, the chained handler is what troubles me the most. You
>> normally would use such a construct if you had a multiplexer. In your
>> case, you have a 1:1 relationship between input and output. It is just
>> that this irqchip allows the trigger to be adapted, which normally
>> calls for a hierarchical implementation.
>>
>> In your case, with only a single interrupt, it doesn't matter much
>> though.
> I see, thank you for the explanation
>
> can you name a driver for a hierarchical irqchip driver that you
> consider "clean" which I could use as reference?
Finding a "clean" driver is a challenge, as the world of IRQ controllers
is where both HW and SW engineers (me included) love to "innovate" ;-).
I'd recommend you have a look at drivers/irqchip/irq-mtk-cirq.c, which
is almost as simple as it gets.
Thanks,
M.
--
Jazz is not dead, it just smells funny...
^ permalink raw reply
* [PATCHv2] drivers/amba: add reset control to primecell probe
From: Dinh Nguyen @ 2019-08-05 14:52 UTC (permalink / raw)
To: devicetree
Cc: dinguyen, linux-kernel, robh+dt, frowand.list, keescook, anton,
ccross, tony.luck
The primecell controller on some SoCs, i.e. SoCFPGA, is held in reset by
default. Until recently, the DMA controller was brought out of reset by the
bootloader(i.e. U-Boot). But a recent change in U-Boot, the peripherals that
are not used are held in reset and are left to Linux to bring them out of
reset.
Add a mechanism for getting the reset property and de-assert the primecell
module from reset if found. This is a not a hard fail if the reset property
is not present in the device tree node, so the driver will continue to probe.
Because there are different variants of the controller that may have multiple
reset signals, the code will find all reset(s) specified and de-assert them.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: move reset control to bus code
find all reset properties and de-assert them
---
drivers/amba/bus.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/amba/bus.c b/drivers/amba/bus.c
index 100e798a5c82..75e18b9e4808 100644
--- a/drivers/amba/bus.c
+++ b/drivers/amba/bus.c
@@ -18,6 +18,7 @@
#include <linux/limits.h>
#include <linux/clk/clk-conf.h>
#include <linux/platform_device.h>
+#include <linux/reset.h>
#include <asm/irq.h>
@@ -401,6 +402,18 @@ static int amba_device_try_add(struct amba_device *dev, struct resource *parent)
ret = amba_get_enable_pclk(dev);
if (ret == 0) {
u32 pid, cid;
+ int count;
+ struct reset_control *rstc;
+
+ /*
+ * Find reset control(s) of the amba bus and de-assert them.
+ */
+ count = reset_control_get_count(&dev->dev);
+ while (count > 0) {
+ rstc = of_reset_control_get_shared_by_index(dev->dev.of_node, count - 1);
+ reset_control_deassert(rstc);
+ count--;
+ }
/*
* Read pid and cid based on size of resource
--
2.20.0
^ permalink raw reply related
* Re: [PATCH 06/16] net: phy: adin: support PHY mode converters
From: Andrew Lunn @ 2019-08-05 14:51 UTC (permalink / raw)
To: Alexandru Ardelean
Cc: netdev, devicetree, linux-kernel, davem, robh+dt, mark.rutland,
f.fainelli, hkallweit1
In-Reply-To: <20190805165453.3989-7-alexandru.ardelean@analog.com>
On Mon, Aug 05, 2019 at 07:54:43PM +0300, Alexandru Ardelean wrote:
> Sometimes, the connection between a MAC and PHY is done via a
> mode/interface converter. An example is a GMII-to-RGMII converter, which
> would mean that the MAC operates in GMII mode while the PHY operates in
> RGMII. In this case there is a discrepancy between what the MAC expects &
> what the PHY expects and both need to be configured in their respective
> modes.
>
> Sometimes, this converter is specified via a board/system configuration (in
> the device-tree for example). But, other times it can be left unspecified.
> The use of these converters is common in boards that have FPGA on them.
>
> This patch also adds support for a `adi,phy-mode-internal` property that
> can be used in these (implicit convert) cases. The internal PHY mode will
> be used to specify the correct register settings for the PHY.
>
> `fwnode_handle` is used, since this property may be specified via ACPI as
> well in other setups, but testing has been done in DT context.
Looking at the patch, you seems to assume phy-mode is what the MAC is
using? That seems rather odd, given the name. It seems like a better
solution would be to add a mac-mode, which the MAC uses to configure
its side of the link. The MAC driver would then implement this
property.
I don't see a need for this. phy-mode indicates what the PHY should
use. End of story.
Andrew
^ permalink raw reply
* Re: [PATCH 05/16] net: phy: adin: configure RGMII/RMII/MII modes on config
From: Andrew Lunn @ 2019-08-05 14:39 UTC (permalink / raw)
To: Alexandru Ardelean
Cc: netdev, devicetree, linux-kernel, davem, robh+dt, mark.rutland,
f.fainelli, hkallweit1
In-Reply-To: <20190805165453.3989-6-alexandru.ardelean@analog.com>
On Mon, Aug 05, 2019 at 07:54:42PM +0300, Alexandru Ardelean wrote:
> The ADIN1300 chip supports RGMII, RMII & MII modes. Default (if
> unconfigured) is RGMII.
> This change adds support for configuring these modes via the device
> registers.
>
> For RGMII with internal delays (modes RGMII_ID,RGMII_TXID, RGMII_RXID),
It would be nice to add the missing space.
> the default delay is 2 ns. This can be configurable and will be done in
> a subsequent change.
>
> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
> ---
> drivers/net/phy/adin.c | 79 +++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 78 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
> index 3dd9fe50f4c8..dbdb8f60741c 100644
> --- a/drivers/net/phy/adin.c
> +++ b/drivers/net/phy/adin.c
> @@ -33,14 +33,91 @@
> ADIN1300_INT_HW_IRQ_EN)
> #define ADIN1300_INT_STATUS_REG 0x0019
>
> +#define ADIN1300_GE_RGMII_CFG_REG 0xff23
> +#define ADIN1300_GE_RGMII_RXID_EN BIT(2)
> +#define ADIN1300_GE_RGMII_TXID_EN BIT(1)
> +#define ADIN1300_GE_RGMII_EN BIT(0)
> +
> +#define ADIN1300_GE_RMII_CFG_REG 0xff24
> +#define ADIN1300_GE_RMII_EN BIT(0)
> +
> +static int adin_config_rgmii_mode(struct phy_device *phydev,
> + phy_interface_t intf)
> +{
> + int reg;
> +
> + reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RGMII_CFG_REG);
> + if (reg < 0)
> + return reg;
> +
> + if (!phy_interface_mode_is_rgmii(intf)) {
> + reg &= ~ADIN1300_GE_RGMII_EN;
> + goto write;
> + }
> +
> + reg |= ADIN1300_GE_RGMII_EN;
> +
> + if (intf == PHY_INTERFACE_MODE_RGMII_ID ||
> + intf == PHY_INTERFACE_MODE_RGMII_RXID) {
> + reg |= ADIN1300_GE_RGMII_RXID_EN;
> + } else {
> + reg &= ~ADIN1300_GE_RGMII_RXID_EN;
> + }
> +
> + if (intf == PHY_INTERFACE_MODE_RGMII_ID ||
> + intf == PHY_INTERFACE_MODE_RGMII_TXID) {
> + reg |= ADIN1300_GE_RGMII_TXID_EN;
> + } else {
> + reg &= ~ADIN1300_GE_RGMII_TXID_EN;
> + }
Nice. Often driver writers forget to clear the delay, they only set
it. Not so here.
However, is checkpatch happy with this? Each half of the if/else is a
single statement, so the {} are not needed.
> +
> +write:
> + return phy_write_mmd(phydev, MDIO_MMD_VEND1,
> + ADIN1300_GE_RGMII_CFG_REG, reg);
> +}
> +
> +static int adin_config_rmii_mode(struct phy_device *phydev,
> + phy_interface_t intf)
> +{
> + int reg;
> +
> + reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG);
> + if (reg < 0)
> + return reg;
> +
> + if (intf != PHY_INTERFACE_MODE_RMII) {
> + reg &= ~ADIN1300_GE_RMII_EN;
> + goto write;
goto? Really?
> + }
> +
> + reg |= ADIN1300_GE_RMII_EN;
> +
> +write:
> + return phy_write_mmd(phydev, MDIO_MMD_VEND1,
> + ADIN1300_GE_RMII_CFG_REG, reg);
> +}
> +
> static int adin_config_init(struct phy_device *phydev)
> {
> - int rc;
> + phy_interface_t interface, rc;
genphy_config_init() does not return a phy_interface_t!
>
> rc = genphy_config_init(phydev);
> if (rc < 0)
> return rc;
>
> + interface = phydev->interface;
> +
> + rc = adin_config_rgmii_mode(phydev, interface);
> + if (rc < 0)
> + return rc;
> +
> + rc = adin_config_rmii_mode(phydev, interface);
> + if (rc < 0)
> + return rc;
> +
> + dev_info(&phydev->mdio.dev, "PHY is using mode '%s'\n",
> + phy_modes(phydev->interface));
phydev_dbg(), or not at all.
Andrew
^ permalink raw reply
* [PATCH v5 4/4] edac: Add support for Amazon's Annapurna Labs L2 EDAC
From: Hanna Hawa @ 2019-08-05 14:39 UTC (permalink / raw)
To: robh+dt, mark.rutland, bp, mchehab, james.morse, davem, gregkh,
linus.walleij, Jonathan.Cameron, nicolas.ferre, paulmck
Cc: dwmw, benh, ronenk, talel, jonnyc, hanochu, devicetree,
linux-kernel, linux-edac, hhhawa
In-Reply-To: <20190805143911.12185-1-hhhawa@amazon.com>
Adds support for Amazon's Annapurna Labs L2 EDAC driver to detect and
report L2 errors.
Signed-off-by: Hanna Hawa <hhhawa@amazon.com>
Reviewed-by: James Morse <james.morse@arm.com>
---
MAINTAINERS | 6 ++
drivers/edac/Kconfig | 8 ++
drivers/edac/Makefile | 1 +
drivers/edac/al_l2_edac.c | 192 ++++++++++++++++++++++++++++++++++++++
4 files changed, 207 insertions(+)
create mode 100644 drivers/edac/al_l2_edac.c
diff --git a/MAINTAINERS b/MAINTAINERS
index fd29ea62ba29..a6dcf3d8e12a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -749,6 +749,12 @@ S: Maintained
F: drivers/edac/al_l1_edac.c
F: Documentation/devicetree/bindings/edac/amazon,al-l1-edac.txt
+AMAZON ANNAPURNA LABS L2 EDAC
+M: Hanna Hawa <hhhawa@amazon.com>
+S: Maintained
+F: drivers/edac/al_l2_edac.c
+F: Documentation/devicetree/bindings/edac/amazon,al-l2-edac.txt
+
AMAZON ANNAPURNA LABS THERMAL MMIO DRIVER
M: Talel Shenhar <talel@amazon.com>
S: Maintained
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 58b92bcb39ce..8bbb745b84ed 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -82,6 +82,14 @@ config EDAC_AL_L1
for Amazon's Annapurna Labs SoCs.
This driver detects errors of L1 caches.
+config EDAC_AL_L2
+ bool "Amazon's Annapurna Labs L2 EDAC"
+ depends on ARCH_ALPINE
+ help
+ Support for L2 error detection and correction
+ for Amazon's Annapurna Labs SoCs.
+ This driver detects errors of L2 caches.
+
config EDAC_AMD64
tristate "AMD64 (Opteron, Athlon64)"
depends on AMD_NB && EDAC_DECODE_MCE
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index caa2dc91e8a0..60a6b8bbe2f8 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -23,6 +23,7 @@ edac_mce_amd-y := mce_amd.o
obj-$(CONFIG_EDAC_DECODE_MCE) += edac_mce_amd.o
obj-$(CONFIG_EDAC_AL_L1) += al_l1_edac.o
+obj-$(CONFIG_EDAC_AL_L2) += al_l2_edac.o
obj-$(CONFIG_EDAC_AMD76X) += amd76x_edac.o
obj-$(CONFIG_EDAC_CPC925) += cpc925_edac.o
obj-$(CONFIG_EDAC_I5000) += i5000_edac.o
diff --git a/drivers/edac/al_l2_edac.c b/drivers/edac/al_l2_edac.c
new file mode 100644
index 000000000000..3dcca380d2aa
--- /dev/null
+++ b/drivers/edac/al_l2_edac.c
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ */
+
+#include <asm/sysreg.h>
+#include <linux/bitfield.h>
+#include <linux/cpumask.h>
+#include <linux/of.h>
+#include <linux/smp.h>
+
+#include "edac_device.h"
+#include "edac_module.h"
+
+#define DRV_NAME "al_l2_edac"
+
+/* Same bit assignments of L2MERRSR_EL1 in ARM CA57/CA72 */
+#define ARM_CA57_L2MERRSR_EL1 sys_reg(3, 1, 15, 2, 3)
+#define ARM_CA57_L2MERRSR_RAMID GENMASK(30, 24)
+#define ARM_CA57_L2_TAG_RAM 0x10
+#define ARM_CA57_L2_DATA_RAM 0x11
+#define ARM_CA57_L2_SNOOP_RAM 0x12
+#define ARM_CA57_L2_DIRTY_RAM 0x14
+#define ARM_CA57_L2_INC_PF_RAM 0x18
+#define ARM_CA57_L2MERRSR_VALID BIT(31)
+#define ARM_CA57_L2MERRSR_REPEAT GENMASK_ULL(39, 32)
+#define ARM_CA57_L2MERRSR_OTHER GENMASK_ULL(47, 40)
+#define ARM_CA57_L2MERRSR_FATAL BIT_ULL(63)
+
+#define AL_L2_EDAC_MSG_MAX 256
+
+struct al_l2_edac {
+ cpumask_t cluster_cpus;
+};
+
+static void al_l2_edac_l2merrsr(void *arg)
+{
+ struct edac_device_ctl_info *edac_dev = arg;
+ int cpu, i;
+ u32 ramid, repeat, other, fatal;
+ u64 val = read_sysreg_s(ARM_CA57_L2MERRSR_EL1);
+ char msg[AL_L2_EDAC_MSG_MAX];
+ int space, count;
+ char *p;
+
+ if (!(FIELD_GET(ARM_CA57_L2MERRSR_VALID, val)))
+ return;
+
+ write_sysreg_s(0, ARM_CA57_L2MERRSR_EL1);
+
+ cpu = smp_processor_id();
+ ramid = FIELD_GET(ARM_CA57_L2MERRSR_RAMID, val);
+ repeat = FIELD_GET(ARM_CA57_L2MERRSR_REPEAT, val);
+ other = FIELD_GET(ARM_CA57_L2MERRSR_OTHER, val);
+ fatal = FIELD_GET(ARM_CA57_L2MERRSR_FATAL, val);
+
+ space = sizeof(msg);
+ p = msg;
+ count = scnprintf(p, space, "CPU%d L2 %serror detected", cpu,
+ (fatal) ? "Fatal " : "");
+ p += count;
+ space -= count;
+
+ switch (ramid) {
+ case ARM_CA57_L2_TAG_RAM:
+ count = scnprintf(p, space, " RAMID='L2 Tag RAM'");
+ break;
+ case ARM_CA57_L2_DATA_RAM:
+ count = scnprintf(p, space, " RAMID='L2 Data RAM'");
+ break;
+ case ARM_CA57_L2_SNOOP_RAM:
+ count = scnprintf(p, space, " RAMID='L2 Snoop Tag RAM'");
+ break;
+ case ARM_CA57_L2_DIRTY_RAM:
+ count = scnprintf(p, space, " RAMID='L2 Dirty RAM'");
+ break;
+ case ARM_CA57_L2_INC_PF_RAM:
+ count = scnprintf(p, space, " RAMID='L2 internal metadata'");
+ break;
+ default:
+ count = scnprintf(p, space, " RAMID='unknown'");
+ break;
+ }
+
+ p += count;
+ space -= count;
+
+ count = scnprintf(p, space,
+ " repeat=%d, other=%d (L2MERRSR_EL1=0x%llx)",
+ repeat, other, val);
+
+ for (i = 0; i < repeat; i++) {
+ if (fatal)
+ edac_device_handle_ue(edac_dev, 0, 0, msg);
+ else
+ edac_device_handle_ce(edac_dev, 0, 0, msg);
+ }
+}
+
+static void al_l2_edac_check(struct edac_device_ctl_info *edac_dev)
+{
+ struct al_l2_edac *al_l2 = edac_dev->pvt_info;
+
+ smp_call_function_any(&al_l2->cluster_cpus, al_l2_edac_l2merrsr,
+ edac_dev, 1);
+}
+
+static int al_l2_edac_probe(struct platform_device *pdev)
+{
+ struct edac_device_ctl_info *edac_dev;
+ struct al_l2_edac *al_l2;
+ struct device *dev = &pdev->dev;
+ int ret, i;
+
+ edac_dev = edac_device_alloc_ctl_info(sizeof(*al_l2),
+ (char *)dev_name(dev), 1, "L", 1,
+ 2, NULL, 0,
+ edac_device_alloc_index());
+ if (IS_ERR_OR_NULL(edac_dev))
+ return -ENOMEM;
+
+ al_l2 = edac_dev->pvt_info;
+ edac_dev->edac_check = al_l2_edac_check;
+ edac_dev->dev = dev;
+ edac_dev->mod_name = DRV_NAME;
+ edac_dev->dev_name = dev_name(dev);
+ edac_dev->ctl_name = "L2 cache";
+ platform_set_drvdata(pdev, edac_dev);
+
+ for_each_possible_cpu(i) {
+ struct device_node *cpu;
+ struct device_node *cpu_cache, *l2_cache;
+
+ cpu = of_get_cpu_node(i, NULL);
+ cpu_cache = of_find_next_cache_node(cpu);
+ l2_cache = of_parse_phandle(dev->of_node, "l2-cache", 0);
+
+ if (cpu_cache == l2_cache)
+ cpumask_set_cpu(i, &al_l2->cluster_cpus);
+
+ of_node_put(cpu);
+ }
+
+ if (cpumask_empty(&al_l2->cluster_cpus)) {
+ dev_err(dev, "CPU mask is empty for this L2 cache\n");
+ ret = -EINVAL;
+ goto err;
+ }
+
+ ret = edac_device_add_device(edac_dev);
+ if (ret) {
+ dev_err(dev, "Failed to add L2 edac device\n");
+ goto err;
+ }
+
+ return 0;
+
+err:
+ edac_device_free_ctl_info(edac_dev);
+
+ return ret;
+}
+
+static int al_l2_edac_remove(struct platform_device *pdev)
+{
+ struct edac_device_ctl_info *edac_dev = platform_get_drvdata(pdev);
+
+ edac_device_del_device(edac_dev->dev);
+ edac_device_free_ctl_info(edac_dev);
+
+ return 0;
+}
+
+static const struct of_device_id al_l2_edac_of_match[] = {
+ { .compatible = "amazon,al-l2-edac" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, al_l2_edac_of_match);
+
+static struct platform_driver al_l2_edac_driver = {
+ .probe = al_l2_edac_probe,
+ .remove = al_l2_edac_remove,
+ .driver = {
+ .name = DRV_NAME,
+ .of_match_table = al_l2_edac_of_match,
+ },
+};
+module_platform_driver(al_l2_edac_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Hanna Hawa <hhhawa@amazon.com>");
+MODULE_DESCRIPTION("Amazon's Annapurna Lab's L2 EDAC Driver");
--
2.17.1
^ permalink raw reply related
* [PATCH v5 3/4] dt-bindings: EDAC: Add Amazon's Annapurna Labs L2 EDAC
From: Hanna Hawa @ 2019-08-05 14:39 UTC (permalink / raw)
To: robh+dt, mark.rutland, bp, mchehab, james.morse, davem, gregkh,
linus.walleij, Jonathan.Cameron, nicolas.ferre, paulmck
Cc: dwmw, benh, ronenk, talel, jonnyc, hanochu, devicetree,
linux-kernel, linux-edac, hhhawa
In-Reply-To: <20190805143911.12185-1-hhhawa@amazon.com>
Document Amazon's Annapurna Labs L2 EDAC SoC binding.
Signed-off-by: Hanna Hawa <hhhawa@amazon.com>
---
.../bindings/edac/amazon,al-l2-edac.txt | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 Documentation/devicetree/bindings/edac/amazon,al-l2-edac.txt
diff --git a/Documentation/devicetree/bindings/edac/amazon,al-l2-edac.txt b/Documentation/devicetree/bindings/edac/amazon,al-l2-edac.txt
new file mode 100644
index 000000000000..7b0b7347b711
--- /dev/null
+++ b/Documentation/devicetree/bindings/edac/amazon,al-l2-edac.txt
@@ -0,0 +1,20 @@
+* Amazon's Annapurna Labs L2 EDAC
+
+Amazon's Annapurna Labs SoCs supports L2 single bit correction and
+two bits detection capability based on ARM implementation.
+
+Required properties:
+- compatible:
+ should be "amazon,al-l2-edac".
+- l2-cache:
+ Phandle to L2 cache handler.
+ This property is used to compare with the CPU node property
+ 'next-level-cache' to create cpu-mask with all CPUs that
+ share same L2 cache.
+
+Example:
+
+ al_l2_edac {
+ compatible = "amazon,al-l2-edac";
+ l2-cache = <&cluster0_l2>;
+ };
--
2.17.1
^ permalink raw reply related
* [PATCH v5 2/4] edac: Add support for Amazon's Annapurna Labs L1 EDAC
From: Hanna Hawa @ 2019-08-05 14:39 UTC (permalink / raw)
To: robh+dt, mark.rutland, bp, mchehab, james.morse, davem, gregkh,
linus.walleij, Jonathan.Cameron, nicolas.ferre, paulmck
Cc: dwmw, benh, ronenk, talel, jonnyc, hanochu, devicetree,
linux-kernel, linux-edac, hhhawa
In-Reply-To: <20190805143911.12185-1-hhhawa@amazon.com>
Adds support for Amazon's Annapurna Labs L1 EDAC driver to detect and
report L1 errors.
Signed-off-by: Hanna Hawa <hhhawa@amazon.com>
Reviewed-by: James Morse <james.morse@arm.com>
---
MAINTAINERS | 6 ++
drivers/edac/Kconfig | 8 ++
drivers/edac/Makefile | 1 +
drivers/edac/al_l1_edac.c | 158 ++++++++++++++++++++++++++++++++++++++
4 files changed, 173 insertions(+)
create mode 100644 drivers/edac/al_l1_edac.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 77eae44bf5de..fd29ea62ba29 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -743,6 +743,12 @@ F: drivers/tty/serial/altera_jtaguart.c
F: include/linux/altera_uart.h
F: include/linux/altera_jtaguart.h
+AMAZON ANNAPURNA LABS L1 EDAC
+M: Hanna Hawa <hhhawa@amazon.com>
+S: Maintained
+F: drivers/edac/al_l1_edac.c
+F: Documentation/devicetree/bindings/edac/amazon,al-l1-edac.txt
+
AMAZON ANNAPURNA LABS THERMAL MMIO DRIVER
M: Talel Shenhar <talel@amazon.com>
S: Maintained
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 200c04ce5b0e..58b92bcb39ce 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -74,6 +74,14 @@ config EDAC_GHES
In doubt, say 'Y'.
+config EDAC_AL_L1
+ bool "Amazon's Annapurna Labs L1 EDAC"
+ depends on ARCH_ALPINE
+ help
+ Support for L1 error detection and correction
+ for Amazon's Annapurna Labs SoCs.
+ This driver detects errors of L1 caches.
+
config EDAC_AMD64
tristate "AMD64 (Opteron, Athlon64)"
depends on AMD_NB && EDAC_DECODE_MCE
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 165ca65e1a3a..caa2dc91e8a0 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_EDAC_GHES) += ghes_edac.o
edac_mce_amd-y := mce_amd.o
obj-$(CONFIG_EDAC_DECODE_MCE) += edac_mce_amd.o
+obj-$(CONFIG_EDAC_AL_L1) += al_l1_edac.o
obj-$(CONFIG_EDAC_AMD76X) += amd76x_edac.o
obj-$(CONFIG_EDAC_CPC925) += cpc925_edac.o
obj-$(CONFIG_EDAC_I5000) += i5000_edac.o
diff --git a/drivers/edac/al_l1_edac.c b/drivers/edac/al_l1_edac.c
new file mode 100644
index 000000000000..9404a2fcaa58
--- /dev/null
+++ b/drivers/edac/al_l1_edac.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ */
+
+#include <asm/sysreg.h>
+#include <linux/bitfield.h>
+#include <linux/smp.h>
+
+#include "edac_device.h"
+#include "edac_module.h"
+
+#define DRV_NAME "al_l1_edac"
+
+/* Same bit assignments of CPUMERRSR_EL1 in ARM CA57/CA72 */
+#define ARM_CA57_CPUMERRSR_EL1 sys_reg(3, 1, 15, 2, 2)
+#define ARM_CA57_CPUMERRSR_RAM_ID GENMASK(30, 24)
+#define ARM_CA57_L1_I_TAG_RAM 0x00
+#define ARM_CA57_L1_I_DATA_RAM 0x01
+#define ARM_CA57_L1_D_TAG_RAM 0x08
+#define ARM_CA57_L1_D_DATA_RAM 0x09
+#define ARM_CA57_L2_TLB_RAM 0x18
+#define ARM_CA57_CPUMERRSR_VALID BIT(31)
+#define ARM_CA57_CPUMERRSR_REPEAT GENMASK_ULL(39, 32)
+#define ARM_CA57_CPUMERRSR_OTHER GENMASK_ULL(47, 40)
+#define ARM_CA57_CPUMERRSR_FATAL BIT_ULL(63)
+
+#define AL_L1_EDAC_MSG_MAX 256
+
+static void al_l1_edac_cpumerrsr(void *arg)
+{
+ struct edac_device_ctl_info *edac_dev = arg;
+ int cpu, i;
+ u32 ramid, repeat, other, fatal;
+ u64 val = read_sysreg_s(ARM_CA57_CPUMERRSR_EL1);
+ char msg[AL_L1_EDAC_MSG_MAX];
+ int space, count;
+ char *p;
+
+ if (!(FIELD_GET(ARM_CA57_CPUMERRSR_VALID, val)))
+ return;
+
+ write_sysreg_s(0, ARM_CA57_CPUMERRSR_EL1);
+
+ cpu = smp_processor_id();
+ ramid = FIELD_GET(ARM_CA57_CPUMERRSR_RAM_ID, val);
+ repeat = FIELD_GET(ARM_CA57_CPUMERRSR_REPEAT, val);
+ other = FIELD_GET(ARM_CA57_CPUMERRSR_OTHER, val);
+ fatal = FIELD_GET(ARM_CA57_CPUMERRSR_FATAL, val);
+
+ space = sizeof(msg);
+ p = msg;
+ count = scnprintf(p, space, "CPU%d L1 %serror detected", cpu,
+ (fatal) ? "Fatal " : "");
+ p += count;
+ space -= count;
+
+ switch (ramid) {
+ case ARM_CA57_L1_I_TAG_RAM:
+ count = scnprintf(p, space, " RAMID='L1-I Tag RAM'");
+ break;
+ case ARM_CA57_L1_I_DATA_RAM:
+ count = scnprintf(p, space, " RAMID='L1-I Data RAM'");
+ break;
+ case ARM_CA57_L1_D_TAG_RAM:
+ count = scnprintf(p, space, " RAMID='L1-D Tag RAM'");
+ break;
+ case ARM_CA57_L1_D_DATA_RAM:
+ count = scnprintf(p, space, " RAMID='L1-D Data RAM'");
+ break;
+ case ARM_CA57_L2_TLB_RAM:
+ count = scnprintf(p, space, " RAMID='L2 TLB RAM'");
+ break;
+ default:
+ count = scnprintf(p, space, " RAMID='unknown'");
+ break;
+ }
+
+ p += count;
+ space -= count;
+ count = scnprintf(p, space,
+ " repeat=%d, other=%d (CPUMERRSR_EL1=0x%llx)",
+ repeat, other, val);
+
+ for (i = 0; i < repeat; i++) {
+ if (fatal)
+ edac_device_handle_ue(edac_dev, 0, 0, msg);
+ else
+ edac_device_handle_ce(edac_dev, 0, 0, msg);
+ }
+}
+
+static void al_l1_edac_check(struct edac_device_ctl_info *edac_dev)
+{
+ on_each_cpu(al_l1_edac_cpumerrsr, edac_dev, 1);
+}
+
+static int al_l1_edac_probe(struct platform_device *pdev)
+{
+ struct edac_device_ctl_info *edac_dev;
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ edac_dev = edac_device_alloc_ctl_info(0, (char *)dev_name(dev), 1, "L",
+ 1, 1, NULL, 0,
+ edac_device_alloc_index());
+ if (IS_ERR_OR_NULL(edac_dev))
+ return -ENOMEM;
+
+ edac_dev->edac_check = al_l1_edac_check;
+ edac_dev->dev = dev;
+ edac_dev->mod_name = DRV_NAME;
+ edac_dev->dev_name = dev_name(dev);
+ edac_dev->ctl_name = "L1 cache";
+ platform_set_drvdata(pdev, edac_dev);
+
+ ret = edac_device_add_device(edac_dev);
+ if (ret) {
+ dev_err(dev, "Failed to add L1 edac device\n");
+ goto err;
+ }
+
+ return 0;
+err:
+ edac_device_free_ctl_info(edac_dev);
+
+ return ret;
+}
+
+static int al_l1_edac_remove(struct platform_device *pdev)
+{
+ struct edac_device_ctl_info *edac_dev = platform_get_drvdata(pdev);
+
+ edac_device_del_device(edac_dev->dev);
+ edac_device_free_ctl_info(edac_dev);
+
+ return 0;
+}
+
+static const struct of_device_id al_l1_edac_of_match[] = {
+ { .compatible = "amazon,al-l1-edac" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, al_l1_edac_of_match);
+
+static struct platform_driver al_l1_edac_driver = {
+ .probe = al_l1_edac_probe,
+ .remove = al_l1_edac_remove,
+ .driver = {
+ .name = DRV_NAME,
+ .of_match_table = al_l1_edac_of_match,
+ },
+};
+module_platform_driver(al_l1_edac_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Hanna Hawa <hhhawa@amazon.com>");
+MODULE_DESCRIPTION("Amazon's Annapurna Lab's L1 EDAC Driver");
--
2.17.1
^ permalink raw reply related
* [PATCH v5 1/4] dt-bindings: EDAC: Add Amazon's Annapurna Labs L1 EDAC
From: Hanna Hawa @ 2019-08-05 14:39 UTC (permalink / raw)
To: robh+dt, mark.rutland, bp, mchehab, james.morse, davem, gregkh,
linus.walleij, Jonathan.Cameron, nicolas.ferre, paulmck
Cc: dwmw, benh, ronenk, talel, jonnyc, hanochu, devicetree,
linux-kernel, linux-edac, hhhawa
In-Reply-To: <20190805143911.12185-1-hhhawa@amazon.com>
Document Amazon's Annapurna Labs L1 EDAC SoC binding.
Signed-off-by: Hanna Hawa <hhhawa@amazon.com>
---
.../devicetree/bindings/edac/amazon,al-l1-edac.txt | 14 ++++++++++++++
1 file changed, 14 insertions(+)
create mode 100644 Documentation/devicetree/bindings/edac/amazon,al-l1-edac.txt
diff --git a/Documentation/devicetree/bindings/edac/amazon,al-l1-edac.txt b/Documentation/devicetree/bindings/edac/amazon,al-l1-edac.txt
new file mode 100644
index 000000000000..2ae8370216bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/edac/amazon,al-l1-edac.txt
@@ -0,0 +1,14 @@
+* Amazon's Annapurna Labs L1 EDAC
+
+Amazon's Annapurna Labs SoCs supports L1 single bit correction and
+two bits detection capability based on ARM implementation.
+
+Required properties:
+- compatible:
+ should be "amazon,al-l1-edac".
+
+Example:
+
+ al_l1_edac {
+ compatible = "amazon,al-l1-edac";
+ };
--
2.17.1
^ permalink raw reply related
* [PATCH v5 0/4] Add support for Amazon's Annapurna Labs EDAC for L1/L2
From: Hanna Hawa @ 2019-08-05 14:39 UTC (permalink / raw)
To: robh+dt, mark.rutland, bp, mchehab, james.morse, davem, gregkh,
linus.walleij, Jonathan.Cameron, nicolas.ferre, paulmck
Cc: dwmw, benh, ronenk, talel, jonnyc, hanochu, devicetree,
linux-kernel, linux-edac, hhhawa
This series adds L1 and L2 caches support for error detection and
correction for Amazon's Annapurna Labs SoCs.
Alpine SoCs supports L1 and L2 single bit correction and two bits detection
capability based on ARM implementation.
Changes since v4:
-----------------
- Added include for cpumask.h in al_l2_edac.c
- Fix RAMID error print according to ARM TRM
- Use for_each_possible_cpu() to parse information for DT.
- Add missing of_node_put() call.
Changes since v3:
-----------------
- Added include for smp.h sysreg.h
- Use scnprintf instead of snprintf
- Move write_sysreg_s after valid check to minimize the window between
read/write.
- Use IS_ERR_OR_NULL instead of IS_ERR, because
edac_device_alloc_ctl_info may return NULL.
Changes since v2:
-----------------
- Use BIT for single bit instead of GENMASK
- Use BIT_ULL and GENMASK_ULL for 64bit vector
- Fix the mod_name/ctrl_name.
Changes since v1:
-----------------
- Split into two drivers
- Get cpu-mask according to l2-cache handler from devicetree
- Remove parameter casting
- Use GENMASK() in bit mask
- Use FIELD_GET()
- Update define description PLRU_RAM -> PF_RAM
- Use sys_reg() and read_sysreg_s()
- Remove all write/read wrappers
- Check fatal field to set if the error correctable or not
- Remove un-relevant information from error prints.
- Update smp_call_function_single() call function to wait
- remove usage of get_online_cpus/put_online_cpus
- Use on_each_cpu() and smp_call_function_any() instead of loop with for_each_cpu.
- use buffer for error prints and pass to edac API
- Remove edac_op_state set
- Add for loop to report on repeated errors of the same type
- Fix error name of the TLB to be L2_TLB as written in ARM TRM
- Minor change in Kconfig
- Minor changes in commit message
Hanna Hawa (4):
dt-bindings: EDAC: Add Amazon's Annapurna Labs L1 EDAC
edac: Add support for Amazon's Annapurna Labs L1 EDAC
dt-bindings: EDAC: Add Amazon's Annapurna Labs L2 EDAC
edac: Add support for Amazon's Annapurna Labs L2 EDAC
.../bindings/edac/amazon,al-l1-edac.txt | 14 ++
.../bindings/edac/amazon,al-l2-edac.txt | 20 ++
MAINTAINERS | 12 ++
drivers/edac/Kconfig | 16 ++
drivers/edac/Makefile | 2 +
drivers/edac/al_l1_edac.c | 158 ++++++++++++++
drivers/edac/al_l2_edac.c | 192 ++++++++++++++++++
7 files changed, 414 insertions(+)
create mode 100644 Documentation/devicetree/bindings/edac/amazon,al-l1-edac.txt
create mode 100644 Documentation/devicetree/bindings/edac/amazon,al-l2-edac.txt
create mode 100644 drivers/edac/al_l1_edac.c
create mode 100644 drivers/edac/al_l2_edac.c
--
2.17.1
^ permalink raw reply
* Re: [RFC PATCH 1/2] dt-bindings: net: macb: Add new property for PS SGMII only
From: Harini Katakam @ 2019-08-05 14:36 UTC (permalink / raw)
To: Andrew Lunn
Cc: Harini Katakam, Nicolas Ferre, David Miller, Claudiu Beznea,
Rob Herring, Mark Rutland, netdev, linux-kernel, Michal Simek,
devicetree
In-Reply-To: <20190805132045.GC24275@lunn.ch>
Hi Andrew,
On Mon, Aug 5, 2019 at 7:00 PM Andrew Lunn <andrew@lunn.ch> wrote:
>
> On Mon, Aug 05, 2019 at 11:45:05AM +0530, Harini Katakam wrote:
> > Hi Andrew,
> >
> > On Sun, Aug 4, 2019 at 8:26 PM Andrew Lunn <andrew@lunn.ch> wrote:
> > >
> > > On Wed, Jul 31, 2019 at 03:10:32PM +0530, Harini Katakam wrote:
> > > > Add a new property to indicate when PS SGMII is used with NO
> > > > external PHY on board.
> > >
> > > Hi Harini
> > >
> > > What exactly is you use case? Are you connecting to a Ethernet switch?
> > > To an SFP cage with a copper module?
> >
> > Yes, an SFP cage is the common HW target for this patch.
>
> Hi Harini
>
> So you have a copper PHY in the SFP cage. It will talk SGMII
> signalling to your PS SGMII. When that signalling is complete i would
> expect the MAC to raise an interrupt, just as if the SGMII PHY was
> soldered on the board. So i don't see why you need this polling?
>
Thanks. Sorry, I overlooked this interrupt. Let me try that.
Regards,
Harini
^ permalink raw reply
* Re: [PATCH 16/16] dt-bindings: net: add bindings for ADIN PHY driver
From: Andrew Lunn @ 2019-08-05 14:27 UTC (permalink / raw)
To: Alexandru Ardelean
Cc: netdev, devicetree, linux-kernel, davem, robh+dt, mark.rutland,
f.fainelli, hkallweit1
In-Reply-To: <20190805165453.3989-17-alexandru.ardelean@analog.com>
On Mon, Aug 05, 2019 at 07:54:53PM +0300, Alexandru Ardelean wrote:
> This change adds bindings for the Analog Devices ADIN PHY driver, detailing
> all the properties implemented by the driver.
>
> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
> ---
> .../devicetree/bindings/net/adi,adin.yaml | 93 +++++++++++++++++++
> MAINTAINERS | 2 +
> include/dt-bindings/net/adin.h | 26 ++++++
> 3 files changed, 121 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/adi,adin.yaml
> create mode 100644 include/dt-bindings/net/adin.h
>
> diff --git a/Documentation/devicetree/bindings/net/adi,adin.yaml b/Documentation/devicetree/bindings/net/adi,adin.yaml
> new file mode 100644
> index 000000000000..fcf884bb86f7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/adi,adin.yaml
> @@ -0,0 +1,93 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/adi,adin.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Analog Devices ADIN1200/ADIN1300 PHY
> +
> +maintainers:
> + - Alexandru Ardelean <alexandru.ardelean@analog.com>
> +
> +description: |
> + Bindings for Analog Devices Industrial Ethernet PHYs
> +
> +properties:
> + compatible:
> + description: |
> + Compatible list, may contain "ethernet-phy-ieee802.3-c45" in which case
> + Clause 45 will be used to access device management registers. If
> + unspecified, Clause 22 will be used. Use this only when MDIO supports
> + Clause 45 access, but there is no other way to determine this.
> + enum:
> + - ethernet-phy-ieee802.3-c45
It is valid to list ethernet-phy-ieee802.3-c22, it is just not
required. So maybe you should list it here to keep the DT validater happy?
Andrew
^ permalink raw reply
* Re: [PATCH 04/16] net: phy: adin: add {write,read}_mmd hooks
From: Andrew Lunn @ 2019-08-05 14:25 UTC (permalink / raw)
To: Alexandru Ardelean
Cc: netdev, devicetree, linux-kernel, davem, robh+dt, mark.rutland,
f.fainelli, hkallweit1
In-Reply-To: <20190805165453.3989-5-alexandru.ardelean@analog.com>
> diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
> index b75c723bda79..3dd9fe50f4c8 100644
> --- a/drivers/net/phy/adin.c
> +++ b/drivers/net/phy/adin.c
> @@ -14,6 +14,9 @@
> #define PHY_ID_ADIN1200 0x0283bc20
> #define PHY_ID_ADIN1300 0x0283bc30
>
> +#define ADIN1300_MII_EXT_REG_PTR 0x10
> +#define ADIN1300_MII_EXT_REG_DATA 0x11
> +
> #define ADIN1300_INT_MASK_REG 0x0018
Please be consistent with registers. Either use 4 digits, or 2 digits.
Andrew
^ permalink raw reply
* Re: [PATCH 2/2] dt-bindings: iio: imu: st_lsm6dsx: add ism330dhcx device bindings
From: Jonathan Cameron @ 2019-08-05 14:24 UTC (permalink / raw)
To: Lorenzo Bianconi; +Cc: lorenzo.bianconi, linux-iio, devicetree
In-Reply-To: <0a970fdcd934c940be1af82ecf1fe2a746abcd2a.1564999807.git.lorenzo@kernel.org>
On Mon, 5 Aug 2019 12:18:44 +0200
Lorenzo Bianconi <lorenzo@kernel.org> wrote:
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Applied,
Thanks,
Jonathan
> ---
> Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt b/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt
> index 92b48f242356..87407d110bb7 100644
> --- a/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt
> +++ b/Documentation/devicetree/bindings/iio/imu/st_lsm6dsx.txt
> @@ -12,6 +12,7 @@ Required properties:
> "st,lsm6dsox"
> "st,lsm6dsr"
> "st,lsm6ds3tr-c"
> + "st,ism330dhcx"
> - reg: i2c address of the sensor / spi cs line
>
> Optional properties:
^ permalink raw reply
* Re: [PATCH 1/2] iio: imu: st_lsm6dsx: add support to ISM330DHCX
From: Jonathan Cameron @ 2019-08-05 14:23 UTC (permalink / raw)
To: Lorenzo Bianconi; +Cc: lorenzo.bianconi, linux-iio, devicetree
In-Reply-To: <a3391b8b4734c483286f1352520dd1d6f8b96d4e.1564999807.git.lorenzo@kernel.org>
On Mon, 5 Aug 2019 12:18:43 +0200
Lorenzo Bianconi <lorenzo@kernel.org> wrote:
> Add support to STM ISM330DHCX 6-axis (acc + gyro) Mems sensor
> https://www.st.com/resource/en/datasheet/ism330dhcx.pdf
>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Given these are exceptionally straight forward and I'm
hoovering up the outstanding patches on this driver today,
I'll be cheeky and not let them sit on the mailing list
before applying.
Applied to the togreg branch of iio.git and pushed out as testing
for the autobuilders to do their usual sanity check.
Thanks,
Jonathan
> ---
> drivers/iio/imu/st_lsm6dsx/Kconfig | 3 ++-
> drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h | 2 ++
> drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c | 7 ++++---
> drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c | 5 ++++-
> drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c | 5 +++++
> drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c | 5 +++++
> 6 files changed, 22 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/iio/imu/st_lsm6dsx/Kconfig b/drivers/iio/imu/st_lsm6dsx/Kconfig
> index 6cbf65a7e11e..939058b27746 100644
> --- a/drivers/iio/imu/st_lsm6dsx/Kconfig
> +++ b/drivers/iio/imu/st_lsm6dsx/Kconfig
> @@ -11,7 +11,8 @@ config IIO_ST_LSM6DSX
> help
> Say yes here to build support for STMicroelectronics LSM6DSx imu
> sensor. Supported devices: lsm6ds3, lsm6ds3h, lsm6dsl, lsm6dsm,
> - ism330dlc, lsm6dso, lsm6dsox, asm330lhh, lsm6dsr, lsm6ds3tr-c
> + ism330dlc, lsm6dso, lsm6dsox, asm330lhh, lsm6dsr, lsm6ds3tr-c,
> + ism330dhcx
>
> To compile this driver as a module, choose M here: the module
> will be called st_lsm6dsx.
> diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h
> index 5090f1b3525a..4d47ba36de84 100644
> --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h
> +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h
> @@ -23,6 +23,7 @@
> #define ST_LSM6DSOX_DEV_NAME "lsm6dsox"
> #define ST_LSM6DSR_DEV_NAME "lsm6dsr"
> #define ST_LSM6DS3TRC_DEV_NAME "lsm6ds3tr-c"
> +#define ST_ISM330DHCX_DEV_NAME "ism330dhcx"
>
> enum st_lsm6dsx_hw_id {
> ST_LSM6DS3_ID,
> @@ -35,6 +36,7 @@ enum st_lsm6dsx_hw_id {
> ST_LSM6DSOX_ID,
> ST_LSM6DSR_ID,
> ST_LSM6DS3TRC_ID,
> + ST_ISM330DHCX_ID,
> ST_LSM6DSX_MAX_ID,
> };
>
> diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c
> index 1be1cec2ab23..2c03a5b80f80 100644
> --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c
> +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_buffer.c
> @@ -14,9 +14,10 @@
> * (e.g. Gx, Gy, Gz, Ax, Ay, Az), then data are repeated depending on the
> * value of the decimation factor and ODR set for each FIFO data set.
> *
> - * LSM6DSO/LSM6DSOX/ASM330LHH/LSM6DSR: The FIFO buffer can be configured to
> - * store data from gyroscope and accelerometer. Each sample is queued with
> - * a tag (1B) indicating data source (gyroscope, accelerometer, hw timer).
> + * LSM6DSO/LSM6DSOX/ASM330LHH/LSM6DSR/ISM330DHCX: The FIFO buffer can be
> + * configured to store data from gyroscope and accelerometer. Each sample
> + * is queued with a tag (1B) indicating data source (gyroscope, accelerometer,
> + * hw timer).
> *
> * FIFO supported modes:
> * - BYPASS: FIFO disabled
> diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
> index fc4d18b58c97..85824d6739ee 100644
> --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
> +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_core.c
> @@ -24,7 +24,7 @@
> * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000
> * - FIFO size: 4KB
> *
> - * - LSM6DSO/LSM6DSOX/ASM330LHH/LSM6DSR
> + * - LSM6DSO/LSM6DSOX/ASM330LHH/LSM6DSR/ISM330DHCX:
> * - Accelerometer/Gyroscope supported ODR [Hz]: 13, 26, 52, 104, 208, 416
> * - Accelerometer supported full-scale [g]: +-2/+-4/+-8/+-16
> * - Gyroscope supported full-scale [dps]: +-125/+-245/+-500/+-1000/+-2000
> @@ -645,6 +645,9 @@ static const struct st_lsm6dsx_settings st_lsm6dsx_sensor_settings[] = {
> {
> .hw_id = ST_LSM6DSR_ID,
> .name = ST_LSM6DSR_DEV_NAME,
> + }, {
> + .hw_id = ST_ISM330DHCX_ID,
> + .name = ST_ISM330DHCX_DEV_NAME,
> },
> },
> .channels = {
> diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c
> index 28581eb0532c..15c6aa5b6caa 100644
> --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c
> +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_i2c.c
> @@ -79,6 +79,10 @@ static const struct of_device_id st_lsm6dsx_i2c_of_match[] = {
> .compatible = "st,lsm6ds3tr-c",
> .data = (void *)ST_LSM6DS3TRC_ID,
> },
> + {
> + .compatible = "st,ism330dhcx",
> + .data = (void *)ST_ISM330DHCX_ID,
> + },
> {},
> };
> MODULE_DEVICE_TABLE(of, st_lsm6dsx_i2c_of_match);
> @@ -94,6 +98,7 @@ static const struct i2c_device_id st_lsm6dsx_i2c_id_table[] = {
> { ST_LSM6DSOX_DEV_NAME, ST_LSM6DSOX_ID },
> { ST_LSM6DSR_DEV_NAME, ST_LSM6DSR_ID },
> { ST_LSM6DS3TRC_DEV_NAME, ST_LSM6DS3TRC_ID },
> + { ST_ISM330DHCX_DEV_NAME, ST_ISM330DHCX_ID },
> {},
> };
> MODULE_DEVICE_TABLE(i2c, st_lsm6dsx_i2c_id_table);
> diff --git a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c
> index 0371e8b94a3e..a8430ee11310 100644
> --- a/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c
> +++ b/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx_spi.c
> @@ -79,6 +79,10 @@ static const struct of_device_id st_lsm6dsx_spi_of_match[] = {
> .compatible = "st,lsm6ds3tr-c",
> .data = (void *)ST_LSM6DS3TRC_ID,
> },
> + {
> + .compatible = "st,ism330dhcx",
> + .data = (void *)ST_ISM330DHCX_ID,
> + },
> {},
> };
> MODULE_DEVICE_TABLE(of, st_lsm6dsx_spi_of_match);
> @@ -94,6 +98,7 @@ static const struct spi_device_id st_lsm6dsx_spi_id_table[] = {
> { ST_LSM6DSOX_DEV_NAME, ST_LSM6DSOX_ID },
> { ST_LSM6DSR_DEV_NAME, ST_LSM6DSR_ID },
> { ST_LSM6DS3TRC_DEV_NAME, ST_LSM6DS3TRC_ID },
> + { ST_ISM330DHCX_DEV_NAME, ST_ISM330DHCX_ID },
> {},
> };
> MODULE_DEVICE_TABLE(spi, st_lsm6dsx_spi_id_table);
^ permalink raw reply
* Re: [PATCH 03/16] net: phy: adin: add support for interrupts
From: Andrew Lunn @ 2019-08-05 14:21 UTC (permalink / raw)
To: Alexandru Ardelean
Cc: netdev, devicetree, linux-kernel, davem, robh+dt, mark.rutland,
f.fainelli, hkallweit1
In-Reply-To: <20190805165453.3989-4-alexandru.ardelean@analog.com>
On Mon, Aug 05, 2019 at 07:54:40PM +0300, Alexandru Ardelean wrote:
> This change adds support for enabling PHY interrupts that can be used by
> the PHY framework to get signal for link/speed/auto-negotiation changes.
>
> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
> ---
> drivers/net/phy/adin.c | 44 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
> index c100a0dd95cd..b75c723bda79 100644
> --- a/drivers/net/phy/adin.c
> +++ b/drivers/net/phy/adin.c
> @@ -14,6 +14,22 @@
> #define PHY_ID_ADIN1200 0x0283bc20
> #define PHY_ID_ADIN1300 0x0283bc30
>
> +#define ADIN1300_INT_MASK_REG 0x0018
> +#define ADIN1300_INT_MDIO_SYNC_EN BIT(9)
> +#define ADIN1300_INT_ANEG_STAT_CHNG_EN BIT(8)
> +#define ADIN1300_INT_ANEG_PAGE_RX_EN BIT(6)
> +#define ADIN1300_INT_IDLE_ERR_CNT_EN BIT(5)
> +#define ADIN1300_INT_MAC_FIFO_OU_EN BIT(4)
> +#define ADIN1300_INT_RX_STAT_CHNG_EN BIT(3)
> +#define ADIN1300_INT_LINK_STAT_CHNG_EN BIT(2)
> +#define ADIN1300_INT_SPEED_CHNG_EN BIT(1)
> +#define ADIN1300_INT_HW_IRQ_EN BIT(0)
> +#define ADIN1300_INT_MASK_EN \
> + (ADIN1300_INT_ANEG_STAT_CHNG_EN | ADIN1300_INT_ANEG_PAGE_RX_EN | \
> + ADIN1300_INT_LINK_STAT_CHNG_EN | ADIN1300_INT_SPEED_CHNG_EN | \
> + ADIN1300_INT_HW_IRQ_EN)
> +#define ADIN1300_INT_STATUS_REG 0x0019
> +
> static int adin_config_init(struct phy_device *phydev)
> {
> int rc;
> @@ -25,15 +41,40 @@ static int adin_config_init(struct phy_device *phydev)
> return 0;
> }
>
> +static int adin_phy_ack_intr(struct phy_device *phydev)
> +{
> + int ret;
> +
> + /* Clear pending interrupts. */
> + ret = phy_read(phydev, ADIN1300_INT_STATUS_REG);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
Please go through the whole driver and throw out all the needless
if (ret < 0)
return ret;
return 0;
Thanks
Andrew
^ permalink raw reply
* Re: [PATCH 02/16] net: phy: adin: hook genphy_{suspend,resume} into the driver
From: Andrew Lunn @ 2019-08-05 14:17 UTC (permalink / raw)
To: Alexandru Ardelean
Cc: netdev, devicetree, linux-kernel, davem, robh+dt, mark.rutland,
f.fainelli, hkallweit1
In-Reply-To: <20190805165453.3989-3-alexandru.ardelean@analog.com>
On Mon, Aug 05, 2019 at 07:54:39PM +0300, Alexandru Ardelean wrote:
> The chip supports standard suspend/resume via BMCR reg.
> Hook these functions into the `adin` driver.
>
> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply
* Re: [PATCH 01/16] net: phy: adin: add support for Analog Devices PHYs
From: Andrew Lunn @ 2019-08-05 14:16 UTC (permalink / raw)
To: Alexandru Ardelean
Cc: netdev, devicetree, linux-kernel, davem, robh+dt, mark.rutland,
f.fainelli, hkallweit1
In-Reply-To: <20190805165453.3989-2-alexandru.ardelean@analog.com>
> +static int adin_config_init(struct phy_device *phydev)
> +{
> + int rc;
> +
> + rc = genphy_config_init(phydev);
> + if (rc < 0)
> + return rc;
> +
> + return 0;
> +}
Why not just
return genphy_config_init(phydev);
Andrew
^ permalink raw reply
* Re: [PATCH 16/16] dt-bindings: net: add bindings for ADIN PHY driver
From: Andrew Lunn @ 2019-08-05 14:11 UTC (permalink / raw)
To: Alexandru Ardelean
Cc: netdev, devicetree, linux-kernel, davem, robh+dt, mark.rutland,
f.fainelli, hkallweit1
In-Reply-To: <20190805165453.3989-17-alexandru.ardelean@analog.com>
> + adi,rx-internal-delay:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + RGMII RX Clock Delay used only when PHY operates in RGMII mode (phy-mode
> + is "rgmii-id", "rgmii-rxid", "rgmii-txid") see `dt-bindings/net/adin.h`
> + default value is 0 (which represents 2 ns)
> + enum: [ 0, 1, 2, 6, 7 ]
We want these numbers to be in ns. So the default value would actually
be 2. The driver needs to convert the number in DT to a value to poke
into a PHY register. Please rename the property adi,rx-internal-delay-ns.
> +
> + adi,tx-internal-delay:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + RGMII TX Clock Delay used only when PHY operates in RGMII mode (phy-mode
> + is "rgmii-id", "rgmii-rxid", "rgmii-txid") see `dt-bindings/net/adin.h`
> + default value is 0 (which represents 2 ns)
> + enum: [ 0, 1, 2, 6, 7 ]
Same here.
> +
> + adi,fifo-depth:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description: |
> + When operating in RMII mode, this option configures the FIFO depth.
> + See `dt-bindings/net/adin.h`.
> + enum: [ 0, 1, 2, 3, 4, 5 ]
Units? You should probably rename this adi,fifo-depth-bits and list
the valid values in bits.
> +
> + adi,eee-enabled:
> + description: |
> + Advertise EEE capabilities on power-up/init (default disabled)
> + type: boolean
It is not the PHY which decides this. The MAC indicates if it is EEE
capable to phylib. phylib looks into the PHY registers to determine if
the PHY supports EEE. phylib will then enable EEE
advertisement. Please remove this, and ensure EEE is disabled by
default.
Andrew
^ permalink raw reply
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