* Re: [PATCH] dt-bindings: net: meson-dwmac: convert to yaml
From: Rob Herring @ 2019-08-05 22:09 UTC (permalink / raw)
To: Neil Armstrong
Cc: Martin Blumenstingl, devicetree, netdev, linux-amlogic,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
linux-kernel@vger.kernel.org
In-Reply-To: <20190805122558.5130-1-narmstrong@baylibre.com>
On Mon, Aug 5, 2019 at 6:26 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> Now that we have the DT validation in place, let's convert the device tree
> bindings for the Synopsys DWMAC Glue for Amlogic SoCs over to a YAML schemas.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> Rob,
>
> I keep getting :
> .../devicetree/bindings/net/amlogic,meson-dwmac.example.dt.yaml: ethernet@c9410000: reg: [[3376480256, 65536], [3364046144, 8]] is too long
Because snps,dwmac.yaml has:
reg:
maxItems: 1
The schemas are applied separately and all have to be valid. You'll
need to change snps,dwmac.yaml to:
reg:
minItems: 1
maxItems: 2
The schema error messages leave something to be desired. I wish the
error messages said which schema is throwing the error.
> for the example DT
>
> and for the board DT :
> ../amlogic/meson-gxl-s905x-libretech-cc.dt.yaml: ethernet@c9410000: reg: [[0, 3376480256, 0, 65536, 0, 3364046144, 0, 4]] is too short
> ../amlogic/meson-gxl-s905x-nexbox-a95x.dt.yaml: soc: ethernet@c9410000:reg:0: [0, 3376480256, 0, 65536, 0, 3364046144, 0, 4] is too long
>
> and I don't know how to get rid of it.
The first issue is the same as the above. The 2nd issue is the use of
<> in dts files becomes stricter with the schema. Each entry in an
array needs to be bracketed:
reg = <0x0 0xc9410000 0x0 0x10000>,
<0x0 0xc8834540 0x0 0x4>;
Rob
^ permalink raw reply
* Re: [RFCv2 0/9] dt-bindings: first tentative of conversion to yaml format
From: Rob Herring @ 2019-08-05 21:51 UTC (permalink / raw)
To: Neil Armstrong
Cc: Philipp Zabel, devicetree, LINUX-WATCHDOG, Jassi Brar, linux-spi,
open list:HARDWARE RANDOM NUMBER GENERATOR CORE,
open list:SERIAL DRIVERS, linux-amlogic, Kishon Vijay Abraham I,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <20190805120320.32282-1-narmstrong@baylibre.com>
On Mon, Aug 5, 2019 at 6:03 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> This is a first tentative to convert some of the simplest Amlogic
> dt-bindings to the yaml format.
>
> All have been tested using :
> $ make ARCH=arm64 dtbs_check
>
> Issues with the amlogic arm64 DTs has already been identified thanks
> to the validation scripts. The DT fixes will be pushed once these yaml
> bindings are acked.
>
> Changes since rfc v1:
> - Fixed bindings according to Rob's comments
> - Added commit log
> - renamed yaml files using amlogic prefix
>
> Neil Armstrong (9):
> dt-bindings: mailbox: meson-mhu: convert to yaml
> dt-bindings: rng: amlogic,meson-rng: convert to yaml
> dt-bindings: spi: meson: convert to yaml
> dt-bindings: reset: amlogic,meson-reset: convert to yaml
> dt-bindings: arm: amlogic: amlogic,meson-gx-ao-secure: convert to yaml
> dt-bindings: phy: meson-g12a-usb2-phy: convert to yaml
> dt-bindings: phy: meson-g12a-usb3-pcie-phy: convert to yaml
> dt-bindings: serial: meson-uart: convert to yaml
> dt-bindings: watchdog: meson-gxbb-wdt: convert to yaml
For the series,
Reviewed-by: Rob Herring <robh@kernel.org>
What's your merge plan? Do you want me to take the whole series?
Rob
^ permalink raw reply
* Re: [PATCH 2/6] dt-bindings: arm: amlogic: add bindings for G12B based S922X SoC
From: Kevin Hilman @ 2019-08-05 21:46 UTC (permalink / raw)
To: devicetree
Cc: Neil Armstrong, linux-amlogic, linux-arm-kernel, linux-kernel,
christianshewitt
In-Reply-To: <20190731124000.22072-3-narmstrong@baylibre.com>
Neil Armstrong <narmstrong@baylibre.com> writes:
> Add a specific compatible for the Amlogic G12B family based S922X SoC
> to differentiate with the A311D SoC from the same family.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> Documentation/devicetree/bindings/arm/amlogic.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml
> index 325c6fd3566d..3c3bc806cd23 100644
> --- a/Documentation/devicetree/bindings/arm/amlogic.yaml
> +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml
> @@ -139,6 +139,7 @@ properties:
> items:
> - enum:
> - hardkernel,odroid-n2
> + - const: amlogic,s922x
> - const: amlogic,g12b
nit: in previous binding docs, we were trying to keep these sorted
alphabetically. I'll reorder the new "s922x" after "g12b" when
applying.
Thanks,
Kevin
^ permalink raw reply
* Re: [RFCv2 3/9] dt-bindings: spi: meson: convert to yaml
From: Rob Herring @ 2019-08-05 21:45 UTC (permalink / raw)
To: Neil Armstrong
Cc: linux-amlogic, devicetree,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
linux-spi
In-Reply-To: <20190805120320.32282-4-narmstrong@baylibre.com>
On Mon, Aug 5, 2019 at 6:03 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> Now that we have the DT validation in place, let's convert the device tree
> bindings for the Amlogic SPI controllers over to two separate YAML schemas.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> .../bindings/spi/amlogic,meson-gx-spicc.yaml | 67 +++++++++++++++++++
> .../bindings/spi/amlogic,meson6-spifc.yaml | 53 +++++++++++++++
> .../devicetree/bindings/spi/spi-meson.txt | 55 ---------------
> 3 files changed, 120 insertions(+), 55 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml
> create mode 100644 Documentation/devicetree/bindings/spi/amlogic,meson6-spifc.yaml
> delete mode 100644 Documentation/devicetree/bindings/spi/spi-meson.txt
>
> diff --git a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml
> new file mode 100644
> index 000000000000..49b617c98ae7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml
> @@ -0,0 +1,67 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright 2019 BayLibre, SAS
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/spi/amlogic,meson-gx-spicc.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Amlogic Meson SPI Communication Controller
> +
> +maintainers:
> + - Neil Armstrong <narmstrong@baylibre.com>
> +
> +allOf:
> + - $ref: "spi-controller.yaml#"
> +
> +description: |
> + The Meson SPICC is a generic SPI controller for general purpose Full-Duplex
> + communications with dedicated 16 words RX/TX PIO FIFOs.
> +
> +properties:
> + compatible:
> + enum:
> + - amlogic,meson-gx-spicc # SPICC controller on Amlogic GX and compatible SoCs
> + - amlogic,meson-axg-spicc # SPICC controller on Amlogic AXG and compatible SoCs
> +
> + interrupts:
> + maxItems: 1
> +
> + reg:
> + maxItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + description: input clock for the baud rate generator
> + items:
> + - const: core
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> +
> +examples:
> + - |
> + spi@c1108d80 {
> + compatible = "amlogic,meson-gx-spicc";
> + reg = <0xc1108d80 0x80>;
> + interrupts = <112>;
> + clocks = <&clk81>;
> + clock-names = "core";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethernet-switch@0 {
> + compatible = "micrel,ks8995m";
> + spi-max-frequency = <1000000>;
> + reg = <0>;
> + };
> + };
> +
> diff --git a/Documentation/devicetree/bindings/spi/amlogic,meson6-spifc.yaml b/Documentation/devicetree/bindings/spi/amlogic,meson6-spifc.yaml
> new file mode 100644
> index 000000000000..67dcedc81a5e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/amlogic,meson6-spifc.yaml
> @@ -0,0 +1,53 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright 2019 BayLibre, SAS
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/spi/amlogic,meson6-spifc.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Amlogic Meson SPI Flash Controller
> +
> +maintainers:
> + - Neil Armstrong <narmstrong@baylibre.com>
> +
> +allOf:
> + - $ref: "spi-controller.yaml#"
> +
> +description: |
> + The Meson SPIFC is a controller optimized for communication with SPI
> + NOR memories, without DMA support and a 64-byte unified transmit /
> + receive buffer.
> +
> +properties:
> + compatible:
> + enum:
> + - amlogic,meson6-spifc # SPI Flash Controller on Meson6 and compatible SoCs
> + - amlogic,meson-gxbb-spifc # SPI Flash Controller on GXBB and compatible SoCs
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> +
> +examples:
> + - |
> + spi@c1108c80 {
> + compatible = "amlogic,meson6-spifc";
> + reg = <0xc1108c80 0x80>;
> + clocks = <&clk81>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + flash: m25p80@0 {
flash@0
I need to write a schema for this or I'll never stop giving this comment...
Otherwise,
Reviewed-by: Rob Herring <robh@kernel.org>
> + compatible = "spansion,m25p80", "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <40000000>;
> + };
> + };
> +
^ permalink raw reply
* Re: [PATCH v2 0/4] Rework secure-monitor driver
From: Kevin Hilman @ 2019-08-05 21:34 UTC (permalink / raw)
To: srinivas.kandagatla
Cc: devicetree, narmstrong, Carlo Caione, robh+dt, linux-amlogic,
tglx, linux-arm-kernel, jbrunet
In-Reply-To: <20190731082339.20163-1-ccaione@baylibre.com>
Srinivas,
Carlo Caione <ccaione@baylibre.com> writes:
> The secure-monitor driver is currently in really bad shape, not my
> proudest piece of code (thanks Jerome for pointing that out ;). I tried
> to rework it a bit to make it a bit more tolerable.
>
> I needed to change a bit the APIs and consequently adapt the only user
> we have, that is the nvmem/efuses driver. To not break bisectability I
> added one single commit to change both the drivers.
With your ack on the nvmem bindings and nvmem part of patch 4/4, I can
take the series take the rest of this series through my tree for Amlogic
SoCs.
Kevin
^ permalink raw reply
* Re: [PATCH 03/16] net: phy: adin: add support for interrupts
From: Heiner Kallweit @ 2019-08-05 21:02 UTC (permalink / raw)
To: Alexandru Ardelean, netdev, devicetree, linux-kernel
Cc: davem, robh+dt, mark.rutland, f.fainelli, andrew
In-Reply-To: <20190805165453.3989-4-alexandru.ardelean@analog.com>
On 05.08.2019 18:54, Alexandru Ardelean wrote:
> This change adds support for enabling PHY interrupts that can be used by
> the PHY framework to get signal for link/speed/auto-negotiation changes.
>
> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
> ---
> drivers/net/phy/adin.c | 44 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
> index c100a0dd95cd..b75c723bda79 100644
> --- a/drivers/net/phy/adin.c
> +++ b/drivers/net/phy/adin.c
> @@ -14,6 +14,22 @@
> #define PHY_ID_ADIN1200 0x0283bc20
> #define PHY_ID_ADIN1300 0x0283bc30
>
> +#define ADIN1300_INT_MASK_REG 0x0018
> +#define ADIN1300_INT_MDIO_SYNC_EN BIT(9)
> +#define ADIN1300_INT_ANEG_STAT_CHNG_EN BIT(8)
> +#define ADIN1300_INT_ANEG_PAGE_RX_EN BIT(6)
> +#define ADIN1300_INT_IDLE_ERR_CNT_EN BIT(5)
> +#define ADIN1300_INT_MAC_FIFO_OU_EN BIT(4)
> +#define ADIN1300_INT_RX_STAT_CHNG_EN BIT(3)
> +#define ADIN1300_INT_LINK_STAT_CHNG_EN BIT(2)
> +#define ADIN1300_INT_SPEED_CHNG_EN BIT(1)
> +#define ADIN1300_INT_HW_IRQ_EN BIT(0)
> +#define ADIN1300_INT_MASK_EN \
> + (ADIN1300_INT_ANEG_STAT_CHNG_EN | ADIN1300_INT_ANEG_PAGE_RX_EN | \
> + ADIN1300_INT_LINK_STAT_CHNG_EN | ADIN1300_INT_SPEED_CHNG_EN | \
> + ADIN1300_INT_HW_IRQ_EN)
> +#define ADIN1300_INT_STATUS_REG 0x0019
> +
> static int adin_config_init(struct phy_device *phydev)
> {
> int rc;
> @@ -25,15 +41,40 @@ static int adin_config_init(struct phy_device *phydev)
> return 0;
> }
>
> +static int adin_phy_ack_intr(struct phy_device *phydev)
> +{
> + int ret;
> +
> + /* Clear pending interrupts. */
> + ret = phy_read(phydev, ADIN1300_INT_STATUS_REG);
> + if (ret < 0)
> + return ret;
> +
> + return 0;
> +}
> +
> +static int adin_phy_config_intr(struct phy_device *phydev)
> +{
> + if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
> + return phy_set_bits(phydev, ADIN1300_INT_MASK_REG,
> + ADIN1300_INT_MASK_EN);
> +
> + return phy_clear_bits(phydev, ADIN1300_INT_MASK_REG,
> + ADIN1300_INT_MASK_EN);
> +}
> +
> static struct phy_driver adin_driver[] = {
> {
> .phy_id = PHY_ID_ADIN1200,
> .name = "ADIN1200",
> .phy_id_mask = 0xfffffff0,
> .features = PHY_BASIC_FEATURES,
> + .flags = PHY_HAS_INTERRUPT,
This flag doesn't exist any longer. This indicates that you
develop against an older kernel version. Please develop
against net-next. Check up-to-date drivers like the one
for Realtek PHY's for hints.
> .config_init = adin_config_init,
> .config_aneg = genphy_config_aneg,
> .read_status = genphy_read_status,
> + .ack_interrupt = adin_phy_ack_intr,
> + .config_intr = adin_phy_config_intr,
> .resume = genphy_resume,
> .suspend = genphy_suspend,
> },
> @@ -42,9 +83,12 @@ static struct phy_driver adin_driver[] = {
> .name = "ADIN1300",
> .phy_id_mask = 0xfffffff0,
> .features = PHY_GBIT_FEATURES,
> + .flags = PHY_HAS_INTERRUPT,
> .config_init = adin_config_init,
> .config_aneg = genphy_config_aneg,
> .read_status = genphy_read_status,
> + .ack_interrupt = adin_phy_ack_intr,
> + .config_intr = adin_phy_config_intr,
> .resume = genphy_resume,
> .suspend = genphy_suspend,
> },
>
^ permalink raw reply
* Re: [PATCH] ARM: dts: meson8b: add ethernet fifo sizes
From: Kevin Hilman @ 2019-08-05 20:57 UTC (permalink / raw)
Cc: Jerome Brunet, linux-amlogic, devicetree, linux-kernel
In-Reply-To: <20190718093623.23598-1-jbrunet@baylibre.com>
Jerome Brunet <jbrunet@baylibre.com> writes:
> If unspecified in DT, the fifo sizes are not automatically detected by
> the dwmac1000 dma driver and the reported fifo sizes default to 0.
> Because of this, flow control will be turned off on the device.
>
> Add the fifo sizes provided by the datasheet in the SoC in DT so
> flow control may be enabled if necessary.
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Queued for v5.4,
Thanks,
Kevin
^ permalink raw reply
* Re: [PATCH] arm64: dts: meson: add ethernet fifo sizes
From: Kevin Hilman @ 2019-08-05 20:57 UTC (permalink / raw)
Cc: Jerome Brunet, devicetree, linux-amlogic, linux-kernel
In-Reply-To: <20190718090301.19283-1-jbrunet@baylibre.com>
Jerome Brunet <jbrunet@baylibre.com> writes:
> If unspecified in DT, the fifo sizes are not automatically detected by
> the dwmac1000 dma driver and the reported fifo sizes default to 0.
> Because of this, flow control will be turned off on the device.
>
> Add the fifo sizes provided by the datasheets in the SoC in DT so
> flow control may be enabled if necessary.
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Queued for v5.4,
Thanks,
Kevin
^ permalink raw reply
* Re: [PATCH 01/16] net: phy: adin: add support for Analog Devices PHYs
From: Heiner Kallweit @ 2019-08-05 20:54 UTC (permalink / raw)
To: Alexandru Ardelean, netdev, devicetree, linux-kernel
Cc: davem, robh+dt, mark.rutland, f.fainelli, andrew
In-Reply-To: <20190805165453.3989-2-alexandru.ardelean@analog.com>
On 05.08.2019 18:54, Alexandru Ardelean wrote:
> This change adds support for Analog Devices Industrial Ethernet PHYs.
> Particularly the PHYs this driver adds support for:
> * ADIN1200 - Robust, Industrial, Low Power 10/100 Ethernet PHY
> * ADIN1300 - Robust, Industrial, Low Latency 10/100/1000 Gigabit
> Ethernet PHY
>
> The 2 chips are pin & register compatible with one another. The main
> difference being that ADIN1200 doesn't operate in gigabit mode.
>
> The chips can be operated by the Generic PHY driver as well via the
> standard IEEE PHY registers (0x0000 - 0x000F) which are supported by the
> kernel as well. This assumes that configuration of the PHY has been done
> required.
>
> Configuration can also be done via registers, which will be implemented by
> the driver in the next changes.
>
> Datasheets:
> https://www.analog.com/media/en/technical-documentation/data-sheets/ADIN1300.pdf
> https://www.analog.com/media/en/technical-documentation/data-sheets/ADIN1200.pdf
>
> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
> ---
> MAINTAINERS | 7 +++++
> drivers/net/phy/Kconfig | 9 ++++++
> drivers/net/phy/Makefile | 1 +
> drivers/net/phy/adin.c | 59 ++++++++++++++++++++++++++++++++++++++++
> 4 files changed, 76 insertions(+)
> create mode 100644 drivers/net/phy/adin.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index ee663e0e2f2e..faf5723610c8 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -938,6 +938,13 @@ S: Supported
> F: drivers/mux/adgs1408.c
> F: Documentation/devicetree/bindings/mux/adi,adgs1408.txt
>
> +ANALOG DEVICES INC ADIN DRIVER
> +M: Alexandru Ardelean <alexaundru.ardelean@analog.com>
> +L: netdev@vger.kernel.org
> +W: http://ez.analog.com/community/linux-device-drivers
> +S: Supported
> +F: drivers/net/phy/adin.c
> +
> ANALOG DEVICES INC ADIS DRIVER LIBRARY
> M: Alexandru Ardelean <alexandru.ardelean@analog.com>
> S: Supported
> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> index 206d8650ee7f..5966d3413676 100644
> --- a/drivers/net/phy/Kconfig
> +++ b/drivers/net/phy/Kconfig
> @@ -257,6 +257,15 @@ config SFP
> depends on HWMON || HWMON=n
> select MDIO_I2C
>
> +config ADIN_PHY
> + tristate "Analog Devices Industrial Ethernet PHYs"
> + help
> + Adds support for the Analog Devices Industrial Ethernet PHYs.
> + Currently supports the:
> + - ADIN1200 - Robust,Industrial, Low Power 10/100 Ethernet PHY
> + - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
> + Ethernet PHY
> +
> config AMD_PHY
> tristate "AMD PHYs"
> ---help---
> diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
> index ba07c27e4208..a03437e091f3 100644
> --- a/drivers/net/phy/Makefile
> +++ b/drivers/net/phy/Makefile
> @@ -47,6 +47,7 @@ obj-$(CONFIG_SFP) += sfp.o
> sfp-obj-$(CONFIG_SFP) += sfp-bus.o
> obj-y += $(sfp-obj-y) $(sfp-obj-m)
>
> +obj-$(CONFIG_ADIN_PHY) += adin.o
> obj-$(CONFIG_AMD_PHY) += amd.o
> aquantia-objs += aquantia_main.o
> ifdef CONFIG_HWMON
> diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
> new file mode 100644
> index 000000000000..6a610d4563c3
> --- /dev/null
> +++ b/drivers/net/phy/adin.c
> @@ -0,0 +1,59 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/**
> + * Driver for Analog Devices Industrial Ethernet PHYs
> + *
> + * Copyright 2019 Analog Devices Inc.
> + */
> +#include <linux/kernel.h>
> +#include <linux/errno.h>
> +#include <linux/init.h>
> +#include <linux/module.h>
> +#include <linux/mii.h>
> +#include <linux/phy.h>
> +
> +#define PHY_ID_ADIN1200 0x0283bc20
> +#define PHY_ID_ADIN1300 0x0283bc30
> +
> +static int adin_config_init(struct phy_device *phydev)
> +{
> + int rc;
> +
> + rc = genphy_config_init(phydev);
> + if (rc < 0)
> + return rc;
> +
> + return 0;
> +}
> +
> +static struct phy_driver adin_driver[] = {
> + {
> + .phy_id = PHY_ID_ADIN1200,
You could use PHY_ID_MATCH_MODEL here.
> + .name = "ADIN1200",
> + .phy_id_mask = 0xfffffff0,
> + .features = PHY_BASIC_FEATURES,
Setting features is deprecated, instead the get_features callback
should be implemented if the default genphy_read_abilities needs
to be extended / replaced. You say that the PHY's work with the
genphy driver, so I suppose the default feature detection is ok
in your case. Then you could simply remove setting "features".
> + .config_init = adin_config_init,
> + .config_aneg = genphy_config_aneg,
> + .read_status = genphy_read_status,
> + },
> + {
> + .phy_id = PHY_ID_ADIN1300,
> + .name = "ADIN1300",
> + .phy_id_mask = 0xfffffff0,
> + .features = PHY_GBIT_FEATURES,
> + .config_init = adin_config_init,
> + .config_aneg = genphy_config_aneg,
> + .read_status = genphy_read_status,
> + },
> +};
> +
> +module_phy_driver(adin_driver);
> +
> +static struct mdio_device_id __maybe_unused adin_tbl[] = {
> + { PHY_ID_ADIN1200, 0xfffffff0 },
> + { PHY_ID_ADIN1300, 0xfffffff0 },
PHY_ID_MATCH_MODEL could be used here too.
> + { }
> +};
> +
> +MODULE_DEVICE_TABLE(mdio, adin_tbl);
> +MODULE_DESCRIPTION("Analog Devices Industrial Ethernet PHY driver");
> +MODULE_LICENSE("GPL");
>
^ permalink raw reply
* Re: [PATCH 3/8] of/fdt: add function to get the SoC wide DMA addressable memory size
From: Rob Herring @ 2019-08-05 19:23 UTC (permalink / raw)
To: Nicolas Saenz Julienne
Cc: Catalin Marinas, Will Deacon, Christoph Hellwig, wahrenst,
Marc Zyngier, Robin Murphy,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
devicetree, Linux IOMMU, linux-mm, Frank Rowand, phill,
Florian Fainelli, linux-kernel@vger.kernel.org, Eric Anholt,
Matthias Brugger, Andrew Morton, Marek Szyprowski,
"moderated list:BROADCOM BCM2835 ARM ARCHITECTURE" <linux-rp>
In-Reply-To: <2050374ac07e0330e505c4a1637256428adb10c4.camel@suse.de>
On Mon, Aug 5, 2019 at 10:03 AM Nicolas Saenz Julienne
<nsaenzjulienne@suse.de> wrote:
>
> Hi Rob,
> Thanks for the review!
>
> On Fri, 2019-08-02 at 11:17 -0600, Rob Herring wrote:
> > On Wed, Jul 31, 2019 at 9:48 AM Nicolas Saenz Julienne
> > <nsaenzjulienne@suse.de> wrote:
> > > Some SoCs might have multiple interconnects each with their own DMA
> > > addressing limitations. This function parses the 'dma-ranges' on each of
> > > them and tries to guess the maximum SoC wide DMA addressable memory
> > > size.
> > >
> > > This is specially useful for arch code in order to properly setup CMA
> > > and memory zones.
> >
> > We already have a way to setup CMA in reserved-memory, so why is this
> > needed for that?
>
> Correct me if I'm wrong but I got the feeling you got the point of the patch
> later on.
No, for CMA I don't. Can't we already pass a size and location for CMA
region under /reserved-memory. The only advantage here is perhaps the
CMA range could be anywhere in the DMA zone vs. a fixed location.
> > > Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
> > > ---
> > >
> > > drivers/of/fdt.c | 72 ++++++++++++++++++++++++++++++++++++++++++
> > > include/linux/of_fdt.h | 2 ++
> > > 2 files changed, 74 insertions(+)
> > >
> > > diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
> > > index 9cdf14b9aaab..f2444c61a136 100644
> > > --- a/drivers/of/fdt.c
> > > +++ b/drivers/of/fdt.c
> > > @@ -953,6 +953,78 @@ int __init early_init_dt_scan_chosen_stdout(void)
> > > }
> > > #endif
> > >
> > > +/**
> > > + * early_init_dt_dma_zone_size - Look at all 'dma-ranges' and provide the
> > > + * maximum common dmable memory size.
> > > + *
> > > + * Some devices might have multiple interconnects each with their own DMA
> > > + * addressing limitations. For example the Raspberry Pi 4 has the
> > > following:
> > > + *
> > > + * soc {
> > > + * dma-ranges = <0xc0000000 0x0 0x00000000 0x3c000000>;
> > > + * [...]
> > > + * }
> > > + *
> > > + * v3dbus {
> > > + * dma-ranges = <0x00000000 0x0 0x00000000 0x3c000000>;
> > > + * [...]
> > > + * }
> > > + *
> > > + * scb {
> > > + * dma-ranges = <0x0 0x00000000 0x0 0x00000000 0xfc000000>;
> > > + * [...]
> > > + * }
> > > + *
> > > + * Here the area addressable by all devices is [0x00000000-0x3bffffff].
> > > Hence
> > > + * the function will write in 'data' a size of 0x3c000000.
> > > + *
> > > + * Note that the implementation assumes all interconnects have the same
> > > physical
> > > + * memory view and that the mapping always start at the beginning of RAM.
> >
> > Not really a valid assumption for general code.
>
> Fair enough. On my defence I settled on that assumption after grepping all dts
> and being unable to find a board that behaved otherwise.
>
> [...]
>
> > It's possible to have multiple levels of nodes and dma-ranges. You need to
> > handle that case too. Doing that and handling differing address translations
> > will be complicated.
>
> Understood.
>
> > IMO, I'd just do:
> >
> > if (of_fdt_machine_is_compatible(blob, "brcm,bcm2711"))
> > dma_zone_size = XX;
> >
> > 2 lines of code is much easier to maintain than 10s of incomplete code
> > and is clearer who needs this. Maybe if we have dozens of SoCs with
> > this problem we should start parsing dma-ranges.
>
> FYI that's what arm32 is doing at the moment and was my first instinct. But it
> seems that arm64 has been able to survive so far without any machine specific
> code and I have the feeling Catalin and Will will not be happy about this
> solution. Am I wrong?
No doubt. I'm fine if the 2 lines live in drivers/of/.
Note that I'm trying to reduce the number of early_init_dt_scan_*
calls from arch code into the DT code so there's more commonality
across architectures in the early DT scans. So ideally, this can all
be handled under early_init_dt_scan() call.
Rob
^ permalink raw reply
* Re: [RESEND PATCH v5 3/4] dt-bindings: mailbox: imx-mu: add imx7ulp MU support
From: Daniel Baluta @ 2019-08-05 19:20 UTC (permalink / raw)
To: Richard Zhu
Cc: Aisheng Dong, Devicetree List, jassisinghbrar,
Linux Kernel Mailing List, Oleksij Rempel, Rob Herring,
dl-linux-imx, Daniel Baluta, linux-arm-kernel
In-Reply-To: <1564980742-19124-4-git-send-email-hongxing.zhu@nxp.com>
+ Rob
On Mon, Aug 5, 2019 at 8:18 AM Richard Zhu <hongxing.zhu@nxp.com> wrote:
>
> There is a version 1.0 MU on imx7ulp, use "fsl,imx7ulp-mu" compatible
> to support it.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
> ---
> Documentation/devicetree/bindings/mailbox/fsl,mu.txt | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
> index f3cf77e..9c43357 100644
> --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
> +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt
> @@ -21,6 +21,8 @@ Required properties:
> imx6sx, imx7s, imx8qxp, imx8qm.
> The "fsl,imx6sx-mu" compatible is seen as generic and should
> be included together with SoC specific compatible.
> + There is a version 1.0 MU on imx7ulp, use "fsl,imx7ulp-mu"
> + compatible to support it.
> - reg : Should contain the registers location and length
> - interrupts : Interrupt number. The interrupt specifier format depends
> on the interrupt controller parent.
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH v7 01/20] pinctrl: tegra: Add suspend and resume support
From: Sowjanya Komatineni @ 2019-08-05 18:06 UTC (permalink / raw)
To: Dmitry Osipenko, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree, rjw, viresh.kumar, linux-pm
In-Reply-To: <6b1482f6-0578-f602-d8d1-541d86303ce2@gmail.com>
On 8/5/19 3:50 AM, Dmitry Osipenko wrote:
> 01.08.2019 0:10, Sowjanya Komatineni пишет:
>> This patch adds support for Tegra pinctrl driver suspend and resume.
>>
>> During suspend, context of all pinctrl registers are stored and
>> on resume they are all restored to have all the pinmux and pad
>> configuration for normal operation.
>>
>> Acked-by: Thierry Reding <treding@nvidia.com>
>> Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>> ---
>> drivers/pinctrl/tegra/pinctrl-tegra.c | 59 +++++++++++++++++++++++++++++++++++
>> drivers/pinctrl/tegra/pinctrl-tegra.h | 3 ++
>> 2 files changed, 62 insertions(+)
>>
>> diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c
>> index 186ef98e7b2b..e3a237534281 100644
>> --- a/drivers/pinctrl/tegra/pinctrl-tegra.c
>> +++ b/drivers/pinctrl/tegra/pinctrl-tegra.c
>> @@ -631,6 +631,58 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
>> }
>> }
>>
>> +static size_t tegra_pinctrl_get_bank_size(struct device *dev,
>> + unsigned int bank_id)
>> +{
>> + struct platform_device *pdev = to_platform_device(dev);
>> + struct resource *res;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, bank_id);
>> +
>> + return resource_size(res) / 4;
>> +}
>> +
>> +static int tegra_pinctrl_suspend(struct device *dev)
>> +{
>> + struct tegra_pmx *pmx = dev_get_drvdata(dev);
>> + u32 *backup_regs = pmx->backup_regs;
>> + u32 *regs;
>> + size_t bank_size;
>> + unsigned int i, k;
>> +
>> + for (i = 0; i < pmx->nbanks; i++) {
>> + bank_size = tegra_pinctrl_get_bank_size(dev, i);
>> + regs = pmx->regs[i];
>> + for (k = 0; k < bank_size; k++)
>> + *backup_regs++ = readl_relaxed(regs++);
>> + }
>> +
>> + return pinctrl_force_sleep(pmx->pctl);
>> +}
>> +
>> +static int tegra_pinctrl_resume(struct device *dev)
>> +{
>> + struct tegra_pmx *pmx = dev_get_drvdata(dev);
>> + u32 *backup_regs = pmx->backup_regs;
>> + u32 *regs;
>> + size_t bank_size;
>> + unsigned int i, k;
>> +
>> + for (i = 0; i < pmx->nbanks; i++) {
>> + bank_size = tegra_pinctrl_get_bank_size(dev, i);
>> + regs = pmx->regs[i];
>> + for (k = 0; k < bank_size; k++)
>> + writel_relaxed(*backup_regs++, regs++);
>> + }
> I'm now curious whether any kind of barrier is needed after the
> writings. The pmx_writel() doesn't insert a barrier after the write and
> seems it just misuses writel, which actually should be writel_relaxed()
> + barrier, IIUC.
pmx_writel uses writel and it has wmb before raw_write which complete
all writes initiated prior to this.
By misusing writel, you mean to have barrier after register write?
> It's also not obvious whether PINCTRL HW has any kind of write-FIFO and
> thus maybe read-back + rmb() is needed in order ensure that writes are
> actually completed.
I believe adding write barrier wmb after writel_relaxed should be good
rather than doing readback + rmb
>
> The last thing which is not obvious is when the new configuration
> actually takes into effect, does it happen immediately or maybe some
> delay is needed?
>
> [snip]
Based on internal design there is no internal delay and it all depends
on APB rate that it takes to write to register.
Pinmux value change to reflect internally might take couple of clock
cycles which is much faster than SW can read.
^ permalink raw reply
* Re: [PATCH 0/6] hwspinlock: allow sharing of hwspinlocks
From: Bjorn Andersson @ 2019-08-05 17:46 UTC (permalink / raw)
To: Fabien DESSENNE
Cc: Ohad Ben-Cohen, Rob Herring, Mark Rutland, Maxime Coquelin,
Alexandre TORGUE, Jonathan Corbet,
linux-remoteproc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org,
Benjamin GAIGNARD
In-Reply-To: <1a057176-81ab-e302-4375-2717ceef6924@st.com>
On Mon 05 Aug 01:48 PDT 2019, Fabien DESSENNE wrote:
>
> On 01/08/2019 9:14 PM, Bjorn Andersson wrote:
> > On Wed 13 Mar 08:50 PDT 2019, Fabien Dessenne wrote:
> >
> >> The current implementation does not allow two different devices to use
> >> a common hwspinlock. This patch set proposes to have, as an option, some
> >> hwspinlocks shared between several users.
> >>
> >> Below is an example that explain the need for this:
> >> exti: interrupt-controller@5000d000 {
> >> compatible = "st,stm32mp1-exti", "syscon";
> >> interrupt-controller;
> >> #interrupt-cells = <2>;
> >> reg = <0x5000d000 0x400>;
> >> hwlocks = <&hsem 1>;
> >> };
> >> The two drivers (stm32mp1-exti and syscon) refer to the same hwlock.
> >> With the current hwspinlock implementation, only the first driver succeeds
> >> in requesting (hwspin_lock_request_specific) the hwlock. The second request
> >> fails.
> >>
> >>
> >> The proposed approach does not modify the API, but extends the DT 'hwlocks'
> >> property with a second optional parameter (the first one identifies an
> >> hwlock) that specifies whether an hwlock is requested for exclusive usage
> >> (current behavior) or can be shared between several users.
> >> Examples:
> >> hwlocks = <&hsem 8>; Ref to hwlock #8 for exclusive usage
> >> hwlocks = <&hsem 8 0>; Ref to hwlock #8 for exclusive (0) usage
> >> hwlocks = <&hsem 8 1>; Ref to hwlock #8 for shared (1) usage
> >>
> >> As a constraint, the #hwlock-cells value must be 1 or 2.
> >> In the current implementation, this can have theorically any value but:
> >> - all of the exisiting drivers use the same value : 1.
> >> - the framework supports only one value : 1 (see implementation of
> >> of_hwspin_lock_simple_xlate())
> >> Hence, it shall not be a problem to restrict this value to 1 or 2 since
> >> it won't break any driver.
> >>
> > Hi Fabien,
> >
> > Your series looks good, but it makes me wonder why the hardware locks
> > should be an exclusive resource.
> >
> > How about just making all (specific) locks shared?
>
> Hi Bjorn,
>
> Making all locks shared is a possible implementation (my first
> implementation
> was going this way) but there are some drawbacks we must be aware of:
>
> A/ This theoretically break the legacy behavior (the legacy works with
> exclusive (UNUSED radix tag) usage). As a consequence, an existing driver
> that is currently failing to request a lock (already claimed by another
> user) would now work fine. Not sure that there are such drivers, so this
> point is probably not a real issue.
>
Right, it's possible that a previously misconfigured system now
successfully probes more than one device that uses a particular
spinlock. But such system would be suffering from issues related to e.g.
probe ordering.
So I think we should ignore this issue.
> B/ This would introduce some inconsistency between the two 'request' API
> which are hwspin_lock_request() and hwspin_lock_request_specific().
> hwspin_lock_request() looks for an unused lock, so requests for an exclusive
> usage. On the other side, request_specific() would request shared locks.
> Worst the following sequence can transform an exclusive usage into a shared
>
There is already an inconsistency in between these; as with above any
system that uses both request() and request_specific() will be suffering
from intermittent failures due to probe ordering.
> one:
> -hwspin_lock_request() -> returns Id#0 (exclusive)
> -hwspin_lock_request() -> returns Id#1 (exclusive)
> -hwspin_lock_request_specific(0) -> returns Id#0 and makes Id#0 shared
> Honestly I am not sure that this is a real issue, but it's better to have it
> in mind before we take ay decision
The case where I can see a
problem with this would be if the two clients somehow would nest their
locking regions.
But generally I think this could consider this an improvement, because
the request_specific() would now be able to acquire its hwlock, with
some additional contention due to the multiple use.
> I could not find any driver using the hwspin_lock_request() API, we
> may decide to remove (or to make deprecated) this API, having
> everything 'shared without any conditions'.
>
It would be nice to have an upstream user of this API.
>
> I can see three options:
> 1- Keep my initial proposition
> 2- Have hwspin_lock_request_specific() using shared locks and
> hwspin_lock_request() using unused (so 'initially' exclusive) locks.
> 3- Have hwspin_lock_request_specific() using shared locks and
> remove/make deprecated hwspin_lock_request().
>
> Just let me know what is your preference.
>
I think we should start with #2 and would like input from e.g. Suman
regarding #3.
Regards,
Bjorn
> BR
>
> Fabien
>
> >
> > Regards,
> > Bjorn
> >
> >> Fabien Dessenne (6):
> >> dt-bindings: hwlock: add support of shared locks
> >> hwspinlock: allow sharing of hwspinlocks
> >> dt-bindings: hwlock: update STM32 #hwlock-cells value
> >> ARM: dts: stm32: Add hwspinlock node for stm32mp157 SoC
> >> ARM: dts: stm32: Add hwlock for irqchip on stm32mp157
> >> ARM: dts: stm32: hwlocks for GPIO for stm32mp157
> >>
> >> .../devicetree/bindings/hwlock/hwlock.txt | 27 +++++--
> >> .../bindings/hwlock/st,stm32-hwspinlock.txt | 6 +-
> >> Documentation/hwspinlock.txt | 10 ++-
> >> arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 2 +
> >> arch/arm/boot/dts/stm32mp157c.dtsi | 10 +++
> >> drivers/hwspinlock/hwspinlock_core.c | 82 +++++++++++++++++-----
> >> drivers/hwspinlock/hwspinlock_internal.h | 2 +
> >> 7 files changed, 108 insertions(+), 31 deletions(-)
> >>
> >> --
> >> 2.7.4
> >>
^ permalink raw reply
* Re: [PATCH v2] of/fdt: implement a "merge-cmdline" property
From: Daniel Gimpelevich @ 2019-08-05 17:39 UTC (permalink / raw)
To: Rob Herring; +Cc: devicetree, Paul Burton
In-Reply-To: <CAL_JsqLobsATYbKR0Rx8kpS3i+hHqsqibYn9h5Xi1T=DVwRF1g@mail.gmail.com>
On Mon, 2019-08-05 at 10:29 -0600, Rob Herring wrote:
> On Mon, Aug 5, 2019 at 9:53 AM Daniel Gimpelevich
> <daniel@gimpelevich.san-francisco.ca.us> wrote:
> >
> > Currently, "bootargs" supplied via the "chosen" node can be used only to
> > supply a kernel command line as a whole. No mechanism exists in DT to add
> > bootargs to the existing command line instead. This is needed in order to
> > avoid having to update the bootloader or default bootloader config when
> > upgrading to a DTB and kernel pair that requires bootargs not previously
> > needed.
>
> The DTB and kernel are not a pair. Or at least they shouldn't be. If
> anything, the bootloader and DTB are a pair as those are the h/w
> specific parts. If the DTB and kernel are a pair, then anything you
> want to put into DTB can just be in the kernel.
They would only be a pair in the sense that DTB changes using newer
bindings would also require a newer kernel.
> There's been some
> attempts to rework the command line handling to be common and support
> prepending and appending which could be useful here.
Sounds good. Can you reference any commit hash for this?
> > One example use case is that OpenWrt currently supports four ARM devices by
> > means of locally applying the previously rejected edition of this patch. So
> > far, the patch has been used in production only on ARM, but architecture is
> > not a distinction in the design.
>
> Other distros support dozens of boards, so why haven't they ever
> needed such a change?
IMHO, each of those four boards could be supported in some other way.
That said, some other devices have bootloaders implementing dual boot
with fallback on failure, and the kernel should always have access to
any bootarg that reflects which one is being booted.
> > On MIPS, Commit 951d223 ("MIPS: Fix CONFIG_CMDLINE handling") currently
> > prevents support of such a mechanism, so I am including a workaround, in
> > anticipation of upcoming changes.
>
> Like I said on irc, mixing this with the mess that is MIPS
> bootloader-kernel interface generally and command line handling
> specifically is not a path to upstream.
The DT proposal can be separated from the MIPS mess.
> This is worse than the original proposal because 'merge' is not clear
> what it does compared to 'append' and how does 'cmdline' relate to
> 'bootargs'.
Can there be a different property name that would be better instead of
worse?
^ permalink raw reply
* Re: [RFC PATCH 1/2] dt-bindings: net: macb: Add new property for PS SGMII only
From: Andrew Lunn @ 2019-08-05 17:16 UTC (permalink / raw)
To: Harini Katakam
Cc: Harini Katakam, Nicolas Ferre, David Miller, Claudiu Beznea,
Rob Herring, Mark Rutland, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org, Michal Simek,
devicetree@vger.kernel.org
In-Reply-To: <CAFcVECLVHY5X=wctxVqRqDTDyG7Zavkt5ui4RtFBLP8g8MW1SA@mail.gmail.com>
> Even with the use of this interrupt, the link status actions (link print and
> netif ops) will still be required. And also the need for macb_open to
> proceed without phydev. Could you please let me know if that is acceptable
> to patch or if there's a cleaner way to
> report this link status?
It sounds like you need to convert to phylink, so you get full sfp
support. phylib does not handle hotplug of PHYs.
Please look at the comments Russell gave the last time this was
attempted.
Andrew
^ permalink raw reply
* [PATCH 16/16] dt-bindings: net: add bindings for ADIN PHY driver
From: Alexandru Ardelean @ 2019-08-05 16:54 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel
Cc: davem, robh+dt, mark.rutland, f.fainelli, hkallweit1, andrew,
Alexandru Ardelean
In-Reply-To: <20190805165453.3989-1-alexandru.ardelean@analog.com>
This change adds bindings for the Analog Devices ADIN PHY driver, detailing
all the properties implemented by the driver.
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
.../devicetree/bindings/net/adi,adin.yaml | 93 +++++++++++++++++++
MAINTAINERS | 2 +
include/dt-bindings/net/adin.h | 26 ++++++
3 files changed, 121 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/adi,adin.yaml
create mode 100644 include/dt-bindings/net/adin.h
diff --git a/Documentation/devicetree/bindings/net/adi,adin.yaml b/Documentation/devicetree/bindings/net/adi,adin.yaml
new file mode 100644
index 000000000000..fcf884bb86f7
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/adi,adin.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: GPL-2.0+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/adi,adin.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices ADIN1200/ADIN1300 PHY
+
+maintainers:
+ - Alexandru Ardelean <alexandru.ardelean@analog.com>
+
+description: |
+ Bindings for Analog Devices Industrial Ethernet PHYs
+
+properties:
+ compatible:
+ description: |
+ Compatible list, may contain "ethernet-phy-ieee802.3-c45" in which case
+ Clause 45 will be used to access device management registers. If
+ unspecified, Clause 22 will be used. Use this only when MDIO supports
+ Clause 45 access, but there is no other way to determine this.
+ enum:
+ - ethernet-phy-ieee802.3-c45
+
+ adi,phy-mode-internal:
+ $ref: /schemas/types.yaml#/definitions/string
+ description: |
+ The internal mode of the PHY. This assumes that there is a PHY converter
+ in-between the MAC & PHY.
+ enum: [ "rgmii", "rgmii-id", "rgmii-txid", "rgmii-rxid", "rmii", "mii" ]
+
+ adi,rx-internal-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ RGMII RX Clock Delay used only when PHY operates in RGMII mode (phy-mode
+ is "rgmii-id", "rgmii-rxid", "rgmii-txid") see `dt-bindings/net/adin.h`
+ default value is 0 (which represents 2 ns)
+ enum: [ 0, 1, 2, 6, 7 ]
+
+ adi,tx-internal-delay:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ RGMII TX Clock Delay used only when PHY operates in RGMII mode (phy-mode
+ is "rgmii-id", "rgmii-rxid", "rgmii-txid") see `dt-bindings/net/adin.h`
+ default value is 0 (which represents 2 ns)
+ enum: [ 0, 1, 2, 6, 7 ]
+
+ adi,fifo-depth:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ When operating in RMII mode, this option configures the FIFO depth.
+ See `dt-bindings/net/adin.h`.
+ enum: [ 0, 1, 2, 3, 4, 5 ]
+
+ adi,eee-enabled:
+ description: |
+ Advertise EEE capabilities on power-up/init (default disabled)
+ type: boolean
+
+ adi,disable-energy-detect:
+ description: |
+ Disables Energy Detect Powerdown Mode (default disabled, i.e energy detect
+ is enabled if this property is unspecified)
+ type: boolean
+
+ reset-gpios:
+ description: |
+ GPIO to reset the PHY
+ see Documentation/devicetree/bindings/gpio/gpio.txt.
+
+examples:
+ - |
+ ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0>;
+ };
+ - |
+ #include <dt-bindings/net/adin.h>
+ ethernet-phy@1 {
+ reg = <1>;
+ adi,phy-mode-internal = "rgmii-id";
+
+ adi,rx-internal-delay = <ADIN1300_RGMII_1_80_NS>;
+ adi,tx-internal-delay = <ADIN1300_RGMII_2_20_NS>;
+ };
+ - |
+ #include <dt-bindings/net/adin.h>
+ ethernet-phy@2 {
+ reg = <2>;
+ phy-mode = "rmii";
+
+ adi,fifo-depth = <ADIN1300_RMII_16_BITS>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index faf5723610c8..6ffbb266dee4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -944,6 +944,8 @@ L: netdev@vger.kernel.org
W: http://ez.analog.com/community/linux-device-drivers
S: Supported
F: drivers/net/phy/adin.c
+F: include/dt-bindings/net/adin.h
+F: Documentation/devicetree/bindings/net/adi,adin.yaml
ANALOG DEVICES INC ADIS DRIVER LIBRARY
M: Alexandru Ardelean <alexandru.ardelean@analog.com>
diff --git a/include/dt-bindings/net/adin.h b/include/dt-bindings/net/adin.h
new file mode 100644
index 000000000000..4c3afa550c59
--- /dev/null
+++ b/include/dt-bindings/net/adin.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/**
+ * Device Tree constants for Analog Devices Industrial Ethernet PHYs
+ *
+ * Copyright 2019 Analog Devices Inc.
+ */
+
+#ifndef _DT_BINDINGS_ADIN_H
+#define _DT_BINDINGS_ADIN_H
+
+/* RGMII internal delay settings for rx and tx for ADIN1300 */
+#define ADIN1300_RGMII_1_60_NS 0x1
+#define ADIN1300_RGMII_1_80_NS 0x2
+#define ADIN1300_RGMII_2_00_NS 0x0
+#define ADIN1300_RGMII_2_20_NS 0x6
+#define ADIN1300_RGMII_2_40_NS 0x7
+
+/* RMII fifo depth values */
+#define ADIN1300_RMII_4_BITS 0x0
+#define ADIN1300_RMII_8_BITS 0x1
+#define ADIN1300_RMII_12_BITS 0x2
+#define ADIN1300_RMII_16_BITS 0x3
+#define ADIN1300_RMII_20_BITS 0x4
+#define ADIN1300_RMII_24_BITS 0x5
+
+#endif
--
2.20.1
^ permalink raw reply related
* [PATCH 15/16] net: phy: adin: add ethtool get_stats support
From: Alexandru Ardelean @ 2019-08-05 16:54 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel
Cc: davem, robh+dt, mark.rutland, f.fainelli, hkallweit1, andrew,
Alexandru Ardelean
In-Reply-To: <20190805165453.3989-1-alexandru.ardelean@analog.com>
This change implements retrieving all the error counters from the PHY.
The PHY supports several error counters/stats. The `Mean Square Errors`
status values are only valie when a link is established, and shouldn't be
incremented. These values characterize the quality of a signal.
The rest of the error counters are self-clearing on read.
Most of them are reports from the Frame Checker engine that the PHY has.
Not retrieving the `LPI Wake Error Count Register` here, since that is used
by the PHY framework to check for any EEE errors. And that register is
self-clearing when read (as per IEEE spec).
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
drivers/net/phy/adin.c | 108 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 108 insertions(+)
diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
index a1f3456a8504..04896547dac8 100644
--- a/drivers/net/phy/adin.c
+++ b/drivers/net/phy/adin.c
@@ -103,6 +103,32 @@ static struct clause22_mmd_map clause22_mmd_map[] = {
{ MDIO_MMD_PCS, MDIO_PCS_EEE_WK_ERR, ADIN1300_LPI_WAKE_ERR_CNT_REG },
};
+struct adin_hw_stat {
+ const char *string;
+ u16 reg1;
+ u16 reg2;
+ bool do_not_inc;
+};
+
+/* Named just like in the datasheet */
+static struct adin_hw_stat adin_hw_stats[] = {
+ { "RxErrCnt", 0x0014, },
+ { "MseA", 0x8402, 0, true },
+ { "MseB", 0x8403, 0, true },
+ { "MseC", 0x8404, 0, true },
+ { "MseD", 0x8405, 0, true },
+ { "FcFrmCnt", 0x940A, 0x940B }, /* FcFrmCntH + FcFrmCntL */
+ { "FcLenErrCnt", 0x940C },
+ { "FcAlgnErrCnt", 0x940D },
+ { "FcSymbErrCnt", 0x940E },
+ { "FcOszCnt", 0x940F },
+ { "FcUszCnt", 0x9410 },
+ { "FcOddCnt", 0x9411 },
+ { "FcOddPreCnt", 0x9412 },
+ { "FcDribbleBitsCnt", 0x9413 },
+ { "FcFalseCarrierCnt", 0x9414 },
+};
+
/**
* struct adin_priv - ADIN PHY driver private data
* gpiod_reset optional reset GPIO, to be used in soft_reset() cb
@@ -113,6 +139,7 @@ struct adin_priv {
struct gpio_desc *gpiod_reset;
u8 eee_modes;
bool edpd_enabled;
+ u64 stats[ARRAY_SIZE(adin_hw_stats)];
};
static int adin_get_phy_internal_mode(struct phy_device *phydev)
@@ -568,6 +595,81 @@ static int adin_reset(struct phy_device *phydev)
return adin_subsytem_soft_reset(phydev);
}
+static int adin_get_sset_count(struct phy_device *phydev)
+{
+ return ARRAY_SIZE(adin_hw_stats);
+}
+
+static void adin_get_strings(struct phy_device *phydev, u8 *data)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++) {
+ memcpy(data + i * ETH_GSTRING_LEN,
+ adin_hw_stats[i].string, ETH_GSTRING_LEN);
+ }
+}
+
+static int adin_read_mmd_stat_regs(struct phy_device *phydev,
+ struct adin_hw_stat *stat,
+ u32 *val)
+{
+ int ret;
+
+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg1);
+ if (ret < 0)
+ return ret;
+
+ *val = (ret & 0xffff);
+
+ if (stat->reg2 == 0)
+ return 0;
+
+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg2);
+ if (ret < 0)
+ return ret;
+
+ *val <<= 16;
+ *val |= (ret & 0xffff);
+
+ return 0;
+}
+
+static u64 adin_get_stat(struct phy_device *phydev, int i)
+{
+ struct adin_hw_stat *stat = &adin_hw_stats[i];
+ struct adin_priv *priv = phydev->priv;
+ u32 val;
+ int ret;
+
+ if (stat->reg1 > 0x1f) {
+ ret = adin_read_mmd_stat_regs(phydev, stat, &val);
+ if (ret < 0)
+ return (u64)(~0);
+ } else {
+ ret = phy_read(phydev, stat->reg1);
+ if (ret < 0)
+ return (u64)(~0);
+ val = (ret & 0xffff);
+ }
+
+ if (stat->do_not_inc)
+ priv->stats[i] = val;
+ else
+ priv->stats[i] += val;
+
+ return priv->stats[i];
+}
+
+static void adin_get_stats(struct phy_device *phydev,
+ struct ethtool_stats *stats, u64 *data)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(adin_hw_stats); i++)
+ data[i] = adin_get_stat(phydev, i);
+}
+
static int adin_probe(struct phy_device *phydev)
{
struct device *dev = &phydev->mdio.dev;
@@ -607,6 +709,9 @@ static struct phy_driver adin_driver[] = {
.read_status = adin_read_status,
.ack_interrupt = adin_phy_ack_intr,
.config_intr = adin_phy_config_intr,
+ .get_sset_count = adin_get_sset_count,
+ .get_strings = adin_get_strings,
+ .get_stats = adin_get_stats,
.resume = genphy_resume,
.suspend = genphy_suspend,
.read_mmd = adin_read_mmd,
@@ -624,6 +729,9 @@ static struct phy_driver adin_driver[] = {
.read_status = adin_read_status,
.ack_interrupt = adin_phy_ack_intr,
.config_intr = adin_phy_config_intr,
+ .get_sset_count = adin_get_sset_count,
+ .get_strings = adin_get_strings,
+ .get_stats = adin_get_stats,
.resume = genphy_resume,
.suspend = genphy_suspend,
.read_mmd = adin_read_mmd,
--
2.20.1
^ permalink raw reply related
* [PATCH 14/16] net: phy: adin: make sure down-speed auto-neg is enabled
From: Alexandru Ardelean @ 2019-08-05 16:54 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel
Cc: davem, robh+dt, mark.rutland, f.fainelli, hkallweit1, andrew,
Alexandru Ardelean
In-Reply-To: <20190805165453.3989-1-alexandru.ardelean@analog.com>
Down-speed auto-negotiation may not always be enabled, in which case the
PHY won't down-shift to 100 or 10 during auto-negotiation.
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
drivers/net/phy/adin.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
index 86848444bd98..a1f3456a8504 100644
--- a/drivers/net/phy/adin.c
+++ b/drivers/net/phy/adin.c
@@ -32,6 +32,13 @@
#define ADIN1300_NRG_PD_TX_EN BIT(2)
#define ADIN1300_NRG_PD_STATUS BIT(1)
+#define ADIN1300_PHY_CTRL2 0x0016
+#define ADIN1300_DOWNSPEED_AN_100_EN BIT(11)
+#define ADIN1300_DOWNSPEED_AN_10_EN BIT(10)
+#define ADIN1300_GROUP_MDIO_EN BIT(6)
+#define ADIN1300_DOWNSPEEDS_EN \
+ (ADIN1300_DOWNSPEED_AN_100_EN | ADIN1300_DOWNSPEED_AN_10_EN)
+
#define ADIN1300_INT_MASK_REG 0x0018
#define ADIN1300_INT_MDIO_SYNC_EN BIT(9)
#define ADIN1300_INT_ANEG_STAT_CHNG_EN BIT(8)
@@ -425,6 +432,22 @@ static int adin_config_mdix(struct phy_device *phydev)
return phy_write(phydev, ADIN1300_PHY_CTRL1, reg);
}
+static int adin_config_downspeeds(struct phy_device *phydev)
+{
+ int reg;
+
+ reg = phy_read(phydev, ADIN1300_PHY_CTRL2);
+ if (reg < 0)
+ return reg;
+
+ if ((reg & ADIN1300_DOWNSPEEDS_EN) == ADIN1300_DOWNSPEEDS_EN)
+ return 0;
+
+ reg |= ADIN1300_DOWNSPEEDS_EN;
+
+ return phy_write(phydev, ADIN1300_PHY_CTRL2, reg);
+}
+
static int adin_config_aneg(struct phy_device *phydev)
{
int ret;
@@ -433,6 +456,10 @@ static int adin_config_aneg(struct phy_device *phydev)
if (ret)
return ret;
+ ret = adin_config_downspeeds(phydev);
+ if (ret < 0)
+ return ret;
+
return genphy_config_aneg(phydev);
}
--
2.20.1
^ permalink raw reply related
* [PATCH 13/16] net: phy: adin: implement Energy Detect Powerdown mode
From: Alexandru Ardelean @ 2019-08-05 16:54 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel
Cc: davem, robh+dt, mark.rutland, f.fainelli, hkallweit1, andrew,
Alexandru Ardelean
In-Reply-To: <20190805165453.3989-1-alexandru.ardelean@analog.com>
The ADIN PHYs support Energy Detect Powerdown mode, which puts the PHY into
a low power mode when there is no signal on the wire (typically cable
unplugged).
This behavior is enabled by default, but can be disabled via device
property.
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
drivers/net/phy/adin.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
index cf99ccacfeeb..86848444bd98 100644
--- a/drivers/net/phy/adin.c
+++ b/drivers/net/phy/adin.c
@@ -27,6 +27,11 @@
#define ADIN1300_AUTO_MDI_EN BIT(10)
#define ADIN1300_MAN_MDIX_EN BIT(9)
+#define ADIN1300_PHY_CTRL_STATUS2 0x0015
+#define ADIN1300_NRG_PD_EN BIT(3)
+#define ADIN1300_NRG_PD_TX_EN BIT(2)
+#define ADIN1300_NRG_PD_STATUS BIT(1)
+
#define ADIN1300_INT_MASK_REG 0x0018
#define ADIN1300_INT_MDIO_SYNC_EN BIT(9)
#define ADIN1300_INT_ANEG_STAT_CHNG_EN BIT(8)
@@ -95,10 +100,12 @@ static struct clause22_mmd_map clause22_mmd_map[] = {
* struct adin_priv - ADIN PHY driver private data
* gpiod_reset optional reset GPIO, to be used in soft_reset() cb
* eee_modes EEE modes to advertise after reset
+ * edpd_enabled true if Energy Detect Powerdown mode is enabled
*/
struct adin_priv {
struct gpio_desc *gpiod_reset;
u8 eee_modes;
+ bool edpd_enabled;
};
static int adin_get_phy_internal_mode(struct phy_device *phydev)
@@ -235,6 +242,18 @@ static int adin_config_init_eee(struct phy_device *phydev)
return phy_write_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_EEE_ADV_REG, reg);
}
+static int adin_config_init_edpd(struct phy_device *phydev)
+{
+ struct adin_priv *priv = phydev->priv;
+
+ if (priv->edpd_enabled)
+ return phy_set_bits(phydev, ADIN1300_PHY_CTRL_STATUS2,
+ (ADIN1300_NRG_PD_EN | ADIN1300_NRG_PD_TX_EN));
+
+ return phy_clear_bits(phydev, ADIN1300_PHY_CTRL_STATUS2,
+ (ADIN1300_NRG_PD_EN | ADIN1300_NRG_PD_TX_EN));
+}
+
static int adin_config_init(struct phy_device *phydev)
{
phy_interface_t interface, rc;
@@ -261,6 +280,10 @@ static int adin_config_init(struct phy_device *phydev)
if (rc < 0)
return rc;
+ rc = adin_config_init_edpd(phydev);
+ if (rc < 0)
+ return rc;
+
if (phydev->interface == interface)
dev_info(&phydev->mdio.dev, "PHY is using mode '%s'\n",
phy_modes(phydev->interface));
@@ -535,6 +558,10 @@ static int adin_probe(struct phy_device *phydev)
priv->gpiod_reset = gpiod_reset;
if (device_property_read_bool(dev, "adi,eee-enabled"))
priv->eee_modes = (MDIO_EEE_100TX | MDIO_EEE_1000T);
+ if (device_property_read_bool(dev, "adi,disable-energy-detect"))
+ priv->edpd_enabled = false;
+ else
+ priv->edpd_enabled = true;
phydev->priv = priv;
return adin_reset(phydev);
--
2.20.1
^ permalink raw reply related
* [PATCH 12/16] net: phy: adin: read EEE setting from device-tree
From: Alexandru Ardelean @ 2019-08-05 16:54 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel
Cc: davem, robh+dt, mark.rutland, f.fainelli, hkallweit1, andrew,
Alexandru Ardelean
In-Reply-To: <20190805165453.3989-1-alexandru.ardelean@analog.com>
By default, EEE is not advertised on system init. This change allows the
user to specify a device property to enable EEE advertisements when the PHY
initializes.
Also, before resetting the PHY, the EEE settings are read, so that after
the reset is complete, they are written back into the EEE advertisement
register.
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
drivers/net/phy/adin.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
index 476a81ce9341..cf99ccacfeeb 100644
--- a/drivers/net/phy/adin.c
+++ b/drivers/net/phy/adin.c
@@ -94,9 +94,11 @@ static struct clause22_mmd_map clause22_mmd_map[] = {
/**
* struct adin_priv - ADIN PHY driver private data
* gpiod_reset optional reset GPIO, to be used in soft_reset() cb
+ * eee_modes EEE modes to advertise after reset
*/
struct adin_priv {
struct gpio_desc *gpiod_reset;
+ u8 eee_modes;
};
static int adin_get_phy_internal_mode(struct phy_device *phydev)
@@ -216,6 +218,23 @@ static int adin_config_rmii_mode(struct phy_device *phydev,
ADIN1300_GE_RMII_CFG_REG, reg);
}
+static int adin_config_init_eee(struct phy_device *phydev)
+{
+ struct adin_priv *priv = phydev->priv;
+ int reg;
+
+ reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_EEE_ADV_REG);
+ if (reg < 0)
+ return reg;
+
+ if (priv->eee_modes)
+ reg |= priv->eee_modes;
+ else
+ reg &= ~(MDIO_EEE_100TX | MDIO_EEE_1000T);
+
+ return phy_write_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_EEE_ADV_REG, reg);
+}
+
static int adin_config_init(struct phy_device *phydev)
{
phy_interface_t interface, rc;
@@ -238,6 +257,10 @@ static int adin_config_init(struct phy_device *phydev)
if (rc < 0)
return rc;
+ rc = adin_config_init_eee(phydev);
+ if (rc < 0)
+ return rc;
+
if (phydev->interface == interface)
dev_info(&phydev->mdio.dev, "PHY is using mode '%s'\n",
phy_modes(phydev->interface));
@@ -473,6 +496,12 @@ static int adin_reset(struct phy_device *phydev)
struct adin_priv *priv = phydev->priv;
int ret;
+ /* Update EEE settings before resetting, in case ethtool changed them */
+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_EEE_ADV_REG);
+ if (ret < 0)
+ return ret;
+ priv->eee_modes = (ret & (MDIO_EEE_100TX | MDIO_EEE_1000T));
+
if (priv->gpiod_reset) {
/* GPIO reset requires min 10 uS low,
* 5 msecs max before we know that the interface is up again
@@ -504,6 +533,8 @@ static int adin_probe(struct phy_device *phydev)
gpiod_reset = NULL;
priv->gpiod_reset = gpiod_reset;
+ if (device_property_read_bool(dev, "adi,eee-enabled"))
+ priv->eee_modes = (MDIO_EEE_100TX | MDIO_EEE_1000T);
phydev->priv = priv;
return adin_reset(phydev);
--
2.20.1
^ permalink raw reply related
* [PATCH 11/16] net: phy: adin: PHY reset mechanisms
From: Alexandru Ardelean @ 2019-08-05 16:54 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel
Cc: davem, robh+dt, mark.rutland, f.fainelli, hkallweit1, andrew,
Alexandru Ardelean
In-Reply-To: <20190805165453.3989-1-alexandru.ardelean@analog.com>
The ADIN PHYs supports 4 types of reset:
1. The standard PHY reset via BMCR_RESET bit in MII_BMCR reg
2. Reset via GPIO
3. Reset via reg GeSftRst (0xff0c) & reload previous pin configs
4. Reset via reg GeSftRst (0xff0c) & request new pin configs
Resets 2 & 4 are almost identical, with the exception that the crystal
oscillator is available during reset for 2.
Resetting via GeSftRst or via GPIO is useful when doing a warm reboot. If
doing various settings via phytool or ethtool, the sub-system registers
don't reset just via BMCR_RESET.
This change implements resetting the entire PHY subsystem during probe.
During PHY HW init (phy_hw_init() logic) the PHY core regs will be reset
again via BMCR_RESET. This will also need to happen during a PM resume.
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
drivers/net/phy/adin.c | 82 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 82 insertions(+)
diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
index 3c559a3ba487..476a81ce9341 100644
--- a/drivers/net/phy/adin.c
+++ b/drivers/net/phy/adin.c
@@ -6,12 +6,14 @@
*/
#include <linux/kernel.h>
#include <linux/bitfield.h>
+#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/mii.h>
#include <linux/phy.h>
#include <linux/property.h>
+#include <linux/gpio/consumer.h>
#include <dt-bindings/net/adin.h>
@@ -55,6 +57,9 @@
#define ADIN1300_CLOCK_STOP_REG 0x9400
#define ADIN1300_LPI_WAKE_ERR_CNT_REG 0xa000
+#define ADIN1300_GE_SOFT_RESET_REG 0xff0c
+#define ADIN1300_GE_SOFT_RESET BIT(0)
+
#define ADIN1300_GE_RGMII_CFG_REG 0xff23
#define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6)
#define ADIN1300_GE_RGMII_RX_SEL(x) \
@@ -86,6 +91,14 @@ static struct clause22_mmd_map clause22_mmd_map[] = {
{ MDIO_MMD_PCS, MDIO_PCS_EEE_WK_ERR, ADIN1300_LPI_WAKE_ERR_CNT_REG },
};
+/**
+ * struct adin_priv - ADIN PHY driver private data
+ * gpiod_reset optional reset GPIO, to be used in soft_reset() cb
+ */
+struct adin_priv {
+ struct gpio_desc *gpiod_reset;
+};
+
static int adin_get_phy_internal_mode(struct phy_device *phydev)
{
struct device *dev = &phydev->mdio.dev;
@@ -429,6 +442,73 @@ static int adin_read_status(struct phy_device *phydev)
return genphy_read_status(phydev);
}
+static int adin_subsytem_soft_reset(struct phy_device *phydev)
+{
+ int reg, rc, i;
+
+ reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_SOFT_RESET_REG);
+ if (reg < 0)
+ return reg;
+
+ reg |= ADIN1300_GE_SOFT_RESET;
+ rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_SOFT_RESET_REG,
+ reg);
+ if (rc < 0)
+ return rc;
+
+ for (i = 0; i < 20; i++) {
+ usleep_range(500, 1000);
+ reg = phy_read_mmd(phydev, MDIO_MMD_VEND1,
+ ADIN1300_GE_SOFT_RESET_REG);
+ if (reg < 0 || (reg & ADIN1300_GE_SOFT_RESET))
+ continue;
+ return 0;
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int adin_reset(struct phy_device *phydev)
+{
+ struct adin_priv *priv = phydev->priv;
+ int ret;
+
+ if (priv->gpiod_reset) {
+ /* GPIO reset requires min 10 uS low,
+ * 5 msecs max before we know that the interface is up again
+ */
+ gpiod_set_value(priv->gpiod_reset, 0);
+ usleep_range(10, 15);
+ gpiod_set_value(priv->gpiod_reset, 1);
+ mdelay(5);
+
+ return 0;
+ }
+
+ /* Reset PHY core regs & subsystem regs */
+ return adin_subsytem_soft_reset(phydev);
+}
+
+static int adin_probe(struct phy_device *phydev)
+{
+ struct device *dev = &phydev->mdio.dev;
+ struct gpio_desc *gpiod_reset;
+ struct adin_priv *priv;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ gpiod_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(gpiod_reset))
+ gpiod_reset = NULL;
+
+ priv->gpiod_reset = gpiod_reset;
+ phydev->priv = priv;
+
+ return adin_reset(phydev);
+}
+
static struct phy_driver adin_driver[] = {
{
.phy_id = PHY_ID_ADIN1200,
@@ -437,6 +517,7 @@ static struct phy_driver adin_driver[] = {
.features = PHY_BASIC_FEATURES,
.flags = PHY_HAS_INTERRUPT,
.config_init = adin_config_init,
+ .probe = adin_probe,
.config_aneg = adin_config_aneg,
.read_status = adin_read_status,
.ack_interrupt = adin_phy_ack_intr,
@@ -453,6 +534,7 @@ static struct phy_driver adin_driver[] = {
.features = PHY_GBIT_FEATURES,
.flags = PHY_HAS_INTERRUPT,
.config_init = adin_config_init,
+ .probe = adin_probe,
.config_aneg = adin_config_aneg,
.read_status = adin_read_status,
.ack_interrupt = adin_phy_ack_intr,
--
2.20.1
^ permalink raw reply related
* [PATCH 10/16] net: phy: adin: add EEE translation layer for Clause 22
From: Alexandru Ardelean @ 2019-08-05 16:54 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel
Cc: davem, robh+dt, mark.rutland, f.fainelli, hkallweit1, andrew,
Alexandru Ardelean
In-Reply-To: <20190805165453.3989-1-alexandru.ardelean@analog.com>
The ADIN1200 & ADIN1300 PHYs support EEE by using standard Clause 45 access
to access MMD registers for EEE.
The EEE register addresses (when using Clause 22) are available at
different addresses (than Clause 45), and since accessing these regs (via
Clause 22) needs a special mechanism, a translation table is required to
convert these addresses.
For Clause 45, this is not needed; the addresses are available as specified
by IEEE.
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
drivers/net/phy/adin.c | 61 ++++++++++++++++++++++++++++++++++++++++--
1 file changed, 59 insertions(+), 2 deletions(-)
diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
index 31c600b7ec66..3c559a3ba487 100644
--- a/drivers/net/phy/adin.c
+++ b/drivers/net/phy/adin.c
@@ -44,6 +44,17 @@
#define ADIN1300_PHY_STATUS1 0x001a
#define ADIN1300_PAIR_01_SWAP BIT(11)
+/* EEE register addresses, accessible via Clause 22 access using
+ * ADIN1300_MII_EXT_REG_PTR & ADIN1300_MII_EXT_REG_DATA.
+ * The bit-fields are the same as specified by IEEE, and can be
+ * accessed via standard Clause 45 access.
+ */
+#define ADIN1300_EEE_CAP_REG 0x8000
+#define ADIN1300_EEE_ADV_REG 0x8001
+#define ADIN1300_EEE_LPABLE_REG 0x8002
+#define ADIN1300_CLOCK_STOP_REG 0x9400
+#define ADIN1300_LPI_WAKE_ERR_CNT_REG 0xa000
+
#define ADIN1300_GE_RGMII_CFG_REG 0xff23
#define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6)
#define ADIN1300_GE_RGMII_RX_SEL(x) \
@@ -61,6 +72,20 @@
FIELD_PREP(ADIN1300_GE_RMII_FIFO_DEPTH_MSK, x)
#define ADIN1300_GE_RMII_EN BIT(0)
+struct clause22_mmd_map {
+ int devad;
+ u16 cl22_regnum;
+ u16 adin_regnum;
+};
+
+static struct clause22_mmd_map clause22_mmd_map[] = {
+ { MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE, ADIN1300_EEE_CAP_REG },
+ { MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, ADIN1300_EEE_LPABLE_REG },
+ { MDIO_MMD_AN, MDIO_AN_EEE_ADV, ADIN1300_EEE_ADV_REG },
+ { MDIO_MMD_PCS, MDIO_CTRL1, ADIN1300_CLOCK_STOP_REG },
+ { MDIO_MMD_PCS, MDIO_PCS_EEE_WK_ERR, ADIN1300_LPI_WAKE_ERR_CNT_REG },
+};
+
static int adin_get_phy_internal_mode(struct phy_device *phydev)
{
struct device *dev = &phydev->mdio.dev;
@@ -233,10 +258,31 @@ static int adin_phy_config_intr(struct phy_device *phydev)
ADIN1300_INT_MASK_EN);
}
+static int adin_cl22_to_adin_reg(int devad, u16 cl22_regnum)
+{
+ struct clause22_mmd_map *m;
+ int i;
+
+ if (devad == MDIO_MMD_VEND1)
+ return cl22_regnum;
+
+ for (i = 0; i < ARRAY_SIZE(clause22_mmd_map); i++) {
+ m = &clause22_mmd_map[i];
+ if (m->devad == devad && m->cl22_regnum == cl22_regnum)
+ return m->adin_regnum;
+ }
+
+ pr_err("No translation available for devad: %d reg: %04x\n",
+ devad, cl22_regnum);
+
+ return -EINVAL;
+}
+
static int adin_read_mmd(struct phy_device *phydev, int devad, u16 regnum)
{
struct mii_bus *bus = phydev->mdio.bus;
int phy_addr = phydev->mdio.addr;
+ int adin_regnum;
int err;
if (phydev->is_c45) {
@@ -245,7 +291,12 @@ static int adin_read_mmd(struct phy_device *phydev, int devad, u16 regnum)
return __mdiobus_read(bus, phy_addr, addr);
}
- err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR, regnum);
+ adin_regnum = adin_cl22_to_adin_reg(devad, regnum);
+ if (adin_regnum < 0)
+ return adin_regnum;
+
+ err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR,
+ adin_regnum);
if (err)
return err;
@@ -257,6 +308,7 @@ static int adin_write_mmd(struct phy_device *phydev, int devad, u16 regnum,
{
struct mii_bus *bus = phydev->mdio.bus;
int phy_addr = phydev->mdio.addr;
+ int adin_regnum;
int err;
if (phydev->is_c45) {
@@ -265,7 +317,12 @@ static int adin_write_mmd(struct phy_device *phydev, int devad, u16 regnum,
return __mdiobus_write(bus, phy_addr, addr, val);
}
- err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR, regnum);
+ adin_regnum = adin_cl22_to_adin_reg(devad, regnum);
+ if (adin_regnum < 0)
+ return adin_regnum;
+
+ err = __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_PTR,
+ adin_regnum);
if (err)
return err;
--
2.20.1
^ permalink raw reply related
* [PATCH 09/16] net: phy: adin: add support MDI/MDIX/Auto-MDI selection
From: Alexandru Ardelean @ 2019-08-05 16:54 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel
Cc: davem, robh+dt, mark.rutland, f.fainelli, hkallweit1, andrew,
Alexandru Ardelean
In-Reply-To: <20190805165453.3989-1-alexandru.ardelean@analog.com>
The ADIN PHYs support automatic MDI/MDIX negotiation. By default this is
disabled, so this is enabled at `config_init`.
This is controlled via the PHY Control 1 register.
The supported modes are:
1. Manual MDI
2. Manual MDIX
3. Auto MDIX - prefer MDIX
4. Auto MDIX - prefer MDI
The phydev mdix & mdix_ctrl fields include modes 3 & 4 into a single
auto-mode. So, the default mode this driver enables is 4 when Auto-MDI mode
is used.
When detecting MDI/MDIX mode, a combination of the PHY Control 1 register
and PHY Status 1 register is used to determine the correct MDI/MDIX mode.
If Auto-MDI mode is not set, then the manual MDI/MDIX mode is returned.
If Auto-MDI mode is set, then MDIX mode is returned differs from the
preferred MDI/MDIX mode.
This covers all cases where:
1. MDI preferred & Pair01Swapped == MDIX
2. MDIX preferred & Pair01Swapped == MDI
3. MDI preferred & ! Pair01Swapped == MDIX
4. MDIX preferred & ! Pair01Swapped == MDI
The preferred MDI/MDIX mode is not configured via SW, but can be configured
via HW pins. Note that the `Pair01Swapped` is the Green-Yellow physical
pairs.
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
drivers/net/phy/adin.c | 117 +++++++++++++++++++++++++++++++++++++++--
1 file changed, 113 insertions(+), 4 deletions(-)
diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
index 2e27ffd403b4..31c600b7ec66 100644
--- a/drivers/net/phy/adin.c
+++ b/drivers/net/phy/adin.c
@@ -21,6 +21,10 @@
#define ADIN1300_MII_EXT_REG_PTR 0x10
#define ADIN1300_MII_EXT_REG_DATA 0x11
+#define ADIN1300_PHY_CTRL1 0x0012
+#define ADIN1300_AUTO_MDI_EN BIT(10)
+#define ADIN1300_MAN_MDIX_EN BIT(9)
+
#define ADIN1300_INT_MASK_REG 0x0018
#define ADIN1300_INT_MDIO_SYNC_EN BIT(9)
#define ADIN1300_INT_ANEG_STAT_CHNG_EN BIT(8)
@@ -37,6 +41,9 @@
ADIN1300_INT_HW_IRQ_EN)
#define ADIN1300_INT_STATUS_REG 0x0019
+#define ADIN1300_PHY_STATUS1 0x001a
+#define ADIN1300_PAIR_01_SWAP BIT(11)
+
#define ADIN1300_GE_RGMII_CFG_REG 0xff23
#define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6)
#define ADIN1300_GE_RGMII_RX_SEL(x) \
@@ -175,6 +182,8 @@ static int adin_config_init(struct phy_device *phydev)
{
phy_interface_t interface, rc;
+ phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
+
rc = genphy_config_init(phydev);
if (rc < 0)
return rc;
@@ -263,6 +272,106 @@ static int adin_write_mmd(struct phy_device *phydev, int devad, u16 regnum,
return __mdiobus_write(bus, phy_addr, ADIN1300_MII_EXT_REG_DATA, val);
}
+static int adin_config_mdix(struct phy_device *phydev)
+{
+ bool auto_en, mdix_en;
+ int reg;
+
+ mdix_en = false;
+ auto_en = false;
+ switch (phydev->mdix_ctrl) {
+ case ETH_TP_MDI:
+ break;
+ case ETH_TP_MDI_X:
+ mdix_en = true;
+ break;
+ case ETH_TP_MDI_AUTO:
+ auto_en = true;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ reg = phy_read(phydev, ADIN1300_PHY_CTRL1);
+ if (reg < 0)
+ return reg;
+
+ if (mdix_en)
+ reg |= ADIN1300_MAN_MDIX_EN;
+ else
+ reg &= ~ADIN1300_MAN_MDIX_EN;
+
+ if (auto_en)
+ reg |= ADIN1300_AUTO_MDI_EN;
+ else
+ reg &= ~ADIN1300_AUTO_MDI_EN;
+
+ return phy_write(phydev, ADIN1300_PHY_CTRL1, reg);
+}
+
+static int adin_config_aneg(struct phy_device *phydev)
+{
+ int ret;
+
+ ret = adin_config_mdix(phydev);
+ if (ret)
+ return ret;
+
+ return genphy_config_aneg(phydev);
+}
+
+static int adin_mdix_update(struct phy_device *phydev)
+{
+ bool auto_en, mdix_en;
+ bool swapped;
+ int reg;
+
+ reg = phy_read(phydev, ADIN1300_PHY_CTRL1);
+ if (reg < 0)
+ return reg;
+
+ auto_en = !!(reg & ADIN1300_AUTO_MDI_EN);
+ mdix_en = !!(reg & ADIN1300_MAN_MDIX_EN);
+
+ /* If MDI/MDIX is forced, just read it from the control reg */
+ if (!auto_en) {
+ if (mdix_en)
+ phydev->mdix = ETH_TP_MDI_X;
+ else
+ phydev->mdix = ETH_TP_MDI;
+ return 0;
+ }
+
+ /**
+ * Otherwise, we need to deduce it from the PHY status2 reg.
+ * When Auto-MDI is enabled, the ADIN1300_MAN_MDIX_EN bit implies
+ * a preference for MDIX when it is set.
+ */
+ reg = phy_read(phydev, ADIN1300_PHY_STATUS1);
+ if (reg < 0)
+ return reg;
+
+ swapped = !!(reg & ADIN1300_PAIR_01_SWAP);
+
+ if (mdix_en != swapped)
+ phydev->mdix = ETH_TP_MDI_X;
+ else
+ phydev->mdix = ETH_TP_MDI;
+
+ return 0;
+}
+
+static int adin_read_status(struct phy_device *phydev)
+{
+ int ret;
+
+ ret = adin_mdix_update(phydev);
+ if (ret < 0)
+ return ret;
+
+ return genphy_read_status(phydev);
+}
+
static struct phy_driver adin_driver[] = {
{
.phy_id = PHY_ID_ADIN1200,
@@ -271,8 +380,8 @@ static struct phy_driver adin_driver[] = {
.features = PHY_BASIC_FEATURES,
.flags = PHY_HAS_INTERRUPT,
.config_init = adin_config_init,
- .config_aneg = genphy_config_aneg,
- .read_status = genphy_read_status,
+ .config_aneg = adin_config_aneg,
+ .read_status = adin_read_status,
.ack_interrupt = adin_phy_ack_intr,
.config_intr = adin_phy_config_intr,
.resume = genphy_resume,
@@ -287,8 +396,8 @@ static struct phy_driver adin_driver[] = {
.features = PHY_GBIT_FEATURES,
.flags = PHY_HAS_INTERRUPT,
.config_init = adin_config_init,
- .config_aneg = genphy_config_aneg,
- .read_status = genphy_read_status,
+ .config_aneg = adin_config_aneg,
+ .read_status = adin_read_status,
.ack_interrupt = adin_phy_ack_intr,
.config_intr = adin_phy_config_intr,
.resume = genphy_resume,
--
2.20.1
^ permalink raw reply related
* [PATCH 08/16] net: phy: adin: make RMII fifo depth configurable
From: Alexandru Ardelean @ 2019-08-05 16:54 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel
Cc: davem, robh+dt, mark.rutland, f.fainelli, hkallweit1, andrew,
Alexandru Ardelean
In-Reply-To: <20190805165453.3989-1-alexandru.ardelean@analog.com>
The FIFO depth can be configured for the RMII mode. This change adds
support for doing this via device-tree (or ACPI).
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
drivers/net/phy/adin.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
index cb96d47d457e..2e27ffd403b4 100644
--- a/drivers/net/phy/adin.c
+++ b/drivers/net/phy/adin.c
@@ -49,6 +49,9 @@
#define ADIN1300_GE_RGMII_EN BIT(0)
#define ADIN1300_GE_RMII_CFG_REG 0xff24
+#define ADIN1300_GE_RMII_FIFO_DEPTH_MSK GENMASK(6, 4)
+#define ADIN1300_GE_RMII_FIFO_DEPTH_SEL(x) \
+ FIELD_PREP(ADIN1300_GE_RMII_FIFO_DEPTH_MSK, x)
#define ADIN1300_GE_RMII_EN BIT(0)
static int adin_get_phy_internal_mode(struct phy_device *phydev)
@@ -142,6 +145,8 @@ static int adin_config_rgmii_mode(struct phy_device *phydev,
static int adin_config_rmii_mode(struct phy_device *phydev,
phy_interface_t intf)
{
+ struct device *dev = &phydev->mdio.dev;
+ u32 val;
int reg;
reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG);
@@ -155,6 +160,12 @@ static int adin_config_rmii_mode(struct phy_device *phydev,
reg |= ADIN1300_GE_RMII_EN;
+ if (device_property_read_u32(dev, "adi,fifo-depth", &val))
+ val = ADIN1300_RMII_8_BITS;
+
+ reg &= ~ADIN1300_GE_RMII_FIFO_DEPTH_MSK;
+ reg |= ADIN1300_GE_RMII_FIFO_DEPTH_SEL(val);
+
write:
return phy_write_mmd(phydev, MDIO_MMD_VEND1,
ADIN1300_GE_RMII_CFG_REG, reg);
--
2.20.1
^ permalink raw reply related
* [PATCH 07/16] net: phy: adin: make RGMII internal delays configurable
From: Alexandru Ardelean @ 2019-08-05 16:54 UTC (permalink / raw)
To: netdev, devicetree, linux-kernel
Cc: davem, robh+dt, mark.rutland, f.fainelli, hkallweit1, andrew,
Alexandru Ardelean
In-Reply-To: <20190805165453.3989-1-alexandru.ardelean@analog.com>
The internal delays for the RGMII are configurable for both RX & TX. This
change adds support for configuring them via device-tree (or ACPI).
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
---
drivers/net/phy/adin.c | 37 +++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
index e3d2ff8cc09c..cb96d47d457e 100644
--- a/drivers/net/phy/adin.c
+++ b/drivers/net/phy/adin.c
@@ -5,6 +5,7 @@
* Copyright 2019 Analog Devices Inc.
*/
#include <linux/kernel.h>
+#include <linux/bitfield.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/module.h>
@@ -12,6 +13,8 @@
#include <linux/phy.h>
#include <linux/property.h>
+#include <dt-bindings/net/adin.h>
+
#define PHY_ID_ADIN1200 0x0283bc20
#define PHY_ID_ADIN1300 0x0283bc30
@@ -35,6 +38,12 @@
#define ADIN1300_INT_STATUS_REG 0x0019
#define ADIN1300_GE_RGMII_CFG_REG 0xff23
+#define ADIN1300_GE_RGMII_RX_MSK GENMASK(8, 6)
+#define ADIN1300_GE_RGMII_RX_SEL(x) \
+ FIELD_PREP(ADIN1300_GE_RGMII_RX_MSK, x)
+#define ADIN1300_GE_RGMII_GTX_MSK GENMASK(5, 3)
+#define ADIN1300_GE_RGMII_GTX_SEL(x) \
+ FIELD_PREP(ADIN1300_GE_RGMII_GTX_MSK, x)
#define ADIN1300_GE_RGMII_RXID_EN BIT(2)
#define ADIN1300_GE_RGMII_TXID_EN BIT(1)
#define ADIN1300_GE_RGMII_EN BIT(0)
@@ -67,6 +76,32 @@ static int adin_get_phy_internal_mode(struct phy_device *phydev)
return -EINVAL;
}
+static void adin_config_rgmii_rx_internal_delay(struct phy_device *phydev,
+ int *reg)
+{
+ struct device *dev = &phydev->mdio.dev;
+ u32 val;
+
+ if (device_property_read_u32(dev, "adi,rx-internal-delay", &val))
+ val = ADIN1300_RGMII_2_00_NS;
+
+ *reg &= ADIN1300_GE_RGMII_RX_MSK;
+ *reg |= ADIN1300_GE_RGMII_RX_SEL(val);
+}
+
+static void adin_config_rgmii_tx_internal_delay(struct phy_device *phydev,
+ int *reg)
+{
+ struct device *dev = &phydev->mdio.dev;
+ u32 val;
+
+ if (device_property_read_u32(dev, "adi,tx-internal-delay", &val))
+ val = ADIN1300_RGMII_2_00_NS;
+
+ *reg &= ADIN1300_GE_RGMII_GTX_MSK;
+ *reg |= ADIN1300_GE_RGMII_GTX_SEL(val);
+}
+
static int adin_config_rgmii_mode(struct phy_device *phydev,
phy_interface_t intf)
{
@@ -86,6 +121,7 @@ static int adin_config_rgmii_mode(struct phy_device *phydev,
if (intf == PHY_INTERFACE_MODE_RGMII_ID ||
intf == PHY_INTERFACE_MODE_RGMII_RXID) {
reg |= ADIN1300_GE_RGMII_RXID_EN;
+ adin_config_rgmii_rx_internal_delay(phydev, ®);
} else {
reg &= ~ADIN1300_GE_RGMII_RXID_EN;
}
@@ -93,6 +129,7 @@ static int adin_config_rgmii_mode(struct phy_device *phydev,
if (intf == PHY_INTERFACE_MODE_RGMII_ID ||
intf == PHY_INTERFACE_MODE_RGMII_TXID) {
reg |= ADIN1300_GE_RGMII_TXID_EN;
+ adin_config_rgmii_tx_internal_delay(phydev, ®);
} else {
reg &= ~ADIN1300_GE_RGMII_TXID_EN;
}
--
2.20.1
^ permalink raw reply related
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