* [PATCH v3] arm64: dts: ls1028a: Add temperature sensor node
From: Yuantian Tang @ 2019-08-06 5:30 UTC (permalink / raw)
To: shawnguo
Cc: leoyang.li, robh+dt, mark.rutland, linux-arm-kernel, devicetree,
linux-kernel, Yuantian Tang
Add nxp sa56004 chip node for temperature monitor.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
---
v3:
- sort the node in i2c address
v2:
- change the node name and add vcc-supply
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 15 +++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 15 +++++++++++++++
2 files changed, 30 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index b359068..960daf2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -47,6 +47,15 @@
regulator-always-on;
};
+ sb_3v3: regulator-sb3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3_vbus";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
@@ -117,6 +126,12 @@
#size-cells = <0>;
reg = <0x3>;
+ temperature-sensor@4c {
+ compatible = "nxp,sa56004";
+ reg = <0x4c>;
+ vcc-supply = <&sb_3v3>;
+ };
+
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index f9c272f..6a22423 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -43,6 +43,15 @@
regulator-always-on;
};
+ sb_3v3: regulator-sb3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3_vbus";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
@@ -115,6 +124,12 @@
#size-cells = <0>;
reg = <0x3>;
+ temperature-sensor@4c {
+ compatible = "nxp,sa56004";
+ reg = <0x4c>;
+ vcc-supply = <&sb_3v3>;
+ };
+
rtc@51 {
compatible = "nxp,pcf2129";
reg = <0x51>;
--
1.7.1
^ permalink raw reply related
* [PATCH v2] arm64: dts: ls1028a: Add Thermal Monitor Unit node
From: Yuantian Tang @ 2019-08-06 5:35 UTC (permalink / raw)
To: shawnguo
Cc: leoyang.li, robh+dt, mark.rutland, linux-arm-kernel, devicetree,
linux-kernel, Yuantian Tang
The Thermal Monitoring Unit (TMU) monitors and reports the
temperature from 2 remote temperature measurement sites
located on ls1028a chip.
Add TMU dts node to enable this feature.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
---
v2:
- remove multiple sensors support
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 85 +++++++++++++++++++
1 file changed, 85 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index aef5b06a98d5..20d7e7db5dcb 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -29,6 +29,7 @@
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PW20>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -39,6 +40,7 @@
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PW20>;
+ #cooling-cells = <2>;
};
l2: l2-cache {
@@ -503,6 +505,89 @@
status = "disabled";
};
+ tmu: tmu@1f00000 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f80000 0x0 0x10000>;
+ interrupts = <0 23 0x4>;
+ fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
+ fsl,tmu-calibration = <0x00000000 0x00000024
+ 0x00000001 0x0000002b
+ 0x00000002 0x00000031
+ 0x00000003 0x00000038
+ 0x00000004 0x0000003f
+ 0x00000005 0x00000045
+ 0x00000006 0x0000004c
+ 0x00000007 0x00000053
+ 0x00000008 0x00000059
+ 0x00000009 0x00000060
+ 0x0000000a 0x00000066
+ 0x0000000b 0x0000006d
+
+ 0x00010000 0x0000001c
+ 0x00010001 0x00000024
+ 0x00010002 0x0000002c
+ 0x00010003 0x00000035
+ 0x00010004 0x0000003d
+ 0x00010005 0x00000045
+ 0x00010006 0x0000004d
+ 0x00010007 0x00000045
+ 0x00010008 0x0000005e
+ 0x00010009 0x00000066
+ 0x0001000a 0x0000006e
+
+ 0x00020000 0x00000018
+ 0x00020001 0x00000022
+ 0x00020002 0x0000002d
+ 0x00020003 0x00000038
+ 0x00020004 0x00000043
+ 0x00020005 0x0000004d
+ 0x00020006 0x00000058
+ 0x00020007 0x00000063
+ 0x00020008 0x0000006e
+
+ 0x00030000 0x00000010
+ 0x00030001 0x0000001c
+ 0x00030002 0x00000029
+ 0x00030003 0x00000036
+ 0x00030004 0x00000042
+ 0x00030005 0x0000004f
+ 0x00030006 0x0000005b
+ 0x00030007 0x00000068>;
+ little-endian;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ core-cluster {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 0>;
+
+ trips {
+ core_cluster_alert: core-cluster-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ core_cluster_crit: core-cluster-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&core_cluster_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
pcie@1f0000000 { /* Integrated Endpoint Root Complex */
compatible = "pci-host-ecam-generic";
reg = <0x01 0xf0000000 0x0 0x100000>;
--
2.17.1
^ permalink raw reply related
* RE: [PATCH v3] arm64: dts: ls1028a: Add temperature sensor node
From: Andy Tang @ 2019-08-06 5:41 UTC (permalink / raw)
To: Andy Tang, shawnguo@kernel.org
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Leo Li, robh+dt@kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190806053004.36956-1-andy.tang@nxp.com>
Please ignore this email. Sorry for sending the wrong patch.
BR,
Andy
> -----Original Message-----
> From: Yuantian Tang <andy.tang@nxp.com>
> Sent: 2019年8月6日 13:30
> To: shawnguo@kernel.org
> Cc: Leo Li <leoyang.li@nxp.com>; robh+dt@kernel.org;
> mark.rutland@arm.com; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Andy Tang
> <andy.tang@nxp.com>
> Subject: [PATCH v3] arm64: dts: ls1028a: Add temperature sensor node
>
> Add nxp sa56004 chip node for temperature monitor.
>
> Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
> ---
> v3:
> - sort the node in i2c address
> v2:
> - change the node name and add vcc-supply
> arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 15
> +++++++++++++++
> arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 15
> +++++++++++++++
> 2 files changed, 30 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> index b359068..960daf2 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> @@ -47,6 +47,15 @@
> regulator-always-on;
> };
>
> + sb_3v3: regulator-sb3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "3v3_vbus";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> sound {
> compatible = "simple-audio-card";
> simple-audio-card,format = "i2s";
> @@ -117,6 +126,12 @@
> #size-cells = <0>;
> reg = <0x3>;
>
> + temperature-sensor@4c {
> + compatible = "nxp,sa56004";
> + reg = <0x4c>;
> + vcc-supply = <&sb_3v3>;
> + };
> +
> rtc@51 {
> compatible = "nxp,pcf2129";
> reg = <0x51>;
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> index f9c272f..6a22423 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> @@ -43,6 +43,15 @@
> regulator-always-on;
> };
>
> + sb_3v3: regulator-sb3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "3v3_vbus";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> sound {
> compatible = "simple-audio-card";
> simple-audio-card,format = "i2s";
> @@ -115,6 +124,12 @@
> #size-cells = <0>;
> reg = <0x3>;
>
> + temperature-sensor@4c {
> + compatible = "nxp,sa56004";
> + reg = <0x4c>;
> + vcc-supply = <&sb_3v3>;
> + };
> +
> rtc@51 {
> compatible = "nxp,pcf2129";
> reg = <0x51>;
> --
> 1.7.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* RE: [PATCH V4 1/4] dt-bindings: arm: imx: Add the soc binding for i.MX8MN
From: Anson Huang @ 2019-08-06 5:42 UTC (permalink / raw)
To: robh+dt@kernel.org, mark.rutland@arm.com, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
andrew.smirnov@gmail.com, manivannan.sadhasivam@linaro.org,
j.neuschaefer@gmx.net, u.kleine-koenig@pengutronix.de, Leo Li,
Aisheng Dong, l.stach@pengutronix.de, Vabhav Sharma,
Bhaskar Upadhaya, Jacky Bai, Pramod Kumar, Leonard Crestez,
Daniel Baluta, devicetree
Cc: dl-linux-imx
In-Reply-To: <20190619022145.42398-1-Anson.Huang@nxp.com>
Ping for this patch series...
> From: Anson Huang <Anson.Huang@nxp.com>
>
> This patch adds the soc & board binding for i.MX8MN.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> No change.
> ---
> Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml
> b/Documentation/devicetree/bindings/arm/fsl.yaml
> index 407138e..b35abb1 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> @@ -177,6 +177,12 @@ properties:
> - fsl,imx8mm-evk # i.MX8MM EVK Board
> - const: fsl,imx8mm
>
> + - description: i.MX8MN based Boards
> + items:
> + - enum:
> + - fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board
> + - const: fsl,imx8mn
> +
> - description: i.MX8QXP based Boards
> items:
> - enum:
> --
> 2.7.4
^ permalink raw reply
* RE: [PATCH V4 1/4] dt-bindings: arm: imx: Add the soc binding for i.MX8MN
From: Anson Huang @ 2019-08-06 5:42 UTC (permalink / raw)
To: robh+dt@kernel.org, mark.rutland@arm.com, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
andrew.smirnov@gmail.com, manivannan.sadhasivam@linaro.org,
j.neuschaefer@gmx.net, u.kleine-koenig@pengutronix.de, Leo Li,
Aisheng Dong, l.stach@pengutronix.de, Vabhav Sharma,
Bhaskar Upadhaya, Jacky Bai, Pramod Kumar, Leonard Crestez,
Daniel Baluta, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: dl-linux-imx
In-Reply-To: <20190619022145.42398-1-Anson.Huang@nxp.com>
Ping for this patch series...
> From: Anson Huang <Anson.Huang@nxp.com>
>
> This patch adds the soc & board binding for i.MX8MN.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> No change.
> ---
> Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml
> b/Documentation/devicetree/bindings/arm/fsl.yaml
> index 407138e..b35abb1 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> @@ -177,6 +177,12 @@ properties:
> - fsl,imx8mm-evk # i.MX8MM EVK Board
> - const: fsl,imx8mm
>
> + - description: i.MX8MN based Boards
> + items:
> + - enum:
> + - fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board
> + - const: fsl,imx8mn
> +
> - description: i.MX8QXP based Boards
> items:
> - enum:
> --
> 2.7.4
^ permalink raw reply
* Re: [RFC PATCH 1/2] dt-bindings: net: macb: Add new property for PS SGMII only
From: Harini Katakam @ 2019-08-06 5:47 UTC (permalink / raw)
To: Andrew Lunn
Cc: Harini Katakam, Nicolas Ferre, David Miller, Claudiu Beznea,
Rob Herring, Mark Rutland, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org, Michal Simek,
devicetree@vger.kernel.org
In-Reply-To: <20190805171639.GV24275@lunn.ch>
Hi Andrew,
On Mon, Aug 5, 2019 at 10:47 PM Andrew Lunn <andrew@lunn.ch> wrote:
>
> > Even with the use of this interrupt, the link status actions (link print and
> > netif ops) will still be required. And also the need for macb_open to
> > proceed without phydev. Could you please let me know if that is acceptable
> > to patch or if there's a cleaner way to
> > report this link status?
>
> It sounds like you need to convert to phylink, so you get full sfp
> support. phylib does not handle hotplug of PHYs.
>
> Please look at the comments Russell gave the last time this was
> attempted.
Yes, I looked at the comments from Russell and wasn't sure if this
case qualified for phylink.
Regards,
Harini
^ permalink raw reply
* Re: [PATCH 14/16] net: phy: adin: make sure down-speed auto-neg is enabled
From: Heiner Kallweit @ 2019-08-06 5:52 UTC (permalink / raw)
To: Alexandru Ardelean, netdev, devicetree, linux-kernel
Cc: davem, robh+dt, mark.rutland, f.fainelli, andrew
In-Reply-To: <20190805165453.3989-15-alexandru.ardelean@analog.com>
On 05.08.2019 18:54, Alexandru Ardelean wrote:
> Down-speed auto-negotiation may not always be enabled, in which case the
> PHY won't down-shift to 100 or 10 during auto-negotiation.
>
> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
> ---
> drivers/net/phy/adin.c | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
> index 86848444bd98..a1f3456a8504 100644
> --- a/drivers/net/phy/adin.c
> +++ b/drivers/net/phy/adin.c
> @@ -32,6 +32,13 @@
> #define ADIN1300_NRG_PD_TX_EN BIT(2)
> #define ADIN1300_NRG_PD_STATUS BIT(1)
>
> +#define ADIN1300_PHY_CTRL2 0x0016
> +#define ADIN1300_DOWNSPEED_AN_100_EN BIT(11)
> +#define ADIN1300_DOWNSPEED_AN_10_EN BIT(10)
> +#define ADIN1300_GROUP_MDIO_EN BIT(6)
> +#define ADIN1300_DOWNSPEEDS_EN \
> + (ADIN1300_DOWNSPEED_AN_100_EN | ADIN1300_DOWNSPEED_AN_10_EN)
> +
> #define ADIN1300_INT_MASK_REG 0x0018
> #define ADIN1300_INT_MDIO_SYNC_EN BIT(9)
> #define ADIN1300_INT_ANEG_STAT_CHNG_EN BIT(8)
> @@ -425,6 +432,22 @@ static int adin_config_mdix(struct phy_device *phydev)
> return phy_write(phydev, ADIN1300_PHY_CTRL1, reg);
> }
>
> +static int adin_config_downspeeds(struct phy_device *phydev)
> +{
> + int reg;
> +
> + reg = phy_read(phydev, ADIN1300_PHY_CTRL2);
> + if (reg < 0)
> + return reg;
> +
> + if ((reg & ADIN1300_DOWNSPEEDS_EN) == ADIN1300_DOWNSPEEDS_EN)
> + return 0;
> +
> + reg |= ADIN1300_DOWNSPEEDS_EN;
> +
> + return phy_write(phydev, ADIN1300_PHY_CTRL2, reg);
Using phy_set_bits() would be easier.
> +}
> +
> static int adin_config_aneg(struct phy_device *phydev)
> {
> int ret;
> @@ -433,6 +456,10 @@ static int adin_config_aneg(struct phy_device *phydev)
> if (ret)
> return ret;
>
> + ret = adin_config_downspeeds(phydev);
> + if (ret < 0)
> + return ret;
> +
> return genphy_config_aneg(phydev);
> }
>
>
^ permalink raw reply
* RE: [PATCH 1/2] dt-bindings: imx-ocotp: Add i.MX8MN compatible
From: Anson Huang @ 2019-08-06 5:59 UTC (permalink / raw)
To: srinivas.kandagatla@linaro.org, robh+dt@kernel.org,
mark.rutland@arm.com, shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Cc: dl-linux-imx
In-Reply-To: <20190711023714.16000-1-Anson.Huang@nxp.com>
Gentle Ping...
> From: Anson Huang <Anson.Huang@nxp.com>
>
> Add compatible for i.MX8MN and add i.MX8MM/i.MX8MN to the description.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> Documentation/devicetree/bindings/nvmem/imx-ocotp.txt | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
> b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
> index 96ffd06..904dadf 100644
> --- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
> +++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
> @@ -2,7 +2,7 @@ Freescale i.MX6 On-Chip OTP Controller (OCOTP) device
> tree bindings
>
> This binding represents the on-chip eFuse OTP controller found on
> i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL, i.MX6ULL/ULZ, i.MX6SLL, -
> i.MX7D/S, i.MX7ULP and i.MX8MQ SoCs.
> +i.MX7D/S, i.MX7ULP, i.MX8MQ, i.MX8MM and i.MX8MN SoCs.
>
> Required properties:
> - compatible: should be one of
> @@ -16,6 +16,7 @@ Required properties:
> "fsl,imx7ulp-ocotp" (i.MX7ULP),
> "fsl,imx8mq-ocotp" (i.MX8MQ),
> "fsl,imx8mm-ocotp" (i.MX8MM),
> + "fsl,imx8mn-ocotp" (i.MX8MN),
> followed by "syscon".
> - #address-cells : Should be 1
> - #size-cells : Should be 1
> --
> 2.7.4
^ permalink raw reply
* [PATCH v3 1/2] dt-bindings: pinctrl: qcom: Add SC7180 pinctrl binding
From: Rajendra Nayak @ 2019-08-06 6:05 UTC (permalink / raw)
To: linus.walleij, bjorn.andersson
Cc: linux-arm-msm, agross, robh+dt, linux-gpio, devicetree,
linux-kernel, Jitendra Sharma, Vivek Gautam, Rajendra Nayak,
Vinod Koul
From: Jitendra Sharma <shajit@codeaurora.org>
Add the binding for the TLMM pinctrl block found in the SC7180 platform
Signed-off-by: Jitendra Sharma <shajit@codeaurora.org>
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
[rnayak: Fix some copy-paste issues, sort and fix functions]
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
---
v3: Minor typo fixes as pointed out by Vinod on v2.
Added Vinods Reviewed-by:
.../bindings/pinctrl/qcom,sc7180-pinctrl.txt | 186 ++++++++++++++++++
1 file changed, 186 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt
new file mode 100644
index 000000000000..b5767ee82ee6
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7180-pinctrl.txt
@@ -0,0 +1,186 @@
+Qualcomm Technologies, Inc. SC7180 TLMM block
+
+This binding describes the Top Level Mode Multiplexer block found in the
+SC7180 platform.
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be "qcom,sc7180-pinctrl"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: the base address and size of the north, south and west
+ TLMM tiles
+
+- reg-names:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: names for the cells of reg, must contain "north", "south"
+ and "west".
+
+- interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: should specify the TLMM summary IRQ.
+
+- interrupt-controller:
+ Usage: required
+ Value type: <none>
+ Definition: identifies this node as an interrupt controller
+
+- #interrupt-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 2. Specifying the pin number and flags, as defined
+ in <dt-bindings/interrupt-controller/irq.h>
+
+- gpio-controller:
+ Usage: required
+ Value type: <none>
+ Definition: identifies this node as a gpio controller
+
+- #gpio-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 2. Specifying the pin number and flags, as defined
+ in <dt-bindings/gpio/gpio.h>
+
+- gpio-ranges:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: see ../gpio/gpio.txt
+
+- gpio-reserved-ranges:
+ Usage: optional
+ Value type: <prop-encoded-array>
+ Definition: see ../gpio/gpio.txt
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+
+PIN CONFIGURATION NODES:
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+
+- pins:
+ Usage: required
+ Value type: <string-array>
+ Definition: List of gpio pins affected by the properties specified in
+ this subnode.
+
+ Valid pins are:
+ gpio0-gpio118
+ Supports mux, bias and drive-strength
+
+ sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd,
+ sdc2_data sdc1_rclk
+ Supports bias and drive-strength
+
+ ufs_reset
+ Supports bias and drive-strength
+
+- function:
+ Usage: required
+ Value type: <string>
+ Definition: Specify the alternative function to be configured for the
+ specified pins. Functions are only valid for gpio pins.
+ Valid values are:
+
+ adsp_ext, agera_pll, aoss_cti, atest_char, atest_char0,
+ atest_char1, atest_char2, atest_char3, atest_tsens,
+ atest_tsens2, atest_usb1, atest_usb10, atest_usb11,
+ atest_usb12, atest_usb13, atest_usb2, atest_usb20,
+ atest_usb21, atest_usb22, atest_usb23, audio_ref,
+ btfm_slimbus, cam_mclk, cci_async, cci_i2c, cci_timer0,
+ cci_timer1, cci_timer2, cci_timer3, cci_timer4,
+ cri_trng, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
+ ddr_pxi2, ddr_pxi3, dp_hot, edp_lcd, gcc_gp1, gcc_gp2,
+ gcc_gp3, gpio, gp_pdm0, gp_pdm1, gp_pdm2, gps_tx,
+ jitter_bist, ldo_en, ldo_update, lpass_ext, mdp_vsync,
+ mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s_0,
+ mi2s_1, mi2s_2, mss_lte, m_voc, pa_indicator, phase_flag,
+ PLL_BIST, pll_bypassnl, pll_reset, prng_rosc, qdss,
+ qdss_cti, qlink_enable, qlink_request, qspi_clk, qspi_cs,
+ qspi_data, qup00, qup01, qup02, qup03, qup04, qup05,
+ qup10, qup11, qup12, qup13, qup14, qup15, sdc1_tb,
+ sdc2_tb, sd_write, sp_cmu, tgu_ch0, tgu_ch1, tgu_ch2,
+ tgu_ch3, tsense_pwm1, tsense_pwm2, uim1, uim2, uim_batt,
+ usb_phy, vfr_1, _V_GPIO, _V_PPS_IN, _V_PPS_OUT,
+ vsense_trigger, wlan1_adc0, wlan1_adc1, wlan2_adc0,
+ wlan2_adc1,
+
+- bias-disable:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configured as no pull.
+
+- bias-pull-down:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configured as pull down.
+
+- bias-pull-up:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configured as pull up.
+
+- output-high:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in output mode, driven
+ high.
+ Not valid for sdc pins.
+
+- output-low:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in output mode, driven
+ low.
+ Not valid for sdc pins.
+
+- drive-strength:
+ Usage: optional
+ Value type: <u32>
+ Definition: Selects the drive strength for the specified pins, in mA.
+ Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
+
+Example:
+
+ tlmm: pinctrl@3500000 {
+ compatible = "qcom,sc7180-pinctrl";
+ reg = <0x3500000 0x300000>,
+ <0x3900000 0x300000>,
+ <0x3D00000 0x300000>;
+ reg-names = "west", "north", "south";
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 119>;
+ gpio-reserved-ranges = <0 4>, <106 4>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v3 2/2] pinctrl: qcom: Add SC7180 pinctrl driver
From: Rajendra Nayak @ 2019-08-06 6:05 UTC (permalink / raw)
To: linus.walleij, bjorn.andersson
Cc: linux-arm-msm, agross, robh+dt, linux-gpio, devicetree,
linux-kernel, Jitendra Sharma, Vivek Gautam, Rajendra Nayak,
Vinod Koul
In-Reply-To: <20190806060536.18094-1-rnayak@codeaurora.org>
From: Jitendra Sharma <shajit@codeaurora.org>
Add initial pinctrl driver to support pin configuration with
pinctrl framework for SC7180
Signed-off-by: Jitendra Sharma <shajit@codeaurora.org>
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
[rnayak: modify to use upstream tile support
sort and squash some functions]
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
---
v3: No change since v2 except for adding Vinods Reviewed-by:
drivers/pinctrl/qcom/Kconfig | 9 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-sc7180.c | 1146 +++++++++++++++++++++++++
3 files changed, 1156 insertions(+)
create mode 100644 drivers/pinctrl/qcom/pinctrl-sc7180.c
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 8e14a5f2e970..af44dafc35e7 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -158,6 +158,15 @@ config PINCTRL_QCOM_SSBI_PMIC
which are using SSBI for communication with SoC. Example PMIC's
devices are pm8058 and pm8921.
+config PINCTRL_SC7180
+ tristate "Qualcomm Technologies Inc SC7180 pin controller driver"
+ depends on GPIOLIB && OF
+ select PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm Technologies Inc TLMM block found on the Qualcomm
+ Technologies Inc SC7180 platform.
+
config PINCTRL_SDM660
tristate "Qualcomm Technologies Inc SDM660 pin controller driver"
depends on GPIOLIB && OF
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index ebe906872272..f8bb0c265381 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-mpp.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-gpio.o
obj-$(CONFIG_PINCTRL_QCOM_SSBI_PMIC) += pinctrl-ssbi-mpp.o
+obj-$(CONFIG_PINCTRL_SC7180) += pinctrl-sc7180.o
obj-$(CONFIG_PINCTRL_SDM660) += pinctrl-sdm660.o
obj-$(CONFIG_PINCTRL_SDM845) += pinctrl-sdm845.o
obj-$(CONFIG_PINCTRL_SM8150) += pinctrl-sm8150.o
diff --git a/drivers/pinctrl/qcom/pinctrl-sc7180.c b/drivers/pinctrl/qcom/pinctrl-sc7180.c
new file mode 100644
index 000000000000..6399c8a2bc22
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-sc7180.c
@@ -0,0 +1,1146 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2019, The Linux Foundation. All rights reserved.
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-msm.h"
+
+static const char * const sc7180_tiles[] = {
+ "north",
+ "south",
+ "west",
+};
+
+enum {
+ NORTH,
+ SOUTH,
+ WEST
+};
+
+#define FUNCTION(fname) \
+ [msm_mux_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins, \
+ .npins = ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9 \
+ }, \
+ .nfuncs = 10, \
+ .ctl_reg = 0x1000 * id, \
+ .io_reg = 0x1000 * id + 0x4, \
+ .intr_cfg_reg = 0x1000 * id + 0x8, \
+ .intr_status_reg = 0x1000 * id + 0xc, \
+ .intr_target_reg = 0x1000 * id + 0x8, \
+ .tile = _tile, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9, \
+ .in_bit = 0, \
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_target_kpss_val = 3, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2, \
+ .intr_detection_width = 2, \
+ }
+
+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = ARRAY_SIZE(pg_name##_pins), \
+ .ctl_reg = ctl, \
+ .io_reg = 0, \
+ .intr_cfg_reg = 0, \
+ .intr_status_reg = 0, \
+ .intr_target_reg = 0, \
+ .mux_bit = -1, \
+ .pull_bit = pull, \
+ .drv_bit = drv, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = -1, \
+ .intr_enable_bit = -1, \
+ .intr_status_bit = -1, \
+ .intr_target_bit = -1, \
+ .intr_raw_status_bit = -1, \
+ .intr_polarity_bit = -1, \
+ .intr_detection_bit = -1, \
+ .intr_detection_width = -1, \
+ }
+
+#define UFS_RESET(pg_name, offset) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = ARRAY_SIZE(pg_name##_pins), \
+ .ctl_reg = offset, \
+ .io_reg = offset + 0x4, \
+ .intr_cfg_reg = 0, \
+ .intr_status_reg = 0, \
+ .intr_target_reg = 0, \
+ .mux_bit = -1, \
+ .pull_bit = 3, \
+ .drv_bit = 0, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = 0, \
+ .intr_enable_bit = -1, \
+ .intr_status_bit = -1, \
+ .intr_target_bit = -1, \
+ .intr_raw_status_bit = -1, \
+ .intr_polarity_bit = -1, \
+ .intr_detection_bit = -1, \
+ .intr_detection_width = -1, \
+ }
+static const struct pinctrl_pin_desc sc7180_pins[] = {
+ PINCTRL_PIN(0, "GPIO_0"),
+ PINCTRL_PIN(1, "GPIO_1"),
+ PINCTRL_PIN(2, "GPIO_2"),
+ PINCTRL_PIN(3, "GPIO_3"),
+ PINCTRL_PIN(4, "GPIO_4"),
+ PINCTRL_PIN(5, "GPIO_5"),
+ PINCTRL_PIN(6, "GPIO_6"),
+ PINCTRL_PIN(7, "GPIO_7"),
+ PINCTRL_PIN(8, "GPIO_8"),
+ PINCTRL_PIN(9, "GPIO_9"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+ PINCTRL_PIN(47, "GPIO_47"),
+ PINCTRL_PIN(48, "GPIO_48"),
+ PINCTRL_PIN(49, "GPIO_49"),
+ PINCTRL_PIN(50, "GPIO_50"),
+ PINCTRL_PIN(51, "GPIO_51"),
+ PINCTRL_PIN(52, "GPIO_52"),
+ PINCTRL_PIN(53, "GPIO_53"),
+ PINCTRL_PIN(54, "GPIO_54"),
+ PINCTRL_PIN(55, "GPIO_55"),
+ PINCTRL_PIN(56, "GPIO_56"),
+ PINCTRL_PIN(57, "GPIO_57"),
+ PINCTRL_PIN(58, "GPIO_58"),
+ PINCTRL_PIN(59, "GPIO_59"),
+ PINCTRL_PIN(60, "GPIO_60"),
+ PINCTRL_PIN(61, "GPIO_61"),
+ PINCTRL_PIN(62, "GPIO_62"),
+ PINCTRL_PIN(63, "GPIO_63"),
+ PINCTRL_PIN(64, "GPIO_64"),
+ PINCTRL_PIN(65, "GPIO_65"),
+ PINCTRL_PIN(66, "GPIO_66"),
+ PINCTRL_PIN(67, "GPIO_67"),
+ PINCTRL_PIN(68, "GPIO_68"),
+ PINCTRL_PIN(69, "GPIO_69"),
+ PINCTRL_PIN(70, "GPIO_70"),
+ PINCTRL_PIN(71, "GPIO_71"),
+ PINCTRL_PIN(72, "GPIO_72"),
+ PINCTRL_PIN(73, "GPIO_73"),
+ PINCTRL_PIN(74, "GPIO_74"),
+ PINCTRL_PIN(75, "GPIO_75"),
+ PINCTRL_PIN(76, "GPIO_76"),
+ PINCTRL_PIN(77, "GPIO_77"),
+ PINCTRL_PIN(78, "GPIO_78"),
+ PINCTRL_PIN(79, "GPIO_79"),
+ PINCTRL_PIN(80, "GPIO_80"),
+ PINCTRL_PIN(81, "GPIO_81"),
+ PINCTRL_PIN(82, "GPIO_82"),
+ PINCTRL_PIN(83, "GPIO_83"),
+ PINCTRL_PIN(84, "GPIO_84"),
+ PINCTRL_PIN(85, "GPIO_85"),
+ PINCTRL_PIN(86, "GPIO_86"),
+ PINCTRL_PIN(87, "GPIO_87"),
+ PINCTRL_PIN(88, "GPIO_88"),
+ PINCTRL_PIN(89, "GPIO_89"),
+ PINCTRL_PIN(90, "GPIO_90"),
+ PINCTRL_PIN(91, "GPIO_91"),
+ PINCTRL_PIN(92, "GPIO_92"),
+ PINCTRL_PIN(93, "GPIO_93"),
+ PINCTRL_PIN(94, "GPIO_94"),
+ PINCTRL_PIN(95, "GPIO_95"),
+ PINCTRL_PIN(96, "GPIO_96"),
+ PINCTRL_PIN(97, "GPIO_97"),
+ PINCTRL_PIN(98, "GPIO_98"),
+ PINCTRL_PIN(99, "GPIO_99"),
+ PINCTRL_PIN(100, "GPIO_100"),
+ PINCTRL_PIN(101, "GPIO_101"),
+ PINCTRL_PIN(102, "GPIO_102"),
+ PINCTRL_PIN(103, "GPIO_103"),
+ PINCTRL_PIN(104, "GPIO_104"),
+ PINCTRL_PIN(105, "GPIO_105"),
+ PINCTRL_PIN(106, "GPIO_106"),
+ PINCTRL_PIN(107, "GPIO_107"),
+ PINCTRL_PIN(108, "GPIO_108"),
+ PINCTRL_PIN(109, "GPIO_109"),
+ PINCTRL_PIN(110, "GPIO_110"),
+ PINCTRL_PIN(111, "GPIO_111"),
+ PINCTRL_PIN(112, "GPIO_112"),
+ PINCTRL_PIN(113, "GPIO_113"),
+ PINCTRL_PIN(114, "GPIO_114"),
+ PINCTRL_PIN(115, "GPIO_115"),
+ PINCTRL_PIN(116, "GPIO_116"),
+ PINCTRL_PIN(117, "GPIO_117"),
+ PINCTRL_PIN(118, "GPIO_118"),
+ PINCTRL_PIN(119, "UFS_RESET"),
+ PINCTRL_PIN(120, "SDC1_RCLK"),
+ PINCTRL_PIN(121, "SDC1_CLK"),
+ PINCTRL_PIN(122, "SDC1_CMD"),
+ PINCTRL_PIN(123, "SDC1_DATA"),
+ PINCTRL_PIN(124, "SDC2_CLK"),
+ PINCTRL_PIN(125, "SDC2_CMD"),
+ PINCTRL_PIN(126, "SDC2_DATA"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) \
+ static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+DECLARE_MSM_GPIO_PINS(47);
+DECLARE_MSM_GPIO_PINS(48);
+DECLARE_MSM_GPIO_PINS(49);
+DECLARE_MSM_GPIO_PINS(50);
+DECLARE_MSM_GPIO_PINS(51);
+DECLARE_MSM_GPIO_PINS(52);
+DECLARE_MSM_GPIO_PINS(53);
+DECLARE_MSM_GPIO_PINS(54);
+DECLARE_MSM_GPIO_PINS(55);
+DECLARE_MSM_GPIO_PINS(56);
+DECLARE_MSM_GPIO_PINS(57);
+DECLARE_MSM_GPIO_PINS(58);
+DECLARE_MSM_GPIO_PINS(59);
+DECLARE_MSM_GPIO_PINS(60);
+DECLARE_MSM_GPIO_PINS(61);
+DECLARE_MSM_GPIO_PINS(62);
+DECLARE_MSM_GPIO_PINS(63);
+DECLARE_MSM_GPIO_PINS(64);
+DECLARE_MSM_GPIO_PINS(65);
+DECLARE_MSM_GPIO_PINS(66);
+DECLARE_MSM_GPIO_PINS(67);
+DECLARE_MSM_GPIO_PINS(68);
+DECLARE_MSM_GPIO_PINS(69);
+DECLARE_MSM_GPIO_PINS(70);
+DECLARE_MSM_GPIO_PINS(71);
+DECLARE_MSM_GPIO_PINS(72);
+DECLARE_MSM_GPIO_PINS(73);
+DECLARE_MSM_GPIO_PINS(74);
+DECLARE_MSM_GPIO_PINS(75);
+DECLARE_MSM_GPIO_PINS(76);
+DECLARE_MSM_GPIO_PINS(77);
+DECLARE_MSM_GPIO_PINS(78);
+DECLARE_MSM_GPIO_PINS(79);
+DECLARE_MSM_GPIO_PINS(80);
+DECLARE_MSM_GPIO_PINS(81);
+DECLARE_MSM_GPIO_PINS(82);
+DECLARE_MSM_GPIO_PINS(83);
+DECLARE_MSM_GPIO_PINS(84);
+DECLARE_MSM_GPIO_PINS(85);
+DECLARE_MSM_GPIO_PINS(86);
+DECLARE_MSM_GPIO_PINS(87);
+DECLARE_MSM_GPIO_PINS(88);
+DECLARE_MSM_GPIO_PINS(89);
+DECLARE_MSM_GPIO_PINS(90);
+DECLARE_MSM_GPIO_PINS(91);
+DECLARE_MSM_GPIO_PINS(92);
+DECLARE_MSM_GPIO_PINS(93);
+DECLARE_MSM_GPIO_PINS(94);
+DECLARE_MSM_GPIO_PINS(95);
+DECLARE_MSM_GPIO_PINS(96);
+DECLARE_MSM_GPIO_PINS(97);
+DECLARE_MSM_GPIO_PINS(98);
+DECLARE_MSM_GPIO_PINS(99);
+DECLARE_MSM_GPIO_PINS(100);
+DECLARE_MSM_GPIO_PINS(101);
+DECLARE_MSM_GPIO_PINS(102);
+DECLARE_MSM_GPIO_PINS(103);
+DECLARE_MSM_GPIO_PINS(104);
+DECLARE_MSM_GPIO_PINS(105);
+DECLARE_MSM_GPIO_PINS(106);
+DECLARE_MSM_GPIO_PINS(107);
+DECLARE_MSM_GPIO_PINS(108);
+DECLARE_MSM_GPIO_PINS(109);
+DECLARE_MSM_GPIO_PINS(110);
+DECLARE_MSM_GPIO_PINS(111);
+DECLARE_MSM_GPIO_PINS(112);
+DECLARE_MSM_GPIO_PINS(113);
+DECLARE_MSM_GPIO_PINS(114);
+DECLARE_MSM_GPIO_PINS(115);
+DECLARE_MSM_GPIO_PINS(116);
+DECLARE_MSM_GPIO_PINS(117);
+DECLARE_MSM_GPIO_PINS(118);
+
+static const unsigned int ufs_reset_pins[] = { 119 };
+static const unsigned int sdc1_rclk_pins[] = { 120 };
+static const unsigned int sdc1_clk_pins[] = { 121 };
+static const unsigned int sdc1_cmd_pins[] = { 122 };
+static const unsigned int sdc1_data_pins[] = { 123 };
+static const unsigned int sdc2_clk_pins[] = { 124 };
+static const unsigned int sdc2_cmd_pins[] = { 125 };
+static const unsigned int sdc2_data_pins[] = { 126 };
+
+enum sc7180_functions {
+ msm_mux_adsp_ext,
+ msm_mux_agera_pll,
+ msm_mux_aoss_cti,
+ msm_mux_atest_char,
+ msm_mux_atest_char0,
+ msm_mux_atest_char1,
+ msm_mux_atest_char2,
+ msm_mux_atest_char3,
+ msm_mux_atest_tsens,
+ msm_mux_atest_tsens2,
+ msm_mux_atest_usb1,
+ msm_mux_atest_usb2,
+ msm_mux_atest_usb10,
+ msm_mux_atest_usb11,
+ msm_mux_atest_usb12,
+ msm_mux_atest_usb13,
+ msm_mux_atest_usb20,
+ msm_mux_atest_usb21,
+ msm_mux_atest_usb22,
+ msm_mux_atest_usb23,
+ msm_mux_audio_ref,
+ msm_mux_btfm_slimbus,
+ msm_mux_cam_mclk,
+ msm_mux_cci_async,
+ msm_mux_cci_i2c,
+ msm_mux_cci_timer0,
+ msm_mux_cci_timer1,
+ msm_mux_cci_timer2,
+ msm_mux_cci_timer3,
+ msm_mux_cci_timer4,
+ msm_mux_cri_trng,
+ msm_mux_dbg_out,
+ msm_mux_ddr_bist,
+ msm_mux_ddr_pxi0,
+ msm_mux_ddr_pxi1,
+ msm_mux_ddr_pxi2,
+ msm_mux_ddr_pxi3,
+ msm_mux_dp_hot,
+ msm_mux_edp_lcd,
+ msm_mux_gcc_gp1,
+ msm_mux_gcc_gp2,
+ msm_mux_gcc_gp3,
+ msm_mux_gpio,
+ msm_mux_gp_pdm0,
+ msm_mux_gp_pdm1,
+ msm_mux_gp_pdm2,
+ msm_mux_gps_tx,
+ msm_mux_jitter_bist,
+ msm_mux_ldo_en,
+ msm_mux_ldo_update,
+ msm_mux_lpass_ext,
+ msm_mux_mdp_vsync,
+ msm_mux_mdp_vsync0,
+ msm_mux_mdp_vsync1,
+ msm_mux_mdp_vsync2,
+ msm_mux_mdp_vsync3,
+ msm_mux_mi2s_1,
+ msm_mux_mi2s_0,
+ msm_mux_mi2s_2,
+ msm_mux_mss_lte,
+ msm_mux_m_voc,
+ msm_mux_pa_indicator,
+ msm_mux_phase_flag,
+ msm_mux_PLL_BIST,
+ msm_mux_pll_bypassnl,
+ msm_mux_pll_reset,
+ msm_mux_prng_rosc,
+ msm_mux_qdss,
+ msm_mux_qdss_cti,
+ msm_mux_qlink_enable,
+ msm_mux_qlink_request,
+ msm_mux_qspi_clk,
+ msm_mux_qspi_cs,
+ msm_mux_qspi_data,
+ msm_mux_qup00,
+ msm_mux_qup01,
+ msm_mux_qup02,
+ msm_mux_qup03,
+ msm_mux_qup04,
+ msm_mux_qup05,
+ msm_mux_qup10,
+ msm_mux_qup11,
+ msm_mux_qup12,
+ msm_mux_qup13,
+ msm_mux_qup14,
+ msm_mux_qup15,
+ msm_mux_sdc1_tb,
+ msm_mux_sdc2_tb,
+ msm_mux_sd_write,
+ msm_mux_sp_cmu,
+ msm_mux_tgu_ch0,
+ msm_mux_tgu_ch1,
+ msm_mux_tgu_ch2,
+ msm_mux_tgu_ch3,
+ msm_mux_tsense_pwm1,
+ msm_mux_tsense_pwm2,
+ msm_mux_uim1,
+ msm_mux_uim2,
+ msm_mux_uim_batt,
+ msm_mux_usb_phy,
+ msm_mux_vfr_1,
+ msm_mux__V_GPIO,
+ msm_mux__V_PPS_IN,
+ msm_mux__V_PPS_OUT,
+ msm_mux_vsense_trigger,
+ msm_mux_wlan1_adc0,
+ msm_mux_wlan1_adc1,
+ msm_mux_wlan2_adc0,
+ msm_mux_wlan2_adc1,
+ msm_mux__,
+};
+
+static const char * const qup01_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio12", "gpio94",
+};
+static const char * const gpio_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+ "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
+ "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
+ "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
+ "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
+ "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
+ "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
+ "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
+ "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
+ "gpio117", "gpio118",
+};
+static const char * const phase_flag_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio8", "gpio9",
+ "gpio11", "gpio12", "gpio17", "gpio18", "gpio19",
+ "gpio20", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
+ "gpio37", "gpio38", "gpio39", "gpio42", "gpio44",
+ "gpio56", "gpio57", "gpio58", "gpio63", "gpio64",
+ "gpio108", "gpio109",
+};
+static const char * const cri_trng_groups[] = {
+ "gpio0", "gpio1", "gpio2",
+};
+static const char * const sp_cmu_groups[] = {
+ "gpio3",
+};
+static const char * const dbg_out_groups[] = {
+ "gpio3",
+};
+static const char * const qdss_cti_groups[] = {
+ "gpio3", "gpio4", "gpio8", "gpio9", "gpio33", "gpio44", "gpio45",
+ "gpio72",
+};
+static const char * const sdc1_tb_groups[] = {
+ "gpio4",
+};
+static const char * const sdc2_tb_groups[] = {
+ "gpio5",
+};
+static const char * const qup11_groups[] = {
+ "gpio6", "gpio7",
+};
+static const char * const ddr_bist_groups[] = {
+ "gpio7", "gpio8", "gpio9", "gpio10",
+};
+static const char * const gp_pdm1_groups[] = {
+ "gpio8", "gpio50",
+};
+static const char * const mdp_vsync_groups[] = {
+ "gpio10", "gpio11", "gpio12", "gpio70", "gpio71",
+};
+static const char * const edp_lcd_groups[] = {
+ "gpio11",
+};
+static const char * const ddr_pxi2_groups[] = {
+ "gpio11", "gpio26",
+};
+static const char * const m_voc_groups[] = {
+ "gpio12",
+};
+static const char * const wlan2_adc0_groups[] = {
+ "gpio12",
+};
+static const char * const atest_usb10_groups[] = {
+ "gpio12",
+};
+static const char * const ddr_pxi3_groups[] = {
+ "gpio12", "gpio108",
+};
+static const char * const cam_mclk_groups[] = {
+ "gpio13", "gpio14", "gpio15", "gpio16", "gpio23",
+};
+static const char * const pll_bypassnl_groups[] = {
+ "gpio13",
+};
+static const char * const qdss_groups[] = {
+ "gpio13", "gpio86", "gpio14", "gpio87",
+ "gpio15", "gpio88", "gpio16", "gpio89",
+ "gpio17", "gpio90", "gpio18", "gpio91",
+ "gpio19", "gpio21", "gpio20", "gpio22",
+ "gpio23", "gpio54", "gpio24", "gpio36",
+ "gpio25", "gpio57", "gpio26", "gpio31",
+ "gpio27", "gpio56", "gpio28", "gpio29",
+ "gpio30", "gpio35", "gpio93", "gpio104",
+ "gpio34", "gpio53", "gpio37", "gpio55",
+};
+static const char * const pll_reset_groups[] = {
+ "gpio14",
+};
+static const char * const qup02_groups[] = {
+ "gpio15", "gpio16",
+};
+static const char * const cci_i2c_groups[] = {
+ "gpio17", "gpio18", "gpio19", "gpio20", "gpio27", "gpio28",
+};
+static const char * const wlan1_adc0_groups[] = {
+ "gpio17",
+};
+static const char * const atest_usb12_groups[] = {
+ "gpio17",
+};
+static const char * const ddr_pxi1_groups[] = {
+ "gpio17", "gpio44",
+};
+static const char * const atest_char_groups[] = {
+ "gpio17",
+};
+static const char * const agera_pll_groups[] = {
+ "gpio18",
+};
+static const char * const vsense_trigger_groups[] = {
+ "gpio18",
+};
+static const char * const ddr_pxi0_groups[] = {
+ "gpio18", "gpio27",
+};
+static const char * const atest_char3_groups[] = {
+ "gpio18",
+};
+static const char * const atest_char2_groups[] = {
+ "gpio19",
+};
+static const char * const atest_char1_groups[] = {
+ "gpio20",
+};
+static const char * const cci_timer0_groups[] = {
+ "gpio21",
+};
+static const char * const gcc_gp2_groups[] = {
+ "gpio21",
+};
+static const char * const atest_char0_groups[] = {
+ "gpio21",
+};
+static const char * const cci_timer1_groups[] = {
+ "gpio22",
+};
+static const char * const gcc_gp3_groups[] = {
+ "gpio22",
+};
+static const char * const cci_timer2_groups[] = {
+ "gpio23",
+};
+static const char * const cci_timer3_groups[] = {
+ "gpio24",
+};
+static const char * const cci_async_groups[] = {
+ "gpio24", "gpio25", "gpio26",
+};
+static const char * const cci_timer4_groups[] = {
+ "gpio25",
+};
+static const char * const qup05_groups[] = {
+ "gpio25", "gpio26", "gpio27", "gpio28",
+};
+static const char * const atest_tsens_groups[] = {
+ "gpio26",
+};
+static const char * const atest_usb11_groups[] = {
+ "gpio26",
+};
+static const char * const PLL_BIST_groups[] = {
+ "gpio27",
+};
+static const char * const sd_write_groups[] = {
+ "gpio33",
+};
+static const char * const qup00_groups[] = {
+ "gpio34", "gpio35", "gpio36", "gpio37",
+};
+static const char * const gp_pdm0_groups[] = {
+ "gpio37", "gpio68",
+};
+static const char * const qup03_groups[] = {
+ "gpio38", "gpio39", "gpio40", "gpio41",
+};
+static const char * const atest_tsens2_groups[] = {
+ "gpio39",
+};
+static const char * const wlan2_adc1_groups[] = {
+ "gpio39",
+};
+static const char * const atest_usb1_groups[] = {
+ "gpio39",
+};
+static const char * const qup12_groups[] = {
+ "gpio42", "gpio43", "gpio44", "gpio45",
+};
+static const char * const wlan1_adc1_groups[] = {
+ "gpio44",
+};
+static const char * const atest_usb13_groups[] = {
+ "gpio44",
+};
+static const char * const qup13_groups[] = {
+ "gpio46", "gpio47",
+};
+static const char * const gcc_gp1_groups[] = {
+ "gpio48", "gpio56",
+};
+static const char * const mi2s_1_groups[] = {
+ "gpio49", "gpio50", "gpio51", "gpio52",
+};
+static const char * const btfm_slimbus_groups[] = {
+ "gpio49", "gpio50", "gpio51", "gpio52",
+};
+static const char * const atest_usb2_groups[] = {
+ "gpio51",
+};
+static const char * const atest_usb23_groups[] = {
+ "gpio52",
+};
+static const char * const mi2s_0_groups[] = {
+ "gpio53", "gpio54", "gpio55", "gpio56",
+};
+static const char * const qup15_groups[] = {
+ "gpio53", "gpio54", "gpio55", "gpio56",
+};
+static const char * const atest_usb22_groups[] = {
+ "gpio53",
+};
+static const char * const atest_usb21_groups[] = {
+ "gpio54",
+};
+static const char * const atest_usb20_groups[] = {
+ "gpio55",
+};
+static const char * const lpass_ext_groups[] = {
+ "gpio57", "gpio58",
+};
+static const char * const audio_ref_groups[] = {
+ "gpio57",
+};
+static const char * const jitter_bist_groups[] = {
+ "gpio57",
+};
+static const char * const gp_pdm2_groups[] = {
+ "gpio57",
+};
+static const char * const qup10_groups[] = {
+ "gpio59", "gpio60", "gpio61", "gpio62", "gpio68", "gpio72",
+};
+static const char * const tgu_ch3_groups[] = {
+ "gpio62",
+};
+static const char * const qspi_clk_groups[] = {
+ "gpio63",
+};
+static const char * const mdp_vsync0_groups[] = {
+ "gpio63",
+};
+static const char * const mi2s_2_groups[] = {
+ "gpio63", "gpio64", "gpio65", "gpio66",
+};
+static const char * const mdp_vsync1_groups[] = {
+ "gpio63",
+};
+static const char * const mdp_vsync2_groups[] = {
+ "gpio63",
+};
+static const char * const mdp_vsync3_groups[] = {
+ "gpio63",
+};
+static const char * const tgu_ch0_groups[] = {
+ "gpio63",
+};
+static const char * const qspi_data_groups[] = {
+ "gpio64", "gpio65", "gpio66", "gpio67",
+};
+static const char * const tgu_ch1_groups[] = {
+ "gpio64",
+};
+static const char * const vfr_1_groups[] = {
+ "gpio65",
+};
+static const char * const tgu_ch2_groups[] = {
+ "gpio65",
+};
+static const char * const qspi_cs_groups[] = {
+ "gpio68", "gpio72",
+};
+static const char * const ldo_en_groups[] = {
+ "gpio70",
+};
+static const char * const ldo_update_groups[] = {
+ "gpio71",
+};
+static const char * const prng_rosc_groups[] = {
+ "gpio72",
+};
+static const char * const uim2_groups[] = {
+ "gpio75", "gpio76", "gpio77", "gpio78",
+};
+static const char * const uim1_groups[] = {
+ "gpio79", "gpio80", "gpio81", "gpio82",
+};
+static const char * const _V_GPIO_groups[] = {
+ "gpio83", "gpio84", "gpio107",
+};
+static const char * const _V_PPS_IN_groups[] = {
+ "gpio83", "gpio84", "gpio107",
+};
+static const char * const _V_PPS_OUT_groups[] = {
+ "gpio83", "gpio84", "gpio107",
+};
+static const char * const gps_tx_groups[] = {
+ "gpio83", "gpio84", "gpio107", "gpio109",
+};
+static const char * const uim_batt_groups[] = {
+ "gpio85",
+};
+static const char * const dp_hot_groups[] = {
+ "gpio85", "gpio117",
+};
+static const char * const aoss_cti_groups[] = {
+ "gpio85",
+};
+static const char * const qup14_groups[] = {
+ "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
+};
+static const char * const adsp_ext_groups[] = {
+ "gpio87",
+};
+static const char * const tsense_pwm1_groups[] = {
+ "gpio88",
+};
+static const char * const tsense_pwm2_groups[] = {
+ "gpio88",
+};
+static const char * const qlink_request_groups[] = {
+ "gpio96",
+};
+static const char * const qlink_enable_groups[] = {
+ "gpio97",
+};
+static const char * const pa_indicator_groups[] = {
+ "gpio99",
+};
+static const char * const usb_phy_groups[] = {
+ "gpio104",
+};
+static const char * const mss_lte_groups[] = {
+ "gpio108", "gpio109",
+};
+static const char * const qup04_groups[] = {
+ "gpio115", "gpio116",
+};
+
+static const struct msm_function sc7180_functions[] = {
+ FUNCTION(adsp_ext),
+ FUNCTION(agera_pll),
+ FUNCTION(aoss_cti),
+ FUNCTION(atest_char),
+ FUNCTION(atest_char0),
+ FUNCTION(atest_char1),
+ FUNCTION(atest_char2),
+ FUNCTION(atest_char3),
+ FUNCTION(atest_tsens),
+ FUNCTION(atest_tsens2),
+ FUNCTION(atest_usb1),
+ FUNCTION(atest_usb2),
+ FUNCTION(atest_usb10),
+ FUNCTION(atest_usb11),
+ FUNCTION(atest_usb12),
+ FUNCTION(atest_usb13),
+ FUNCTION(atest_usb20),
+ FUNCTION(atest_usb21),
+ FUNCTION(atest_usb22),
+ FUNCTION(atest_usb23),
+ FUNCTION(audio_ref),
+ FUNCTION(btfm_slimbus),
+ FUNCTION(cam_mclk),
+ FUNCTION(cci_async),
+ FUNCTION(cci_i2c),
+ FUNCTION(cci_timer0),
+ FUNCTION(cci_timer1),
+ FUNCTION(cci_timer2),
+ FUNCTION(cci_timer3),
+ FUNCTION(cci_timer4),
+ FUNCTION(cri_trng),
+ FUNCTION(dbg_out),
+ FUNCTION(ddr_bist),
+ FUNCTION(ddr_pxi0),
+ FUNCTION(ddr_pxi1),
+ FUNCTION(ddr_pxi2),
+ FUNCTION(ddr_pxi3),
+ FUNCTION(dp_hot),
+ FUNCTION(edp_lcd),
+ FUNCTION(gcc_gp1),
+ FUNCTION(gcc_gp2),
+ FUNCTION(gcc_gp3),
+ FUNCTION(gpio),
+ FUNCTION(gp_pdm0),
+ FUNCTION(gp_pdm1),
+ FUNCTION(gp_pdm2),
+ FUNCTION(gps_tx),
+ FUNCTION(jitter_bist),
+ FUNCTION(ldo_en),
+ FUNCTION(ldo_update),
+ FUNCTION(lpass_ext),
+ FUNCTION(mdp_vsync),
+ FUNCTION(mdp_vsync0),
+ FUNCTION(mdp_vsync1),
+ FUNCTION(mdp_vsync2),
+ FUNCTION(mdp_vsync3),
+ FUNCTION(mi2s_0),
+ FUNCTION(mi2s_1),
+ FUNCTION(mi2s_2),
+ FUNCTION(mss_lte),
+ FUNCTION(m_voc),
+ FUNCTION(pa_indicator),
+ FUNCTION(phase_flag),
+ FUNCTION(PLL_BIST),
+ FUNCTION(pll_bypassnl),
+ FUNCTION(pll_reset),
+ FUNCTION(prng_rosc),
+ FUNCTION(qdss),
+ FUNCTION(qdss_cti),
+ FUNCTION(qlink_enable),
+ FUNCTION(qlink_request),
+ FUNCTION(qspi_clk),
+ FUNCTION(qspi_cs),
+ FUNCTION(qspi_data),
+ FUNCTION(qup00),
+ FUNCTION(qup01),
+ FUNCTION(qup02),
+ FUNCTION(qup03),
+ FUNCTION(qup04),
+ FUNCTION(qup05),
+ FUNCTION(qup10),
+ FUNCTION(qup11),
+ FUNCTION(qup12),
+ FUNCTION(qup13),
+ FUNCTION(qup14),
+ FUNCTION(qup15),
+ FUNCTION(sdc1_tb),
+ FUNCTION(sdc2_tb),
+ FUNCTION(sd_write),
+ FUNCTION(sp_cmu),
+ FUNCTION(tgu_ch0),
+ FUNCTION(tgu_ch1),
+ FUNCTION(tgu_ch2),
+ FUNCTION(tgu_ch3),
+ FUNCTION(tsense_pwm1),
+ FUNCTION(tsense_pwm2),
+ FUNCTION(uim1),
+ FUNCTION(uim2),
+ FUNCTION(uim_batt),
+ FUNCTION(usb_phy),
+ FUNCTION(vfr_1),
+ FUNCTION(_V_GPIO),
+ FUNCTION(_V_PPS_IN),
+ FUNCTION(_V_PPS_OUT),
+ FUNCTION(vsense_trigger),
+ FUNCTION(wlan1_adc0),
+ FUNCTION(wlan1_adc1),
+ FUNCTION(wlan2_adc0),
+ FUNCTION(wlan2_adc1),
+};
+
+/* Every pin is maintained as a single group, and missing or non-existing pin
+ * would be maintained as dummy group to synchronize pin group index with
+ * pin descriptor registered with pinctrl core.
+ * Clients would not be able to request these dummy pin groups.
+ */
+static const struct msm_pingroup sc7180_groups[] = {
+ [0] = PINGROUP(0, SOUTH, qup01, cri_trng, _, phase_flag, _, _, _, _, _),
+ [1] = PINGROUP(1, SOUTH, qup01, cri_trng, _, phase_flag, _, _, _, _, _),
+ [2] = PINGROUP(2, SOUTH, qup01, cri_trng, _, phase_flag, _, _, _, _, _),
+ [3] = PINGROUP(3, SOUTH, qup01, sp_cmu, dbg_out, qdss_cti, _, _, _, _, _),
+ [4] = PINGROUP(4, NORTH, sdc1_tb, _, qdss_cti, _, _, _, _, _, _),
+ [5] = PINGROUP(5, NORTH, sdc2_tb, _, _, _, _, _, _, _, _),
+ [6] = PINGROUP(6, NORTH, qup11, qup11, _, _, _, _, _, _, _),
+ [7] = PINGROUP(7, NORTH, qup11, qup11, ddr_bist, _, _, _, _, _, _),
+ [8] = PINGROUP(8, NORTH, gp_pdm1, ddr_bist, _, phase_flag, qdss_cti, _, _, _, _),
+ [9] = PINGROUP(9, NORTH, ddr_bist, _, phase_flag, qdss_cti, _, _, _, _, _),
+ [10] = PINGROUP(10, NORTH, mdp_vsync, ddr_bist, _, _, _, _, _, _, _),
+ [11] = PINGROUP(11, NORTH, mdp_vsync, edp_lcd, _, phase_flag, ddr_pxi2, _, _, _, _),
+ [12] = PINGROUP(12, SOUTH, mdp_vsync, m_voc, qup01, _, phase_flag, wlan2_adc0, atest_usb10, ddr_pxi3, _),
+ [13] = PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, qdss, _, _, _, _, _, _),
+ [14] = PINGROUP(14, SOUTH, cam_mclk, pll_reset, qdss, _, _, _, _, _, _),
+ [15] = PINGROUP(15, SOUTH, cam_mclk, qup02, qup02, qdss, _, _, _, _, _),
+ [16] = PINGROUP(16, SOUTH, cam_mclk, qup02, qup02, qdss, _, _, _, _, _),
+ [17] = PINGROUP(17, SOUTH, cci_i2c, _, phase_flag, qdss, _, wlan1_adc0, atest_usb12, ddr_pxi1, atest_char),
+ [18] = PINGROUP(18, SOUTH, cci_i2c, agera_pll, _, phase_flag, qdss, vsense_trigger, ddr_pxi0, atest_char3, _),
+ [19] = PINGROUP(19, SOUTH, cci_i2c, _, phase_flag, qdss, atest_char2, _, _, _, _),
+ [20] = PINGROUP(20, SOUTH, cci_i2c, _, phase_flag, qdss, atest_char1, _, _, _, _),
+ [21] = PINGROUP(21, NORTH, cci_timer0, gcc_gp2, _, qdss, atest_char0, _, _, _, _),
+ [22] = PINGROUP(22, NORTH, cci_timer1, gcc_gp3, _, qdss, _, _, _, _, _),
+ [23] = PINGROUP(23, SOUTH, cci_timer2, cam_mclk, qdss, _, _, _, _, _, _),
+ [24] = PINGROUP(24, SOUTH, cci_timer3, cci_async, qdss, _, _, _, _, _, _),
+ [25] = PINGROUP(25, SOUTH, cci_timer4, cci_async, qup05, _, phase_flag, qdss, _, _, _),
+ [26] = PINGROUP(26, SOUTH, cci_async, qup05, _, phase_flag, qdss, atest_tsens, atest_usb11, ddr_pxi2, _),
+ [27] = PINGROUP(27, SOUTH, cci_i2c, qup05, PLL_BIST, _, phase_flag, qdss, ddr_pxi0, _, _),
+ [28] = PINGROUP(28, SOUTH, cci_i2c, qup05, _, phase_flag, qdss, _, _, _, _),
+ [29] = PINGROUP(29, NORTH, _, qdss, _, _, _, _, _, _, _),
+ [30] = PINGROUP(30, SOUTH, qdss, _, _, _, _, _, _, _, _),
+ [31] = PINGROUP(31, NORTH, _, qdss, _, _, _, _, _, _, _),
+ [32] = PINGROUP(32, NORTH, _, phase_flag, _, _, _, _, _, _, _),
+ [33] = PINGROUP(33, NORTH, sd_write, _, phase_flag, qdss_cti, _, _, _, _, _),
+ [34] = PINGROUP(34, SOUTH, qup00, _, phase_flag, qdss, _, _, _, _, _),
+ [35] = PINGROUP(35, SOUTH, qup00, _, phase_flag, qdss, _, _, _, _, _),
+ [36] = PINGROUP(36, SOUTH, qup00, _, phase_flag, qdss, _, _, _, _, _),
+ [37] = PINGROUP(37, SOUTH, qup00, gp_pdm0, _, phase_flag, qdss, _, _, _, _),
+ [38] = PINGROUP(38, SOUTH, qup03, _, phase_flag, _, _, _, _, _, _),
+ [39] = PINGROUP(39, SOUTH, qup03, _, phase_flag, atest_tsens2, wlan2_adc1, atest_usb1, _, _, _),
+ [40] = PINGROUP(40, SOUTH, qup03, _, _, _, _, _, _, _, _),
+ [41] = PINGROUP(41, SOUTH, qup03, _, _, _, _, _, _, _, _),
+ [42] = PINGROUP(42, NORTH, qup12, _, phase_flag, _, _, _, _, _, _),
+ [43] = PINGROUP(43, NORTH, qup12, _, _, _, _, _, _, _, _),
+ [44] = PINGROUP(44, NORTH, qup12, _, phase_flag, qdss_cti, wlan1_adc1, atest_usb13, ddr_pxi1, _, _),
+ [45] = PINGROUP(45, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _),
+ [46] = PINGROUP(46, NORTH, qup13, qup13, _, _, _, _, _, _, _),
+ [47] = PINGROUP(47, NORTH, qup13, qup13, _, _, _, _, _, _, _),
+ [48] = PINGROUP(48, NORTH, gcc_gp1, _, _, _, _, _, _, _, _),
+ [49] = PINGROUP(49, WEST, mi2s_1, btfm_slimbus, _, _, _, _, _, _, _),
+ [50] = PINGROUP(50, WEST, mi2s_1, btfm_slimbus, gp_pdm1, _, _, _, _, _, _),
+ [51] = PINGROUP(51, WEST, mi2s_1, btfm_slimbus, atest_usb2, _, _, _, _, _, _),
+ [52] = PINGROUP(52, WEST, mi2s_1, btfm_slimbus, atest_usb23, _, _, _, _, _, _),
+ [53] = PINGROUP(53, WEST, mi2s_0, qup15, qdss, atest_usb22, _, _, _, _, _),
+ [54] = PINGROUP(54, WEST, mi2s_0, qup15, qdss, atest_usb21, _, _, _, _, _),
+ [55] = PINGROUP(55, WEST, mi2s_0, qup15, qdss, atest_usb20, _, _, _, _, _),
+ [56] = PINGROUP(56, WEST, mi2s_0, qup15, gcc_gp1, _, phase_flag, qdss, _, _, _),
+ [57] = PINGROUP(57, WEST, lpass_ext, audio_ref, jitter_bist, gp_pdm2, _, phase_flag, qdss, _, _),
+ [58] = PINGROUP(58, WEST, lpass_ext, _, phase_flag, _, _, _, _, _, _),
+ [59] = PINGROUP(59, NORTH, qup10, _, _, _, _, _, _, _, _),
+ [60] = PINGROUP(60, NORTH, qup10, _, _, _, _, _, _, _, _),
+ [61] = PINGROUP(61, NORTH, qup10, _, _, _, _, _, _, _, _),
+ [62] = PINGROUP(62, NORTH, qup10, tgu_ch3, _, _, _, _, _, _, _),
+ [63] = PINGROUP(63, NORTH, qspi_clk, mdp_vsync0, mi2s_2, mdp_vsync1, mdp_vsync2, mdp_vsync3, tgu_ch0, _, phase_flag),
+ [64] = PINGROUP(64, NORTH, qspi_data, mi2s_2, tgu_ch1, _, phase_flag, _, _, _, _),
+ [65] = PINGROUP(65, NORTH, qspi_data, mi2s_2, vfr_1, tgu_ch2, _, _, _, _, _),
+ [66] = PINGROUP(66, NORTH, qspi_data, mi2s_2, _, _, _, _, _, _, _),
+ [67] = PINGROUP(67, NORTH, qspi_data, _, _, _, _, _, _, _, _),
+ [68] = PINGROUP(68, NORTH, qspi_cs, qup10, gp_pdm0, _, _, _, _, _, _),
+ [69] = PINGROUP(69, WEST, _, _, _, _, _, _, _, _, _),
+ [70] = PINGROUP(70, NORTH, _, _, mdp_vsync, ldo_en, _, _, _, _, _),
+ [71] = PINGROUP(71, NORTH, _, mdp_vsync, ldo_update, _, _, _, _, _, _),
+ [72] = PINGROUP(72, NORTH, qspi_cs, qup10, prng_rosc, _, qdss_cti, _, _, _, _),
+ [73] = PINGROUP(73, WEST, _, _, _, _, _, _, _, _, _),
+ [74] = PINGROUP(74, WEST, _, _, _, _, _, _, _, _, _),
+ [75] = PINGROUP(75, WEST, uim2, _, _, _, _, _, _, _, _),
+ [76] = PINGROUP(76, WEST, uim2, _, _, _, _, _, _, _, _),
+ [77] = PINGROUP(77, WEST, uim2, _, _, _, _, _, _, _, _),
+ [78] = PINGROUP(78, WEST, uim2, _, _, _, _, _, _, _, _),
+ [79] = PINGROUP(79, WEST, uim1, _, _, _, _, _, _, _, _),
+ [80] = PINGROUP(80, WEST, uim1, _, _, _, _, _, _, _, _),
+ [81] = PINGROUP(81, WEST, uim1, _, _, _, _, _, _, _, _),
+ [82] = PINGROUP(82, WEST, uim1, _, _, _, _, _, _, _, _),
+ [83] = PINGROUP(83, WEST, _, _V_GPIO, _V_PPS_IN, _V_PPS_OUT, gps_tx, _, _, _, _),
+ [84] = PINGROUP(84, WEST, _, _V_GPIO, _V_PPS_IN, _V_PPS_OUT, gps_tx, _, _, _, _),
+ [85] = PINGROUP(85, WEST, uim_batt, dp_hot, aoss_cti, _, _, _, _, _, _),
+ [86] = PINGROUP(86, NORTH, qup14, qdss, _, _, _, _, _, _, _),
+ [87] = PINGROUP(87, NORTH, qup14, adsp_ext, qdss, _, _, _, _, _, _),
+ [88] = PINGROUP(88, NORTH, qup14, qdss, tsense_pwm1, tsense_pwm2, _, _, _, _, _),
+ [89] = PINGROUP(89, NORTH, qup14, qdss, _, _, _, _, _, _, _),
+ [90] = PINGROUP(90, NORTH, qup14, qdss, _, _, _, _, _, _, _),
+ [91] = PINGROUP(91, NORTH, qup14, qdss, _, _, _, _, _, _, _),
+ [92] = PINGROUP(92, NORTH, _, _, _, _, _, _, _, _, _),
+ [93] = PINGROUP(93, NORTH, qdss, _, _, _, _, _, _, _, _),
+ [94] = PINGROUP(94, SOUTH, qup01, _, _, _, _, _, _, _, _),
+ [95] = PINGROUP(95, WEST, _, _, _, _, _, _, _, _, _),
+ [96] = PINGROUP(96, WEST, qlink_request, _, _, _, _, _, _, _, _),
+ [97] = PINGROUP(97, WEST, qlink_enable, _, _, _, _, _, _, _, _),
+ [98] = PINGROUP(98, WEST, _, _, _, _, _, _, _, _, _),
+ [99] = PINGROUP(99, WEST, _, pa_indicator, _, _, _, _, _, _, _),
+ [100] = PINGROUP(100, WEST, _, _, _, _, _, _, _, _, _),
+ [101] = PINGROUP(101, NORTH, _, _, _, _, _, _, _, _, _),
+ [102] = PINGROUP(102, NORTH, _, _, _, _, _, _, _, _, _),
+ [103] = PINGROUP(103, NORTH, _, _, _, _, _, _, _, _, _),
+ [104] = PINGROUP(104, WEST, usb_phy, _, qdss, _, _, _, _, _, _),
+ [105] = PINGROUP(105, NORTH, _, _, _, _, _, _, _, _, _),
+ [106] = PINGROUP(106, NORTH, _, _, _, _, _, _, _, _, _),
+ [107] = PINGROUP(107, WEST, _, _V_GPIO, _V_PPS_IN, _V_PPS_OUT, gps_tx, _, _, _, _),
+ [108] = PINGROUP(108, SOUTH, mss_lte, _, phase_flag, ddr_pxi3, _, _, _, _, _),
+ [109] = PINGROUP(109, SOUTH, mss_lte, gps_tx, _, phase_flag, _, _, _, _, _),
+ [110] = PINGROUP(110, NORTH, _, _, _, _, _, _, _, _, _),
+ [111] = PINGROUP(111, NORTH, _, _, _, _, _, _, _, _, _),
+ [112] = PINGROUP(112, NORTH, _, _, _, _, _, _, _, _, _),
+ [113] = PINGROUP(113, NORTH, _, _, _, _, _, _, _, _, _),
+ [114] = PINGROUP(114, NORTH, _, _, _, _, _, _, _, _, _),
+ [115] = PINGROUP(115, WEST, qup04, qup04, _, _, _, _, _, _, _),
+ [116] = PINGROUP(116, WEST, qup04, qup04, _, _, _, _, _, _, _),
+ [117] = PINGROUP(117, WEST, dp_hot, _, _, _, _, _, _, _, _),
+ [118] = PINGROUP(118, WEST, _, _, _, _, _, _, _, _, _),
+ [119] = UFS_RESET(ufs_reset, 0x97f000),
+ [120] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x97a000, 15, 0),
+ [121] = SDC_QDSD_PINGROUP(sdc1_clk, 0x97a000, 13, 6),
+ [122] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x97a000, 11, 3),
+ [123] = SDC_QDSD_PINGROUP(sdc1_data, 0x97a000, 9, 0),
+ [124] = SDC_QDSD_PINGROUP(sdc2_clk, 0x97b000, 14, 6),
+ [125] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x97b000, 11, 3),
+ [126] = SDC_QDSD_PINGROUP(sdc2_data, 0x97b000, 9, 0),
+};
+
+static const struct msm_pinctrl_soc_data sc7180_pinctrl = {
+ .pins = sc7180_pins,
+ .npins = ARRAY_SIZE(sc7180_pins),
+ .functions = sc7180_functions,
+ .nfunctions = ARRAY_SIZE(sc7180_functions),
+ .groups = sc7180_groups,
+ .ngroups = ARRAY_SIZE(sc7180_groups),
+ .ngpios = 120,
+ .tiles = sc7180_tiles,
+ .ntiles = ARRAY_SIZE(sc7180_tiles),
+};
+
+static int sc7180_pinctrl_probe(struct platform_device *pdev)
+{
+ return msm_pinctrl_probe(pdev, &sc7180_pinctrl);
+}
+
+static const struct of_device_id sc7180_pinctrl_of_match[] = {
+ { .compatible = "qcom,sc7180-pinctrl", },
+ { },
+};
+
+static struct platform_driver sc7180_pinctrl_driver = {
+ .driver = {
+ .name = "sc7180-pinctrl",
+ .pm = &msm_pinctrl_dev_pm_ops,
+ .of_match_table = sc7180_pinctrl_of_match,
+ },
+ .probe = sc7180_pinctrl_probe,
+ .remove = msm_pinctrl_remove,
+};
+
+static int __init sc7180_pinctrl_init(void)
+{
+ return platform_driver_register(&sc7180_pinctrl_driver);
+}
+arch_initcall(sc7180_pinctrl_init);
+
+static void __exit sc7180_pinctrl_exit(void)
+{
+ platform_driver_unregister(&sc7180_pinctrl_driver);
+}
+module_exit(sc7180_pinctrl_exit);
+
+MODULE_DESCRIPTION("QTI sc7180 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, sc7180_pinctrl_of_match);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* Re: [PATCH 1/2] dt-bindings: pinctrl: qcom: Add SC7180 pinctrl binding
From: Rajendra Nayak @ 2019-08-06 6:09 UTC (permalink / raw)
To: Linus Walleij
Cc: Bjorn Andersson, MSM, Andy Gross, Rob Herring,
open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-kernel@vger.kernel.org, Jitendra Sharma, Vivek Gautam
In-Reply-To: <CACRpkdaoOuyUmysb3OmErbLJ6zZuHGGt7RRzG9wULDkg=hLCAw@mail.gmail.com>
On 8/5/2019 5:05 PM, Linus Walleij wrote:
> On Mon, Aug 5, 2019 at 1:34 PM Linus Walleij <linus.walleij@linaro.org> wrote:
>> On Thu, Aug 1, 2019 at 12:07 PM Rajendra Nayak <rnayak@codeaurora.org> wrote:
>>
>>> From: Jitendra Sharma <shajit@codeaurora.org>
>>>
>>> Add the binding for the TLMM pinctrl block found in the SC7180 platform
>>>
>>> Signed-off-by: Jitendra Sharma <shajit@codeaurora.org>
>>> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
>>> [rnayak: Fix some copy-paste issues, sort and fix functions]
>>> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
>>
>> Patch applied with Bjorn's ACK.
>
> Ooops there is v2 and even v3 coming, OK I wait for v3 and
> backed this out.
Hi Linus, I just posted the v3 out with all the ACKs added.
They should be good to pick up now.
thanks,
Rajendra
>
> Yours,
> Linus Walleij
>
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply
* [PATCHv3 1/3] dt-bindings: pci: layerscape-pci: add compatible strings "fsl,ls1028a-pcie"
From: Xiaowei Bao @ 2019-08-06 6:15 UTC (permalink / raw)
To: bhelgaas, robh+dt, mark.rutland, shawnguo, leoyang.li, kishon,
lorenzo.pieralisi, arnd, gregkh, minghuan.Lian, mingkai.hu,
zhiqiang.hou, roy.zang, kstewart, pombredanne, shawn.lin,
linux-pci, devicetree, linux-kernel, linux-arm-kernel,
linuxppc-dev
Cc: Xiaowei Bao, Hou Zhiqiang
Add the PCIe compatible string for LS1028A
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
v2:
- no change.
v3:
- no change.
Documentation/devicetree/bindings/pci/layerscape-pci.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index e20ceaa..99a386e 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -21,6 +21,7 @@ Required properties:
"fsl,ls1046a-pcie"
"fsl,ls1043a-pcie"
"fsl,ls1012a-pcie"
+ "fsl,ls1028a-pcie"
EP mode:
"fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
- reg: base addresses and lengths of the PCIe controller register blocks.
--
2.9.5
^ permalink raw reply related
* [PATCHv3 2/3] arm64: dts: ls1028a: Add PCIe controller DT nodes
From: Xiaowei Bao @ 2019-08-06 6:15 UTC (permalink / raw)
To: bhelgaas, robh+dt, mark.rutland, shawnguo, leoyang.li, kishon,
lorenzo.pieralisi, arnd, gregkh, minghuan.Lian, mingkai.hu,
zhiqiang.hou, roy.zang, kstewart, pombredanne, shawn.lin,
linux-pci, devicetree, linux-kernel, linux-arm-kernel,
linuxppc-dev
Cc: Xiaowei Bao, Hou Zhiqiang
In-Reply-To: <20190806061553.19934-1-xiaowei.bao@nxp.com>
LS1028a implements 2 PCIe 3.0 controllers.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
v2:
- Fix up the legacy INTx allocate failed issue.
v3:
- no change.
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 52 ++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index aef5b06..0b542ed 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -503,6 +503,58 @@
status = "disabled";
};
+ pcie@3400000 {
+ compatible = "fsl,ls1028a-pcie";
+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
+ 0x80 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
+ interrupt-names = "pme", "aer";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ pcie@3500000 {
+ compatible = "fsl,ls1028a-pcie";
+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
+ 0x88 0x00000000 0x0 0x00002000>; /* configuration space */
+ reg-names = "regs", "config";
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pme", "aer";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ dma-coherent;
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ msi-parent = <&its>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
pcie@1f0000000 { /* Integrated Endpoint Root Complex */
compatible = "pci-host-ecam-generic";
reg = <0x01 0xf0000000 0x0 0x100000>;
--
2.9.5
^ permalink raw reply related
* [PATCHv3 3/3] PCI: layerscape: Add LS1028a support
From: Xiaowei Bao @ 2019-08-06 6:15 UTC (permalink / raw)
To: bhelgaas, robh+dt, mark.rutland, shawnguo, leoyang.li, kishon,
lorenzo.pieralisi, arnd, gregkh, minghuan.Lian, mingkai.hu,
zhiqiang.hou, roy.zang, kstewart, pombredanne, shawn.lin,
linux-pci, devicetree, linux-kernel, linux-arm-kernel,
linuxppc-dev
Cc: Xiaowei Bao, Hou Zhiqiang
In-Reply-To: <20190806061553.19934-1-xiaowei.bao@nxp.com>
Add support for the LS1028a PCIe controller.
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
v2:
- no change.
v3:
- Reuse the ls2088 driver data structurt.
drivers/pci/controller/dwc/pci-layerscape.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c
index 3a5fa26..f24f79a 100644
--- a/drivers/pci/controller/dwc/pci-layerscape.c
+++ b/drivers/pci/controller/dwc/pci-layerscape.c
@@ -263,6 +263,7 @@ static const struct ls_pcie_drvdata ls2088_drvdata = {
static const struct of_device_id ls_pcie_of_match[] = {
{ .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata },
{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
+ { .compatible = "fsl,ls1028a-pcie", .data = &ls2088_drvdata },
{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
{ .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
{ .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
--
2.9.5
^ permalink raw reply related
* Re: [PATCH 01/16] net: phy: adin: add support for Analog Devices PHYs
From: Ardelean, Alexandru @ 2019-08-06 6:32 UTC (permalink / raw)
To: andrew@lunn.ch
Cc: davem@davemloft.net, hkallweit1@gmail.com,
devicetree@vger.kernel.org, mark.rutland@arm.com,
linux-kernel@vger.kernel.org, f.fainelli@gmail.com,
netdev@vger.kernel.org, robh+dt@kernel.org
In-Reply-To: <20190805141644.GH24275@lunn.ch>
On Mon, 2019-08-05 at 16:16 +0200, Andrew Lunn wrote:
> [External]
>
> > +static int adin_config_init(struct phy_device *phydev)
> > +{
> > + int rc;
> > +
> > + rc = genphy_config_init(phydev);
> > + if (rc < 0)
> > + return rc;
> > +
> > + return 0;
> > +}
>
> Why not just
>
> return genphy_config_init(phydev);
Because stuff will get added after this return statement in the next patches.
I thought maybe this would be a good idea to keep the git changes minimal, but I can do a direct return and update it in
the next patches when needed.
>
> Andrew
>
^ permalink raw reply
* Re: [PATCH 01/16] net: phy: adin: add support for Analog Devices PHYs
From: Ardelean, Alexandru @ 2019-08-06 6:35 UTC (permalink / raw)
To: andrew@lunn.ch
Cc: davem@davemloft.net, hkallweit1@gmail.com,
devicetree@vger.kernel.org, mark.rutland@arm.com,
linux-kernel@vger.kernel.org, f.fainelli@gmail.com,
netdev@vger.kernel.org, robh+dt@kernel.org
In-Reply-To: <20190805151736.GQ24275@lunn.ch>
On Mon, 2019-08-05 at 17:17 +0200, Andrew Lunn wrote:
> [External]
>
> > +static struct phy_driver adin_driver[] = {
> > + {
> > + .phy_id = PHY_ID_ADIN1200,
> > + .name = "ADIN1200",
> > + .phy_id_mask = 0xfffffff0,
> > + .features = PHY_BASIC_FEATURES,
>
> Do you need this? If the device implements the registers correctly,
> phylib can determine this from the registers.
ack;
will take a look;
>
> > + .config_init = adin_config_init,
> > + .config_aneg = genphy_config_aneg,
> > + .read_status = genphy_read_status,
> > + },
> > + {
> > + .phy_id = PHY_ID_ADIN1300,
> > + .name = "ADIN1300",
> > + .phy_id_mask = 0xfffffff0,
> > + .features = PHY_GBIT_FEATURES,
>
> same here.
ack;
>
> > + .config_init = adin_config_init,
> > + .config_aneg = genphy_config_aneg,
> > + .read_status = genphy_read_status,
> > + },
> > +};
> > +
> > +module_phy_driver(adin_driver);
> > +
> > +static struct mdio_device_id __maybe_unused adin_tbl[] = {
> > + { PHY_ID_ADIN1200, 0xfffffff0 },
> > + { PHY_ID_ADIN1300, 0xfffffff0 },
>
> PHY_ID_MATCH_VENDOR().
ack;
>
> Andrew
^ permalink raw reply
* Re: [PATCH 01/16] net: phy: adin: add support for Analog Devices PHYs
From: Ardelean, Alexandru @ 2019-08-06 6:35 UTC (permalink / raw)
To: devicetree@vger.kernel.org, hkallweit1@gmail.com,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: f.fainelli@gmail.com, davem@davemloft.net, mark.rutland@arm.com,
robh+dt@kernel.org, andrew@lunn.ch
In-Reply-To: <206ec97f-3115-9a2c-91a0-e5f7aec4a39e@gmail.com>
On Mon, 2019-08-05 at 22:54 +0200, Heiner Kallweit wrote:
> [External]
>
> On 05.08.2019 18:54, Alexandru Ardelean wrote:
> > This change adds support for Analog Devices Industrial Ethernet PHYs.
> > Particularly the PHYs this driver adds support for:
> > * ADIN1200 - Robust, Industrial, Low Power 10/100 Ethernet PHY
> > * ADIN1300 - Robust, Industrial, Low Latency 10/100/1000 Gigabit
> > Ethernet PHY
> >
> > The 2 chips are pin & register compatible with one another. The main
> > difference being that ADIN1200 doesn't operate in gigabit mode.
> >
> > The chips can be operated by the Generic PHY driver as well via the
> > standard IEEE PHY registers (0x0000 - 0x000F) which are supported by the
> > kernel as well. This assumes that configuration of the PHY has been done
> > required.
> >
> > Configuration can also be done via registers, which will be implemented by
> > the driver in the next changes.
> >
> > Datasheets:
> > https://www.analog.com/media/en/technical-documentation/data-sheets/ADIN1300.pdf
> > https://www.analog.com/media/en/technical-documentation/data-sheets/ADIN1200.pdf
> >
> > Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
> > ---
> > MAINTAINERS | 7 +++++
> > drivers/net/phy/Kconfig | 9 ++++++
> > drivers/net/phy/Makefile | 1 +
> > drivers/net/phy/adin.c | 59 ++++++++++++++++++++++++++++++++++++++++
> > 4 files changed, 76 insertions(+)
> > create mode 100644 drivers/net/phy/adin.c
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index ee663e0e2f2e..faf5723610c8 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -938,6 +938,13 @@ S: Supported
> > F: drivers/mux/adgs1408.c
> > F: Documentation/devicetree/bindings/mux/adi,adgs1408.txt
> >
> > +ANALOG DEVICES INC ADIN DRIVER
> > +M: Alexandru Ardelean <alexaundru.ardelean@analog.com>
> > +L: netdev@vger.kernel.org
> > +W: http://ez.analog.com/community/linux-device-drivers
> > +S: Supported
> > +F: drivers/net/phy/adin.c
> > +
> > ANALOG DEVICES INC ADIS DRIVER LIBRARY
> > M: Alexandru Ardelean <alexandru.ardelean@analog.com>
> > S: Supported
> > diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> > index 206d8650ee7f..5966d3413676 100644
> > --- a/drivers/net/phy/Kconfig
> > +++ b/drivers/net/phy/Kconfig
> > @@ -257,6 +257,15 @@ config SFP
> > depends on HWMON || HWMON=n
> > select MDIO_I2C
> >
> > +config ADIN_PHY
> > + tristate "Analog Devices Industrial Ethernet PHYs"
> > + help
> > + Adds support for the Analog Devices Industrial Ethernet PHYs.
> > + Currently supports the:
> > + - ADIN1200 - Robust,Industrial, Low Power 10/100 Ethernet PHY
> > + - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
> > + Ethernet PHY
> > +
> > config AMD_PHY
> > tristate "AMD PHYs"
> > ---help---
> > diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
> > index ba07c27e4208..a03437e091f3 100644
> > --- a/drivers/net/phy/Makefile
> > +++ b/drivers/net/phy/Makefile
> > @@ -47,6 +47,7 @@ obj-$(CONFIG_SFP) += sfp.o
> > sfp-obj-$(CONFIG_SFP) += sfp-bus.o
> > obj-y += $(sfp-obj-y) $(sfp-obj-m)
> >
> > +obj-$(CONFIG_ADIN_PHY) += adin.o
> > obj-$(CONFIG_AMD_PHY) += amd.o
> > aquantia-objs += aquantia_main.o
> > ifdef CONFIG_HWMON
> > diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
> > new file mode 100644
> > index 000000000000..6a610d4563c3
> > --- /dev/null
> > +++ b/drivers/net/phy/adin.c
> > @@ -0,0 +1,59 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/**
> > + * Driver for Analog Devices Industrial Ethernet PHYs
> > + *
> > + * Copyright 2019 Analog Devices Inc.
> > + */
> > +#include <linux/kernel.h>
> > +#include <linux/errno.h>
> > +#include <linux/init.h>
> > +#include <linux/module.h>
> > +#include <linux/mii.h>
> > +#include <linux/phy.h>
> > +
> > +#define PHY_ID_ADIN1200 0x0283bc20
> > +#define PHY_ID_ADIN1300 0x0283bc30
> > +
> > +static int adin_config_init(struct phy_device *phydev)
> > +{
> > + int rc;
> > +
> > + rc = genphy_config_init(phydev);
> > + if (rc < 0)
> > + return rc;
> > +
> > + return 0;
> > +}
> > +
> > +static struct phy_driver adin_driver[] = {
> > + {
> > + .phy_id = PHY_ID_ADIN1200,
>
> You could use PHY_ID_MATCH_MODEL here.
>
> > + .name = "ADIN1200",
> > + .phy_id_mask = 0xfffffff0,
> > + .features = PHY_BASIC_FEATURES,
>
> Setting features is deprecated, instead the get_features callback
> should be implemented if the default genphy_read_abilities needs
> to be extended / replaced. You say that the PHY's work with the
> genphy driver, so I suppose the default feature detection is ok
> in your case. Then you could simply remove setting "features".
ack;
thanks for the info
>
> > + .config_init = adin_config_init,
> > + .config_aneg = genphy_config_aneg,
> > + .read_status = genphy_read_status,
> > + },
> > + {
> > + .phy_id = PHY_ID_ADIN1300,
> > + .name = "ADIN1300",
> > + .phy_id_mask = 0xfffffff0,
> > + .features = PHY_GBIT_FEATURES,
> > + .config_init = adin_config_init,
> > + .config_aneg = genphy_config_aneg,
> > + .read_status = genphy_read_status,
> > + },
> > +};
> > +
> > +module_phy_driver(adin_driver);
> > +
> > +static struct mdio_device_id __maybe_unused adin_tbl[] = {
> > + { PHY_ID_ADIN1200, 0xfffffff0 },
> > + { PHY_ID_ADIN1300, 0xfffffff0 },
>
> PHY_ID_MATCH_MODEL could be used here too.
ack;
will take a look
>
> > + { }
> > +};
> > +
> > +MODULE_DEVICE_TABLE(mdio, adin_tbl);
> > +MODULE_DESCRIPTION("Analog Devices Industrial Ethernet PHY driver");
> > +MODULE_LICENSE("GPL");
> >
^ permalink raw reply
* Re: [PATCH 03/16] net: phy: adin: add support for interrupts
From: Ardelean, Alexandru @ 2019-08-06 6:37 UTC (permalink / raw)
To: andrew@lunn.ch
Cc: davem@davemloft.net, hkallweit1@gmail.com,
devicetree@vger.kernel.org, mark.rutland@arm.com,
linux-kernel@vger.kernel.org, f.fainelli@gmail.com,
netdev@vger.kernel.org, robh+dt@kernel.org
In-Reply-To: <20190805142123.GJ24275@lunn.ch>
On Mon, 2019-08-05 at 16:21 +0200, Andrew Lunn wrote:
> [External]
>
> On Mon, Aug 05, 2019 at 07:54:40PM +0300, Alexandru Ardelean wrote:
> > This change adds support for enabling PHY interrupts that can be used by
> > the PHY framework to get signal for link/speed/auto-negotiation changes.
> >
> > Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
> > ---
> > drivers/net/phy/adin.c | 44 ++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 44 insertions(+)
> >
> > diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
> > index c100a0dd95cd..b75c723bda79 100644
> > --- a/drivers/net/phy/adin.c
> > +++ b/drivers/net/phy/adin.c
> > @@ -14,6 +14,22 @@
> > #define PHY_ID_ADIN1200 0x0283bc20
> > #define PHY_ID_ADIN1300 0x0283bc30
> >
> > +#define ADIN1300_INT_MASK_REG 0x0018
> > +#define ADIN1300_INT_MDIO_SYNC_EN BIT(9)
> > +#define ADIN1300_INT_ANEG_STAT_CHNG_EN BIT(8)
> > +#define ADIN1300_INT_ANEG_PAGE_RX_EN BIT(6)
> > +#define ADIN1300_INT_IDLE_ERR_CNT_EN BIT(5)
> > +#define ADIN1300_INT_MAC_FIFO_OU_EN BIT(4)
> > +#define ADIN1300_INT_RX_STAT_CHNG_EN BIT(3)
> > +#define ADIN1300_INT_LINK_STAT_CHNG_EN BIT(2)
> > +#define ADIN1300_INT_SPEED_CHNG_EN BIT(1)
> > +#define ADIN1300_INT_HW_IRQ_EN BIT(0)
> > +#define ADIN1300_INT_MASK_EN \
> > + (ADIN1300_INT_ANEG_STAT_CHNG_EN | ADIN1300_INT_ANEG_PAGE_RX_EN | \
> > + ADIN1300_INT_LINK_STAT_CHNG_EN | ADIN1300_INT_SPEED_CHNG_EN | \
> > + ADIN1300_INT_HW_IRQ_EN)
> > +#define ADIN1300_INT_STATUS_REG 0x0019
> > +
> > static int adin_config_init(struct phy_device *phydev)
> > {
> > int rc;
> > @@ -25,15 +41,40 @@ static int adin_config_init(struct phy_device *phydev)
> > return 0;
> > }
> >
> > +static int adin_phy_ack_intr(struct phy_device *phydev)
> > +{
> > + int ret;
> > +
> > + /* Clear pending interrupts. */
> > + ret = phy_read(phydev, ADIN1300_INT_STATUS_REG);
> > + if (ret < 0)
> > + return ret;
> > +
> > + return 0;
>
> Please go through the whole driver and throw out all the needless
ack;
i'll re-visit;
>
> if (ret < 0)
> return ret;
>
> return 0;
>
> Thanks
> Andrew
^ permalink raw reply
* Re: [PATCH 03/16] net: phy: adin: add support for interrupts
From: Ardelean, Alexandru @ 2019-08-06 6:38 UTC (permalink / raw)
To: devicetree@vger.kernel.org, hkallweit1@gmail.com,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: f.fainelli@gmail.com, davem@davemloft.net, mark.rutland@arm.com,
robh+dt@kernel.org, andrew@lunn.ch
In-Reply-To: <4f539572-4c59-0450-fcd4-0bbc3eece9c8@gmail.com>
On Mon, 2019-08-05 at 23:02 +0200, Heiner Kallweit wrote:
> [External]
>
> On 05.08.2019 18:54, Alexandru Ardelean wrote:
> > This change adds support for enabling PHY interrupts that can be used by
> > the PHY framework to get signal for link/speed/auto-negotiation changes.
> >
> > Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
> > ---
> > drivers/net/phy/adin.c | 44 ++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 44 insertions(+)
> >
> > diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
> > index c100a0dd95cd..b75c723bda79 100644
> > --- a/drivers/net/phy/adin.c
> > +++ b/drivers/net/phy/adin.c
> > @@ -14,6 +14,22 @@
> > #define PHY_ID_ADIN1200 0x0283bc20
> > #define PHY_ID_ADIN1300 0x0283bc30
> >
> > +#define ADIN1300_INT_MASK_REG 0x0018
> > +#define ADIN1300_INT_MDIO_SYNC_EN BIT(9)
> > +#define ADIN1300_INT_ANEG_STAT_CHNG_EN BIT(8)
> > +#define ADIN1300_INT_ANEG_PAGE_RX_EN BIT(6)
> > +#define ADIN1300_INT_IDLE_ERR_CNT_EN BIT(5)
> > +#define ADIN1300_INT_MAC_FIFO_OU_EN BIT(4)
> > +#define ADIN1300_INT_RX_STAT_CHNG_EN BIT(3)
> > +#define ADIN1300_INT_LINK_STAT_CHNG_EN BIT(2)
> > +#define ADIN1300_INT_SPEED_CHNG_EN BIT(1)
> > +#define ADIN1300_INT_HW_IRQ_EN BIT(0)
> > +#define ADIN1300_INT_MASK_EN \
> > + (ADIN1300_INT_ANEG_STAT_CHNG_EN | ADIN1300_INT_ANEG_PAGE_RX_EN | \
> > + ADIN1300_INT_LINK_STAT_CHNG_EN | ADIN1300_INT_SPEED_CHNG_EN | \
> > + ADIN1300_INT_HW_IRQ_EN)
> > +#define ADIN1300_INT_STATUS_REG 0x0019
> > +
> > static int adin_config_init(struct phy_device *phydev)
> > {
> > int rc;
> > @@ -25,15 +41,40 @@ static int adin_config_init(struct phy_device *phydev)
> > return 0;
> > }
> >
> > +static int adin_phy_ack_intr(struct phy_device *phydev)
> > +{
> > + int ret;
> > +
> > + /* Clear pending interrupts. */
> > + ret = phy_read(phydev, ADIN1300_INT_STATUS_REG);
> > + if (ret < 0)
> > + return ret;
> > +
> > + return 0;
> > +}
> > +
> > +static int adin_phy_config_intr(struct phy_device *phydev)
> > +{
> > + if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
> > + return phy_set_bits(phydev, ADIN1300_INT_MASK_REG,
> > + ADIN1300_INT_MASK_EN);
> > +
> > + return phy_clear_bits(phydev, ADIN1300_INT_MASK_REG,
> > + ADIN1300_INT_MASK_EN);
> > +}
> > +
> > static struct phy_driver adin_driver[] = {
> > {
> > .phy_id = PHY_ID_ADIN1200,
> > .name = "ADIN1200",
> > .phy_id_mask = 0xfffffff0,
> > .features = PHY_BASIC_FEATURES,
> > + .flags = PHY_HAS_INTERRUPT,
>
> This flag doesn't exist any longer. This indicates that you
> develop against an older kernel version. Please develop
> against net-next. Check up-to-date drivers like the one
> for Realtek PHY's for hints.
ack;
>
> > .config_init = adin_config_init,
> > .config_aneg = genphy_config_aneg,
> > .read_status = genphy_read_status,
> > + .ack_interrupt = adin_phy_ack_intr,
> > + .config_intr = adin_phy_config_intr,
> > .resume = genphy_resume,
> > .suspend = genphy_suspend,
> > },
> > @@ -42,9 +83,12 @@ static struct phy_driver adin_driver[] = {
> > .name = "ADIN1300",
> > .phy_id_mask = 0xfffffff0,
> > .features = PHY_GBIT_FEATURES,
> > + .flags = PHY_HAS_INTERRUPT,
> > .config_init = adin_config_init,
> > .config_aneg = genphy_config_aneg,
> > .read_status = genphy_read_status,
> > + .ack_interrupt = adin_phy_ack_intr,
> > + .config_intr = adin_phy_config_intr,
> > .resume = genphy_resume,
> > .suspend = genphy_suspend,
> > },
> >
^ permalink raw reply
* Re: [PATCH 04/16] net: phy: adin: add {write,read}_mmd hooks
From: Ardelean, Alexandru @ 2019-08-06 6:38 UTC (permalink / raw)
To: andrew@lunn.ch
Cc: davem@davemloft.net, hkallweit1@gmail.com,
devicetree@vger.kernel.org, mark.rutland@arm.com,
linux-kernel@vger.kernel.org, f.fainelli@gmail.com,
netdev@vger.kernel.org, robh+dt@kernel.org
In-Reply-To: <20190805142513.GK24275@lunn.ch>
On Mon, 2019-08-05 at 16:25 +0200, Andrew Lunn wrote:
> [External]
>
> > diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
> > index b75c723bda79..3dd9fe50f4c8 100644
> > --- a/drivers/net/phy/adin.c
> > +++ b/drivers/net/phy/adin.c
> > @@ -14,6 +14,9 @@
> > #define PHY_ID_ADIN1200 0x0283bc20
> > #define PHY_ID_ADIN1300 0x0283bc30
> >
> > +#define ADIN1300_MII_EXT_REG_PTR 0x10
> > +#define ADIN1300_MII_EXT_REG_DATA 0x11
> > +
> > #define ADIN1300_INT_MASK_REG 0x0018
>
> Please be consistent with registers. Either use 4 digits, or 2 digits.
ack;
>
> Andrew
^ permalink raw reply
* Re: [PATCH 05/16] net: phy: adin: configure RGMII/RMII/MII modes on config
From: Ardelean, Alexandru @ 2019-08-06 6:43 UTC (permalink / raw)
To: andrew@lunn.ch
Cc: davem@davemloft.net, hkallweit1@gmail.com,
devicetree@vger.kernel.org, mark.rutland@arm.com,
linux-kernel@vger.kernel.org, f.fainelli@gmail.com,
netdev@vger.kernel.org, robh+dt@kernel.org
In-Reply-To: <20190805143935.GM24275@lunn.ch>
On Mon, 2019-08-05 at 16:39 +0200, Andrew Lunn wrote:
> [External]
>
> On Mon, Aug 05, 2019 at 07:54:42PM +0300, Alexandru Ardelean wrote:
> > The ADIN1300 chip supports RGMII, RMII & MII modes. Default (if
> > unconfigured) is RGMII.
> > This change adds support for configuring these modes via the device
> > registers.
> >
> > For RGMII with internal delays (modes RGMII_ID,RGMII_TXID, RGMII_RXID),
>
> It would be nice to add the missing space.
>
> > the default delay is 2 ns. This can be configurable and will be done in
> > a subsequent change.
> >
> > Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
> > ---
> > drivers/net/phy/adin.c | 79 +++++++++++++++++++++++++++++++++++++++++-
> > 1 file changed, 78 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
> > index 3dd9fe50f4c8..dbdb8f60741c 100644
> > --- a/drivers/net/phy/adin.c
> > +++ b/drivers/net/phy/adin.c
> > @@ -33,14 +33,91 @@
> > ADIN1300_INT_HW_IRQ_EN)
> > #define ADIN1300_INT_STATUS_REG 0x0019
> >
> > +#define ADIN1300_GE_RGMII_CFG_REG 0xff23
> > +#define ADIN1300_GE_RGMII_RXID_EN BIT(2)
> > +#define ADIN1300_GE_RGMII_TXID_EN BIT(1)
> > +#define ADIN1300_GE_RGMII_EN BIT(0)
> > +
> > +#define ADIN1300_GE_RMII_CFG_REG 0xff24
> > +#define ADIN1300_GE_RMII_EN BIT(0)
> > +
> > +static int adin_config_rgmii_mode(struct phy_device *phydev,
> > + phy_interface_t intf)
> > +{
> > + int reg;
> > +
> > + reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RGMII_CFG_REG);
> > + if (reg < 0)
> > + return reg;
> > +
> > + if (!phy_interface_mode_is_rgmii(intf)) {
> > + reg &= ~ADIN1300_GE_RGMII_EN;
> > + goto write;
> > + }
> > +
> > + reg |= ADIN1300_GE_RGMII_EN;
> > +
> > + if (intf == PHY_INTERFACE_MODE_RGMII_ID ||
> > + intf == PHY_INTERFACE_MODE_RGMII_RXID) {
> > + reg |= ADIN1300_GE_RGMII_RXID_EN;
> > + } else {
> > + reg &= ~ADIN1300_GE_RGMII_RXID_EN;
> > + }
> > +
> > + if (intf == PHY_INTERFACE_MODE_RGMII_ID ||
> > + intf == PHY_INTERFACE_MODE_RGMII_TXID) {
> > + reg |= ADIN1300_GE_RGMII_TXID_EN;
> > + } else {
> > + reg &= ~ADIN1300_GE_RGMII_TXID_EN;
> > + }
>
> Nice. Often driver writers forget to clear the delay, they only set
> it. Not so here.
>
> However, is checkpatch happy with this? Each half of the if/else is a
> single statement, so the {} are not needed.
it did not complain;
this whole series is checkpatch friendly [with the version of checkpatch in net-next]
i think it complained about un-balanced if-block; something like:
```
if () {
} else
single-statement
```
but checkpatch is also a moving target;
so ¯\_(ツ)_/¯
>
> > +
> > +write:
> > + return phy_write_mmd(phydev, MDIO_MMD_VEND1,
> > + ADIN1300_GE_RGMII_CFG_REG, reg);
> > +}
> > +
> > +static int adin_config_rmii_mode(struct phy_device *phydev,
> > + phy_interface_t intf)
> > +{
> > + int reg;
> > +
> > + reg = phy_read_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_RMII_CFG_REG);
> > + if (reg < 0)
> > + return reg;
> > +
> > + if (intf != PHY_INTERFACE_MODE_RMII) {
> > + reg &= ~ADIN1300_GE_RMII_EN;
> > + goto write;
>
> goto? Really?
yep;
personally, i used to not like it all that much up until a few years, but sometimes it feels it can help with creating
cleaner patches in certain contexts;
i'll re-spin without it;
>
> > + }
> > +
> > + reg |= ADIN1300_GE_RMII_EN;
> > +
> > +write:
> > + return phy_write_mmd(phydev, MDIO_MMD_VEND1,
> > + ADIN1300_GE_RMII_CFG_REG, reg);
> > +}
> > +
> > static int adin_config_init(struct phy_device *phydev)
> > {
> > - int rc;
> > + phy_interface_t interface, rc;
>
> genphy_config_init() does not return a phy_interface_t!
good point;
will check;
>
> >
> > rc = genphy_config_init(phydev);
> > if (rc < 0)
> > return rc;
> >
> > + interface = phydev->interface;
> > +
> > + rc = adin_config_rgmii_mode(phydev, interface);
> > + if (rc < 0)
> > + return rc;
> > +
> > + rc = adin_config_rmii_mode(phydev, interface);
> > + if (rc < 0)
> > + return rc;
> > +
> > + dev_info(&phydev->mdio.dev, "PHY is using mode '%s'\n",
> > + phy_modes(phydev->interface));
>
> phydev_dbg(), or not at all.
ack
>
> Andrew
^ permalink raw reply
* Re: [PATCH 06/16] net: phy: adin: support PHY mode converters
From: Ardelean, Alexandru @ 2019-08-06 6:47 UTC (permalink / raw)
To: andrew@lunn.ch
Cc: davem@davemloft.net, hkallweit1@gmail.com,
devicetree@vger.kernel.org, mark.rutland@arm.com,
linux-kernel@vger.kernel.org, f.fainelli@gmail.com,
netdev@vger.kernel.org, robh+dt@kernel.org
In-Reply-To: <20190805145105.GN24275@lunn.ch>
On Mon, 2019-08-05 at 16:51 +0200, Andrew Lunn wrote:
> [External]
>
> On Mon, Aug 05, 2019 at 07:54:43PM +0300, Alexandru Ardelean wrote:
> > Sometimes, the connection between a MAC and PHY is done via a
> > mode/interface converter. An example is a GMII-to-RGMII converter, which
> > would mean that the MAC operates in GMII mode while the PHY operates in
> > RGMII. In this case there is a discrepancy between what the MAC expects &
> > what the PHY expects and both need to be configured in their respective
> > modes.
> >
> > Sometimes, this converter is specified via a board/system configuration (in
> > the device-tree for example). But, other times it can be left unspecified.
> > The use of these converters is common in boards that have FPGA on them.
> >
> > This patch also adds support for a `adi,phy-mode-internal` property that
> > can be used in these (implicit convert) cases. The internal PHY mode will
> > be used to specify the correct register settings for the PHY.
> >
> > `fwnode_handle` is used, since this property may be specified via ACPI as
> > well in other setups, but testing has been done in DT context.
>
> Looking at the patch, you seems to assume phy-mode is what the MAC is
> using? That seems rather odd, given the name. It seems like a better
> solution would be to add a mac-mode, which the MAC uses to configure
> its side of the link. The MAC driver would then implement this
> property.
>
actually, that's a pretty good idea;
i guess i was narrow-minded when writing the driver, and got stuck on phy specifics, and forgot about the MAC-side;
[ i also catch these design elements when reviewing, but i also seem to miss them when writing stuff sometimes ]
thanks
> I don't see a need for this. phy-mode indicates what the PHY should
> use. End of story.
>
> Andrew
^ permalink raw reply
* Re: [PATCH 10/16] net: phy: adin: add EEE translation layer for Clause 22
From: Ardelean, Alexandru @ 2019-08-06 6:47 UTC (permalink / raw)
To: andrew@lunn.ch
Cc: davem@davemloft.net, hkallweit1@gmail.com,
devicetree@vger.kernel.org, mark.rutland@arm.com,
linux-kernel@vger.kernel.org, f.fainelli@gmail.com,
netdev@vger.kernel.org, robh+dt@kernel.org
In-Reply-To: <20190805221150.GE25700@lunn.ch>
On Tue, 2019-08-06 at 00:11 +0200, Andrew Lunn wrote:
> [External]
>
> > +static int adin_cl22_to_adin_reg(int devad, u16 cl22_regnum)
> > +{
> > + struct clause22_mmd_map *m;
> > + int i;
> > +
> > + if (devad == MDIO_MMD_VEND1)
> > + return cl22_regnum;
> > +
> > + for (i = 0; i < ARRAY_SIZE(clause22_mmd_map); i++) {
> > + m = &clause22_mmd_map[i];
> > + if (m->devad == devad && m->cl22_regnum == cl22_regnum)
> > + return m->adin_regnum;
> > + }
> > +
> > + pr_err("No translation available for devad: %d reg: %04x\n",
> > + devad, cl22_regnum);
>
> phydev_err().
ack
>
> Andrew
^ permalink raw reply
* Re: [PATCH 11/16] net: phy: adin: PHY reset mechanisms
From: Ardelean, Alexandru @ 2019-08-06 6:50 UTC (permalink / raw)
To: andrew@lunn.ch
Cc: davem@davemloft.net, hkallweit1@gmail.com,
devicetree@vger.kernel.org, mark.rutland@arm.com,
linux-kernel@vger.kernel.org, f.fainelli@gmail.com,
netdev@vger.kernel.org, robh+dt@kernel.org
In-Reply-To: <20190805151500.GP24275@lunn.ch>
On Mon, 2019-08-05 at 17:15 +0200, Andrew Lunn wrote:
> [External]
>
> On Mon, Aug 05, 2019 at 07:54:48PM +0300, Alexandru Ardelean wrote:
> > The ADIN PHYs supports 4 types of reset:
> > 1. The standard PHY reset via BMCR_RESET bit in MII_BMCR reg
> > 2. Reset via GPIO
> > 3. Reset via reg GeSftRst (0xff0c) & reload previous pin configs
> > 4. Reset via reg GeSftRst (0xff0c) & request new pin configs
> >
> > Resets 2 & 4 are almost identical, with the exception that the crystal
> > oscillator is available during reset for 2.
> >
> > Resetting via GeSftRst or via GPIO is useful when doing a warm reboot. If
> > doing various settings via phytool or ethtool, the sub-system registers
> > don't reset just via BMCR_RESET.
> >
> > This change implements resetting the entire PHY subsystem during probe.
> > During PHY HW init (phy_hw_init() logic) the PHY core regs will be reset
> > again via BMCR_RESET. This will also need to happen during a PM resume.
>
> phylib already has support for GPIO reset. So if possible, you should
> not repeat that code here.
>
> What is the difference between a GPIO reset, and a GPIO reset followed
> by a subsystem soft reset?
there shouldn't be any difference;
it's just 2 consecutive resets;
i'll take a closer look at phylib's GPIO reset and see
>
> Andrew
^ permalink raw reply
* Re: [PATCH 12/16] net: phy: adin: read EEE setting from device-tree
From: Ardelean, Alexandru @ 2019-08-06 6:52 UTC (permalink / raw)
To: andrew@lunn.ch
Cc: davem@davemloft.net, hkallweit1@gmail.com,
devicetree@vger.kernel.org, mark.rutland@arm.com,
linux-kernel@vger.kernel.org, f.fainelli@gmail.com,
netdev@vger.kernel.org, robh+dt@kernel.org
In-Reply-To: <20190805151909.GR24275@lunn.ch>
On Mon, 2019-08-05 at 17:19 +0200, Andrew Lunn wrote:
> [External]
>
> On Mon, Aug 05, 2019 at 07:54:49PM +0300, Alexandru Ardelean wrote:
> > By default, EEE is not advertised on system init. This change allows the
> > user to specify a device property to enable EEE advertisements when the PHY
> > initializes.
>
> This patch is not required. If EEE is not being advertised when it
> should, it means there is a MAC driver bug.
ack;
same thing about PHY specifics ignoring MAC specifics
thanks
>
> Andrew
^ permalink raw reply
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