* [RESEND PATCH v5 0/4] add coupled regulators for Exynos5422/5800
From: Kamil Konieczny @ 2019-08-08 9:02 UTC (permalink / raw)
To: k.konieczny
Cc: Bartlomiej Zolnierkiewicz, Marek Szyprowski, Chanwoo Choi,
Krzysztof Kozlowski, Kukjin Kim, Kyungmin Park, Mark Rutland,
MyungJoo Ham, Nishanth Menon, Rob Herring, Stephen Boyd,
Viresh Kumar, devicetree, linux-arm-kernel, linux-kernel,
linux-pm, linux-samsung-soc
In-Reply-To: <CGME20190808090249eucas1p19944820d79ec211c85d9e1285f892f9c@eucas1p1.samsung.com>
Hi,
The main purpose of this patch series is to add coupled regulators for
Exynos5422/5800 to keep constrain on voltage difference between vdd_arm
and vdd_int to be at most 300mV. In exynos-bus instead of using
regulator_set_voltage_tol() with default voltage tolerance it should be
used regulator_set_voltage_triplet() with volatege range, and this is
already present in opp/core.c code, so it can be reused. While at this,
move setting regulators into opp/core.
This patchset was tested on Odroid XU3.
The DTS coupled regulators patch depends on previous patches.
Changes:
v5:
- squashed last patch "remove exynos_bus_passive_target()" into second
- added Acked-by to patch "correct clock enable sequence"
v4:
- removed "opp: core: add regulators enable and disable" from patchset
as it was applied by Viresh Kumar and changed cover letter
- fix patch "devfreq: exynos-bus: correct clock enable sequence" to
correct order of enable/disable
- removed unrelated changes in "devfreq: exynos-bus: convert to use
dev_pm_opp_set_rate()"
- added new patch "devfreq: exynos-bus: remove exynos_bus_passive_target()"
as suggested by Chanwoo Choi
v3:
- added new exynos-bus patch to correct clock and regulator enabling
and disabling sequence as suggested by Chanwoo Choi
- corrected error path in enable and improved commit message in opp/core
- improve comment in devfreq/exynos-bus.c before devfreq_recommended_opp()
- change cover letter as there is new patch
- added note before Signed-off-by in 4th patch
v2:
- improve regulators enable/disable code in opp/core as suggested by
Viresh Kumar
- add new patch for remove unused dt-bindings as suggested by Krzysztof
Kozlowski
Kamil Konieczny (3):
devfreq: exynos-bus: correct clock enable sequence
devfreq: exynos-bus: convert to use dev_pm_opp_set_rate()
dt-bindings: devfreq: exynos-bus: remove unused property
Marek Szyprowski (1):
ARM: dts: exynos: add initial data for coupled regulators for
Exynos5422/5800
.../bindings/devfreq/exynos-bus.txt | 2 -
arch/arm/boot/dts/exynos5420.dtsi | 34 ++--
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 4 +
arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 +
arch/arm/boot/dts/exynos5800.dtsi | 32 ++--
drivers/devfreq/exynos-bus.c | 153 +++++-------------
6 files changed, 78 insertions(+), 151 deletions(-)
--
2.22.0
^ permalink raw reply
* Re: [PATCH v5 0/4] add coupled regulators for Exynos5422/5800
From: Kamil Konieczny @ 2019-08-08 9:01 UTC (permalink / raw)
To: Chanwoo Choi
Cc: Bartlomiej Zolnierkiewicz, Marek Szyprowski, Krzysztof Kozlowski,
Kukjin Kim, Kyungmin Park, Mark Rutland, MyungJoo Ham,
Nishanth Menon, Rob Herring, Stephen Boyd, Viresh Kumar,
devicetree, linux-arm-kernel, linux-kernel, linux-pm,
linux-samsung-soc
In-Reply-To: <6888b704-1971-4832-d7b9-092368c797d0@samsung.com>
Hi Chanwoo,
On 08.08.2019 03:47, Chanwoo Choi wrote:
> Hi Kamil,
>
> When I applied them to testing branch, those don't have the author name
> only just have the email address as following:
> You have to edit the your git author information with your name.
Sorry, I will resend with proper From: info.
> author k.konieczny@partner.samsung.com <k.konieczny@partner.samsung.com> 2019-08-07 15:38:36 +0200
> committer Chanwoo Choi <cw00.choi@samsung.com> 2019-08-08 10:35:16 +0900
> commit 4304f4ecec93cebd255463d56b0a4f112ee9dc50 (patch)
> tree 2859e566d6f68219f71a61e7c412717c1adba4f5
> parent 57d85421038b458dd87ec268404ff608f90c36ae (diff)
> download linux-4304f4ecec93cebd255463d56b0a4f112ee9dc50.tar.gz
>
> Regards,
> Chanwoo Choi
>
> On 19. 8. 7. 오후 10:38, k.konieczny@partner.samsung.com wrote:
>> [...]
--
Best regards,
Kamil Konieczny
Samsung R&D Institute Poland
^ permalink raw reply
* [PATCH 2/2] pwm: sprd: Add Spreadtrum PWM support
From: Baolin Wang @ 2019-08-08 8:59 UTC (permalink / raw)
To: thierry.reding, robh+dt
Cc: mark.rutland, orsonzhai, zhang.lyra, baolin.wang, vincent.guittot,
linux-pwm, devicetree, linux-kernel
In-Reply-To: <6a38a3655bc8100764d85cb04dea5c2546a311e1.1565168564.git.baolin.wang@linaro.org>
From: Neo Hou <neo.hou@unisoc.com>
This patch adds the Spreadtrum PWM support, which provides maximum 4
channels.
Signed-off-by: Neo Hou <neo.hou@unisoc.com>
Co-developed-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
---
drivers/pwm/Kconfig | 10 ++
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-sprd.c | 311 ++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 322 insertions(+)
create mode 100644 drivers/pwm/pwm-sprd.c
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index a7e5751..4963b4d 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -423,6 +423,16 @@ config PWM_SPEAR
To compile this driver as a module, choose M here: the module
will be called pwm-spear.
+config PWM_SPRD
+ tristate "Spreadtrum PWM support"
+ depends on ARCH_SPRD || COMPILE_TEST
+ help
+ Generic PWM framework driver for the PWM controller on
+ Spreadtrum SoCs.
+
+ To compile this driver as a module, choose M here: the module
+ will be called pwm-sprd.
+
config PWM_STI
tristate "STiH4xx PWM support"
depends on ARCH_STI
diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
index 76b555b..26326ad 100644
--- a/drivers/pwm/Makefile
+++ b/drivers/pwm/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
obj-$(CONFIG_PWM_SAMSUNG) += pwm-samsung.o
obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o
obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o
+obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o
obj-$(CONFIG_PWM_STI) += pwm-sti.o
obj-$(CONFIG_PWM_STM32) += pwm-stm32.o
obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o
diff --git a/drivers/pwm/pwm-sprd.c b/drivers/pwm/pwm-sprd.c
new file mode 100644
index 0000000..f6fc793
--- /dev/null
+++ b/drivers/pwm/pwm-sprd.c
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Spreadtrum Communications Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/math64.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+
+#define SPRD_PWM_PRESCALE 0x0
+#define SPRD_PWM_MOD 0x4
+#define SPRD_PWM_DUTY 0x8
+#define SPRD_PWM_DIV 0xc
+#define SPRD_PWM_PAT_LOW 0x10
+#define SPRD_PWM_PAT_HIGH 0x14
+#define SPRD_PWM_ENABLE 0x18
+
+#define SPRD_PWM_MOD_MAX GENMASK(7, 0)
+#define SPRD_PWM_REG_MSK GENMASK(15, 0)
+#define SPRD_PWM_ENABLE_BIT BIT(0)
+
+#define SPRD_PWM_NUM 4
+#define SPRD_PWM_REGS_SHIFT 5
+#define SPRD_PWM_NUM_CLKS 2
+#define SPRD_PWM_DEFAULT_CLK 26000000UL
+
+struct sprd_pwm_chn {
+ struct clk_bulk_data clks[SPRD_PWM_NUM_CLKS];
+ unsigned long clk_rate;
+ bool clk_enabled;
+};
+
+struct sprd_pwm_chip {
+ void __iomem *base;
+ struct device *dev;
+ struct pwm_chip chip;
+ int num_pwms;
+ struct sprd_pwm_chn chn[SPRD_PWM_NUM];
+};
+
+/* list of clocks required by PWM channels */
+static const char * const sprd_pwm_clks[] = {
+ "enable0", "pwm0",
+ "enable1", "pwm1",
+ "enable2", "pwm2",
+ "enable3", "pwm3",
+};
+
+static u32 sprd_pwm_read(struct sprd_pwm_chip *chip, u32 num, u32 reg)
+{
+ u32 offset = reg + (num << SPRD_PWM_REGS_SHIFT);
+
+ return readl_relaxed(chip->base + offset);
+}
+
+static void sprd_pwm_write(struct sprd_pwm_chip *chip, u32 num,
+ u32 reg, u32 val)
+{
+ u32 offset = reg + (num << SPRD_PWM_REGS_SHIFT);
+
+ writel_relaxed(val, chip->base + offset);
+}
+
+static int sprd_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
+ int duty_ns, int period_ns)
+{
+ struct sprd_pwm_chip *spc =
+ container_of(chip, struct sprd_pwm_chip, chip);
+ struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
+ u64 div, tmp;
+ u32 prescale, duty;
+ int ret;
+
+ /*
+ * NOTE: the clocks to PWM channel has to be enabled first before
+ * writing to the registers.
+ */
+ if (!chn->clk_enabled) {
+ ret = clk_bulk_prepare_enable(SPRD_PWM_NUM_CLKS, chn->clks);
+ if (ret) {
+ dev_err(spc->dev, "failed to enable pwm%u clock\n",
+ pwm->hwpwm);
+ return ret;
+ }
+
+ chn->clk_enabled = true;
+ }
+
+ duty = duty_ns * SPRD_PWM_MOD_MAX / period_ns;
+
+ /*
+ * According to the datasheet, the period_ns calculation formula
+ * should be:
+ * period_ns = 10^9 * (prescale + 1) * mod / clk_rate
+ *
+ * Then we can get the prescale formula:
+ * prescale = (period_ns * clk_rate) / (10^9 * mod) -1
+ */
+ tmp = chn->clk_rate * period_ns;
+ div = 1000000000ULL * SPRD_PWM_MOD_MAX;
+ prescale = div64_u64(tmp, div) - 1;
+
+ sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_MOD, SPRD_PWM_MOD_MAX);
+ sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_DUTY, duty);
+ sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PAT_LOW, SPRD_PWM_REG_MSK);
+ sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PAT_HIGH, SPRD_PWM_REG_MSK);
+ sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_PRESCALE, prescale);
+
+ return 0;
+}
+
+static int sprd_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ struct sprd_pwm_chip *spc =
+ container_of(chip, struct sprd_pwm_chip, chip);
+ struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
+ int ret;
+
+ if (!chn->clk_enabled) {
+ ret = clk_bulk_prepare_enable(SPRD_PWM_NUM_CLKS, chn->clks);
+ if (ret) {
+ dev_err(spc->dev, "failed to enable pwm%u clocks\n",
+ pwm->hwpwm);
+ return ret;
+ }
+
+ chn->clk_enabled = true;
+ }
+
+ sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 1);
+
+ return 0;
+}
+
+static void sprd_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
+{
+ struct sprd_pwm_chip *spc =
+ container_of(chip, struct sprd_pwm_chip, chip);
+ struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
+
+ sprd_pwm_write(spc, pwm->hwpwm, SPRD_PWM_ENABLE, 0);
+
+ if (chn->clk_enabled) {
+ clk_bulk_disable_unprepare(SPRD_PWM_NUM_CLKS, chn->clks);
+ chn->clk_enabled = false;
+ }
+}
+
+static void sprd_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
+ struct pwm_state *state)
+{
+ struct sprd_pwm_chip *spc =
+ container_of(chip, struct sprd_pwm_chip, chip);
+ struct sprd_pwm_chn *chn = &spc->chn[pwm->hwpwm];
+ u32 enabled, duty, prescale;
+ u64 tmp;
+ int ret;
+
+ ret = clk_bulk_prepare_enable(SPRD_PWM_NUM_CLKS, chn->clks);
+ if (ret) {
+ dev_err(spc->dev, "failed to enable pwm%u clocks\n",
+ pwm->hwpwm);
+ return;
+ }
+
+ chn->clk_enabled = true;
+
+ duty = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_DUTY) & SPRD_PWM_REG_MSK;
+ prescale = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_PRESCALE) & SPRD_PWM_REG_MSK;
+ enabled = sprd_pwm_read(spc, pwm->hwpwm, SPRD_PWM_ENABLE) & SPRD_PWM_ENABLE_BIT;
+
+ /*
+ * According to the datasheet, the period_ns and duty_ns calculation
+ * formula should be:
+ * period_ns = 10^9 * (prescale + 1) * mod / clk_rate
+ * duty_ns = 10^9 * (prescale + 1) * duty / clk_rate
+ */
+ tmp = (prescale + 1) * 1000000000ULL * SPRD_PWM_MOD_MAX;
+ state->period = div64_u64(tmp, chn->clk_rate);
+
+ tmp = (prescale + 1) * 1000000000ULL * duty;
+ state->duty_cycle = div64_u64(tmp, chn->clk_rate);
+
+ state->enabled = !!enabled;
+
+ /* Disable PWM clocks if the PWM channel is not in enable state. */
+ if (!enabled) {
+ clk_bulk_disable_unprepare(SPRD_PWM_NUM_CLKS, chn->clks);
+ chn->clk_enabled = false;
+ }
+}
+
+static const struct pwm_ops sprd_pwm_ops = {
+ .config = sprd_pwm_config,
+ .enable = sprd_pwm_enable,
+ .disable = sprd_pwm_disable,
+ .get_state = sprd_pwm_get_state,
+ .owner = THIS_MODULE,
+};
+
+static int sprd_pwm_clk_init(struct sprd_pwm_chip *spc)
+{
+ struct clk *clk_parent, *clk_pwm;
+ int ret, i, clk_index = 0;
+
+ clk_parent = devm_clk_get(spc->dev, "source");
+ if (IS_ERR(clk_parent)) {
+ dev_err(spc->dev, "failed to get source clock\n");
+ return PTR_ERR(clk_parent);
+ }
+
+ for (i = 0; i < SPRD_PWM_NUM; i++) {
+ struct sprd_pwm_chn *chn = &spc->chn[i];
+ int j;
+
+ for (j = 0; j < SPRD_PWM_NUM_CLKS; ++j)
+ chn->clks[j].id = sprd_pwm_clks[clk_index++];
+
+ ret = devm_clk_bulk_get(spc->dev, SPRD_PWM_NUM_CLKS, chn->clks);
+ if (ret) {
+ if (ret == -ENOENT)
+ break;
+
+ dev_err(spc->dev, "failed to get channel clocks\n");
+ return ret;
+ }
+
+ clk_pwm = chn->clks[1].clk;
+ if (!clk_set_parent(clk_pwm, clk_parent))
+ chn->clk_rate = clk_get_rate(clk_pwm);
+ else
+ chn->clk_rate = SPRD_PWM_DEFAULT_CLK;
+ }
+
+ if (!i) {
+ dev_err(spc->dev, "no availbale PWM channels\n");
+ return -EINVAL;
+ }
+
+ spc->num_pwms = i;
+
+ return 0;
+}
+
+static int sprd_pwm_probe(struct platform_device *pdev)
+{
+ struct sprd_pwm_chip *spc;
+ int ret;
+
+ spc = devm_kzalloc(&pdev->dev, sizeof(*spc), GFP_KERNEL);
+ if (!spc)
+ return -ENOMEM;
+
+ spc->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(spc->base))
+ return PTR_ERR(spc->base);
+
+ spc->dev = &pdev->dev;
+ ret = sprd_pwm_clk_init(spc);
+ if (ret)
+ return ret;
+
+ spc->chip.dev = &pdev->dev;
+ spc->chip.ops = &sprd_pwm_ops;
+ spc->chip.base = -1;
+ spc->chip.npwm = spc->num_pwms;
+
+ ret = pwmchip_add(&spc->chip);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to add PWM chip\n");
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, spc);
+ return 0;
+}
+
+static int sprd_pwm_remove(struct platform_device *pdev)
+{
+ struct sprd_pwm_chip *spc = platform_get_drvdata(pdev);
+ int i;
+
+ for (i = 0; i < spc->num_pwms; i++)
+ pwm_disable(&spc->chip.pwms[i]);
+
+ return pwmchip_remove(&spc->chip);
+}
+
+static const struct of_device_id sprd_pwm_of_match[] = {
+ { .compatible = "sprd,ums512-pwm", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, sprd_pwm_of_match);
+
+static struct platform_driver sprd_pwm_driver = {
+ .driver = {
+ .name = "sprd-pwm",
+ .of_match_table = sprd_pwm_of_match,
+ },
+ .probe = sprd_pwm_probe,
+ .remove = sprd_pwm_remove,
+};
+
+module_platform_driver(sprd_pwm_driver);
+
+MODULE_DESCRIPTION("Spreadtrum PWM Driver");
+MODULE_LICENSE("GPL v2");
--
1.7.9.5
^ permalink raw reply related
* [PATCH 1/2] dt-bindings: pwm: sprd: Add Spreadtrum PWM documentation
From: Baolin Wang @ 2019-08-08 8:59 UTC (permalink / raw)
To: thierry.reding, robh+dt
Cc: mark.rutland, orsonzhai, zhang.lyra, baolin.wang, vincent.guittot,
linux-pwm, devicetree, linux-kernel
Add Spreadtrum PWM controller documentation.
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
---
Documentation/devicetree/bindings/pwm/pwm-sprd.txt | 31 ++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/pwm-sprd.txt
diff --git a/Documentation/devicetree/bindings/pwm/pwm-sprd.txt b/Documentation/devicetree/bindings/pwm/pwm-sprd.txt
new file mode 100644
index 0000000..e8e0d5a
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/pwm-sprd.txt
@@ -0,0 +1,31 @@
+Spreadtrum PWM controller
+
+Spreadtrum SoCs PWM controller provides 4 PWM channels.
+
+Required porperties:
+- compatible : Should be "sprd,ums512-pwm".
+- reg: Physical base address and length of the controller's registers.
+- clocks: The phandle and specifier referencing the controller's clocks.
+- clock-names: Should contain following entries:
+ "source": for PWM source (parent) clock.
+ "pwmn": used to derive the functional clock for PWM channel n (n range: 0 ~ 3).
+ "enablen": for PWM channel n enable clock (n range: 0 ~ 3).
+- #pwm-cells: Should be 2. See pwm.txt in this directory for a description of
+ the cells format.
+
+Example:
+ pwms: pwm@32260000 {
+ compatible = "sprd,ums512-pwm";
+ reg = <0 0x32260000 0 0x10000>;
+ clock-names = "source",
+ "pwm0", "enable0",
+ "pwm1", "enable1",
+ "pwm2", "enable2",
+ "pwm3", "enable3";
+ clocks = <&ext_26m>,
+ <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>,
+ <&aon_clk CLK_PWM1>, <&aonapb_gate CLK_PWM1_EB>,
+ <&aon_clk CLK_PWM2>, <&aonapb_gate CLK_PWM2_EB>,
+ <&aon_clk CLK_PWM3>, <&aonapb_gate CLK_PWM3_EB>;
+ #pwm-cells = <2>;
+ };
--
1.7.9.5
^ permalink raw reply related
* Re: [PATCH] dt-bindings: rcar-imr: Rename bindings documentation file
From: Geert Uytterhoeven @ 2019-08-08 8:58 UTC (permalink / raw)
To: Simon Horman
Cc: Mauro Carvalho Chehab, Rob Herring, Mark Rutland, Magnus Damm,
Geert Uytterhoeven, Linux Media Mailing List,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas, Niklas Söderlund
In-Reply-To: <CAMuHMdUkogXnd6_H_q=STyVS0zxpKYif_iJH0pw753onCeU3gw@mail.gmail.com>
On Mon, Jul 29, 2019 at 10:31 AM Geert Uytterhoeven
<geert@linux-m68k.org> wrote:
> On Mon, Jul 29, 2019 at 9:48 AM Simon Horman <horms+renesas@verge.net.au> wrote:
> > Renesas media binding documentation files uses a naming schema of
>
> use
>
> > 'renesas,<module>.txt'. Rename IMR file to match this pattern.
>
> the IMR file?
>
> >
> > Cc: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, queued in renesas-devel/renesas-dt-bindings-for-v5.4 with the above
fixed.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v3] dt-bindings: rcar-{csi2,vin}: Rename bindings documentation files
From: Geert Uytterhoeven @ 2019-08-08 8:57 UTC (permalink / raw)
To: Niklas Söderlund
Cc: Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Media Mailing List, Linux-Renesas, Geert Uytterhoeven,
Ulrich Hecht, Simon Horman
In-Reply-To: <20190808010330.19515-1-niklas.soderlund+renesas@ragnatech.se>
Hi Niklas,
On Thu, Aug 8, 2019 at 3:04 AM Niklas Söderlund
<niklas.soderlund+renesas@ragnatech.se> wrote:
> Renesas media binding documentation files uses a naming schema of
> 'renesas,<module>.txt'. Rename VIN and CSI-2 files to match this
> pattern.
>
> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> .../media/{renesas,rcar-csi2.txt => renesas,csi2.txt} | 0
> .../bindings/media/{rcar_vin.txt => renesas,vin.txt} | 0
> MAINTAINERS | 4 ++--
> 3 files changed, 2 insertions(+), 2 deletions(-)
> rename Documentation/devicetree/bindings/media/{renesas,rcar-csi2.txt => renesas,csi2.txt} (100%)
> rename Documentation/devicetree/bindings/media/{rcar_vin.txt => renesas,vin.txt} (100%)
>
> ---
>
> Hi Geert,
>
> Would you be willing to take this patch in your renesas tree? There
> seems to be a lack of interest in it :-(
Thanks, queued in renesas-devel/renesas-dt-bindings-for-v5.4.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH v3 3/3] MAINTAINERS: Update with Amlogic DRM bindings converted as YAML
From: Neil Armstrong @ 2019-08-08 8:55 UTC (permalink / raw)
To: robh+dt; +Cc: devicetree, linux-amlogic, linux-kernel, dri-devel,
Neil Armstrong
In-Reply-To: <20190808085522.21950-1-narmstrong@baylibre.com>
The amlogic,meson-dw-hdmi.txt and amlogic,meson-vpu.txt has been
converted to YAML schemas, update MAINTAINERS to match them again.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6426db5198f0..c55c18531cd1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5318,8 +5318,8 @@ L: linux-amlogic@lists.infradead.org
W: http://linux-meson.com/
S: Supported
F: drivers/gpu/drm/meson/
-F: Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt
-F: Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt
+F: Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
+F: Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
F: Documentation/gpu/meson.rst
T: git git://anongit.freedesktop.org/drm/drm-misc
--
2.22.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* [PATCH v3 2/3] dt-bindings: display: amlogic,meson-vpu: convert to yaml
From: Neil Armstrong @ 2019-08-08 8:55 UTC (permalink / raw)
To: robh+dt; +Cc: Neil Armstrong, devicetree, dri-devel, linux-amlogic,
linux-kernel
In-Reply-To: <20190808085522.21950-1-narmstrong@baylibre.com>
Now that we have the DT validation in place, let's convert the device tree
bindings for the Amlogic Display Controller over to YAML schemas.
The original example has a leftover "dmc" memory cell, that has been
removed in the yaml rewrite.
The port connection table has been dropped in favor of a description
of each port.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../bindings/display/amlogic,meson-vpu.txt | 121 ----------------
.../bindings/display/amlogic,meson-vpu.yaml | 137 ++++++++++++++++++
2 files changed, 137 insertions(+), 121 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt
create mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt
deleted file mode 100644
index be40a780501c..000000000000
--- a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt
+++ /dev/null
@@ -1,121 +0,0 @@
-Amlogic Meson Display Controller
-================================
-
-The Amlogic Meson Display controller is composed of several components
-that are going to be documented below:
-
-DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
- | vd1 _______ _____________ _________________ | |
-D |-------| |----| | | | | HDMI PLL |
-D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
-R |-------| |----| Processing | | | | |
- | osd2 | | | |---| Enci ----------|----|-----VDAC------|
-R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----|
-A | osd1 | | | Blenders | | Encl ----------|----|---------------|
-M |-------|______|----|____________| |________________| | |
-___|__________________________________________________________|_______________|
-
-
-VIU: Video Input Unit
----------------------
-
-The Video Input Unit is in charge of the pixel scanout from the DDR memory.
-It fetches the frames addresses, stride and parameters from the "Canvas" memory.
-This part is also in charge of the CSC (Colorspace Conversion).
-It can handle 2 OSD Planes and 2 Video Planes.
-
-VPP: Video Post Processing
---------------------------
-
-The Video Post Processing is in charge of the scaling and blending of the
-various planes into a single pixel stream.
-There is a special "pre-blending" used by the video planes with a dedicated
-scaler and a "post-blending" to merge with the OSD Planes.
-The OSD planes also have a dedicated scaler for one of the OSD.
-
-VENC: Video Encoders
---------------------
-
-The VENC is composed of the multiple pixel encoders :
- - ENCI : Interlace Video encoder for CVBS and Interlace HDMI
- - ENCP : Progressive Video Encoder for HDMI
- - ENCL : LCD LVDS Encoder
-The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
-tree and provides the scanout clock to the VPP and VIU.
-The ENCI is connected to a single VDAC for Composite Output.
-The ENCI and ENCP are connected to an on-chip HDMI Transceiver.
-
-Device Tree Bindings:
----------------------
-
-VPU: Video Processing Unit
---------------------------
-
-Required properties:
-- compatible: value should be different for each SoC family as :
- - GXBB (S905) : "amlogic,meson-gxbb-vpu"
- - GXL (S905X, S905D) : "amlogic,meson-gxl-vpu"
- - GXM (S912) : "amlogic,meson-gxm-vpu"
- followed by the common "amlogic,meson-gx-vpu"
- - G12A (S905X2, S905Y2, S905D2) : "amlogic,meson-g12a-vpu"
-- reg: base address and size of he following memory-mapped regions :
- - vpu
- - hhi
-- reg-names: should contain the names of the previous memory regions
-- interrupts: should contain the VENC Vsync interrupt number
-- amlogic,canvas: phandle to canvas provider node as described in the file
- ../soc/amlogic/amlogic,canvas.txt
-
-Optional properties:
-- power-domains: Optional phandle to associated power domain as described in
- the file ../power/power_domain.txt
-
-Required nodes:
-
-The connections to the VPU output video ports are modeled using the OF graph
-bindings specified in Documentation/devicetree/bindings/graph.txt.
-
-The following table lists for each supported model the port number
-corresponding to each VPU output.
-
- Port 0 Port 1
------------------------------------------
- S905 (GXBB) CVBS VDAC HDMI-TX
- S905X (GXL) CVBS VDAC HDMI-TX
- S905D (GXL) CVBS VDAC HDMI-TX
- S912 (GXM) CVBS VDAC HDMI-TX
- S905X2 (G12A) CVBS VDAC HDMI-TX
- S905Y2 (G12A) CVBS VDAC HDMI-TX
- S905D2 (G12A) CVBS VDAC HDMI-TX
-
-Example:
-
-tv-connector {
- compatible = "composite-video-connector";
-
- port {
- tv_connector_in: endpoint {
- remote-endpoint = <&cvbs_vdac_out>;
- };
- };
-};
-
-vpu: vpu@d0100000 {
- compatible = "amlogic,meson-gxbb-vpu";
- reg = <0x0 0xd0100000 0x0 0x100000>,
- <0x0 0xc883c000 0x0 0x1000>,
- <0x0 0xc8838000 0x0 0x1000>;
- reg-names = "vpu", "hhi", "dmc";
- interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* CVBS VDAC output port */
- port@0 {
- reg = <0>;
-
- cvbs_vdac_out: endpoint {
- remote-endpoint = <&tv_connector_in>;
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
new file mode 100644
index 000000000000..d1205a6697a0
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
@@ -0,0 +1,137 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 BayLibre, SAS
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic Meson Display Controller
+
+maintainers:
+ - Neil Armstrong <narmstrong@baylibre.com>
+
+description: |
+ The Amlogic Meson Display controller is composed of several components
+ that are going to be documented below
+
+ DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
+ | vd1 _______ _____________ _________________ | |
+ D |-------| |----| | | | | HDMI PLL |
+ D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
+ R |-------| |----| Processing | | | | |
+ | osd2 | | | |---| Enci ----------|----|-----VDAC------|
+ R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----|
+ A | osd1 | | | Blenders | | Encl ----------|----|---------------|
+ M |-------|______|----|____________| |________________| | |
+ ___|__________________________________________________________|_______________|
+
+
+ VIU: Video Input Unit
+ ---------------------
+
+ The Video Input Unit is in charge of the pixel scanout from the DDR memory.
+ It fetches the frames addresses, stride and parameters from the "Canvas" memory.
+ This part is also in charge of the CSC (Colorspace Conversion).
+ It can handle 2 OSD Planes and 2 Video Planes.
+
+ VPP: Video Post Processing
+ --------------------------
+
+ The Video Post Processing is in charge of the scaling and blending of the
+ various planes into a single pixel stream.
+ There is a special "pre-blending" used by the video planes with a dedicated
+ scaler and a "post-blending" to merge with the OSD Planes.
+ The OSD planes also have a dedicated scaler for one of the OSD.
+
+ VENC: Video Encoders
+ --------------------
+
+ The VENC is composed of the multiple pixel encoders
+ - ENCI : Interlace Video encoder for CVBS and Interlace HDMI
+ - ENCP : Progressive Video Encoder for HDMI
+ - ENCL : LCD LVDS Encoder
+ The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
+ tree and provides the scanout clock to the VPP and VIU.
+ The ENCI is connected to a single VDAC for Composite Output.
+ The ENCI and ENCP are connected to an on-chip HDMI Transceiver.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - amlogic,meson-gxbb-vpu # GXBB (S905)
+ - amlogic,meson-gxl-vpu # GXL (S905X, S905D)
+ - amlogic,meson-gxm-vpu # GXM (S912)
+ - const: amlogic,meson-gx-vpu
+ - enum:
+ - amlogic,meson-g12a-vpu # G12A (S905X2, S905Y2, S905D2)
+
+ reg:
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: vpu
+ - const: hhi
+
+ interrupts:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+ description: phandle to the associated power domain
+
+ port@0:
+ type: object
+ description:
+ A port node pointing to the CVBS VDAC port node.
+
+ port@1:
+ type: object
+ description:
+ A port node pointing to the HDMI-TX port node.
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - port@0
+ - port@1
+ - "#address-cells"
+ - "#size-cells"
+
+examples:
+ - |
+ vpu: vpu@d0100000 {
+ compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
+ reg = <0xd0100000 0x100000>, <0xc883c000 0x1000>;
+ reg-names = "vpu", "hhi";
+ interrupts = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* CVBS VDAC output port */
+ port@0 {
+ reg = <0>;
+
+ cvbs_vdac_out: endpoint {
+ remote-endpoint = <&tv_connector_in>;
+ };
+ };
+
+ /* HDMI TX output port */
+ port@1 {
+ reg = <1>;
+
+ hdmi_tx_out: endpoint {
+ remote-endpoint = <&hdmi_tx_in>;
+ };
+ };
+ };
--
2.22.0
^ permalink raw reply related
* [PATCH v3 1/3] dt-bindings: display: amlogic, meson-dw-hdmi: convert to yaml
From: Neil Armstrong @ 2019-08-08 8:55 UTC (permalink / raw)
To: robh+dt; +Cc: devicetree, Neil Armstrong, linux-kernel, dri-devel,
linux-amlogic
In-Reply-To: <20190808085522.21950-1-narmstrong@baylibre.com>
Now that we have the DT validation in place, let's convert the device tree
bindings for the Amlogic Synopsys DW-HDMI specifics over to YAML schemas.
The original example and usage of clock-names uses a reversed "isfr"
and "iahb" clock-names, the rewritten YAML bindings uses the reversed
instead of fixing the device trees order.
The #sound-dai-cells optional property has been added to match this node
as a sound dai.
The port connection table has been dropped in favor of a description
of each port.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../display/amlogic,meson-dw-hdmi.txt | 119 --------------
.../display/amlogic,meson-dw-hdmi.yaml | 150 ++++++++++++++++++
2 files changed, 150 insertions(+), 119 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt
create mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt
deleted file mode 100644
index 3a50a7862cf3..000000000000
--- a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt
+++ /dev/null
@@ -1,119 +0,0 @@
-Amlogic specific extensions to the Synopsys Designware HDMI Controller
-======================================================================
-
-The Amlogic Meson Synopsys Designware Integration is composed of :
-- A Synopsys DesignWare HDMI Controller IP
-- A TOP control block controlling the Clocks and PHY
-- A custom HDMI PHY in order to convert video to TMDS signal
- ___________________________________
-| HDMI TOP |<= HPD
-|___________________________________|
-| | |
-| Synopsys HDMI | HDMI PHY |=> TMDS
-| Controller |________________|
-|___________________________________|<=> DDC
-
-The HDMI TOP block only supports HPD sensing.
-The Synopsys HDMI Controller interrupt is routed through the
-TOP Block interrupt.
-Communication to the TOP Block and the Synopsys HDMI Controller is done
-via a pair of dedicated addr+read/write registers.
-The HDMI PHY is configured by registers in the HHI register block.
-
-Pixel data arrives in 4:4:4 format from the VENC block and the VPU HDMI mux
-selects either the ENCI encoder for the 576i or 480i formats or the ENCP
-encoder for all the other formats including interlaced HD formats.
-
-The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate
-DVI timings for the HDMI controller.
-
-Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare
-HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF
-audio source interfaces.
-
-Required properties:
-- compatible: value should be different for each SoC family as :
- - GXBB (S905) : "amlogic,meson-gxbb-dw-hdmi"
- - GXL (S905X, S905D) : "amlogic,meson-gxl-dw-hdmi"
- - GXM (S912) : "amlogic,meson-gxm-dw-hdmi"
- followed by the common "amlogic,meson-gx-dw-hdmi"
- - G12A (S905X2, S905Y2, S905D2) : "amlogic,meson-g12a-dw-hdmi"
-- reg: Physical base address and length of the controller's registers.
-- interrupts: The HDMI interrupt number
-- clocks, clock-names : must have the phandles to the HDMI iahb and isfr clocks,
- and the Amlogic Meson venci clocks as described in
- Documentation/devicetree/bindings/clock/clock-bindings.txt,
- the clocks are soc specific, the clock-names should be "iahb", "isfr", "venci"
-- resets, resets-names: must have the phandles to the HDMI apb, glue and phy
- resets as described in :
- Documentation/devicetree/bindings/reset/reset.txt,
- the reset-names should be "hdmitx_apb", "hdmitx", "hdmitx_phy"
-
-Optional properties:
-- hdmi-supply: Optional phandle to an external 5V regulator to power the HDMI
- logic, as described in the file ../regulator/regulator.txt
-
-Required nodes:
-
-The connections to the HDMI ports are modeled using the OF graph
-bindings specified in Documentation/devicetree/bindings/graph.txt.
-
-The following table lists for each supported model the port number
-corresponding to each HDMI output and input.
-
- Port 0 Port 1
------------------------------------------
- S905 (GXBB) VENC Input TMDS Output
- S905X (GXL) VENC Input TMDS Output
- S905D (GXL) VENC Input TMDS Output
- S912 (GXM) VENC Input TMDS Output
- S905X2 (G12A) VENC Input TMDS Output
- S905Y2 (G12A) VENC Input TMDS Output
- S905D2 (G12A) VENC Input TMDS Output
-
-Example:
-
-hdmi-connector {
- compatible = "hdmi-connector";
- type = "a";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&hdmi_tx_tmds_out>;
- };
- };
-};
-
-hdmi_tx: hdmi-tx@c883a000 {
- compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
- reg = <0x0 0xc883a000 0x0 0x1c>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
- resets = <&reset RESET_HDMITX_CAPB3>,
- <&reset RESET_HDMI_SYSTEM_RESET>,
- <&reset RESET_HDMI_TX>;
- reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
- clocks = <&clkc CLKID_HDMI_PCLK>,
- <&clkc CLKID_CLK81>,
- <&clkc CLKID_GCLK_VENCI_INT0>;
- clock-names = "isfr", "iahb", "venci";
- #address-cells = <1>;
- #size-cells = <0>;
-
- /* VPU VENC Input */
- hdmi_tx_venc_port: port@0 {
- reg = <0>;
-
- hdmi_tx_in: endpoint {
- remote-endpoint = <&hdmi_tx_out>;
- };
- };
-
- /* TMDS Output */
- hdmi_tx_tmds_port: port@1 {
- reg = <1>;
-
- hdmi_tx_tmds_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
new file mode 100644
index 000000000000..fb747682006d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
@@ -0,0 +1,150 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 BayLibre, SAS
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic specific extensions to the Synopsys Designware HDMI Controller
+
+maintainers:
+ - Neil Armstrong <narmstrong@baylibre.com>
+
+description: |
+ The Amlogic Meson Synopsys Designware Integration is composed of
+ - A Synopsys DesignWare HDMI Controller IP
+ - A TOP control block controlling the Clocks and PHY
+ - A custom HDMI PHY in order to convert video to TMDS signal
+ ___________________________________
+ | HDMI TOP |<= HPD
+ |___________________________________|
+ | | |
+ | Synopsys HDMI | HDMI PHY |=> TMDS
+ | Controller |________________|
+ |___________________________________|<=> DDC
+
+ The HDMI TOP block only supports HPD sensing.
+ The Synopsys HDMI Controller interrupt is routed through the
+ TOP Block interrupt.
+ Communication to the TOP Block and the Synopsys HDMI Controller is done
+ via a pair of dedicated addr+read/write registers.
+ The HDMI PHY is configured by registers in the HHI register block.
+
+ Pixel data arrives in "4:4:4" format from the VENC block and the VPU HDMI mux
+ selects either the ENCI encoder for the 576i or 480i formats or the ENCP
+ encoder for all the other formats including interlaced HD formats.
+
+ The VENC uses a DVI encoder on top of the ENCI or ENCP encoders to generate
+ DVI timings for the HDMI controller.
+
+ Amlogic Meson GXBB, GXL and GXM SoCs families embeds the Synopsys DesignWare
+ HDMI TX IP version 2.01a with HDCP and I2C & S/PDIF
+ audio source interfaces.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - amlogic,meson-gxbb-dw-hdmi # GXBB (S905)
+ - amlogic,meson-gxl-dw-hdmi # GXL (S905X, S905D)
+ - amlogic,meson-gxm-dw-hdmi # GXM (S912)
+ - const: amlogic,meson-gx-dw-hdmi
+ - enum:
+ - amlogic,meson-g12a-dw-hdmi # G12A (S905X2, S905Y2, S905D2)
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 3
+
+ clock-names:
+ items:
+ - const: isfr
+ - const: iahb
+ - const: venci
+
+ resets:
+ minItems: 3
+
+ reset-names:
+ items:
+ - const: hdmitx_apb
+ - const: hdmitx
+ - const: hdmitx_phy
+
+ hdmi-supply:
+ description: phandle to an external 5V regulator to power the HDMI logic
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/phandle
+
+ port@0:
+ type: object
+ description:
+ A port node pointing to the VENC Input port node.
+
+ port@1:
+ type: object
+ description:
+ A port node pointing to the TMDS Output port node.
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ "#sound-dai-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - port@0
+ - port@1
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ hdmi_tx: hdmi-tx@c883a000 {
+ compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
+ reg = <0xc883a000 0x1c>;
+ interrupts = <57>;
+ resets = <&reset_apb>, <&reset_hdmitx>, <&reset_hdmitx_phy>;
+ reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
+ clocks = <&clk_isfr>, <&clk_iahb>, <&clk_venci>;
+ clock-names = "isfr", "iahb", "venci";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* VPU VENC Input */
+ hdmi_tx_venc_port: port@0 {
+ reg = <0>;
+
+ hdmi_tx_in: endpoint {
+ remote-endpoint = <&hdmi_tx_out>;
+ };
+ };
+
+ /* TMDS Output */
+ hdmi_tx_tmds_port: port@1 {
+ reg = <1>;
+
+ hdmi_tx_tmds_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+
--
2.22.0
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* [PATCH v3 0/3] drm/meson: convert bindings to YAML schemas
From: Neil Armstrong @ 2019-08-08 8:55 UTC (permalink / raw)
To: robh+dt; +Cc: Neil Armstrong, devicetree, dri-devel, linux-amlogic,
linux-kernel
This patchset converts the existing text bindings to YAML schemas.
Those bindings have a lot of texts, thus is interesting to convert.
All have been tested using :
$ make ARCH=arm64 dtbs_check
Issues with the amlogic arm64 DTs has already been identified thanks
to the validation scripts. The DT fixes will be pushed once these yaml
bindings are acked.
Changes since v2:
- Added review tag on amlogic,meson-dw-hdmi.yaml
- Removed power-domains type from amlogic,meson-vpu.yaml
Neil Armstrong (3):
dt-bindings: display: amlogic,meson-dw-hdmi: convert to yaml
dt-bindings: display: amlogic,meson-vpu: convert to yaml
MAINTAINERS: Update with Amlogic DRM bindings converted as YAML
.../display/amlogic,meson-dw-hdmi.txt | 119 --------------
.../display/amlogic,meson-dw-hdmi.yaml | 150 ++++++++++++++++++
.../bindings/display/amlogic,meson-vpu.txt | 121 --------------
.../bindings/display/amlogic,meson-vpu.yaml | 137 ++++++++++++++++
MAINTAINERS | 4 +-
5 files changed, 289 insertions(+), 242 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.txt
create mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml
delete mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt
create mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
--
2.22.0
^ permalink raw reply
* [PATCH 9/9] dt-bindings: watchdog: meson-gxbb-wdt: convert to yaml
From: Neil Armstrong @ 2019-08-08 8:51 UTC (permalink / raw)
To: robh+dt
Cc: Rob Herring, linux-watchdog, devicetree, Neil Armstrong,
Guenter Roeck, linux-amlogic, linux-arm-kernel
In-Reply-To: <20190808085139.21438-1-narmstrong@baylibre.com>
Now that we have the DT validation in place, let's convert the device tree
bindings for the Amlogic GXBB Watchdog timer over to a YAML schemas.
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../watchdog/amlogic,meson-gxbb-wdt.yaml | 37 +++++++++++++++++++
.../bindings/watchdog/meson-gxbb-wdt.txt | 16 --------
2 files changed, 37 insertions(+), 16 deletions(-)
create mode 100644 Documentation/devicetree/bindings/watchdog/amlogic,meson-gxbb-wdt.yaml
delete mode 100644 Documentation/devicetree/bindings/watchdog/meson-gxbb-wdt.txt
diff --git a/Documentation/devicetree/bindings/watchdog/amlogic,meson-gxbb-wdt.yaml b/Documentation/devicetree/bindings/watchdog/amlogic,meson-gxbb-wdt.yaml
new file mode 100644
index 000000000000..d7352f709b37
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/amlogic,meson-gxbb-wdt.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 BayLibre, SAS
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/watchdog/amlogic,meson-gxbb-wdt.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Meson GXBB SoCs Watchdog timer
+
+maintainers:
+ - Neil Armstrong <narmstrong@baylibre.com>
+
+properties:
+ compatible:
+ enum:
+ - amlogic,meson-gxbb-wdt
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description:
+ A phandle to the clock of this PHY
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+examples:
+ - |
+ watchdog@98d0 {
+ compatible = "amlogic,meson-gxbb-wdt";
+ reg = <0x98d0 0x10>;
+ clocks = <&xtal>;
+ };
diff --git a/Documentation/devicetree/bindings/watchdog/meson-gxbb-wdt.txt b/Documentation/devicetree/bindings/watchdog/meson-gxbb-wdt.txt
deleted file mode 100644
index c7fe36fa739c..000000000000
--- a/Documentation/devicetree/bindings/watchdog/meson-gxbb-wdt.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-Meson GXBB SoCs Watchdog timer
-
-Required properties:
-
-- compatible : should be "amlogic,meson-gxbb-wdt"
-- reg : Specifies base physical address and size of the registers.
-- clocks : Should be a phandle to the Watchdog clock source, for GXBB the xtal
- is the default clock source.
-
-Example:
-
-wdt: watchdog@98d0 {
- compatible = "amlogic,meson-gxbb-wdt";
- reg = <0 0x98d0 0x0 0x10>;
- clocks = <&xtal>;
-};
--
2.22.0
^ permalink raw reply related
* [PATCH 8/9] dt-bindings: serial: meson-uart: convert to yaml
From: Neil Armstrong @ 2019-08-08 8:51 UTC (permalink / raw)
To: robh+dt
Cc: Rob Herring, devicetree, Martin Blumenstingl, Neil Armstrong,
linux-serial, linux-amlogic, linux-arm-kernel
In-Reply-To: <20190808085139.21438-1-narmstrong@baylibre.com>
Now that we have the DT validation in place, let's convert the device tree
bindings for the Amlogic UART Serial controller over to a YAML schemas.
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../bindings/serial/amlogic,meson-uart.txt | 38 ----------
.../bindings/serial/amlogic,meson-uart.yaml | 73 +++++++++++++++++++
2 files changed, 73 insertions(+), 38 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt
create mode 100644 Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml
diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt
deleted file mode 100644
index c06c045126fc..000000000000
--- a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-Amlogic Meson SoC UART Serial Interface
-=======================================
-
-The Amlogic Meson SoC UART Serial Interface is present on a large range
-of SoCs, and can be present either in the "Always-On" power domain or the
-"Everything-Else" power domain.
-
-The particularity of the "Always-On" Serial Interface is that the hardware
-is active since power-on and does not need any clock gating and is usable
-as very early serial console.
-
-Required properties:
-- compatible : compatible: value should be different for each SoC family as :
- - Meson6 : "amlogic,meson6-uart"
- - Meson8 : "amlogic,meson8-uart"
- - Meson8b : "amlogic,meson8b-uart"
- - GX (GXBB, GXL, GXM) : "amlogic,meson-gx-uart"
- eventually followed by : "amlogic,meson-ao-uart" if this UART interface
- is in the "Always-On" power domain.
-- reg : offset and length of the register set for the device.
-- interrupts : identifier to the device interrupt
-- clocks : a list of phandle + clock-specifier pairs, one for each
- entry in clock names.
-- clock-names :
- * "xtal" for external xtal clock identifier
- * "pclk" for the bus core clock, either the clk81 clock or the gate clock
- * "baud" for the source of the baudrate generator, can be either the xtal
- or the pclk.
-
-e.g.
-uart_A: serial@84c0 {
- compatible = "amlogic,meson-gx-uart";
- reg = <0x0 0x84c0 0x0 0x14>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
- /* Use xtal as baud rate clock source */
- clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
- clock-names = "xtal", "pclk", "baud";
-};
diff --git a/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml
new file mode 100644
index 000000000000..214fe8beddc3
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 BayLibre, SAS
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/serial/amlogic,meson-uart.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic Meson SoC UART Serial Interface
+
+maintainers:
+ - Neil Armstrong <narmstrong@baylibre.com>
+
+description: |
+ The Amlogic Meson SoC UART Serial Interface is present on a large range
+ of SoCs, and can be present either in the "Always-On" power domain or the
+ "Everything-Else" power domain.
+
+ The particularity of the "Always-On" Serial Interface is that the hardware
+ is active since power-on and does not need any clock gating and is usable
+ as very early serial console.
+
+properties:
+ compatible:
+ oneOf:
+ - description: Always-on power domain UART controller
+ items:
+ - enum:
+ - amlogic,meson6-uart
+ - amlogic,meson8-uart
+ - amlogic,meson8b-uart
+ - amlogic,meson-gx-uart
+ - const: amlogic,meson-ao-uart
+ - description: Everything-Else power domain UART controller
+ enum:
+ - amlogic,meson6-uart
+ - amlogic,meson8-uart
+ - amlogic,meson8b-uart
+ - amlogic,meson-gx-uart
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: external xtal clock identifier
+ - description: the bus core clock, either the clk81 clock or the gate clock
+ - description: the source of the baudrate generator, can be either the xtal or the pclk
+
+ clock-names:
+ items:
+ - const: xtal
+ - const: pclk
+ - const: baud
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+examples:
+ - |
+ serial@84c0 {
+ compatible = "amlogic,meson-gx-uart";
+ reg = <0x84c0 0x14>;
+ interrupts = <26>;
+ clocks = <&xtal>, <&pclk>, <&xtal>;
+ clock-names = "xtal", "pclk", "baud";
+ };
--
2.22.0
^ permalink raw reply related
* [PATCH 7/9] dt-bindings: phy: meson-g12a-usb3-pcie-phy: convert to yaml
From: Neil Armstrong @ 2019-08-08 8:51 UTC (permalink / raw)
To: robh+dt
Cc: devicetree, Rob Herring, Neil Armstrong, kishon, linux-amlogic,
linux-arm-kernel
In-Reply-To: <20190808085139.21438-1-narmstrong@baylibre.com>
Now that we have the DT validation in place, let's convert the device tree
bindings for the Amlogic G12A USB3 + PCIE Combo PHY over to a YAML schemas.
While the original phy bindings specifies phy-supply as required,
the examples and implementations makes it optional, thus phy-supply
is not present in the properties and required lists.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../phy/amlogic,meson-g12a-usb3-pcie-phy.yaml | 57 +++++++++++++++++++
.../bindings/phy/meson-g12a-usb3-pcie-phy.txt | 22 -------
2 files changed, 57 insertions(+), 22 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/meson-g12a-usb3-pcie-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml
new file mode 100644
index 000000000000..346f9c35427c
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 BayLibre, SAS
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic G12A USB3 + PCIE Combo PHY
+
+maintainers:
+ - Neil Armstrong <narmstrong@baylibre.com>
+
+properties:
+ compatible:
+ enum:
+ - amlogic,meson-g12a-usb3-pcie-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: ref_clk
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: phy
+
+ "#phy-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - "#phy-cells"
+
+examples:
+ - |
+ phy@46000 {
+ compatible = "amlogic,meson-g12a-usb3-pcie-phy";
+ reg = <0x46000 0x2000>;
+ clocks = <&ref_clk>;
+ clock-names = "ref_clk";
+ resets = <&phy_reset>;
+ reset-names = "phy";
+ #phy-cells = <1>;
+ };
diff --git a/Documentation/devicetree/bindings/phy/meson-g12a-usb3-pcie-phy.txt b/Documentation/devicetree/bindings/phy/meson-g12a-usb3-pcie-phy.txt
deleted file mode 100644
index 7cfc17e2df31..000000000000
--- a/Documentation/devicetree/bindings/phy/meson-g12a-usb3-pcie-phy.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-* Amlogic G12A USB3 + PCIE Combo PHY binding
-
-Required properties:
-- compatible: Should be "amlogic,meson-g12a-usb3-pcie-phy"
-- #phys-cells: must be 1. The cell number is used to select the phy mode
- as defined in <dt-bindings/phy/phy.h> between PHY_TYPE_USB3 and PHY_TYPE_PCIE
-- reg: The base address and length of the registers
-- clocks: a phandle to the 100MHz reference clock of this PHY
-- clock-names: must be "ref_clk"
-- resets: phandle to the reset lines for the PHY control
-- reset-names: must be "phy"
-
-Example:
- usb3_pcie_phy: phy@46000 {
- compatible = "amlogic,g12a-usb3-pcie-phy";
- reg = <0x0 0x46000 0x0 0x2000>;
- clocks = <&clkc CLKID_PCIE_PLL>;
- clock-names = "ref_clk";
- resets = <&reset RESET_PCIE_PHY>;
- reset-names = "phy";
- #phy-cells = <1>;
- };
--
2.22.0
^ permalink raw reply related
* [PATCH 6/9] dt-bindings: phy: meson-g12a-usb2-phy: convert to yaml
From: Neil Armstrong @ 2019-08-08 8:51 UTC (permalink / raw)
To: robh+dt
Cc: devicetree, Rob Herring, Martin Blumenstingl, Neil Armstrong,
kishon, linux-amlogic, linux-arm-kernel
In-Reply-To: <20190808085139.21438-1-narmstrong@baylibre.com>
Now that we have the DT validation in place, let's convert the device tree
bindings for the Amlogic G12A USB2 PHY over to a YAML schemas.
While the original phy bindings specifies phy-supply as required,
the examples and implementations makes it optional, thus phy-supply
is not in the required list of attributes.
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../phy/amlogic,meson-g12a-usb2-phy.yaml | 63 +++++++++++++++++++
.../bindings/phy/meson-g12a-usb2-phy.txt | 22 -------
2 files changed, 63 insertions(+), 22 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb2-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/meson-g12a-usb2-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb2-phy.yaml
new file mode 100644
index 000000000000..51254b4e65dd
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb2-phy.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 BayLibre, SAS
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/amlogic,meson-g12a-usb2-phy.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic G12A USB2 PHY
+
+maintainers:
+ - Neil Armstrong <narmstrong@baylibre.com>
+
+properties:
+ compatible:
+ enum:
+ - amlogic,meson-g12a-usb2-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: xtal
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ items:
+ - const: phy
+
+ "#phy-cells":
+ const: 0
+
+ phy-supply:
+ maxItems: 1
+ description:
+ Phandle to a regulator that provides power to the PHY. This
+ regulator will be managed during the PHY power on/off sequence.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - "#phy-cells"
+
+examples:
+ - |
+ phy@36000 {
+ compatible = "amlogic,meson-g12a-usb2-phy";
+ reg = <0x36000 0x2000>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ resets = <&phy_reset>;
+ reset-names = "phy";
+ #phy-cells = <0>;
+ };
diff --git a/Documentation/devicetree/bindings/phy/meson-g12a-usb2-phy.txt b/Documentation/devicetree/bindings/phy/meson-g12a-usb2-phy.txt
deleted file mode 100644
index a6ebc3dea159..000000000000
--- a/Documentation/devicetree/bindings/phy/meson-g12a-usb2-phy.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-* Amlogic G12A USB2 PHY binding
-
-Required properties:
-- compatible: Should be "amlogic,meson-g12a-usb2-phy"
-- reg: The base address and length of the registers
-- #phys-cells: must be 0 (see phy-bindings.txt in this directory)
-- clocks: a phandle to the clock of this PHY
-- clock-names: must be "xtal"
-- resets: a phandle to the reset line of this PHY
-- reset-names: must be "phy"
-- phy-supply: see phy-bindings.txt in this directory
-
-Example:
- usb2_phy0: phy@36000 {
- compatible = "amlogic,g12a-usb2-phy";
- reg = <0x0 0x36000 0x0 0x2000>;
- clocks = <&xtal>;
- clock-names = "xtal";
- resets = <&reset RESET_USB_PHY21>;
- reset-names = "phy";
- #phy-cells = <0>;
- };
--
2.22.0
^ permalink raw reply related
* [PATCH 5/9] dt-bindings: arm: amlogic: amlogic, meson-gx-ao-secure: convert to yaml
From: Neil Armstrong @ 2019-08-08 8:51 UTC (permalink / raw)
To: robh+dt
Cc: linux-amlogic, devicetree, Rob Herring, linux-arm-kernel,
Neil Armstrong
In-Reply-To: <20190808085139.21438-1-narmstrong@baylibre.com>
Now that we have the DT validation in place, let's convert the device tree
bindings for the Amlogic Always-On Secure Registers over to a YAML schemas.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../amlogic/amlogic,meson-gx-ao-secure.txt | 28 ----------
.../amlogic/amlogic,meson-gx-ao-secure.yaml | 52 +++++++++++++++++++
2 files changed, 52 insertions(+), 28 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.txt
create mode 100644 Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml
diff --git a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.txt b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.txt
deleted file mode 100644
index c67d9f48fb91..000000000000
--- a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-Amlogic Meson Firmware registers Interface
-------------------------------------------
-
-The Meson SoCs have a register bank with status and data shared with the
-secure firmware.
-
-Required properties:
- - compatible: For Meson GX SoCs, must be "amlogic,meson-gx-ao-secure", "syscon"
-
-Properties should indentify components of this register interface :
-
-Meson GX SoC Information
-------------------------
-A firmware register encodes the SoC type, package and revision information on
-the Meson GX SoCs.
-If present, the following property should be added :
-
-Optional properties:
- - amlogic,has-chip-id: If present, the interface gives the current SoC version.
-
-Example
--------
-
-ao-secure@140 {
- compatible = "amlogic,meson-gx-ao-secure", "syscon";
- reg = <0x0 0x140 0x0 0x140>;
- amlogic,has-chip-id;
-};
diff --git a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml
new file mode 100644
index 000000000000..853d7d2b56f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 BayLibre, SAS
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/arm/amlogic/amlogic,meson-gx-ao-secure.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic Meson Firmware registers Interface
+
+maintainers:
+ - Neil Armstrong <narmstrong@baylibre.com>
+
+description: |
+ The Meson SoCs have a register bank with status and data shared with the
+ secure firmware.
+
+# We need a select here so we don't match all nodes with 'syscon'
+select:
+ properties:
+ compatible:
+ contains:
+ const: amlogic,meson-gx-ao-secure
+ required:
+ - compatible
+
+properties:
+ compatible:
+ items:
+ - const: amlogic,meson-gx-ao-secure
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ amlogic,has-chip-id:
+ description: |
+ A firmware register encodes the SoC type, package and revision
+ information on the Meson GX SoCs. If present, the interface gives
+ the current SoC version.
+ type: boolean
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ ao-secure@140 {
+ compatible = "amlogic,meson-gx-ao-secure", "syscon";
+ reg = <0x140 0x140>;
+ amlogic,has-chip-id;
+ };
--
2.22.0
^ permalink raw reply related
* [PATCH 4/9] dt-bindings: reset: amlogic,meson-reset: convert to yaml
From: Neil Armstrong @ 2019-08-08 8:51 UTC (permalink / raw)
To: robh+dt
Cc: Rob Herring, devicetree, Martin Blumenstingl, Neil Armstrong,
p.zabel, linux-amlogic, linux-arm-kernel
In-Reply-To: <20190808085139.21438-1-narmstrong@baylibre.com>
Now that we have the DT validation in place, let's convert the device tree
bindings for the Amlogic Reset controller over to a YAML schemas.
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../bindings/reset/amlogic,meson-reset.txt | 19 ----------
.../bindings/reset/amlogic,meson-reset.yaml | 37 +++++++++++++++++++
2 files changed, 37 insertions(+), 19 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt
create mode 100644 Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml
diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt
deleted file mode 100644
index 28ef6c295c76..000000000000
--- a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-Amlogic Meson SoC Reset Controller
-=======================================
-
-Please also refer to reset.txt in this directory for common reset
-controller binding usage.
-
-Required properties:
-- compatible: Should be "amlogic,meson8b-reset", "amlogic,meson-gxbb-reset" or
- "amlogic,meson-axg-reset".
-- reg: should contain the register address base
-- #reset-cells: 1, see below
-
-example:
-
-reset: reset-controller {
- compatible = "amlogic,meson-gxbb-reset";
- reg = <0x0 0x04404 0x0 0x20>;
- #reset-cells = <1>;
-};
diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml
new file mode 100644
index 000000000000..00917d868d58
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 BayLibre, SAS
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/amlogic,meson-reset.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic Meson SoC Reset Controller
+
+maintainers:
+ - Neil Armstrong <narmstrong@baylibre.com>
+
+properties:
+ compatible:
+ enum:
+ - amlogic,meson8b-reset # Reset Controller on Meson8b and compatible SoCs
+ - amlogic,meson-gxbb-reset # Reset Controller on GXBB and compatible SoCs
+ - amlogic,meson-axg-reset # Reset Controller on AXG and compatible SoCs
+
+ reg:
+ maxItems: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#reset-cells"
+
+examples:
+ - |
+ reset-controller@c884404 {
+ compatible = "amlogic,meson-gxbb-reset";
+ reg = <0xc884404 0x20>;
+ #reset-cells = <1>;
+ };
--
2.22.0
^ permalink raw reply related
* [PATCH 3/9] dt-bindings: spi: meson: convert to yaml
From: Neil Armstrong @ 2019-08-08 8:51 UTC (permalink / raw)
To: robh+dt
Cc: devicetree, Rob Herring, Neil Armstrong, linux-spi, linux-amlogic,
linux-arm-kernel
In-Reply-To: <20190808085139.21438-1-narmstrong@baylibre.com>
Now that we have the DT validation in place, let's convert the device tree
bindings for the Amlogic SPI controllers over to two separate YAML schemas.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../bindings/spi/amlogic,meson-gx-spicc.yaml | 67 +++++++++++++++++++
.../bindings/spi/amlogic,meson6-spifc.yaml | 53 +++++++++++++++
.../devicetree/bindings/spi/spi-meson.txt | 55 ---------------
3 files changed, 120 insertions(+), 55 deletions(-)
create mode 100644 Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml
create mode 100644 Documentation/devicetree/bindings/spi/amlogic,meson6-spifc.yaml
delete mode 100644 Documentation/devicetree/bindings/spi/spi-meson.txt
diff --git a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml
new file mode 100644
index 000000000000..49b617c98ae7
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 BayLibre, SAS
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/spi/amlogic,meson-gx-spicc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic Meson SPI Communication Controller
+
+maintainers:
+ - Neil Armstrong <narmstrong@baylibre.com>
+
+allOf:
+ - $ref: "spi-controller.yaml#"
+
+description: |
+ The Meson SPICC is a generic SPI controller for general purpose Full-Duplex
+ communications with dedicated 16 words RX/TX PIO FIFOs.
+
+properties:
+ compatible:
+ enum:
+ - amlogic,meson-gx-spicc # SPICC controller on Amlogic GX and compatible SoCs
+ - amlogic,meson-axg-spicc # SPICC controller on Amlogic AXG and compatible SoCs
+
+ interrupts:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ description: input clock for the baud rate generator
+ items:
+ - const: core
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+examples:
+ - |
+ spi@c1108d80 {
+ compatible = "amlogic,meson-gx-spicc";
+ reg = <0xc1108d80 0x80>;
+ interrupts = <112>;
+ clocks = <&clk81>;
+ clock-names = "core";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-switch@0 {
+ compatible = "micrel,ks8995m";
+ spi-max-frequency = <1000000>;
+ reg = <0>;
+ };
+ };
+
diff --git a/Documentation/devicetree/bindings/spi/amlogic,meson6-spifc.yaml b/Documentation/devicetree/bindings/spi/amlogic,meson6-spifc.yaml
new file mode 100644
index 000000000000..67dcedc81a5e
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/amlogic,meson6-spifc.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 BayLibre, SAS
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/spi/amlogic,meson6-spifc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic Meson SPI Flash Controller
+
+maintainers:
+ - Neil Armstrong <narmstrong@baylibre.com>
+
+allOf:
+ - $ref: "spi-controller.yaml#"
+
+description: |
+ The Meson SPIFC is a controller optimized for communication with SPI
+ NOR memories, without DMA support and a 64-byte unified transmit /
+ receive buffer.
+
+properties:
+ compatible:
+ enum:
+ - amlogic,meson6-spifc # SPI Flash Controller on Meson6 and compatible SoCs
+ - amlogic,meson-gxbb-spifc # SPI Flash Controller on GXBB and compatible SoCs
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+examples:
+ - |
+ spi@c1108c80 {
+ compatible = "amlogic,meson6-spifc";
+ reg = <0xc1108c80 0x80>;
+ clocks = <&clk81>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ flash: flash@0 {
+ compatible = "spansion,m25p80", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <40000000>;
+ };
+ };
+
diff --git a/Documentation/devicetree/bindings/spi/spi-meson.txt b/Documentation/devicetree/bindings/spi/spi-meson.txt
deleted file mode 100644
index b7f5e86fed22..000000000000
--- a/Documentation/devicetree/bindings/spi/spi-meson.txt
+++ /dev/null
@@ -1,55 +0,0 @@
-Amlogic Meson SPI controllers
-
-* SPIFC (SPI Flash Controller)
-
-The Meson SPIFC is a controller optimized for communication with SPI
-NOR memories, without DMA support and a 64-byte unified transmit /
-receive buffer.
-
-Required properties:
- - compatible: should be "amlogic,meson6-spifc" or "amlogic,meson-gxbb-spifc"
- - reg: physical base address and length of the controller registers
- - clocks: phandle of the input clock for the baud rate generator
- - #address-cells: should be 1
- - #size-cells: should be 0
-
- spi@c1108c80 {
- compatible = "amlogic,meson6-spifc";
- reg = <0xc1108c80 0x80>;
- clocks = <&clk81>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
-* SPICC (SPI Communication Controller)
-
-The Meson SPICC is generic SPI controller for general purpose Full-Duplex
-communications with dedicated 16 words RX/TX PIO FIFOs.
-
-Required properties:
- - compatible: should be:
- "amlogic,meson-gx-spicc" on Amlogic GX and compatible SoCs.
- "amlogic,meson-axg-spicc" on Amlogic AXG and compatible SoCs
- - reg: physical base address and length of the controller registers
- - interrupts: The interrupt specifier
- - clock-names: Must contain "core"
- - clocks: phandle of the input clock for the baud rate generator
- - #address-cells: should be 1
- - #size-cells: should be 0
-
-Optional properties:
- - resets: phandle of the internal reset line
-
-See ../spi/spi-bus.txt for more details on SPI bus master and slave devices
-required and optional properties.
-
-Example :
- spi@c1108d80 {
- compatible = "amlogic,meson-gx-spicc";
- reg = <0xc1108d80 0x80>;
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core";
- clocks = <&clk81>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
--
2.22.0
^ permalink raw reply related
* [PATCH 2/9] dt-bindings: rng: amlogic,meson-rng: convert to yaml
From: Neil Armstrong @ 2019-08-08 8:51 UTC (permalink / raw)
To: robh+dt
Cc: Rob Herring, devicetree, Martin Blumenstingl, Neil Armstrong,
linux-crypto, linux-amlogic, linux-arm-kernel
In-Reply-To: <20190808085139.21438-1-narmstrong@baylibre.com>
Now that we have the DT validation in place, let's convert the device tree
bindings for the Amlogic Random Number generator over to a YAML schemas.
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../bindings/rng/amlogic,meson-rng.txt | 21 -----------
.../bindings/rng/amlogic,meson-rng.yaml | 37 +++++++++++++++++++
2 files changed, 37 insertions(+), 21 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/rng/amlogic,meson-rng.txt
create mode 100644 Documentation/devicetree/bindings/rng/amlogic,meson-rng.yaml
diff --git a/Documentation/devicetree/bindings/rng/amlogic,meson-rng.txt b/Documentation/devicetree/bindings/rng/amlogic,meson-rng.txt
deleted file mode 100644
index 4d403645ac9b..000000000000
--- a/Documentation/devicetree/bindings/rng/amlogic,meson-rng.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Amlogic Meson Random number generator
-=====================================
-
-Required properties:
-
-- compatible : should be "amlogic,meson-rng"
-- reg : Specifies base physical address and size of the registers.
-
-Optional properties:
-
-- clocks : phandle to the following named clocks
-- clock-names: Name of core clock, must be "core"
-
-Example:
-
-rng {
- compatible = "amlogic,meson-rng";
- reg = <0x0 0xc8834000 0x0 0x4>;
- clocks = <&clkc CLKID_RNG0>;
- clock-names = "core";
-};
diff --git a/Documentation/devicetree/bindings/rng/amlogic,meson-rng.yaml b/Documentation/devicetree/bindings/rng/amlogic,meson-rng.yaml
new file mode 100644
index 000000000000..a9ff3cb35c5e
--- /dev/null
+++ b/Documentation/devicetree/bindings/rng/amlogic,meson-rng.yaml
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 BayLibre, SAS
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/rng/amlogic,meson-rng.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic Meson Random number generator
+
+maintainers:
+ - Neil Armstrong <narmstrong@baylibre.com>
+
+properties:
+ compatible:
+ enum:
+ - amlogic,meson-rng
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: core
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ rng@c8834000 {
+ compatible = "amlogic,meson-rng";
+ reg = <0xc8834000 0x4>;
+ };
--
2.22.0
^ permalink raw reply related
* [PATCH 1/9] dt-bindings: mailbox: meson-mhu: convert to yaml
From: Neil Armstrong @ 2019-08-08 8:51 UTC (permalink / raw)
To: robh+dt
Cc: devicetree, Rob Herring, jassisinghbrar, Neil Armstrong,
linux-amlogic, linux-arm-kernel
In-Reply-To: <20190808085139.21438-1-narmstrong@baylibre.com>
Now that we have the DT validation in place, let's convert the device tree
bindings for the Amlogic MHU controller over to a YAML schemas.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../mailbox/amlogic,meson-gxbb-mhu.yaml | 52 +++++++++++++++++++
.../devicetree/bindings/mailbox/meson-mhu.txt | 34 ------------
2 files changed, 52 insertions(+), 34 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mailbox/amlogic,meson-gxbb-mhu.yaml
delete mode 100644 Documentation/devicetree/bindings/mailbox/meson-mhu.txt
diff --git a/Documentation/devicetree/bindings/mailbox/amlogic,meson-gxbb-mhu.yaml b/Documentation/devicetree/bindings/mailbox/amlogic,meson-gxbb-mhu.yaml
new file mode 100644
index 000000000000..319280563648
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/amlogic,meson-gxbb-mhu.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2019 BayLibre, SAS
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/mailbox/amlogic,meson-gxbb-mhu.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic Meson Message-Handling-Unit Controller
+
+maintainers:
+ - Neil Armstrong <narmstrong@baylibre.com>
+
+description: |
+ The Amlogic's Meson SoCs Message-Handling-Unit (MHU) is a mailbox controller
+ that has 3 independent channels/links to communicate with remote processor(s).
+ MHU links are hardwired on a platform. A link raises interrupt for any
+ received data. However, there is no specified way of knowing if the sent
+ data has been read by the remote. This driver assumes the sender polls
+ STAT register and the remote clears it after having read the data.
+
+properties:
+ compatible:
+ enum:
+ - amlogic,meson-gxbb-mhu
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 3
+ description:
+ Contains the interrupt information corresponding to each of the 3 links
+ of MHU.
+
+ "#mbox-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#mbox-cells"
+
+examples:
+ - |
+ mailbox@c883c404 {
+ compatible = "amlogic,meson-gxbb-mhu";
+ reg = <0xc883c404 0x4c>;
+ interrupts = <208>, <209>, <210>;
+ #mbox-cells = <1>;
+ };
+
diff --git a/Documentation/devicetree/bindings/mailbox/meson-mhu.txt b/Documentation/devicetree/bindings/mailbox/meson-mhu.txt
deleted file mode 100644
index a530310772b9..000000000000
--- a/Documentation/devicetree/bindings/mailbox/meson-mhu.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-Amlogic Meson MHU Mailbox Driver
-================================
-
-The Amlogic's Meson SoCs Message-Handling-Unit (MHU) is a mailbox controller
-that has 3 independent channels/links to communicate with remote processor(s).
-MHU links are hardwired on a platform. A link raises interrupt for any
-received data. However, there is no specified way of knowing if the sent
-data has been read by the remote. This driver assumes the sender polls
-STAT register and the remote clears it after having read the data.
-
-Mailbox Device Node:
-====================
-
-Required properties:
---------------------
-- compatible: Shall be "amlogic,meson-gxbb-mhu"
-- reg: Contains the mailbox register address range (base
- address and length)
-- #mbox-cells Shall be 1 - the index of the channel needed.
-- interrupts: Contains the interrupt information corresponding to
- each of the 2 links of MHU.
-
-Example:
---------
-
- mailbox: mailbox@c883c404 {
- #mbox-cells = <1>;
- compatible = "amlogic,meson-gxbb-mhu";
- reg = <0 0xc883c404 0 0x4c>;
- interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
- <0 209 IRQ_TYPE_EDGE_RISING>,
- <0 210 IRQ_TYPE_EDGE_RISING>;
- #mbox-cells = <1>;
- };
--
2.22.0
^ permalink raw reply related
* [PATCH 0/9] dt-bindings: first tentative of conversion to yaml format
From: Neil Armstrong @ 2019-08-08 8:51 UTC (permalink / raw)
To: robh+dt
Cc: p.zabel, devicetree, linux-watchdog, Neil Armstrong,
jassisinghbrar, linux-spi, linux-crypto, linux-serial,
linux-amlogic, kishon, linux-arm-kernel
This is a first tentative to convert some of the simplest Amlogic
dt-bindings to the yaml format.
All have been tested using :
$ make ARCH=arm64 dtbs_check
Issues with the amlogic arm64 DTs has already been identified thanks
to the validation scripts. The DT fixes will be pushed once these yaml
bindings are acked.
Changes since rfc v2:
- Collected Rob's, Martin's, Philipp's and Guenter's tags
- Removed mhu maxItems: 3 to leave only minItems
- Fixed flash@0 in spifc example
Changes since rfc v1:
- Fixed bindings according to Rob's comments
- Added commit log
- renamed yaml files using amlogic prefix
Neil Armstrong (9):
dt-bindings: mailbox: meson-mhu: convert to yaml
dt-bindings: rng: amlogic,meson-rng: convert to yaml
dt-bindings: spi: meson: convert to yaml
dt-bindings: reset: amlogic,meson-reset: convert to yaml
dt-bindings: arm: amlogic: amlogic,meson-gx-ao-secure: convert to yaml
dt-bindings: phy: meson-g12a-usb2-phy: convert to yaml
dt-bindings: phy: meson-g12a-usb3-pcie-phy: convert to yaml
dt-bindings: serial: meson-uart: convert to yaml
dt-bindings: watchdog: meson-gxbb-wdt: convert to yaml
.../amlogic/amlogic,meson-gx-ao-secure.txt | 28 -------
.../amlogic/amlogic,meson-gx-ao-secure.yaml | 52 +++++++++++++
.../mailbox/amlogic,meson-gxbb-mhu.yaml | 52 +++++++++++++
.../devicetree/bindings/mailbox/meson-mhu.txt | 34 ---------
.../phy/amlogic,meson-g12a-usb2-phy.yaml | 63 ++++++++++++++++
.../phy/amlogic,meson-g12a-usb3-pcie-phy.yaml | 57 +++++++++++++++
.../bindings/phy/meson-g12a-usb2-phy.txt | 22 ------
.../bindings/phy/meson-g12a-usb3-pcie-phy.txt | 22 ------
.../bindings/reset/amlogic,meson-reset.txt | 19 -----
.../bindings/reset/amlogic,meson-reset.yaml | 37 ++++++++++
.../bindings/rng/amlogic,meson-rng.txt | 21 ------
.../bindings/rng/amlogic,meson-rng.yaml | 37 ++++++++++
.../bindings/serial/amlogic,meson-uart.txt | 38 ----------
.../bindings/serial/amlogic,meson-uart.yaml | 73 +++++++++++++++++++
.../bindings/spi/amlogic,meson-gx-spicc.yaml | 67 +++++++++++++++++
.../bindings/spi/amlogic,meson6-spifc.yaml | 53 ++++++++++++++
.../devicetree/bindings/spi/spi-meson.txt | 55 --------------
.../watchdog/amlogic,meson-gxbb-wdt.yaml | 37 ++++++++++
.../bindings/watchdog/meson-gxbb-wdt.txt | 16 ----
19 files changed, 528 insertions(+), 255 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.txt
create mode 100644 Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml
create mode 100644 Documentation/devicetree/bindings/mailbox/amlogic,meson-gxbb-mhu.yaml
delete mode 100644 Documentation/devicetree/bindings/mailbox/meson-mhu.txt
create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb2-phy.yaml
create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/meson-g12a-usb2-phy.txt
delete mode 100644 Documentation/devicetree/bindings/phy/meson-g12a-usb3-pcie-phy.txt
delete mode 100644 Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt
create mode 100644 Documentation/devicetree/bindings/reset/amlogic,meson-reset.yaml
delete mode 100644 Documentation/devicetree/bindings/rng/amlogic,meson-rng.txt
create mode 100644 Documentation/devicetree/bindings/rng/amlogic,meson-rng.yaml
delete mode 100644 Documentation/devicetree/bindings/serial/amlogic,meson-uart.txt
create mode 100644 Documentation/devicetree/bindings/serial/amlogic,meson-uart.yaml
create mode 100644 Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml
create mode 100644 Documentation/devicetree/bindings/spi/amlogic,meson6-spifc.yaml
delete mode 100644 Documentation/devicetree/bindings/spi/spi-meson.txt
create mode 100644 Documentation/devicetree/bindings/watchdog/amlogic,meson-gxbb-wdt.yaml
delete mode 100644 Documentation/devicetree/bindings/watchdog/meson-gxbb-wdt.txt
--
2.22.0
^ permalink raw reply
* [PATCH] ARM64: dts: allwinner: Add devicetree for pine H64 modelA evaluation board
From: Corentin Labbe @ 2019-08-08 8:42 UTC (permalink / raw)
To: mark.rutland-5wv7dgnIgG8, mripard-DgEjT+Ai2ygdnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, wens-jdAy2FN1RRM
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Corentin Labbe
This patch adds the evaluation variant of the model A of the PineH64.
The model A has the same size of the pine64 and has a PCIE slot.
The only devicetree difference with current pineH64, is the PHY
regulator.
Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/arm64/boot/dts/allwinner/Makefile | 1 +
.../sun50i-h6-pine-h64-modelA-eval.dts | 26 +++++++++++++++++++
2 files changed, 27 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-modelA-eval.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index f6db0611cb85..9a02166cbf72 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -25,3 +25,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-modelA-eval.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-modelA-eval.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-modelA-eval.dts
new file mode 100644
index 000000000000..d8ff02747efe
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-modelA-eval.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
+/*
+ * Copyright (C) 2019 Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ */
+
+#include "sun50i-h6-pine-h64.dts"
+
+/ {
+ model = "Pine H64 model A evaluation board";
+ compatible = "pine64,pine-h64-modelA-eval", "allwinner,sun50i-h6";
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+};
+
+&emac {
+ phy-supply = <®_gmac_3v3>;
+};
--
2.21.0
^ permalink raw reply related
* [v3,3/3] arm: dts: ls1021a: add ftm_alarm0 DT node
From: Biwen Li @ 2019-08-08 8:38 UTC (permalink / raw)
To: robh+dt, mark.rutland, leoyang.li; +Cc: devicetree, linux-kernel, Biwen Li
In-Reply-To: <20190808083839.28594-1-biwen.li@nxp.com>
The patch add ftm_alarm0 DT node
- add rcpm node
- add ftm_alarm0 node
- aliases ftm_alarm0 as rtc1
Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
Change in v3:
- None
Change in v2:
- delete reg-name property
- correct fsl,rcpm-wakeup property
arch/arm/boot/dts/ls1021a.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 464df4290ffc..30bd6bc1f49a 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -66,6 +66,7 @@
serial4 = &lpuart4;
serial5 = &lpuart5;
sysclk = &sysclk;
+ rtc1 = &ftm_alarm0;
};
cpus {
@@ -985,5 +986,18 @@
big-endian;
};
+ rcpm: rcpm@1ee2140 {
+ compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1ee2140 0x0 0x8>;
+ #fsl,rcpm-wakeup-cells = <2>;
+ };
+
+ ftm_alarm0: timer0@29d0000 {
+ compatible = "fsl,ls1021a-ftm-alarm";
+ reg = <0x0 0x29d0000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x0 0x20000000>;
+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
+ };
};
};
--
2.17.1
^ permalink raw reply related
* [v3,2/3] arm64: dts: ls1012a/ls1043a/ls1046a/ls1088a/ls208xa: add ftm_alarm0 node
From: Biwen Li @ 2019-08-08 8:38 UTC (permalink / raw)
To: robh+dt, mark.rutland, leoyang.li; +Cc: devicetree, linux-kernel, Biwen Li
In-Reply-To: <20190808083839.28594-1-biwen.li@nxp.com>
The patch adds ftm_alarm0 DT node
- add new rcpm node
- add ftm_alarm0 node
- aliases ftm_alarm0 as rtc1
Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
Change in v3:
- add little-endian property of rcpm for ls1088a,ls208xa
Change in v2:
- None
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 15 +++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 14 ++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 15 +++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 15 +++++++++++++++
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 15 +++++++++++++++
5 files changed, 74 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index ec6257a5b251..401210e3afd2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -22,6 +22,7 @@
rtic-c = &rtic_c;
rtic-d = &rtic_d;
sec-mon = &sec_mon;
+ rtc1 = &ftm_alarm0;
};
cpus {
@@ -500,6 +501,20 @@
<0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
+
+ rcpm: rcpm@1ee2140 {
+ compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1ee2140 0x0 0x4>;
+ #fsl,rcpm-wakeup-cells = <1>;
+ };
+
+ ftm_alarm0: timer@29d0000 {
+ compatible = "fsl,ls1012a-ftm-alarm";
+ reg = <0x0 0x29d0000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x20000>;
+ interrupts = <0 86 0x4>;
+ big-endian;
+ };
};
firmware {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 71d9ed9ff985..9ff5dd32e87d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -27,6 +27,7 @@
ethernet4 = &enet4;
ethernet5 = &enet5;
ethernet6 = &enet6;
+ rtc1 = &ftm_alarm0;
};
cpus {
@@ -767,6 +768,19 @@
big-endian;
};
+ rcpm: rcpm@1ee2140 {
+ compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1ee2140 0x0 0x4>;
+ #fsl,rcpm-wakeup-cells = <1>;
+ };
+
+ ftm_alarm0: timer@29d0000 {
+ compatible = "fsl,ls1043a-ftm-alarm";
+ reg = <0x0 0x29d0000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x20000>;
+ interrupts = <0 86 0x4>;
+ big-endian;
+ };
};
firmware {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index b0ef08b090dd..d216375b174f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -28,6 +28,7 @@
ethernet5 = &enet5;
ethernet6 = &enet6;
ethernet7 = &enet7;
+ rtc1 = &ftm_alarm0;
};
cpus {
@@ -771,6 +772,20 @@
queue-sizes = <64 64>;
big-endian;
};
+
+ rcpm: rcpm@1ee208c {
+ compatible = "fsl,ls1046a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1ee208c 0x0 0x4>;
+ #fsl,rcpm-wakeup-cells = <1>;
+ };
+
+ ftm_alarm0: timer@29d0000 {
+ compatible = "fsl,ls1046a-ftm-alarm";
+ reg = <0x0 0x29d0000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x20000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ big-endian;
+ };
};
reserved-memory {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index dacd8cf03a7f..99bc16ef2a98 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -18,6 +18,7 @@
aliases {
crypto = &crypto;
+ rtc1 = &ftm_alarm0;
};
cpus {
@@ -745,6 +746,20 @@
};
};
};
+
+ rcpm: rcpm@1e34040 {
+ compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1e34040 0x0 0x18>;
+ #fsl,rcpm-wakeup-cells = <6>;
+ little-endian;
+ };
+
+ ftm_alarm0: timer@2800000 {
+ compatible = "fsl,ls1088a-ftm-alarm";
+ reg = <0x0 0x2800000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
+ interrupts = <0 44 4>;
+ };
};
firmware {
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 3ace91945b72..af4fcdc1c2e4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -24,6 +24,7 @@
serial1 = &serial1;
serial2 = &serial2;
serial3 = &serial3;
+ rtc1 = &ftm_alarm0;
};
cpu: cpus {
@@ -758,6 +759,20 @@
reg = <0x0 0x04000000 0x0 0x01000000>;
interrupts = <0 12 4>;
};
+
+ rcpm: rcpm@1e34040 {
+ compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1e34040 0x0 0x18>;
+ #fsl,rcpm-wakeup-cells = <6>;
+ little-endian;
+ };
+
+ ftm_alarm0: timer@2800000 {
+ compatible = "fsl,ls208xa-ftm-alarm";
+ reg = <0x0 0x2800000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
+ interrupts = <0 44 4>;
+ };
};
ddr1: memory-controller@1080000 {
--
2.17.1
^ permalink raw reply related
* [v3,1/3] arm64: dts: ls1028a: Add ftm_alarm0 DT node
From: Biwen Li @ 2019-08-08 8:38 UTC (permalink / raw)
To: robh+dt, mark.rutland, leoyang.li; +Cc: devicetree, linux-kernel, Biwen Li
The patch adds ftm_alarm0 DT node for LS1028ARDB board
FlexTimer1 module is used to wakeup the system
Signed-off-by: Biwen Li <biwen.li@nxp.com>
---
Change in v3:
- add little-endian property of rcpm
Change in v2:
- None
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 7975519b4f56..23a758239419 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -17,6 +17,10 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ rtc1 = &ftm_alarm0;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -543,6 +547,20 @@
little-endian;
};
};
+
+ rcpm: rcpm@1e34040 {
+ compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+";
+ reg = <0x0 0x1e34040 0x0 0x1c>;
+ #fsl,rcpm-wakeup-cells = <7>;
+ little-endian;
+ };
+
+ ftm_alarm0: timer@2800000 {
+ compatible = "fsl,ls1028a-ftm-alarm";
+ reg = <0x0 0x2800000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
malidp0: display@f080000 {
--
2.17.1
^ permalink raw reply related
* [PATCH 2/2] ARM: dts: at91: sama5d27_som1_ek: add mmc capabilities for SDMMC0
From: Eugen.Hristev @ 2019-08-08 8:35 UTC (permalink / raw)
To: Nicolas.Ferre, Ludovic.Desroches, alexandre.belloni,
adrian.hunter, ulf.hansson, linux-arm-kernel, devicetree,
linux-kernel, linux-mmc
Cc: Eugen.Hristev
In-Reply-To: <1565252928-28994-1-git-send-email-eugen.hristev@microchip.com>
From: Eugen Hristev <eugen.hristev@microchip.com>
Add mmc capabilities for SDMMC0 for this board.
With this enabled, eMMC connected card is detected as:
mmc0: new DDR MMC card at address 0001
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
---
arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
index 149e539..194b3a3 100644
--- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
@@ -54,6 +54,7 @@
sdmmc0: sdio-host@a0000000 {
bus-width = <8>;
+ mmc-ddr-3_3v;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_default>;
status = "okay";
--
2.7.4
^ permalink raw reply related
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