* Re: [PATCH v2 03/15] net: phy: adin: hook genphy_{suspend,resume} into the driver
From: Andrew Lunn @ 2019-08-08 15:24 UTC (permalink / raw)
To: Alexandru Ardelean
Cc: netdev, devicetree, linux-kernel, davem, robh+dt, mark.rutland,
f.fainelli, hkallweit1
In-Reply-To: <20190808123026.17382-4-alexandru.ardelean@analog.com>
On Thu, Aug 08, 2019 at 03:30:14PM +0300, Alexandru Ardelean wrote:
> The chip supports standard suspend/resume via BMCR reg.
> Hook these functions into the `adin` driver.
>
> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply
* Re: [PATCH v2 02/15] net: phy: adin: hook genphy_read_abilities() to get_features
From: Andrew Lunn @ 2019-08-08 15:24 UTC (permalink / raw)
To: Alexandru Ardelean
Cc: netdev, devicetree, linux-kernel, davem, robh+dt, mark.rutland,
f.fainelli, hkallweit1
In-Reply-To: <20190808123026.17382-3-alexandru.ardelean@analog.com>
On Thu, Aug 08, 2019 at 03:30:13PM +0300, Alexandru Ardelean wrote:
> The ADIN PHYs can operate with Clause 45, however they are not typical for
> how phylib considers Clause 45 PHYs.
>
> If the `features` field & the `get_features` hook are unspecified, and the
> device wants to operate via Clause 45, it would also try to read features
> via the `genphy_c45_pma_read_abilities()`, which will try to read PMA regs
> that are unsupported.
>
> Hooking the `genphy_read_abilities()` function to the `get_features` hook
> will ensure that this does not happen and the PHY features are read
> correctly regardless of Clause 22 or Clause 45 operation.
I think we need to stop and think about a PHY which supports both C22
and C45.
How does bus enumeration work? Is it discovered twice? I've always
considered phydev->is_c45 means everything is c45, not that some
registers can be accessed via c45. But the driver is mixing c22 and
c45. Does the driver actually require c45? Are some features which are
only accessibly via C45? What does C45 actually bring us for this
device?
Andrew
^ permalink raw reply
* Re: [PATCH 1/2] mmc: sdhci-of-at91: add quirk for broken HS200
From: Ulf Hansson @ 2019-08-08 15:23 UTC (permalink / raw)
To: Eugen.Hristev
Cc: Nicolas Ferre, Ludovic Desroches, Alexandre Belloni,
Adrian Hunter, Linux ARM, DTML, Linux Kernel Mailing List,
linux-mmc@vger.kernel.org
In-Reply-To: <1565252928-28994-1-git-send-email-eugen.hristev@microchip.com>
On Thu, 8 Aug 2019 at 10:35, <Eugen.Hristev@microchip.com> wrote:
>
> From: Eugen Hristev <eugen.hristev@microchip.com>
>
> HS200 is not implemented in the driver, but the controller claims it
> through caps.
> Remove it via quirk.
> Without this quirk, the mmc core will try to enable hs200, which will fail,
> and the eMMC initialization will fail.
>
> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Should this be applied as a fix and possibly tagged for stable?
In such case, do you have a specific commit that it fixes?
Kind regards
Uffe
> ---
> drivers/mmc/host/sdhci-of-at91.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-of-at91.c b/drivers/mmc/host/sdhci-of-at91.c
> index 57fe3b2..3a8c6d8 100644
> --- a/drivers/mmc/host/sdhci-of-at91.c
> +++ b/drivers/mmc/host/sdhci-of-at91.c
> @@ -370,6 +370,9 @@ static int sdhci_at91_probe(struct platform_device *pdev)
> pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
> pm_runtime_use_autosuspend(&pdev->dev);
>
> + /* HS200 is broken at this moment */
> + host->quirks2 = SDHCI_QUIRK2_BROKEN_HS200;
> +
> ret = sdhci_add_host(host);
> if (ret)
> goto pm_runtime_disable;
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH v5 3/7] clk: qcom: define probe by index API as common API
From: Stephen Boyd @ 2019-08-08 15:20 UTC (permalink / raw)
To: bjorn.andersson, linux-arm-msm, linux-clk, linux-remoteproc
Cc: andy.gross, linux-soc, devicetree, Govind Singh
In-Reply-To: <20190726092332.25202-4-govinds@codeaurora.org>
Quoting Govind Singh (2019-07-26 02:23:28)
> Extend the probe by index API in common code to be used
> by other qcom clock controller.
>
> Signed-off-by: Govind Singh <govinds@codeaurora.org>
> ---
Applied to clk-next
^ permalink raw reply
* Re: [alsa-devel] [PATCH v2 4/4] ASoC: codecs: add wsa881x amplifier support
From: Pierre-Louis Bossart @ 2019-08-08 15:18 UTC (permalink / raw)
To: Srinivas Kandagatla, vkoul, broonie
Cc: devicetree, alsa-devel, bgoswami, linux-kernel, plai, lgirdwood,
robh+dt
In-Reply-To: <20190808144504.24823-5-srinivas.kandagatla@linaro.org>
> +/* 4 ports */
> +static struct sdw_dpn_prop wsa_sink_dpn_prop[WSA881X_MAX_SWR_PORTS] = {
> + {
> + /* DAC */
> + .num = 1,
> + .type = SDW_DPN_SIMPLE,
IIRC we added the REDUCED type in SoundWire 1.1 to cover the PDM case
with channel packing (or was it grouping) used by Qualcomm. I am not
sure the SIMPLE type works?
> + .min_ch = 1,
> + .max_ch = 8,
> + .simple_ch_prep_sm = true,
> + }, {
> + /* COMP */
> + .num = 2,
> + .type = SDW_DPN_SIMPLE,
> + .min_ch = 1,
> + .max_ch = 8,
> + .simple_ch_prep_sm = true,
> + }, {
> + /* BOOST */
> + .num = 3,
> + .type = SDW_DPN_SIMPLE,
> + .min_ch = 1,
> + .max_ch = 8,
> + .simple_ch_prep_sm = true,
> + }, {
> + /* VISENSE */
> + .num = 4,
> + .type = SDW_DPN_SIMPLE,
> + .min_ch = 1,
> + .max_ch = 8,
> + .simple_ch_prep_sm = true,
> + }
> +};
> +static int wsa881x_update_status(struct sdw_slave *slave,
> + enum sdw_slave_status status)
> +{
> + struct wsa881x_priv *wsa881x = dev_get_drvdata(&slave->dev);
> +
> + if (status == SDW_SLAVE_ATTACHED) {
there is an ambiguity here, the Slave can be attached but as device0
(not enumerated). We should check dev_num > 0
> + if (!wsa881x->regmap) {
> + wsa881x->regmap = devm_regmap_init_sdw(slave,
> + &wsa881x_regmap_config);
> + if (IS_ERR(wsa881x->regmap)) {
> + dev_err(&slave->dev, "regmap_init failed\n");
> + return PTR_ERR(wsa881x->regmap);
> + }
> + }
> +
> + return snd_soc_register_component(&slave->dev,
> + &wsa881x_component_drv,
> + NULL, 0);
> + } else if (status == SDW_SLAVE_UNATTACHED) {
> + snd_soc_unregister_component(&slave->dev);
the update_status() is supposed to be called based on bus events, it'd
be very odd to register/unregister the component itself dynamically. In
our existing Realtek-based solutions the register_component() is called
in the probe function (and unregister_component() in remove). We do the
inits when the Slave becomes attached but the component is already
registered.
> + }
> +
> + return 0;
> +}
> +
> +static int wsa881x_port_prep(struct sdw_slave *slave,
> + struct sdw_prepare_ch *prepare_ch,
> + enum sdw_port_prep_ops state)
> +{
> + struct wsa881x_priv *wsa881x = dev_get_drvdata(&slave->dev);
> +
> + if (state == SDW_OPS_PORT_POST_PREP)
> + wsa881x->port_prepared[prepare_ch->num - 1] = true;
> + else
> + wsa881x->port_prepared[prepare_ch->num - 1] = false;
> +
> + return 0;
> +}
> +
> +static int wsa881x_bus_config(struct sdw_slave *slave,
> + struct sdw_bus_params *params)
> +{
> + sdw_write(slave, SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(params->next_bank),
> + 0x01);
> +
> + return 0;
> +}
> +
> +static struct sdw_slave_ops wsa881x_slave_ops = {
> + .update_status = wsa881x_update_status,
> + .bus_config = wsa881x_bus_config,
> + .port_prep = wsa881x_port_prep,
> +};
> +
> +static int wsa881x_probe(struct sdw_slave *pdev,
> + const struct sdw_device_id *id)
> +{
> + struct wsa881x_priv *wsa881x;
> +
> + wsa881x = devm_kzalloc(&pdev->dev, sizeof(*wsa881x), GFP_KERNEL);
> + if (!wsa881x)
> + return -ENOMEM;
> +
> + wsa881x->sd_n = devm_gpiod_get_optional(&pdev->dev, "pd",
> + GPIOD_FLAGS_BIT_NONEXCLUSIVE);
> + if (IS_ERR(wsa881x->sd_n)) {
> + dev_err(&pdev->dev, "Shutdown Control GPIO not found\n");
> + return PTR_ERR(wsa881x->sd_n);
> + }
> +
> + dev_set_drvdata(&pdev->dev, wsa881x);
> + wsa881x->slave = pdev;
> + wsa881x->dev = &pdev->dev;
> + pdev->prop.sink_ports = GENMASK(WSA881X_MAX_SWR_PORTS, 0);
> + pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop;
> + gpiod_set_value(wsa881x->sd_n, 1);
> +
> + return 0;
> +}
> +
> +static int wsa881x_remove(struct sdw_slave *sdw)
> +{
> + return 0;
> +}
> +
> +static const struct sdw_device_id wsa881x_slave_id[] = {
> + SDW_SLAVE_ENTRY(0x0217, 0x2010, 0),
> + {},
> +};
> +MODULE_DEVICE_TABLE(sdw, wsa881x_slave_id);
> +
> +static struct sdw_driver wsa881x_codec_driver = {
> + .probe = wsa881x_probe,
> + .remove = wsa881x_remove,
is this needed since you do nothing in that function?
> + .ops = &wsa881x_slave_ops,
> + .id_table = wsa881x_slave_id,
> + .driver = {
> + .name = "wsa881x-codec",
> + }
> +};
> +module_sdw_driver(wsa881x_codec_driver);
> +
> +MODULE_DESCRIPTION("WSA881x codec driver");
> +MODULE_LICENSE("GPL v2");
>
^ permalink raw reply
* Re: [PATCH v2 2/4] soundwire: core: add device tree support for slave devices
From: Srinivas Kandagatla @ 2019-08-08 15:17 UTC (permalink / raw)
To: Pierre-Louis Bossart, vkoul, broonie
Cc: bgoswami, plai, robh+dt, devicetree, lgirdwood, alsa-devel,
linux-kernel
In-Reply-To: <42ca4170-0fa0-6951-f568-89a05c095d5a@linux.intel.com>
Thanks for taking time to review.
On 08/08/2019 16:00, Pierre-Louis Bossart wrote:
>
>> @@ -35,6 +36,7 @@ static int sdw_slave_add(struct sdw_bus *bus,
>> slave->dev.release = sdw_slave_release;
>> slave->dev.bus = &sdw_bus_type;
>> + slave->dev.of_node = of_node_get(to_of_node(fwnode));
>
> shouldn't this protected by
> #if IS_ENABLED(CONFIG_OF) ?
>
These macros and functions have dummy entries, so it should not be an issue.
I did build soundwire with i386_defconfig with no issues.
>> slave->bus = bus;
>> slave->status = SDW_SLAVE_UNATTACHED;
>> slave->dev_num = 0;
>> @@ -112,3 +114,48 @@ int sdw_acpi_find_slaves(struct sdw_bus *bus)
>> }
>> #endif
>> +
>> +/*
>> + * sdw_of_find_slaves() - Find Slave devices in master device tree node
>> + * @bus: SDW bus instance
>> + *
>> + * Scans Master DT node for SDW child Slave devices and registers it.
>> + */
>> +int sdw_of_find_slaves(struct sdw_bus *bus)
>> +{
>> + struct device *dev = bus->dev;
>> + struct device_node *node;
>> +
>> + for_each_child_of_node(bus->dev->of_node, node) {
>> + struct sdw_slave_id id;
>> + const char *compat = NULL;
>> + int unique_id, ret;
>> + int ver, mfg_id, part_id, class_id;
>> +
>> + compat = of_get_property(node, "compatible", NULL);
>> + if (!compat)
>> + continue;
>> +
>> + ret = sscanf(compat, "sdw%x,%x,%x,%x",
>> + &ver, &mfg_id, &part_id, &class_id);
>> + if (ret != 4) {
>> + dev_err(dev, "Manf ID & Product code not found %s\n",
>> + compat);
>> + continue;
>> + }
>> +
>> + ret = of_property_read_u32(node, "sdw-instance-id", &unique_id);
>> + if (ret) {
>> + dev_err(dev, "Instance id not found:%d\n", ret);
>> + continue;
>
> I am confused here.
> If you have two identical devices on the same link, isn't this property
> required and that should be a real error instead of a continue?
Yes, I agree it will be mandatory in such cases.
Am okay either way, I dont mind changing it to returning EINVAL in all
the cases.
>
>> + }
>> +
>> + id.sdw_version = ver - 0xF;
>
> maybe a comment in the code would help to make the encoding
> self-explanatory, as you did in the DT bindings
>
> Version number '0x10' represents SoundWire 1.0
> Version number '0x11' represents SoundWire 1.1
Makes sense, will fix this in next version.
This info is also available in bindings.
--srini
>
>> + id.unique_id = unique_id;
>> + id.mfg_id = mfg_id;
>> + id.part_id = part_id;
>> + id.class_id = class_id;
>> + sdw_slave_add(bus, &id, of_fwnode_handle(node));
>> + }
>> + return 0;
>> +}
>>
^ permalink raw reply
* Re: [PATCH v2 01/15] net: phy: adin: add support for Analog Devices PHYs
From: Andrew Lunn @ 2019-08-08 15:13 UTC (permalink / raw)
To: Alexandru Ardelean
Cc: netdev, devicetree, linux-kernel, davem, robh+dt, mark.rutland,
f.fainelli, hkallweit1
In-Reply-To: <20190808123026.17382-2-alexandru.ardelean@analog.com>
On Thu, Aug 08, 2019 at 03:30:12PM +0300, Alexandru Ardelean wrote:
> This change adds support for Analog Devices Industrial Ethernet PHYs.
> Particularly the PHYs this driver adds support for:
> * ADIN1200 - Robust, Industrial, Low Power 10/100 Ethernet PHY
> * ADIN1300 - Robust, Industrial, Low Latency 10/100/1000 Gigabit
> Ethernet PHY
>
> The 2 chips are pin & register compatible with one another. The main
> difference being that ADIN1200 doesn't operate in gigabit mode.
>
> The chips can be operated by the Generic PHY driver as well via the
> standard IEEE PHY registers (0x0000 - 0x000F) which are supported by the
> kernel as well. This assumes that configuration of the PHY has been done
> completely in HW, according to spec.
>
> Configuration can also be done via registers, which will be supported by
> this driver.
>
> Datasheets:
> https://www.analog.com/media/en/technical-documentation/data-sheets/ADIN1300.pdf
> https://www.analog.com/media/en/technical-documentation/data-sheets/ADIN1200.pdf
>
> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply
* Re: [PATCH v5 1/7] clk: qcom: Add WCSS gcc clock control for QCS404
From: Stephen Boyd @ 2019-08-08 15:10 UTC (permalink / raw)
To: bjorn.andersson, linux-arm-msm, linux-clk, linux-remoteproc
Cc: andy.gross, linux-soc, devicetree, Govind Singh
In-Reply-To: <20190726092332.25202-2-govinds@codeaurora.org>
Quoting Govind Singh (2019-07-26 02:23:26)
> Add support for the WCSS QDSP gcc clock control used on qcs404
> based devices. This would allow wcss remoteproc driver to control
> the required gcc clocks to bring the subsystem out of reset.
>
> Signed-off-by: Govind Singh <govinds@codeaurora.org>
> ---
Applied to clk-next
^ permalink raw reply
* Re: [PATCH v5 4/7] clk: qcom: Add Q6SSTOP clock controller for QCS404
From: Stephen Boyd @ 2019-08-08 15:09 UTC (permalink / raw)
To: bjorn.andersson, linux-arm-msm, linux-clk, linux-remoteproc
Cc: andy.gross, linux-soc, devicetree, Govind Singh
In-Reply-To: <20190726092332.25202-5-govinds@codeaurora.org>
Quoting Govind Singh (2019-07-26 02:23:29)
> diff --git a/drivers/clk/qcom/q6sstop-qcs404.c b/drivers/clk/qcom/q6sstop-qcs404.c
> new file mode 100644
> index 000000000000..b6281986b077
> --- /dev/null
> +++ b/drivers/clk/qcom/q6sstop-qcs404.c
> @@ -0,0 +1,223 @@
[...]
> +};
> +
> +static struct platform_driver q6sstopcc_qcs404_driver = {
> + .probe = q6sstopcc_qcs404_probe,
> + .remove = q6sstopcc_qcs404_remove,
> + .driver = {
> + .name = "qcs404-q6sstopcc",
> + .of_match_table = q6sstopcc_qcs404_match_table,
> + .pm = &q6sstopcc_pm_ops,
This got some weird indent.
> + },
> +};
> +
> +module_platform_driver(q6sstopcc_qcs404_driver);
> +
> +MODULE_DESCRIPTION("QTI QCS404 Q6SSTOP Clock Controller Driver");
> +MODULE_LICENSE("GPL v2");
^ permalink raw reply
* Re: [PATCH 3/8] of/fdt: add function to get the SoC wide DMA addressable memory size
From: Rob Herring @ 2019-08-08 15:02 UTC (permalink / raw)
To: Nicolas Saenz Julienne
Cc: Catalin Marinas, Will Deacon, Christoph Hellwig, wahrenst,
Marc Zyngier, Robin Murphy,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
devicetree, Linux IOMMU, linux-mm, Frank Rowand, phill,
Florian Fainelli, linux-kernel@vger.kernel.org, Eric Anholt,
Matthias Brugger, Andrew Morton, Marek Szyprowski,
"moderated list:BROADCOM BCM2835 ARM ARCHITECTURE" <linux-rp>
In-Reply-To: <12eb3aba207c552e5eb727535e7c4f08673c4c80.camel@suse.de>
On Tue, Aug 6, 2019 at 12:12 PM Nicolas Saenz Julienne
<nsaenzjulienne@suse.de> wrote:
>
> Hi Rob,
>
> On Mon, 2019-08-05 at 13:23 -0600, Rob Herring wrote:
> > On Mon, Aug 5, 2019 at 10:03 AM Nicolas Saenz Julienne
> > <nsaenzjulienne@suse.de> wrote:
> > > Hi Rob,
> > > Thanks for the review!
> > >
> > > On Fri, 2019-08-02 at 11:17 -0600, Rob Herring wrote:
> > > > On Wed, Jul 31, 2019 at 9:48 AM Nicolas Saenz Julienne
> > > > <nsaenzjulienne@suse.de> wrote:
> > > > > Some SoCs might have multiple interconnects each with their own DMA
> > > > > addressing limitations. This function parses the 'dma-ranges' on each of
> > > > > them and tries to guess the maximum SoC wide DMA addressable memory
> > > > > size.
> > > > >
> > > > > This is specially useful for arch code in order to properly setup CMA
> > > > > and memory zones.
> > > >
> > > > We already have a way to setup CMA in reserved-memory, so why is this
> > > > needed for that?
> > >
> > > Correct me if I'm wrong but I got the feeling you got the point of the patch
> > > later on.
> >
> > No, for CMA I don't. Can't we already pass a size and location for CMA
> > region under /reserved-memory. The only advantage here is perhaps the
> > CMA range could be anywhere in the DMA zone vs. a fixed location.
>
> Now I get it, sorry I wasn't aware of that interface.
>
> Still, I'm not convinced it matches RPi's use case as this would hard-code
> CMA's size. Most people won't care, but for the ones that do, it's nicer to
> change the value from the kernel command line than editing the dtb.
Sure, I fully agree and am not a fan of the CMA DT overlays I've seen.
> I get that
> if you need to, for example, reserve some memory for the video to work, it's
> silly not to hard-code it. Yet due to the board's nature and users base I say
> it's important to favor flexibility. It would also break compatibility with
> earlier versions of the board and diverge from the downstream kernel behaviour.
> Which is a bigger issue than it seems as most users don't always understand
> which kernel they are running and unknowingly copy configuration options from
> forums.
>
> As I also need to know the DMA addressing limitations to properly configure
> memory zones and dma-direct. Setting up the proper CMA constraints during the
> arch's init will be trivial anyway.
It was really just commentary on commit text as for CMA alone we have
a solution already. I agree on the need for zones.
>
> > > > IMO, I'd just do:
> > > >
> > > > if (of_fdt_machine_is_compatible(blob, "brcm,bcm2711"))
> > > > dma_zone_size = XX;
> > > >
> > > > 2 lines of code is much easier to maintain than 10s of incomplete code
> > > > and is clearer who needs this. Maybe if we have dozens of SoCs with
> > > > this problem we should start parsing dma-ranges.
> > >
> > > FYI that's what arm32 is doing at the moment and was my first instinct. But
> > > it
> > > seems that arm64 has been able to survive so far without any machine
> > > specific
> > > code and I have the feeling Catalin and Will will not be happy about this
> > > solution. Am I wrong?
> >
> > No doubt. I'm fine if the 2 lines live in drivers/of/.
> >
> > Note that I'm trying to reduce the number of early_init_dt_scan_*
> > calls from arch code into the DT code so there's more commonality
> > across architectures in the early DT scans. So ideally, this can all
> > be handled under early_init_dt_scan() call.
>
> How does this look? (I'll split it in two patches and add a comment explaining
> why dt_dma_zone_size is needed)
>
> diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
> index f2444c61a136..1395be40b722 100644
> --- a/drivers/of/fdt.c
> +++ b/drivers/of/fdt.c
> @@ -30,6 +30,8 @@
>
> #include "of_private.h"
>
> +u64 dt_dma_zone_size __ro_after_init;
Avoiding a call from arch code by just having a variable isn't really
better. I'd rather see a common, non DT specific variable that can be
adjusted. Something similar to initrd_start/end. Then the arch code
doesn't have to care what hardware description code adjusted the
value.
Rob
^ permalink raw reply
* Re: [RFC PATCH 09/11] devfreq: exynos-bus: Add interconnect functionality to exynos-bus
From: Leonard Crestez @ 2019-08-08 15:00 UTC (permalink / raw)
To: Chanwoo Choi, Artur Świgoń, georgi.djakov@linaro.org,
Viresh Kumar
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org, dri-devel@lists.freedesktop.org,
krzk@kernel.org, myungjoo.ham@samsung.com, inki.dae@samsung.com,
sw0312.kim@samsung.com, m.szyprowski@samsung.com,
Rafael J. Wysocki, Saravana Kannan, Lukasz Luba
In-Reply-To: <5a82bf8a-d925-ba54-a26f-98b64bedc6e1@samsung.com>
On 29.07.2019 04:49, Chanwoo Choi wrote:
> On 19. 7. 23. 오후 9:20, Artur Świgoń wrote:
>> This patch adds interconnect functionality to the exynos-bus devfreq
>> driver.
>>
>> The devfreq target() callback provided by exynos-bus now selects either the
>> frequency calculated by the devfreq governor or the frequency requested via
>> the interconnect API for the given node, whichever is higher.
>
> Basically, I agree to support the QoS requirement between devices.
> But, I think that need to consider the multiple cases.
>
> 1. When changing the devfreq governor by user,
> For example of the connection between bus_dmc/leftbus/display on patch8,
> there are possible multiple cases with various devfreq governor
> which is changed on the runtime by user through sysfs interface.
>
> If users changes the devfreq governor as following:
> Before,
> - bus_dmc (simple_ondemand, available frequency 100/200/300/400 MHz)
> --> bus_leftbus(simple_ondemand, available frequency 100/200/300/400 MHz)
> ----> bus_display(passive)
>
> After changed governor of bus_dmc,
> if the min_freq by interconnect requirement is 400Mhz,
> - bus_dmc (powersave) : min_freq and max_freq and cur_freq is 100MHz
> --> bus_leftbus(simple_ondemand) : cur_freq is 400Mhz
> ----> bus_display(passive)
>
> The final frequency is 400MHz of bus_dmc
> even if the min_freq/max_freq/cur_freq is 100MHz.
> It cannot show the correct min_freq/max_freq through
> devfreq sysfs interface.
>
>
> 2. When disabling the some frequency by devfreq-thermal throttling,
> This patch checks the min_freq of interconnect requirement
> in the exynos_bus_target() and exynos_bus_passive_target().
> Also, it cannot show the correct min_freq/max_freq through
> devfreq sysfs interface.
>
> For example of bus_dmc bus,
> - The available frequencies are 100MHz, 200MHz, 300MHz, 400MHz
> - Disable 400MHz by devfreq-thermal throttling
> - min_freq is 100MHz
> - max_freq is 300MHz
> - min_freq of interconnect is 400MHz
>
> In result, the final frequency is 400MHz by exynos_bus_target()
> There are no problem for working. But, the user cannot know
> reason why cur_freq is 400MHz even if max_freq is 300MHz.
>
> Basically, update_devfreq() considers the all constraints
> of min_freq/max_freq to decide the proper target frequency.
I think that applying the interconnect min_freq via dev_pm_qos can help
with many of these concerns: update_devfreq controls all the min/max
handling, sysfs is accurate and better decisions can be made regarding
thermal. Enforcing constraints in the core is definitely better.
This wouldn't even be a very big change, you don't need to actually move
the interconnect code outside of devfreq. Just make every devfreq/icc
node register a dev_pm_qos_request for itself during registration and
call dev_pm_qos_update_request inside exynos_bus_icc_set.
See: https://patchwork.kernel.org/patch/11084279/
--
Regards,
Leonard
^ permalink raw reply
* Re: [PATCH v2 2/4] soundwire: core: add device tree support for slave devices
From: Pierre-Louis Bossart @ 2019-08-08 15:00 UTC (permalink / raw)
To: Srinivas Kandagatla, vkoul, broonie
Cc: bgoswami, plai, robh+dt, devicetree, lgirdwood, alsa-devel,
linux-kernel
In-Reply-To: <20190808144504.24823-3-srinivas.kandagatla@linaro.org>
> @@ -35,6 +36,7 @@ static int sdw_slave_add(struct sdw_bus *bus,
>
> slave->dev.release = sdw_slave_release;
> slave->dev.bus = &sdw_bus_type;
> + slave->dev.of_node = of_node_get(to_of_node(fwnode));
shouldn't this protected by
#if IS_ENABLED(CONFIG_OF) ?
> slave->bus = bus;
> slave->status = SDW_SLAVE_UNATTACHED;
> slave->dev_num = 0;
> @@ -112,3 +114,48 @@ int sdw_acpi_find_slaves(struct sdw_bus *bus)
> }
>
> #endif
> +
> +/*
> + * sdw_of_find_slaves() - Find Slave devices in master device tree node
> + * @bus: SDW bus instance
> + *
> + * Scans Master DT node for SDW child Slave devices and registers it.
> + */
> +int sdw_of_find_slaves(struct sdw_bus *bus)
> +{
> + struct device *dev = bus->dev;
> + struct device_node *node;
> +
> + for_each_child_of_node(bus->dev->of_node, node) {
> + struct sdw_slave_id id;
> + const char *compat = NULL;
> + int unique_id, ret;
> + int ver, mfg_id, part_id, class_id;
> +
> + compat = of_get_property(node, "compatible", NULL);
> + if (!compat)
> + continue;
> +
> + ret = sscanf(compat, "sdw%x,%x,%x,%x",
> + &ver, &mfg_id, &part_id, &class_id);
> + if (ret != 4) {
> + dev_err(dev, "Manf ID & Product code not found %s\n",
> + compat);
> + continue;
> + }
> +
> + ret = of_property_read_u32(node, "sdw-instance-id", &unique_id);
> + if (ret) {
> + dev_err(dev, "Instance id not found:%d\n", ret);
> + continue;
I am confused here.
If you have two identical devices on the same link, isn't this property
required and that should be a real error instead of a continue?
> + }
> +
> + id.sdw_version = ver - 0xF;
maybe a comment in the code would help to make the encoding
self-explanatory, as you did in the DT bindings
Version number '0x10' represents SoundWire 1.0
Version number '0x11' represents SoundWire 1.1
> + id.unique_id = unique_id;
> + id.mfg_id = mfg_id;
> + id.part_id = part_id;
> + id.class_id = class_id;
> + sdw_slave_add(bus, &id, of_fwnode_handle(node));
> + }
> + return 0;
> +}
>
^ permalink raw reply
* Re: [PATCH] ARM64: dts: allwinner: Add devicetree for pine H64 modelA evaluation board
From: Clément Péron @ 2019-08-08 14:50 UTC (permalink / raw)
To: clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w
Cc: Mark Rutland, mripard-DgEjT+Ai2ygdnm+yROfE0A, Rob Herring,
Chen-Yu Tsai, devicetree, linux-arm-kernel, linux-kernel,
linux-sunxi
In-Reply-To: <20190808084253.10573-1-clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Hi,
On Thu, 8 Aug 2019 at 10:42, Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>
> This patch adds the evaluation variant of the model A of the PineH64.
> The model A has the same size of the pine64 and has a PCIE slot.
>
> The only devicetree difference with current pineH64, is the PHY
> regulator.
You also need to add the board in
"Documentation/devicetree/bindings/arm/sunxi.yaml"
Regards,
Clément
>
> Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> arch/arm64/boot/dts/allwinner/Makefile | 1 +
> .../sun50i-h6-pine-h64-modelA-eval.dts | 26 +++++++++++++++++++
> 2 files changed, 27 insertions(+)
> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-modelA-eval.dts
>
> diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
> index f6db0611cb85..9a02166cbf72 100644
> --- a/arch/arm64/boot/dts/allwinner/Makefile
> +++ b/arch/arm64/boot/dts/allwinner/Makefile
> @@ -25,3 +25,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
> +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-modelA-eval.dtb
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-modelA-eval.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-modelA-eval.dts
> new file mode 100644
> index 000000000000..d8ff02747efe
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64-modelA-eval.dts
> @@ -0,0 +1,26 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +/*
> + * Copyright (C) 2019 Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> + */
> +
> +#include "sun50i-h6-pine-h64.dts"
> +
> +/ {
> + model = "Pine H64 model A evaluation board";
> + compatible = "pine64,pine-h64-modelA-eval", "allwinner,sun50i-h6";
> +
> + reg_gmac_3v3: gmac-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc-gmac-3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + startup-delay-us = <100000>;
> + gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> +};
> +
> +&emac {
> + phy-supply = <®_gmac_3v3>;
> +};
> --
> 2.21.0
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
> To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20190808084253.10573-1-clabbe.montjoie%40gmail.com.
--
You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/CAJiuCccEQFvKemTodJbuEDzDy9j6-M4SYskxPFJ5DpsbQDnvkA%40mail.gmail.com.
^ permalink raw reply
* Re: [PATCH v15 05/13] clk: ingenic: Add driver for the TCU clocks
From: Stephen Boyd @ 2019-08-08 14:48 UTC (permalink / raw)
To: Arnd Bergmann, Daniel Lezcano, James Hogan, Jason Cooper,
Jonathan Corbet, Lee Jones, Marc Zyngier, Mark Rutland,
Michael Turquette, Paul Burton, Ralf Baechle, Rob Herring,
Thomas Gleixner
Cc: devicetree, linux-kernel, linux-doc, linux-mips, linux-clk, od,
Mathieu Malaterre, Paul Cercueil, Artur Rojek
In-Reply-To: <20190724171615.20774-6-paul@crapouillou.net>
Quoting Paul Cercueil (2019-07-24 10:16:07)
> Add driver to support the clocks provided by the Timer/Counter Unit
> (TCU) of the JZ47xx SoCs from Ingenic.
>
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> Tested-by: Mathieu Malaterre <malat@debian.org>
> Tested-by: Artur Rojek <contact@artur-rojek.eu>
> ---
Acked-by: Stephen Boyd <sboyd@kernel.org>
^ permalink raw reply
* [PATCH v2 4/4] ASoC: codecs: add wsa881x amplifier support
From: Srinivas Kandagatla @ 2019-08-08 14:45 UTC (permalink / raw)
To: vkoul, broonie
Cc: bgoswami, plai, pierre-louis.bossart, robh+dt, devicetree,
lgirdwood, alsa-devel, linux-kernel, Srinivas Kandagatla
In-Reply-To: <20190808144504.24823-1-srinivas.kandagatla@linaro.org>
This patch adds support to WSA8810/WSA8815 Class-D Smart Speaker
Amplifier. This Amplifier is primarily interfaced with SoundWire.
One WSA is used for mono speaker configuration and second one
would give stereo setup.
This patch is tested on SDM845 based DragonBoard DB845c.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
sound/soc/codecs/Kconfig | 10 +
sound/soc/codecs/Makefile | 2 +
sound/soc/codecs/wsa881x.c | 1160 ++++++++++++++++++++++++++++++++++++
3 files changed, 1172 insertions(+)
create mode 100644 sound/soc/codecs/wsa881x.c
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 89238343e34d..9f8fa1016d22 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -203,6 +203,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_UDA134X
select SND_SOC_UDA1380 if I2C
select SND_SOC_WCD9335 if SLIMBUS
+ select SND_SOC_WSA881X if SOUNDWIRE
select SND_SOC_WL1273 if MFD_WL1273_CORE
select SND_SOC_WM0010 if SPI_MASTER
select SND_SOC_WM1250_EV1 if I2C
@@ -1233,6 +1234,15 @@ config SND_SOC_WCD9335
Qualcomm Technologies, Inc. (QTI) multimedia solutions,
including the MSM8996, MSM8976, and MSM8956 chipsets.
+config SND_SOC_WSA881X
+ tristate "WSA881X Codec"
+ depends on SOUNDWIRE
+ select REGMAP_SOUNDWIRE
+ tristate
+ help
+ This enables support for Qualcomm WSA8810/WSA8815 Class-D
+ Smart Speaker Amplifier.
+
config SND_SOC_WL1273
tristate
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index c498373dcc5f..ab07becf31f8 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -216,6 +216,7 @@ snd-soc-uda1334-objs := uda1334.o
snd-soc-uda134x-objs := uda134x.o
snd-soc-uda1380-objs := uda1380.o
snd-soc-wcd9335-objs := wcd-clsh-v2.o wcd9335.o
+snd-soc-wsa881x-objs := wsa881x.o
snd-soc-wl1273-objs := wl1273.o
snd-soc-wm-adsp-objs := wm_adsp.o
snd-soc-wm0010-objs := wm0010.o
@@ -499,6 +500,7 @@ obj-$(CONFIG_SND_SOC_UDA1334) += snd-soc-uda1334.o
obj-$(CONFIG_SND_SOC_UDA134X) += snd-soc-uda134x.o
obj-$(CONFIG_SND_SOC_UDA1380) += snd-soc-uda1380.o
obj-$(CONFIG_SND_SOC_WCD9335) += snd-soc-wcd9335.o
+obj-$(CONFIG_SND_SOC_WSA881X) += snd-soc-wsa881x.o
obj-$(CONFIG_SND_SOC_WL1273) += snd-soc-wl1273.o
obj-$(CONFIG_SND_SOC_WM0010) += snd-soc-wm0010.o
obj-$(CONFIG_SND_SOC_WM1250_EV1) += snd-soc-wm1250-ev1.o
diff --git a/sound/soc/codecs/wsa881x.c b/sound/soc/codecs/wsa881x.c
new file mode 100644
index 000000000000..7bf72b3e6f7c
--- /dev/null
+++ b/sound/soc/codecs/wsa881x.c
@@ -0,0 +1,1160 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2015-2017, The Linux Foundation.
+// Copyright (c) 2019, Linaro Limited
+
+#include <linux/bitops.h>
+#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/soundwire/sdw.h>
+#include <linux/soundwire/sdw_registers.h>
+#include <linux/soundwire/sdw_type.h>
+#include <sound/soc.h>
+#include <sound/tlv.h>
+
+#define WSA881X_DIGITAL_BASE 0x3000
+#define WSA881X_ANALOG_BASE 0x3100
+
+/* Digital register address space */
+#define WSA881X_CHIP_ID0 (WSA881X_DIGITAL_BASE + 0x0000)
+#define WSA881X_CHIP_ID1 (WSA881X_DIGITAL_BASE + 0x0001)
+#define WSA881X_CHIP_ID2 (WSA881X_DIGITAL_BASE + 0x0002)
+#define WSA881X_CHIP_ID3 (WSA881X_DIGITAL_BASE + 0x0003)
+#define WSA881X_BUS_ID (WSA881X_DIGITAL_BASE + 0x0004)
+#define WSA881X_CDC_RST_CTL (WSA881X_DIGITAL_BASE + 0x0005)
+#define WSA881X_CDC_TOP_CLK_CTL (WSA881X_DIGITAL_BASE + 0x0006)
+#define WSA881X_CDC_ANA_CLK_CTL (WSA881X_DIGITAL_BASE + 0x0007)
+#define WSA881X_CDC_DIG_CLK_CTL (WSA881X_DIGITAL_BASE + 0x0008)
+#define WSA881X_CLOCK_CONFIG (WSA881X_DIGITAL_BASE + 0x0009)
+#define WSA881X_ANA_CTL (WSA881X_DIGITAL_BASE + 0x000A)
+#define WSA881X_SWR_RESET_EN (WSA881X_DIGITAL_BASE + 0x000B)
+#define WSA881X_RESET_CTL (WSA881X_DIGITAL_BASE + 0x000C)
+#define WSA881X_TADC_VALUE_CTL (WSA881X_DIGITAL_BASE + 0x000F)
+#define WSA881X_TEMP_DETECT_CTL (WSA881X_DIGITAL_BASE + 0x0010)
+#define WSA881X_TEMP_MSB (WSA881X_DIGITAL_BASE + 0x0011)
+#define WSA881X_TEMP_LSB (WSA881X_DIGITAL_BASE + 0x0012)
+#define WSA881X_TEMP_CONFIG0 (WSA881X_DIGITAL_BASE + 0x0013)
+#define WSA881X_TEMP_CONFIG1 (WSA881X_DIGITAL_BASE + 0x0014)
+#define WSA881X_CDC_CLIP_CTL (WSA881X_DIGITAL_BASE + 0x0015)
+#define WSA881X_SDM_PDM9_LSB (WSA881X_DIGITAL_BASE + 0x0016)
+#define WSA881X_SDM_PDM9_MSB (WSA881X_DIGITAL_BASE + 0x0017)
+#define WSA881X_CDC_RX_CTL (WSA881X_DIGITAL_BASE + 0x0018)
+#define WSA881X_DEM_BYPASS_DATA0 (WSA881X_DIGITAL_BASE + 0x0019)
+#define WSA881X_DEM_BYPASS_DATA1 (WSA881X_DIGITAL_BASE + 0x001A)
+#define WSA881X_DEM_BYPASS_DATA2 (WSA881X_DIGITAL_BASE + 0x001B)
+#define WSA881X_DEM_BYPASS_DATA3 (WSA881X_DIGITAL_BASE + 0x001C)
+#define WSA881X_OTP_CTRL0 (WSA881X_DIGITAL_BASE + 0x001D)
+#define WSA881X_OTP_CTRL1 (WSA881X_DIGITAL_BASE + 0x001E)
+#define WSA881X_HDRIVE_CTL_GROUP1 (WSA881X_DIGITAL_BASE + 0x001F)
+#define WSA881X_INTR_MODE (WSA881X_DIGITAL_BASE + 0x0020)
+#define WSA881X_INTR_MASK (WSA881X_DIGITAL_BASE + 0x0021)
+#define WSA881X_INTR_STATUS (WSA881X_DIGITAL_BASE + 0x0022)
+#define WSA881X_INTR_CLEAR (WSA881X_DIGITAL_BASE + 0x0023)
+#define WSA881X_INTR_LEVEL (WSA881X_DIGITAL_BASE + 0x0024)
+#define WSA881X_INTR_SET (WSA881X_DIGITAL_BASE + 0x0025)
+#define WSA881X_INTR_TEST (WSA881X_DIGITAL_BASE + 0x0026)
+#define WSA881X_PDM_TEST_MODE (WSA881X_DIGITAL_BASE + 0x0030)
+#define WSA881X_ATE_TEST_MODE (WSA881X_DIGITAL_BASE + 0x0031)
+#define WSA881X_PIN_CTL_MODE (WSA881X_DIGITAL_BASE + 0x0032)
+#define WSA881X_PIN_CTL_OE (WSA881X_DIGITAL_BASE + 0x0033)
+#define WSA881X_PIN_WDATA_IOPAD (WSA881X_DIGITAL_BASE + 0x0034)
+#define WSA881X_PIN_STATUS (WSA881X_DIGITAL_BASE + 0x0035)
+#define WSA881X_DIG_DEBUG_MODE (WSA881X_DIGITAL_BASE + 0x0037)
+#define WSA881X_DIG_DEBUG_SEL (WSA881X_DIGITAL_BASE + 0x0038)
+#define WSA881X_DIG_DEBUG_EN (WSA881X_DIGITAL_BASE + 0x0039)
+#define WSA881X_SWR_HM_TEST1 (WSA881X_DIGITAL_BASE + 0x003B)
+#define WSA881X_SWR_HM_TEST2 (WSA881X_DIGITAL_BASE + 0x003C)
+#define WSA881X_TEMP_DETECT_DBG_CTL (WSA881X_DIGITAL_BASE + 0x003D)
+#define WSA881X_TEMP_DEBUG_MSB (WSA881X_DIGITAL_BASE + 0x003E)
+#define WSA881X_TEMP_DEBUG_LSB (WSA881X_DIGITAL_BASE + 0x003F)
+#define WSA881X_SAMPLE_EDGE_SEL (WSA881X_DIGITAL_BASE + 0x0044)
+#define WSA881X_IOPAD_CTL (WSA881X_DIGITAL_BASE + 0x0045)
+#define WSA881X_SPARE_0 (WSA881X_DIGITAL_BASE + 0x0050)
+#define WSA881X_SPARE_1 (WSA881X_DIGITAL_BASE + 0x0051)
+#define WSA881X_SPARE_2 (WSA881X_DIGITAL_BASE + 0x0052)
+#define WSA881X_OTP_REG_0 (WSA881X_DIGITAL_BASE + 0x0080)
+#define WSA881X_OTP_REG_1 (WSA881X_DIGITAL_BASE + 0x0081)
+#define WSA881X_OTP_REG_2 (WSA881X_DIGITAL_BASE + 0x0082)
+#define WSA881X_OTP_REG_3 (WSA881X_DIGITAL_BASE + 0x0083)
+#define WSA881X_OTP_REG_4 (WSA881X_DIGITAL_BASE + 0x0084)
+#define WSA881X_OTP_REG_5 (WSA881X_DIGITAL_BASE + 0x0085)
+#define WSA881X_OTP_REG_6 (WSA881X_DIGITAL_BASE + 0x0086)
+#define WSA881X_OTP_REG_7 (WSA881X_DIGITAL_BASE + 0x0087)
+#define WSA881X_OTP_REG_8 (WSA881X_DIGITAL_BASE + 0x0088)
+#define WSA881X_OTP_REG_9 (WSA881X_DIGITAL_BASE + 0x0089)
+#define WSA881X_OTP_REG_10 (WSA881X_DIGITAL_BASE + 0x008A)
+#define WSA881X_OTP_REG_11 (WSA881X_DIGITAL_BASE + 0x008B)
+#define WSA881X_OTP_REG_12 (WSA881X_DIGITAL_BASE + 0x008C)
+#define WSA881X_OTP_REG_13 (WSA881X_DIGITAL_BASE + 0x008D)
+#define WSA881X_OTP_REG_14 (WSA881X_DIGITAL_BASE + 0x008E)
+#define WSA881X_OTP_REG_15 (WSA881X_DIGITAL_BASE + 0x008F)
+#define WSA881X_OTP_REG_16 (WSA881X_DIGITAL_BASE + 0x0090)
+#define WSA881X_OTP_REG_17 (WSA881X_DIGITAL_BASE + 0x0091)
+#define WSA881X_OTP_REG_18 (WSA881X_DIGITAL_BASE + 0x0092)
+#define WSA881X_OTP_REG_19 (WSA881X_DIGITAL_BASE + 0x0093)
+#define WSA881X_OTP_REG_20 (WSA881X_DIGITAL_BASE + 0x0094)
+#define WSA881X_OTP_REG_21 (WSA881X_DIGITAL_BASE + 0x0095)
+#define WSA881X_OTP_REG_22 (WSA881X_DIGITAL_BASE + 0x0096)
+#define WSA881X_OTP_REG_23 (WSA881X_DIGITAL_BASE + 0x0097)
+#define WSA881X_OTP_REG_24 (WSA881X_DIGITAL_BASE + 0x0098)
+#define WSA881X_OTP_REG_25 (WSA881X_DIGITAL_BASE + 0x0099)
+#define WSA881X_OTP_REG_26 (WSA881X_DIGITAL_BASE + 0x009A)
+#define WSA881X_OTP_REG_27 (WSA881X_DIGITAL_BASE + 0x009B)
+#define WSA881X_OTP_REG_28 (WSA881X_DIGITAL_BASE + 0x009C)
+#define WSA881X_OTP_REG_29 (WSA881X_DIGITAL_BASE + 0x009D)
+#define WSA881X_OTP_REG_30 (WSA881X_DIGITAL_BASE + 0x009E)
+#define WSA881X_OTP_REG_31 (WSA881X_DIGITAL_BASE + 0x009F)
+#define WSA881X_OTP_REG_63 (WSA881X_DIGITAL_BASE + 0x00BF)
+
+/* Analog Register address space */
+#define WSA881X_BIAS_REF_CTRL (WSA881X_ANALOG_BASE + 0x0000)
+#define WSA881X_BIAS_TEST (WSA881X_ANALOG_BASE + 0x0001)
+#define WSA881X_BIAS_BIAS (WSA881X_ANALOG_BASE + 0x0002)
+#define WSA881X_TEMP_OP (WSA881X_ANALOG_BASE + 0x0003)
+#define WSA881X_TEMP_IREF_CTRL (WSA881X_ANALOG_BASE + 0x0004)
+#define WSA881X_TEMP_ISENS_CTRL (WSA881X_ANALOG_BASE + 0x0005)
+#define WSA881X_TEMP_CLK_CTRL (WSA881X_ANALOG_BASE + 0x0006)
+#define WSA881X_TEMP_TEST (WSA881X_ANALOG_BASE + 0x0007)
+#define WSA881X_TEMP_BIAS (WSA881X_ANALOG_BASE + 0x0008)
+#define WSA881X_TEMP_ADC_CTRL (WSA881X_ANALOG_BASE + 0x0009)
+#define WSA881X_TEMP_DOUT_MSB (WSA881X_ANALOG_BASE + 0x000A)
+#define WSA881X_TEMP_DOUT_LSB (WSA881X_ANALOG_BASE + 0x000B)
+#define WSA881X_ADC_EN_MODU_V (WSA881X_ANALOG_BASE + 0x0010)
+#define WSA881X_ADC_EN_MODU_I (WSA881X_ANALOG_BASE + 0x0011)
+#define WSA881X_ADC_EN_DET_TEST_V (WSA881X_ANALOG_BASE + 0x0012)
+#define WSA881X_ADC_EN_DET_TEST_I (WSA881X_ANALOG_BASE + 0x0013)
+#define WSA881X_ADC_SEL_IBIAS (WSA881X_ANALOG_BASE + 0x0014)
+#define WSA881X_ADC_EN_SEL_IBAIS (WSA881X_ANALOG_BASE + 0x0015)
+#define WSA881X_SPKR_DRV_EN (WSA881X_ANALOG_BASE + 0x001A)
+#define WSA881X_SPKR_DRV_GAIN (WSA881X_ANALOG_BASE + 0x001B)
+#define WSA881X_SPKR_DAC_CTL (WSA881X_ANALOG_BASE + 0x001C)
+#define WSA881X_SPKR_DRV_DBG (WSA881X_ANALOG_BASE + 0x001D)
+#define WSA881X_SPKR_PWRSTG_DBG (WSA881X_ANALOG_BASE + 0x001E)
+#define WSA881X_SPKR_OCP_CTL (WSA881X_ANALOG_BASE + 0x001F)
+#define WSA881X_SPKR_CLIP_CTL (WSA881X_ANALOG_BASE + 0x0020)
+#define WSA881X_SPKR_BBM_CTL (WSA881X_ANALOG_BASE + 0x0021)
+#define WSA881X_SPKR_MISC_CTL1 (WSA881X_ANALOG_BASE + 0x0022)
+#define WSA881X_SPKR_MISC_CTL2 (WSA881X_ANALOG_BASE + 0x0023)
+#define WSA881X_SPKR_BIAS_INT (WSA881X_ANALOG_BASE + 0x0024)
+#define WSA881X_SPKR_PA_INT (WSA881X_ANALOG_BASE + 0x0025)
+#define WSA881X_SPKR_BIAS_CAL (WSA881X_ANALOG_BASE + 0x0026)
+#define WSA881X_SPKR_BIAS_PSRR (WSA881X_ANALOG_BASE + 0x0027)
+#define WSA881X_SPKR_STATUS1 (WSA881X_ANALOG_BASE + 0x0028)
+#define WSA881X_SPKR_STATUS2 (WSA881X_ANALOG_BASE + 0x0029)
+#define WSA881X_BOOST_EN_CTL (WSA881X_ANALOG_BASE + 0x002A)
+#define WSA881X_BOOST_CURRENT_LIMIT (WSA881X_ANALOG_BASE + 0x002B)
+#define WSA881X_BOOST_PS_CTL (WSA881X_ANALOG_BASE + 0x002C)
+#define WSA881X_BOOST_PRESET_OUT1 (WSA881X_ANALOG_BASE + 0x002D)
+#define WSA881X_BOOST_PRESET_OUT2 (WSA881X_ANALOG_BASE + 0x002E)
+#define WSA881X_BOOST_FORCE_OUT (WSA881X_ANALOG_BASE + 0x002F)
+#define WSA881X_BOOST_LDO_PROG (WSA881X_ANALOG_BASE + 0x0030)
+#define WSA881X_BOOST_SLOPE_COMP_ISENSE_FB (WSA881X_ANALOG_BASE + 0x0031)
+#define WSA881X_BOOST_RON_CTL (WSA881X_ANALOG_BASE + 0x0032)
+#define WSA881X_BOOST_LOOP_STABILITY (WSA881X_ANALOG_BASE + 0x0033)
+#define WSA881X_BOOST_ZX_CTL (WSA881X_ANALOG_BASE + 0x0034)
+#define WSA881X_BOOST_START_CTL (WSA881X_ANALOG_BASE + 0x0035)
+#define WSA881X_BOOST_MISC1_CTL (WSA881X_ANALOG_BASE + 0x0036)
+#define WSA881X_BOOST_MISC2_CTL (WSA881X_ANALOG_BASE + 0x0037)
+#define WSA881X_BOOST_MISC3_CTL (WSA881X_ANALOG_BASE + 0x0038)
+#define WSA881X_BOOST_ATEST_CTL (WSA881X_ANALOG_BASE + 0x0039)
+#define WSA881X_SPKR_PROT_FE_GAIN (WSA881X_ANALOG_BASE + 0x003A)
+#define WSA881X_SPKR_PROT_FE_CM_LDO_SET (WSA881X_ANALOG_BASE + 0x003B)
+#define WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1 (WSA881X_ANALOG_BASE + 0x003C)
+#define WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2 (WSA881X_ANALOG_BASE + 0x003D)
+#define WSA881X_SPKR_PROT_ATEST1 (WSA881X_ANALOG_BASE + 0x003E)
+#define WSA881X_SPKR_PROT_ATEST2 (WSA881X_ANALOG_BASE + 0x003F)
+#define WSA881X_SPKR_PROT_FE_VSENSE_VCM (WSA881X_ANALOG_BASE + 0x0040)
+#define WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1 (WSA881X_ANALOG_BASE + 0x0041)
+#define WSA881X_BONGO_RESRV_REG1 (WSA881X_ANALOG_BASE + 0x0042)
+#define WSA881X_BONGO_RESRV_REG2 (WSA881X_ANALOG_BASE + 0x0043)
+#define WSA881X_SPKR_PROT_SAR (WSA881X_ANALOG_BASE + 0x0044)
+#define WSA881X_SPKR_STATUS3 (WSA881X_ANALOG_BASE + 0x0045)
+
+#define SWRS_SCP_FRAME_CTRL_BANK(m) (0x60 + 0x10 * (m))
+#define SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(m) (0xE0 + 0x10 * (m))
+
+#define WSA881X_NUM_REGISTERS (WSA881X_SPKR_STATUS3 + 1)
+#define WSA881X_MAX_REGISTER (WSA881X_NUM_REGISTERS - 1)
+#define WSA881X_CACHE_SIZE WSA881X_NUM_REGISTERS
+#define SWR_SLV_MAX_REG_ADDR 0x390
+#define SWR_SLV_START_REG_ADDR 0x40
+#define SWR_SLV_MAX_BUF_LEN 20
+#define BYTES_PER_LINE 12
+#define SWR_SLV_RD_BUF_LEN 8
+#define SWR_SLV_WR_BUF_LEN 32
+#define SWR_SLV_MAX_DEVICES 2
+#define WSA881X_MAX_SWR_PORTS 4
+#define WSA881X_VERSION_ENTRY_SIZE 27
+#define WSA881X_OCP_CTL_TIMER_SEC 2
+#define WSA881X_OCP_CTL_TEMP_CELSIUS 25
+#define WSA881X_OCP_CTL_POLL_TIMER_SEC 60
+
+#define WSA881X_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
+{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
+ .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
+ SNDRV_CTL_ELEM_ACCESS_READWRITE,\
+ .tlv.p = (tlv_array), \
+ .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
+ .put = wsa881x_put_pa_gain, \
+ .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
+
+static const u8 wsa881x_reg_readable[WSA881X_CACHE_SIZE] = {
+ [WSA881X_CHIP_ID0] = 1,
+ [WSA881X_CHIP_ID1] = 1,
+ [WSA881X_CHIP_ID2] = 1,
+ [WSA881X_CHIP_ID3] = 1,
+ [WSA881X_BUS_ID] = 1,
+ [WSA881X_CDC_RST_CTL] = 1,
+ [WSA881X_CDC_TOP_CLK_CTL] = 1,
+ [WSA881X_CDC_ANA_CLK_CTL] = 1,
+ [WSA881X_CDC_DIG_CLK_CTL] = 1,
+ [WSA881X_CLOCK_CONFIG] = 1,
+ [WSA881X_ANA_CTL] = 1,
+ [WSA881X_SWR_RESET_EN] = 1,
+ [WSA881X_RESET_CTL] = 1,
+ [WSA881X_TADC_VALUE_CTL] = 1,
+ [WSA881X_TEMP_DETECT_CTL] = 1,
+ [WSA881X_TEMP_MSB] = 1,
+ [WSA881X_TEMP_LSB] = 1,
+ [WSA881X_TEMP_CONFIG0] = 1,
+ [WSA881X_TEMP_CONFIG1] = 1,
+ [WSA881X_CDC_CLIP_CTL] = 1,
+ [WSA881X_SDM_PDM9_LSB] = 1,
+ [WSA881X_SDM_PDM9_MSB] = 1,
+ [WSA881X_CDC_RX_CTL] = 1,
+ [WSA881X_DEM_BYPASS_DATA0] = 1,
+ [WSA881X_DEM_BYPASS_DATA1] = 1,
+ [WSA881X_DEM_BYPASS_DATA2] = 1,
+ [WSA881X_DEM_BYPASS_DATA3] = 1,
+ [WSA881X_OTP_CTRL0] = 1,
+ [WSA881X_OTP_CTRL1] = 1,
+ [WSA881X_HDRIVE_CTL_GROUP1] = 1,
+ [WSA881X_INTR_MODE] = 1,
+ [WSA881X_INTR_MASK] = 1,
+ [WSA881X_INTR_STATUS] = 1,
+ [WSA881X_INTR_CLEAR] = 1,
+ [WSA881X_INTR_LEVEL] = 1,
+ [WSA881X_INTR_SET] = 1,
+ [WSA881X_INTR_TEST] = 1,
+ [WSA881X_PDM_TEST_MODE] = 1,
+ [WSA881X_ATE_TEST_MODE] = 1,
+ [WSA881X_PIN_CTL_MODE] = 1,
+ [WSA881X_PIN_CTL_OE] = 1,
+ [WSA881X_PIN_WDATA_IOPAD] = 1,
+ [WSA881X_PIN_STATUS] = 1,
+ [WSA881X_DIG_DEBUG_MODE] = 1,
+ [WSA881X_DIG_DEBUG_SEL] = 1,
+ [WSA881X_DIG_DEBUG_EN] = 1,
+ [WSA881X_SWR_HM_TEST1] = 1,
+ [WSA881X_SWR_HM_TEST2] = 1,
+ [WSA881X_TEMP_DETECT_DBG_CTL] = 1,
+ [WSA881X_TEMP_DEBUG_MSB] = 1,
+ [WSA881X_TEMP_DEBUG_LSB] = 1,
+ [WSA881X_SAMPLE_EDGE_SEL] = 1,
+ [WSA881X_IOPAD_CTL] = 1,
+ [WSA881X_SPARE_0] = 1,
+ [WSA881X_SPARE_1] = 1,
+ [WSA881X_SPARE_2] = 1,
+ [WSA881X_OTP_REG_0] = 1,
+ [WSA881X_OTP_REG_1] = 1,
+ [WSA881X_OTP_REG_2] = 1,
+ [WSA881X_OTP_REG_3] = 1,
+ [WSA881X_OTP_REG_4] = 1,
+ [WSA881X_OTP_REG_5] = 1,
+ [WSA881X_OTP_REG_6] = 1,
+ [WSA881X_OTP_REG_7] = 1,
+ [WSA881X_OTP_REG_8] = 1,
+ [WSA881X_OTP_REG_9] = 1,
+ [WSA881X_OTP_REG_10] = 1,
+ [WSA881X_OTP_REG_11] = 1,
+ [WSA881X_OTP_REG_12] = 1,
+ [WSA881X_OTP_REG_13] = 1,
+ [WSA881X_OTP_REG_14] = 1,
+ [WSA881X_OTP_REG_15] = 1,
+ [WSA881X_OTP_REG_16] = 1,
+ [WSA881X_OTP_REG_17] = 1,
+ [WSA881X_OTP_REG_18] = 1,
+ [WSA881X_OTP_REG_19] = 1,
+ [WSA881X_OTP_REG_20] = 1,
+ [WSA881X_OTP_REG_21] = 1,
+ [WSA881X_OTP_REG_22] = 1,
+ [WSA881X_OTP_REG_23] = 1,
+ [WSA881X_OTP_REG_24] = 1,
+ [WSA881X_OTP_REG_25] = 1,
+ [WSA881X_OTP_REG_26] = 1,
+ [WSA881X_OTP_REG_27] = 1,
+ [WSA881X_OTP_REG_28] = 1,
+ [WSA881X_OTP_REG_29] = 1,
+ [WSA881X_OTP_REG_30] = 1,
+ [WSA881X_OTP_REG_31] = 1,
+ [WSA881X_OTP_REG_63] = 1,
+ /* Analog Registers */
+ [WSA881X_BIAS_REF_CTRL] = 1,
+ [WSA881X_BIAS_TEST] = 1,
+ [WSA881X_BIAS_BIAS] = 1,
+ [WSA881X_TEMP_OP] = 1,
+ [WSA881X_TEMP_IREF_CTRL] = 1,
+ [WSA881X_TEMP_ISENS_CTRL] = 1,
+ [WSA881X_TEMP_CLK_CTRL] = 1,
+ [WSA881X_TEMP_TEST] = 1,
+ [WSA881X_TEMP_BIAS] = 1,
+ [WSA881X_TEMP_ADC_CTRL] = 1,
+ [WSA881X_TEMP_DOUT_MSB] = 1,
+ [WSA881X_TEMP_DOUT_LSB] = 1,
+ [WSA881X_ADC_EN_MODU_V] = 1,
+ [WSA881X_ADC_EN_MODU_I] = 1,
+ [WSA881X_ADC_EN_DET_TEST_V] = 1,
+ [WSA881X_ADC_EN_DET_TEST_I] = 1,
+ [WSA881X_ADC_SEL_IBIAS] = 1,
+ [WSA881X_ADC_EN_SEL_IBAIS] = 1,
+ [WSA881X_SPKR_DRV_EN] = 1,
+ [WSA881X_SPKR_DRV_GAIN] = 1,
+ [WSA881X_SPKR_DAC_CTL] = 1,
+ [WSA881X_SPKR_DRV_DBG] = 1,
+ [WSA881X_SPKR_PWRSTG_DBG] = 1,
+ [WSA881X_SPKR_OCP_CTL] = 1,
+ [WSA881X_SPKR_CLIP_CTL] = 1,
+ [WSA881X_SPKR_BBM_CTL] = 1,
+ [WSA881X_SPKR_MISC_CTL1] = 1,
+ [WSA881X_SPKR_MISC_CTL2] = 1,
+ [WSA881X_SPKR_BIAS_INT] = 1,
+ [WSA881X_SPKR_PA_INT] = 1,
+ [WSA881X_SPKR_BIAS_CAL] = 1,
+ [WSA881X_SPKR_BIAS_PSRR] = 1,
+ [WSA881X_SPKR_STATUS1] = 1,
+ [WSA881X_SPKR_STATUS2] = 1,
+ [WSA881X_BOOST_EN_CTL] = 1,
+ [WSA881X_BOOST_CURRENT_LIMIT] = 1,
+ [WSA881X_BOOST_PS_CTL] = 1,
+ [WSA881X_BOOST_PRESET_OUT1] = 1,
+ [WSA881X_BOOST_PRESET_OUT2] = 1,
+ [WSA881X_BOOST_FORCE_OUT] = 1,
+ [WSA881X_BOOST_LDO_PROG] = 1,
+ [WSA881X_BOOST_SLOPE_COMP_ISENSE_FB] = 1,
+ [WSA881X_BOOST_RON_CTL] = 1,
+ [WSA881X_BOOST_LOOP_STABILITY] = 1,
+ [WSA881X_BOOST_ZX_CTL] = 1,
+ [WSA881X_BOOST_START_CTL] = 1,
+ [WSA881X_BOOST_MISC1_CTL] = 1,
+ [WSA881X_BOOST_MISC2_CTL] = 1,
+ [WSA881X_BOOST_MISC3_CTL] = 1,
+ [WSA881X_BOOST_ATEST_CTL] = 1,
+ [WSA881X_SPKR_PROT_FE_GAIN] = 1,
+ [WSA881X_SPKR_PROT_FE_CM_LDO_SET] = 1,
+ [WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1] = 1,
+ [WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2] = 1,
+ [WSA881X_SPKR_PROT_ATEST1] = 1,
+ [WSA881X_SPKR_PROT_ATEST2] = 1,
+ [WSA881X_SPKR_PROT_FE_VSENSE_VCM] = 1,
+ [WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1] = 1,
+ [WSA881X_BONGO_RESRV_REG1] = 1,
+ [WSA881X_BONGO_RESRV_REG2] = 1,
+ [WSA881X_SPKR_PROT_SAR] = 1,
+ [WSA881X_SPKR_STATUS3] = 1,
+};
+
+static struct reg_default wsa881x_defaults[] = {
+ {WSA881X_CHIP_ID0, 0x00},
+ {WSA881X_CHIP_ID1, 0x00},
+ {WSA881X_CHIP_ID2, 0x00},
+ {WSA881X_CHIP_ID3, 0x02},
+ {WSA881X_BUS_ID, 0x00},
+ {WSA881X_CDC_RST_CTL, 0x00},
+ {WSA881X_CDC_TOP_CLK_CTL, 0x03},
+ {WSA881X_CDC_ANA_CLK_CTL, 0x00},
+ {WSA881X_CDC_DIG_CLK_CTL, 0x00},
+ {WSA881X_CLOCK_CONFIG, 0x00},
+ {WSA881X_ANA_CTL, 0x08},
+ {WSA881X_SWR_RESET_EN, 0x00},
+ {WSA881X_TEMP_DETECT_CTL, 0x01},
+ {WSA881X_TEMP_MSB, 0x00},
+ {WSA881X_TEMP_LSB, 0x00},
+ {WSA881X_TEMP_CONFIG0, 0x00},
+ {WSA881X_TEMP_CONFIG1, 0x00},
+ {WSA881X_CDC_CLIP_CTL, 0x03},
+ {WSA881X_SDM_PDM9_LSB, 0x00},
+ {WSA881X_SDM_PDM9_MSB, 0x00},
+ {WSA881X_CDC_RX_CTL, 0x7E},
+ {WSA881X_DEM_BYPASS_DATA0, 0x00},
+ {WSA881X_DEM_BYPASS_DATA1, 0x00},
+ {WSA881X_DEM_BYPASS_DATA2, 0x00},
+ {WSA881X_DEM_BYPASS_DATA3, 0x00},
+ {WSA881X_OTP_CTRL0, 0x00},
+ {WSA881X_OTP_CTRL1, 0x00},
+ {WSA881X_HDRIVE_CTL_GROUP1, 0x00},
+ {WSA881X_INTR_MODE, 0x00},
+ {WSA881X_INTR_STATUS, 0x00},
+ {WSA881X_INTR_CLEAR, 0x00},
+ {WSA881X_INTR_LEVEL, 0x00},
+ {WSA881X_INTR_SET, 0x00},
+ {WSA881X_INTR_TEST, 0x00},
+ {WSA881X_PDM_TEST_MODE, 0x00},
+ {WSA881X_ATE_TEST_MODE, 0x00},
+ {WSA881X_PIN_CTL_MODE, 0x00},
+ {WSA881X_PIN_CTL_OE, 0x00},
+ {WSA881X_PIN_WDATA_IOPAD, 0x00},
+ {WSA881X_PIN_STATUS, 0x00},
+ {WSA881X_DIG_DEBUG_MODE, 0x00},
+ {WSA881X_DIG_DEBUG_SEL, 0x00},
+ {WSA881X_DIG_DEBUG_EN, 0x00},
+ {WSA881X_SWR_HM_TEST1, 0x08},
+ {WSA881X_SWR_HM_TEST2, 0x00},
+ {WSA881X_TEMP_DETECT_DBG_CTL, 0x00},
+ {WSA881X_TEMP_DEBUG_MSB, 0x00},
+ {WSA881X_TEMP_DEBUG_LSB, 0x00},
+ {WSA881X_SAMPLE_EDGE_SEL, 0x0C},
+ {WSA881X_SPARE_0, 0x00},
+ {WSA881X_SPARE_1, 0x00},
+ {WSA881X_SPARE_2, 0x00},
+ {WSA881X_OTP_REG_0, 0x01},
+ {WSA881X_OTP_REG_1, 0xFF},
+ {WSA881X_OTP_REG_2, 0xC0},
+ {WSA881X_OTP_REG_3, 0xFF},
+ {WSA881X_OTP_REG_4, 0xC0},
+ {WSA881X_OTP_REG_5, 0xFF},
+ {WSA881X_OTP_REG_6, 0xFF},
+ {WSA881X_OTP_REG_7, 0xFF},
+ {WSA881X_OTP_REG_8, 0xFF},
+ {WSA881X_OTP_REG_9, 0xFF},
+ {WSA881X_OTP_REG_10, 0xFF},
+ {WSA881X_OTP_REG_11, 0xFF},
+ {WSA881X_OTP_REG_12, 0xFF},
+ {WSA881X_OTP_REG_13, 0xFF},
+ {WSA881X_OTP_REG_14, 0xFF},
+ {WSA881X_OTP_REG_15, 0xFF},
+ {WSA881X_OTP_REG_16, 0xFF},
+ {WSA881X_OTP_REG_17, 0xFF},
+ {WSA881X_OTP_REG_18, 0xFF},
+ {WSA881X_OTP_REG_19, 0xFF},
+ {WSA881X_OTP_REG_20, 0xFF},
+ {WSA881X_OTP_REG_21, 0xFF},
+ {WSA881X_OTP_REG_22, 0xFF},
+ {WSA881X_OTP_REG_23, 0xFF},
+ {WSA881X_OTP_REG_24, 0x03},
+ {WSA881X_OTP_REG_25, 0x01},
+ {WSA881X_OTP_REG_26, 0x03},
+ {WSA881X_OTP_REG_27, 0x11},
+ {WSA881X_OTP_REG_63, 0x40},
+ /* WSA881x Analog registers */
+ {WSA881X_BIAS_REF_CTRL, 0x6C},
+ {WSA881X_BIAS_TEST, 0x16},
+ {WSA881X_BIAS_BIAS, 0xF0},
+ {WSA881X_TEMP_OP, 0x00},
+ {WSA881X_TEMP_IREF_CTRL, 0x56},
+ {WSA881X_TEMP_ISENS_CTRL, 0x47},
+ {WSA881X_TEMP_CLK_CTRL, 0x87},
+ {WSA881X_TEMP_TEST, 0x00},
+ {WSA881X_TEMP_BIAS, 0x51},
+ {WSA881X_TEMP_DOUT_MSB, 0x00},
+ {WSA881X_TEMP_DOUT_LSB, 0x00},
+ {WSA881X_ADC_EN_MODU_V, 0x00},
+ {WSA881X_ADC_EN_MODU_I, 0x00},
+ {WSA881X_ADC_EN_DET_TEST_V, 0x00},
+ {WSA881X_ADC_EN_DET_TEST_I, 0x00},
+ {WSA881X_ADC_EN_SEL_IBAIS, 0x10},
+ {WSA881X_SPKR_DRV_EN, 0x74},
+ {WSA881X_SPKR_DRV_DBG, 0x15},
+ {WSA881X_SPKR_PWRSTG_DBG, 0x00},
+ {WSA881X_SPKR_OCP_CTL, 0xD4},
+ {WSA881X_SPKR_CLIP_CTL, 0x90},
+ {WSA881X_SPKR_PA_INT, 0x54},
+ {WSA881X_SPKR_BIAS_CAL, 0xAC},
+ {WSA881X_SPKR_STATUS1, 0x00},
+ {WSA881X_SPKR_STATUS2, 0x00},
+ {WSA881X_BOOST_EN_CTL, 0x18},
+ {WSA881X_BOOST_CURRENT_LIMIT, 0x7A},
+ {WSA881X_BOOST_PRESET_OUT2, 0x70},
+ {WSA881X_BOOST_FORCE_OUT, 0x0E},
+ {WSA881X_BOOST_LDO_PROG, 0x16},
+ {WSA881X_BOOST_SLOPE_COMP_ISENSE_FB, 0x71},
+ {WSA881X_BOOST_RON_CTL, 0x0F},
+ {WSA881X_BOOST_ZX_CTL, 0x34},
+ {WSA881X_BOOST_START_CTL, 0x23},
+ {WSA881X_BOOST_MISC1_CTL, 0x80},
+ {WSA881X_BOOST_MISC2_CTL, 0x00},
+ {WSA881X_BOOST_MISC3_CTL, 0x00},
+ {WSA881X_BOOST_ATEST_CTL, 0x00},
+ {WSA881X_SPKR_PROT_FE_GAIN, 0x46},
+ {WSA881X_SPKR_PROT_FE_CM_LDO_SET, 0x3B},
+ {WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET1, 0x8D},
+ {WSA881X_SPKR_PROT_FE_ISENSE_BIAS_SET2, 0x8D},
+ {WSA881X_SPKR_PROT_ATEST1, 0x01},
+ {WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x8D},
+ {WSA881X_SPKR_PROT_FE_VSENSE_BIAS_SET1, 0x4D},
+ {WSA881X_SPKR_PROT_SAR, 0x00},
+ {WSA881X_SPKR_STATUS3, 0x00},
+};
+
+static const struct reg_sequence wsa881x_pre_pmu_pa[] = {
+ {WSA881X_SPKR_DRV_GAIN, 0x41, 0},
+ {WSA881X_SPKR_MISC_CTL1, 0x01, 0},
+ {WSA881X_ADC_EN_DET_TEST_I, 0x01, 0},
+ {WSA881X_ADC_EN_MODU_V, 0x02, 0},
+ {WSA881X_ADC_EN_DET_TEST_V, 0x10, 0},
+ {WSA881X_SPKR_PWRSTG_DBG, 0xA0, 0},
+};
+
+static const struct reg_sequence wsa881x_pre_pmu_pa_2_0[] = {
+ {WSA881X_SPKR_DRV_GAIN, 0x41, 0},
+ {WSA881X_SPKR_MISC_CTL1, 0x87, 0},
+};
+
+static const struct reg_sequence wsa881x_post_pmu_pa[] = {
+ {WSA881X_SPKR_PWRSTG_DBG, 0x00, 0},
+ {WSA881X_ADC_EN_DET_TEST_V, 0x00, 0},
+ {WSA881X_ADC_EN_MODU_V, 0x00, 0},
+ {WSA881X_ADC_EN_DET_TEST_I, 0x00, 0},
+};
+
+static const struct reg_sequence wsa881x_vi_txfe_en[] = {
+ {WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x85, 0},
+ {WSA881X_SPKR_PROT_ATEST2, 0x0A, 0},
+ {WSA881X_SPKR_PROT_FE_GAIN, 0xCF, 0},
+};
+
+static const struct reg_sequence wsa881x_vi_txfe_en_2_0[] = {
+ {WSA881X_SPKR_PROT_FE_VSENSE_VCM, 0x85, 0},
+ {WSA881X_SPKR_PROT_ATEST2, 0x0A, 0},
+ {WSA881X_SPKR_PROT_FE_GAIN, 0x47, 0},
+};
+
+/* Default register reset values for WSA881x rev 2.0 */
+static struct reg_sequence wsa881x_rev_2_0[] = {
+ {WSA881X_RESET_CTL, 0x00, 0x00},
+ {WSA881X_TADC_VALUE_CTL, 0x01, 0x00},
+ {WSA881X_INTR_MASK, 0x1B, 0x00},
+ {WSA881X_IOPAD_CTL, 0x00, 0x00},
+ {WSA881X_OTP_REG_28, 0x3F, 0x00},
+ {WSA881X_OTP_REG_29, 0x3F, 0x00},
+ {WSA881X_OTP_REG_30, 0x01, 0x00},
+ {WSA881X_OTP_REG_31, 0x01, 0x00},
+ {WSA881X_TEMP_ADC_CTRL, 0x03, 0x00},
+ {WSA881X_ADC_SEL_IBIAS, 0x45, 0x00},
+ {WSA881X_SPKR_DRV_GAIN, 0xC1, 0x00},
+ {WSA881X_SPKR_DAC_CTL, 0x42, 0x00},
+ {WSA881X_SPKR_BBM_CTL, 0x02, 0x00},
+ {WSA881X_SPKR_MISC_CTL1, 0x40, 0x00},
+ {WSA881X_SPKR_MISC_CTL2, 0x07, 0x00},
+ {WSA881X_SPKR_BIAS_INT, 0x5F, 0x00},
+ {WSA881X_SPKR_BIAS_PSRR, 0x44, 0x00},
+ {WSA881X_BOOST_PS_CTL, 0xA0, 0x00},
+ {WSA881X_BOOST_PRESET_OUT1, 0xB7, 0x00},
+ {WSA881X_BOOST_LOOP_STABILITY, 0x8D, 0x00},
+ {WSA881X_SPKR_PROT_ATEST2, 0x02, 0x00},
+ {WSA881X_BONGO_RESRV_REG1, 0x5E, 0x00},
+ {WSA881X_BONGO_RESRV_REG2, 0x07, 0x00},
+};
+
+enum wsa_port_ids {
+ WSA881X_PORT_DAC,
+ WSA881X_PORT_COMP,
+ WSA881X_PORT_BOOST,
+ WSA881X_PORT_VISENSE,
+};
+
+/* 4 ports */
+static struct sdw_dpn_prop wsa_sink_dpn_prop[WSA881X_MAX_SWR_PORTS] = {
+ {
+ /* DAC */
+ .num = 1,
+ .type = SDW_DPN_SIMPLE,
+ .min_ch = 1,
+ .max_ch = 8,
+ .simple_ch_prep_sm = true,
+ }, {
+ /* COMP */
+ .num = 2,
+ .type = SDW_DPN_SIMPLE,
+ .min_ch = 1,
+ .max_ch = 8,
+ .simple_ch_prep_sm = true,
+ }, {
+ /* BOOST */
+ .num = 3,
+ .type = SDW_DPN_SIMPLE,
+ .min_ch = 1,
+ .max_ch = 8,
+ .simple_ch_prep_sm = true,
+ }, {
+ /* VISENSE */
+ .num = 4,
+ .type = SDW_DPN_SIMPLE,
+ .min_ch = 1,
+ .max_ch = 8,
+ .simple_ch_prep_sm = true,
+ }
+};
+
+static bool wsa881x_readable_register(struct device *dev, unsigned int reg)
+{
+ return wsa881x_reg_readable[reg];
+}
+
+static bool wsa881x_volatile_register(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case WSA881X_CHIP_ID0:
+ case WSA881X_CHIP_ID1:
+ case WSA881X_CHIP_ID2:
+ case WSA881X_CHIP_ID3:
+ case WSA881X_BUS_ID:
+ case WSA881X_TEMP_MSB:
+ case WSA881X_TEMP_LSB:
+ case WSA881X_SDM_PDM9_LSB:
+ case WSA881X_SDM_PDM9_MSB:
+ case WSA881X_OTP_CTRL1:
+ case WSA881X_INTR_STATUS:
+ case WSA881X_ATE_TEST_MODE:
+ case WSA881X_PIN_STATUS:
+ case WSA881X_SWR_HM_TEST2:
+ case WSA881X_SPKR_STATUS1:
+ case WSA881X_SPKR_STATUS2:
+ case WSA881X_SPKR_STATUS3:
+ case WSA881X_OTP_REG_0:
+ case WSA881X_OTP_REG_1:
+ case WSA881X_OTP_REG_2:
+ case WSA881X_OTP_REG_3:
+ case WSA881X_OTP_REG_4:
+ case WSA881X_OTP_REG_5:
+ case WSA881X_OTP_REG_31:
+ case WSA881X_TEMP_DOUT_MSB:
+ case WSA881X_TEMP_DOUT_LSB:
+ case WSA881X_TEMP_OP:
+ case WSA881X_SPKR_PROT_SAR:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static struct regmap_config wsa881x_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 8,
+ .cache_type = REGCACHE_RBTREE,
+ .reg_defaults = wsa881x_defaults,
+ .num_reg_defaults = ARRAY_SIZE(wsa881x_defaults),
+ .max_register = WSA881X_MAX_REGISTER,
+ .volatile_reg = wsa881x_volatile_register,
+ .readable_reg = wsa881x_readable_register,
+ .reg_format_endian = REGMAP_ENDIAN_NATIVE,
+ .val_format_endian = REGMAP_ENDIAN_NATIVE,
+ .can_multi_write = true,
+};
+
+enum {
+ G_18DB = 0,
+ G_16P5DB,
+ G_15DB,
+ G_13P5DB,
+ G_12DB,
+ G_10P5DB,
+ G_9DB,
+ G_7P5DB,
+ G_6DB,
+ G_4P5DB,
+ G_3DB,
+ G_1P5DB,
+ G_0DB,
+};
+
+/*
+ * Private data Structure for wsa881x. All parameters related to
+ * WSA881X codec needs to be defined here.
+ */
+struct wsa881x_priv {
+ struct regmap *regmap;
+ struct device *dev;
+ struct sdw_slave *slave;
+ struct gpio_desc *sd_n;
+ int bg_cnt;
+ int clk_cnt;
+ int version;
+ /* bandgap lock */
+ struct mutex bg_lock;
+ /* clk resource lock */
+ struct mutex res_lock;
+ bool port_prepared[WSA881X_MAX_SWR_PORTS];
+ u8 pa_gain;
+};
+
+static void wsa881x_init(struct snd_soc_component *comp)
+{
+ struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
+
+ wsa881x->version = snd_soc_component_read32(comp, WSA881X_CHIP_ID1);
+ regcache_cache_only(wsa881x->regmap, true);
+ regmap_multi_reg_write(wsa881x->regmap, wsa881x_rev_2_0,
+ ARRAY_SIZE(wsa881x_rev_2_0));
+ regcache_cache_only(wsa881x->regmap, false);
+ /* Enable software reset output from soundwire slave */
+ snd_soc_component_update_bits(comp, WSA881X_SWR_RESET_EN, 0x07, 0x07);
+ /* Bring out of analog reset */
+ snd_soc_component_update_bits(comp, WSA881X_CDC_RST_CTL, 0x02, 0x02);
+ /* Bring out of digital reset */
+ snd_soc_component_update_bits(comp, WSA881X_CDC_RST_CTL, 0x01, 0x01);
+
+ snd_soc_component_update_bits(comp, WSA881X_CLOCK_CONFIG, 0x10, 0x10);
+ snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL, 0x02, 0x02);
+ snd_soc_component_update_bits(comp, WSA881X_SPKR_MISC_CTL1, 0xC0, 0x80);
+ snd_soc_component_update_bits(comp, WSA881X_SPKR_MISC_CTL1, 0x06, 0x06);
+ snd_soc_component_update_bits(comp, WSA881X_SPKR_BIAS_INT, 0xFF, 0x00);
+ snd_soc_component_update_bits(comp, WSA881X_SPKR_PA_INT, 0xF0, 0x40);
+ snd_soc_component_update_bits(comp, WSA881X_SPKR_PA_INT, 0x0E, 0x0E);
+ snd_soc_component_update_bits(comp, WSA881X_BOOST_LOOP_STABILITY,
+ 0x03, 0x03);
+ snd_soc_component_update_bits(comp, WSA881X_BOOST_MISC2_CTL,
+ 0xFF, 0x14);
+ snd_soc_component_update_bits(comp, WSA881X_BOOST_START_CTL,
+ 0x80, 0x80);
+ snd_soc_component_update_bits(comp, WSA881X_BOOST_START_CTL,
+ 0x03, 0x00);
+ snd_soc_component_update_bits(comp, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB,
+ 0x0C, 0x04);
+ snd_soc_component_update_bits(comp, WSA881X_BOOST_SLOPE_COMP_ISENSE_FB,
+ 0x03, 0x00);
+ if (snd_soc_component_read32(comp, WSA881X_OTP_REG_0))
+ snd_soc_component_update_bits(comp, WSA881X_BOOST_PRESET_OUT1,
+ 0xF0, 0x70);
+ snd_soc_component_update_bits(comp, WSA881X_BOOST_PRESET_OUT2,
+ 0xF0, 0x30);
+ snd_soc_component_update_bits(comp, WSA881X_SPKR_DRV_EN, 0x08, 0x08);
+ snd_soc_component_update_bits(comp, WSA881X_BOOST_CURRENT_LIMIT,
+ 0x0F, 0x08);
+ snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL, 0x30, 0x30);
+ snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL, 0x0C, 0x00);
+ snd_soc_component_update_bits(comp, WSA881X_OTP_REG_28, 0x3F, 0x3A);
+ snd_soc_component_update_bits(comp, WSA881X_BONGO_RESRV_REG1,
+ 0xFF, 0xB2);
+ snd_soc_component_update_bits(comp, WSA881X_BONGO_RESRV_REG2,
+ 0xFF, 0x05);
+}
+
+static int wsa881x_component_probe(struct snd_soc_component *comp)
+{
+ struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
+
+ if (!wsa881x)
+ return -EINVAL;
+
+ snd_soc_component_init_regmap(comp, wsa881x->regmap);
+
+ mutex_init(&wsa881x->bg_lock);
+ mutex_init(&wsa881x->res_lock);
+ wsa881x_init(comp);
+ wsa881x->bg_cnt = 0;
+ wsa881x->clk_cnt = 0;
+
+ return 0;
+}
+
+static int wsa881x_put_pa_gain(struct snd_kcontrol *kc,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *comp = snd_soc_kcontrol_component(kc);
+ struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
+ struct soc_mixer_control *mc =
+ (struct soc_mixer_control *)kc->private_value;
+ int max = mc->max;
+ unsigned int mask = (1 << fls(max)) - 1;
+
+ /*
+ * program actual register just before compander enable and ensure hw
+ * sequence is followed
+ */
+ wsa881x->pa_gain = (max - ucontrol->value.integer.value[0]) & mask;
+
+ return 0;
+}
+
+static const char * const smart_boost_lvl_text[] = {
+ "6.625 V", "6.750 V", "6.875 V", "7.000 V",
+ "7.125 V", "7.250 V", "7.375 V", "7.500 V",
+ "7.625 V", "7.750 V", "7.875 V", "8.000 V",
+ "8.125 V", "8.250 V", "8.375 V", "8.500 V"
+};
+
+static const struct soc_enum smart_boost_lvl_enum =
+ SOC_ENUM_SINGLE(WSA881X_BOOST_PRESET_OUT1, 0,
+ ARRAY_SIZE(smart_boost_lvl_text),
+ smart_boost_lvl_text);
+
+static const DECLARE_TLV_DB_SCALE(pa_gain, 0, 150, 0);
+
+static const struct snd_kcontrol_new wsa881x_snd_controls[] = {
+ SOC_ENUM("Smart Boost Level", smart_boost_lvl_enum),
+ WSA881X_PA_GAIN_TLV("PA Gain", WSA881X_SPKR_DRV_GAIN,
+ 4, 0xC, 1, pa_gain),
+ SOC_SINGLE("PA Mute Switch", WSA881X_SPKR_DRV_EN, 7, 1, 1),
+};
+
+static const struct snd_soc_dapm_route wsa881x_audio_map[] = {
+ {"RDAC", NULL, "IN"},
+ {"SPKR PGA", NULL, "RDAC"},
+ {"SPKR", NULL, "SPKR PGA"},
+};
+
+static void wsa881x_clk_ctrl(struct snd_soc_component *comp, bool enable)
+{
+ struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
+
+ mutex_lock(&wsa881x->res_lock);
+ if (enable) {
+ ++wsa881x->clk_cnt;
+ if (wsa881x->clk_cnt == 1) {
+ snd_soc_component_write(comp,
+ WSA881X_CDC_DIG_CLK_CTL,
+ enable);
+ snd_soc_component_write(comp,
+ WSA881X_CDC_ANA_CLK_CTL,
+ enable);
+ }
+ } else {
+ --wsa881x->clk_cnt;
+ if (wsa881x->clk_cnt <= 0) {
+ WARN_ON(wsa881x->clk_cnt < 0);
+ wsa881x->clk_cnt = 0;
+ snd_soc_component_write(comp,
+ WSA881X_CDC_DIG_CLK_CTL,
+ enable);
+ snd_soc_component_write(comp,
+ WSA881X_CDC_ANA_CLK_CTL,
+ enable);
+ }
+ }
+ mutex_unlock(&wsa881x->res_lock);
+}
+
+static void wsa881x_bandgap_ctrl(struct snd_soc_component *comp, bool enable)
+{
+ struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
+
+ mutex_lock(&wsa881x->bg_lock);
+ if (enable) {
+ ++wsa881x->bg_cnt;
+ if (wsa881x->bg_cnt == 1) {
+ snd_soc_component_update_bits(comp, WSA881X_TEMP_OP,
+ 0x08, 0x08);
+ /* 400usec sleep is needed as per HW requirement */
+ usleep_range(400, 410);
+ snd_soc_component_update_bits(comp, WSA881X_TEMP_OP,
+ 0x04, 0x04);
+ }
+ } else {
+ --wsa881x->bg_cnt;
+ if (wsa881x->bg_cnt <= 0) {
+ WARN_ON(wsa881x->bg_cnt < 0);
+ wsa881x->bg_cnt = 0;
+ snd_soc_component_update_bits(comp, WSA881X_TEMP_OP,
+ 0x04, 0x00);
+ snd_soc_component_update_bits(comp, WSA881X_TEMP_OP,
+ 0x08, 0x00);
+ }
+ }
+ mutex_unlock(&wsa881x->bg_lock);
+}
+
+static int wsa881x_boost_ctrl(struct snd_soc_component *comp, bool enable)
+{
+ if (enable)
+ snd_soc_component_update_bits(comp, WSA881X_BOOST_EN_CTL,
+ 0x80, 0x80);
+ else
+ snd_soc_component_update_bits(comp, WSA881X_BOOST_EN_CTL,
+ 0x80, 0x00);
+ /*
+ * 1.5ms sleep is needed after boost enable/disable as per
+ * HW requirement
+ */
+ usleep_range(1500, 1510);
+ return 0;
+}
+
+static int32_t wsa881x_resource_acquire(struct snd_soc_component *comp,
+ bool enable)
+{
+ wsa881x_clk_ctrl(comp, enable);
+ wsa881x_bandgap_ctrl(comp, enable);
+
+ return 0;
+}
+
+static int wsa881x_rdac_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ wsa881x_resource_acquire(comp, true);
+ wsa881x_boost_ctrl(comp, true);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ wsa881x_boost_ctrl(comp, false);
+ wsa881x_resource_acquire(comp, false);
+ break;
+ }
+ return 0;
+}
+
+static int wsa881x_ramp_pa_gain(struct snd_soc_component *comp,
+ int min_gain, int max_gain, int udelay)
+{
+ int val;
+
+ for (val = min_gain; max_gain <= val; val--) {
+ snd_soc_component_update_bits(comp, WSA881X_SPKR_DRV_GAIN,
+ 0xF0, val << 4);
+ /*
+ * 1ms delay is needed for every step change in gain as per
+ * HW requirement.
+ */
+ usleep_range(udelay, udelay + 10);
+ }
+ return 0;
+}
+
+static int wsa881x_visense_txfe_ctrl(struct snd_soc_component *comp,
+ bool enable, u8 isense1_gain,
+ u8 isense2_gain,
+ u8 vsense_gain)
+{
+ struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
+
+ if (enable) {
+ regmap_multi_reg_write(wsa881x->regmap,
+ wsa881x_vi_txfe_en_2_0,
+ ARRAY_SIZE(wsa881x_vi_txfe_en_2_0));
+ } else {
+ snd_soc_component_update_bits(comp,
+ WSA881X_SPKR_PROT_FE_VSENSE_VCM,
+ 0x08, 0x08);
+ /*
+ * 200us sleep is needed after visense txfe disable as per
+ * HW requirement.
+ */
+ usleep_range(200, 210);
+ snd_soc_component_update_bits(comp, WSA881X_SPKR_PROT_FE_GAIN,
+ 0x01, 0x00);
+ }
+ return 0;
+}
+
+static int wsa881x_visense_adc_ctrl(struct snd_soc_component *comp,
+ bool enable)
+{
+ snd_soc_component_update_bits(comp, WSA881X_ADC_EN_MODU_V, (0x01 << 7),
+ (enable << 7));
+ snd_soc_component_update_bits(comp, WSA881X_ADC_EN_MODU_I, (0x01 << 7),
+ (enable << 7));
+ return 0;
+}
+
+static int wsa881x_spkr_pa_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
+ struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
+ int min_gain, max_gain;
+
+ dev_err(comp->dev, "%s: %s %d\n", __func__, w->name, event);
+
+ switch (event) {
+ case SND_SOC_DAPM_PRE_PMU:
+ snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL,
+ 0xC0, 0x80);
+ regmap_multi_reg_write(wsa881x->regmap,
+ wsa881x_pre_pmu_pa_2_0,
+ ARRAY_SIZE(wsa881x_pre_pmu_pa_2_0));
+
+ /* Set register mode if compander is not enabled */
+ if (!wsa881x->port_prepared[WSA881X_PORT_COMP])
+ snd_soc_component_update_bits(comp,
+ WSA881X_SPKR_DRV_GAIN,
+ 0x08, 0x08);
+ else
+ snd_soc_component_update_bits(comp,
+ WSA881X_SPKR_DRV_GAIN,
+ 0x08, 0x00);
+ break;
+ case SND_SOC_DAPM_POST_PMU:
+ if (!wsa881x->port_prepared[WSA881X_PORT_COMP]) {
+ max_gain = wsa881x->pa_gain;
+ /*
+ * Gain has to set incrementally in 4 steps
+ * as per HW sequence
+ */
+ if (max_gain > G_4P5DB)
+ min_gain = G_0DB;
+ else
+ min_gain = max_gain + 3;
+ /*
+ * 1ms delay is needed before change in gain
+ * as per HW requirement.
+ */
+ usleep_range(1000, 1010);
+ wsa881x_ramp_pa_gain(comp, min_gain, max_gain, 1000);
+ }
+
+ if (wsa881x->port_prepared[WSA881X_PORT_VISENSE]) {
+ wsa881x_visense_txfe_ctrl(comp, true,
+ 0x00, 0x03, 0x01);
+ snd_soc_component_update_bits(comp,
+ WSA881X_ADC_EN_SEL_IBAIS,
+ 0x07, 0x01);
+ wsa881x_visense_adc_ctrl(comp, true);
+ }
+
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ if (wsa881x->port_prepared[WSA881X_PORT_VISENSE]) {
+ wsa881x_visense_adc_ctrl(comp, false);
+ wsa881x_visense_txfe_ctrl(comp, false,
+ 0x00, 0x01, 0x01);
+ }
+
+ snd_soc_component_update_bits(comp, WSA881X_SPKR_OCP_CTL,
+ 0xC0, 0xC0);
+ break;
+ }
+ return 0;
+}
+
+static const struct snd_soc_dapm_widget wsa881x_dapm_widgets[] = {
+ SND_SOC_DAPM_INPUT("IN"),
+ SND_SOC_DAPM_DAC_E("RDAC", NULL, WSA881X_SPKR_DAC_CTL, 7, 0,
+ wsa881x_rdac_event,
+ SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_PGA_E("SPKR PGA", WSA881X_SPKR_DRV_EN, 7, 0, NULL, 0,
+ wsa881x_spkr_pa_event, SND_SOC_DAPM_PRE_PMU |
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_OUTPUT("SPKR"),
+};
+
+static void wsa881x_component_remove(struct snd_soc_component *comp)
+{
+ struct wsa881x_priv *wsa881x = snd_soc_component_get_drvdata(comp);
+
+ mutex_destroy(&wsa881x->bg_lock);
+ mutex_destroy(&wsa881x->res_lock);
+}
+
+static const struct snd_soc_component_driver wsa881x_component_drv = {
+ .probe = wsa881x_component_probe,
+ .controls = wsa881x_snd_controls,
+ .num_controls = ARRAY_SIZE(wsa881x_snd_controls),
+ .remove = wsa881x_component_remove,
+ .dapm_widgets = wsa881x_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(wsa881x_dapm_widgets),
+ .dapm_routes = wsa881x_audio_map,
+ .num_dapm_routes = ARRAY_SIZE(wsa881x_audio_map),
+};
+
+static int wsa881x_update_status(struct sdw_slave *slave,
+ enum sdw_slave_status status)
+{
+ struct wsa881x_priv *wsa881x = dev_get_drvdata(&slave->dev);
+
+ if (status == SDW_SLAVE_ATTACHED) {
+ if (!wsa881x->regmap) {
+ wsa881x->regmap = devm_regmap_init_sdw(slave,
+ &wsa881x_regmap_config);
+ if (IS_ERR(wsa881x->regmap)) {
+ dev_err(&slave->dev, "regmap_init failed\n");
+ return PTR_ERR(wsa881x->regmap);
+ }
+ }
+
+ return snd_soc_register_component(&slave->dev,
+ &wsa881x_component_drv,
+ NULL, 0);
+ } else if (status == SDW_SLAVE_UNATTACHED) {
+ snd_soc_unregister_component(&slave->dev);
+ }
+
+ return 0;
+}
+
+static int wsa881x_port_prep(struct sdw_slave *slave,
+ struct sdw_prepare_ch *prepare_ch,
+ enum sdw_port_prep_ops state)
+{
+ struct wsa881x_priv *wsa881x = dev_get_drvdata(&slave->dev);
+
+ if (state == SDW_OPS_PORT_POST_PREP)
+ wsa881x->port_prepared[prepare_ch->num - 1] = true;
+ else
+ wsa881x->port_prepared[prepare_ch->num - 1] = false;
+
+ return 0;
+}
+
+static int wsa881x_bus_config(struct sdw_slave *slave,
+ struct sdw_bus_params *params)
+{
+ sdw_write(slave, SWRS_SCP_HOST_CLK_DIV2_CTL_BANK(params->next_bank),
+ 0x01);
+
+ return 0;
+}
+
+static struct sdw_slave_ops wsa881x_slave_ops = {
+ .update_status = wsa881x_update_status,
+ .bus_config = wsa881x_bus_config,
+ .port_prep = wsa881x_port_prep,
+};
+
+static int wsa881x_probe(struct sdw_slave *pdev,
+ const struct sdw_device_id *id)
+{
+ struct wsa881x_priv *wsa881x;
+
+ wsa881x = devm_kzalloc(&pdev->dev, sizeof(*wsa881x), GFP_KERNEL);
+ if (!wsa881x)
+ return -ENOMEM;
+
+ wsa881x->sd_n = devm_gpiod_get_optional(&pdev->dev, "pd",
+ GPIOD_FLAGS_BIT_NONEXCLUSIVE);
+ if (IS_ERR(wsa881x->sd_n)) {
+ dev_err(&pdev->dev, "Shutdown Control GPIO not found\n");
+ return PTR_ERR(wsa881x->sd_n);
+ }
+
+ dev_set_drvdata(&pdev->dev, wsa881x);
+ wsa881x->slave = pdev;
+ wsa881x->dev = &pdev->dev;
+ pdev->prop.sink_ports = GENMASK(WSA881X_MAX_SWR_PORTS, 0);
+ pdev->prop.sink_dpn_prop = wsa_sink_dpn_prop;
+ gpiod_set_value(wsa881x->sd_n, 1);
+
+ return 0;
+}
+
+static int wsa881x_remove(struct sdw_slave *sdw)
+{
+ return 0;
+}
+
+static const struct sdw_device_id wsa881x_slave_id[] = {
+ SDW_SLAVE_ENTRY(0x0217, 0x2010, 0),
+ {},
+};
+MODULE_DEVICE_TABLE(sdw, wsa881x_slave_id);
+
+static struct sdw_driver wsa881x_codec_driver = {
+ .probe = wsa881x_probe,
+ .remove = wsa881x_remove,
+ .ops = &wsa881x_slave_ops,
+ .id_table = wsa881x_slave_id,
+ .driver = {
+ .name = "wsa881x-codec",
+ }
+};
+module_sdw_driver(wsa881x_codec_driver);
+
+MODULE_DESCRIPTION("WSA881x codec driver");
+MODULE_LICENSE("GPL v2");
--
2.21.0
^ permalink raw reply related
* [PATCH v2 3/4] dt-bindings: ASoC: Add WSA881x bindings
From: Srinivas Kandagatla @ 2019-08-08 14:45 UTC (permalink / raw)
To: vkoul, broonie
Cc: bgoswami, plai, pierre-louis.bossart, robh+dt, devicetree,
lgirdwood, alsa-devel, linux-kernel, Srinivas Kandagatla
In-Reply-To: <20190808144504.24823-1-srinivas.kandagatla@linaro.org>
This patch adds bindings for WSA8810/WSA8815 Class-D Smart Speaker
Amplifier. This Amplifier also has a simple thermal sensor for
over temperature and speaker protection.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
.../bindings/sound/qcom,wsa881x.txt | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/qcom,wsa881x.txt
diff --git a/Documentation/devicetree/bindings/sound/qcom,wsa881x.txt b/Documentation/devicetree/bindings/sound/qcom,wsa881x.txt
new file mode 100644
index 000000000000..582db402a482
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/qcom,wsa881x.txt
@@ -0,0 +1,27 @@
+Bindings for Qualcomm WSA8810/WSA8815 Class-D Smart Speaker Amplifier
+
+WSA8810 is a class-D smart speaker amplifier and WSA8815 is a high-output
+power class-D smart speaker amplifier. This amplifier uses SoundWire
+digital audio as primary interface.
+
+Required properties with SoundWire Interface:
+
+- compatible: Should be textual representation of SoundWire Enumeration
+ address.
+ Refer to soundwire/bus.txt for details.
+ Should be "sdw10,0217,2010,0" for WSA8810
+- sdw-instance-id: Should be ('Instance ID') from SoundWire Enumeration
+ address.
+ Refer to soundwire/bus.txt for details.
+- pd-gpios: Should be phandle and gpio pair for
+ Powerdown/Shutdown pin.
+- #thermal-sensor-cells: Should be 0
+
+Example:
+
+spkr_left:wsa8810-left{
+ compatible = "sdw10,0217,2010,0";
+ sdw-instance-id = <1>;
+ #thermal-sensor-cells = <0>;
+ ...
+};
--
2.21.0
^ permalink raw reply related
* [PATCH v2 2/4] soundwire: core: add device tree support for slave devices
From: Srinivas Kandagatla @ 2019-08-08 14:45 UTC (permalink / raw)
To: vkoul, broonie
Cc: bgoswami, plai, pierre-louis.bossart, robh+dt, devicetree,
lgirdwood, alsa-devel, linux-kernel, Srinivas Kandagatla
In-Reply-To: <20190808144504.24823-1-srinivas.kandagatla@linaro.org>
This patch adds support to parsing device tree based
SoundWire slave devices.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
drivers/soundwire/bus.c | 2 ++
drivers/soundwire/bus.h | 1 +
drivers/soundwire/slave.c | 47 +++++++++++++++++++++++++++++++++++++++
3 files changed, 50 insertions(+)
diff --git a/drivers/soundwire/bus.c b/drivers/soundwire/bus.c
index fe745830a261..324c54dc52fb 100644
--- a/drivers/soundwire/bus.c
+++ b/drivers/soundwire/bus.c
@@ -77,6 +77,8 @@ int sdw_add_bus_master(struct sdw_bus *bus)
*/
if (IS_ENABLED(CONFIG_ACPI) && ACPI_HANDLE(bus->dev))
ret = sdw_acpi_find_slaves(bus);
+ else if (IS_ENABLED(CONFIG_OF) && bus->dev->of_node)
+ ret = sdw_of_find_slaves(bus);
else
ret = -ENOTSUPP; /* No ACPI/DT so error out */
diff --git a/drivers/soundwire/bus.h b/drivers/soundwire/bus.h
index 3048ca153f22..ee46befedbd1 100644
--- a/drivers/soundwire/bus.h
+++ b/drivers/soundwire/bus.h
@@ -15,6 +15,7 @@ static inline int sdw_acpi_find_slaves(struct sdw_bus *bus)
}
#endif
+int sdw_of_find_slaves(struct sdw_bus *bus);
void sdw_extract_slave_id(struct sdw_bus *bus,
u64 addr, struct sdw_slave_id *id);
diff --git a/drivers/soundwire/slave.c b/drivers/soundwire/slave.c
index f39a5815e25d..8ab76f5d5a56 100644
--- a/drivers/soundwire/slave.c
+++ b/drivers/soundwire/slave.c
@@ -2,6 +2,7 @@
// Copyright(c) 2015-17 Intel Corporation.
#include <linux/acpi.h>
+#include <linux/of.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_type.h>
#include "bus.h"
@@ -35,6 +36,7 @@ static int sdw_slave_add(struct sdw_bus *bus,
slave->dev.release = sdw_slave_release;
slave->dev.bus = &sdw_bus_type;
+ slave->dev.of_node = of_node_get(to_of_node(fwnode));
slave->bus = bus;
slave->status = SDW_SLAVE_UNATTACHED;
slave->dev_num = 0;
@@ -112,3 +114,48 @@ int sdw_acpi_find_slaves(struct sdw_bus *bus)
}
#endif
+
+/*
+ * sdw_of_find_slaves() - Find Slave devices in master device tree node
+ * @bus: SDW bus instance
+ *
+ * Scans Master DT node for SDW child Slave devices and registers it.
+ */
+int sdw_of_find_slaves(struct sdw_bus *bus)
+{
+ struct device *dev = bus->dev;
+ struct device_node *node;
+
+ for_each_child_of_node(bus->dev->of_node, node) {
+ struct sdw_slave_id id;
+ const char *compat = NULL;
+ int unique_id, ret;
+ int ver, mfg_id, part_id, class_id;
+
+ compat = of_get_property(node, "compatible", NULL);
+ if (!compat)
+ continue;
+
+ ret = sscanf(compat, "sdw%x,%x,%x,%x",
+ &ver, &mfg_id, &part_id, &class_id);
+ if (ret != 4) {
+ dev_err(dev, "Manf ID & Product code not found %s\n",
+ compat);
+ continue;
+ }
+
+ ret = of_property_read_u32(node, "sdw-instance-id", &unique_id);
+ if (ret) {
+ dev_err(dev, "Instance id not found:%d\n", ret);
+ continue;
+ }
+
+ id.sdw_version = ver - 0xF;
+ id.unique_id = unique_id;
+ id.mfg_id = mfg_id;
+ id.part_id = part_id;
+ id.class_id = class_id;
+ sdw_slave_add(bus, &id, of_fwnode_handle(node));
+ }
+ return 0;
+}
--
2.21.0
^ permalink raw reply related
* [PATCH v2 1/4] dt-bindings: soundwire: add slave bindings
From: Srinivas Kandagatla @ 2019-08-08 14:45 UTC (permalink / raw)
To: vkoul, broonie
Cc: bgoswami, plai, pierre-louis.bossart, robh+dt, devicetree,
lgirdwood, alsa-devel, linux-kernel, Srinivas Kandagatla
In-Reply-To: <20190808144504.24823-1-srinivas.kandagatla@linaro.org>
This patch adds bindings for Soundwire Slave devices which includes how
SoundWire enumeration address is represented in SoundWire slave device
tree nodes.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
.../devicetree/bindings/soundwire/slave.txt | 46 +++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/soundwire/slave.txt
diff --git a/Documentation/devicetree/bindings/soundwire/slave.txt b/Documentation/devicetree/bindings/soundwire/slave.txt
new file mode 100644
index 000000000000..b8e8d34bbc92
--- /dev/null
+++ b/Documentation/devicetree/bindings/soundwire/slave.txt
@@ -0,0 +1,46 @@
+SoundWire slave device bindings.
+
+SoundWire is a 2-pin multi-drop interface with data and clock line.
+It facilitates development of low cost, efficient, high performance systems.
+
+SoundWire slave devices:
+Every SoundWire controller node can contain zero or more child nodes
+representing slave devices on the bus. Every SoundWire slave device is
+uniquely determined by the enumeration address containing 5 fields:
+SoundWire Version, Instance ID, Manufacturer ID, Part ID and Class ID
+for a device. Addition to below required properties, child nodes can
+have device specific bindings.
+
+Required property for SoundWire child node if it is present:
+- compatible: "sdwVER,MFD,PID,CID". The textual representation of
+ SoundWire Enumeration address comprising SoundWire
+ Version, Manufacturer ID, Part ID and Class ID,
+ shall be in lower-case hexadecimal with leading
+ zeroes suppressed.
+ Version number '0x10' represents SoundWire 1.0
+ Version number '0x11' represents SoundWire 1.1
+ ex: "sdw10,0217,2010,0"
+
+- sdw-instance-id: Should be ('Instance ID') from SoundWire
+ Enumeration Address. Instance ID is for the cases
+ where multiple Devices of the same type or Class
+ are attached to the bus.
+
+SoundWire example for Qualcomm's SoundWire controller:
+
+soundwire@c2d0000 {
+ compatible = "qcom,soundwire-v1.5.0"
+ reg = <0x0c2d0000 0x2000>;
+
+ spkr_left:wsa8810-left{
+ compatible = "sdw10,0217,2010,0";
+ sdw-instance-id = <1>;
+ ...
+ };
+
+ spkr_right:wsa8810-right{
+ compatible = "sdw10,0217,2010,0";
+ sdw-instance-id = <2>;
+ ...
+ };
+};
--
2.21.0
^ permalink raw reply related
* [PATCH v2 0/4] ASoC: codecs: Add WSA881x Smart Speaker amplifier support
From: Srinivas Kandagatla @ 2019-08-08 14:45 UTC (permalink / raw)
To: vkoul, broonie
Cc: bgoswami, plai, pierre-louis.bossart, robh+dt, devicetree,
lgirdwood, alsa-devel, linux-kernel, Srinivas Kandagatla
This patchset adds support to WSA8810/WSA8815 Class-D Smart Speaker
Amplifier which is SoundWire interfaced.
This also adds support to some missing bits in SoundWire bus layer like
Device Tree support and module_sdw_driver macro.
This patchset along with DB845c machine driver and WCD934x codec driver
has been tested on SDM845 SoC based DragonBoard DB845c with two
WSA8810 speakers.
Most of the code in this driver is rework of Qualcomm downstream drivers
used in Andriod. Credits to Banajit Goswami and Patrick Lai's Team.
TODO:
Add thermal sensor support in WSA881x.
This patchset also depends on the soundwire Kconfig patch
https://lkml.org/lkml/2019/7/18/834 from Pierre
Thanks,
srini
Changes since v1 RFC:
- bindings document renamed to slave.txt
- fix error code from dt slave parsing
Srinivas Kandagatla (4):
dt-bindings: soundwire: add slave bindings
soundwire: core: add device tree support for slave devices
dt-bindings: ASoC: Add WSA881x bindings
ASoC: codecs: add wsa881x amplifier support
.../bindings/sound/qcom,wsa881x.txt | 27 +
.../devicetree/bindings/soundwire/slave.txt | 46 +
drivers/soundwire/bus.c | 2 +
drivers/soundwire/bus.h | 1 +
drivers/soundwire/slave.c | 47 +
sound/soc/codecs/Kconfig | 10 +
sound/soc/codecs/Makefile | 2 +
sound/soc/codecs/wsa881x.c | 1160 +++++++++++++++++
8 files changed, 1295 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/qcom,wsa881x.txt
create mode 100644 Documentation/devicetree/bindings/soundwire/slave.txt
create mode 100644 sound/soc/codecs/wsa881x.c
--
2.21.0
^ permalink raw reply
* [PATCH 2/2] arm64: dts: ti: k3-j721e-main: Fix gic-its node unit-address
From: Suman Anna @ 2019-08-08 14:39 UTC (permalink / raw)
To: Tero Kristo, Nishanth Menon; +Cc: devicetree, Robert Tivy, linux-arm-kernel
In-Reply-To: <20190808143929.11148-1-s-anna@ti.com>
The gic-its node unit-address has an additional zero compared
to the actual reg value. Fix it.
Fixes: 2d87061e70de ("arm64: dts: ti: Add Support for J721E SoC")
Reported-by: Robert Tivy <rtivy@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index a01308142f77..ea5c0fd42baf 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -31,7 +31,7 @@
/* vcpumntirq: virtual CPU interface maintenance interrupt */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- gic_its: gic-its@18200000 {
+ gic_its: gic-its@1820000 {
compatible = "arm,gic-v3-its";
reg = <0x00 0x01820000 0x00 0x10000>;
socionext,synquacer-pre-its = <0x1000000 0x400000>;
--
2.22.0
^ permalink raw reply related
* [PATCH 1/2] arm64: dts: ti: k3-am65-main: Fix gic-its node unit-address
From: Suman Anna @ 2019-08-08 14:39 UTC (permalink / raw)
To: Tero Kristo, Nishanth Menon; +Cc: devicetree, Robert Tivy, linux-arm-kernel
In-Reply-To: <20190808143929.11148-1-s-anna@ti.com>
The gic-its node unit-address has an additional zero compared
to the actual reg value. Fix it.
Fixes: ea47eed33a3f ("arm64: dts: ti: Add Support for AM654 SoC")
Reported-by: Robert Tivy <rtivy@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index ca70ff73f171..38c75fb3f232 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -42,7 +42,7 @@
*/
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
- gic_its: gic-its@18200000 {
+ gic_its: gic-its@1820000 {
compatible = "arm,gic-v3-its";
reg = <0x00 0x01820000 0x00 0x10000>;
socionext,synquacer-pre-its = <0x1000000 0x400000>;
--
2.22.0
^ permalink raw reply related
* [PATCH 0/2] K3 dts minor typo fixes
From: Suman Anna @ 2019-08-08 14:39 UTC (permalink / raw)
To: Tero Kristo, Nishanth Menon; +Cc: devicetree, linux-arm-kernel
Hi Tero, Nishanth,
The following 2 patches are minor typo fixes in git-its nodes
on both AM65x and J721E SoCs. Patches done on top of the latest
master.
regards
Suman
Suman Anna (2):
arm64: dts: ti: k3-am65-main: Fix gic-its node unit-address
arm64: dts: ti: k3-j721e-main: Fix gic-its node unit-address
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 +-
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
--
2.22.0
^ permalink raw reply
* Re: [PATCH v2] arm64: dts: rockchip: Add dts for Leez RK3399 P710 SBC
From: Rob Herring @ 2019-08-08 14:24 UTC (permalink / raw)
To: Andy Yan
Cc: heiko@sntech.de, devicetree,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list:ARM/Rockchip SoC..., linux-kernel@vger.kernel.org
In-Reply-To: <CANbgqATvVSo_D-n_mW2hK2KEK_8cs3374ddB6C8GcZZwjMSoRQ@mail.gmail.com>
On Wed, Aug 7, 2019 at 12:14 AM Andy Yan <andyshrk@gmail.com> wrote:
>
> Hi Rob:
>
> Rob Herring <robh+dt@kernel.org> 于2019年8月6日周二 下午10:48写道：
>>
>> On Mon, Aug 5, 2019 at 6:40 AM Andy Yan <andyshrk@gmail.com> wrote:
>> >
>> > P710 is a RK3399 based SBC, designed by Leez [0].
>> >
>> > Specification
>> > - Rockchip RK3399
>> > - 4/2GB LPDDR4
>> > - TF sd scard slot
>> > - eMMC
>> > - M.2 B-Key for 4G LTE
>> > - AP6256 for WiFi + BT
>> > - Gigabit ethernet
>> > - HDMI out
>> > - 40 pin header
>> > - USB 2.0 x 2
>> > - USB 3.0 x 1
>> > - USB 3.0 Type-C x 1
>> > - TYPE-C Power supply
>> >
>> > [0]https://leez.lenovo.com
>>
>> I'm not really convinced Leez is a vendor. Looks like branding to me.
>> We have enough with company names changing, we don't need changing
>> brands too. Use 'lenovo'.
>>
>
> I had checked with Leez people before V1, they said Leez will run as an independent company, so they don't want to
> give a lenovo label for this board.
Okay.
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v3 2/3] dt-bindings: display: amlogic,meson-vpu: convert to yaml
From: Rob Herring @ 2019-08-08 14:22 UTC (permalink / raw)
To: Neil Armstrong
Cc: devicetree, dri-devel, linux-amlogic,
linux-kernel@vger.kernel.org
In-Reply-To: <20190808085522.21950-3-narmstrong@baylibre.com>
On Thu, Aug 8, 2019 at 2:55 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> Now that we have the DT validation in place, let's convert the device tree
> bindings for the Amlogic Display Controller over to YAML schemas.
>
> The original example has a leftover "dmc" memory cell, that has been
> removed in the yaml rewrite.
>
> The port connection table has been dropped in favor of a description
> of each port.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> .../bindings/display/amlogic,meson-vpu.txt | 121 ----------------
> .../bindings/display/amlogic,meson-vpu.yaml | 137 ++++++++++++++++++
> 2 files changed, 137 insertions(+), 121 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-vpu.txt
> create mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH] of/platform: fix compilation warning of of_link_property()
From: Anders Roxell @ 2019-08-08 14:18 UTC (permalink / raw)
To: robh+dt, frowand.list; +Cc: devicetree, linux-kernel, Anders Roxell
GCC warns that a negative integer can be returned but the
of_link_property() function should return a boolean.
../drivers/of/platform.c: In function ‘of_link_property’:
../drivers/of/platform.c:650:18: warning: ?: using integer constants in boolean context [-Wint-in-bool-context]
return done ? 0 : -ENODEV;
Rework so function of_link_property() return an integer instead of a boolean.
Fixes: 690ff7881b26 ("of/platform: Add functional dependency link from DT bindings")
Signed-off-by: Anders Roxell <anders.roxell@linaro.org>
---
drivers/of/platform.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/of/platform.c b/drivers/of/platform.c
index 21838226d68a..86fb8ab8c012 100644
--- a/drivers/of/platform.c
+++ b/drivers/of/platform.c
@@ -625,7 +625,7 @@ static const struct supplier_bindings bindings[] = {
{ },
};
-static bool of_link_property(struct device *dev, struct device_node *con_np,
+static int of_link_property(struct device *dev, struct device_node *con_np,
const char *prop)
{
struct device_node *phandle;
--
2.20.1
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox