* Re: [PATCH v2] of/fdt: implement a "merge-cmdline" property
From: Frank Rowand @ 2019-08-10 2:26 UTC (permalink / raw)
To: Daniel Gimpelevich, devicetree; +Cc: Paul Burton, Frank Rowand
In-Reply-To: <1565020400-25679-1-git-send-email-daniel@gimpelevich.san-francisco.ca.us>
+Frank (me)
On 8/5/19 8:53 AM, Daniel Gimpelevich wrote:
> Currently, "bootargs" supplied via the "chosen" node can be used only to
> supply a kernel command line as a whole. No mechanism exists in DT to add
> bootargs to the existing command line instead. This is needed in order to
> avoid having to update the bootloader or default bootloader config when
> upgrading to a DTB and kernel pair that requires bootargs not previously
> needed.
>
> One example use case is that OpenWrt currently supports four ARM devices by
> means of locally applying the previously rejected edition of this patch. So
> far, the patch has been used in production only on ARM, but architecture is
> not a distinction in the design.
>
> On MIPS, Commit 951d223 ("MIPS: Fix CONFIG_CMDLINE handling") currently
> prevents support of such a mechanism, so I am including a workaround, in
> anticipation of upcoming changes.
>
> Signed-off-by: Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
> Fixes: 951d223 ("MIPS: Fix CONFIG_CMDLINE handling")
> References: https://patchwork.linux-mips.org/patch/17659/
> ---
> arch/mips/kernel/setup.c | 12 ++++++++----
> drivers/of/fdt.c | 9 +++++++--
> 2 files changed, 15 insertions(+), 6 deletions(-)
>
> diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
> index ab349d2..9ce58f2 100644
> --- a/arch/mips/kernel/setup.c
> +++ b/arch/mips/kernel/setup.c
> @@ -725,7 +725,10 @@ static void __init arch_mem_init(char **cmdline_p)
> * CONFIG_CMDLINE ourselves below & don't want to duplicate its
> * content because repeating arguments can be problematic.
> */
> - strlcpy(boot_command_line, " ", COMMAND_LINE_SIZE);
> + if (USE_DTB_CMDLINE)
> + strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
> + else
> + strlcpy(boot_command_line, " ", COMMAND_LINE_SIZE);
>
> /* call board setup routine */
> plat_mem_setup();
> @@ -753,9 +756,10 @@ static void __init arch_mem_init(char **cmdline_p)
> #if defined(CONFIG_CMDLINE_BOOL) && defined(CONFIG_CMDLINE_OVERRIDE)
> strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
> #else
> - if ((USE_PROM_CMDLINE && arcs_cmdline[0]) ||
> - (USE_DTB_CMDLINE && !boot_command_line[0]))
> + if (USE_PROM_CMDLINE)
> strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
> + else if (!strcmp(boot_command_line, " "))
> + boot_command_line[0] = '\0';
>
> if (EXTEND_WITH_PROM && arcs_cmdline[0]) {
> if (boot_command_line[0])
> @@ -764,7 +768,7 @@ static void __init arch_mem_init(char **cmdline_p)
> }
>
> #if defined(CONFIG_CMDLINE_BOOL)
> - if (builtin_cmdline[0]) {
> + if (builtin_cmdline[0] && strcmp(boot_command_line, builtin_cmdline)) {
> if (boot_command_line[0])
> strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
> strlcat(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
> diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
> index 9cdf14b..08c25eb 100644
> --- a/drivers/of/fdt.c
> +++ b/drivers/of/fdt.c
> @@ -1055,8 +1055,13 @@ int __init early_init_dt_scan_chosen(unsigned long node, const char *uname,
>
> /* Retrieve command line */
> p = of_get_flat_dt_prop(node, "bootargs", &l);
> - if (p != NULL && l > 0)
> - strlcpy(data, p, min(l, COMMAND_LINE_SIZE));
> + if (p != NULL && l > 0) {
> + if (!of_get_flat_dt_prop(node, "merge-cmdline", NULL))
> + *(char *)data = '\0';
> + if (*(char *)data)
> + strlcat(data, " ", COMMAND_LINE_SIZE);
> + strlcat(data, p, min(l + strlen(data), COMMAND_LINE_SIZE));
> + }
>
> /*
> * CONFIG_CMDLINE is meant to be a default in case nothing else
>
^ permalink raw reply
* Re: [PATCH v2] of/fdt: implement a "merge-cmdline" property
From: Frank Rowand @ 2019-08-10 2:12 UTC (permalink / raw)
To: Daniel Gimpelevich, devicetree; +Cc: Paul Burton
In-Reply-To: <1565020400-25679-1-git-send-email-daniel@gimpelevich.san-francisco.ca.us>
Hi Daniel,
Please include me on the distribution list for devicetree patches.
-Frank
On 8/5/19 8:53 AM, Daniel Gimpelevich wrote:
> Currently, "bootargs" supplied via the "chosen" node can be used only to
> supply a kernel command line as a whole. No mechanism exists in DT to add
> bootargs to the existing command line instead. This is needed in order to
> avoid having to update the bootloader or default bootloader config when
> upgrading to a DTB and kernel pair that requires bootargs not previously
> needed.
>
> One example use case is that OpenWrt currently supports four ARM devices by
> means of locally applying the previously rejected edition of this patch. So
> far, the patch has been used in production only on ARM, but architecture is
> not a distinction in the design.
>
> On MIPS, Commit 951d223 ("MIPS: Fix CONFIG_CMDLINE handling") currently
> prevents support of such a mechanism, so I am including a workaround, in
> anticipation of upcoming changes.
>
> Signed-off-by: Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
> Fixes: 951d223 ("MIPS: Fix CONFIG_CMDLINE handling")
> References: https://patchwork.linux-mips.org/patch/17659/
> ---
> arch/mips/kernel/setup.c | 12 ++++++++----
> drivers/of/fdt.c | 9 +++++++--
> 2 files changed, 15 insertions(+), 6 deletions(-)
>
> diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
> index ab349d2..9ce58f2 100644
> --- a/arch/mips/kernel/setup.c
> +++ b/arch/mips/kernel/setup.c
> @@ -725,7 +725,10 @@ static void __init arch_mem_init(char **cmdline_p)
> * CONFIG_CMDLINE ourselves below & don't want to duplicate its
> * content because repeating arguments can be problematic.
> */
> - strlcpy(boot_command_line, " ", COMMAND_LINE_SIZE);
> + if (USE_DTB_CMDLINE)
> + strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
> + else
> + strlcpy(boot_command_line, " ", COMMAND_LINE_SIZE);
>
> /* call board setup routine */
> plat_mem_setup();
> @@ -753,9 +756,10 @@ static void __init arch_mem_init(char **cmdline_p)
> #if defined(CONFIG_CMDLINE_BOOL) && defined(CONFIG_CMDLINE_OVERRIDE)
> strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
> #else
> - if ((USE_PROM_CMDLINE && arcs_cmdline[0]) ||
> - (USE_DTB_CMDLINE && !boot_command_line[0]))
> + if (USE_PROM_CMDLINE)
> strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
> + else if (!strcmp(boot_command_line, " "))
> + boot_command_line[0] = '\0';
>
> if (EXTEND_WITH_PROM && arcs_cmdline[0]) {
> if (boot_command_line[0])
> @@ -764,7 +768,7 @@ static void __init arch_mem_init(char **cmdline_p)
> }
>
> #if defined(CONFIG_CMDLINE_BOOL)
> - if (builtin_cmdline[0]) {
> + if (builtin_cmdline[0] && strcmp(boot_command_line, builtin_cmdline)) {
> if (boot_command_line[0])
> strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
> strlcat(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
> diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
> index 9cdf14b..08c25eb 100644
> --- a/drivers/of/fdt.c
> +++ b/drivers/of/fdt.c
> @@ -1055,8 +1055,13 @@ int __init early_init_dt_scan_chosen(unsigned long node, const char *uname,
>
> /* Retrieve command line */
> p = of_get_flat_dt_prop(node, "bootargs", &l);
> - if (p != NULL && l > 0)
> - strlcpy(data, p, min(l, COMMAND_LINE_SIZE));
> + if (p != NULL && l > 0) {
> + if (!of_get_flat_dt_prop(node, "merge-cmdline", NULL))
> + *(char *)data = '\0';
> + if (*(char *)data)
> + strlcat(data, " ", COMMAND_LINE_SIZE);
> + strlcat(data, p, min(l + strlen(data), COMMAND_LINE_SIZE));
> + }
>
> /*
> * CONFIG_CMDLINE is meant to be a default in case nothing else
>
^ permalink raw reply
* Re: [PATCH v3 0/6] Add support of New Amlogic temperature sensor for G12 SoCs
From: Kevin Hilman @ 2019-08-10 0:11 UTC (permalink / raw)
To: Guillaume La Roque, daniel.lezcano
Cc: linux-pm, devicetree, linux-amlogic, linux-kernel,
linux-arm-kernel
In-Reply-To: <20190806130506.8753-1-glaroque@baylibre.com>
Guillaume La Roque <glaroque@baylibre.com> writes:
> This patchs series add support of New Amlogic temperature sensor and minimal
> thermal zone for SEI510 and ODROID-N2 boards.
>
> First implementation was doing on IIO[1] but after comments i move on thermal framework.
> Formulas and calibration values come from amlogic.
>
> Changes since v2:
> - fix yaml documention
> - remove unneeded status variable for temperature-sensor node
> - rework driver after Martin review
> - add some information in commit message
>
> Changes since v1:
> - fix enum vs const in documentation
> - fix error with thermal-sensor-cells value set to 1 instead of 0
> - add some dependencies needed to add cooling-maps
>
> Dependencies :
> - patch 3,4 & 5: depends on Neil's patch and series :
> - missing dwc2 phy-names[2]
> - patchsets to add DVFS on G12a[3] which have deps on [4] and [5]
>
> [1] https://lore.kernel.org/linux-amlogic/20190604144714.2009-1-glaroque@baylibre.com/
> [2] https://lore.kernel.org/linux-amlogic/20190625123647.26117-1-narmstrong@baylibre.com/
> [3] https://lore.kernel.org/linux-amlogic/20190729132622.7566-1-narmstrong@baylibre.com/
> [4] https://lore.kernel.org/linux-amlogic/20190731084019.8451-5-narmstrong@baylibre.com/
> [5] https://lore.kernel.org/linux-amlogic/20190729132622.7566-3-narmstrong@baylibre.com/
Thank you for the detailed list of dependencies! Much appreciated.
With all the deps, I tested this on sei510 and odroid-n2, and basic
functionality seems to work.
As discussed off-list: it would be nice to have an example of how
cpufreq could be used as a cooling device for hot temperatures. The
vendor kernel has some trip points that could be included as examples,
or even included as extra patches.
Also the driver patch is missing the two main thermal maintainers, so
please resend at least the driver and bindings including them.
Kevin
^ permalink raw reply
* Re: [PATCH v2] dt-bindings: usb: renesas_gen3: Rename bindings documentation file to reflect IP block
From: Niklas Söderlund @ 2019-08-10 0:02 UTC (permalink / raw)
To: Simon Horman
Cc: Greg Kroah-Hartman, Yoshihiro Shimoda, Geert Uytterhoeven,
Magnus Damm, Rob Herring, Mark Rutland, linux-usb, devicetree,
linux-renesas-soc
In-Reply-To: <20190809213710.31783-1-horms+renesas@verge.net.au>
Hi Simon,
Thanks for your work.
On 2019-08-09 14:37:10 -0700, Simon Horman wrote:
> For consistency with the naming of (most) other documentation files for DT
> bindings for Renesas IP blocks rename the Renesas USB3.0 peripheral
> documentation file from renesas,usb3.txt to renesas,usb3-peri.txt
>
> This refines a recent rename from renesas_usb3.txt to renesas-usb3.txt.
> The motivation is to more accurately reflect the IP block documented in
> this file.
>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas S�derlund <niklas.soderlund+renesas@ragnatech.se>
> ---
> * Based on v5.3-rc1
>
> v2
> * Add review tag
> * Correct changelog
> ---
> .../devicetree/bindings/usb/{renesas,usb3.txt => renesas,usb3-peri.txt} | 0
> 1 file changed, 0 insertions(+), 0 deletions(-)
> rename Documentation/devicetree/bindings/usb/{renesas,usb3.txt => renesas,usb3-peri.txt} (100%)
>
> diff --git a/Documentation/devicetree/bindings/usb/renesas,usb3.txt b/Documentation/devicetree/bindings/usb/renesas,usb3-peri.txt
> similarity index 100%
> rename from Documentation/devicetree/bindings/usb/renesas,usb3.txt
> rename to Documentation/devicetree/bindings/usb/renesas,usb3-peri.txt
> --
> 2.11.0
>
--
Regards,
Niklas S�derlund
^ permalink raw reply
* Re: [PATCH] dt-bindings: arm: amlogic: fix x96-max/sei510 section in amlogic.yaml
From: Kevin Hilman @ 2019-08-09 22:39 UTC (permalink / raw)
To: Rob Herring, Neil Armstrong
Cc: devicetree, linux-amlogic, linux-kernel@vger.kernel.org,
Christian Hewitt
In-Reply-To: <CAL_JsqJ=dUX-bPa06KxJowf_3GM2-mPwm4U1KyTXyH0thA1pvg@mail.gmail.com>
Rob Herring <robh+dt@kernel.org> writes:
> On Tue, Aug 6, 2019 at 1:55 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
>>
>> From: Christian Hewitt <christianshewitt@gmail.com>
>>
>> Move amediatech,x96-max and seirobotics,sei510 to the S905D2 section and
>> update the S905D2 description to S905D2/X2/Y2.
>>
>> Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
>> ---
>> Documentation/devicetree/bindings/arm/amlogic.yaml | 6 +++---
>> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> Acked-by: Rob Herring <robh@kernel.org>
Queued for v5.4,
Thanks,
Kevin
^ permalink raw reply
* Re: [PATCH] of: Fix of_empty_ranges_quirk()
From: Rob Herring @ 2019-08-09 22:34 UTC (permalink / raw)
To: Marek Vašut
Cc: devicetree, Marek Vasut, Frank Rowand,
open list:MEDIA DRIVERS FOR RENESAS - FCP
In-Reply-To: <20190809173321.19944-1-marek.vasut@gmail.com>
On Fri, Aug 9, 2019 at 11:33 AM <marek.vasut@gmail.com> wrote:
>
> From: Marek Vasut <marek.vasut+renesas@gmail.com>
>
> The of_empty_ranges_quirk() returns a mix of boolean and signed integer
> types, which cannot work well.
It never returns a negative. The negative is used as an uninitialized
flag. Note quirk_state is static.
> Replace that with boolean only and fix
> usage logic in of_translate_one() -- the check should trigger when the
> ranges are NULL and the quirk is applicable on the hardware.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Frank Rowand <frowand.list@gmail.com>
> Cc: linux-renesas-soc@vger.kernel.org
> To: devicetree@vger.kernel.org
> ---
> drivers/of/address.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/of/address.c b/drivers/of/address.c
> index b492176c0572..ae2819e148b8 100644
> --- a/drivers/of/address.c
> +++ b/drivers/of/address.c
> @@ -616,7 +616,7 @@ static struct of_bus *of_match_bus(struct device_node *np)
> return NULL;
> }
>
> -static int of_empty_ranges_quirk(struct device_node *np)
> +static bool of_empty_ranges_quirk(struct device_node *np)
> {
> if (IS_ENABLED(CONFIG_PPC)) {
> /* To save cycles, we cache the result for global "Mac" setting */
> @@ -631,7 +631,8 @@ static int of_empty_ranges_quirk(struct device_node *np)
> quirk_state =
> of_machine_is_compatible("Power Macintosh") ||
> of_machine_is_compatible("MacRISC");
> - return quirk_state;
> + if (quirk_state > 0)
> + return true;
> }
> return false;
> }
> @@ -662,8 +663,8 @@ static int of_translate_one(struct device_node *parent, struct of_bus *bus,
> * This code is only enabled on powerpc. --gcl
> */
> ranges = of_get_property(parent, rprop, &rlen);
> - if (ranges == NULL && !of_empty_ranges_quirk(parent)) {
> - pr_debug("no ranges; cannot translate\n");
> + if (ranges == NULL && of_empty_ranges_quirk(parent)) {
> + pr_err("no ranges; cannot translate\n");
This is wrong. If you have NULL ranges and not the quirk, then no
ranges is an error. IOW, if you are getting an error here, you have an
error in your DT (because I assume you are not working on a PASemi or
Apple system).
Rob
^ permalink raw reply
* Re: [PATCH v2 2/2] spi: npcm-fiu: add NPCM FIU controller driver
From: Tomer Maimon @ 2019-08-09 22:23 UTC (permalink / raw)
To: Benjamin Fair
Cc: Mark Brown, Rob Herring, Mark Rutland, Vignesh Raghavendra,
Boris Brezillon, Avi Fishman, Tali Perry, Patrick Venture,
Nancy Yuen, linux-spi, devicetree, OpenBMC Maillist,
Linux Kernel Mailing List
In-Reply-To: <CADKL2t4=k=73uDMwdg3OJch1ZhRcv6Z5pRFoAbHvPxmSzvJczg@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 34243 bytes --]
On Fri, 9 Aug 2019 at 21:02, Benjamin Fair <benjaminfair@google.com> wrote:
> On Thu, Aug 8, 2019 at 6:15 AM Tomer Maimon <tmaimon77@gmail.com> wrote:
> >
> > Add Nuvoton NPCM BMC Flash Interface Unit(FIU) SPI master
> > controller driver using SPI-MEM interface.
> >
> > The FIU supports single, dual or quad communication interface.
> >
> > the FIU controller can operate in following modes:
> > - User Mode Access(UMA): provides flash access by using an
> > indirect address/data mechanism.
> > - direct rd/wr mode: maps the flash memory into the core
> > address space.
> > - SPI-X mode: used for an expansion bus to an ASIC or CPLD.
> >
> > Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
> > ---
> > drivers/spi/Kconfig | 10 +
> > drivers/spi/Makefile | 1 +
> > drivers/spi/spi-npcm-fiu.c | 761 +++++++++++++++++++++++++++++++++++++
> > 3 files changed, 772 insertions(+)
> > create mode 100644 drivers/spi/spi-npcm-fiu.c
> >
> > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> > index 3a1d8f1170de..6ee514fd0920 100644
> > --- a/drivers/spi/Kconfig
> > +++ b/drivers/spi/Kconfig
> > @@ -433,6 +433,16 @@ config SPI_MT7621
> > help
> > This selects a driver for the MediaTek MT7621 SPI Controller.
> >
> > +config SPI_NPCM_FIU
> > + tristate "Nuvoton NPCM FLASH Interface Unit"
> > + depends on ARCH_NPCM || COMPILE_TEST
> > + depends on OF && HAS_IOMEM
> > + help
> > + This enables support for the Flash Interface Unit SPI
> controller
> > + in master mode.
> > + This driver does not support generic SPI. The implementation
> only
> > + supports spi-mem interface.
> > +
> > config SPI_NPCM_PSPI
> > tristate "Nuvoton NPCM PSPI Controller"
> > depends on ARCH_NPCM || COMPILE_TEST
> > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> > index 63dcab552bcb..adbebee93a75 100644
> > --- a/drivers/spi/Makefile
> > +++ b/drivers/spi/Makefile
> > @@ -63,6 +63,7 @@ obj-$(CONFIG_SPI_MT65XX) += spi-mt65xx.o
> > obj-$(CONFIG_SPI_MT7621) += spi-mt7621.o
> > obj-$(CONFIG_SPI_MXIC) += spi-mxic.o
> > obj-$(CONFIG_SPI_MXS) += spi-mxs.o
> > +obj-$(CONFIG_SPI_NPCM_FIU) += spi-npcm-fiu.o
> > obj-$(CONFIG_SPI_NPCM_PSPI) += spi-npcm-pspi.o
> > obj-$(CONFIG_SPI_NUC900) += spi-nuc900.o
> > obj-$(CONFIG_SPI_NXP_FLEXSPI) += spi-nxp-fspi.o
> > diff --git a/drivers/spi/spi-npcm-fiu.c b/drivers/spi/spi-npcm-fiu.c
> > new file mode 100644
> > index 000000000000..2d8c281e8fa9
> > --- /dev/null
> > +++ b/drivers/spi/spi-npcm-fiu.c
> > @@ -0,0 +1,761 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +// Copyright (c) 2019 Nuvoton Technology corporation.
> > +
> > +#include <linux/init.h>
> > +#include <linux/kernel.h>
> > +#include <linux/device.h>
> > +#include <linux/module.h>
> > +#include <linux/ioport.h>
> > +#include <linux/clk.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/io.h>
> > +#include <linux/vmalloc.h>
> > +#include <linux/regmap.h>
> > +#include <linux/of_device.h>
> > +#include <linux/spi/spi-mem.h>
> > +#include <linux/mfd/syscon.h>
> > +
> > +/* NPCM7xx GCR module */
> > +#define NPCM7XX_INTCR3_OFFSET 0x9C
> > +#define NPCM7XX_INTCR3_FIU_FIX BIT(6)
> > +
> > +/* Flash Interface Unit (FIU) Registers */
> > +#define NPCM_FIU_DRD_CFG 0x00
> > +#define NPCM_FIU_DWR_CFG 0x04
> > +#define NPCM_FIU_UMA_CFG 0x08
> > +#define NPCM_FIU_UMA_CTS 0x0C
> > +#define NPCM_FIU_UMA_CMD 0x10
> > +#define NPCM_FIU_UMA_ADDR 0x14
> > +#define NPCM_FIU_PRT_CFG 0x18
> > +#define NPCM_FIU_UMA_DW0 0x20
> > +#define NPCM_FIU_UMA_DW1 0x24
> > +#define NPCM_FIU_UMA_DW2 0x28
> > +#define NPCM_FIU_UMA_DW3 0x2C
> > +#define NPCM_FIU_UMA_DR0 0x30
> > +#define NPCM_FIU_UMA_DR1 0x34
> > +#define NPCM_FIU_UMA_DR2 0x38
> > +#define NPCM_FIU_UMA_DR3 0x3C
> > +#define NPCM_FIU_MAX_REG_LIMIT 0x80
> > +
> > +/* FIU Direct Read Configuration Register */
> > +#define NPCM_FIU_DRD_CFG_LCK BIT(31)
> > +#define NPCM_FIU_DRD_CFG_R_BURST GENMASK(25, 24)
> > +#define NPCM_FIU_DRD_CFG_ADDSIZ GENMASK(17, 16)
> > +#define NPCM_FIU_DRD_CFG_DBW GENMASK(13, 12)
> > +#define NPCM_FIU_DRD_CFG_ACCTYPE GENMASK(9, 8)
> > +#define NPCM_FIU_DRD_CFG_RDCMD GENMASK(7, 0)
> > +#define NPCM_FIU_DRD_ADDSIZ_SHIFT 16
> > +#define NPCM_FIU_DRD_DBW_SHIFT 12
> > +#define NPCM_FIU_DRD_ACCTYPE_SHIFT 8
> > +
> > +/* FIU Direct Write Configuration Register */
> > +#define NPCM_FIU_DWR_CFG_LCK BIT(31)
> > +#define NPCM_FIU_DWR_CFG_W_BURST GENMASK(25, 24)
> > +#define NPCM_FIU_DWR_CFG_ADDSIZ GENMASK(17, 16)
> > +#define NPCM_FIU_DWR_CFG_ABPCK GENMASK(11, 10)
> > +#define NPCM_FIU_DWR_CFG_DBPCK GENMASK(9, 8)
> > +#define NPCM_FIU_DWR_CFG_WRCMD GENMASK(7, 0)
> > +#define NPCM_FIU_DWR_ADDSIZ_SHIFT 16
> > +#define NPCM_FIU_DWR_ABPCK_SHIFT 10
> > +#define NPCM_FIU_DWR_DBPCK_SHIFT 8
> > +
> > +/* FIU UMA Configuration Register */
> > +#define NPCM_FIU_UMA_CFG_LCK BIT(31)
> > +#define NPCM_FIU_UMA_CFG_CMMLCK BIT(30)
> > +#define NPCM_FIU_UMA_CFG_RDATSIZ GENMASK(28, 24)
> > +#define NPCM_FIU_UMA_CFG_DBSIZ GENMASK(23, 21)
> > +#define NPCM_FIU_UMA_CFG_WDATSIZ GENMASK(20, 16)
> > +#define NPCM_FIU_UMA_CFG_ADDSIZ GENMASK(13, 11)
> > +#define NPCM_FIU_UMA_CFG_CMDSIZ BIT(10)
> > +#define NPCM_FIU_UMA_CFG_RDBPCK GENMASK(9, 8)
> > +#define NPCM_FIU_UMA_CFG_DBPCK GENMASK(7, 6)
> > +#define NPCM_FIU_UMA_CFG_WDBPCK GENMASK(5, 4)
> > +#define NPCM_FIU_UMA_CFG_ADBPCK GENMASK(3, 2)
> > +#define NPCM_FIU_UMA_CFG_CMBPCK GENMASK(1, 0)
> > +#define NPCM_FIU_UMA_CFG_ADBPCK_SHIFT 2
> > +#define NPCM_FIU_UMA_CFG_WDBPCK_SHIFT 4
> > +#define NPCM_FIU_UMA_CFG_DBPCK_SHIFT 6
> > +#define NPCM_FIU_UMA_CFG_RDBPCK_SHIFT 8
> > +#define NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT 11
> > +#define NPCM_FIU_UMA_CFG_WDATSIZ_SHIFT 16
> > +#define NPCM_FIU_UMA_CFG_DBSIZ_SHIFT 21
> > +#define NPCM_FIU_UMA_CFG_RDATSIZ_SHIFT 24
> > +
> > +/* FIU UMA Control and Status Register */
> > +#define NPCM_FIU_UMA_CTS_RDYIE BIT(25)
> > +#define NPCM_FIU_UMA_CTS_RDYST BIT(24)
> > +#define NPCM_FIU_UMA_CTS_SW_CS BIT(16)
> > +#define NPCM_FIU_UMA_CTS_DEV_NUM GENMASK(9, 8)
> > +#define NPCM_FIU_UMA_CTS_EXEC_DONE BIT(0)
> > +#define NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT 8
> > +
> > +/* FIU UMA Command Register */
> > +#define NPCM_FIU_UMA_CMD_DUM3 GENMASK(31, 24)
> > +#define NPCM_FIU_UMA_CMD_DUM2 GENMASK(23, 16)
> > +#define NPCM_FIU_UMA_CMD_DUM1 GENMASK(15, 8)
> > +#define NPCM_FIU_UMA_CMD_CMD GENMASK(7, 0)
> > +
> > +/* FIU UMA Address Register */
> > +#define NPCM_FIU_UMA_ADDR_UMA_ADDR GENMASK(31, 0)
> > +#define NPCM_FIU_UMA_ADDR_AB3 GENMASK(31, 24)
> > +#define NPCM_FIU_UMA_ADDR_AB2 GENMASK(23, 16)
> > +#define NPCM_FIU_UMA_ADDR_AB1 GENMASK(15, 8)
> > +#define NPCM_FIU_UMA_ADDR_AB0 GENMASK(7, 0)
> > +
> > +/* FIU UMA Write Data Bytes 0-3 Register */
> > +#define NPCM_FIU_UMA_DW0_WB3 GENMASK(31, 24)
> > +#define NPCM_FIU_UMA_DW0_WB2 GENMASK(23, 16)
> > +#define NPCM_FIU_UMA_DW0_WB1 GENMASK(15, 8)
> > +#define NPCM_FIU_UMA_DW0_WB0 GENMASK(7, 0)
> > +
> > +/* FIU UMA Write Data Bytes 4-7 Register */
> > +#define NPCM_FIU_UMA_DW1_WB7 GENMASK(31, 24)
> > +#define NPCM_FIU_UMA_DW1_WB6 GENMASK(23, 16)
> > +#define NPCM_FIU_UMA_DW1_WB5 GENMASK(15, 8)
> > +#define NPCM_FIU_UMA_DW1_WB4 GENMASK(7, 0)
> > +
> > +/* FIU UMA Write Data Bytes 8-11 Register */
> > +#define NPCM_FIU_UMA_DW2_WB11 GENMASK(31, 24)
> > +#define NPCM_FIU_UMA_DW2_WB10 GENMASK(23, 16)
> > +#define NPCM_FIU_UMA_DW2_WB9 GENMASK(15, 8)
> > +#define NPCM_FIU_UMA_DW2_WB8 GENMASK(7, 0)
> > +
> > +/* FIU UMA Write Data Bytes 12-15 Register */
> > +#define NPCM_FIU_UMA_DW3_WB15 GENMASK(31, 24)
> > +#define NPCM_FIU_UMA_DW3_WB14 GENMASK(23, 16)
> > +#define NPCM_FIU_UMA_DW3_WB13 GENMASK(15, 8)
> > +#define NPCM_FIU_UMA_DW3_WB12 GENMASK(7, 0)
> > +
> > +/* FIU UMA Read Data Bytes 0-3 Register */
> > +#define NPCM_FIU_UMA_DR0_RB3 GENMASK(31, 24)
> > +#define NPCM_FIU_UMA_DR0_RB2 GENMASK(23, 16)
> > +#define NPCM_FIU_UMA_DR0_RB1 GENMASK(15, 8)
> > +#define NPCM_FIU_UMA_DR0_RB0 GENMASK(7, 0)
> > +
> > +/* FIU UMA Read Data Bytes 4-7 Register */
> > +#define NPCM_FIU_UMA_DR1_RB15 GENMASK(31, 24)
> > +#define NPCM_FIU_UMA_DR1_RB14 GENMASK(23, 16)
> > +#define NPCM_FIU_UMA_DR1_RB13 GENMASK(15, 8)
> > +#define NPCM_FIU_UMA_DR1_RB12 GENMASK(7, 0)
> > +
> > +/* FIU UMA Read Data Bytes 8-11 Register */
> > +#define NPCM_FIU_UMA_DR2_RB15 GENMASK(31, 24)
> > +#define NPCM_FIU_UMA_DR2_RB14 GENMASK(23, 16)
> > +#define NPCM_FIU_UMA_DR2_RB13 GENMASK(15, 8)
> > +#define NPCM_FIU_UMA_DR2_RB12 GENMASK(7, 0)
> > +
> > +/* FIU UMA Read Data Bytes 12-15 Register */
> > +#define NPCM_FIU_UMA_DR3_RB15 GENMASK(31, 24)
> > +#define NPCM_FIU_UMA_DR3_RB14 GENMASK(23, 16)
> > +#define NPCM_FIU_UMA_DR3_RB13 GENMASK(15, 8)
> > +#define NPCM_FIU_UMA_DR3_RB12 GENMASK(7, 0)
> > +
> > +/* FIU Read Mode */
> > +enum {
> > + DRD_SINGLE_WIRE_MODE = 0,
> > + DRD_DUAL_IO_MODE = 1,
> > + DRD_QUAD_IO_MODE = 2,
> > + DRD_SPI_X_MODE = 3,
> > +};
> > +
> > +enum {
> > + DWR_ABPCK_BIT_PER_CLK = 0,
> > + DWR_ABPCK_2_BIT_PER_CLK = 1,
> > + DWR_ABPCK_4_BIT_PER_CLK = 2,
> > +};
> > +
> > +enum {
> > + DWR_DBPCK_BIT_PER_CLK = 0,
> > + DWR_DBPCK_2_BIT_PER_CLK = 1,
> > + DWR_DBPCK_4_BIT_PER_CLK = 2,
> > +};
> > +
> > +#define NPCM_FIU_DRD_16_BYTE_BURST 0x3000000
> > +#define NPCM_FIU_DWR_16_BYTE_BURST 0x3000000
> > +
> > +#define MAP_SIZE_128MB 0x8000000
> > +#define MAP_SIZE_16MB 0x1000000
> > +#define MAP_SIZE_8MB 0x800000
> > +
> > +#define NUM_BITS_IN_BYTE 8
> > +#define FIU_DRD_MAX_DUMMY_NUMBER 3
> > +#define NPCM_MAX_CHIP_NUM 4
> > +#define CHUNK_SIZE 16
> > +#define UMA_MICRO_SEC_TIMEOUT 150
> > +
> > +enum {
> > + FIU0 = 0,
> > + FIU3,
> > + FIUX,
> > +};
> > +
> > +struct npcm_fiu_info {
> > + char *name;
> > + u32 fiu_id;
> > + u32 max_map_size;
> > + u32 max_cs;
> > +};
> > +
> > +struct fiu_data {
> > + const struct npcm_fiu_info *npcm_fiu_data_info;
> > + int fiu_max;
> > +};
> > +
> > +static const struct npcm_fiu_info npxm7xx_fiu_info[] = {
> > + {.name = "FIU0", .fiu_id = FIU0,
> > + .max_map_size = MAP_SIZE_128MB, .max_cs = 2},
> > + {.name = "FIU3", .fiu_id = FIU3,
> > + .max_map_size = MAP_SIZE_128MB, .max_cs = 4},
> > + {.name = "FIUX", .fiu_id = FIUX,
> > + .max_map_size = MAP_SIZE_16MB, .max_cs = 2} };
> > +
> > +static const struct fiu_data npxm7xx_fiu_data = {
> > + .npcm_fiu_data_info = npxm7xx_fiu_info,
> > + .fiu_max = 3,
> > +};
> > +
> > +struct npcm_fiu_spi;
> > +
> > +struct npcm_fiu_chip {
> > + void __iomem *flash_region_mapped_ptr;
> > + struct npcm_fiu_spi *fiu;
> > + unsigned long clkrate;
> > + u32 chipselect;
> > +};
> > +
> > +struct npcm_fiu_spi {
> > + struct npcm_fiu_chip chip[NPCM_MAX_CHIP_NUM];
> > + const struct npcm_fiu_info *info;
> > + struct spi_mem_op drd_op;
> > + struct resource *res_mem;
> > + struct regmap *regmap;
> > + unsigned long clkrate;
> > + struct device *dev;
> > + struct clk *clk;
> > + bool spix_mode;
> > +};
> > +
> > +static const struct regmap_config npcm_mtd_regmap_config = {
> > + .reg_bits = 32,
> > + .val_bits = 32,
> > + .reg_stride = 4,
> > + .max_register = NPCM_FIU_MAX_REG_LIMIT,
> > +};
> > +
> > +static void npcm_fiu_set_drd(struct npcm_fiu_spi *fiu,
> > + const struct spi_mem_op *op)
> > +{
> > + regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
> > + NPCM_FIU_DRD_CFG_ACCTYPE,
> > + ilog2(op->addr.buswidth) <<
> > + NPCM_FIU_DRD_ACCTYPE_SHIFT);
> > + fiu->drd_op.addr.buswidth = op->addr.buswidth;
> > + regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
> > + NPCM_FIU_DRD_CFG_DBW,
> > + ((op->dummy.nbytes * ilog2(op->addr.buswidth))
> > + / NUM_BITS_IN_BYTE) <<
> NPCM_FIU_DRD_DBW_SHIFT);
> > + fiu->drd_op.dummy.nbytes = op->dummy.nbytes;
> > + regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
> > + NPCM_FIU_DRD_CFG_RDCMD, op->cmd.opcode);
> > + fiu->drd_op.cmd.opcode = op->cmd.opcode;
> > + regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
> > + NPCM_FIU_DRD_CFG_ADDSIZ,
> > + (op->addr.nbytes - 3) <<
> NPCM_FIU_DRD_ADDSIZ_SHIFT);
> > + fiu->drd_op.addr.nbytes = op->addr.nbytes;
> > +}
> > +
> > +static ssize_t npcm_fiu_direct_read(struct spi_mem_dirmap_desc *desc,
> > + u64 offs, size_t len, void *buf)
> > +{
> > + struct npcm_fiu_spi *fiu =
> > + spi_controller_get_devdata(desc->mem->spi->master);
> > + struct npcm_fiu_chip *chip =
> &fiu->chip[desc->mem->spi->chip_select];
> > + void __iomem *src = (void __iomem
> *)(chip->flash_region_mapped_ptr +
> > + offs);
> > + u8 *buf_rx = buf;
> > + u32 i;
> > +
> > + if (fiu->spix_mode) {
> > + for (i = 0 ; i < len ; i++)
> > + *(buf_rx + i) = ioread8(src + i);
> > + } else {
> > + if (desc->info.op_tmpl.addr.buswidth !=
> fiu->drd_op.addr.buswidth ||
> > + desc->info.op_tmpl.dummy.nbytes !=
> fiu->drd_op.dummy.nbytes ||
> > + desc->info.op_tmpl.cmd.opcode !=
> fiu->drd_op.cmd.opcode ||
> > + desc->info.op_tmpl.addr.nbytes !=
> fiu->drd_op.addr.nbytes)
> > + npcm_fiu_set_drd(fiu, &desc->info.op_tmpl);
> > +
> > + memcpy_fromio(buf_rx, src, len);
>
> Does this need to make sure the memcpy is aligned, or is that handled
> at a higher layer?
>
The memcpy_fromio use in the direct functions can deal with unaligned
address, we have stress test it for some time
and it working well, I have sent Kun the test stress scripts.
> > + }
> > +
> > + return len;
> > +}
> > +
> > +static ssize_t npcm_fiu_direct_write(struct spi_mem_dirmap_desc *desc,
> > + u64 offs, size_t len, const void
> *buf)
> > +{
> > + struct npcm_fiu_spi *fiu =
> > + spi_controller_get_devdata(desc->mem->spi->master);
> > + struct npcm_fiu_chip *chip =
> &fiu->chip[desc->mem->spi->chip_select];
> > + void __iomem *dst = (void __iomem
> *)(chip->flash_region_mapped_ptr +
> > + offs);
> > + const u8 *buf_tx = buf;
> > + u32 i;
> > +
> > + if (fiu->spix_mode)
> > + for (i = 0 ; i < len ; i++)
> > + iowrite8(*(buf_tx + i), dst + i);
> > + else
> > + memcpy_toio(dst, buf_tx, len);
> > +
> > + return len;
> > +}
> > +
> > +static int npcm_fiu_uma_read(struct spi_mem *mem,
> > + const struct spi_mem_op *op, u32 addr,
> > + bool is_address_size, u8 *data, u32
> data_size)
> > +{
> > + struct npcm_fiu_spi *fiu =
> > + spi_controller_get_devdata(mem->spi->master);
> > + u32 uma_cfg = BIT(10);
> > + u32 data_reg[4];
> > + int ret;
> > + u32 val;
> > + u32 i;
> > +
> > + regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
> > + NPCM_FIU_UMA_CTS_DEV_NUM,
> > + (mem->spi->chip_select <<
> > + NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT));
> > + regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD,
> > + NPCM_FIU_UMA_CMD_CMD, op->cmd.opcode);
> > +
> > + if (is_address_size) {
> > + uma_cfg |= ilog2(op->cmd.buswidth);
> > + uma_cfg |= ilog2(op->addr.buswidth)
> > + << NPCM_FIU_UMA_CFG_ADBPCK_SHIFT;
> > + uma_cfg |= ilog2(op->dummy.buswidth)
> > + << NPCM_FIU_UMA_CFG_DBPCK_SHIFT;
> > + uma_cfg |= ilog2(op->data.buswidth)
> > + << NPCM_FIU_UMA_CFG_RDBPCK_SHIFT;
> > + uma_cfg |= op->dummy.nbytes <<
> NPCM_FIU_UMA_CFG_DBSIZ_SHIFT;
> > + uma_cfg |= op->addr.nbytes <<
> NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT;
> > + regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, addr);
> > + } else {
> > + regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0);
> > + }
> > +
> > + uma_cfg |= data_size << NPCM_FIU_UMA_CFG_RDATSIZ_SHIFT;
> > + regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg);
> > + regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
> > + NPCM_FIU_UMA_CTS_EXEC_DONE,
> > + NPCM_FIU_UMA_CTS_EXEC_DONE);
> > + ret = regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS,
> val,
> > + (!(val &
> NPCM_FIU_UMA_CTS_EXEC_DONE)), 0,
> > + UMA_MICRO_SEC_TIMEOUT);
> > + if (ret)
> > + return ret;
> > +
> > + if (data_size) {
> > + for (i = 0; i < DIV_ROUND_UP(data_size, 4); i++)
> > + regmap_read(fiu->regmap, NPCM_FIU_UMA_DR0 + (i *
> 4),
> > + &data_reg[i]);
> > + memcpy(data, data_reg, data_size);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int npcm_fiu_uma_write(struct spi_mem *mem,
> > + const struct spi_mem_op *op, u8 cmd,
> > + bool is_address_size, u8 *data, u32
> data_size)
> > +{
> > + struct npcm_fiu_spi *fiu =
> > + spi_controller_get_devdata(mem->spi->master);
> > + u32 uma_cfg = BIT(10);
> > + u32 data_reg[4] = {0};
> > + u32 val;
> > + u32 i;
> > +
> > + regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
> > + NPCM_FIU_UMA_CTS_DEV_NUM,
> > + (mem->spi->chip_select <<
> > + NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT));
> > +
> > + regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CMD,
> > + NPCM_FIU_UMA_CMD_CMD, cmd);
> > +
> > + if (data_size) {
> > + memcpy(data_reg, data, data_size);
> > + for (i = 0; i < DIV_ROUND_UP(data_size, 4); i++)
> > + regmap_write(fiu->regmap, NPCM_FIU_UMA_DW0 + (i
> * 4),
> > + data_reg[i]);
> > + }
> > +
> > + if (is_address_size) {
> > + uma_cfg |= ilog2(op->cmd.buswidth);
> > + uma_cfg |= ilog2(op->addr.buswidth) <<
> > + NPCM_FIU_UMA_CFG_ADBPCK_SHIFT;
> > + uma_cfg |= ilog2(op->data.buswidth) <<
> > + NPCM_FIU_UMA_CFG_WDBPCK_SHIFT;
> > + uma_cfg |= op->addr.nbytes <<
> NPCM_FIU_UMA_CFG_ADDSIZ_SHIFT;
> > + regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR,
> op->addr.val);
> > + } else {
> > + regmap_write(fiu->regmap, NPCM_FIU_UMA_ADDR, 0x0);
> > + }
> > +
> > + uma_cfg |= (data_size << NPCM_FIU_UMA_CFG_WDATSIZ_SHIFT);
> > + regmap_write(fiu->regmap, NPCM_FIU_UMA_CFG, uma_cfg);
> > +
> > + regmap_write_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
> > + NPCM_FIU_UMA_CTS_EXEC_DONE,
> > + NPCM_FIU_UMA_CTS_EXEC_DONE);
> > +
> > + return regmap_read_poll_timeout(fiu->regmap, NPCM_FIU_UMA_CTS,
> val,
> > + (!(val &
> NPCM_FIU_UMA_CTS_EXEC_DONE)), 0,
> > + UMA_MICRO_SEC_TIMEOUT);
> > +}
> > +
> > +static int npcm_fiu_manualwrite(struct spi_mem *mem,
> > + const struct spi_mem_op *op)
> > +{
> > + struct npcm_fiu_spi *fiu =
> > + spi_controller_get_devdata(mem->spi->master);
> > + u8 *data = (u8 *)op->data.buf.out;
> > + u32 num_data_chunks;
> > + u32 remain_data;
> > + u32 idx = 0;
> > + int ret;
> > +
> > + num_data_chunks = op->data.nbytes / CHUNK_SIZE;
> > + remain_data = op->data.nbytes % CHUNK_SIZE;
> > +
> > + regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
> > + NPCM_FIU_UMA_CTS_DEV_NUM,
> > + (mem->spi->chip_select <<
> > + NPCM_FIU_UMA_CTS_DEV_NUM_SHIFT));
> > + regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
> > + NPCM_FIU_UMA_CTS_SW_CS, 0);
> > +
> > + ret = npcm_fiu_uma_write(mem, op, op->cmd.opcode, true, NULL, 0);
> > + if (ret)
> > + return ret;
> > +
> > + /* Starting the data writing loop in multiples of 8 */
> > + for (idx = 0; idx < num_data_chunks; ++idx) {
> > + ret = npcm_fiu_uma_write(mem, op, data[0], false,
> > + &data[1], CHUNK_SIZE - 1);
> > + if (ret)
> > + return ret;
> > +
> > + data += CHUNK_SIZE;
> > + }
> > +
> > + /* Handling chunk remains */
> > + if (remain_data > 0) {
> > + ret = npcm_fiu_uma_write(mem, op, data[0], false,
> > + &data[1], remain_data - 1);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + regmap_update_bits(fiu->regmap, NPCM_FIU_UMA_CTS,
> > + NPCM_FIU_UMA_CTS_SW_CS,
> NPCM_FIU_UMA_CTS_SW_CS);
> > +
> > + return 0;
> > +}
> > +
> > +static int npcm_fiu_read(struct spi_mem *mem, const struct spi_mem_op
> *op)
> > +{
> > + u8 *data = op->data.buf.in;
> > + int i, readlen, currlen;
> > + size_t retlen = 0;
> > + u8 *buf_ptr;
> > + u32 addr;
> > + int ret;
> > +
> > + i = 0;
> > + currlen = op->data.nbytes;
> > +
> > + do {
> > + addr = ((u32)op->addr.val + i);
> > + if (currlen < 16)
> > + readlen = currlen;
> > + else
> > + readlen = 16;
> > +
> > + buf_ptr = data + i;
> > + ret = npcm_fiu_uma_read(mem, op, addr, true, buf_ptr,
> > + readlen);
> > + if (ret)
> > + return ret;
> > +
> > + i += readlen;
> > + currlen -= 16;
> > + } while (currlen > 0);
> > +
> > + retlen = i;
> > +
> > + return 0;
> > +}
> > +
> > +static void npcm_fiux_set_direct_wr(struct npcm_fiu_spi *fiu)
> > +{
> > + regmap_write(fiu->regmap, NPCM_FIU_DWR_CFG,
> > + NPCM_FIU_DWR_16_BYTE_BURST);
> > + regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG,
> > + NPCM_FIU_DWR_CFG_ABPCK,
> > + DWR_ABPCK_4_BIT_PER_CLK <<
> NPCM_FIU_DWR_ABPCK_SHIFT);
> > + regmap_update_bits(fiu->regmap, NPCM_FIU_DWR_CFG,
> > + NPCM_FIU_DWR_CFG_DBPCK,
> > + DWR_DBPCK_4_BIT_PER_CLK <<
> NPCM_FIU_DWR_DBPCK_SHIFT);
> > +}
> > +
> > +static void npcm_fiux_set_direct_rd(struct npcm_fiu_spi *fiu)
> > +{
> > + u32 rx_dummy = 0;
> > +
> > + regmap_write(fiu->regmap, NPCM_FIU_DRD_CFG,
> > + NPCM_FIU_DRD_16_BYTE_BURST);
> > + regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
> > + NPCM_FIU_DRD_CFG_ACCTYPE,
> > + DRD_SPI_X_MODE << NPCM_FIU_DRD_ACCTYPE_SHIFT);
> > + regmap_update_bits(fiu->regmap, NPCM_FIU_DRD_CFG,
> > + NPCM_FIU_DRD_CFG_DBW,
> > + rx_dummy << NPCM_FIU_DRD_DBW_SHIFT);
> > +}
> > +
> > +static int npcm_fiu_exec_op(struct spi_mem *mem, const struct
> spi_mem_op *op)
> > +{
> > + struct npcm_fiu_spi *fiu =
> > + spi_controller_get_devdata(mem->spi->master);
> > + struct npcm_fiu_chip *chip = &fiu->chip[mem->spi->chip_select];
> > + int ret = 0;
> > + u8 *buf;
> > +
> > + dev_dbg(fiu->dev, "cmd:%#x mode:%d.%d.%d.%d addr:%#llx
> len:%#x\n",
> > + op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth,
> > + op->dummy.buswidth, op->data.buswidth, op->addr.val,
> > + op->data.nbytes);
> > +
> > + if (fiu->spix_mode)
> > + return -ENOTSUPP;
> > +
> > + if (fiu->clkrate != chip->clkrate) {
> > + ret = clk_set_rate(fiu->clk, chip->clkrate);
> > + if (ret < 0)
> > + dev_warn(fiu->dev, "Failed setting %lu
> frequancy, stay at %lu frequancy\n", chip->clkrate, fiu->clkrate);
> > + else
> > + fiu->clkrate = chip->clkrate;
> > + }
> > +
> > + if (op->data.dir == SPI_MEM_DATA_IN) {
> > + if (!op->addr.nbytes) {
> > + buf = op->data.buf.in;
> > + ret = npcm_fiu_uma_read(mem, op, op->addr.val,
> false,
> > + buf, op->data.nbytes);
> > + } else {
> > + ret = npcm_fiu_read(mem, op);
> > + }
> > + } else {
> > + if (!op->addr.nbytes || !op->data.nbytes) {
> > + if (op->data.nbytes)
> > + buf = (u8 *)op->data.buf.out;
> > + else
> > + buf = NULL;
> > + ret = npcm_fiu_uma_write(mem, op,
> op->cmd.opcode, false,
> > + buf, op->data.nbytes);
> > + } else {
> > + ret = npcm_fiu_manualwrite(mem, op);
> > + }
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static int npcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc)
> > +{
> > + struct npcm_fiu_spi *fiu =
> > + spi_controller_get_devdata(desc->mem->spi->master);
> > + struct npcm_fiu_chip *chip =
> &fiu->chip[desc->mem->spi->chip_select];
> > + struct regmap *gcr_regmap;
> > +
> > + if (!fiu->res_mem) {
> > + dev_warn(fiu->dev, "Reserved memory not defined, direct
> read disabled\n");
> > + desc->nodirmap = true;
> > + return 0;
> > + }
> > +
> > + if (!fiu->spix_mode &&
> > + desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) {
> > + desc->nodirmap = true;
> > + return 0;
> > + }
> > +
> > + if (!chip->flash_region_mapped_ptr) {
> > + chip->flash_region_mapped_ptr =
> > + devm_ioremap_nocache(fiu->dev,
> (fiu->res_mem->start +
> > +
> (fiu->info->max_map_size *
> > +
> desc->mem->spi->chip_select)),
> > + (u32)desc->info.length);
> > + if (!chip->flash_region_mapped_ptr) {
> > + dev_warn(fiu->dev, "Error mapping memory region,
> direct read disabled\n");
> > + desc->nodirmap = true;
> > + return 0;
> > + }
> > + }
> > +
> > + if (of_device_is_compatible(fiu->dev->of_node,
> "nuvoton,npcm750-fiu")) {
> > + gcr_regmap =
> > +
> syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
> > + if (IS_ERR(gcr_regmap)) {
> > + dev_warn(fiu->dev, "Didn't find
> nuvoton,npcm750-gcr, direct read disabled\n");
> > + desc->nodirmap = true;
> > + return 0;
> > + }
> > + regmap_update_bits(gcr_regmap, NPCM7XX_INTCR3_OFFSET,
> > + NPCM7XX_INTCR3_FIU_FIX,
> > + NPCM7XX_INTCR3_FIU_FIX);
> > + }
> > +
> > + if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN) {
> > + if (!fiu->spix_mode)
> > + npcm_fiu_set_drd(fiu, &desc->info.op_tmpl);
> > + else
> > + npcm_fiux_set_direct_rd(fiu);
> > +
> > + } else {
> > + npcm_fiux_set_direct_wr(fiu);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int npcm_fiu_setup(struct spi_device *spi)
> > +{
> > + struct spi_controller *ctrl = spi->master;
> > + struct npcm_fiu_spi *fiu = spi_controller_get_devdata(ctrl);
> > + struct npcm_fiu_chip *chip;
> > +
> > + chip = &fiu->chip[spi->chip_select];
> > + chip->fiu = fiu;
> > + chip->chipselect = spi->chip_select;
> > + chip->clkrate = spi->max_speed_hz;
> > +
> > + fiu->clkrate = clk_get_rate(fiu->clk);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct spi_controller_mem_ops npcm_fiu_mem_ops = {
> > + .exec_op = npcm_fiu_exec_op,
> > + .dirmap_create = npcm_fiu_dirmap_create,
> > + .dirmap_read = npcm_fiu_direct_read,
> > + .dirmap_write = npcm_fiu_direct_write,
> > +};
> > +
> > +static const struct of_device_id npcm_fiu_dt_ids[] = {
> > + { .compatible = "nuvoton,npcm750-fiu", .data =
> &npxm7xx_fiu_data },
> > + { /* sentinel */ }
> > +};
> > +
> > +static int npcm_fiu_probe(struct platform_device *pdev)
> > +{
> > + const struct fiu_data *fiu_data_match;
> > + const struct of_device_id *match;
> > + struct device *dev = &pdev->dev;
> > + struct spi_controller *ctrl;
> > + struct npcm_fiu_spi *fiu;
> > + void __iomem *regbase;
> > + struct resource *res;
> > + int ret;
> > + int id;
> > +
> > + ctrl = spi_alloc_master(dev, sizeof(*fiu));
> > + if (!ctrl)
> > + return -ENOMEM;
> > +
> > + fiu = spi_controller_get_devdata(ctrl);
> > +
> > + match = of_match_device(npcm_fiu_dt_ids, dev);
> > + if (!match || !match->data) {
> > + dev_err(dev, "No compatible OF match\n");
> > + return -ENODEV;
> > + }
> > +
> > + fiu_data_match = match->data;
> > + id = of_alias_get_id(dev->of_node, "fiu");
> > + if (id < 0 || id >= fiu_data_match->fiu_max) {
> > + dev_err(dev, "Invalid platform device id: %d\n", id);
> > + return -EINVAL;
> > + }
> > +
> > + fiu->info = &fiu_data_match->npcm_fiu_data_info[id];
> > +
> > + platform_set_drvdata(pdev, fiu);
> > + fiu->dev = dev;
> > +
> > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> "control");
> > + regbase = devm_ioremap_resource(dev, res);
> > + if (IS_ERR(regbase))
> > + return PTR_ERR(regbase);
> > +
> > + fiu->regmap = devm_regmap_init_mmio(dev, regbase,
> > + &npcm_mtd_regmap_config);
> > + if (IS_ERR(fiu->regmap)) {
> > + dev_err(dev, "Failed to create regmap\n");
> > + return PTR_ERR(fiu->regmap);
> > + }
> > +
> > + fiu->res_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > + "memory");
> > + fiu->clk = devm_clk_get(dev, NULL);
> > + if (IS_ERR(fiu->clk))
> > + return PTR_ERR(fiu->clk);
> > +
> > + fiu->spix_mode = of_property_read_bool(dev->of_node,
> "spix-mode");
> > +
> > + platform_set_drvdata(pdev, fiu);
> > + clk_prepare_enable(fiu->clk);
> > +
> > + ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD
> > + | SPI_TX_DUAL | SPI_TX_QUAD;
> > + ctrl->setup = npcm_fiu_setup;
> > + ctrl->bus_num = -1;
> > + ctrl->mem_ops = &npcm_fiu_mem_ops;
> > + ctrl->num_chipselect = fiu->info->max_cs;
> > + ctrl->dev.of_node = dev->of_node;
> > +
> > + ret = devm_spi_register_master(dev, ctrl);
> > + if (ret)
> > + return ret;
> > +
> > + dev_info(dev, "NPCM %s probe succeed\n", fiu->info->name);
> > +
> > + return 0;
> > +}
> > +
> > +static int npcm_fiu_remove(struct platform_device *pdev)
> > +{
> > + struct npcm_fiu_spi *fiu = platform_get_drvdata(pdev);
> > +
> > + clk_disable_unprepare(fiu->clk);
> > + return 0;
> > +}
> > +
> > +MODULE_DEVICE_TABLE(of, npcm_fiu_dt_ids);
> > +
> > +static struct platform_driver npcm_fiu_driver = {
> > + .driver = {
> > + .name = "NPCM-FIU",
> > + .bus = &platform_bus_type,
> > + .of_match_table = npcm_fiu_dt_ids,
> > + },
> > + .probe = npcm_fiu_probe,
> > + .remove = npcm_fiu_remove,
> > +};
> > +module_platform_driver(npcm_fiu_driver);
> > +
> > +MODULE_DESCRIPTION("Nuvoton FLASH Interface Unit SPI Controller
> Driver");
> > +MODULE_AUTHOR("Tomer Maimon <tomer.maimon@nuvoton.com>");
> > +MODULE_LICENSE("GPL v2");
> > --
> > 2.18.0
> >
>
[-- Attachment #2: Type: text/html, Size: 45178 bytes --]
^ permalink raw reply
* [PATCH] dt-bindings: ata: sata_rcar: Rename bindings documentation file
From: Simon Horman @ 2019-08-09 21:51 UTC (permalink / raw)
To: Jens Axboe
Cc: Rob Herring, Mark Rutland, Geert Uytterhoeven, Magnus Damm,
linux-ide, devicetree, linux-renesas-soc, Simon Horman
Rename the bindings documentation file for Renesas SATA controller
from sata_rcar.txt to renesas,rcar-sata.txt
This is part of an ongoing effort to name bindings documentation files for
Renesas IP blocks consistently, in line with the compat strings they
document.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
Based on v5.3-rc1
---
.../devicetree/bindings/ata/{sata_rcar.txt => renesas,rcar-sata.txt} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/ata/{sata_rcar.txt => renesas,rcar-sata.txt} (100%)
diff --git a/Documentation/devicetree/bindings/ata/sata_rcar.txt b/Documentation/devicetree/bindings/ata/renesas,rcar-sata.txt
similarity index 100%
rename from Documentation/devicetree/bindings/ata/sata_rcar.txt
rename to Documentation/devicetree/bindings/ata/renesas,rcar-sata.txt
--
2.11.0
^ permalink raw reply
* Re: [PATCH v2 0/4] Rework secure-monitor driver
From: Kevin Hilman @ 2019-08-09 21:42 UTC (permalink / raw)
To: Srinivas Kandagatla, Carlo Caione
Cc: devicetree, narmstrong, robh+dt, linux-amlogic, tglx,
linux-arm-kernel, jbrunet
In-Reply-To: <12d38512-605c-3544-a525-2c3599559391@linaro.org>
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> writes:
> Hi Kevin,
>
> On 05/08/2019 22:34, Kevin Hilman wrote:
>> Srinivas,
>>
>> Carlo Caione <ccaione@baylibre.com> writes:
>>
>>> The secure-monitor driver is currently in really bad shape, not my
>>> proudest piece of code (thanks Jerome for pointing that out ;). I tried
>>> to rework it a bit to make it a bit more tolerable.
>>>
>>> I needed to change a bit the APIs and consequently adapt the only user
>>> we have, that is the nvmem/efuses driver. To not break bisectability I
>>> added one single commit to change both the drivers.
>>
>> With your ack on the nvmem bindings and nvmem part of patch 4/4, I can
>> take the series take the rest of this series through my tree for Amlogic
>> SoCs.
> Sounds good for me!
>
> I have Acked the driver changes, bindings need ack from DT guys.
OK, thanks. I'll wait for an ack on the binding patch, then take the
whole series through my tree.
Kevin
^ permalink raw reply
* [PATCH v2] dt-bindings: usb: renesas_gen3: Rename bindings documentation file to reflect IP block
From: Simon Horman @ 2019-08-09 21:37 UTC (permalink / raw)
To: Greg Kroah-Hartman
Cc: Yoshihiro Shimoda, Geert Uytterhoeven, Niklas Söderlund,
Magnus Damm, Rob Herring, Mark Rutland, linux-usb, devicetree,
linux-renesas-soc, Simon Horman
For consistency with the naming of (most) other documentation files for DT
bindings for Renesas IP blocks rename the Renesas USB3.0 peripheral
documentation file from renesas,usb3.txt to renesas,usb3-peri.txt
This refines a recent rename from renesas_usb3.txt to renesas-usb3.txt.
The motivation is to more accurately reflect the IP block documented in
this file.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
* Based on v5.3-rc1
v2
* Add review tag
* Correct changelog
---
.../devicetree/bindings/usb/{renesas,usb3.txt => renesas,usb3-peri.txt} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/usb/{renesas,usb3.txt => renesas,usb3-peri.txt} (100%)
diff --git a/Documentation/devicetree/bindings/usb/renesas,usb3.txt b/Documentation/devicetree/bindings/usb/renesas,usb3-peri.txt
similarity index 100%
rename from Documentation/devicetree/bindings/usb/renesas,usb3.txt
rename to Documentation/devicetree/bindings/usb/renesas,usb3-peri.txt
--
2.11.0
^ permalink raw reply
* [PATCH v2 4/4] dt-bindings: i2c: i2c-emev2: Rename bindings documentation file
From: Simon Horman @ 2019-08-09 21:30 UTC (permalink / raw)
To: Wolfram Sang, Chris Brandt
Cc: Rob Herring, Mark Rutland, Magnus Damm, linux-i2c, devicetree,
linux-renesas-soc, Simon Horman
In-Reply-To: <20190809213004.31181-1-horms+renesas@verge.net.au>
Rename the bindings documentation file for Renesas EMEV2 IIC controller
from i2c-emev2.txt to renesas,iic-emev2.txt.
This is part of an ongoing effort to name bindings documentation files for
Renesas IP blocks consistently, in line with the compat strings they
document.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2
* Added review tag
* Corrected subject to refer to i2c-emev2
---
.../devicetree/bindings/i2c/{i2c-emev2.txt => renesas,iic-emev2.txt} | 0
MAINTAINERS | 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)
rename Documentation/devicetree/bindings/i2c/{i2c-emev2.txt => renesas,iic-emev2.txt} (100%)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-emev2.txt b/Documentation/devicetree/bindings/i2c/renesas,iic-emev2.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/i2c-emev2.txt
rename to Documentation/devicetree/bindings/i2c/renesas,iic-emev2.txt
diff --git a/MAINTAINERS b/MAINTAINERS
index fc3ed4fe0ba5..e751ebb1a0ed 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13628,7 +13628,7 @@ F: drivers/clk/renesas/
RENESAS EMEV2 I2C DRIVER
M: Wolfram Sang <wsa+renesas@sang-engineering.com>
S: Supported
-F: Documentation/devicetree/bindings/i2c/i2c-emev2.txt
+F: Documentation/devicetree/bindings/i2c/renesas,iic-emev2.txt
F: drivers/i2c/busses/i2c-emev2.c
RENESAS ETHERNET DRIVERS
--
2.11.0
^ permalink raw reply related
* [PATCH v2 3/4] dt-bindings: i2c: riic: Rename bindings documentation file
From: Simon Horman @ 2019-08-09 21:30 UTC (permalink / raw)
To: Wolfram Sang, Chris Brandt
Cc: Rob Herring, Mark Rutland, Magnus Damm, linux-i2c, devicetree,
linux-renesas-soc, Simon Horman
In-Reply-To: <20190809213004.31181-1-horms+renesas@verge.net.au>
Rename the bindings documentation file for RIIC controller
from i2c-riic.txt to renesas,riic.txt.
This is part of an ongoing effort to name bindings documentation files for
Renesas IP blocks consistently, in line with the compat strings they
document.
Cc: Chris Brandt <chris.brandt@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2
* Add review tag
---
.../devicetree/bindings/i2c/{i2c-riic.txt => renesas,riic.txt} | 0
MAINTAINERS | 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)
rename Documentation/devicetree/bindings/i2c/{i2c-riic.txt => renesas,riic.txt} (100%)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-riic.txt b/Documentation/devicetree/bindings/i2c/renesas,riic.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/i2c-riic.txt
rename to Documentation/devicetree/bindings/i2c/renesas,riic.txt
diff --git a/MAINTAINERS b/MAINTAINERS
index b8c1181baea9..fc3ed4fe0ba5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13658,7 +13658,7 @@ F: drivers/i2c/busses/i2c-sh_mobile.c
RENESAS RIIC DRIVER
M: Chris Brandt <chris.brandt@renesas.com>
S: Supported
-F: Documentation/devicetree/bindings/i2c/i2c-riic.txt
+F: Documentation/devicetree/bindings/i2c/renesas,riic.txt
F: drivers/i2c/busses/i2c-riic.c
RENESAS USB PHY DRIVER
--
2.11.0
^ permalink raw reply related
* [PATCH v2 2/4] dt-bindings: i2c: rcar: Rename bindings documentation file
From: Simon Horman @ 2019-08-09 21:30 UTC (permalink / raw)
To: Wolfram Sang, Chris Brandt
Cc: Rob Herring, Mark Rutland, Magnus Damm, linux-i2c, devicetree,
linux-renesas-soc, Simon Horman
In-Reply-To: <20190809213004.31181-1-horms+renesas@verge.net.au>
Rename the bindings documentation file for R-Car I2C controller
from i2c-rcar.txt to renesas,i2c.txt.
This is part of an ongoing effort to name bindings documentation files for
Renesas IP blocks consistently, in line with the compat strings they
document.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2
* Added review tag
* Corrected changelog to refer to renesas,i2c.txt
---
Documentation/devicetree/bindings/i2c/{i2c-rcar.txt => renesas,i2c.txt} | 0
MAINTAINERS | 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)
rename Documentation/devicetree/bindings/i2c/{i2c-rcar.txt => renesas,i2c.txt} (100%)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt b/Documentation/devicetree/bindings/i2c/renesas,i2c.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/i2c-rcar.txt
rename to Documentation/devicetree/bindings/i2c/renesas,i2c.txt
diff --git a/MAINTAINERS b/MAINTAINERS
index 4c8262837da9..b8c1181baea9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13650,7 +13650,7 @@ F: drivers/iio/adc/rcar-gyroadc.c
RENESAS R-CAR I2C DRIVERS
M: Wolfram Sang <wsa+renesas@sang-engineering.com>
S: Supported
-F: Documentation/devicetree/bindings/i2c/i2c-rcar.txt
+F: Documentation/devicetree/bindings/i2c/renesas,i2c.txt
F: Documentation/devicetree/bindings/i2c/renesas,iic.txt
F: drivers/i2c/busses/i2c-rcar.c
F: drivers/i2c/busses/i2c-sh_mobile.c
--
2.11.0
^ permalink raw reply related
* [PATCH v2 1/4] dt-bindings: i2c: sh_mobile: Rename bindings documentation file
From: Simon Horman @ 2019-08-09 21:30 UTC (permalink / raw)
To: Wolfram Sang, Chris Brandt
Cc: Rob Herring, Mark Rutland, Magnus Damm, linux-i2c, devicetree,
linux-renesas-soc, Simon Horman
In-Reply-To: <20190809213004.31181-1-horms+renesas@verge.net.au>
Rename the bindings documentation file for sh_mobile I2C controller
from i2c-sh_mobile.txt to renesas,iic.txt.
This is part of an ongoing effort to name bindings documentation files for
Renesas IP blocks consistently, in line with the compat strings they
document.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
v2
* Add review tag
---
.../devicetree/bindings/i2c/{i2c-sh_mobile.txt => renesas,iic.txt} | 0
MAINTAINERS | 2 +-
2 files changed, 1 insertion(+), 1 deletion(-)
rename Documentation/devicetree/bindings/i2c/{i2c-sh_mobile.txt => renesas,iic.txt} (100%)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt b/Documentation/devicetree/bindings/i2c/renesas,iic.txt
similarity index 100%
rename from Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
rename to Documentation/devicetree/bindings/i2c/renesas,iic.txt
diff --git a/MAINTAINERS b/MAINTAINERS
index 783569e3c4b4..4c8262837da9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13651,7 +13651,7 @@ RENESAS R-CAR I2C DRIVERS
M: Wolfram Sang <wsa+renesas@sang-engineering.com>
S: Supported
F: Documentation/devicetree/bindings/i2c/i2c-rcar.txt
-F: Documentation/devicetree/bindings/i2c/i2c-sh_mobile.txt
+F: Documentation/devicetree/bindings/i2c/renesas,iic.txt
F: drivers/i2c/busses/i2c-rcar.c
F: drivers/i2c/busses/i2c-sh_mobile.c
--
2.11.0
^ permalink raw reply related
* [PATCH v2 0/4] dt-bindings: i2c: renesas: Rename bindings documentation files
From: Simon Horman @ 2019-08-09 21:30 UTC (permalink / raw)
To: Wolfram Sang, Chris Brandt
Cc: Rob Herring, Mark Rutland, Magnus Damm, linux-i2c, devicetree,
linux-renesas-soc, Simon Horman
Rename the bindings documentation file for Renesas I2C controllers.
This is part of an ongoing effort to name bindings documentation files for
Renesas IP blocks consistently, in line with the compat strings they
document.
Based on v5.3-rc1
Changes since v1
* Accumulate review tags
* Correct changelogs
Simon Horman (4):
dt-bindings: i2c: sh_mobile: Rename bindings documentation file
dt-bindings: i2c: rcar: Rename bindings documentation file
dt-bindings: i2c: riic: Rename bindings documentation file
dt-bindings: i2c: i2c-emev2: Rename bindings documentation file
.../devicetree/bindings/i2c/{i2c-rcar.txt => renesas,i2c.txt} | 0
.../bindings/i2c/{i2c-emev2.txt => renesas,iic-emev2.txt} | 0
.../bindings/i2c/{i2c-sh_mobile.txt => renesas,iic.txt} | 0
.../devicetree/bindings/i2c/{i2c-riic.txt => renesas,riic.txt} | 0
MAINTAINERS | 8 ++++----
5 files changed, 4 insertions(+), 4 deletions(-)
rename Documentation/devicetree/bindings/i2c/{i2c-rcar.txt => renesas,i2c.txt} (100%)
rename Documentation/devicetree/bindings/i2c/{i2c-emev2.txt => renesas,iic-emev2.txt} (100%)
rename Documentation/devicetree/bindings/i2c/{i2c-sh_mobile.txt => renesas,iic.txt} (100%)
rename Documentation/devicetree/bindings/i2c/{i2c-riic.txt => renesas,riic.txt} (100%)
--
2.11.0
^ permalink raw reply
* Re: [PATCH] of: Fix of_empty_ranges_quirk()
From: Simon Horman @ 2019-08-09 20:41 UTC (permalink / raw)
To: marek.vasut
Cc: devicetree, Marek Vasut, Rob Herring, Frank Rowand,
linux-renesas-soc
In-Reply-To: <20190809173321.19944-1-marek.vasut@gmail.com>
On Fri, Aug 09, 2019 at 07:33:21PM +0200, marek.vasut@gmail.com wrote:
> From: Marek Vasut <marek.vasut+renesas@gmail.com>
>
> The of_empty_ranges_quirk() returns a mix of boolean and signed integer
> types, which cannot work well. Replace that with boolean only and fix
> usage logic in of_translate_one() -- the check should trigger when the
> ranges are NULL and the quirk is applicable on the hardware.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Frank Rowand <frowand.list@gmail.com>
> Cc: linux-renesas-soc@vger.kernel.org
> To: devicetree@vger.kernel.org
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> drivers/of/address.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/of/address.c b/drivers/of/address.c
> index b492176c0572..ae2819e148b8 100644
> --- a/drivers/of/address.c
> +++ b/drivers/of/address.c
> @@ -616,7 +616,7 @@ static struct of_bus *of_match_bus(struct device_node *np)
> return NULL;
> }
>
> -static int of_empty_ranges_quirk(struct device_node *np)
> +static bool of_empty_ranges_quirk(struct device_node *np)
> {
> if (IS_ENABLED(CONFIG_PPC)) {
> /* To save cycles, we cache the result for global "Mac" setting */
> @@ -631,7 +631,8 @@ static int of_empty_ranges_quirk(struct device_node *np)
> quirk_state =
> of_machine_is_compatible("Power Macintosh") ||
> of_machine_is_compatible("MacRISC");
> - return quirk_state;
> + if (quirk_state > 0)
> + return true;
> }
> return false;
> }
> @@ -662,8 +663,8 @@ static int of_translate_one(struct device_node *parent, struct of_bus *bus,
> * This code is only enabled on powerpc. --gcl
> */
> ranges = of_get_property(parent, rprop, &rlen);
> - if (ranges == NULL && !of_empty_ranges_quirk(parent)) {
> - pr_debug("no ranges; cannot translate\n");
> + if (ranges == NULL && of_empty_ranges_quirk(parent)) {
> + pr_err("no ranges; cannot translate\n");
> return 1;
> }
> if (ranges == NULL || rlen == 0) {
> --
> 2.20.1
>
^ permalink raw reply
* Re: [PATCH v2 2/3] dt-bindings: display/bridge: Add binding for NWL mipi dsi host controller
From: Rob Herring @ 2019-08-09 20:41 UTC (permalink / raw)
To: Guido Günther
Cc: David Airlie, Daniel Vetter, Mark Rutland, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Andrzej Hajda, Neil Armstrong, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, Lee Jones, dri-devel, devicetree,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
linux-kernel@vger.kernel.org
In-Reply-To: <9c906bb6592424acdb1a67447a482e010a113b49.1565367567.git.agx@sigxcpu.org>
On Fri, Aug 9, 2019 at 10:24 AM Guido Günther <agx@sigxcpu.org> wrote:
>
> The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs.
>
> Signed-off-by: Guido Günther <agx@sigxcpu.org>
> ---
> .../bindings/display/bridge/nwl-dsi.yaml | 155 ++++++++++++++++++
> 1 file changed, 155 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
> new file mode 100644
> index 000000000000..5ed8bc4a4d18
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml
> @@ -0,0 +1,155 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/bridge/imx-nwl-dsi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Northwest Logic MIPI-DSI on imx SoCs
> +
> +maintainers:
> + - Guido Gúnther <agx@sigxcpu.org>
> + - Robert Chiras <robert.chiras@nxp.com>
> +
> +description: |
> + NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
> + the SOCs NWL MIPI-DSI host controller.
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - const: fsl,imx8mq-nwl-dsi
Don't need oneOf nor items here for a single possible value:
compatible:
const: fsl,imx8mq-nwl-dsi
Or go ahead and add other compatibles because the 'if' below seems to
indicate you'll have more.
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: DSI core clock
> + - description: RX_ESC clock (used in escape mode)
> + - description: TX_ESC clock (used in escape mode)
> + - description: PHY_REF clock
> +
> + clock-names:
> + items:
> + - const: core
> + - const: rx_esc
> + - const: tx_esc
> + - const: phy_ref
> +
> + phys:
> + maxItems: 1
> + description:
> + A phandle to the phy module representing the DPHY
> +
> + phy-names:
> + items:
> + - const: dphy
> +
> + power-domains:
> + maxItems: 1
> + description:
> + A phandle to the power domain
> +
> + resets:
> + maxItems: 4
> + description:
> + A phandle to the reset controller
Sounds like 4 phandles... This should look similar to 'clocks'.
> +
> + reset-names:
> + items:
> + - const: byte
> + - const: dpi
> + - const: esc
> + - const: pclk
> +
> + mux-sel:
Needs a vendor prefix and will need a $ref to the type.
> + maxItems: 1
> + description:
> + A phandle to the MUX register set
> +
> + port:
> + type: object
> + description:
> + A input put or output port node.
> +
> + ports:
> + type: object
> + description:
> + A node containing DSI input & output port nodes with endpoint
> + definitions as documented in
> + Documentation/devicetree/bindings/graph.txt.
You need to define what port@0 and port@1 are.
> +
> +patternProperties:
> + "^panel@[0-9]+$": true
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - fsl,imx8mq-nwl-dsi
This conditional isn't needed until you have more than one compatible.
> + required:
> + - resets
> + - reset-names
> + - mux-sel
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - clock-names
> + - phys
> + - phy-names
ports should be required.
> +
> +examples:
> + - |
> +
> + mipi_dsi: mipi_dsi@30a00000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx8mq-nwl-dsi";
> + reg = <0x30A00000 0x300>;
> + clocks = <&clk 163>, <&clk 244>, <&clk 245>, <&clk 164>;
> + clock-names = "core", "rx_esc", "tx_esc", "phy_ref";
> + interrupts = <0 34 4>;
> + power-domains = <&pgc_mipi>;
> + resets = <&src 0>, <&src 1>, <&src 2>, <&src 3>;
> + reset-names = "byte", "dpi", "esc", "pclk";
> + mux-sel = <&iomuxc_gpr>;
> + phys = <&dphy>;
> + phy-names = "dphy";
> +
> + panel@0 {
> + compatible = "...";
Needs to be a valid compatible. Also need 'reg' here or drop the unit-address.
> + port@0 {
> + panel_in: endpoint {
> + remote-endpoint = <&mipi_dsi_out>;
> + };
> + };
> + };
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mipi_dsi_in: endpoint {
> + remote-endpoint = <&lcdif_mipi_dsi>;
> + };
> + };
> + port@1 {
> + reg = <1>;
> + mipi_dsi_out: endpoint {
> + remote-endpoint = <&panel_in>;
> + };
> + };
> + };
> + };
> --
> 2.20.1
>
^ permalink raw reply
* Re: [PATCH 1/2] ASoC: fsl_esai: Add compatible string for imx6ull
From: Nicolin Chen @ 2019-08-09 19:58 UTC (permalink / raw)
To: Shengjiu Wang
Cc: timur, Xiubo.Lee, festevam, broonie, alsa-devel, robh+dt,
mark.rutland, linuxppc-dev, linux-kernel, devicetree
In-Reply-To: <1565346467-5769-1-git-send-email-shengjiu.wang@nxp.com>
On Fri, Aug 09, 2019 at 06:27:46PM +0800, Shengjiu Wang wrote:
> Add compatible string for imx6ull, from imx6ull platform,
> the issue of channel swap after xrun is fixed in hardware.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
> sound/soc/fsl/fsl_esai.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/sound/soc/fsl/fsl_esai.c b/sound/soc/fsl/fsl_esai.c
> index 10d2210c91ef..4b4a8e831e9e 100644
> --- a/sound/soc/fsl/fsl_esai.c
> +++ b/sound/soc/fsl/fsl_esai.c
> @@ -920,6 +920,7 @@ static int fsl_esai_remove(struct platform_device *pdev)
> static const struct of_device_id fsl_esai_dt_ids[] = {
> { .compatible = "fsl,imx35-esai", },
> { .compatible = "fsl,vf610-esai", },
> + { .compatible = "fsl,imx6ull-esai", },
> {}
> };
> MODULE_DEVICE_TABLE(of, fsl_esai_dt_ids);
> --
> 2.21.0
>
^ permalink raw reply
* Re: [PATCH 2/2] ASoC: fsl_esai: Add new compatible string for imx6ull
From: Nicolin Chen @ 2019-08-09 19:58 UTC (permalink / raw)
To: Shengjiu Wang
Cc: timur, Xiubo.Lee, festevam, broonie, alsa-devel, robh+dt,
mark.rutland, linuxppc-dev, linux-kernel, devicetree
In-Reply-To: <1565346467-5769-2-git-send-email-shengjiu.wang@nxp.com>
On Fri, Aug 09, 2019 at 06:27:47PM +0800, Shengjiu Wang wrote:
> Add new compatible string "fsl,imx6ull-esai" in the binding document.
>
> Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
> ---
> Documentation/devicetree/bindings/sound/fsl,esai.txt | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/sound/fsl,esai.txt b/Documentation/devicetree/bindings/sound/fsl,esai.txt
> index 5b9914367610..0e6e2166f76c 100644
> --- a/Documentation/devicetree/bindings/sound/fsl,esai.txt
> +++ b/Documentation/devicetree/bindings/sound/fsl,esai.txt
> @@ -7,8 +7,11 @@ other DSPs. It has up to six transmitters and four receivers.
>
> Required properties:
>
> - - compatible : Compatible list, must contain "fsl,imx35-esai" or
> - "fsl,vf610-esai"
> + - compatible : Compatible list, should contain one of the following
> + compatibles:
> + "fsl,imx35-esai",
> + "fsl,vf610-esai",
> + "fsl,imx6ull-esai",
>
> - reg : Offset and length of the register set for the device.
>
> --
> 2.21.0
>
^ permalink raw reply
* Re: [PATCH 7/9] dt-bindings: phy: meson-g12a-usb3-pcie-phy: convert to yaml
From: Martin Blumenstingl @ 2019-08-09 19:55 UTC (permalink / raw)
To: Neil Armstrong
Cc: devicetree, Rob Herring, kishon, robh+dt, linux-amlogic,
linux-arm-kernel
In-Reply-To: <2e6ade0e-175c-e77c-e767-28f4bbfbe575@baylibre.com>
On Fri, Aug 9, 2019 at 9:00 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> Hi,
>
> On 08/08/2019 21:50, Martin Blumenstingl wrote:
> > On Thu, Aug 8, 2019 at 10:54 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
> >>
> >> Now that we have the DT validation in place, let's convert the device tree
> >> bindings for the Amlogic G12A USB3 + PCIE Combo PHY over to a YAML schemas.
> >>
> >> While the original phy bindings specifies phy-supply as required,
> >> the examples and implementations makes it optional, thus phy-supply
> >> is not present in the properties and required lists.
> > nit-pick: the original bindings didn't mention the phy-supply property at all
> > I'm not sure if you have to re-send it, maybe this can be fixed up
> > while applying?
>
> It didn't, but the phy.txt made it mandatory, but was optional in all examples
> and implementation, thus rob asked me to precise it in the commit log.
sorry, I missed that
my Reviewed-by still stands - thanks for pointing it out (again)
^ permalink raw reply
* Re: [PATCH v8 11/21] clk: tegra: clk-dfll: Add suspend and resume support
From: Dmitry Osipenko @ 2019-08-09 18:52 UTC (permalink / raw)
To: Sowjanya Komatineni, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree, rjw, viresh.kumar, linux-pm
In-Reply-To: <9902aa72-3f18-9840-35ad-137293d2e26c@nvidia.com>
09.08.2019 21:33, Sowjanya Komatineni пишет:
>
> On 8/9/19 11:00 AM, Dmitry Osipenko wrote:
>> 09.08.2019 19:39, Sowjanya Komatineni пишет:
>>> On 8/9/19 5:23 AM, Dmitry Osipenko wrote:
>>>> 09.08.2019 2:46, Sowjanya Komatineni пишет:
>>>>> This patch implements DFLL suspend and resume operation.
>>>>>
>>>>> During system suspend entry, CPU clock will switch CPU to safe
>>>>> clock source of PLLP and disables DFLL clock output.
>>>>>
>>>>> DFLL driver suspend confirms DFLL disable state and errors out on
>>>>> being active.
>>>>>
>>>>> DFLL is re-initialized during the DFLL driver resume as it goes
>>>>> through complete reset during suspend entry.
>>>>>
>>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>>> ---
>>>>> drivers/clk/tegra/clk-dfll.c | 56 ++++++++++++++++++++++++++++++
>>>>> drivers/clk/tegra/clk-dfll.h | 2 ++
>>>>> drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 1 +
>>>>> 3 files changed, 59 insertions(+)
>>>>>
>>>>> diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
>>>>> index f8688c2ddf1a..eb298a5d7be9 100644
>>>>> --- a/drivers/clk/tegra/clk-dfll.c
>>>>> +++ b/drivers/clk/tegra/clk-dfll.c
>>>>> @@ -1487,6 +1487,7 @@ static int dfll_init(struct tegra_dfll *td)
>>>>> td->last_unrounded_rate = 0;
>>>>> pm_runtime_enable(td->dev);
>>>>> + pm_runtime_irq_safe(td->dev);
>>>>> pm_runtime_get_sync(td->dev);
>>>>> dfll_set_mode(td, DFLL_DISABLED);
>>>>> @@ -1513,6 +1514,61 @@ static int dfll_init(struct tegra_dfll *td)
>>>>> return ret;
>>>>> }
>>>>> +/**
>>>>> + * tegra_dfll_suspend - check DFLL is disabled
>>>>> + * @dev: DFLL device *
>>>>> + *
>>>>> + * DFLL clock should be disabled by the CPUFreq driver. So, make
>>>>> + * sure it is disabled and disable all clocks needed by the DFLL.
>>>>> + */
>>>>> +int tegra_dfll_suspend(struct device *dev)
>>>>> +{
>>>>> + struct tegra_dfll *td = dev_get_drvdata(dev);
>>>>> +
>>>>> + if (dfll_is_running(td)) {
>>>>> + dev_err(td->dev, "dfll is enabled while shouldn't be\n");
>>>>> + return -EBUSY;
>>>>> + }
>>>>> +
>>>>> + reset_control_assert(td->dvco_rst);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +EXPORT_SYMBOL(tegra_dfll_suspend);
>>>>> +
>>>>> +/**
>>>>> + * tegra_dfll_resume - reinitialize DFLL on resume
>>>>> + * @dev: DFLL instance
>>>>> + *
>>>>> + * DFLL is disabled and reset during suspend and resume.
>>>>> + * So, reinitialize the DFLL IP block back for use.
>>>>> + * DFLL clock is enabled later in closed loop mode by CPUFreq
>>>>> + * driver before switching its clock source to DFLL output.
>>>>> + */
>>>>> +int tegra_dfll_resume(struct device *dev)
>>>>> +{
>>>>> + struct tegra_dfll *td = dev_get_drvdata(dev);
>>>>> +
>>>>> + reset_control_deassert(td->dvco_rst);
>>>> This doesn't look right because I assume that DFLL resetting is
>>>> synchronous and thus clk should be enabled in order for reset to
>>>> propagate inside hardware.
>>>>
>>>>> + pm_runtime_get_sync(td->dev);
>>>> Hence it will be better to remove the above reset_control_deassert() and
>>>> add here:
>>>>
>>>> reset_control_reset(td->dvco_rst);
>>> By the time dfll resume happens, dfll controller clock will already be enabled.
>>>
>>> so doing reset de-assert before pm_runtime seems ok.
>> I don't see what enables the DFLL clock because it should be enabled by the CPUFreq driver
>> on resume from suspend and resume happens after resuming of the DFLL driver.
>
> dvco_rst is part of peripheral clocks and all peripheral clocks are restored by clk-tegra210
> driver which happens before dfll driver resume.
>
> So dfll rst thru part of peripheral clock enable is set prior to dfll reset deassertion
Ah, so that is DVCO resetting and not DFLL, which are different blocks. Looks correct then.
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
^ permalink raw reply
* Re: [PATCH v8 05/21] clk: tegra: pll: Save and restore pll context
From: Sowjanya Komatineni @ 2019-08-09 18:50 UTC (permalink / raw)
To: Dmitry Osipenko, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree, rjw, viresh.kumar, linux-pm
In-Reply-To: <2eecf4ff-802d-7e0e-d971-0257fae4e3a2@gmail.com>
On 8/9/19 10:50 AM, Dmitry Osipenko wrote:
> 09.08.2019 20:39, Sowjanya Komatineni пишет:
>> On 8/9/19 4:33 AM, Dmitry Osipenko wrote:
>>> 09.08.2019 2:46, Sowjanya Komatineni пишет:
>>>> This patch implements save and restore of PLL context.
>>>>
>>>> During system suspend, core power goes off and looses the settings
>>>> of the Tegra CAR controller registers.
>>>>
>>>> So during suspend entry pll context is stored and on resume it is
>>>> restored back along with its state.
>>>>
>>>> Acked-by: Thierry Reding <treding@nvidia.com>
>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>> ---
>>>> drivers/clk/tegra/clk-pll.c | 88 ++++++++++++++++++++++++++++-----------------
>>>> drivers/clk/tegra/clk.h | 2 ++
>>>> 2 files changed, 58 insertions(+), 32 deletions(-)
>>>>
>>>> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
>>>> index 1583f5fc992f..e52add2bbdbb 100644
>>>> --- a/drivers/clk/tegra/clk-pll.c
>>>> +++ b/drivers/clk/tegra/clk-pll.c
>>>> @@ -1008,6 +1008,28 @@ static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,
>>>> return rate;
>>>> }
>>>> +static void tegra_clk_pll_restore_context(struct clk_hw *hw)
>>>> +{
>>>> + struct tegra_clk_pll *pll = to_clk_pll(hw);
>>>> + struct clk_hw *parent = clk_hw_get_parent(hw);
>>>> + unsigned long parent_rate = clk_hw_get_rate(parent);
>>>> + unsigned long rate = clk_hw_get_rate(hw);
>>>> + u32 val;
>>>> +
>>>> + if (clk_pll_is_enabled(hw))
>>>> + return;
>>>> +
>>>> + if (pll->params->set_defaults)
>>>> + pll->params->set_defaults(pll);
>>>> +
>>>> + clk_pll_set_rate(hw, rate, parent_rate);
>>>> +
>>>> + if (!__clk_get_enable_count(hw->clk))
>>> What about orphaned clocks? Is enable_count > 0 for them?
>> There are no orphaned pll clocks.
> Sorry, I meant the "clk_ignore_unused".
clocks with CLK_IGNORE_UNUSED are taken care by clk driver.
clk_disable_unused checks for clocks with this flag and if they are not
enabled it will enable them.
So by the time suspend happens enable_count is > 0
^ permalink raw reply
* Re: [PATCH v8 00/14] Rockchip ISP1 Driver
From: Manivannan Sadhasivam @ 2019-08-09 18:45 UTC (permalink / raw)
To: Helen Koike
Cc: linux-rockchip, devicetree, eddie.cai.linux, mchehab, heiko,
jacob2.chen, jeffy.chen, zyc, linux-kernel, tfiga, hans.verkuil,
laurent.pinchart, sakari.ailus, kernel, ezequiel, linux-media,
linux-arm-kernel, zhengsq
In-Reply-To: <20190730184256.30338-1-helen.koike@collabora.com>
Hi Helen,
On Fri, Aug 09, 2019 at 03:40:02PM -0300, Helen Koike wrote:
> Hello,
>
> I'm re-sending a new version of ISP(Camera) v4l2 driver for rockchip
> rk3399 SoC.
>
> I didn't change much from the last version, just applying the
> suggestions made in the previous one.
>
> This patchset is also available at:
> https://gitlab.collabora.com/koike/linux/tree/rockchip/isp/v8
>
> Libcamera patched to work with this version:
> https://gitlab.collabora.com/koike/libcamera
> (also sent to the mailing list)
>
> I tested on the rockpi 4 with a rpi v1.3 sensor and also with the
> Scarlet Chromebook.
>
I just tested this patchset on Rock960 but getting below error while
configuring media link:
root@linaro-alip:~# media-ctl -p /dev/media0 -v
Opening media device /dev/media0
Enumerating entities
looking up device: 81:4
looking up device: 81:0
looking up device: 81:1
looking up device: 81:2
looking up device: 81:3
looking up device: 81:5
Found 6 entities
Enumerating pads and links
*** Error in `media-ctl': munmap_chunk(): invalid pointer: 0x01ce44d0 ***
Aborted
Here is the change I did for Rock960:
https://pastebin.ubuntu.com/p/CmdcqJ7bsJ/
Did I miss anything?
Thanks,
Mani
> Known issues (same as in v7):
> -------------
> - Reloading the module doesn't work (there is some missing cleanup when
> unloading)
> - When capturing in bayer format, changing the size doesn't seem to
> affect the image.
> - crop needs more tests
> - v4l2-compliance error:
> fail: v4l2-test-controls.cpp(824): subscribe event for control 'Image Processing Controls' failed
> test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
> It seems that if controls are supported, v4l2-compliance says that
> controls of type 'Image Processing Controls' are mandatory, is this
> correct?
> - It seems there are still some issues with interrupts, but I couldn't
> isolate them yet.
>
> Previous changelog:
> -------------------
>
> changes in V6:
> - add mipi txrx phy support
> - remove bool and enum from uapi header
> - add buf_prepare op
> - correct some spelling problems
> - return all queued buffers when starting stream failed
>
> changes in V5: Sync with local changes,
> - fix the SP height limit
> - speed up the second stream capture
> - the second stream can't force sync for rsz when start/stop streaming
> - add frame id to param vb2 buf
> - enable luminance maximum threshold
>
> changes in V4:
> - fix some bugs during development
> - move quantization settings to rkisp1 subdev
> - correct some spelling problems
> - describe ports in dt-binding documents
>
> changes in V3:
> - add some comments
> - fix wrong use of v4l2_async_subdev_notifier_register
> - optimize two paths capture at a time
> - remove compose
> - re-struct headers
> - add a tmp wiki page: http://opensource.rock-chips.com/wiki_Rockchip-isp1
>
> changes in V2:
> mipi-phy:
> - use async probing
> - make it be a child device of the GRF
> isp:
> - add dummy buffer
> - change the way to get bus configuration, which make it possible to
> add parallel sensor support in the future(without mipi-phy driver).
>
> ------------------
>
> Changes in v8:
> - Add SPDX in the header
> - Remove emacs configs
> - Fix doc style
> - Remove boiler plate license text
>
> Changes in v7:
> - s/IPU3/RK_ISP1
> - s/correspond/corresponding
> - s/use/uses
> - s/docuemnt/document
> - Fix checkpatch errors (lines over 80 and SPDX)
> - Add TODO to improve docs
> - Migrate dphy specific code from
> drivers/media/platform/rockchip/isp1/mipi_dphy_sy.c
> to drivers/phy/rockchip/phy-rockchip-dphy.c
> - Drop support for rk3288
> - Drop support for dphy txrx
> - code styling and checkpatch fixes
> - fixed warning because of unknown entity type
> - fixed v4l2-compliance errors regarding rkisp1 formats, try formats
> and default values
> - fix typo riksp1/rkisp1
> - redesign: remove mipi/csi subdevice, sensors connect directly to the
> isp subdevice in the media topology now. As a consequence, remove the
> hack in mipidphy_g_mbus_config() where information from the sensor was
> being propagated through the topology.
> - From the old dphy:
> * cache get_remote_sensor() in s_stream
> * use V4L2_CID_PIXEL_RATE instead of V4L2_CID_LINK_FREQ
> - Replace stream state with a boolean
> - code styling and checkpatch fixes
> - fix stop_stream (return after calling stop, do not reenable the stream)
> - fix rkisp1_isp_sd_get_selection when V4L2_SUBDEV_FORMAT_TRY is set
> - fix get format in output (isp_sd->out_fmt.mbus_code was being ignored)
> - s/intput/input
> - remove #define sd_to_isp_sd(_sd), add a static inline as it will be
> reused by the capture
> - s/strlcpy/strscpy
> - sort out the locks in isp stats
> - code styling and checkpatch fixes
> - s/strlcpy/strscpy
> - s/strcpy/strscpy
> - fix config lsc error
> LSC data table size is 17x17, but when configuring data to ISP,
> should be aligned to 18x17. That means every last data of last
> line should be filled with 0, and not filled with the data of
> next line.
> - Update new ISP parameters immediately
> For those sub modules that have shadow registers in core isp, the
> new programing parameters would not be active if both
> CIF_ISP_CTRL_ISP_CFG_UPD_PERMANENT and CFG_UPD are not set. Now
> we configure CFG_UPD to force update the shadow registers when new
> ISP parameters are configured.
> - fix some ISP parameters config error
> Some ISP parameter config functions may override the old enable
> bit value, because the enable bits of these modules are in the
> same registers with parameters. So we should save the old enable
> bits firstly.
> - code styling and checkpatch fixes
> - s/strlcpy/strscpy
> - Fix v4l2-compliance issues:
> * remove input ioctls
> media api can be used to define the topology, this input api is not
> required. Besides it, if an input is enumerated, v4l2-compliance is not
> happy with G_FMT returning the default colorspace instead of something
> more specific.
> * return the pixelformat to the userspace
> G_/S_/TRY_ FORMAT should return a valid pixelformat to the user, even if
> the user gave an invalid one
> * add missing default colorspace and ycbcr
> * fix wrong pixformat in mp_fmts[] table
> * add buf type check in s_/g_selection
> * queue_setup - check sizes
> * normalize bus_info name
> * fix field any v4l2-compliance -s complain - set field none
> when streaming
> - Fix compiling error: s/vidioc_enum_fmt_vid_cap_mplane/vidioc_enum_fmt_vid_cap
> - Replace stream state with a boolean
> The rkisp1_state enum consists only of 3 entries, where 1 is completely
> unused and the other two respectively mean not streaming or streaming.
> Replace it with a boolean called "streaming".
> - Simplify MI interrupt handling
> Rather than adding unnecessary indirection, just use stream index to
> handle MI interrupt enable/disable/clear, since the stream index matches
> the order of bits now, thanks to previous patch. While at it, remove
> some dead code.
> - code styling and checkpatch fixes
> - add link_validate: don't allow a link with bayer/non-bayer mismatch
> - VIDEO_ROCKCHIP_ISP1 selects VIDEOBUF2_VMALLOC
> - add PHY_ROCKCHIP_DPHY as a dependency for VIDEO_ROCKCHIP_ISP1
> - Fix compilation and runtime errors due to bitrotting
> The code has bit-rotten since March 2018, fix compilation errors.
> The new V4L2 async notifier API requires notifiers to be initialized by
> a call to v4l2_async_notifier_init() before being used, do so.
> - Add missing module device table
> - use clk_bulk framework
> - add missing notifiers cleanups
> - s/strlcpy/strscpy
> - normalize bus_info name
> - fix s_stream error path, stream_cnt wans't being decremented properly
> - use devm_platform_ioremap_resource() helper
> - s/deice/device
> - redesign: remove mipi/csi subdevice, sensors connect directly to the
> isp subdevice in the media topology now.
> - remove "saved_state" member from rkisp1_stream struct
> - Reverse the order of MIs
> - Simplify MI interrupt handling
> Rather than adding unnecessary indirection, just use stream index to
> handle MI interrupt enable/disable/clear, since the stream index matches
> the order of bits now, thanks to previous patch. While at it, remove
> some dead code.
> - code styling and checkpatch fixes
> - update document with new design and tested example
> - updated doc with new design and tested example
> - add phy properties
> - add ports
> - add phy-cells
>
> Helen Koike (1):
> MAINTAINERS: add entry for Rockchip ISP1 driver
>
> Jacob Chen (9):
> media: doc: add document for rkisp1 meta buffer format
> media: rkisp1: add Rockchip MIPI Synopsys DPHY driver
> media: rkisp1: add Rockchip ISP1 subdev driver
> media: rkisp1: add ISP1 statistics driver
> media: rkisp1: add ISP1 params driver
> media: rkisp1: add capture device driver
> media: rkisp1: add rockchip isp1 core driver
> dt-bindings: Document the Rockchip ISP1 bindings
> dt-bindings: Document the Rockchip MIPI RX D-PHY bindings
>
> Jeffy Chen (1):
> media: rkisp1: Add user space ABI definitions
>
> Shunqian Zheng (3):
> media: videodev2.h, v4l2-ioctl: add rkisp1 meta buffer format
> arm64: dts: rockchip: add isp0 node for rk3399
> arm64: dts: rockchip: add rx0 mipi-phy for rk3399
>
> .../bindings/media/rockchip-isp1.txt | 71 +
> .../bindings/media/rockchip-mipi-dphy.txt | 38 +
> Documentation/media/uapi/v4l/meta-formats.rst | 2 +
> .../uapi/v4l/pixfmt-meta-rkisp1-params.rst | 23 +
> .../uapi/v4l/pixfmt-meta-rkisp1-stat.rst | 22 +
> MAINTAINERS | 8 +
> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 36 +
> drivers/media/platform/Kconfig | 12 +
> drivers/media/platform/Makefile | 1 +
> drivers/media/platform/rockchip/isp1/Makefile | 7 +
> .../media/platform/rockchip/isp1/capture.c | 1754 +++++++++++++++++
> .../media/platform/rockchip/isp1/capture.h | 164 ++
> drivers/media/platform/rockchip/isp1/common.h | 101 +
> drivers/media/platform/rockchip/isp1/dev.c | 675 +++++++
> drivers/media/platform/rockchip/isp1/dev.h | 97 +
> .../media/platform/rockchip/isp1/isp_params.c | 1604 +++++++++++++++
> .../media/platform/rockchip/isp1/isp_params.h | 50 +
> .../media/platform/rockchip/isp1/isp_stats.c | 508 +++++
> .../media/platform/rockchip/isp1/isp_stats.h | 60 +
> drivers/media/platform/rockchip/isp1/regs.c | 223 +++
> drivers/media/platform/rockchip/isp1/regs.h | 1525 ++++++++++++++
> drivers/media/platform/rockchip/isp1/rkisp1.c | 1286 ++++++++++++
> drivers/media/platform/rockchip/isp1/rkisp1.h | 111 ++
> drivers/media/v4l2-core/v4l2-ioctl.c | 2 +
> drivers/phy/rockchip/Kconfig | 8 +
> drivers/phy/rockchip/Makefile | 1 +
> drivers/phy/rockchip/phy-rockchip-dphy.c | 408 ++++
> include/uapi/linux/rkisp1-config.h | 816 ++++++++
> include/uapi/linux/videodev2.h | 4 +
> 29 files changed, 9617 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/rockchip-isp1.txt
> create mode 100644 Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt
> create mode 100644 Documentation/media/uapi/v4l/pixfmt-meta-rkisp1-params.rst
> create mode 100644 Documentation/media/uapi/v4l/pixfmt-meta-rkisp1-stat.rst
> create mode 100644 drivers/media/platform/rockchip/isp1/Makefile
> create mode 100644 drivers/media/platform/rockchip/isp1/capture.c
> create mode 100644 drivers/media/platform/rockchip/isp1/capture.h
> create mode 100644 drivers/media/platform/rockchip/isp1/common.h
> create mode 100644 drivers/media/platform/rockchip/isp1/dev.c
> create mode 100644 drivers/media/platform/rockchip/isp1/dev.h
> create mode 100644 drivers/media/platform/rockchip/isp1/isp_params.c
> create mode 100644 drivers/media/platform/rockchip/isp1/isp_params.h
> create mode 100644 drivers/media/platform/rockchip/isp1/isp_stats.c
> create mode 100644 drivers/media/platform/rockchip/isp1/isp_stats.h
> create mode 100644 drivers/media/platform/rockchip/isp1/regs.c
> create mode 100644 drivers/media/platform/rockchip/isp1/regs.h
> create mode 100644 drivers/media/platform/rockchip/isp1/rkisp1.c
> create mode 100644 drivers/media/platform/rockchip/isp1/rkisp1.h
> create mode 100644 drivers/phy/rockchip/phy-rockchip-dphy.c
> create mode 100644 include/uapi/linux/rkisp1-config.h
>
> --
> 2.22.0
>
>
> --
> To unsubscribe, send mail to kernel-unsubscribe@lists.collabora.co.uk.
>
^ permalink raw reply
* Re: [PATCH v8 14/21] clk: tegra210: Add suspend and resume support
From: Sowjanya Komatineni @ 2019-08-09 18:40 UTC (permalink / raw)
To: Dmitry Osipenko, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree, rjw, viresh.kumar, linux-pm
In-Reply-To: <aa823801-00c7-df88-0f63-45338bffa854@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 8669 bytes --]
On 8/9/19 11:18 AM, Dmitry Osipenko wrote:
> 09.08.2019 19:19, Sowjanya Komatineni пишет:
>> On 8/9/19 6:56 AM, Dmitry Osipenko wrote:
>>> 09.08.2019 2:46, Sowjanya Komatineni пишет:
>>>> This patch adds support for clk: tegra210: suspend-resume.
>>>>
>>>> All the CAR controller settings are lost on suspend when core
>>>> power goes off.
>>>>
>>>> This patch has implementation for saving and restoring all PLLs
>>>> and clocks context during system suspend and resume to have the
>>>> clocks back to same state for normal operation.
>>>>
>>>> Clock driver suspend and resume are registered as syscore_ops as clocks
>>>> restore need to happen before the other drivers resume to have all their
>>>> clocks back to the same state as before suspend.
>>>>
>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>> ---
>>>> drivers/clk/tegra/clk-tegra210.c | 103 +++++++++++++++++++++++++++++++++++++--
>>>> drivers/clk/tegra/clk.c | 64 ++++++++++++++++++++++++
>>>> drivers/clk/tegra/clk.h | 3 ++
>>>> 3 files changed, 166 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
>>>> index 998bf60b219a..8dd6f4f4debb 100644
>>>> --- a/drivers/clk/tegra/clk-tegra210.c
>>>> +++ b/drivers/clk/tegra/clk-tegra210.c
>>>> @@ -9,13 +9,13 @@
>>>> #include <linux/clkdev.h>
>>>> #include <linux/of.h>
>>>> #include <linux/of_address.h>
>>>> +#include <linux/syscore_ops.h>
>>>> #include <linux/delay.h>
>>>> #include <linux/export.h>
>>>> #include <linux/mutex.h>
>>>> #include <linux/clk/tegra.h>
>>>> #include <dt-bindings/clock/tegra210-car.h>
>>>> #include <dt-bindings/reset/tegra210-car.h>
>>>> -#include <linux/iopoll.h>
>>>> #include <linux/sizes.h>
>>>> #include <soc/tegra/pmc.h>
>>>> @@ -220,11 +220,15 @@
>>>> #define CLK_M_DIVISOR_SHIFT 2
>>>> #define CLK_M_DIVISOR_MASK 0x3
>>>> +#define CLK_MASK_ARM 0x44
>>>> +#define MISC_CLK_ENB 0x48
>>>> +
>>>> #define RST_DFLL_DVCO 0x2f4
>>>> #define DVFS_DFLL_RESET_SHIFT 0
>>>> #define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8
>>>> #define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac
>>>> +#define CPU_SOFTRST_CTRL 0x380
>>>> #define LVL2_CLK_GATE_OVRA 0xf8
>>>> #define LVL2_CLK_GATE_OVRC 0x3a0
>>>> @@ -2825,6 +2829,7 @@ static int tegra210_enable_pllu(void)
>>>> struct tegra_clk_pll_freq_table *fentry;
>>>> struct tegra_clk_pll pllu;
>>>> u32 reg;
>>>> + int ret;
>>>> for (fentry = pll_u_freq_table; fentry->input_rate; fentry++) {
>>>> if (fentry->input_rate == pll_ref_freq)
>>>> @@ -2853,9 +2858,14 @@ static int tegra210_enable_pllu(void)
>>>> reg |= PLL_ENABLE;
>>>> writel(reg, clk_base + PLLU_BASE);
>>>> - readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg,
>>>> - reg & PLL_BASE_LOCK, 2, 1000);
>>>> - if (!(reg & PLL_BASE_LOCK)) {
>>>> + /*
>>>> + * During clocks resume, same PLLU init and enable sequence get
>>>> + * executed. So, readx_poll_timeout_atomic can't be used here as it
>>>> + * uses ktime_get() and timekeeping resume doesn't happen by that
>>>> + * time. So, using tegra210_wait_for_mask for PLL LOCK.
>>>> + */
>>>> + ret = tegra210_wait_for_mask(&pllu, PLLU_BASE, PLL_BASE_LOCK);
>>>> + if (ret) {
>>>> pr_err("Timed out waiting for PLL_U to lock\n");
>>>> return -ETIMEDOUT;
>>>> }
>>>> @@ -3288,6 +3298,84 @@ static void tegra210_disable_cpu_clock(u32 cpu)
>>>> }
>>>> #ifdef CONFIG_PM_SLEEP
>>>> +/*
>>>> + * This array lists mask values for each peripheral clk bank
>>>> + * to mask out reserved bits during the clocks state restore
>>>> + * on SC7 resume to prevent accidental writes to these reserved
>>>> + * bits.
>>>> + */
>>>> +static u32 periph_clk_rsvd_mask[TEGRA210_CAR_BANK_COUNT] = {
>>> Should be more natural to have a "valid_mask" instead of "rsvd_mask".
>>>
>>> What's actually wrong with touching of the reserved bits? They must be NO-OP.. or the
>>> reserved bits are actually some kind of "secret" bits? If those bits have some use-case
>>> outside of Silicon HW (like FPGA simulation), then this doesn't matter for upstream and you
>>> have to keep the workaround locally in the downstream kernel or whatever.
>> Will rename as valid_mask.
>>
>> some bits in these registers are undefined and is not good to write to these bits as they
>> can cause pslverr.
> Okay, it should be explained in the comment.
>
> Is it possible to disable trapping of changing the undefined bits?
No its internal to design
>
>>>> + 0x23282006,
>>>> + 0x782e0c18,
>>>> + 0x0c012c05,
>>>> + 0x003e7304,
>>>> + 0x86c04800,
>>>> + 0xc0199000,
>>>> + 0x03e03800,
>>>> +};
>>>> +
>>>> +#define car_readl(_base, _off) readl_relaxed(clk_base + (_base) + ((_off) * 4))
>>>> +#define car_writel(_val, _base, _off) \
>>>> + writel_relaxed(_val, clk_base + (_base) + ((_off) * 4))
>>>> +
>>>> +static u32 spare_reg_ctx, misc_clk_enb_ctx, clk_msk_arm_ctx;
>>>> +static u32 cpu_softrst_ctx[3];
>>>> +
>>>> +static int tegra210_clk_suspend(void)
>>>> +{
>>>> + unsigned int i;
>>>> +
>>>> + clk_save_context();
>>>> +
>>>> + /*
>>>> + * Save the bootloader configured clock registers SPARE_REG0,
>>>> + * MISC_CLK_ENB, CLK_MASK_ARM, CPU_SOFTRST_CTRL.
>>>> + */
>>>> + spare_reg_ctx = readl_relaxed(clk_base + SPARE_REG0);
>>>> + misc_clk_enb_ctx = readl_relaxed(clk_base + MISC_CLK_ENB);
>>>> + clk_msk_arm_ctx = readl_relaxed(clk_base + CLK_MASK_ARM);
>>>> +
>>>> + for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++)
>>>> + cpu_softrst_ctx[i] = car_readl(CPU_SOFTRST_CTRL, i);
>>>> +
>>>> + tegra_clk_periph_suspend();
>>>> + return 0;
>>>> +}
>>>> +
>>>> +static void tegra210_clk_resume(void)
>>>> +{
>>>> + unsigned int i;
>>>> +
>>>> + tegra_clk_osc_resume(clk_base);
>>>> +
>>>> + /*
>>>> + * Restore the bootloader configured clock registers SPARE_REG0,
>>>> + * MISC_CLK_ENB, CLK_MASK_ARM, CPU_SOFTRST_CTRL from saved context.
>>>> + */
>>>> + writel_relaxed(spare_reg_ctx, clk_base + SPARE_REG0);
>>>> + writel_relaxed(misc_clk_enb_ctx, clk_base + MISC_CLK_ENB);
>>>> + writel_relaxed(clk_msk_arm_ctx, clk_base + CLK_MASK_ARM);
>>>> +
>>>> + for (i = 0; i < ARRAY_SIZE(cpu_softrst_ctx); i++)
>>>> + car_writel(cpu_softrst_ctx[i], CPU_SOFTRST_CTRL, i);
>>>> +
>>>> + fence_udelay(5, clk_base);
>>>> +
>>>> + /* enable all the clocks before changing the clock sources */
>>>> + tegra_clk_periph_force_on(periph_clk_rsvd_mask);
>>> Why clocks need to be enabled before changing the sources?
>> To prevent glitchless frequency switch, Tegra clock programming recommended sequence is to
>> change MUX control or divisor or both with the clocks running.
> This should be explained in the comment.
>
>> Actual state of clocks before suspend are restored later after all PLL's and peripheral
>> clocks are restored.
>>
>>>> + /* wait for all writes to happen to have all the clocks enabled */
>>>> + wmb();
>>> fence_udelay() has exactly the same barrier at the very beginning of readl(), no need to
>>> duplicate it here.
> Actually, readl does the rmb() and it should be a more correct variant of fencing because it
> actually ensures that the write reached hardware. I suppose that something like fence_udelay
> should be used for the pinctrl as well.
>
>>>> + fence_udelay(2, clk_base);
>>>> +
>>>> + /* restore PLLs and all peripheral clock rates */
>>>> + tegra210_init_pllu();
>>> Why USB PLL need to be restored at first?
>> USB PLL restore is independent to all other clocks restore. So this can be done either
>> before clk_restore_context or even after.
> Then why not to implement restore_context for PLLU?
pllu is registered as fixed_rate clock and we using clk core
clk_register_fixed_rate which uses clk_fixed_rate_ops from the same
generic clk-fixed-rate driver.
Also pllu init happens in the same clk-tegra210, so invoking it during
resume which is the same sequence needed during resume as well.
>>>> + clk_restore_context();
>>>> +
>>>> + /* restore all peripheral clocks enable and reset state */
>>>> + tegra_clk_periph_resume();
>>>> +}
>>> [snip]
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^ permalink raw reply
* Re: [PATCH v8 11/21] clk: tegra: clk-dfll: Add suspend and resume support
From: Sowjanya Komatineni @ 2019-08-09 18:33 UTC (permalink / raw)
To: Dmitry Osipenko, thierry.reding, jonathanh, tglx, jason,
marc.zyngier, linus.walleij, stefan, mark.rutland
Cc: pdeschrijver, pgaikwad, sboyd, linux-clk, linux-gpio, jckuo,
josephl, talho, linux-tegra, linux-kernel, mperttunen, spatra,
robh+dt, devicetree, rjw, viresh.kumar, linux-pm
In-Reply-To: <84a0d46a-bca2-1000-a2a6-8890ee702dd3@gmail.com>
On 8/9/19 11:00 AM, Dmitry Osipenko wrote:
> 09.08.2019 19:39, Sowjanya Komatineni пишет:
>> On 8/9/19 5:23 AM, Dmitry Osipenko wrote:
>>> 09.08.2019 2:46, Sowjanya Komatineni пишет:
>>>> This patch implements DFLL suspend and resume operation.
>>>>
>>>> During system suspend entry, CPU clock will switch CPU to safe
>>>> clock source of PLLP and disables DFLL clock output.
>>>>
>>>> DFLL driver suspend confirms DFLL disable state and errors out on
>>>> being active.
>>>>
>>>> DFLL is re-initialized during the DFLL driver resume as it goes
>>>> through complete reset during suspend entry.
>>>>
>>>> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
>>>> ---
>>>> drivers/clk/tegra/clk-dfll.c | 56 ++++++++++++++++++++++++++++++
>>>> drivers/clk/tegra/clk-dfll.h | 2 ++
>>>> drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 1 +
>>>> 3 files changed, 59 insertions(+)
>>>>
>>>> diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c
>>>> index f8688c2ddf1a..eb298a5d7be9 100644
>>>> --- a/drivers/clk/tegra/clk-dfll.c
>>>> +++ b/drivers/clk/tegra/clk-dfll.c
>>>> @@ -1487,6 +1487,7 @@ static int dfll_init(struct tegra_dfll *td)
>>>> td->last_unrounded_rate = 0;
>>>> pm_runtime_enable(td->dev);
>>>> + pm_runtime_irq_safe(td->dev);
>>>> pm_runtime_get_sync(td->dev);
>>>> dfll_set_mode(td, DFLL_DISABLED);
>>>> @@ -1513,6 +1514,61 @@ static int dfll_init(struct tegra_dfll *td)
>>>> return ret;
>>>> }
>>>> +/**
>>>> + * tegra_dfll_suspend - check DFLL is disabled
>>>> + * @dev: DFLL device *
>>>> + *
>>>> + * DFLL clock should be disabled by the CPUFreq driver. So, make
>>>> + * sure it is disabled and disable all clocks needed by the DFLL.
>>>> + */
>>>> +int tegra_dfll_suspend(struct device *dev)
>>>> +{
>>>> + struct tegra_dfll *td = dev_get_drvdata(dev);
>>>> +
>>>> + if (dfll_is_running(td)) {
>>>> + dev_err(td->dev, "dfll is enabled while shouldn't be\n");
>>>> + return -EBUSY;
>>>> + }
>>>> +
>>>> + reset_control_assert(td->dvco_rst);
>>>> +
>>>> + return 0;
>>>> +}
>>>> +EXPORT_SYMBOL(tegra_dfll_suspend);
>>>> +
>>>> +/**
>>>> + * tegra_dfll_resume - reinitialize DFLL on resume
>>>> + * @dev: DFLL instance
>>>> + *
>>>> + * DFLL is disabled and reset during suspend and resume.
>>>> + * So, reinitialize the DFLL IP block back for use.
>>>> + * DFLL clock is enabled later in closed loop mode by CPUFreq
>>>> + * driver before switching its clock source to DFLL output.
>>>> + */
>>>> +int tegra_dfll_resume(struct device *dev)
>>>> +{
>>>> + struct tegra_dfll *td = dev_get_drvdata(dev);
>>>> +
>>>> + reset_control_deassert(td->dvco_rst);
>>> This doesn't look right because I assume that DFLL resetting is
>>> synchronous and thus clk should be enabled in order for reset to
>>> propagate inside hardware.
>>>
>>>> + pm_runtime_get_sync(td->dev);
>>> Hence it will be better to remove the above reset_control_deassert() and
>>> add here:
>>>
>>> reset_control_reset(td->dvco_rst);
>> By the time dfll resume happens, dfll controller clock will already be enabled.
>>
>> so doing reset de-assert before pm_runtime seems ok.
> I don't see what enables the DFLL clock because it should be enabled by the CPUFreq driver
> on resume from suspend and resume happens after resuming of the DFLL driver.
dvco_rst is part of peripheral clocks and all peripheral clocks are
restored by clk-tegra210 driver which happens before dfll driver resume.
So dfll rst thru part of peripheral clock enable is set prior to dfll
reset deassertion
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