* Re: [linux-sunxi] [PATCH v5 3/3] arm64: defconfig: Enable Sun4i SPDIF module
From: Chen-Yu Tsai @ 2019-08-12 6:37 UTC (permalink / raw)
To: Clément Péron
Cc: devicetree, Maxime Ripard, linux-kernel, linux-sunxi, Rob Herring,
linux-arm-kernel
In-Reply-To: <20190811203144.5999-4-peron.clem@gmail.com>
On Mon, Aug 12, 2019 at 4:32 AM Clément Péron <peron.clem@gmail.com> wrote:
>
> Allwinner A64 and H6 use the Sun4i SPDIF driver.
>
> Enable this to allow a proper support.
>
> Signed-off-by: Clément Péron <peron.clem@gmail.com>
Applied. Thanks.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [linux-sunxi] [PATCH v5 1/3] arm64: dts: allwinner: Add SPDIF node for Allwinner H6
From: Chen-Yu Tsai @ 2019-08-12 6:34 UTC (permalink / raw)
To: Clément Péron
Cc: Chen-Yu Tsai, Maxime Ripard, Rob Herring, linux-arm-kernel,
devicetree, linux-kernel, linux-sunxi
In-Reply-To: <CAGb2v67T3h_KTVZ20NVWNd78xqCa2ZhYiCJr4oOwYjUM3OaZXA@mail.gmail.com>
On Mon, Aug 12, 2019 at 12:52 PM Chen-Yu Tsai <wens@kernel.org> wrote:
>
> Hi,
>
> On Mon, Aug 12, 2019 at 4:31 AM Clément Péron <peron.clem@gmail.com> wrote:
> >
> > The Allwinner H6 has a SPDIF controller called OWA (One Wire Audio).
> >
> > Only one pinmuxing is available so set it as default.
> >
> > Signed-off-by: Clément Péron <peron.clem@gmail.com>
> > ---
> > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 38 ++++++++++++++++++++
> > 1 file changed, 38 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > index 7628a7c83096..677eb374678d 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > @@ -83,6 +83,24 @@
> > method = "smc";
> > };
> >
> > + sound-spdif {
> > + compatible = "simple-audio-card";
> > + simple-audio-card,name = "sun50i-h6-spdif";
> > +
> > + simple-audio-card,cpu {
> > + sound-dai = <&spdif>;
> > + };
> > +
> > + simple-audio-card,codec {
> > + sound-dai = <&spdif_out>;
> > + };
> > + };
> > +
> > + spdif_out: spdif-out {
> > + #sound-dai-cells = <0>;
> > + compatible = "linux,spdif-dit";
> > + };
> > +
>
> We've always had this part in the board dts. It isn't relevant to boards
> that don't have SPDIF output.
>
> Also, not so relevant here, but there are different simple sound card
> constructs. Some support multiple audio streams with dynamic PCM routing.
> How these are configured really depends on what interfaces are usable.
>
> So keeping this at the board level is IMO a better choice.
Forgot to mention. Both patches and all parts in this patch are OK. It's
just the parts the need to be moved.
> ChenYu
>
>
> > timer {
> > compatible = "arm,armv8-timer";
> > interrupts = <GIC_PPI 13
> > @@ -282,6 +300,11 @@
> > bias-pull-up;
> > };
> >
> > + spdif_tx_pin: spdif-tx-pin {
> > + pins = "PH7";
> > + function = "spdif";
> > + };
> > +
> > uart0_ph_pins: uart0-ph-pins {
> > pins = "PH0", "PH1";
> > function = "uart0";
> > @@ -411,6 +434,21 @@
> > };
> > };
> >
> > + spdif: spdif@5093000 {
> > + #sound-dai-cells = <0>;
> > + compatible = "allwinner,sun50i-h6-spdif";
> > + reg = <0x05093000 0x400>;
> > + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
> > + clock-names = "apb", "spdif";
> > + resets = <&ccu RST_BUS_SPDIF>;
> > + dmas = <&dma 2>;
> > + dma-names = "tx";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&spdif_tx_pin>;
> > + status = "disabled";
> > + };
> > +
> > usb2otg: usb@5100000 {
> > compatible = "allwinner,sun50i-h6-musb",
> > "allwinner,sun8i-a33-musb";
> > --
> > 2.20.1
> >
> > --
> > You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> > To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20190811203144.5999-2-peron.clem%40gmail.com.
^ permalink raw reply
* Re: [PATCH] dt-bindings: mfd: rn5t618: Document optional property system-power-controller
From: Lee Jones @ 2019-08-12 6:25 UTC (permalink / raw)
To: Jonathan Neuschäfer
Cc: devicetree, Rob Herring, Mark Rutland, linux-kernel
In-Reply-To: <20190808183924.GB1966@latitude>
On Thu, 08 Aug 2019, Jonathan Neuschäfer wrote:
> On Fri, Feb 01, 2019 at 09:24:11AM +0000, Lee Jones wrote:
> > On Tue, 29 Jan 2019, Jonathan Neuschäfer wrote:
> >
> > > The RN5T618 family of PMICs can be used as system management
> > > controllers, in which case they handle poweroff and restart. Document
> > > this capability by referring to the corresponding generic DT binding.
> > >
> > > Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
> > > ---
> > > Documentation/devicetree/bindings/mfd/rn5t618.txt | 5 +++++
> > > 1 file changed, 5 insertions(+)
> >
> > Applied, thanks.
>
> Hi,
>
> apparently this patch got lost somehow (I can't find it in mainline or
> -next). Should I resend it?
Yes, it appears that it did.
I've applied it again.
--
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* RE: [PATCH v9 5/6] usb:cdns3 Add Cadence USB3 DRD Driver
From: Felipe Balbi @ 2019-08-12 5:24 UTC (permalink / raw)
To: Pawel Laszczak, devicetree@vger.kernel.org
Cc: gregkh@linuxfoundation.org, linux-usb@vger.kernel.org,
hdegoede@redhat.com, heikki.krogerus@linux.intel.com,
robh+dt@kernel.org, rogerq@ti.com, linux-kernel@vger.kernel.org,
jbergsagel@ti.com, nsekhar@ti.com, nm@ti.com, Suresh Punnoose,
peter.chen@nxp.com, Jayshri Dajiram Pawar, Rahul Kumar
In-Reply-To: <BYAPR07MB4709B0A4FADFB76183D651DCDDD10@BYAPR07MB4709.namprd07.prod.outlook.com>
Hi,
Pawel Laszczak <pawell@cadence.com> writes:
> Hi,
>
>>
>>Pawel Laszczak <pawell@cadence.com> writes:
>>>>> +static int cdns3_gadget_start(struct cdns3 *cdns)
>>>>> +{
>>>>> + struct cdns3_device *priv_dev;
>>>>> + u32 max_speed;
>>>>> + int ret;
>>>>> +
>>>>> + priv_dev = kzalloc(sizeof(*priv_dev), GFP_KERNEL);
>>>>> + if (!priv_dev)
>>>>> + return -ENOMEM;
>>>>> +
>>>>> + cdns->gadget_dev = priv_dev;
>>>>> + priv_dev->sysdev = cdns->dev;
>>>>> + priv_dev->dev = cdns->dev;
>>>>> + priv_dev->regs = cdns->dev_regs;
>>>>> +
>>>>> + device_property_read_u16(priv_dev->dev, "cdns,on-chip-buff-size",
>>>>> + &priv_dev->onchip_buffers);
>>>>> +
>>>>> + if (priv_dev->onchip_buffers <= 0) {
>>>>> + u32 reg = readl(&priv_dev->regs->usb_cap2);
>>>>> +
>>>>> + priv_dev->onchip_buffers = USB_CAP2_ACTUAL_MEM_SIZE(reg);
>>>>> + }
>>>>> +
>>>>> + if (!priv_dev->onchip_buffers)
>>>>> + priv_dev->onchip_buffers = 256;
>>>>> +
>>>>> + max_speed = usb_get_maximum_speed(cdns->dev);
>>>>> +
>>>>> + /* Check the maximum_speed parameter */
>>>>> + switch (max_speed) {
>>>>> + case USB_SPEED_FULL:
>>>>> + case USB_SPEED_HIGH:
>>>>> + case USB_SPEED_SUPER:
>>>>> + break;
>>>>> + default:
>>>>> + dev_err(cdns->dev, "invalid maximum_speed parameter %d\n",
>>>>> + max_speed);
>>>>> + /* fall through */
>>>>> + case USB_SPEED_UNKNOWN:
>>>>> + /* default to superspeed */
>>>>> + max_speed = USB_SPEED_SUPER;
>>>>> + break;
>>>>> + }
>>>>> +
>>>>> + /* fill gadget fields */
>>>>> + priv_dev->gadget.max_speed = max_speed;
>>>>> + priv_dev->gadget.speed = USB_SPEED_UNKNOWN;
>>>>> + priv_dev->gadget.ops = &cdns3_gadget_ops;
>>>>> + priv_dev->gadget.name = "usb-ss-gadget";
>>>>> + priv_dev->gadget.sg_supported = 1;
>>>>> +
>>>>> + spin_lock_init(&priv_dev->lock);
>>>>> + INIT_WORK(&priv_dev->pending_status_wq,
>>>>> + cdns3_pending_setup_status_handler);
>>>>> +
>>>>> + /* initialize endpoint container */
>>>>> + INIT_LIST_HEAD(&priv_dev->gadget.ep_list);
>>>>> + INIT_LIST_HEAD(&priv_dev->aligned_buf_list);
>>>>> +
>>>>> + ret = cdns3_init_eps(priv_dev);
>>>>> + if (ret) {
>>>>> + dev_err(priv_dev->dev, "Failed to create endpoints\n");
>>>>> + goto err1;
>>>>> + }
>>>>> +
>>>>> + /* allocate memory for setup packet buffer */
>>>>> + priv_dev->setup_buf = dma_alloc_coherent(priv_dev->sysdev, 8,
>>>>> + &priv_dev->setup_dma, GFP_DMA);
>>>>> + if (!priv_dev->setup_buf) {
>>>>> + ret = -ENOMEM;
>>>>> + goto err2;
>>>>> + }
>>>>> +
>>>>> + priv_dev->dev_ver = readl(&priv_dev->regs->usb_cap6);
>>>>> +
>>>>> + dev_dbg(priv_dev->dev, "Device Controller version: %08x\n",
>>>>> + readl(&priv_dev->regs->usb_cap6));
>>>>> + dev_dbg(priv_dev->dev, "USB Capabilities:: %08x\n",
>>>>> + readl(&priv_dev->regs->usb_cap1));
>>>>> + dev_dbg(priv_dev->dev, "On-Chip memory cnfiguration: %08x\n",
>>>>> + readl(&priv_dev->regs->usb_cap2));
>>>>> +
>>>>> + priv_dev->dev_ver = GET_DEV_BASE_VERSION(priv_dev->dev_ver);
>>>>> +
>>>>> + priv_dev->zlp_buf = kzalloc(CDNS3_EP_ZLP_BUF_SIZE, GFP_KERNEL);
>>>>> + if (!priv_dev->zlp_buf) {
>>>>> + ret = -ENOMEM;
>>>>> + goto err3;
>>>>> + }
>>>>> +
>>>>> + /* add USB gadget device */
>>>>> + ret = usb_add_gadget_udc(priv_dev->dev, &priv_dev->gadget);
>>>>> + if (ret < 0) {
>>>>> + dev_err(priv_dev->dev,
>>>>> + "Failed to register USB device controller\n");
>>>>> + goto err4;
>>>>> + }
>>>>> +
>>>>> + return 0;
>>>>> +err4:
>>>>> + kfree(priv_dev->zlp_buf);
>>>>> +err3:
>>>>> + dma_free_coherent(priv_dev->sysdev, 8, priv_dev->setup_buf,
>>>>> + priv_dev->setup_dma);
>>>>> +err2:
>>>>> + cdns3_free_all_eps(priv_dev);
>>>>> +err1:
>>>>> + cdns->gadget_dev = NULL;
>>>>> + return ret;
>>>>> +}
>>>>> +
>>>>> +static int __cdns3_gadget_init(struct cdns3 *cdns)
>>>>> +{
>>>>> + struct cdns3_device *priv_dev;
>>>>> + int ret = 0;
>>>>> +
>>>>> + cdns3_drd_switch_gadget(cdns, 1);
>>>>> + pm_runtime_get_sync(cdns->dev);
>>>>> +
>>>>> + ret = cdns3_gadget_start(cdns);
>>>>> + if (ret)
>>>>> + return ret;
>>>>> +
>>>>> + priv_dev = cdns->gadget_dev;
>>>>> + ret = devm_request_threaded_irq(cdns->dev, cdns->dev_irq,
>>>>> + cdns3_device_irq_handler,
>>>>> + cdns3_device_thread_irq_handler,
>>>>> + IRQF_SHARED, dev_name(cdns->dev), cdns);
>>>>
>>>>copied handlers here for commenting. Note that you don't have
>>>>IRQF_ONESHOT:
>>>
>>> I know, I can't use IRQF_ ONESHOT flag in this case. I have implemented
>>> some code for masking/unmasking interrupts in cdns3_device_irq_handler.
>>>
>>> Some priority interrupts should be handled ASAP so I can't blocked interrupt
>>> Line.
>>
>>You're completely missing my comment. Your top half should be as short
>>as possile. It should only check if current device generated
>>interrupts. If it did, then you should wake the thread handler.
>>
>>This is to improve realtime behavior but not keeping preemption disabled
>>for longer than necessary.
>
> Ok, I understand. I will move it to thread handler.
>
> I can't use IRQF_ONESHOT flag because it doesn't work when interrupt line is shared.
yeah, you should try to avoid ONESHOT :-)
> I have such situation in which one interrupt line is shared with ehci and cdns3 driver.
> In such case this function returns error code.
which function returns error code?
> So probably I will need to mask only the reported interrupts.
you should mask all interrupts from your device, otherwise you top-halt
may still end up reentrant.
> I can't mask all interrupt using controller register because I can miss some of them.
why would you miss them? They would be left in the register until you
unmask them and the line is raised again.
> After masking all interrupt the next new event will not be reported in usb_ists, ep_ists
> registers.
why not? Masking means that new events won't cause the IRQ line to be
asserted (or MSI DWORD write won't be initiated), but the event itself
should still be in the register.
>>>>> +static irqreturn_t cdns3_device_irq_handler(int irq, void *data)
>>>>> +{
>>>>> + struct cdns3_device *priv_dev;
>>>>> + struct cdns3 *cdns = data;
>>>>> + irqreturn_t ret = IRQ_NONE;
>>>>> + unsigned long flags;
>>>>> + u32 reg;
>>>>> +
>>>>> + priv_dev = cdns->gadget_dev;
>>>>> + spin_lock_irqsave(&priv_dev->lock, flags);
>>>>
>>>>the top half handler runs in hardirq context. You don't need any locks
>>>>here. Also IRQs are *already* disabled, you don't need to disable them again.
>>>
>>> I will remove spin_lock_irqsave but I need to disable only some of the interrupts.
>>> I disable interrupts associated with USB endpoints. Handling of them can be
>>> deferred to thread handled.
>>
>>you should defer all of them to thread. Endpoints or otherwise.
>
> I will do this.
>
> Also I remove spin_lock_irqsave(&priv_dev->lock, flags);
> As I remember it's not needed here.
right
>>>>> + /* check USB device interrupt */
>>>>> + reg = readl(&priv_dev->regs->usb_ists);
>>>>> +
>>>>> + if (reg) {
>>>>> + writel(reg, &priv_dev->regs->usb_ists);
>>>>> + cdns3_check_usb_interrupt_proceed(priv_dev, reg);
>>>>> + ret = IRQ_HANDLED;
>>>>
>>>>now, because you _don't_ mask this interrupt, you're gonna have
>>>>issues. Say we actually get both device and endpoint interrupts while
>>>>the thread is already running with previous endpoint interrupts. Now
>>>>we're gonna reenter the top half, because device interrupts are *not*
>>>>masked, which will read usb_ists and handle it here.
>>>
>>> Endpoint interrupts are masked in cdns3_device_irq_handler and stay masked
>>> until they are not handled in threaded handler.
>>
>>Quick question, then: these ISTS registers, are they masked interrupt
>>status or raw interrupt status?
>
> Yes it's masked, but after masking them the new interrupts will not be reported
> In ISTS registers. Form this reason I can mask only reported interrupt.
and what happens when you unmask the registers? Do they get reported?
>>> Of course, not all endpoint interrupts are masked, but only reported in ep_ists.
>>> USB interrupt will be handled immediately.
>>>
>>> Also, I can get next endpoint interrupt from not masked endpoint and driver also again wake
>>> the thread. I saw such situation, but threaded interrupt handler has been working correct
>>> in such situations.
>>>
>>> In thread handler driver checks again which endpoint should be handled in ep_ists.
>>>
>>> I think that such situation should also occurs during our LPM enter/exit test.
>>> So, driver has been tested for such case. During this test driver during
>>> transferring data generate a huge number of LPM interrupts which
>>> are usb interrupts.
>>>
>>> I can't block usb interrupts interrupts because:
>>> /*
>>> * WORKAROUND: CDNS3 controller has issue with hardware resuming
>>> * from L1. To fix it, if any DMA transfer is pending driver
>>> * must starts driving resume signal immediately.
>>> */
>>
>>I can't see why this would prevent you from defering handling to thread
>>handler.
>>
>
> I also will try to move it, but this change can has impact on performance.
how much is the impact? What's the impact? Why does this impact performance?
>>>>> + struct cdns3_aligned_buf *buf, *tmp;
>>>>> +
>>>>> + list_for_each_entry_safe(buf, tmp, &priv_dev->aligned_buf_list,
>>>>> + list) {
>>>>> + if (!buf->in_use) {
>>>>> + list_del(&buf->list);
>>>>> +
>>>>> + spin_unlock_irqrestore(&priv_dev->lock, flags);
>>>>
>>>>creates the possibility of a race condition
>>> Why? In this place the buf can't be used.
>>
>>but you're reenabling interrupts, right?
>
> Yes, driver frees not used buffers here.
> I think that it's the safest place for this purpose.
I guess you missed the point a little. Since you reenable interrupts
just to free the buffer, you end up creating the possibility for a race
condition. Specially since you don't mask all interrupt events. The
moment you reenable interrupts, one of your not-unmasked interrupt
sources could trigger, then top-half gets scheduled which tries to wake
up the IRQ thread again and things go boom.
>>>>> + dma_free_coherent(priv_dev->sysdev, buf->size,
>>>>> + buf->buf,
>>>>> + buf->dma);
>>>>> + spin_lock_irqsave(&priv_dev->lock, flags);
>>>>> +
>>>>> + kfree(buf);
>>>>
>>>>why do you even need this "garbage collector"?
>>>
>>> I need to free not used memory. The once allocated buffer will be associated with
>>> request, but if request.length will be increased in usb_request then driver will
>>> must allocate the bigger buffer. As I remember I couldn't call dma_free_coherent
>>> in interrupt context so I had to move it to thread handled. This flag was used to avoid
>>> going through whole aligned_buf_list every time.
>>> In most cases this part will never called int this place
>>
>>Did you try, btw, setting the quirk flag which tells gadget drivers to
>>always allocate buffers aligned to MaxPacketSize? Wouldn't that be enough?
>
> If found only quirk_ep_out_aligned_size flag, but it align only buffer size.
>
> DMA used by this controller must have buffer address aligned to 8.
> I think that on most architecture kmalloc should guarantee such aligned.
right, it should be aligned on PAGE_SIZE
> The problem was detected on NXP testing board.
and what was the alignment on that? IIRC, ARM had the same alignment
requirements as x86. Where you sing SLUB allocator on that NXP board,
perhaps?
--
balbi
^ permalink raw reply
* Re: [linux-sunxi] [PATCH v5 1/3] arm64: dts: allwinner: Add SPDIF node for Allwinner H6
From: Chen-Yu Tsai @ 2019-08-12 4:52 UTC (permalink / raw)
To: Clément Péron
Cc: Maxime Ripard, Rob Herring, linux-arm-kernel, devicetree,
linux-kernel, linux-sunxi
In-Reply-To: <20190811203144.5999-2-peron.clem@gmail.com>
Hi,
On Mon, Aug 12, 2019 at 4:31 AM Clément Péron <peron.clem@gmail.com> wrote:
>
> The Allwinner H6 has a SPDIF controller called OWA (One Wire Audio).
>
> Only one pinmuxing is available so set it as default.
>
> Signed-off-by: Clément Péron <peron.clem@gmail.com>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 38 ++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> index 7628a7c83096..677eb374678d 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> @@ -83,6 +83,24 @@
> method = "smc";
> };
>
> + sound-spdif {
> + compatible = "simple-audio-card";
> + simple-audio-card,name = "sun50i-h6-spdif";
> +
> + simple-audio-card,cpu {
> + sound-dai = <&spdif>;
> + };
> +
> + simple-audio-card,codec {
> + sound-dai = <&spdif_out>;
> + };
> + };
> +
> + spdif_out: spdif-out {
> + #sound-dai-cells = <0>;
> + compatible = "linux,spdif-dit";
> + };
> +
We've always had this part in the board dts. It isn't relevant to boards
that don't have SPDIF output.
Also, not so relevant here, but there are different simple sound card
constructs. Some support multiple audio streams with dynamic PCM routing.
How these are configured really depends on what interfaces are usable.
So keeping this at the board level is IMO a better choice.
ChenYu
> timer {
> compatible = "arm,armv8-timer";
> interrupts = <GIC_PPI 13
> @@ -282,6 +300,11 @@
> bias-pull-up;
> };
>
> + spdif_tx_pin: spdif-tx-pin {
> + pins = "PH7";
> + function = "spdif";
> + };
> +
> uart0_ph_pins: uart0-ph-pins {
> pins = "PH0", "PH1";
> function = "uart0";
> @@ -411,6 +434,21 @@
> };
> };
>
> + spdif: spdif@5093000 {
> + #sound-dai-cells = <0>;
> + compatible = "allwinner,sun50i-h6-spdif";
> + reg = <0x05093000 0x400>;
> + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
> + clock-names = "apb", "spdif";
> + resets = <&ccu RST_BUS_SPDIF>;
> + dmas = <&dma 2>;
> + dma-names = "tx";
> + pinctrl-names = "default";
> + pinctrl-0 = <&spdif_tx_pin>;
> + status = "disabled";
> + };
> +
> usb2otg: usb@5100000 {
> compatible = "allwinner,sun50i-h6-musb",
> "allwinner,sun8i-a33-musb";
> --
> 2.20.1
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20190811203144.5999-2-peron.clem%40gmail.com.
^ permalink raw reply
* RE: [PATCH v9 5/6] usb:cdns3 Add Cadence USB3 DRD Driver
From: Pawel Laszczak @ 2019-08-12 4:43 UTC (permalink / raw)
To: Peter Chen, Felipe Balbi, devicetree@vger.kernel.org
Cc: gregkh@linuxfoundation.org, linux-usb@vger.kernel.org,
hdegoede@redhat.com, heikki.krogerus@linux.intel.com,
robh+dt@kernel.org, rogerq@ti.com, linux-kernel@vger.kernel.org,
jbergsagel@ti.com, nsekhar@ti.com, nm@ti.com, Suresh Punnoose,
Jayshri Dajiram Pawar, Rahul Kumar
In-Reply-To: <VI1PR04MB53279117788B7D7CC3080B398BD30@VI1PR04MB5327.eurprd04.prod.outlook.com>
>
>>
>> Yes, driver frees not used buffers here.
>> I think that it's the safest place for this purpose.
>>
>> >
>> >>>> + dma_free_coherent(priv_dev->sysdev, buf-
>> >size,
>> >>>> + buf->buf,
>> >>>> + buf->dma);
>> >>>> + spin_lock_irqsave(&priv_dev->lock, flags);
>> >>>> +
>> >>>> + kfree(buf);
>> >>>
>> >>>why do you even need this "garbage collector"?
>> >>
>> >> I need to free not used memory. The once allocated buffer will be
>> >> associated with request, but if request.length will be increased in
>> >> usb_request then driver will must allocate the bigger buffer. As I
>> >> remember I couldn't call dma_free_coherent in interrupt context so I
>> >> had to move it to thread handled. This flag was used to avoid going through
>> whole aligned_buf_list every time.
>> >> In most cases this part will never called int this place
>> >
>> >Did you try, btw, setting the quirk flag which tells gadget drivers to
>> >always allocate buffers aligned to MaxPacketSize? Wouldn't that be enough?
>>
>> If found only quirk_ep_out_aligned_size flag, but it align only buffer size.
>>
>> DMA used by this controller must have buffer address aligned to 8.
>> I think that on most architecture kmalloc should guarantee such aligned.
>> The problem was detected on NXP testing board.
>> On my board all buffer address are alignment at least to 8.
>>
>
>This un-aligned request buffer address for 8 occurs for Ethernet Gadget (eg, NCM),
>it allocates socket buffer with NET_IP_ALIGN, so the last byte of buffer address
>is always 2. Although this can be workaround by setting quirk_avoids_skb_reserve,
>but we are not sure if all gadget request buffers can be 8 or Max Packet Size aligned.
>
Thanks Peter for explanation.
I will add quirk_avoids_skb_reserve to avoid using this extra buffers, but I leave this
code for safety.
--
Cheers,
Pawell
^ permalink raw reply
* [PATCH 4/4] arm64: dts: fsl: Remove num-lanes property from PCIe nodes
From: Z.q. Hou @ 2019-08-12 4:22 UTC (permalink / raw)
To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, gustavo.pimentel@synopsys.com,
jingoohan1@gmail.com, bhelgaas@google.com, robh+dt@kernel.org,
mark.rutland@arm.com, shawnguo@kernel.org, Leo Li,
lorenzo.pieralisi@arm.com
Cc: M.h. Lian, Z.q. Hou
In-Reply-To: <20190812042435.25102-1-Zhiqiang.Hou@nxp.com>
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
On FSL Layerscape SoCs, the number of lanes assigned to PCIe
controller is not fixed, it is determined by the selected
SerDes protocol in the RCW (Reset Configuration Word), and
the PCIe link training is completed automatically base on
the selected SerDes protocol, and the link width set-up is
updated by hardware. So the num-lanes is not needed to
specify the link width.
The current num-lanes indicates the max lanes PCIe controller
can support up to, instead of the lanes assigned to the PCIe
controller. This can result in PCIe link training fail after
hot-reset. So remove the num-lanes to avoid set-up to incorrect
link width.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 -
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 ---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ------
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 3 ---
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 4 ----
5 files changed, 17 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index ec6257a5b251..119c597ca867 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -486,7 +486,6 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- num-lanes = <4>;
num-viewport = <2>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 71d9ed9ff985..c084c7a4b6a6 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -677,7 +677,6 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- num-lanes = <4>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
@@ -704,7 +703,6 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- num-lanes = <2>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
@@ -731,7 +729,6 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- num-lanes = <2>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index b0ef08b090dd..d4c1da3d4bde 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -649,7 +649,6 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- num-lanes = <4>;
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
@@ -671,7 +670,6 @@
reg-names = "regs", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <8>;
- num-lanes = <2>;
status = "disabled";
};
@@ -687,7 +685,6 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- num-lanes = <2>;
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
@@ -709,7 +706,6 @@
reg-names = "regs", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <8>;
- num-lanes = <2>;
status = "disabled";
};
@@ -725,7 +721,6 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- num-lanes = <2>;
num-viewport = <8>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
@@ -747,7 +742,6 @@
reg-names = "regs", "addr_space";
num-ib-windows = <6>;
num-ob-windows = <8>;
- num-lanes = <2>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index dfbead405783..76c87afeba1e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -456,7 +456,6 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- num-lanes = <4>;
num-viewport = <256>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
@@ -482,7 +481,6 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- num-lanes = <4>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
@@ -508,7 +506,6 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- num-lanes = <8>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 64101c9962ce..7a0be8eaa84a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -639,7 +639,6 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- num-lanes = <4>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
@@ -661,7 +660,6 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- num-lanes = <4>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
@@ -683,7 +681,6 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- num-lanes = <8>;
num-viewport = <256>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
@@ -705,7 +702,6 @@
#size-cells = <2>;
device_type = "pci";
dma-coherent;
- num-lanes = <4>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
msi-parent = <&its>;
--
2.17.1
^ permalink raw reply related
* [PATCH 3/4] ARM: dts: ls1021a: Remove num-lanes property from PCIe nodes
From: Z.q. Hou @ 2019-08-12 4:22 UTC (permalink / raw)
To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, gustavo.pimentel@synopsys.com,
jingoohan1@gmail.com, bhelgaas@google.com, robh+dt@kernel.org,
mark.rutland@arm.com, shawnguo@kernel.org, Leo Li,
lorenzo.pieralisi@arm.com
Cc: M.h. Lian, Z.q. Hou
In-Reply-To: <20190812042435.25102-1-Zhiqiang.Hou@nxp.com>
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
On FSL Layerscape SoCs, the number of lanes assigned to PCIe
controller is not fixed, it is determined by the selected
SerDes protocol in the RCW (Reset Configuration Word), and
the PCIe link training is completed automatically base on
the selected SerDes protocol, and the link width set-up is
updated by hardware. So the num-lanes is not needed to
specify the link width.
The current num-lanes indicates the max lanes PCIe controller
can support up to, instead of the lanes assigned to the PCIe
controller. This can result in PCIe link training fail after
hot-reset. So remove the num-lanes to avoid set-up to incorrect
link width.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
arch/arm/boot/dts/ls1021a.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 464df4290ffc..2f6977ada447 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -874,7 +874,6 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- num-lanes = <4>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
@@ -899,7 +898,6 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- num-lanes = <4>;
num-viewport = <6>;
bus-range = <0x0 0xff>;
ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
--
2.17.1
^ permalink raw reply related
* [PATCH 2/4] PCI: dwc: Return directly when num-lanes is not found
From: Z.q. Hou @ 2019-08-12 4:22 UTC (permalink / raw)
To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, gustavo.pimentel@synopsys.com,
jingoohan1@gmail.com, bhelgaas@google.com, robh+dt@kernel.org,
mark.rutland@arm.com, shawnguo@kernel.org, Leo Li,
lorenzo.pieralisi@arm.com
Cc: M.h. Lian, Z.q. Hou
In-Reply-To: <20190812042435.25102-1-Zhiqiang.Hou@nxp.com>
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
The num-lanes is optional, so probably it isn't added
on some platforms. The subsequent programming is base
on the num-lanes, hence return when it is not found.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
drivers/pci/controller/dwc/pcie-designware.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 7d25102c304c..0a89bfd1636e 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -423,8 +423,10 @@ void dw_pcie_setup(struct dw_pcie *pci)
ret = of_property_read_u32(np, "num-lanes", &lanes);
- if (ret)
- lanes = 0;
+ if (ret) {
+ dev_dbg(pci->dev, "property num-lanes isn't found\n");
+ return;
+ }
/* Set the number of lanes */
val = dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
--
2.17.1
^ permalink raw reply related
* [PATCH 1/4] dt-bingings: PCI: Remove the num-lanes from Required properties
From: Z.q. Hou @ 2019-08-12 4:22 UTC (permalink / raw)
To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, gustavo.pimentel@synopsys.com,
jingoohan1@gmail.com, bhelgaas@google.com, robh+dt@kernel.org,
mark.rutland@arm.com, shawnguo@kernel.org, Leo Li,
lorenzo.pieralisi@arm.com
Cc: M.h. Lian, Z.q. Hou
In-Reply-To: <20190812042435.25102-1-Zhiqiang.Hou@nxp.com>
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
The num-lanes is not a mandatory property, e.g. on FSL
Layerscape SoCs, the PCIe link training is completed
automatically base on the selected SerDes protocol, it
doesn't need the num-lanes to set-up the link width.
It has been added in the Optional properties. This
patch is to remove it from the Required properties.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
---
Documentation/devicetree/bindings/pci/designware-pcie.txt | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index 5561a1c060d0..bd880df39a79 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -11,7 +11,6 @@ Required properties:
the ATU address space.
(The old way of getting the configuration address space from "ranges"
is deprecated and should be avoided.)
-- num-lanes: number of lanes to use
RC mode:
- #address-cells: set to <3>
- #size-cells: set to <2>
--
2.17.1
^ permalink raw reply related
* [PATCH 0/4] Layerscape: Remove num-lanes property from PCIe nodes
From: Z.q. Hou @ 2019-08-12 4:22 UTC (permalink / raw)
To: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, gustavo.pimentel@synopsys.com,
jingoohan1@gmail.com, bhelgaas@google.com, robh+dt@kernel.org,
mark.rutland@arm.com, shawnguo@kernel.org, Leo Li,
lorenzo.pieralisi@arm.com
Cc: M.h. Lian, Z.q. Hou
From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
On FSL Layerscape SoCs, the number of lanes assigned to PCIe
controller is not fixed, it is determined by the selected
SerDes protocol. The current num-lanes indicates the max lanes
PCIe controller can support up to, instead of the lanes assigned
to the PCIe controller. This can result in PCIe link training fail
after hot-reset.
Hou Zhiqiang (4):
dt-bingings: PCI: Remove the num-lanes from Required properties
PCI: dwc: Return directly when num-lanes is not found
ARM: dts: ls1021a: Remove num-lanes property from PCIe nodes
arm64: dts: fsl: Remove num-lanes property from PCIe nodes
Documentation/devicetree/bindings/pci/designware-pcie.txt | 1 -
arch/arm/boot/dts/ls1021a.dtsi | 2 --
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 1 -
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 ---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 6 ------
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 3 ---
arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 4 ----
drivers/pci/controller/dwc/pcie-designware.c | 6 ++++--
8 files changed, 4 insertions(+), 22 deletions(-)
--
2.17.1
^ permalink raw reply
* Re: [PATCH 2/2] arm64: allwinner: h6: enable i2c0 in PineH64
From: Chen-Yu Tsai @ 2019-08-12 4:19 UTC (permalink / raw)
To: Bhushan Shah
Cc: Mark Rutland, devicetree, Maxime Ripard, linux-kernel,
Rob Herring, linux-arm-kernel, Icenowy Zheng
In-Reply-To: <20190811090503.32396-3-bshah@kde.org>
On Sun, Aug 11, 2019 at 5:05 PM Bhushan Shah <bshah@kde.org> wrote:
>
> i2c0 bus is exposed by PI-2 BUS in the PineH64, model B.
>
> Signed-off-by: Bhushan Shah <bshah@kde.org>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
> index 684d1daa3081..a184361bc10d 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
> @@ -160,6 +160,14 @@
> vcc-pg-supply = <®_aldo1>;
> };
>
> +&i2c0 {
> + status = "okay";
We don't enable interfaces that are exposed on the extension headers
by default. Instead we let the users enable it themselves, by modifying
the device tree either with overlays or through U-boot commands.
Please set this to "disabled", and add a comment mentioning that it is
on the PI-2 BUS. Having it explicitly listed in the source serves as a
pointer to people looking at how to enable stuff.
ChenYu
> +};
> +
> +&i2c0_pins {
> + bias-pull-up;
> +};
> +
> &r_i2c {
> status = "okay";
>
> --
> 2.17.1
>
^ permalink raw reply
* Re: [PATCH 1/2] arm64: allwinner: h6: add I2C nodes
From: Chen-Yu Tsai @ 2019-08-12 4:12 UTC (permalink / raw)
To: Bhushan Shah
Cc: Icenowy Zheng, Maxime Ripard, Rob Herring, Mark Rutland,
linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20190811090503.32396-2-bshah@kde.org>
On Sun, Aug 11, 2019 at 5:05 PM Bhushan Shah <bshah@kde.org> wrote:
>
> Add device-tree nodes for i2c0 to i2c2, and also add relevant pinctrl
> nodes.
>
> Suggested-by: Icenowy Zheng <icenowy@aosc.io>
> Signed-off-by: Bhushan Shah <bshah@kde.org>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 54 ++++++++++++++++++++
> 1 file changed, 54 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> index bcecca17d61d..1d9ad3ec0b65 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> @@ -329,6 +329,21 @@
> function = "hdmi";
> };
>
> + i2c0_pins: i2c0-pins {
> + pins = "PD25", "PD26";
> + function = "i2c0";
> + };
> +
> + i2c1_pins: i2c1-pins {
> + pins = "PH5", "PH6";
> + function = "i2c1";
> + };
> +
> + i2c2_pins: i2c2-pins {
> + pins = "PD23", "PD24";
> + function = "i2c2";
> + };
> +
> mmc0_pins: mmc0-pins {
> pins = "PF0", "PF1", "PF2", "PF3",
> "PF4", "PF5";
> @@ -464,6 +479,45 @@
> status = "disabled";
> };
>
> + i2c0: i2c@5002000 {
> + compatible = "allwinner,sun6i-a31-i2c";
Please add an soc-specific compatible string, like "allwinner,sun50i-h6-i2c".
This is a last-resort way out in case the hardware isn't so compatible with
the A31.
You'll also need to update the bindings in
Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
The file also shows that we do this for other chips, such as the A23,
A64 and A83T.
ChenYu
> + reg = <0x05002000 0x400>;
> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C0>;
> + resets = <&ccu RST_BUS_I2C0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_pins>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c1: i2c@5002400 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x05002400 0x400>;
> + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C1>;
> + resets = <&ccu RST_BUS_I2C1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c1_pins>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c2: i2c@5002800 {
> + compatible = "allwinner,sun6i-a31-i2c";
> + reg = <0x05002800 0x400>;
> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C2>;
> + resets = <&ccu RST_BUS_I2C2>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c2_pins>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> emac: ethernet@5020000 {
> compatible = "allwinner,sun50i-h6-emac",
> "allwinner,sun50i-a64-emac";
> --
> 2.17.1
>
^ permalink raw reply
* [PATCH v3 1/2] dt-bindings: Add ipsps1 as a trivial device
From: John Wang @ 2019-08-12 2:52 UTC (permalink / raw)
To: robh+dt, mark.rutland, trivial, linux, venture, anson.huang,
jgebben, devicetree, linux-kernel, miltonm, mine260309,
duanzhijia01, joel, openbmc
The ipsps1 is an Inspur Power System power supply unit
Signed-off-by: John Wang <wangzqbj@inspur.com>
---
v3:
- Fix adding entry to the inappropriate line
v2:
- No changes.
---
Documentation/devicetree/bindings/trivial-devices.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml
index 747fd3f689dc..8f21498faa92 100644
--- a/Documentation/devicetree/bindings/trivial-devices.yaml
+++ b/Documentation/devicetree/bindings/trivial-devices.yaml
@@ -100,6 +100,8 @@ properties:
- infineon,slb9645tt
# Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor
- infineon,tlv493d-a1b6
+ # Inspur Power System power supply unit version 1
+ - inspur,ipsps1
# Intersil ISL29028 Ambient Light and Proximity Sensor
- isil,isl29028
# Intersil ISL29030 Ambient Light and Proximity Sensor
--
2.17.1
^ permalink raw reply related
* Re: [PATCH v3 4/4] ASoC: codecs: add wsa881x amplifier support
From: kbuild test robot @ 2019-08-12 2:46 UTC (permalink / raw)
Cc: devicetree, alsa-devel, bgoswami, linux-kernel, plai,
pierre-louis.bossart, robh+dt, lgirdwood, vkoul, broonie,
Srinivas Kandagatla, kbuild-all
In-Reply-To: <20190809133407.25918-5-srinivas.kandagatla@linaro.org>
[-- Attachment #1: Type: text/plain, Size: 1392 bytes --]
Hi Srinivas,
I love your patch! Yet something to improve:
[auto build test ERROR on linus/master]
[cannot apply to v5.3-rc4 next-20190809]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Srinivas-Kandagatla/ASoC-codecs-Add-WSA881x-Smart-Speaker-amplifier-support/20190812-080612
config: m68k-allmodconfig (attached as .config)
compiler: m68k-linux-gcc (GCC) 7.4.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=m68k
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> ERROR: "sdw_unregister_driver" [sound/soc/codecs/snd-soc-wsa881x.ko] undefined!
>> ERROR: "sdw_write" [sound/soc/codecs/snd-soc-wsa881x.ko] undefined!
>> ERROR: "__sdw_register_driver" [sound/soc/codecs/snd-soc-wsa881x.ko] undefined!
>> ERROR: "sdw_write" [drivers/base/regmap/regmap-sdw.ko] undefined!
>> ERROR: "sdw_read" [drivers/base/regmap/regmap-sdw.ko] undefined!
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 50926 bytes --]
[-- Attachment #3: Type: text/plain, Size: 0 bytes --]
^ permalink raw reply
* RE: [PATCH 1/4] dt-bindings: watchdog: Add i.MX7ULP bindings
From: Anson Huang @ 2019-08-12 2:03 UTC (permalink / raw)
To: Guenter Roeck
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Leonard Crestez,
schnitzeltony@gmail.com, linux-watchdog@vger.kernel.org,
otavio@ossystems.com.br, festevam@gmail.com,
s.hauer@pengutronix.de, jan.tuerk@emtrion.com,
linux@armlinux.org.uk, linux-kernel@vger.kernel.org,
robh+dt@kernel.org, dl-linux-imx, kernel@pengutronix.de,
u.kleine-koenig@pengutronix.de, wim@linux-watchdog.org,
shawnguo@kernel.org, linux-arm-ker
In-Reply-To: <20190809164245.GA17136@roeck-us.net>
Hi, Guenter
> On Fri, Aug 09, 2019 at 03:13:59PM +0800, Anson Huang wrote:
> > Add the watchdog bindings for Freescale i.MX7ULP.
> >
> > Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> > ---
> > .../bindings/watchdog/fsl-imx7ulp-wdt.txt | 22
> ++++++++++++++++++++++
> > 1 file changed, 22 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt
> >
> > diff --git
> > a/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt
> > b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt
> > new file mode 100644
> > index 0000000..d83fc5c
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/watchdog/fsl-imx7ulp-wdt.txt
> > @@ -0,0 +1,22 @@
> > +* Freescale i.MX7ULP Watchdog Timer (WDT) Controller
> > +
> > +Required properties:
> > +- compatible : Should be "fsl,imx7ulp-wdt"
> > +- reg : Should contain WDT registers location and length
> > +- interrupts : Should contain WDT interrupt
> > +- clocks: Should contain a phandle pointing to the gated peripheral clock.
>
> The driver as submitted does not include clock or interrupt handling.
> Why are those properties listed as mandatory if they are not really needed
> (nor used) ?
I missed the clk part in driver, it is working ONLY because the wdog clock is enabled
unexpected, I will add it in V2, thanks for pointing out such big mistake!
Anson
>
> > +
> > +Optional properties:
> > +- timeout-sec : Contains the watchdog timeout in seconds
> > +
> > +Examples:
> > +
> > +wdog1: wdog@403d0000 {
> > + compatible = "fsl,imx7ulp-wdt";
> > + reg = <0x403d0000 0x10000>;
> > + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
> > + assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
> > + assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
> > + timeout-sec = <40>;
> > +};
> > --
> > 2.7.4
> >
^ permalink raw reply
* RE: [PATCH v9 5/6] usb:cdns3 Add Cadence USB3 DRD Driver
From: Peter Chen @ 2019-08-12 1:55 UTC (permalink / raw)
To: Pawel Laszczak, Felipe Balbi, devicetree@vger.kernel.org
Cc: gregkh@linuxfoundation.org, linux-usb@vger.kernel.org,
hdegoede@redhat.com, heikki.krogerus@linux.intel.com,
robh+dt@kernel.org, rogerq@ti.com, linux-kernel@vger.kernel.org,
jbergsagel@ti.com, nsekhar@ti.com, nm@ti.com, Suresh Punnoose,
Jayshri Dajiram Pawar, Rahul Kumar
In-Reply-To: <BYAPR07MB4709B0A4FADFB76183D651DCDDD10@BYAPR07MB4709.namprd07.prod.outlook.com>
>
> Yes, driver frees not used buffers here.
> I think that it's the safest place for this purpose.
>
> >
> >>>> + dma_free_coherent(priv_dev->sysdev, buf-
> >size,
> >>>> + buf->buf,
> >>>> + buf->dma);
> >>>> + spin_lock_irqsave(&priv_dev->lock, flags);
> >>>> +
> >>>> + kfree(buf);
> >>>
> >>>why do you even need this "garbage collector"?
> >>
> >> I need to free not used memory. The once allocated buffer will be
> >> associated with request, but if request.length will be increased in
> >> usb_request then driver will must allocate the bigger buffer. As I
> >> remember I couldn't call dma_free_coherent in interrupt context so I
> >> had to move it to thread handled. This flag was used to avoid going through
> whole aligned_buf_list every time.
> >> In most cases this part will never called int this place
> >
> >Did you try, btw, setting the quirk flag which tells gadget drivers to
> >always allocate buffers aligned to MaxPacketSize? Wouldn't that be enough?
>
> If found only quirk_ep_out_aligned_size flag, but it align only buffer size.
>
> DMA used by this controller must have buffer address aligned to 8.
> I think that on most architecture kmalloc should guarantee such aligned.
> The problem was detected on NXP testing board.
> On my board all buffer address are alignment at least to 8.
>
This un-aligned request buffer address for 8 occurs for Ethernet Gadget (eg, NCM),
it allocates socket buffer with NET_IP_ALIGN, so the last byte of buffer address
is always 2. Although this can be workaround by setting quirk_avoids_skb_reserve,
but we are not sure if all gadget request buffers can be 8 or Max Packet Size aligned.
Peter
^ permalink raw reply
* RE: [PATCH 2/4] watchdog: Add i.MX7ULP watchdog support
From: Anson Huang @ 2019-08-12 1:41 UTC (permalink / raw)
To: Guenter Roeck
Cc: wim@linux-watchdog.org, robh+dt@kernel.org, mark.rutland@arm.com,
shawnguo@kernel.org, s.hauer@pengutronix.de,
kernel@pengutronix.de, festevam@gmail.com, linux@armlinux.org.uk,
otavio@ossystems.com.br, Leonard Crestez, schnitzeltony@gmail.com,
u.kleine-koenig@pengutronix.de, jan.tuerk@emtrion.com,
linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org
In-Reply-To: <20190809161956.GA6248@roeck-us.net>
Hi, Guenter
> On Fri, Aug 09, 2019 at 03:14:00PM +0800, Anson Huang wrote:
> > The i.MX7ULP Watchdog Timer (WDOG) module is an independent timer
> that
> > is available for system use.
> > It provides a safety feature to ensure that software is executing as
> > planned and that the CPU is not stuck in an infinite loop or executing
> > unintended code. If the WDOG module is not serviced
> > (refreshed) within a certain period, it resets the MCU.
> >
> > Add driver support for i.MX7ULP watchdog.
> >
> > Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> > ---
> > drivers/watchdog/Kconfig | 13 +++
> > drivers/watchdog/Makefile | 1 +
> > drivers/watchdog/imx7ulp_wdt.c | 221
> > +++++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 235 insertions(+)
> > create mode 100644 drivers/watchdog/imx7ulp_wdt.c
> >
> > diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index
> > 8188963..0884e53 100644
> > --- a/drivers/watchdog/Kconfig
> > +++ b/drivers/watchdog/Kconfig
> > @@ -740,6 +740,19 @@ config IMX_SC_WDT
> > To compile this driver as a module, choose M here: the
> > module will be called imx_sc_wdt.
> >
> > +config IMX7ULP_WDT
> > + tristate "IMX7ULP Watchdog"
> > + depends on ARCH_MXC || COMPILE_TEST
> > + select WATCHDOG_CORE
> > + help
> > + This is the driver for the hardware watchdog on the Freescale
> > + IMX7ULP and later processors. If you have one of these
> > + processors and wish to have watchdog support enabled,
> > + say Y, otherwise say N.
> > +
> > + To compile this driver as a module, choose M here: the
> > + module will be called imx7ulp_wdt.
> > +
> > config UX500_WATCHDOG
> > tristate "ST-Ericsson Ux500 watchdog"
> > depends on MFD_DB8500_PRCMU
> > diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> > index 7caa920..7d32537 100644
> > --- a/drivers/watchdog/Makefile
> > +++ b/drivers/watchdog/Makefile
> > @@ -69,6 +69,7 @@ obj-$(CONFIG_TS4800_WATCHDOG) += ts4800_wdt.o
> > obj-$(CONFIG_TS72XX_WATCHDOG) += ts72xx_wdt.o
> > obj-$(CONFIG_IMX2_WDT) += imx2_wdt.o
> > obj-$(CONFIG_IMX_SC_WDT) += imx_sc_wdt.o
> > +obj-$(CONFIG_IMX7ULP_WDT) += imx7ulp_wdt.o
> > obj-$(CONFIG_UX500_WATCHDOG) += ux500_wdt.o
> > obj-$(CONFIG_RETU_WATCHDOG) += retu_wdt.o
> > obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o diff --git
> > a/drivers/watchdog/imx7ulp_wdt.c b/drivers/watchdog/imx7ulp_wdt.c
> new
> > file mode 100644 index 0000000..8d56023
> > --- /dev/null
> > +++ b/drivers/watchdog/imx7ulp_wdt.c
> > @@ -0,0 +1,221 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright 2019 NXP.
> > + */
> > +
> > +#include <linux/init.h>
> > +#include <linux/io.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/reboot.h>
> > +#include <linux/watchdog.h>
> > +
> > +#define WDOG_CS 0x0
> > +#define WDOG_CS_CMD32EN (1 << 13)
> > +#define WDOG_CS_ULK (1 << 11)
> > +#define WDOG_CS_RCS (1 << 10)
> > +#define WDOG_CS_EN (1 << 7)
> > +#define WDOG_CS_UPDATE (1 << 5)
> > +
>
> Please use BIT() where appropriate.
Got it.
>
> > +#define WDOG_CNT 0x4
> > +#define WDOG_TOVAL 0x8
> > +
> > +#define REFRESH_SEQ0 0xA602
> > +#define REFRESH_SEQ1 0xB480
> > +#define REFRESH ((REFRESH_SEQ1 << 16) | (REFRESH_SEQ0))
>
> The inner ( ) are unnecessary. While I would accept it for readability for the
> first part, (REFRESH_SEQ0) really doesn't add value.
Got it.
>
> > +
> > +#define UNLOCK_SEQ0 0xC520
> > +#define UNLOCK_SEQ1 0xD928
> > +#define UNLOCK ((UNLOCK_SEQ1 << 16) | (UNLOCK_SEQ0))
>
> Same as above.
Got it.
>
> > +
> > +#define DEFAULT_TIMEOUT 60
> > +#define MAX_TIMEOUT 128
>
> tabs after _TIMEOUT, please
Got it.
>
> > +
> > +static bool nowayout = WATCHDOG_NOWAYOUT;
> module_param(nowayout,
> > +bool, 0000); MODULE_PARM_DESC(nowayout, "Watchdog cannot be
> stopped
> > +once started (default="
> > + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
> > +
> > +struct imx7ulp_wdt_device {
> > + struct notifier_block restart_handler;
> > + struct watchdog_device wdd;
> > + void __iomem *base;
> > + int rate;
> > +};
> > +
> > +static inline void imx7ulp_wdt_enable(void __iomem *base, bool
> > +enable) {
> > + u32 val = readl(base + WDOG_CS);
> > +
> > + writel(UNLOCK, base + WDOG_CNT);
> > + if (enable)
> > + writel(val | WDOG_CS_EN, base + WDOG_CS);
> > + else
> > + writel(val & ~WDOG_CS_EN, base + WDOG_CS); }
> > +
> > +static inline bool imx7ulp_wdt_is_enabled(void __iomem *base) {
> > + u32 val = readl(base + WDOG_CS);
> > +
> > + return val & WDOG_CS_EN;
> > +}
> > +
> > +static int imx7ulp_wdt_ping(struct watchdog_device *wdog) {
> > + struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
> > +
> > + writel(REFRESH, wdt->base + WDOG_CNT);
> > +
> > + return 0;
> > +}
> > +
> > +static int imx7ulp_wdt_start(struct watchdog_device *wdog) {
> > + struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
> > +
> > + imx7ulp_wdt_enable(wdt->base, true);
> > +
> > + return 0;
> > +}
> > +
> > +static int imx7ulp_wdt_stop(struct watchdog_device *wdog) {
> > + struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
> > +
> > + imx7ulp_wdt_enable(wdt->base, false);
> > +
> > + return 0;
> > +}
> > +
> > +static int imx7ulp_wdt_set_timeout(struct watchdog_device *wdog,
> > + unsigned int timeout)
> > +{
> > + struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
> > + u32 val = wdt->rate * timeout;
> > +
> > + writel(UNLOCK, wdt->base + WDOG_CNT);
> > + writel(val, wdt->base + WDOG_TOVAL);
> > +
> > + wdog->timeout = timeout;
> > +
> > + return 0;
> > +}
> > +
> > +static const struct watchdog_ops imx7ulp_wdt_ops = {
> > + .owner = THIS_MODULE,
> > + .start = imx7ulp_wdt_start,
> > + .stop = imx7ulp_wdt_stop,
> > + .ping = imx7ulp_wdt_ping,
> > + .set_timeout = imx7ulp_wdt_set_timeout, };
> > +
> > +static const struct watchdog_info imx7ulp_wdt_info = {
> > + .identity = "i.MX7ULP watchdog timer",
> > + .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
> > + WDIOF_MAGICCLOSE,
> > +};
> > +
> > +static inline void imx7ulp_wdt_init(void __iomem *base, unsigned int
> > +timeout) {
> > + u32 val;
> > +
> > + /* unlock the wdog for reconfiguration */
> > + writel_relaxed(UNLOCK_SEQ0, base + WDOG_CNT);
> > + writel_relaxed(UNLOCK_SEQ1, base + WDOG_CNT);
> > +
> > + /* set an initial timeout value in TOVAL */
> > + writel(timeout, base + WDOG_TOVAL);
> > + /* enable 32bit command sequence and reconfigure */
> > + val = (1 << 13) | (1 << 8) | (1 << 5);
>
> Please use BIT()
Got it.
>
> > + writel(val, base + WDOG_CS);
> > +}
> > +
> > +static int imx7ulp_wdt_probe(struct platform_device *pdev) {
> > + struct imx7ulp_wdt_device *imx7ulp_wdt;
> > + struct device *dev = &pdev->dev;
> > + struct watchdog_device *wdog;
> > + int ret;
> > +
> > + imx7ulp_wdt = devm_kzalloc(&pdev->dev,
> > + sizeof(*imx7ulp_wdt), GFP_KERNEL);
> > + if (!imx7ulp_wdt)
> > + return -ENOMEM;
> > +
> > + platform_set_drvdata(pdev, imx7ulp_wdt);
> > +
> > + imx7ulp_wdt->base = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(imx7ulp_wdt->base))
> > + return PTR_ERR(imx7ulp_wdt->base);
> > +
> > + imx7ulp_wdt->rate = 1000;
> > + wdog = &imx7ulp_wdt->wdd;
> > + wdog->info = &imx7ulp_wdt_info;
> > + wdog->ops = &imx7ulp_wdt_ops;
> > + wdog->min_timeout = 1;
> > + wdog->max_timeout = MAX_TIMEOUT;
> > + wdog->parent = dev;
> > + wdog->timeout = DEFAULT_TIMEOUT;
> > +
> > + watchdog_init_timeout(wdog, 0, dev);
> > + watchdog_stop_on_reboot(wdog);
> > + watchdog_stop_on_unregister(wdog);
> > + watchdog_set_drvdata(wdog, imx7ulp_wdt);
> > + imx7ulp_wdt_init(imx7ulp_wdt->base, wdog->timeout *
> > +imx7ulp_wdt->rate);
> > +
> > + ret = devm_watchdog_register_device(dev, wdog);
> > + if (ret)
> > + dev_err(dev, "Failed to register watchdog device\n");
>
> An error message is already displayed by the watchdog core.
Got it.
>
> > +
> > + return ret;
> > +}
> > +
> > +static int __maybe_unused imx7ulp_wdt_suspend(struct device *dev) {
> > + struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev);
> > +
> > + if (watchdog_active(&imx7ulp_wdt->wdd))
> > + imx7ulp_wdt_stop(&imx7ulp_wdt->wdd);
> > +
> > + return 0;
> > +}
> > +
> > +static int __maybe_unused imx7ulp_wdt_resume(struct device *dev) {
> > + struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev);
> > + u32 timeout = imx7ulp_wdt->wdd.timeout * imx7ulp_wdt->rate;
> > +
> > + if (imx7ulp_wdt_is_enabled(imx7ulp_wdt->base))
> > + imx7ulp_wdt_init(imx7ulp_wdt->base, timeout);
> > +
> If I understand correctly, imx7ulp_wdt_is_enabled() returns true if the
> watchdog is running. Since it was stopped on suspend, that means that it was
> started in BIOS/rommon during resume.
>
> With that, the above translates to "If the watchdog was started by
> BIOS/rommon, re-initialize it. Otherwise do nothing". This doesn't really
> make much sense to me. What if the watchdog was reprogrammed by the
> BIOS/rommon, but not started ? In other words, why not call
> imx7ulp_wdt_init() unconditionally ?
The i.MX7ULP hardware design is, if A7 domain is powered off during suspend (mem suspend),
watchdog will be always reset and re-started by boot ROM. If A7 domain is NOT powered off during
suspend (standby suspend), the watchdog does NOT lose context and boot ROM NOT
run again after resume.
>
> Also, if it is possible that the watchdog is started by BIOS/rommon, why not
> keep it enabled and tell the watchdog core about it in the probe function ?
There are 2 cases of watchdog status during suspend/resume, i.MX7ULP supports
both standby suspend and mem suspend, for mem suspend, the whole A7 domain
will be powered off, and after resume, watchdog will be re-started by boot ROM (BIOS),
while for standby suspend, the watchdog does NOT re-started by boot ROM, as A7
domain is NOT powered off. That is why I added the check here, since there are 2 cases
sharing same suspend/resume callback. Does it make sense to you?
Thanks,
Anson
>
> > + if (watchdog_active(&imx7ulp_wdt->wdd))
> > + imx7ulp_wdt_start(&imx7ulp_wdt->wdd);
> > +
> > + return 0;
> > +}
> > +
> > +static SIMPLE_DEV_PM_OPS(imx7ulp_wdt_pm_ops,
> imx7ulp_wdt_suspend,
> > + imx7ulp_wdt_resume);
> > +
> > +static const struct of_device_id imx7ulp_wdt_dt_ids[] = {
> > + { .compatible = "fsl,imx7ulp-wdt", },
> > + { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, imx7ulp_wdt_dt_ids);
> > +
> > +static struct platform_driver imx7ulp_wdt_driver = {
> > + .probe = imx7ulp_wdt_probe,
> > + .driver = {
> > + .name = "imx7ulp-wdt",
> > + .pm = &imx7ulp_wdt_pm_ops,
> > + .of_match_table = imx7ulp_wdt_dt_ids,
> > + },
> > +};
> > +module_platform_driver(imx7ulp_wdt_driver);
> > +
> > +MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
> > +MODULE_DESCRIPTION("Freescale i.MX7ULP watchdog driver");
> > +MODULE_LICENSE("GPL v2");
> > --
> > 2.7.4
> >
^ permalink raw reply
* [PATCH v2] ARM: dts: add device tree for Mecer Xtreme Mini S6
From: Justin Swartz @ 2019-08-11 23:00 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Heiko Stuebner
Cc: Justin Swartz, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel
The Mecer Xtreme Mini S6 features a Rockchip RK3229 SoC,
1GB DDR3 RAM, 8GB eMMC, MicroSD port, 10/100Mbps Ethernet,
Realtek 8723BS WLAN module, 2 x USB 2.0 ports, HDMI output,
and S/PDIF output.
Signed-off-by: Justin Swartz <justin.swartz@risingedge.co.za>
---
.../devicetree/bindings/arm/rockchip.yaml | 5 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/rk3229-xms6.dts | 283 +++++++++++++++++++++
4 files changed, 291 insertions(+)
create mode 100644 arch/arm/boot/dts/rk3229-xms6.dts
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index 34865042f4e4..4abd91c2b0bd 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -329,6 +329,11 @@ properties:
- khadas,edge-v
- const: rockchip,rk3399
+ - description: Mecer Xtreme Mini S6
+ items:
+ - const: mecer,xms6
+ - const: rockchip,rk3229
+
- description: mqmaker MiQi
items:
- const: mqmaker,miqi
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 6992bbbbffab..97992fccfc3d 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -549,6 +549,8 @@ patternProperties:
description: mCube
"^meas,.*":
description: Measurement Specialties
+ "^mecer,.*":
+ description: Mustek Limited
"^mediatek,.*":
description: MediaTek Inc.
"^megachips,.*":
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 9159fa2cea90..4567c0b045c2 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -905,6 +905,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3188-radxarock.dtb \
rk3228-evb.dtb \
rk3229-evb.dtb \
+ rk3229-xms6.dtb \
rk3288-evb-act8846.dtb \
rk3288-evb-rk808.dtb \
rk3288-fennec.dtb \
diff --git a/arch/arm/boot/dts/rk3229-xms6.dts b/arch/arm/boot/dts/rk3229-xms6.dts
new file mode 100644
index 000000000000..4b6ab4954dd4
--- /dev/null
+++ b/arch/arm/boot/dts/rk3229-xms6.dts
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "rk3229.dtsi"
+
+/ {
+ model = "Mecer Xtreme Mini S6";
+ compatible = "mecer,xms6", "rockchip,rk3229";
+
+ dc_12v: dc-12v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ ext_gmac: ext_gmac {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "ext_gmac";
+ #clock-cells = <0>;
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x40000000>;
+ };
+
+ power-led {
+ compatible = "gpio-leds";
+
+ blue {
+ gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ vcc_host: vcc-host-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&host_vbus_drv>;
+ regulator-name = "vcc_host";
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vcc_phy: vcc-phy-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ regulator-name = "vcc_phy";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vccio_1v8>;
+ };
+
+ vcc_sys: vcc-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vccio_1v8: vccio-1v8-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vccio_1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vccio_3v3: vccio-3v3-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vccio_3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&vcc_sys>;
+ };
+
+ vdd_arm: vdd-arm-regulator {
+ compatible = "pwm-regulator";
+ pwms = <&pwm1 0 25000 1>;
+ pwm-supply = <&vcc_sys>;
+ regulator-name = "vdd_arm";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+
+ vdd_log: vdd-log-regulator {
+ compatible = "pwm-regulator";
+ pwms = <&pwm2 0 25000 1>;
+ pwm-supply = <&vcc_sys>;
+ regulator-name = "vdd_log";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&emmc {
+ cap-mmc-highspeed;
+ disable-wp;
+ non-removable;
+ status = "okay";
+};
+
+&gmac {
+ assigned-clocks = <&cru SCLK_MAC_SRC>;
+ assigned-clock-rates = <50000000>;
+ clock_in_out = "output";
+ phy-supply = <&vcc_phy>;
+ phy-mode = "rmii";
+ phy-handle = <&phy>;
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy: phy@0 {
+ compatible = "ethernet-phy-id1234.d400",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ clocks = <&cru SCLK_MAC_PHY>;
+ resets = <&cru SRST_MACPHY>;
+ phy-is-integrated;
+ };
+ };
+};
+
+&gpu {
+ mali-supply = <&vdd_log>;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_phy {
+ status = "okay";
+};
+
+&iep_mmu {
+ status = "okay";
+};
+
+&io_domains {
+ status = "okay";
+
+ vccio1-supply = <&vccio_3v3>;
+ vccio2-supply = <&vccio_1v8>;
+ vccio4-supply = <&vccio_3v3>;
+};
+
+&pinctrl {
+ usb {
+ host_vbus_drv: host-vbus-drv {
+ rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&sdmmc {
+ cap-mmc-highspeed;
+ disable-wp;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <0>;
+ status = "okay";
+};
+
+&u2phy0 {
+ status = "okay";
+
+ u2phy0_host: host-port {
+ phy-supply = <&vcc_host>;
+ status = "okay";
+ };
+
+ u2phy0_otg: otg-port {
+ phy-supply = <&vcc_host>;
+ status = "okay";
+ };
+};
+
+&u2phy1 {
+ status = "okay";
+
+ u2phy1_host: host-port {
+ phy-supply = <&vcc_host>;
+ status = "okay";
+ };
+
+ u2phy1_otg: otg-port {
+ phy-supply = <&vcc_host>;
+ status = "okay";
+ };
+};
+
+&uart2 {
+ pinctrl-0 = <&uart21_xfer>;
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host2_ehci {
+ status = "okay";
+};
+
+&usb_host2_ohci {
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
+};
+
+&vop {
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
--
2.11.0
^ permalink raw reply related
* Re: [PATCH v2 1/2] dt-bindings: Add ipsps1 as a trivial device
From: Milton Miller II @ 2019-08-11 22:06 UTC (permalink / raw)
To: John Wang
Cc: robh+dt, mark.rutland, trivial, linux, venture, jgebben,
anson.huang, devicetree, openbmc, duanzhijia01, mine260309
In-Reply-To: <20190810095325.5333-1-wangzqbj@inspur.com>
Around 08/10/2019 04:54AM in some timezone, John Wang wrote:
>The ipsps1 is an Inspur Power System power supply unit
>
>Signed-off-by: John Wang <wangzqbj@inspur.com>
>---
>v2:
> - No changes.
>---
> Documentation/devicetree/bindings/trivial-devices.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
>diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml
>b/Documentation/devicetree/bindings/trivial-devices.yaml
>index 747fd3f689dc..63960c7d949a 100644
>--- a/Documentation/devicetree/bindings/trivial-devices.yaml
>+++ b/Documentation/devicetree/bindings/trivial-devices.yaml
>@@ -101,6 +101,8 @@ properties:
> # Infineon TLV493D-A1B6 I2C 3D Magnetic Sensor
> - infineon,tlv493d-a1b6
> # Intersil ISL29028 Ambient Light and Proximity Sensor
>+ - inspur,ipsps1
>+ # Inspur Power System power supply unit version 1
> - isil,isl29028
The comment describing your entry should go abvoe your entry, and
your new entry (starting with the comment) should be before the
Intersil entry comment line.
> # Intersil ISL29030 Ambient Light and Proximity Sensor
> - isil,isl29030
>--
>2.17.1
>
>
Milton
^ permalink raw reply
* Re: [PATCH v5 00/18] add thermal driver for h6
From: Clément Péron @ 2019-08-11 21:14 UTC (permalink / raw)
To: Yangtao Li, rui.zhang, edubezval, daniel.lezcano, robh+dt,
mark.rutland, maxime.ripard, wens, mchehab+samsung, davem, gregkh,
Jonathan.Cameron, nicolas.ferre
Cc: linux-pm, devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <20190810052829.6032-1-tiny.windzz@gmail.com>
Hi Yangtao,
On 10/08/2019 07:28, Yangtao Li wrote:
> This patchset add support for A64, H3, H5, H6 and R40 thermal sensor.
Could you add the device-tree configuration in the same series?
This will allow user to test it.
Thanks,
Clément
>
> Thx to Icenowy and Vasily.
>
> BTY, do a cleanup in thermal makfile.
>
> Icenowy Zheng (3):
> thermal: sun8i: allow to use custom temperature calculation function
> thermal: sun8i: add support for Allwinner H5 thermal sensor
> thermal: sun8i: add support for Allwinner R40 thermal sensor
>
> Vasily Khoruzhick (1):
> thermal: sun8i: add thermal driver for A64
>
> Yangtao Li (14):
> thermal: sun8i: add thermal driver for h6
> dt-bindings: thermal: add binding document for h6 thermal controller
> thermal: fix indentation in makefile
> thermal: sun8i: get ths sensor number from device compatible
> thermal: sun8i: rework for sun8i_ths_get_temp()
> thermal: sun8i: get ths init func from device compatible
> thermal: sun8i: rework for ths irq handler func
> thermal: sun8i: support mod clocks
> thermal: sun8i: rework for ths calibrate func
> dt-bindings: thermal: add binding document for h3 thermal controller
> thermal: sun8i: add thermal driver for h3
> dt-bindings: thermal: add binding document for a64 thermal controller
> dt-bindings: thermal: add binding document for h5 thermal controller
> dt-bindings: thermal: add binding document for r40 thermal controller
>
> .../bindings/thermal/sun8i-thermal.yaml | 157 +++++
> MAINTAINERS | 7 +
> drivers/thermal/Kconfig | 14 +
> drivers/thermal/Makefile | 9 +-
> drivers/thermal/sun8i_thermal.c | 596 ++++++++++++++++++
> 5 files changed, 779 insertions(+), 4 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/thermal/sun8i-thermal.yaml
> create mode 100644 drivers/thermal/sun8i_thermal.c
> ---
> v5:
> -add more support
> -some trival fix
> ---
> 2.17.1
>
>
^ permalink raw reply
* Re: [PATCH v4 0/4] Add drivers for auo, kd101n80-45na and boe, tv101wum-nl6 panels
From: Sam Ravnborg @ 2019-08-11 21:11 UTC (permalink / raw)
To: Jitao Shi
Cc: Mark Rutland, devicetree, David Airlie, stonea168, dri-devel,
Ajay Kumar, Vincent Palatin, cawa.cheng, yingjoe.chen,
Thierry Reding, Sean Paul, linux-pwm, Pawel Moll, Ian Campbell,
Rob Herring, linux-mediatek, Russell King, Matthias Brugger,
eddie.huang, linux-arm-kernel, Rahul Sharma, srv_heupstream,
linux-kernel, Sascha Hauer, Andy Yan
In-Reply-To: <20190811091001.49555-1-jitao.shi@mediatek.com>
Hi Jitao.
> .../display/panel/auo,kd101n80-45na.txt | 34 +
> .../display/panel/boe,tv101wum-nl6.txt | 34 +
panel bindings are in the process of being migrated to the new
meta-schema format.
Therefore new bindings should preferably also follow the new format.
Can you please look into this.
In upstream and drm-misc-next there is already some examples.
Note: It is not a hard rule that new bindings shall be in
the new meta-schema format (.yaml extension), but as this is
best practice now it is preferred.
Same goes for display bindings btw.
Sam
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* [PATCH v10 15/15] ARM: dts: tegra30: Add External Memory Controller node
From: Dmitry Osipenko @ 2019-08-11 21:00 UTC (permalink / raw)
To: Rob Herring, Michael Turquette, Joseph Lo, Thierry Reding,
Jonathan Hunter, Peter De Schrijver, Prashant Gaikwad,
Stephen Boyd
Cc: devicetree, linux-clk, linux-tegra, linux-kernel
In-Reply-To: <20190811210043.20122-1-digetx@gmail.com>
Add External Memory Controller node to the device-tree.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/boot/dts/tegra30.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index e074258d4518..8355264e2265 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -732,6 +732,15 @@
#reset-cells = <1>;
};
+ memory-controller@7000f400 {
+ compatible = "nvidia,tegra30-emc";
+ reg = <0x7000f400 0x400>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA30_CLK_EMC>;
+
+ nvidia,memory-controller = <&mc>;
+ };
+
fuse@7000f800 {
compatible = "nvidia,tegra30-efuse";
reg = <0x7000f800 0x400>;
--
2.22.0
^ permalink raw reply related
* [PATCH v10 14/15] memory: tegra: Consolidate registers definition into common header
From: Dmitry Osipenko @ 2019-08-11 21:00 UTC (permalink / raw)
To: Rob Herring, Michael Turquette, Joseph Lo, Thierry Reding,
Jonathan Hunter, Peter De Schrijver, Prashant Gaikwad,
Stephen Boyd
Cc: devicetree, linux-clk, linux-tegra, linux-kernel
In-Reply-To: <20190811210043.20122-1-digetx@gmail.com>
The Memory Controller registers definition is sparse and duplicated,
let's consolidate everything into a common place for consistency.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/memory/tegra/mc.c | 30 -------------------
drivers/memory/tegra/mc.h | 52 +++++++++++++++++++++++++++++----
drivers/memory/tegra/tegra124.c | 20 -------------
drivers/memory/tegra/tegra30.c | 19 ------------
4 files changed, 47 insertions(+), 74 deletions(-)
diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index 1bad7f238881..955f1d3f6b6a 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -18,36 +18,6 @@
#include "mc.h"
-#define MC_INTSTATUS 0x000
-
-#define MC_INTMASK 0x004
-
-#define MC_ERR_STATUS 0x08
-#define MC_ERR_STATUS_TYPE_SHIFT 28
-#define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (6 << MC_ERR_STATUS_TYPE_SHIFT)
-#define MC_ERR_STATUS_TYPE_MASK (0x7 << MC_ERR_STATUS_TYPE_SHIFT)
-#define MC_ERR_STATUS_READABLE (1 << 27)
-#define MC_ERR_STATUS_WRITABLE (1 << 26)
-#define MC_ERR_STATUS_NONSECURE (1 << 25)
-#define MC_ERR_STATUS_ADR_HI_SHIFT 20
-#define MC_ERR_STATUS_ADR_HI_MASK 0x3
-#define MC_ERR_STATUS_SECURITY (1 << 17)
-#define MC_ERR_STATUS_RW (1 << 16)
-
-#define MC_ERR_ADR 0x0c
-
-#define MC_GART_ERROR_REQ 0x30
-#define MC_DECERR_EMEM_OTHERS_STATUS 0x58
-#define MC_SECURITY_VIOLATION_STATUS 0x74
-
-#define MC_EMEM_ARB_CFG 0x90
-#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) (((x) & 0x1ff) << 0)
-#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
-#define MC_EMEM_ARB_MISC0 0xd8
-
-#define MC_EMEM_ADR_CFG 0x54
-#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
-
static const struct of_device_id tegra_mc_of_match[] = {
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
{ .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h
index cd52628c2b96..957c6eb74ff9 100644
--- a/drivers/memory/tegra/mc.h
+++ b/drivers/memory/tegra/mc.h
@@ -12,6 +12,37 @@
#include <soc/tegra/mc.h>
+#define MC_INTSTATUS 0x00
+#define MC_INTMASK 0x04
+#define MC_ERR_STATUS 0x08
+#define MC_ERR_ADR 0x0c
+#define MC_GART_ERROR_REQ 0x30
+#define MC_EMEM_ADR_CFG 0x54
+#define MC_DECERR_EMEM_OTHERS_STATUS 0x58
+#define MC_SECURITY_VIOLATION_STATUS 0x74
+#define MC_EMEM_ARB_CFG 0x90
+#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
+#define MC_EMEM_ARB_TIMING_RCD 0x98
+#define MC_EMEM_ARB_TIMING_RP 0x9c
+#define MC_EMEM_ARB_TIMING_RC 0xa0
+#define MC_EMEM_ARB_TIMING_RAS 0xa4
+#define MC_EMEM_ARB_TIMING_FAW 0xa8
+#define MC_EMEM_ARB_TIMING_RRD 0xac
+#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
+#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
+#define MC_EMEM_ARB_TIMING_R2R 0xb8
+#define MC_EMEM_ARB_TIMING_W2W 0xbc
+#define MC_EMEM_ARB_TIMING_R2W 0xc0
+#define MC_EMEM_ARB_TIMING_W2R 0xc4
+#define MC_EMEM_ARB_DA_TURNS 0xd0
+#define MC_EMEM_ARB_DA_COVERS 0xd4
+#define MC_EMEM_ARB_MISC0 0xd8
+#define MC_EMEM_ARB_MISC1 0xdc
+#define MC_EMEM_ARB_RING1_THROTTLE 0xe0
+#define MC_EMEM_ARB_OVERRIDE 0xe8
+#define MC_TIMING_CONTROL_DBG 0xf8
+#define MC_TIMING_CONTROL 0xfc
+
#define MC_INT_DECERR_MTS BIT(16)
#define MC_INT_SECERR_SEC BIT(13)
#define MC_INT_DECERR_VPR BIT(12)
@@ -22,17 +53,28 @@
#define MC_INT_INVALID_GART_PAGE BIT(7)
#define MC_INT_DECERR_EMEM BIT(6)
-#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
+#define MC_ERR_STATUS_TYPE_SHIFT 28
+#define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (0x6 << 28)
+#define MC_ERR_STATUS_TYPE_MASK (0x7 << 28)
+#define MC_ERR_STATUS_READABLE BIT(27)
+#define MC_ERR_STATUS_WRITABLE BIT(26)
+#define MC_ERR_STATUS_NONSECURE BIT(25)
+#define MC_ERR_STATUS_ADR_HI_SHIFT 20
+#define MC_ERR_STATUS_ADR_HI_MASK 0x3
+#define MC_ERR_STATUS_SECURITY BIT(17)
+#define MC_ERR_STATUS_RW BIT(16)
+
+#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
+
+#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x) ((x) & 0x1ff)
+#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
+
#define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK 0x1ff
#define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE BIT(30)
#define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE BIT(31)
-#define MC_EMEM_ARB_OVERRIDE 0xe8
#define MC_EMEM_ARB_OVERRIDE_EACK_MASK 0x3
-#define MC_TIMING_CONTROL_DBG 0xf8
-
-#define MC_TIMING_CONTROL 0xfc
#define MC_TIMING_UPDATE BIT(0)
static inline u32 mc_readl(struct tegra_mc *mc, unsigned long offset)
diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c
index 5d0ccb2be206..4d80c81a4581 100644
--- a/drivers/memory/tegra/tegra124.c
+++ b/drivers/memory/tegra/tegra124.c
@@ -10,26 +10,6 @@
#include "mc.h"
-#define MC_EMEM_ARB_CFG 0x90
-#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
-#define MC_EMEM_ARB_TIMING_RCD 0x98
-#define MC_EMEM_ARB_TIMING_RP 0x9c
-#define MC_EMEM_ARB_TIMING_RC 0xa0
-#define MC_EMEM_ARB_TIMING_RAS 0xa4
-#define MC_EMEM_ARB_TIMING_FAW 0xa8
-#define MC_EMEM_ARB_TIMING_RRD 0xac
-#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
-#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
-#define MC_EMEM_ARB_TIMING_R2R 0xb8
-#define MC_EMEM_ARB_TIMING_W2W 0xbc
-#define MC_EMEM_ARB_TIMING_R2W 0xc0
-#define MC_EMEM_ARB_TIMING_W2R 0xc4
-#define MC_EMEM_ARB_DA_TURNS 0xd0
-#define MC_EMEM_ARB_DA_COVERS 0xd4
-#define MC_EMEM_ARB_MISC0 0xd8
-#define MC_EMEM_ARB_MISC1 0xdc
-#define MC_EMEM_ARB_RING1_THROTTLE 0xe0
-
static const struct tegra_mc_client tegra124_mc_clients[] = {
{
.id = 0x00,
diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c
index b1226d3f067f..fdc0b342cf80 100644
--- a/drivers/memory/tegra/tegra30.c
+++ b/drivers/memory/tegra/tegra30.c
@@ -10,25 +10,6 @@
#include "mc.h"
-#define MC_EMEM_ARB_CFG 0x90
-#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
-#define MC_EMEM_ARB_TIMING_RCD 0x98
-#define MC_EMEM_ARB_TIMING_RP 0x9c
-#define MC_EMEM_ARB_TIMING_RC 0xa0
-#define MC_EMEM_ARB_TIMING_RAS 0xa4
-#define MC_EMEM_ARB_TIMING_FAW 0xa8
-#define MC_EMEM_ARB_TIMING_RRD 0xac
-#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
-#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
-#define MC_EMEM_ARB_TIMING_R2R 0xb8
-#define MC_EMEM_ARB_TIMING_W2W 0xbc
-#define MC_EMEM_ARB_TIMING_R2W 0xc0
-#define MC_EMEM_ARB_TIMING_W2R 0xc4
-#define MC_EMEM_ARB_DA_TURNS 0xd0
-#define MC_EMEM_ARB_DA_COVERS 0xd4
-#define MC_EMEM_ARB_MISC0 0xd8
-#define MC_EMEM_ARB_RING1_THROTTLE 0xe0
-
static const unsigned long tegra30_mc_emem_regs[] = {
MC_EMEM_ARB_CFG,
MC_EMEM_ARB_OUTSTANDING_REQ,
--
2.22.0
^ permalink raw reply related
* [PATCH v10 13/15] memory: tegra: Ensure timing control debug features are disabled
From: Dmitry Osipenko @ 2019-08-11 21:00 UTC (permalink / raw)
To: Rob Herring, Michael Turquette, Joseph Lo, Thierry Reding,
Jonathan Hunter, Peter De Schrijver, Prashant Gaikwad,
Stephen Boyd
Cc: devicetree, linux-clk, linux-tegra, linux-kernel
In-Reply-To: <20190811210043.20122-1-digetx@gmail.com>
Timing control debug features should be disabled at a boot time, but you
never now and hence it's better to disable them explicitly because some of
those features are crucial for the driver to do a proper thing.
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/memory/tegra/mc.c | 3 +++
drivers/memory/tegra/mc.h | 2 ++
2 files changed, 5 insertions(+)
diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index 43819e8df95c..1bad7f238881 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -657,6 +657,9 @@ static int tegra_mc_probe(struct platform_device *pdev)
} else
#endif
{
+ /* ensure that debug features are disabled */
+ mc_writel(mc, 0x00000000, MC_TIMING_CONTROL_DBG);
+
err = tegra_mc_setup_latency_allowance(mc);
if (err < 0) {
dev_err(&pdev->dev,
diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h
index 410efc4d7e7b..cd52628c2b96 100644
--- a/drivers/memory/tegra/mc.h
+++ b/drivers/memory/tegra/mc.h
@@ -30,6 +30,8 @@
#define MC_EMEM_ARB_OVERRIDE 0xe8
#define MC_EMEM_ARB_OVERRIDE_EACK_MASK 0x3
+#define MC_TIMING_CONTROL_DBG 0xf8
+
#define MC_TIMING_CONTROL 0xfc
#define MC_TIMING_UPDATE BIT(0)
--
2.22.0
^ permalink raw reply related
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