* [PATCH v2 01/10] PCIe: qcom: add missing ipq806x clocks in PCIe driver
From: Ansuel Smith @ 2020-04-02 12:11 UTC (permalink / raw)
To: Andy Gross
Cc: Ansuel Smith, Sham Muthayyan, Bjorn Andersson, Bjorn Helgaas,
Rob Herring, Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi,
Andrew Murray, Philipp Zabel, linux-arm-msm, linux-pci,
devicetree, linux-kernel
In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com>
Aux and Ref clk are missing in pcie qcom driver.
Add support in the driver to fix pcie inizialization in ipq806x.
Fixes: 82a82383 PCI: qcom: Add Qualcomm PCIe controller driver
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 38 ++++++++++++++++++++++----
1 file changed, 33 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 5ea527a6bd9f..f958c535de6e 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -88,6 +88,8 @@ struct qcom_pcie_resources_2_1_0 {
struct clk *iface_clk;
struct clk *core_clk;
struct clk *phy_clk;
+ struct clk *aux_clk;
+ struct clk *ref_clk;
struct reset_control *pci_reset;
struct reset_control *axi_reset;
struct reset_control *ahb_reset;
@@ -246,6 +248,14 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
if (IS_ERR(res->phy_clk))
return PTR_ERR(res->phy_clk);
+ res->aux_clk = devm_clk_get(dev, "aux");
+ if (IS_ERR(res->aux_clk))
+ return PTR_ERR(res->aux_clk);
+
+ res->ref_clk = devm_clk_get(dev, "ref");
+ if (IS_ERR(res->ref_clk))
+ return PTR_ERR(res->ref_clk);
+
res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
if (IS_ERR(res->pci_reset))
return PTR_ERR(res->pci_reset);
@@ -278,6 +288,8 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
clk_disable_unprepare(res->iface_clk);
clk_disable_unprepare(res->core_clk);
clk_disable_unprepare(res->phy_clk);
+ clk_disable_unprepare(res->aux_clk);
+ clk_disable_unprepare(res->ref_clk);
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
}
@@ -307,16 +319,28 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
goto err_assert_ahb;
}
+ ret = clk_prepare_enable(res->core_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable core clock\n");
+ goto err_clk_core;
+ }
+
ret = clk_prepare_enable(res->phy_clk);
if (ret) {
dev_err(dev, "cannot prepare/enable phy clock\n");
goto err_clk_phy;
}
- ret = clk_prepare_enable(res->core_clk);
+ ret = clk_prepare_enable(res->aux_clk);
if (ret) {
- dev_err(dev, "cannot prepare/enable core clock\n");
- goto err_clk_core;
+ dev_err(dev, "cannot prepare/enable aux clock\n");
+ goto err_clk_aux;
+ }
+
+ ret = clk_prepare_enable(res->ref_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable ref clock\n");
+ goto err_clk_ref;
}
ret = reset_control_deassert(res->ahb_reset);
@@ -372,10 +396,14 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
return 0;
err_deassert_ahb:
- clk_disable_unprepare(res->core_clk);
-err_clk_core:
+ clk_disable_unprepare(res->ref_clk);
+err_clk_ref:
+ clk_disable_unprepare(res->aux_clk);
+err_clk_aux:
clk_disable_unprepare(res->phy_clk);
err_clk_phy:
+ clk_disable_unprepare(res->core_clk);
+err_clk_core:
clk_disable_unprepare(res->iface_clk);
err_assert_ahb:
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
--
2.25.1
^ permalink raw reply related
* [PATCH v2 02/10] devicetree: bindings: pci: add missing clks to qcom,pcie
From: Ansuel Smith @ 2020-04-02 12:11 UTC (permalink / raw)
To: Andy Gross
Cc: Ansuel Smith, Rob Herring, Bjorn Andersson, Bjorn Helgaas,
Rob Herring, Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi,
Andrew Murray, Philipp Zabel, linux-arm-msm, linux-pci,
devicetree, linux-kernel
In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com>
Document missing clks used in ipq806x soc.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/pci/qcom,pcie.txt | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index 981b4de12807..becdbdc0fffa 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -90,6 +90,8 @@
Definition: Should contain the following entries
- "core" Clocks the pcie hw block
- "phy" Clocks the pcie PHY block
+ - "aux" Clocks the pcie AUX block
+ - "ref" Clocks the pcie ref block
- clock-names:
Usage: required for apq8084/ipq4019
Value type: <stringlist>
@@ -277,8 +279,10 @@
<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc PCIE_A_CLK>,
<&gcc PCIE_H_CLK>,
- <&gcc PCIE_PHY_CLK>;
- clock-names = "core", "iface", "phy";
+ <&gcc PCIE_PHY_CLK>,
+ <&gcc PCIE_AUX_CLK>,
+ <&gcc PCIE_ALT_REF_CLK>;
+ clock-names = "core", "iface", "phy", "aux", "ref";
resets = <&gcc PCIE_ACLK_RESET>,
<&gcc PCIE_HCLK_RESET>,
<&gcc PCIE_POR_RESET>,
--
2.25.1
^ permalink raw reply related
* [PATCH v2 03/10] PCIe: qcom: change duplicate PCI reset to phy reset
From: Ansuel Smith @ 2020-04-02 12:11 UTC (permalink / raw)
To: Andy Gross
Cc: Abhishek Sahu, Ansuel Smith, Bjorn Andersson, Bjorn Helgaas,
Rob Herring, Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi,
Andrew Murray, Philipp Zabel, linux-arm-msm, linux-pci,
devicetree, linux-kernel
In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com>
From: Abhishek Sahu <absahu@codeaurora.org>
The deinit issues reset_control_assert for pci twice and does not contain
phy reset.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index f958c535de6e..1fcc7fed8443 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -284,7 +284,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
reset_control_assert(res->axi_reset);
reset_control_assert(res->ahb_reset);
reset_control_assert(res->por_reset);
- reset_control_assert(res->pci_reset);
+ reset_control_assert(res->phy_reset);
clk_disable_unprepare(res->iface_clk);
clk_disable_unprepare(res->core_clk);
clk_disable_unprepare(res->phy_clk);
--
2.25.1
^ permalink raw reply related
* [PATCH v2 04/10] PCIe: qcom: Fixed pcie_phy_clk branch issue
From: Ansuel Smith @ 2020-04-02 12:11 UTC (permalink / raw)
To: Andy Gross
Cc: Ansuel Smith, Abhishek Sahu, Bjorn Andersson, Bjorn Helgaas,
Rob Herring, Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi,
Andrew Murray, Philipp Zabel, linux-arm-msm, linux-pci,
devicetree, linux-kernel
In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com>
Following backtraces are observed in PCIe deinit operation.
Hardware name: Qualcomm (Flattened Device Tree)
(unwind_backtrace) from [] (show_stack+0x10/0x14)
(show_stack) from [] (dump_stack+0x84/0x98)
(dump_stack) from [] (warn_slowpath_common+0x9c/0xb8)
(warn_slowpath_common) from [] (warn_slowpath_fmt+0x30/0x40)
(warn_slowpath_fmt) from [] (clk_branch_wait+0x114/0x120)
(clk_branch_wait) from [] (clk_core_disable+0xd0/0x1f4)
(clk_core_disable) from [] (clk_disable+0x24/0x30)
(clk_disable) from [] (qcom_pcie_deinit_v0+0x6c/0xb8)
(qcom_pcie_deinit_v0) from [] (qcom_pcie_host_init+0xe0/0xe8)
(qcom_pcie_host_init) from [] (dw_pcie_host_init+0x3b0/0x538)
(dw_pcie_host_init) from [] (qcom_pcie_probe+0x20c/0x2e4)
pcie_phy_clk is generated for PCIe controller itself and the
GCC controls its branch operation. This error is coming since
the assert operations turn off the parent clock before branch
clock. Now this patch moves clk_disable_unprepare before assert
operations.
Similarly, during probe function, the clock branch operation
should be done after dessert operation. Currently, it does not
generate any error since bootloader enables the pcie_phy_clk
but the same error is coming during probe, if bootloader
disables pcie_phy_clk.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 16 +++++++---------
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 1fcc7fed8443..596731b54728 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -280,6 +280,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
{
struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
+ clk_disable_unprepare(res->phy_clk);
reset_control_assert(res->pci_reset);
reset_control_assert(res->axi_reset);
reset_control_assert(res->ahb_reset);
@@ -287,7 +288,6 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
reset_control_assert(res->phy_reset);
clk_disable_unprepare(res->iface_clk);
clk_disable_unprepare(res->core_clk);
- clk_disable_unprepare(res->phy_clk);
clk_disable_unprepare(res->aux_clk);
clk_disable_unprepare(res->ref_clk);
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
@@ -325,12 +325,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
goto err_clk_core;
}
- ret = clk_prepare_enable(res->phy_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable phy clock\n");
- goto err_clk_phy;
- }
-
ret = clk_prepare_enable(res->aux_clk);
if (ret) {
dev_err(dev, "cannot prepare/enable aux clock\n");
@@ -383,6 +377,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
return ret;
}
+ ret = clk_prepare_enable(res->phy_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable phy clock\n");
+ goto err_deassert_ahb;
+ }
+
/* wait for clock acquisition */
usleep_range(1000, 1500);
@@ -400,8 +400,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
err_clk_ref:
clk_disable_unprepare(res->aux_clk);
err_clk_aux:
- clk_disable_unprepare(res->phy_clk);
-err_clk_phy:
clk_disable_unprepare(res->core_clk);
err_clk_core:
clk_disable_unprepare(res->iface_clk);
--
2.25.1
^ permalink raw reply related
* [PATCH v2 05/10] PCIe: qcom: add missing reset for ipq806x
From: Ansuel Smith @ 2020-04-02 12:11 UTC (permalink / raw)
To: Andy Gross
Cc: Ansuel Smith, Sham Muthayyan, Bjorn Andersson, Bjorn Helgaas,
Rob Herring, Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi,
Andrew Murray, Philipp Zabel, linux-arm-msm, linux-pci,
devicetree, linux-kernel
In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com>
Add missing ext reset used by ipq806x SoC in PCIe qcom driver.
Fixes: 82a82383 PCI: qcom: Add Qualcomm PCIe controller driver
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 596731b54728..211a1aa7d0f1 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -95,6 +95,7 @@ struct qcom_pcie_resources_2_1_0 {
struct reset_control *ahb_reset;
struct reset_control *por_reset;
struct reset_control *phy_reset;
+ struct reset_control *ext_reset;
struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
};
@@ -272,6 +273,10 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
if (IS_ERR(res->por_reset))
return PTR_ERR(res->por_reset);
+ res->ext_reset = devm_reset_control_get_exclusive(dev, "ext");
+ if (IS_ERR(res->ext_reset))
+ return PTR_ERR(res->ext_reset);
+
res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
return PTR_ERR_OR_ZERO(res->phy_reset);
}
@@ -285,6 +290,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
reset_control_assert(res->axi_reset);
reset_control_assert(res->ahb_reset);
reset_control_assert(res->por_reset);
+ reset_control_assert(res->ext_reset);
reset_control_assert(res->phy_reset);
clk_disable_unprepare(res->iface_clk);
clk_disable_unprepare(res->core_clk);
@@ -343,6 +349,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
goto err_deassert_ahb;
}
+ ret = reset_control_deassert(res->ext_reset);
+ if (ret) {
+ dev_err(dev, "cannot assert ext reset\n");
+ goto err_deassert_ahb;
+ }
+
/* enable PCIe clocks and resets */
val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
val &= ~BIT(0);
--
2.25.1
^ permalink raw reply related
* [PATCH v2 06/10] devicetree: bindings: pci: add ext reset to qcom,pcie
From: Ansuel Smith @ 2020-04-02 12:11 UTC (permalink / raw)
To: Andy Gross
Cc: Ansuel Smith, Rob Herring, Bjorn Andersson, Bjorn Helgaas,
Rob Herring, Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi,
Andrew Murray, Philipp Zabel, linux-arm-msm, linux-pci,
devicetree, linux-kernel
In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com>
Document ext reset used in ipq806x soc by qcom pcie driver
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/pci/qcom,pcie.txt | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index becdbdc0fffa..6efcef040741 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -179,6 +179,7 @@
- "pwr" PWR reset
- "ahb" AHB reset
- "phy_ahb" PHY AHB reset
+ - "ext" EXT reset
- reset-names:
Usage: required for ipq8074
@@ -287,8 +288,9 @@
<&gcc PCIE_HCLK_RESET>,
<&gcc PCIE_POR_RESET>,
<&gcc PCIE_PCI_RESET>,
- <&gcc PCIE_PHY_RESET>;
- reset-names = "axi", "ahb", "por", "pci", "phy";
+ <&gcc PCIE_PHY_RESET>,
+ <&gcc PCIE_EXT_RESET>;
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
pinctrl-0 = <&pcie_pins_default>;
pinctrl-names = "default";
};
--
2.25.1
^ permalink raw reply related
* [PATCH v2 08/10] PCIe: qcom: add ipq8064 rev2 variant and set tx term offset
From: Ansuel Smith @ 2020-04-02 12:11 UTC (permalink / raw)
To: Andy Gross
Cc: Sham Muthayyan, Ansuel Smith, Bjorn Andersson, Bjorn Helgaas,
Rob Herring, Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi,
Andrew Murray, Philipp Zabel, linux-arm-msm, linux-pci,
devicetree, linux-kernel
In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com>
From: Sham Muthayyan <smuthayy@codeaurora.org>
Add tx term offset support to pcie qcom driver need in some revision of
the ipq806x SoC.
Ipq8064 have tx term offset set to 7.
Ipq8064 v2 revision and ipq8065 have the tx term offset set to 0.
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 77b1ab7e23a3..8047ac7dc8c7 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -45,6 +45,9 @@
#define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
#define PCIE20_PARF_PHY_CTRL 0x40
+#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(12, 16)
+#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) (x << 16)
+
#define PCIE20_PARF_PHY_REFCLK 0x4C
#define REF_SSP_EN BIT(16)
#define REF_USE_PAD BIT(12)
@@ -112,6 +115,7 @@ struct qcom_pcie_resources_2_1_0 {
struct reset_control *phy_reset;
struct reset_control *ext_reset;
struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
+ uint8_t phy_tx0_term_offset;
};
struct qcom_pcie_resources_1_0_0 {
@@ -302,6 +306,11 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
if (IS_ERR(res->ext_reset))
return PTR_ERR(res->ext_reset);
+ if (of_device_is_compatible(dev->of_node, "qcom,pcie-ipq8064"))
+ res->phy_tx0_term_offset = 7;
+ else
+ res->phy_tx0_term_offset = 0;
+
res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
return PTR_ERR_OR_ZERO(res->phy_reset);
}
@@ -381,6 +390,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);
+ /* set TX termination offset */
+ qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_CTRL,
+ PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK,
+ PHY_CTRL_PHY_TX0_TERM_OFFSET(res->phy_tx0_term_offset));
+
/* PARF programming */
writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) |
PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) |
@@ -1494,6 +1508,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
{ .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
+ { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 },
{ .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
{ .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
{ .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
--
2.25.1
^ permalink raw reply related
* [PATCH v2 09/10] devicetree: bindings: pci: add ipq8064 rev 2 variant to qcom,pcie
From: Ansuel Smith @ 2020-04-02 12:11 UTC (permalink / raw)
To: Andy Gross
Cc: Ansuel Smith, Bjorn Andersson, Bjorn Helgaas, Rob Herring,
Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi, Andrew Murray,
Philipp Zabel, linux-arm-msm, linux-pci, devicetree, linux-kernel
In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com>
Document qcom,pcie-ipq8064-v2 needed to use different phy_tx0_term_offset.
In ipq8064 phy_tx0_term_offset is 7, in rev 2, ipq8065 and other SoC it's
set to 0 by default.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
.../devicetree/bindings/pci/qcom,pcie.txt | 42 +++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index 6efcef040741..b699f126ea29 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -5,6 +5,7 @@
Value type: <stringlist>
Definition: Value should contain
- "qcom,pcie-ipq8064" for ipq8064
+ - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
- "qcom,pcie-apq8064" for apq8064
- "qcom,pcie-apq8084" for apq8084
- "qcom,pcie-msm8996" for msm8996 or apq8096
@@ -295,6 +296,47 @@
pinctrl-names = "default";
};
+* Example for ipq8064 rev 2 or ipq8065
+ pcie@1b500000 {
+ compatible = "qcom,pcie-ipq8064-v2", "snps,dw-pcie";
+ reg = <0x1b500000 0x1000
+ 0x1b502000 0x80
+ 0x1b600000 0x100
+ 0x0ff00000 0x100000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
+ 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
+ interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ clocks = <&gcc PCIE_A_CLK>,
+ <&gcc PCIE_H_CLK>,
+ <&gcc PCIE_PHY_CLK>,
+ <&gcc PCIE_AUX_CLK>,
+ <&gcc PCIE_ALT_REF_CLK>;
+ clock-names = "core", "iface", "phy", "aux", "ref";
+ resets = <&gcc PCIE_ACLK_RESET>,
+ <&gcc PCIE_HCLK_RESET>,
+ <&gcc PCIE_POR_RESET>,
+ <&gcc PCIE_PCI_RESET>,
+ <&gcc PCIE_PHY_RESET>,
+ <&gcc PCIE_EXT_RESET>;
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
+ pinctrl-0 = <&pcie_pins_default>;
+ pinctrl-names = "default";
+ };
+
* Example for apq8084
pcie0@fc520000 {
compatible = "qcom,pcie-apq8084", "snps,dw-pcie";
--
2.25.1
^ permalink raw reply related
* [PATCH v2 10/10] PCIe: qcom: add Force GEN1 support
From: Ansuel Smith @ 2020-04-02 12:11 UTC (permalink / raw)
To: Andy Gross
Cc: Sham Muthayyan, Ansuel Smith, Bjorn Andersson, Bjorn Helgaas,
Rob Herring, Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi,
Andrew Murray, Philipp Zabel, linux-arm-msm, linux-pci,
devicetree, linux-kernel
In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com>
From: Sham Muthayyan <smuthayy@codeaurora.org>
Add Force GEN1 support needed in some ipq806x board
that needs to limit some pcie line to gen1 for some
hardware limitation.
This is set by the max-link-speed dts entry and needed
by some soc based on ipq806x. (for example Netgear R7800
router)
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 8047ac7dc8c7..2212e9498b91 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -27,6 +27,7 @@
#include <linux/slab.h>
#include <linux/types.h>
+#include "../../pci.h"
#include "pcie-designware.h"
#define PCIE20_PARF_SYS_CTRL 0x00
@@ -99,6 +100,8 @@
#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
#define SLV_ADDR_SPACE_SZ 0x10000000
+#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xA0
+
#define DEVICE_TYPE_RC 0x4
#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
@@ -199,6 +202,7 @@ struct qcom_pcie {
struct phy *phy;
struct gpio_desc *reset;
const struct qcom_pcie_ops *ops;
+ bool force_gen1;
};
#define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
@@ -441,6 +445,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
/* wait for clock acquisition */
usleep_range(1000, 1500);
+ if (pcie->force_gen1) {
+ writel_relaxed((readl_relaxed(
+ pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2) | 1),
+ pcie->pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
+ }
/* Set the Max TLP size to 2K, instead of using default of 4K */
@@ -1440,6 +1449,10 @@ static int qcom_pcie_probe(struct platform_device *pdev)
goto err_pm_runtime_put;
}
+ ret = of_pci_get_max_link_speed(pdev->dev.of_node);
+ if (ret == 1)
+ pcie->force_gen1 = true;
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
pcie->parf = devm_ioremap_resource(dev, res);
if (IS_ERR(pcie->parf)) {
--
2.25.1
^ permalink raw reply related
* [PATCH v2 07/10] PCIe: qcom: fix init problem with missing PARF programming
From: Ansuel Smith @ 2020-04-02 12:11 UTC (permalink / raw)
To: Andy Gross
Cc: Ansuel Smith, Bjorn Andersson, Bjorn Helgaas, Rob Herring,
Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi, Andrew Murray,
Philipp Zabel, linux-arm-msm, linux-pci, devicetree, linux-kernel
In-Reply-To: <20200402121148.1767-1-ansuelsmth@gmail.com>
PARF programming was missing and this cause initilizzation problem on
some ipq806x based device (Netgear R7800 for example). This cause a
total lock of the system on kernel load.
Fixes: 82a82383 PCI: qcom: Add Qualcomm PCIe controller driver
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 48 +++++++++++++++++++++-----
1 file changed, 39 insertions(+), 9 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 211a1aa7d0f1..77b1ab7e23a3 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -46,6 +46,9 @@
#define PCIE20_PARF_PHY_CTRL 0x40
#define PCIE20_PARF_PHY_REFCLK 0x4C
+#define REF_SSP_EN BIT(16)
+#define REF_USE_PAD BIT(12)
+
#define PCIE20_PARF_DBI_BASE_ADDR 0x168
#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
@@ -77,6 +80,18 @@
#define DBI_RO_WR_EN 1
#define PERST_DELAY_US 1000
+/* PARF registers */
+#define PCIE20_PARF_PCS_DEEMPH 0x34
+#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) (x << 16)
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) (x << 8)
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) (x << 0)
+
+#define PCIE20_PARF_PCS_SWING 0x38
+#define PCS_SWING_TX_SWING_FULL(x) (x << 8)
+#define PCS_SWING_TX_SWING_LOW(x) (x << 0)
+
+#define PCIE20_PARF_CONFIG_BITS 0x50
+#define PHY_RX0_EQ(x) (x << 24)
#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
#define SLV_ADDR_SPACE_SZ 0x10000000
@@ -184,6 +199,16 @@ struct qcom_pcie {
#define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
+static inline void qcom_clear_and_set_dword(void __iomem *addr,
+ u32 clear_mask, u32 set_mask)
+{
+ u32 val = readl(addr);
+
+ val &= ~clear_mask;
+ val |= set_mask;
+ writel(val, addr);
+}
+
static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
{
gpiod_set_value_cansleep(pcie->reset, 1);
@@ -304,7 +329,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
- u32 val;
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
@@ -355,15 +379,21 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
goto err_deassert_ahb;
}
- /* enable PCIe clocks and resets */
- val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
- val &= ~BIT(0);
- writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+ qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);
+
+ /* PARF programming */
+ writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) |
+ PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) |
+ PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(0x22),
+ pcie->parf + PCIE20_PARF_PCS_DEEMPH);
+ writel(PCS_SWING_TX_SWING_FULL(0x78) |
+ PCS_SWING_TX_SWING_LOW(0x78),
+ pcie->parf + PCIE20_PARF_PCS_SWING);
+ writel(PHY_RX0_EQ(0x4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
- /* enable external reference clock */
- val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
- val |= BIT(16);
- writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
+ /* enable reference clock */
+ qcom_clear_and_set_dword(pcie->parf + PCIE20_PARF_PHY_REFCLK,
+ REF_USE_PAD, REF_SSP_EN);
ret = reset_control_deassert(res->phy_reset);
if (ret) {
--
2.25.1
^ permalink raw reply related
* [PATCH v2 00/10] Multiple fixes in PCIe qcom driver
From: Ansuel Smith @ 2020-04-02 12:11 UTC (permalink / raw)
To: Andy Gross
Cc: Ansuel Smith, Bjorn Andersson, Bjorn Helgaas, Rob Herring,
Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi, Andrew Murray,
Philipp Zabel, linux-arm-msm, linux-pci, devicetree, linux-kernel
This contains multiple fix for PCIe qcom driver.
Some optional reset and clocks were missing.
Fix a problem with no PARF programming that cause kernel lock on load.
Add support to force gen 1 speed if needed. (due to hardware limitation)
Add ipq8064 rev 2 support that use a different tx termination offset.
v2:
* Drop iATU programming (already done in pcie init)
* Use max-link-speed instead of force-gen1 custom definition
* Drop MRRS to 256B (Can't find a realy reason why this was suggested)
* Introduce a new variant for different revision of ipq8064
Abhishek Sahu (1):
PCIe: qcom: change duplicate PCI reset to phy reset
Ansuel Smith (7):
PCIe: qcom: add missing ipq806x clocks in PCIe driver
devicetree: bindings: pci: add missing clks to qcom,pcie
PCIe: qcom: Fixed pcie_phy_clk branch issue
PCIe: qcom: add missing reset for ipq806x
devicetree: bindings: pci: add ext reset to qcom,pcie
PCIe: qcom: fix init problem with missing PARF programming
devicetree: bindings: pci: add ipq8064 rev 2 variant to qcom,pcie
Sham Muthayyan (2):
PCIe: qcom: add ipq8064 rev2 variant and set tx term offset
PCIe: qcom: add Force GEN1 support
.../devicetree/bindings/pci/qcom,pcie.txt | 56 +++++++-
drivers/pci/controller/dwc/pcie-qcom.c | 134 +++++++++++++++---
2 files changed, 167 insertions(+), 23 deletions(-)
--
2.25.1
^ permalink raw reply
* Re: Re: [PATCH v4 1/4] dt-bindings: net: phy: Add support for NXP TJA11xx
From: Oleksij Rempel @ 2020-04-02 11:42 UTC (permalink / raw)
To: Andrew Lunn
Cc: Christian Herber, Rob Herring, Florian Fainelli, Mark Rutland,
devicetree@vger.kernel.org, Marek Vasut, netdev,
linux-kernel@vger.kernel.org, Pengutronix Kernel Team,
David Jander, David S. Miller, Heiner Kallweit
In-Reply-To: <20200323151423.GA32387@lunn.ch>
On Mon, Mar 23, 2020 at 04:14:23PM +0100, Andrew Lunn wrote:
> > Yes, it is one device with two address. This is if you call the entire IC a device. If you look at it from a PHY perspective, it is two devices with 1 address.
> > If you just look at it as a single device, it gets difficult to add PHY specific properties in the future, e.g. master/slave selection.
>
> > In my opinion its important to have some kind of container for the
> > entire IC, but likewise for the individual PHYs.
>
> Yes, we need some sort of representation of two devices.
>
> Logically, the two PHYs are on the same MDIO bus, so you could have
> two nodes on the main bus.
>
> Or you consider the secondary PHY as being on an internal MDIO bus
> which is transparently bridged to the main bus. This is what was
> proposed in the last patchset.
>
> Because this bridge is transparent, the rest of the PHY/MDIO framework
> has no idea about it. So i prefer that we keep with two PHY nodes on
> the main bus. But i still think we need the master PHY to register the
> secondary PHY, due to the missing PHY ID, and the other constrains
> like resets which the master PHY has to handle.
Yes, this is the way how current patches are implemented.
Should dt-binding documentation and PHY changes go via David's tree
upstream? If nobody has strong opinion against it, @David can you
please take them.
Regards,
Oleksij & Marc
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* Re: [PATCH 2/4] dt-bindings: media: rkisp1: move rockchip-isp1 bindings out of staging
From: Johan Jonker @ 2020-04-02 11:35 UTC (permalink / raw)
To: helen.koike
Cc: dafna.hirschfeld, devel, devicetree, ezequiel, heiko,
hverkuil-cisco, karthik.poduval, kernel, linux-kernel,
linux-media, linux-rockchip, mark.rutland, robh+dt
In-Reply-To: <20200402000234.226466-3-helen.koike@collabora.com>
Hi Helen,
> # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> %YAML 1.2
> ---
> $id: http://devicetree.org/schemas/media/rockchip-isp1.yaml#
> $schema: http://devicetree.org/meta-schemas/core.yaml#
>
> title: Rockchip SoC Image Signal Processing unit v1
Where do we need 'v1' for? Is there a 'v2'?
>
> maintainers:
> - Helen Koike <helen.koike@collabora.com>
>
> description: |
> Rockchip ISP1 is the Camera interface for the Rockchip series of SoCs
> which contains image processing, scaling, and compression functions.
>
> properties:
> compatible:
> const: rockchip,rk3399-cif-isp
>
> reg:
> maxItems: 1
>
> interrupts:
> maxItems: 1
>
> iommus:
> maxItems: 1
>
> power-domains:
> maxItems: 1
>
> phys:
> maxItems: 1
> description: phandle for the PHY port
>
> phy-names:
> const: dphy
>
> clocks:
> items:
> - description: ISP clock
> - description: ISP AXI clock clock
> - description: ISP AXI clock wrapper clock
> - description: ISP AHB clock clock
> - description: ISP AHB wrapper clock
>
> clock-names:
> items:
> - const: clk_isp
> - const: aclk_isp
> - const: aclk_isp_wrap
> - const: hclk_isp
> - const: hclk_isp_wrap
>
> # See ./video-interfaces.txt for details
> ports:
> type: object
> additionalProperties: false
>
> properties:
> "#address-cells":
> const: 1
>
> "#size-cells":
> const: 0
>
> port@0:
> type: object
> description: connection point for sensors at MIPI-DPHY RX0
> additionalProperties: false
Nothing required here?
>
> properties:
> "#address-cells":
> const: 1
>
> "#size-cells":
> const: 0
>
> reg:
> const: 0
>
> patternProperties:
> endpoint:
> type: object
> additionalProperties: false
>
> properties:
> reg:
> maxItems: 1
>
> data-lanes:
> minItems: 1
> maxItems: 4
>
> remote-endpoint: true
>
> required:
> - port@0
The use of '@0' makes "#address-cells" and "#size-cells" also a requirement.
- "#address-cells"
- "#size-cells"
>
> required:
> - compatible
How about 'reg'?
- reg
> - interrupts
> - clocks
> - clock-names
> - power-domains
> - iommus
> - phys
> - phy-names
> - ports
>
> additionalProperties: false
>
> examples:
> - |
>
> #include <dt-bindings/clock/rk3399-cru.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/power/rk3399-power.h>
>
> parent0: parent@0 {
> #address-cells = <2>;
> #size-cells = <2>;
>
> isp0: isp0@ff910000 {
> compatible = "rockchip,rk3399-cif-isp";
> reg = <0x0 0xff910000 0x0 0x4000>;
> interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
> clocks = <&cru SCLK_ISP0>,
> <&cru ACLK_ISP0>, <&cru ACLK_ISP0_WRAPPER>,
> <&cru HCLK_ISP0>, <&cru HCLK_ISP0_WRAPPER>;
> clock-names = "clk_isp",
> "aclk_isp", "aclk_isp_wrap",
> "hclk_isp", "hclk_isp_wrap";
> power-domains = <&power RK3399_PD_ISP0>;
> iommus = <&isp0_mmu>;
> phys = <&dphy>;
> phy-names = "dphy";
>
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
>
> port@0 {
> #address-cells = <1>;
> #size-cells = <0>;
> reg = <0>;
>
> mipi_in_wcam: endpoint@0 {
> reg = <0>;
> remote-endpoint = <&wcam_out>;
> data-lanes = <1 2>;
> };
>
> mipi_in_ucam: endpoint@1 {
> reg = <1>;
> remote-endpoint = <&ucam_out>;
> data-lanes = <1>;
> };
> };
> };
> };
>
> i2c7: i2c@ff160000 {
> clock-frequency = <400000>;
> #address-cells = <1>;
> #size-cells = <0>;
Incomplete example.
From i2c-rk3x.yaml:
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
>
> wcam: camera@36 {
> compatible = "ovti,ov5695";
> reg = <0x36>;
>
> port {
> wcam_out: endpoint {
> remote-endpoint = <&mipi_in_wcam>;
> data-lanes = <1 2>;
> };
> };
> };
>
> ucam: camera@3c {
> compatible = "ovti,ov2685";
> reg = <0x3c>;
>
> port {
> ucam_out: endpoint {
> remote-endpoint = <&mipi_in_ucam>;
> data-lanes = <1>;
> };
> };
> };
> };
> };
^ permalink raw reply
* Re: u-boot DT configuration node
From: Mark Kettenis @ 2020-04-02 11:34 UTC (permalink / raw)
To: Michal Simek; +Cc: michal.simek, robh, devicetree, u-boot, trini, loic.poulain
In-Reply-To: <ff4d0123-ca41-630e-322f-5251ee1e308e@xilinx.com>
> From: Michal Simek <michal.simek@xilinx.com>
> Date: Thu, 2 Apr 2020 08:05:36 +0200
>
> On 01. 04. 20 20:09, Mark Kettenis wrote:
> >> From: Michal Simek <michal.simek@xilinx.com>
> >> Date: Wed, 1 Apr 2020 11:23:13 +0200
> >>
> >> Hi Rob and others,
> >>
> >> for couple of years already u-boot is using config node in root DT for
> >> u-boot configuration.
> >>
> >> Here is one example in u-boot source code.
> >> https://gitlab.denx.de/u-boot/u-boot/-/blob/master/arch/arm/dts/exynos5250-spring.dts#L47
> >>
> >> And here is dt binding description
> >> https://gitlab.denx.de/u-boot/u-boot/-/blob/master/doc/device-tree-bindings/config.txt
> >>
> >> I was checking dt binding specification and there no such a thing
> >> described there. It means I expect this is more adhoc u-boot solution.
> >> We have reached the point where could be beneficial to put some u-boot
> >> specific configurations to DT.
> >>
> >> Actually I have done similar thing some time ago too by using chosen
> >> node and add xilinx specific property there to point to eeprom.
> >> https://gitlab.denx.de/u-boot/u-boot/-/blob/master/arch/arm/dts/zynqmp-zcu102-revA.dts#L39
> >>
> >> I think it is a time to discuss it and do it properly.
> >>
> >> First of all my question is where we could list SW prefixes to make sure
> >> that they are listed and everybody is aware about it. We have
> >> vendor-prefixes and we should have a way to record also prefixes for sw
> >> projects. U-Boot is using u-boot. Xen has file in the kernel with using
> >> xen prefix. At least these two should be listed.
> >
> > OpenBSD is using "openbsd," as a prefix. I've always thought it would
> > be good to have it listed in the list of vendor prefixes there. In an
> > open source world it shouldn't matter whether an entity sells
> > something or not. And in fact "inux," is already there. And so is
> > "qemu,".
>
> Good we have more.
>
>
> >
> >> Next my question is what is the recommended way to pass sw specific
> >> parameters via DT? I think using chosen node is more appropriate then
> >> adhoc config node. Or is there a better way how this should be done?
> >
> > On OpenBSD we do indeed use the the chosen node to pass information
> > between the bootloader and the kernel.
>
> Can you please point me to any example or description what you are
> adding there?
Here is an example of what the chosen node looks like:
Node 0x2220
name: 'chosen'
openbsd,uefi-mmap-desc-ver: 00000001
openbsd,uefi-mmap-desc-size: 00000030
openbsd,uefi-mmap-size: 00000540
openbsd,uefi-mmap-start: 00000081.fbe37df8
openbsd,uefi-system-table: 00000081.ff910018
openbsd,bootduid: 1b33bbab.1613122f
bootargs: 'sd0a:/bsd'
stdout-path: '/smb/serial@e1010000'
The openbsd,uefi-* proprties are effectively the same those already
documented for linux and xen. The openbsd,bootduid contains the
unique idea of the boot disk such that the kernel can find it and use
it as its root disk. There is also an openbsd,bootmac property to
support netbooting, and openbsd,sr-bootuuid and openbsd,sr-bootkey
properties to support booting from software raid with full disk
encryption. The actual key is zeroed out as soon as possible by the
kernel.
This all is pretty much a private interface between the boot loader
and the kernel though.
For booting on arm64 systems that use ACPI instead of a device tree,
the bootloader creates its own minimal device tree that contains a few
specific nodes that use compatible properties wuth an "openbsd,"
prefix. But once again that is a private interface between bootloader
and kernel.
Cheers,
Mark
^ permalink raw reply
* Re: [PATCH v2 5/8] interconnect: imx: Add platform driver for imx8mm
From: Georgi Djakov @ 2020-04-02 11:14 UTC (permalink / raw)
To: Leonard Crestez
Cc: Rob Herring, Chanwoo Choi, Alexandre Bailon, Rafael J. Wysocki,
Jacky Bai, Anson Huang, Artur Świgoń, Abel Vesa,
Krzysztof Kozlowski, MyungJoo Ham, Kyungmin Park, Saravana Kannan,
Mark Rutland, Viresh Kumar, Shawn Guo, Dong Aisheng,
Fabio Estevam, Stephen Boyd, Michael Turquette, Matthias Kaehlcke,
Angus Ainslie, Martin Kepplinger, Silvano di Ninno, linux-pm,
kernel, linux-imx, devicetree, linux-arm-kernel
In-Reply-To: <823cd307bea7416cf7df804bbcb77ab2887e0687.1585751281.git.leonard.crestez@nxp.com>
Hi Leonard,
On 4/1/20 17:33, Leonard Crestez wrote:
> Add a platform driver for the i.MX8MM SoC describing bus topology.
>
> Bandwidth adjustments is currently only supported on the DDRC and main
> NOC. Scaling for the vpu/gpu/display NICs could be added in the future.
>
> Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
> ---
> drivers/interconnect/imx/Kconfig | 4 +
> drivers/interconnect/imx/Makefile | 2 +
> drivers/interconnect/imx/imx8mm.c | 108 ++++++++++++++++++++++
> include/dt-bindings/interconnect/imx8mm.h | 49 ++++++++++
> 4 files changed, 163 insertions(+)
> create mode 100644 drivers/interconnect/imx/imx8mm.c
> create mode 100644 include/dt-bindings/interconnect/imx8mm.h
>
> diff --git a/drivers/interconnect/imx/Kconfig b/drivers/interconnect/imx/Kconfig
> index f39336f8d603..2cd4fad4976a 100644
> --- a/drivers/interconnect/imx/Kconfig
> +++ b/drivers/interconnect/imx/Kconfig
> @@ -1,5 +1,9 @@
> config INTERCONNECT_IMX
> tristate "i.MX interconnect drivers"
> depends on ARCH_MXC || COMPILE_TEST
> help
> Generic interconnect drivers for i.MX SOCs
> +
> +config INTERCONNECT_IMX8MM
> + tristate "i.MX8MM interconnect driver"
> + depends on INTERCONNECT_IMX
> diff --git a/drivers/interconnect/imx/Makefile b/drivers/interconnect/imx/Makefile
> index 86ae0bd28d8c..c234e5d3dfd1 100644
> --- a/drivers/interconnect/imx/Makefile
> +++ b/drivers/interconnect/imx/Makefile
> @@ -1,3 +1,5 @@
> imx-interconnect-objs := imx.o
> +imx8mm-interconnect-objs := imx8mm.o
>
> obj-$(CONFIG_INTERCONNECT_IMX) += imx-interconnect.o
> +obj-$(CONFIG_INTERCONNECT_IMX8MM) += imx8mm-interconnect.o
> diff --git a/drivers/interconnect/imx/imx8mm.c b/drivers/interconnect/imx/imx8mm.c
> new file mode 100644
> index 000000000000..ee3783a98c01
> --- /dev/null
> +++ b/drivers/interconnect/imx/imx8mm.c
> @@ -0,0 +1,108 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Interconnect framework driver for i.MX SoC
> + *
> + * Copyright (c) 2019, BayLibre
> + * Copyright (c) 2019, NXP
> + * Author: Alexandre Bailon <abailon@baylibre.com>
> + * Author: Leonard Crestez <leonard.crestez@nxp.com>
> + */
> +
> +#include <linux/device.h>
Is this used?
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
Is this used?
> +#include <linux/platform_device.h>
> +
> +#include <dt-bindings/interconnect/imx8mm.h>
> +
> +#include "imx.h"
> +
> +static const struct imx_icc_node_adj_desc imx8mm_dram_adj = {
> + .bw_mul = 1,
> + .bw_div = 16,
> + .phandle_name = "fsl,ddrc",
> +};
> +
> +static const struct imx_icc_node_adj_desc imx8mm_noc_adj = {
> + .bw_mul = 1,
> + .bw_div = 16,
> + .main_noc = true,
> +};
> +
> +/*
> + * Describe bus masters, slaves and connections between them
> + *
> + * This is a simplified subset of the bus diagram, there are several other
> + * PL301 nics which are skipped/merged into PL301_MAIN
> + */
> +static struct imx_icc_node_desc nodes[] = {
> + DEFINE_BUS_INTERCONNECT("NOC", IMX8MM_ICN_NOC, &imx8mm_noc_adj,
> + IMX8MM_ICS_DRAM, IMX8MM_ICN_MAIN),
> +
> + DEFINE_BUS_SLAVE("DRAM", IMX8MM_ICS_DRAM, &imx8mm_dram_adj),
> + DEFINE_BUS_SLAVE("OCRAM", IMX8MM_ICS_OCRAM, NULL),
> + DEFINE_BUS_MASTER("A53", IMX8MM_ICM_A53, IMX8MM_ICN_NOC),
> +
> + /* VPUMIX */
> + DEFINE_BUS_MASTER("VPU H1", IMX8MM_ICM_VPU_H1, IMX8MM_ICN_VIDEO),
> + DEFINE_BUS_MASTER("VPU G1", IMX8MM_ICM_VPU_G1, IMX8MM_ICN_VIDEO),
> + DEFINE_BUS_MASTER("VPU G2", IMX8MM_ICM_VPU_G2, IMX8MM_ICN_VIDEO),
> + DEFINE_BUS_INTERCONNECT("PL301_VIDEO", IMX8MM_ICN_VIDEO, NULL, IMX8MM_ICN_NOC),
> +
> + /* GPUMIX */
> + DEFINE_BUS_MASTER("GPU 2D", IMX8MM_ICM_GPU2D, IMX8MM_ICN_GPU),
> + DEFINE_BUS_MASTER("GPU 3D", IMX8MM_ICM_GPU3D, IMX8MM_ICN_GPU),
> + DEFINE_BUS_INTERCONNECT("PL301_GPU", IMX8MM_ICN_GPU, NULL, IMX8MM_ICN_NOC),
> +
> + /* DISPLAYMIX */
> + DEFINE_BUS_MASTER("CSI", IMX8MM_ICM_CSI, IMX8MM_ICN_MIPI),
> + DEFINE_BUS_MASTER("LCDIF", IMX8MM_ICM_LCDIF, IMX8MM_ICN_MIPI),
> + DEFINE_BUS_INTERCONNECT("PL301_MIPI", IMX8MM_ICN_MIPI, NULL, IMX8MM_ICN_NOC),
> +
> + /* HSIO */
> + DEFINE_BUS_MASTER("USB1", IMX8MM_ICM_USB1, IMX8MM_ICN_HSIO),
> + DEFINE_BUS_MASTER("USB2", IMX8MM_ICM_USB2, IMX8MM_ICN_HSIO),
> + DEFINE_BUS_MASTER("PCIE", IMX8MM_ICM_PCIE, IMX8MM_ICN_HSIO),
> + DEFINE_BUS_INTERCONNECT("PL301_HSIO", IMX8MM_ICN_HSIO, NULL, IMX8MM_ICN_NOC),
> +
> + /* Audio */
> + DEFINE_BUS_MASTER("SDMA2", IMX8MM_ICM_SDMA2, IMX8MM_ICN_AUDIO),
> + DEFINE_BUS_MASTER("SDMA3", IMX8MM_ICM_SDMA3, IMX8MM_ICN_AUDIO),
> + DEFINE_BUS_INTERCONNECT("PL301_AUDIO", IMX8MM_ICN_AUDIO, NULL, IMX8MM_ICN_MAIN),
> +
> + /* Ethernet */
> + DEFINE_BUS_MASTER("ENET", IMX8MM_ICM_ENET, IMX8MM_ICN_ENET),
> + DEFINE_BUS_INTERCONNECT("PL301_ENET", IMX8MM_ICN_ENET, NULL, IMX8MM_ICN_MAIN),
> +
> + /* Other */
> + DEFINE_BUS_MASTER("SDMA1", IMX8MM_ICM_SDMA1, IMX8MM_ICN_MAIN),
> + DEFINE_BUS_MASTER("NAND", IMX8MM_ICM_NAND, IMX8MM_ICN_MAIN),
> + DEFINE_BUS_MASTER("USDHC1", IMX8MM_ICM_USDHC1, IMX8MM_ICN_MAIN),
> + DEFINE_BUS_MASTER("USDHC2", IMX8MM_ICM_USDHC2, IMX8MM_ICN_MAIN),
> + DEFINE_BUS_MASTER("USDHC3", IMX8MM_ICM_USDHC3, IMX8MM_ICN_MAIN),
> + DEFINE_BUS_INTERCONNECT("PL301_MAIN", IMX8MM_ICN_MAIN, NULL,
> + IMX8MM_ICN_NOC, IMX8MM_ICS_OCRAM),
> +};
> +
> +static int imx8mm_icc_probe(struct platform_device *pdev)
> +{
> + return imx_icc_register(pdev, nodes, ARRAY_SIZE(nodes));
> +}
> +
> +static int imx8mm_icc_remove(struct platform_device *pdev)
> +{
> + return imx_icc_unregister(pdev);
> +}
> +
> +static struct platform_driver imx8mm_icc_driver = {
> + .probe = imx8mm_icc_probe,
> + .remove = imx8mm_icc_remove,
> + .driver = {
> + .name = "imx8mm-interconnect",
> + },
> +};
> +
> +module_platform_driver(imx8mm_icc_driver);
> +MODULE_AUTHOR("Alexandre Bailon <abailon@baylibre.com>");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:imx8mm-interconnect");
> diff --git a/include/dt-bindings/interconnect/imx8mm.h b/include/dt-bindings/interconnect/imx8mm.h
> new file mode 100644
> index 000000000000..5404f2af15c3
> --- /dev/null
> +++ b/include/dt-bindings/interconnect/imx8mm.h
> @@ -0,0 +1,49 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Interconnect framework driver for i.MX SoC
> + *
> + * Copyright (c) 2019, BayLibre
> + * Author: Alexandre Bailon <abailon@baylibre.com>
> + */
> +
> +#ifndef __IMX8MM_ICM_INTERCONNECT_IDS_H
> +#define __IMX8MM_ICM_INTERCONNECT_IDS_H
Nit: Some people make this match the path, but it's up to you.
> +
> +#define IMX8MM_ICN_NOC 1
> +#define IMX8MM_ICS_DRAM 2
> +#define IMX8MM_ICS_OCRAM 3
> +#define IMX8MM_ICM_A53 4
> +
> +#define IMX8MM_ICM_VPU_H1 5
> +#define IMX8MM_ICM_VPU_G1 6
> +#define IMX8MM_ICM_VPU_G2 7
> +#define IMX8MM_ICN_VIDEO 8
> +
> +#define IMX8MM_ICM_GPU2D 9
> +#define IMX8MM_ICM_GPU3D 10
> +#define IMX8MM_ICN_GPU 11
> +
> +#define IMX8MM_ICM_CSI 12
> +#define IMX8MM_ICM_LCDIF 13
> +#define IMX8MM_ICN_MIPI 14
> +
> +#define IMX8MM_ICM_USB1 15
> +#define IMX8MM_ICM_USB2 16
> +#define IMX8MM_ICM_PCIE 17
> +#define IMX8MM_ICN_HSIO 18
> +
> +#define IMX8MM_ICM_SDMA2 19
> +#define IMX8MM_ICM_SDMA3 20
> +#define IMX8MM_ICN_AUDIO 21
> +
> +#define IMX8MM_ICN_ENET 22
> +#define IMX8MM_ICM_ENET 23
> +
> +#define IMX8MM_ICN_MAIN 24
> +#define IMX8MM_ICM_NAND 25
> +#define IMX8MM_ICM_SDMA1 26
> +#define IMX8MM_ICM_USDHC1 27
> +#define IMX8MM_ICM_USDHC2 28
> +#define IMX8MM_ICM_USDHC3 29
> +
> +#endif /* __IMX8MM_ICM_INTERCONNECT_IDS_H */
>
Looks good!
Thanks,
Georgi
^ permalink raw reply
* Re: [PATCH net-next v6 00/11] net: ethernet: ti: add networking support for k3 am65x/j721e soc
From: Grygorii Strashko @ 2020-04-02 11:05 UTC (permalink / raw)
To: Will Deacon, Nick Desaulniers
Cc: davem, arnd, devicetree, kishon, kuba, linux-arm-kernel,
linux-kernel, m-karicheri2, netdev, nsekhar, olof, olteanv,
peter.ujfalusi, robh, rogerq, t-kristo, clang-built-linux
In-Reply-To: <20200402094239.GA3770@willie-the-truck>
On 02/04/2020 12:42, Will Deacon wrote:
> On Wed, Apr 01, 2020 at 03:35:00PM -0700, Nick Desaulniers wrote:
>>>> I think the ARM64 build is now also broken on Linus' master branch,
>>>> after the net-next merge? I am not quite sure if the device tree
>>>> patches were supposed to land in mainline the way they did.
>>>
>>> There's a fix in my net tree and it will go to Linus soon.
>>>
>>> There is no clear policy for dt change integration, and honestly
>>> I try to deal with the situation on a case by case basis.
>>
>> Yep, mainline aarch64-linux-gnu- builds are totally hosed. DTC fails the build
>> very early on:
>> https://travis-ci.com/github/ClangBuiltLinux/continuous-integration/jobs/311246218
>> https://travis-ci.com/github/ClangBuiltLinux/continuous-integration/jobs/311246270
>> There was no failure in -next, not sure how we skipped our canary in the coal
>> mine.
>
> Yes, one of the things linux-next does a really good job at catching is
> build breakage so it would've been nice to have seen this there rather
> than end up with breakage in Linus' tree :(
>
> Was the timing just bad, or are we missing DT coverage or something else?
It seems issue was not caught in -next because the patch that fixes the issue was already in -next
before this series was pushed.
Sorry for the mess again.
--
Best regards,
grygorii
^ permalink raw reply
* Re: [PATCH v2 4/8] interconnect: Add imx core driver
From: Georgi Djakov @ 2020-04-02 11:05 UTC (permalink / raw)
To: Leonard Crestez
Cc: Rob Herring, Chanwoo Choi, Alexandre Bailon, Rafael J. Wysocki,
Jacky Bai, Anson Huang, Artur Świgoń, Abel Vesa,
Krzysztof Kozlowski, MyungJoo Ham, Kyungmin Park, Saravana Kannan,
Mark Rutland, Viresh Kumar, Shawn Guo, Dong Aisheng,
Fabio Estevam, Stephen Boyd, Michael Turquette, Matthias Kaehlcke,
Angus Ainslie, Martin Kepplinger, Silvano di Ninno, linux-pm,
kernel, linux-imx, devicetree, linux-arm-kernel
In-Reply-To: <50e6bdb1aab7d8f73cb10d11a4ea1e55056448fc.1585751281.git.leonard.crestez@nxp.com>
Hi Leonard,
Thank you for updating the patches!
On 4/1/20 17:33, Leonard Crestez wrote:
> This adds support for i.MX SoC family to interconnect framework.
>
> Platform drivers can describe the interconnect graph and several
> adjustment knobs where icc node bandwidth is converted to a
> DEV_PM_QOS_MIN_FREQUENCY request.
>
> The interconnect provider is probed through the main NOC device and
> other adjustable nodes on the same graph are found from a
> fsl,scalable-nodes phandle array property.
>
> Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
> Tested-by: Martin Kepplinger <martin.kepplinger@puri.sm>
> ---
> drivers/interconnect/Kconfig | 1 +
> drivers/interconnect/Makefile | 1 +
> drivers/interconnect/imx/Kconfig | 5 +
> drivers/interconnect/imx/Makefile | 3 +
> drivers/interconnect/imx/imx.c | 298 ++++++++++++++++++++++++++++++
> drivers/interconnect/imx/imx.h | 62 +++++++
> 6 files changed, 370 insertions(+)
> create mode 100644 drivers/interconnect/imx/Kconfig
> create mode 100644 drivers/interconnect/imx/Makefile
> create mode 100644 drivers/interconnect/imx/imx.c
> create mode 100644 drivers/interconnect/imx/imx.h
>
> diff --git a/drivers/interconnect/Kconfig b/drivers/interconnect/Kconfig
> index bfa4ca3ab7a9..e61802230f90 100644
> --- a/drivers/interconnect/Kconfig
> +++ b/drivers/interconnect/Kconfig
> @@ -10,7 +10,8 @@ menuconfig INTERCONNECT
> If unsure, say no.
>
> if INTERCONNECT
>
> source "drivers/interconnect/qcom/Kconfig"
> +source "drivers/interconnect/imx/Kconfig"
Nit: Please move it up to make it sorted.
>
> endif
> diff --git a/drivers/interconnect/Makefile b/drivers/interconnect/Makefile
> index 725029ae7a2c..6998288a7d98 100644
> --- a/drivers/interconnect/Makefile
> +++ b/drivers/interconnect/Makefile
> @@ -3,5 +3,6 @@
> CFLAGS_core.o := -I$(src)
> icc-core-objs := core.o
>
> obj-$(CONFIG_INTERCONNECT) += icc-core.o
> obj-$(CONFIG_INTERCONNECT_QCOM) += qcom/
> +obj-$(CONFIG_INTERCONNECT_IMX) += imx/
Ditto.
> diff --git a/drivers/interconnect/imx/Kconfig b/drivers/interconnect/imx/Kconfig
> new file mode 100644
> index 000000000000..f39336f8d603
> --- /dev/null
> +++ b/drivers/interconnect/imx/Kconfig
> @@ -0,0 +1,5 @@
> +config INTERCONNECT_IMX
> + tristate "i.MX interconnect drivers"
> + depends on ARCH_MXC || COMPILE_TEST
> + help
> + Generic interconnect drivers for i.MX SOCs
> diff --git a/drivers/interconnect/imx/Makefile b/drivers/interconnect/imx/Makefile
> new file mode 100644
> index 000000000000..86ae0bd28d8c
> --- /dev/null
> +++ b/drivers/interconnect/imx/Makefile
> @@ -0,0 +1,3 @@
> +imx-interconnect-objs := imx.o
> +
> +obj-$(CONFIG_INTERCONNECT_IMX) += imx-interconnect.o
> diff --git a/drivers/interconnect/imx/imx.c b/drivers/interconnect/imx/imx.c
> new file mode 100644
> index 000000000000..527b1de1c41a
> --- /dev/null
> +++ b/drivers/interconnect/imx/imx.c
> @@ -0,0 +1,298 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Interconnect framework driver for i.MX SoC
> + *
> + * Copyright (c) 2019, BayLibre
> + * Copyright (c) 2019, NXP
Maybe update it to 2020.
> + * Author: Alexandre Bailon <abailon@baylibre.com>
> + * Author: Leonard Crestez <leonard.crestez@nxp.com>
> + */
> +
> +#include <linux/device.h>
> +#include <linux/interconnect-provider.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_qos.h>
> +
> +#include "imx.h"
> +
> +/* private icc_node data */
> +struct imx_icc_node {
> + const struct imx_icc_node_desc *desc;
> + struct device *qos_dev;
> + struct dev_pm_qos_request qos_req;
> +};
> +
> +static int imx_icc_aggregate(struct icc_node *node, u32 tag,
> + u32 avg_bw, u32 peak_bw,
> + u32 *agg_avg, u32 *agg_peak)
> +{
> + *agg_avg += avg_bw;
> + *agg_peak = max(*agg_peak, peak_bw);
> +
> + return 0;
> +}
Please remove and use the common library function:
icc_std_aggregate().
> +
> +static int imx_icc_node_set(struct icc_node *node)
> +{
> + struct device *dev = node->provider->dev;
> + struct imx_icc_node *node_data = node->data;
> + u64 freq;
> +
> + if (!node_data->qos_dev)
> + return 0;
> +
> + freq = (node->avg_bw + node->peak_bw) * node_data->desc->adj->bw_mul;
> + do_div(freq, node_data->desc->adj->bw_div);
> + dev_dbg(dev, "node %s device %s avg_bw %ukBps peak_bw %ukBps min_freq %llukHz\n",
> + node->name, dev_name(node_data->qos_dev),
> + node->avg_bw, node->peak_bw, freq);
> +
> + if (freq > S32_MAX) {
> + dev_err(dev, "%s can't request more than S32_MAX freq\n",
> + node->name);
Please align with the open parenthesis.
> + return -ERANGE;
> + }
> +
> + dev_pm_qos_update_request(&node_data->qos_req, freq);
> +
> + return 0;
> +}
> +
> +static int imx_icc_set(struct icc_node *src, struct icc_node *dst)
> +{
> + return imx_icc_node_set(dst);
> +}
> +
> +/* imx_icc_node_destroy() - Destroy an imx icc_node, including private data */
> +static void imx_icc_node_destroy(struct icc_node *node)
> +{
> + struct imx_icc_node *node_data = node->data;
> + int ret;
> +
> + if (dev_pm_qos_request_active(&node_data->qos_req)) {
> + ret = dev_pm_qos_remove_request(&node_data->qos_req);
> + if (ret)
> + dev_warn(node->provider->dev, "failed to remove qos request for %s\n",
> + dev_name(node_data->qos_dev));
> + }
> +
> + put_device(node_data->qos_dev);
> + icc_node_del(node);
> + icc_node_destroy(node->id);
> +}
> +
> +static int imx_icc_node_init_qos(struct icc_provider *provider,
> + struct icc_node *node)
> +{
> + struct imx_icc_node *node_data = node->data;
> + const struct imx_icc_node_adj_desc *adj = node_data->desc->adj;
> + struct device *dev = provider->dev;
> + struct device_node *dn = NULL;
> + struct platform_device *pdev;
> +
> + if (adj->main_noc) {
> + node_data->qos_dev = dev;
> + dev_info(dev, "icc node %s[%d] is main noc itself\n",
> + node->name, node->id);
Should this be dev_dbg()?
> + } else {
> + dn = of_parse_phandle(dev->of_node, adj->phandle_name, 0);
> + if (IS_ERR(dn)) {
> + dev_warn(dev, "Failed to parse %s: %ld\n",
> + adj->phandle_name, PTR_ERR(dn));
Please align with the open parenthesis.
> + return PTR_ERR(dn);
> + }
> + /* Allow scaling to be disabled on a per-node basis */
> + if (!dn || !of_device_is_available(dn)) {
> + dev_warn(dev, "Missing property %s, skip scaling %s\n",
> + adj->phandle_name, node->name);
Please align with the open parenthesis.
> + return 0;
> + }
> +
> + pdev = of_find_device_by_node(dn);
> + of_node_put(dn);
> + if (!pdev) {
> + dev_warn(dev, "node %s[%d] missing device for %pOF\n",
> + node->name, node->id, dn);
Please align with the open parenthesis.
> + return -EPROBE_DEFER;
> + }
> + node_data->qos_dev = &pdev->dev;
> + dev_info(dev, "node %s[%d] has device node %pOF\n",
> + node->name, node->id, dn);
dev_dbg() again maybe? Unless you think that it make sense to print this
information to the user?
> + }
> +
> + return dev_pm_qos_add_request(node_data->qos_dev,
> + &node_data->qos_req,
> + DEV_PM_QOS_MIN_FREQUENCY, 0);
> +}
> +
> +static struct icc_node *imx_icc_node_add(struct icc_provider *provider,
> + const struct imx_icc_node_desc *node_desc)
> +{
> + struct device *dev = provider->dev;
> + struct imx_icc_node *node_data;
> + struct icc_node *node;
> + int ret;
> +
> + node = icc_node_create(node_desc->id);
> + if (IS_ERR(node)) {
> + dev_err(dev, "failed to create node %d\n", node_desc->id);
> + return node;
> + }
> +
> + if (node->data) {
> + dev_err(dev, "already created node %s id=%d\n",
> + node_desc->name, node_desc->id);
Please align with the open parenthesis.
> + return ERR_PTR(-EEXIST);
> + }
> +
> + node_data = devm_kzalloc(dev, sizeof(*node_data), GFP_KERNEL);
> + if (!node_data) {
> + icc_node_destroy(node->id);
> + return ERR_PTR(-ENOMEM);
> + }
> +
> + node->name = node_desc->name;
> + node->data = node_data;
> + node_data->desc = node_desc;
> + icc_node_add(node, provider);
> +
> + if (node_desc->adj) {
> + ret = imx_icc_node_init_qos(provider, node);
> + if (ret < 0) {
> + imx_icc_node_destroy(node);
> + return ERR_PTR(ret);
> + }
> + }
> +
> + return node;
> +}
> +
> +static void imx_icc_unregister_nodes(struct icc_provider *provider)
> +{
> + struct icc_node *node, *tmp;
> +
> + list_for_each_entry_safe(node, tmp, &provider->nodes, node_list)
> + imx_icc_node_destroy(node);
> +}
> +
> +static int imx_icc_register_nodes(struct icc_provider *provider,
> + const struct imx_icc_node_desc *descs,
> + int count)
> +{
> + struct icc_onecell_data *provider_data = provider->data;
> + int ret;
> + int i;
> +
> + for (i = 0; i < count; i++) {
> + struct icc_node *node;
> + const struct imx_icc_node_desc *node_desc = &descs[i];
> + size_t j;
> +
> + node = imx_icc_node_add(provider, node_desc);
> + if (IS_ERR(node)) {
> + ret = PTR_ERR(node);
> + if (ret != -EPROBE_DEFER)
> + dev_err(provider->dev, "failed to add %s: %d\n",
> + node_desc->name, ret);
> + goto err;
> + }
> + provider_data->nodes[node->id] = node;
> +
> + for (j = 0; j < node_desc->num_links; j++) {
> + ret = icc_link_create(node, node_desc->links[j]);
> + if (ret) {
> + dev_err(provider->dev, "failed to link node %d to %d: %d\n",
> + node->id, node_desc->links[j], ret);
> + goto err;
> + }
> + }
> + }
> +
> + return 0;
> +
> +err:
> + imx_icc_unregister_nodes(provider);
> +
> + return ret;
> +}
> +
> +static int get_max_node_id(struct imx_icc_node_desc *nodes, int nodes_count)
> +{
> + int i, ret = 0;
> +
> + for (i = 0; i < nodes_count; ++i)
> + if (nodes[i].id > ret)
> + ret = nodes[i].id;
> +
> + return ret;
> +}
> +
> +int imx_icc_register(struct platform_device *pdev,
> + struct imx_icc_node_desc *nodes, int nodes_count)
> +{
> + struct device *dev = &pdev->dev;
> + struct icc_onecell_data *data;
> + struct icc_provider *provider;
> + int max_node_id;
> + int ret;
> +
> + /* icc_onecell_data is indexed by node_id, unlike nodes param */
> + max_node_id = get_max_node_id(nodes, nodes_count);
> + data = devm_kzalloc(dev, struct_size(data, nodes, max_node_id),
> + GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> + data->num_nodes = max_node_id;
> +
> + provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL);
> + if (!provider)
> + return -ENOMEM;
> + provider->set = imx_icc_set;
> + provider->aggregate = imx_icc_aggregate;
provider->aggregate = icc_std_aggregate;
> + provider->xlate = of_icc_xlate_onecell;
> + provider->data = data;
> + provider->dev = dev->parent;
> + platform_set_drvdata(pdev, provider);
> +
> + ret = icc_provider_add(provider);
> + if (ret) {
> + dev_err(dev, "error adding interconnect provider: %d\n", ret);
> + return ret;
> + }
> +
> + ret = imx_icc_register_nodes(provider, nodes, nodes_count);
> + if (ret)
> + goto provider_del;
> +
> + return 0;
> +
> +provider_del:
> + icc_provider_del(provider);
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(imx_icc_register);
> +
> +int imx_icc_unregister(struct platform_device *pdev)
> +{
> + struct icc_provider *provider = platform_get_drvdata(pdev);
> + int ret;
> +
> + if (provider->users) {
> + dev_warn(&pdev->dev, "interconnect provider still has %d users\n",
> + provider->users);
> + return -EBUSY;
> + }
The above check already exists in icc_provider_del(). But i assume you don't
want to delete any nodes from the provider if it still has users. Maybe it will
be sensible to add this check into icc_nodes_remove() instead, so that such
cases are handled on a framework level.
> + imx_icc_unregister_nodes(provider);
> +
> + ret = icc_provider_del(provider);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(imx_icc_unregister);
> +
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/interconnect/imx/imx.h b/drivers/interconnect/imx/imx.h
> new file mode 100644
> index 000000000000..aa811e4ebb7e
> --- /dev/null
> +++ b/drivers/interconnect/imx/imx.h
> @@ -0,0 +1,62 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Interconnect framework driver for i.MX SoC
> + *
> + * Copyright (c) 2019, BayLibre
> + * Copyright (c) 2019, NXP
> + * Author: Alexandre Bailon <abailon@baylibre.com>
> + * Author: Leonard Crestez <leonard.crestez@nxp.com>
> + */
> +#ifndef __DRIVERS_INTERCONNECT_IMX_H
> +#define __DRIVERS_INTERCONNECT_IMX_H
> +
> +#include <linux/kernel.h>
> +
> +#define IMX_ICC_MAX_LINKS 4
> +
> +/*
> + * struct imx_icc_node_adj - Describe a dynamic adjustable node
> + */
> +struct imx_icc_node_adj_desc {
> + unsigned int bw_mul, bw_div;
> + const char *phandle_name;
> + bool main_noc;
> +};
> +
> +/*
> + * struct imx_icc_node - Describe an interconnect node
> + * @name: name of the node
> + * @id: an unique id to identify the node
> + * @links: an array of slaves' node id
> + * @num_links: number of id defined in links
> + */
> +struct imx_icc_node_desc {
> + const char *name;
> + u16 id;
> + u16 links[IMX_ICC_MAX_LINKS];
> + u16 num_links;
> +
Why the blank line?
> + const struct imx_icc_node_adj_desc *adj;
> +};
> +
> +#define DEFINE_BUS_INTERCONNECT(_name, _id, _adj, ...) \
> + { \
> + .id = _id, \
> + .name = _name, \
> + .adj = _adj, \
> + .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \
> + .links = { __VA_ARGS__ }, \
> + }
> +
> +#define DEFINE_BUS_MASTER(_name, _id, _dest_id) \
> + DEFINE_BUS_INTERCONNECT(_name, _id, NULL, _dest_id)
> +
> +#define DEFINE_BUS_SLAVE(_name, _id, _adj) \
> + DEFINE_BUS_INTERCONNECT(_name, _id, _adj)
> +
> +int imx_icc_register(struct platform_device *pdev,
> + struct imx_icc_node_desc *nodes,
> + int nodes_count);
> +int imx_icc_unregister(struct platform_device *pdev);
> +
> +#endif /* __DRIVERS_INTERCONNECT_IMX_H */
>
Thanks,
Georgi
^ permalink raw reply
* [PATCH 5/5] MIPS: Loongson64: Mark RS780 HPET as broken
From: Jiaxun Yang @ 2020-04-02 10:48 UTC (permalink / raw)
To: linux-mips
Cc: Jiaxun Yang, Thomas Bogendoerfer, Rob Herring, Huacai Chen,
devicetree, linux-kernel
In-Reply-To: <20200402104851.368465-1-jiaxun.yang@flygoat.com>
This driver is using some dangerous hack to set MMIO address for HPET,
which might break systems with other kinds of PCH.
Also, as Loongson-3 cpufreq driver never appeared in mainline,
this driver rarely got used.
So we temporarily mark it as broken until we find a better solution.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/loongson64/Kconfig | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/mips/loongson64/Kconfig b/arch/mips/loongson64/Kconfig
index c386b8a3c753..16e6acab8cce 100644
--- a/arch/mips/loongson64/Kconfig
+++ b/arch/mips/loongson64/Kconfig
@@ -4,14 +4,12 @@ if MACH_LOONGSON64
config RS780_HPET
bool "RS780/SBX00 HPET Timer"
depends on MACH_LOONGSON64
+ depends on BROKEN
select MIPS_EXTERNAL_TIMER
help
This option enables the hpet timer of AMD RS780/SBX00.
- If you want to enable the Loongson3 CPUFreq Driver, Please enable
- this option at first, otherwise, You will get wrong system time.
-
- If unsure, say Yes.
-
+ Note: This driver is doing some dangerous hack. Please only enable
+ it on RS780 systems.
endif # MACH_LOONGSON64
--
2.26.0.rc2
^ permalink raw reply related
* [PATCH 4/5] MIPS: DTS: Loongson64: Add ACPI Controller Node
From: Jiaxun Yang @ 2020-04-02 10:48 UTC (permalink / raw)
To: linux-mips
Cc: Jiaxun Yang, Thomas Bogendoerfer, Rob Herring, Huacai Chen,
devicetree, linux-kernel
In-Reply-To: <20200402104851.368465-1-jiaxun.yang@flygoat.com>
Add ACPI Controller Node for RS780E PCH to fit newly added driver.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/boot/dts/loongson/rs780e-pch.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
index 8766f97306c6..5e68ceae20ca 100644
--- a/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
+++ b/arch/mips/boot/dts/loongson/rs780e-pch.dtsi
@@ -36,6 +36,11 @@ rtc0: rtc@70 {
interrupts = <8>;
interrupt-parent = <&htpic>;
};
+
+ acpi@800 {
+ compatible = "loongson,rs780e-acpi";
+ reg = <1 0x800 0x100>;
+ };
};
};
};
--
2.26.0.rc2
^ permalink raw reply related
* [PATCH 1/5] MIPS: Loongson64: Remove dead RTC code
From: Jiaxun Yang @ 2020-04-02 10:48 UTC (permalink / raw)
To: linux-mips
Cc: Jiaxun Yang, Thomas Bogendoerfer, Rob Herring, Huacai Chen,
devicetree, linux-kernel
RTC is now enabled by devicetree. So platform code is
no longer needed.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
.../include/asm/mach-loongson64/mc146818rtc.h | 36 -----------------
arch/mips/loongson64/Kconfig | 4 --
arch/mips/loongson64/Makefile | 1 -
arch/mips/loongson64/rtc.c | 39 -------------------
arch/mips/loongson64/time.c | 8 +---
5 files changed, 1 insertion(+), 87 deletions(-)
delete mode 100644 arch/mips/include/asm/mach-loongson64/mc146818rtc.h
delete mode 100644 arch/mips/loongson64/rtc.c
diff --git a/arch/mips/include/asm/mach-loongson64/mc146818rtc.h b/arch/mips/include/asm/mach-loongson64/mc146818rtc.h
deleted file mode 100644
index ebdccfee50be..000000000000
--- a/arch/mips/include/asm/mach-loongson64/mc146818rtc.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998, 2001, 03, 07 by Ralf Baechle (ralf@linux-mips.org)
- *
- * RTC routines for PC style attached Dallas chip.
- */
-#ifndef __ASM_MACH_LOONGSON64_MC146818RTC_H
-#define __ASM_MACH_LOONGSON64_MC146818RTC_H
-
-#include <linux/io.h>
-
-#define RTC_PORT(x) (0x70 + (x))
-#define RTC_IRQ 8
-
-static inline unsigned char CMOS_READ(unsigned long addr)
-{
- outb_p(addr, RTC_PORT(0));
- return inb_p(RTC_PORT(1));
-}
-
-static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
-{
- outb_p(addr, RTC_PORT(0));
- outb_p(data, RTC_PORT(1));
-}
-
-#define RTC_ALWAYS_BCD 0
-
-#ifndef mc146818_decode_year
-#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970)
-#endif
-
-#endif /* __ASM_MACH_LOONGSON64_MC146818RTC_H */
diff --git a/arch/mips/loongson64/Kconfig b/arch/mips/loongson64/Kconfig
index 48b29c198acf..c386b8a3c753 100644
--- a/arch/mips/loongson64/Kconfig
+++ b/arch/mips/loongson64/Kconfig
@@ -14,8 +14,4 @@ config RS780_HPET
If unsure, say Yes.
-config LOONGSON_MC146818
- bool
- default n
-
endif # MACH_LOONGSON64
diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile
index f04461839540..102a19aa92aa 100644
--- a/arch/mips/loongson64/Makefile
+++ b/arch/mips/loongson64/Makefile
@@ -8,6 +8,5 @@ obj-$(CONFIG_MACH_LOONGSON64) += cop2-ex.o platform.o acpi_init.o dma.o \
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_NUMA) += numa.o
obj-$(CONFIG_RS780_HPET) += hpet.o
-obj-$(CONFIG_LOONGSON_MC146818) += rtc.o
obj-$(CONFIG_SUSPEND) += pm.o
obj-$(CONFIG_PCI_QUIRKS) += vbios_quirk.o
diff --git a/arch/mips/loongson64/rtc.c b/arch/mips/loongson64/rtc.c
deleted file mode 100644
index 8d7628c0f513..000000000000
--- a/arch/mips/loongson64/rtc.c
+++ /dev/null
@@ -1,39 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Lemote Fuloong platform support
- *
- * Copyright(c) 2010 Arnaud Patard <apatard@mandriva.com>
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/mc146818rtc.h>
-
-static struct resource loongson_rtc_resources[] = {
- {
- .start = RTC_PORT(0),
- .end = RTC_PORT(1),
- .flags = IORESOURCE_IO,
- }, {
- .start = RTC_IRQ,
- .end = RTC_IRQ,
- .flags = IORESOURCE_IRQ,
- }
-};
-
-static struct platform_device loongson_rtc_device = {
- .name = "rtc_cmos",
- .id = -1,
- .resource = loongson_rtc_resources,
- .num_resources = ARRAY_SIZE(loongson_rtc_resources),
-};
-
-
-static int __init loongson_rtc_platform_init(void)
-{
- platform_device_register(&loongson_rtc_device);
- return 0;
-}
-
-device_initcall(loongson_rtc_platform_init);
diff --git a/arch/mips/loongson64/time.c b/arch/mips/loongson64/time.c
index 1245f22cec84..91e842b58365 100644
--- a/arch/mips/loongson64/time.c
+++ b/arch/mips/loongson64/time.c
@@ -6,7 +6,7 @@
* Copyright (C) 2009 Lemote Inc.
* Author: Wu Zhangjin, wuzhangjin@gmail.com
*/
-#include <asm/mc146818-time.h>
+
#include <asm/time.h>
#include <asm/hpet.h>
@@ -21,9 +21,3 @@ void __init plat_time_init(void)
setup_hpet_timer();
#endif
}
-
-void read_persistent_clock64(struct timespec64 *ts)
-{
- ts->tv_sec = mc146818_get_cmos_time();
- ts->tv_nsec = 0;
-}
--
2.26.0.rc2
^ permalink raw reply related
* [PATCH 2/5] MIPS: Loongson64: Make RS780E ACPI as a platform driver
From: Jiaxun Yang @ 2020-04-02 10:48 UTC (permalink / raw)
To: linux-mips
Cc: Jiaxun Yang, Thomas Bogendoerfer, Rob Herring, Huacai Chen,
devicetree, linux-kernel
In-Reply-To: <20200402104851.368465-1-jiaxun.yang@flygoat.com>
Make RS780E ACPI as a platform driver so we can enable it
by DeviceTree selectively.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/loongson64/Makefile | 2 +-
drivers/platform/mips/Kconfig | 6 ++
drivers/platform/mips/Makefile | 1 +
.../platform/mips/rs780e-acpi.c | 58 ++++++++++++-------
4 files changed, 46 insertions(+), 21 deletions(-)
rename arch/mips/loongson64/acpi_init.c => drivers/platform/mips/rs780e-acpi.c (70%)
diff --git a/arch/mips/loongson64/Makefile b/arch/mips/loongson64/Makefile
index 102a19aa92aa..6f81b822aeae 100644
--- a/arch/mips/loongson64/Makefile
+++ b/arch/mips/loongson64/Makefile
@@ -2,7 +2,7 @@
#
# Makefile for Loongson-3 family machines
#
-obj-$(CONFIG_MACH_LOONGSON64) += cop2-ex.o platform.o acpi_init.o dma.o \
+obj-$(CONFIG_MACH_LOONGSON64) += cop2-ex.o platform.o dma.o \
setup.o init.o env.o time.o reset.o \
obj-$(CONFIG_SMP) += smp.o
diff --git a/drivers/platform/mips/Kconfig b/drivers/platform/mips/Kconfig
index 5e77b0dc5fd6..8ac149173c64 100644
--- a/drivers/platform/mips/Kconfig
+++ b/drivers/platform/mips/Kconfig
@@ -24,4 +24,10 @@ config CPU_HWMON
help
Loongson-3A/3B CPU Hwmon (temperature sensor) driver.
+config RS780E_ACPI
+ bool "Loongson RS780E ACPI Controller"
+ depends on MACH_LOONGSON64 || COMPILE_TEST
+ help
+ Loongson RS780E PCH ACPI Controller driver.
+
endif # MIPS_PLATFORM_DEVICES
diff --git a/drivers/platform/mips/Makefile b/drivers/platform/mips/Makefile
index be8146c20dc8..178149098777 100644
--- a/drivers/platform/mips/Makefile
+++ b/drivers/platform/mips/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_CPU_HWMON) += cpu_hwmon.o
+obj-$(CONFIG_RS780E_ACPI) += rs780e-acpi.o
diff --git a/arch/mips/loongson64/acpi_init.c b/drivers/platform/mips/rs780e-acpi.c
similarity index 70%
rename from arch/mips/loongson64/acpi_init.c
rename to drivers/platform/mips/rs780e-acpi.c
index 8d7c119ddf91..e5a643b78ac9 100644
--- a/arch/mips/loongson64/acpi_init.c
+++ b/drivers/platform/mips/rs780e-acpi.c
@@ -3,32 +3,23 @@
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/export.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
-#define SBX00_ACPI_IO_BASE 0x800
-#define SBX00_ACPI_IO_SIZE 0x100
+static unsigned long acpi_iobase;
-#define ACPI_PM_EVT_BLK (SBX00_ACPI_IO_BASE + 0x00) /* 4 bytes */
-#define ACPI_PM_CNT_BLK (SBX00_ACPI_IO_BASE + 0x04) /* 2 bytes */
-#define ACPI_PMA_CNT_BLK (SBX00_ACPI_IO_BASE + 0x0F) /* 1 byte */
-#define ACPI_PM_TMR_BLK (SBX00_ACPI_IO_BASE + 0x18) /* 4 bytes */
-#define ACPI_GPE0_BLK (SBX00_ACPI_IO_BASE + 0x10) /* 8 bytes */
-#define ACPI_END (SBX00_ACPI_IO_BASE + 0x80)
+#define ACPI_PM_EVT_BLK (acpi_iobase + 0x00) /* 4 bytes */
+#define ACPI_PM_CNT_BLK (acpi_iobase + 0x04) /* 2 bytes */
+#define ACPI_PMA_CNT_BLK (acpi_iobase + 0x0F) /* 1 byte */
+#define ACPI_PM_TMR_BLK (acpi_iobase + 0x18) /* 4 bytes */
+#define ACPI_GPE0_BLK (acpi_iobase + 0x10) /* 8 bytes */
+#define ACPI_END (acpi_iobase + 0x80)
#define PM_INDEX 0xCD6
#define PM_DATA 0xCD7
#define PM2_INDEX 0xCD0
#define PM2_DATA 0xCD1
-/*
- * SCI interrupt need acpi space, allocate here
- */
-
-static int __init register_acpi_resource(void)
-{
- request_region(SBX00_ACPI_IO_BASE, SBX00_ACPI_IO_SIZE, "acpi");
- return 0;
-}
-
static void pmio_write_index(u16 index, u8 reg, u8 value)
{
outb(reg, index);
@@ -141,11 +132,38 @@ void acpi_registers_setup(void)
pm2_iowrite(0xf8, value);
}
-int __init sbx00_acpi_init(void)
+static int rs780e_acpi_probe(struct platform_device *pdev)
{
- register_acpi_resource();
+ struct resource *res;
+
+ res = platform_get_resource(pdev, IORESOURCE_IO, 0);
+ if (!res)
+ return -ENODEV;
+
+ /* SCI interrupt need acpi space, allocate here */
+ if (!request_region(res->start, resource_size(res), "acpi")) {
+ pr_err("RS780E-ACPI: Failed to request IO Region\n");
+ return -EBUSY;
+ }
+
+ acpi_iobase = res->start;
+
acpi_registers_setup();
acpi_hw_clear_status();
return 0;
}
+
+static const struct of_device_id rs780e_acpi_match[] = {
+ { .compatible = "loongson,rs780e-acpi" },
+ {},
+};
+
+static struct platform_driver rs780e_acpi_driver = {
+ .probe = rs780e_acpi_probe,
+ .driver = {
+ .name = "RS780E-ACPI",
+ .of_match_table = rs780e_acpi_match,
+ },
+};
+builtin_platform_driver(rs780e_acpi_driver);
--
2.26.0.rc2
^ permalink raw reply related
* [PATCH 3/5] dt-bindings: Document Loongson RS780E PCH ACPI Controller
From: Jiaxun Yang @ 2020-04-02 10:48 UTC (permalink / raw)
To: linux-mips
Cc: Jiaxun Yang, Thomas Bogendoerfer, Rob Herring, Huacai Chen,
devicetree, linux-kernel
In-Reply-To: <20200402104851.368465-1-jiaxun.yang@flygoat.com>
This controller is attached under ISA Bus and can be found
in Loongson-3 systems with RS780E PCH.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
.../bindings/mips/loongson/rs780e-acpi.yaml | 40 +++++++++++++++++++
1 file changed, 40 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/loongson/rs780e-acpi.yaml
diff --git a/Documentation/devicetree/bindings/mips/loongson/rs780e-acpi.yaml b/Documentation/devicetree/bindings/mips/loongson/rs780e-acpi.yaml
new file mode 100644
index 000000000000..d317897e1115
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/loongson/rs780e-acpi.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/mips/loongson/rs780e-acpi.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Loongson RS780E PCH ACPI Controller
+
+maintainers:
+ - Jiaxun Yang <jiaxun.yang@flygoat.com>
+
+description: |
+ This controller can be found in Loongson-3 systems with RS780E PCH.
+
+properties:
+ compatible:
+ const: loongson,rs780e-acpi
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ isa@0 {
+ compatible = "isa";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0 0x1000>;
+
+ acpi@800 {
+ compatible = "loongson,rs780e-acpi";
+ reg = <1 0x800 0x100>;
+ };
+ };
+
+...
--
2.26.0.rc2
^ permalink raw reply related
* Re: [PATCH V3 3/3] arm64: dts: imx8mp: Add thermal zones support
From: Amit Kucheria @ 2020-04-02 10:40 UTC (permalink / raw)
To: Anson Huang
Cc: Zhang Rui, Daniel Lezcano, Rob Herring, Shawn Guo, Sascha Hauer,
kernel, Fabio Estevam, horia.geanta, peng.fan, Linux PM list,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, lakml,
LKML, Linux-imx
In-Reply-To: <1584966504-21719-3-git-send-email-Anson.Huang@nxp.com>
On Mon, Mar 23, 2020 at 6:05 PM Anson Huang <Anson.Huang@nxp.com> wrote:
>
> i.MX8MP has a TMU inside which supports two thermal zones, add support
> for them.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
[snip]
>
> + thermal-zones {
> + cpu-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <2000>;
> + thermal-sensors = <&tmu 0x0>;
No need for 0x0, just use 0
> + trips {
> + cpu_alert0: trip0 {
> + temperature = <85000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + cpu_crit0: trip1 {
> + temperature = <95000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + trip = <&cpu_alert0>;
> + cooling-device =
> + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
> + <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
> + };
> + };
> + };
> +
> + soc-thermal {
> + polling-delay-passive = <250>;
> + polling-delay = <2000>;
> + thermal-sensors = <&tmu 0x1>;
No need for 0x1, just use 1
> + trips {
> + soc_alert0: trip0 {
> + temperature = <85000>;
> + hysteresis = <2000>;
> + type = "passive";
> + };
> +
> + soc_crit0: trip1 {
> + temperature = <95000>;
> + hysteresis = <2000>;
> + type = "critical";
> + };
> + };
You need a cooling-map here since you have a passive trip point.
> + };
> + };
> +
> timer {
> compatible = "arm,armv8-timer";
> interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
> @@ -215,6 +271,13 @@
> gpio-ranges = <&iomuxc 0 114 30>;
> };
>
> + tmu: tmu@30260000 {
> + compatible = "fsl,imx8mp-tmu";
> + reg = <0x30260000 0x10000>;
> + clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
> + #thermal-sensor-cells = <1>;
> + };
> +
> wdog1: watchdog@30280000 {
> compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
> reg = <0x30280000 0x10000>;
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH v2 6/6] dt-bindings: usb: document aspeed vhub device ID/string properties
From: Benjamin Herrenschmidt @ 2020-04-02 10:37 UTC (permalink / raw)
To: Rob Herring
Cc: rentao.bupt, Felipe Balbi, Greg Kroah-Hartman, Joel Stanley,
Andrew Jeffery, Chunfeng Yun, Colin Ian King, Stephen Boyd,
Mark Rutland, Linux USB List,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
linux-aspeed, devicetree, linux-kernel@vger.kernel.org,
OpenBMC Maillist, Tao Ren
In-Reply-To: <CAL_JsqKZeCC352TKFGDNRRogSefF9vq+J=WqCEeg59PBsSOW1w@mail.gmail.com>
On Tue, 2020-03-31 at 10:21 -0600, Rob Herring wrote:
> Surely the descriptor building code can be shared at a minimum.
>
> Regardless of whether gadget configfs fits, usually it is pretty clear
> whether something belongs in DT or userspace. That should be decided
> first.
>
> > Maybe we could expose the port as UDCs but not actually expose them on
> > the bus until the hub is "activated" via a special configfs entry...
>
> If control of the hub is done by userspace, I'd think configuration
> should be there too.
It's not in the current driver. For now, I expose the hub when the
driver loads/initializes, and it creates UDCs for each port, which are
then controlled from userspace.
That said, I did it this way because it was easy, not because there are
fundamental reasons to do so...
The main reason to want to change the hub descriptor is for the device
to advertise a vendor/device ID rather than our generic linux one,
which some vendors might want to do for ... reasons. I didn't implement
that functionality initially as in openbmc case, we didn't care. But I
know some vendors would like to, if anything because from a user
perspective, it's actually nice to have the string tell you that it's
your BMC rather than Linux Fundation Hub.
Originally I suggested we allow that via the device-tree because it was
the simplest way to get there and I love have to deal with less code ..
:)
However, if we want to support the whole language string set etc... it
gets really clumsy. So if there's a strong will to get there all the
way, then configfs is probably the way to go.
In that case, some sugery will probably be needed to make the gadget
descriptor building code a bit less dependent on the overall gadget
stuff... either that, or pre-create a "hub" gadget at driver loading
time that userspace can modify before "plugging".
In that case, the discussion should move back to linux-usb...
Cheers,
Ben.
^ permalink raw reply
* Re: [PATCH 1/5] ARM: dts: at91: sama5d2_ptc_ek: fix sdmmc0 node description
From: Eugen.Hristev @ 2020-04-02 10:27 UTC (permalink / raw)
To: Ludovic.Desroches, Nicolas.Ferre, alexandre.belloni, robh+dt
Cc: devicetree, Tudor.Ambarus, linux-kernel, stable, linux-arm-kernel,
Codrin.Ciubotariu, Cristian.Birsan
In-Reply-To: <5f762bdc-fe07-adbc-af8d-7670b5b4b286@microchip.com>
On 02.04.2020 13:07, Ludovic Desroches - M43218 wrote:
> On 4/2/2020 11:20 AM, Eugen Hristev - M18282 wrote:
>> On 02.04.2020 01:15, Ludovic Desroches wrote:
>>> Remove non-removable and mmc-ddr-1_8v properties from the sdmmc0
>>> node which come probably from an unchecked copy/paste.
>>>
>>> Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
>>> Fixes:42ed535595ec "ARM: dts: at91: introduce the sama5d2 ptc ek board"
>>> Cc: stable@vger.kernel.org # 4.19 and later
>>> ---
>>> arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 2 --
>>> 1 file changed, 2 deletions(-)
>>>
>>> diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
>>> index 1c24ac8019ba7..772809c54c1f3 100644
>>> --- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
>>> +++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
>>> @@ -125,8 +125,6 @@ sdmmc0: sdio-host@a0000000 {
>>> bus-width = <8>;
>>> pinctrl-names = "default";
>>> pinctrl-0 = <&pinctrl_sdmmc0_default>;
>>> - non-removable;
>>> - mmc-ddr-1_8v;
>>
>> Hi Ludovic,
>>
>> I am not sure about the removal of mmc-ddr-1_8v; this means eMMCs
>> connected on this slot won't work in high speed mode, some people use
>> eMMC to SD-Card adapters and stick them into SD-Card slots.
>> Would it be a problem to keep this property here ?
>
> Hi Eugen,
>
> It's not a problem to keep it, but I don't think it makes sense. In this
> case mmc-ddr-3_3v should be added too.
>
> Will it work 'out of the box' with any eMMC to SD-Card adapters and
> eMMCs? I remember discussions where we said HW changes were needed to be
> able to select the voltage for the IOs other than using the VDDSEL
> signal of the controller.
Yes indeed , ddr-3_3v would be needed for those. I can follow up later
with a patch to add that if required.
Thanks !
>
> Regards
>
> Ludovic
>
>
>>
>> Thanks,
>> Eugen
>>
>>> status = "okay";
>>> };
>>>
>>>
>>
>
^ permalink raw reply
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