* Re: [RFC v1 2/3] drivers: nvmem: Add driver for QTI qfprom-efuse support
From: Randy Dunlap @ 2020-05-12 19:20 UTC (permalink / raw)
To: Ravi Kumar Bokka, Srinivas Kandagatla, Rob Herring
Cc: linux-kernel, devicetree, rnayak, saiprakash.ranjan, dhavalp,
mturney, sparate, c_rbokka, mkurumel
In-Reply-To: <1589307480-27508-3-git-send-email-rbokka@codeaurora.org>
On 5/12/20 11:17 AM, Ravi Kumar Bokka wrote:
> diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
> index d7b7f6d..c9345c5 100644
> --- a/drivers/nvmem/Kconfig
> +++ b/drivers/nvmem/Kconfig
> @@ -121,6 +121,16 @@ config QCOM_QFPROM
> This driver can also be built as a module. If so, the module
> will be called nvmem_qfprom.
>
> +config QTI_QFPROM_EFUSE
> + tristate "QTI_QFPROM_EFUSE Support"
> + depends on HAS_IOMEM
> + help
> + Say y here to enable QFPROM-Efuse support. This driver provides access
access to
> + QTI qfprom efuse via nvmem interface.
> +
> + This driver can also be built as a module. If so, the module
> + will be called nvmem_qfprom-efuse.
The last 3 non-blank lines should be indented with one tab + 2 spaces
instead of lots of spaces.
> +
> config NVMEM_SPMI_SDAM
> tristate "SPMI SDAM Support"
> depends on SPMI
--
~Randy
^ permalink raw reply
* [PATCH v3] dt-bindings: power: Convert bq27xxx dt to yaml
From: Dan Murphy @ 2020-05-12 19:14 UTC (permalink / raw)
To: sre
Cc: linux-pm, robh, linux-kernel, devicetree, Dan Murphy,
Pali Rohár, Andrew F . Davis
Convert the bq27xxx.txt to yaml format
CC: Pali Rohár <pali@kernel.org>
CC: Andrew F. Davis <afd@ti.com>
Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
.../bindings/power/supply/bq27xxx.txt | 56 ------------
.../bindings/power/supply/bq27xxx.yaml | 91 +++++++++++++++++++
2 files changed, 91 insertions(+), 56 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/power/supply/bq27xxx.txt
create mode 100644 Documentation/devicetree/bindings/power/supply/bq27xxx.yaml
diff --git a/Documentation/devicetree/bindings/power/supply/bq27xxx.txt b/Documentation/devicetree/bindings/power/supply/bq27xxx.txt
deleted file mode 100644
index 4fa8e08df2b6..000000000000
--- a/Documentation/devicetree/bindings/power/supply/bq27xxx.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-TI BQ27XXX fuel gauge family
-
-Required properties:
-- compatible: contains one of the following:
- * "ti,bq27200" - BQ27200
- * "ti,bq27210" - BQ27210
- * "ti,bq27500" - deprecated, use revision specific property below
- * "ti,bq27510" - deprecated, use revision specific property below
- * "ti,bq27520" - deprecated, use revision specific property below
- * "ti,bq27500-1" - BQ27500/1
- * "ti,bq27510g1" - BQ27510-g1
- * "ti,bq27510g2" - BQ27510-g2
- * "ti,bq27510g3" - BQ27510-g3
- * "ti,bq27520g1" - BQ27520-g1
- * "ti,bq27520g2" - BQ27520-g2
- * "ti,bq27520g3" - BQ27520-g3
- * "ti,bq27520g4" - BQ27520-g4
- * "ti,bq27521" - BQ27521
- * "ti,bq27530" - BQ27530
- * "ti,bq27531" - BQ27531
- * "ti,bq27541" - BQ27541
- * "ti,bq27542" - BQ27542
- * "ti,bq27546" - BQ27546
- * "ti,bq27742" - BQ27742
- * "ti,bq27545" - BQ27545
- * "ti,bq27411" - BQ27411
- * "ti,bq27421" - BQ27421
- * "ti,bq27425" - BQ27425
- * "ti,bq27426" - BQ27426
- * "ti,bq27441" - BQ27441
- * "ti,bq27621" - BQ27621
-- reg: integer, I2C address of the fuel gauge.
-
-Optional properties:
-- monitored-battery: phandle of battery characteristics node
- The fuel gauge uses the following battery properties:
- + energy-full-design-microwatt-hours
- + charge-full-design-microamp-hours
- + voltage-min-design-microvolt
- Both or neither of the *-full-design-*-hours properties must be set.
- See Documentation/devicetree/bindings/power/supply/battery.txt
-
-Example:
-
- bat: battery {
- compatible = "simple-battery";
- voltage-min-design-microvolt = <3200000>;
- energy-full-design-microwatt-hours = <5290000>;
- charge-full-design-microamp-hours = <1430000>;
- };
-
- bq27510g3: fuel-gauge@55 {
- compatible = "ti,bq27510g3";
- reg = <0x55>;
- monitored-battery = <&bat>;
- };
diff --git a/Documentation/devicetree/bindings/power/supply/bq27xxx.yaml b/Documentation/devicetree/bindings/power/supply/bq27xxx.yaml
new file mode 100644
index 000000000000..03d1020a2e47
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/supply/bq27xxx.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2020 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/power/supply/bq27xxx.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: TI BQ27XXX fuel gauge family
+
+maintainers:
+ - Pali Rohár <pali@kernel.org>
+ - Andrew F. Davis <afd@ti.com>
+ - Sebastian Reichel <sre@kernel.org>
+
+description: |
+ Support various Texas Instruments fuel gauge devices that share similar
+ register maps and power supply properties
+
+allOf:
+ - $ref: power-supply.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ti,bq27200
+ - ti,bq27210
+ - ti,bq27500 # deprecated, use revision specific property below
+ - ti,bq27510 # deprecated, use revision specific property below
+ - ti,bq27520 # deprecated, use revision specific property below
+ - ti,bq27500-1
+ - ti,bq27510g1
+ - ti,bq27510g2
+ - ti,bq27510g3
+ - ti,bq27520g1
+ - ti,bq27520g2
+ - ti,bq27520g3
+ - ti,bq27520g4
+ - ti,bq27521
+ - ti,bq27530
+ - ti,bq27531
+ - ti,bq27541
+ - ti,bq27542
+ - ti,bq27546
+ - ti,bq27742
+ - ti,bq27545
+ - ti,bq27411
+ - ti,bq27421
+ - ti,bq27425
+ - ti,bq27426
+ - ti,bq27441
+ - ti,bq27621
+
+ reg:
+ maxItems: 1
+ description: integer, I2C address of the fuel gauge.
+
+ monitored-battery:
+ description: |
+ phandle of battery characteristics node.
+ The fuel gauge uses the following battery properties:
+ - energy-full-design-microwatt-hours
+ - charge-full-design-microamp-hours
+ - voltage-min-design-microvolt
+ Both or neither of the *-full-design-*-hours properties must be set.
+ See Documentation/devicetree/bindings/power/supply/battery.txt
+
+ power-supplies: true
+
+required:
+ - compatible
+ - reg
+additionalProperties: false
+
+examples:
+ - |
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bat: battery {
+ compatible = "simple-battery";
+ voltage-min-design-microvolt = <3200000>;
+ energy-full-design-microwatt-hours = <5290000>;
+ charge-full-design-microamp-hours = <1430000>;
+ };
+
+ bq27510g3: fuel-gauge@55 {
+ compatible = "ti,bq27510g3";
+ reg = <0x55>;
+ monitored-battery = <&bat>;
+ };
+ };
--
2.25.1
^ permalink raw reply related
* Re: [PATCH v3] dt-bindings: power: Convert bq27xxx dt to yaml
From: Dan Murphy @ 2020-05-12 19:15 UTC (permalink / raw)
To: sre
Cc: linux-pm, robh, linux-kernel, devicetree, Pali Rohár,
Andrew F . Davis
In-Reply-To: <20200512191451.1517-1-dmurphy@ti.com>
All
On 5/12/20 2:14 PM, Dan Murphy wrote:
> Convert the bq27xxx.txt to yaml format
Please ignore this patch I send the wrong one
Dan
^ permalink raw reply
* [RESEND PATCH v3] dt-bindings: power: Convert bq27xxx dt to yaml
From: Dan Murphy @ 2020-05-12 19:19 UTC (permalink / raw)
To: sre
Cc: linux-pm, robh, linux-kernel, devicetree, Dan Murphy,
Pali Rohár, Andrew F . Davis
Convert the bq27xxx.txt to yaml format
CC: Pali Rohár <pali@kernel.org>
CC: Andrew F. Davis <afd@ti.com>
Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
v3 - Added power supply reference to yaml, fixed the deprecated compatibles,
I did not change any compatibles as discussed in the list these should come in
separate patches - https://lore.kernel.org/patchwork/patch/1237912/
.../bindings/power/supply/bq27xxx.txt | 56 ------------
.../bindings/power/supply/bq27xxx.yaml | 91 +++++++++++++++++++
2 files changed, 91 insertions(+), 56 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/power/supply/bq27xxx.txt
create mode 100644 Documentation/devicetree/bindings/power/supply/bq27xxx.yaml
diff --git a/Documentation/devicetree/bindings/power/supply/bq27xxx.txt b/Documentation/devicetree/bindings/power/supply/bq27xxx.txt
deleted file mode 100644
index 4fa8e08df2b6..000000000000
--- a/Documentation/devicetree/bindings/power/supply/bq27xxx.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-TI BQ27XXX fuel gauge family
-
-Required properties:
-- compatible: contains one of the following:
- * "ti,bq27200" - BQ27200
- * "ti,bq27210" - BQ27210
- * "ti,bq27500" - deprecated, use revision specific property below
- * "ti,bq27510" - deprecated, use revision specific property below
- * "ti,bq27520" - deprecated, use revision specific property below
- * "ti,bq27500-1" - BQ27500/1
- * "ti,bq27510g1" - BQ27510-g1
- * "ti,bq27510g2" - BQ27510-g2
- * "ti,bq27510g3" - BQ27510-g3
- * "ti,bq27520g1" - BQ27520-g1
- * "ti,bq27520g2" - BQ27520-g2
- * "ti,bq27520g3" - BQ27520-g3
- * "ti,bq27520g4" - BQ27520-g4
- * "ti,bq27521" - BQ27521
- * "ti,bq27530" - BQ27530
- * "ti,bq27531" - BQ27531
- * "ti,bq27541" - BQ27541
- * "ti,bq27542" - BQ27542
- * "ti,bq27546" - BQ27546
- * "ti,bq27742" - BQ27742
- * "ti,bq27545" - BQ27545
- * "ti,bq27411" - BQ27411
- * "ti,bq27421" - BQ27421
- * "ti,bq27425" - BQ27425
- * "ti,bq27426" - BQ27426
- * "ti,bq27441" - BQ27441
- * "ti,bq27621" - BQ27621
-- reg: integer, I2C address of the fuel gauge.
-
-Optional properties:
-- monitored-battery: phandle of battery characteristics node
- The fuel gauge uses the following battery properties:
- + energy-full-design-microwatt-hours
- + charge-full-design-microamp-hours
- + voltage-min-design-microvolt
- Both or neither of the *-full-design-*-hours properties must be set.
- See Documentation/devicetree/bindings/power/supply/battery.txt
-
-Example:
-
- bat: battery {
- compatible = "simple-battery";
- voltage-min-design-microvolt = <3200000>;
- energy-full-design-microwatt-hours = <5290000>;
- charge-full-design-microamp-hours = <1430000>;
- };
-
- bq27510g3: fuel-gauge@55 {
- compatible = "ti,bq27510g3";
- reg = <0x55>;
- monitored-battery = <&bat>;
- };
diff --git a/Documentation/devicetree/bindings/power/supply/bq27xxx.yaml b/Documentation/devicetree/bindings/power/supply/bq27xxx.yaml
new file mode 100644
index 000000000000..03d1020a2e47
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/supply/bq27xxx.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2020 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/power/supply/bq27xxx.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: TI BQ27XXX fuel gauge family
+
+maintainers:
+ - Pali Rohár <pali@kernel.org>
+ - Andrew F. Davis <afd@ti.com>
+ - Sebastian Reichel <sre@kernel.org>
+
+description: |
+ Support various Texas Instruments fuel gauge devices that share similar
+ register maps and power supply properties
+
+allOf:
+ - $ref: power-supply.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ti,bq27200
+ - ti,bq27210
+ - ti,bq27500 # deprecated, use revision specific property below
+ - ti,bq27510 # deprecated, use revision specific property below
+ - ti,bq27520 # deprecated, use revision specific property below
+ - ti,bq27500-1
+ - ti,bq27510g1
+ - ti,bq27510g2
+ - ti,bq27510g3
+ - ti,bq27520g1
+ - ti,bq27520g2
+ - ti,bq27520g3
+ - ti,bq27520g4
+ - ti,bq27521
+ - ti,bq27530
+ - ti,bq27531
+ - ti,bq27541
+ - ti,bq27542
+ - ti,bq27546
+ - ti,bq27742
+ - ti,bq27545
+ - ti,bq27411
+ - ti,bq27421
+ - ti,bq27425
+ - ti,bq27426
+ - ti,bq27441
+ - ti,bq27621
+
+ reg:
+ maxItems: 1
+ description: integer, I2C address of the fuel gauge.
+
+ monitored-battery:
+ description: |
+ phandle of battery characteristics node.
+ The fuel gauge uses the following battery properties:
+ - energy-full-design-microwatt-hours
+ - charge-full-design-microamp-hours
+ - voltage-min-design-microvolt
+ Both or neither of the *-full-design-*-hours properties must be set.
+ See Documentation/devicetree/bindings/power/supply/battery.txt
+
+ power-supplies: true
+
+required:
+ - compatible
+ - reg
+additionalProperties: false
+
+examples:
+ - |
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ bat: battery {
+ compatible = "simple-battery";
+ voltage-min-design-microvolt = <3200000>;
+ energy-full-design-microwatt-hours = <5290000>;
+ charge-full-design-microamp-hours = <1430000>;
+ };
+
+ bq27510g3: fuel-gauge@55 {
+ compatible = "ti,bq27510g3";
+ reg = <0x55>;
+ monitored-battery = <&bat>;
+ };
+ };
--
2.25.1
^ permalink raw reply related
* Re: [PATCH v2 05/14] net: core: provide priv_to_netdev()
From: David Miller @ 2020-05-12 19:30 UTC (permalink / raw)
To: brgl
Cc: robh+dt, matthias.bgg, john, sean.wang, Mark-MC.Lee, kuba, arnd,
fparent, hkallweit1, edwin.peer, devicetree, linux-kernel, netdev,
linux-arm-kernel, linux-mediatek, stephane.leprovost, pedro.tsai,
andrew.perepech, bgolaszewski
In-Reply-To: <CAMRc=MdUCkgCo8UndDbhQRZt_tXJJjtR4uM2g05N5ti7Hw1f2w@mail.gmail.com>
From: Bartosz Golaszewski <brgl@bgdev.pl>
Date: Tue, 12 May 2020 08:04:39 +0200
> I will if you insist but would you mind sharing some details on why it
> was removed? To me it still makes more sense than storing the pointer
> to a structure in *that* structure.
Flexibility in implementation of where the private data is located
and how it is allocated.
And yes, I do insist.
^ permalink raw reply
* Re: [PATCH net-next v2] dt-bindings: net: Convert UniPhier AVE4 controller to json-schema
From: David Miller @ 2020-05-12 19:31 UTC (permalink / raw)
To: hayashi.kunihiko
Cc: robh+dt, yamada.masahiro, netdev, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <1589268410-17066-1-git-send-email-hayashi.kunihiko@socionext.com>
From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Date: Tue, 12 May 2020 16:26:50 +0900
> Convert the UniPhier AVE4 controller binding to DT schema format.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> ---
>
> Changes since v1:
> - Set true to phy-mode and phy-handle instead of $ref
> - Add mac-address and local-mac-address for existing dts warning
Applied to net-next, thank you.
^ permalink raw reply
* [RFC PATCH] media: v4l: xilinx: xcsi2rxss_enum_mbus_code() can be static
From: kbuild test robot @ 2020-05-12 19:36 UTC (permalink / raw)
To: Vishal Sagar, Hyun Kwon, laurent.pinchart, mchehab, robh+dt,
mark.rutland, Michal Simek, linux-media, devicetree, hans.verkuil,
linux-arm-kernel, linux-kernel, Dinesh Kumar, Sandip Kothari,
Luca Ceresoli, Jacopo Mondi
Cc: kbuild-all, Hyun Kwon, Vishal Sagar
In-Reply-To: <20200512151947.120348-3-vishal.sagar@xilinx.com>
Signed-off-by: kbuild test robot <lkp@intel.com>
---
xilinx-csi2rxss.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/media/platform/xilinx/xilinx-csi2rxss.c b/drivers/media/platform/xilinx/xilinx-csi2rxss.c
index cac08149ae7a8..3c2e9ff166db1 100644
--- a/drivers/media/platform/xilinx/xilinx-csi2rxss.c
+++ b/drivers/media/platform/xilinx/xilinx-csi2rxss.c
@@ -813,9 +813,9 @@ static int xcsi2rxss_set_format(struct v4l2_subdev *sd,
*
* Return: -EINVAL or zero on success
*/
-int xcsi2rxss_enum_mbus_code(struct v4l2_subdev *sd,
- struct v4l2_subdev_pad_config *cfg,
- struct v4l2_subdev_mbus_code_enum *code)
+static int xcsi2rxss_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_mbus_code_enum *code)
{
struct xcsi2rxss_state *state = to_xcsi2rxssstate(sd);
u32 dt, n;
^ permalink raw reply related
* Re: [PATCH v13 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver
From: kbuild test robot @ 2020-05-12 19:36 UTC (permalink / raw)
To: Vishal Sagar, Hyun Kwon, laurent.pinchart, mchehab, robh+dt,
mark.rutland, Michal Simek, linux-media, devicetree, hans.verkuil,
linux-arm-kernel, linux-kernel, Dinesh Kumar, Sandip Kothari,
Luca Ceresoli, Jacopo Mondi
Cc: kbuild-all, Hyun Kwon, Vishal Sagar
In-Reply-To: <20200512151947.120348-3-vishal.sagar@xilinx.com>
Hi Vishal,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linuxtv-media/master]
[also build test WARNING on v5.7-rc5 next-20200512]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Vishal-Sagar/Add-support-for-Xilinx-CSI2-Receiver-Subsystem/20200512-232348
base: git://linuxtv.org/media_tree.git master
reproduce:
# apt-get install sparse
# sparse version: v0.6.1-191-gc51a0382-dirty
make ARCH=x86_64 allmodconfig
make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'
If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
>> drivers/media/platform/xilinx/xilinx-csi2rxss.c:816:5: sparse: sparse: symbol 'xcsi2rxss_enum_mbus_code' was not declared. Should it be static?
Please review and possibly fold the followup patch.
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply
* Re: [PATCH 2/4] dt-bindings: sram: add documentation for reserved-only flag
From: Stephen Warren @ 2020-05-12 19:45 UTC (permalink / raw)
To: Mian Yousaf Kaukab
Cc: robh+dt, robin.murphy, devicetree, talho, thierry.reding,
jonathanh, linux-tegra, linux-kernel, linux-arm-kernel, afaerber,
arnd, gregkh
In-Reply-To: <20200512144803.24344-2-ykaukab@suse.de>
On 5/12/20 8:48 AM, Mian Yousaf Kaukab wrote:
> Add documentation for the new optional flag added for SRAM driver.
> diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml
> + reserved-only:
> + description:
> + The flag indicating, that only SRAM reserved regions have to be remapped.
> + remapping type is selected depending upon no-memory-wc as usual.
> + type: boolean
This feels a bit like a SW flag rather than a HW description, so I'm not
sure it's appropriate to put it into DT.
Are there any cases where the SW should map all of the SRAM, i.e. where
we wouldn't expect to set reserved-only? I'd expect reserved-only to be
the default, and perhaps only, mode of operation for the SRAM driver. If
we can't do that because some SW currently expects to be able to map
arbitrary portions of the SRAM, shouldn't that SW be fixed to tell the
SRAM driver which parts it's using, hence still allowing the driver to
only map in-use portions?
^ permalink raw reply
* Re: [PATCH v2 5/6] dmaengine: dw: Introduce max burst length hw config
From: Serge Semin @ 2020-05-12 19:47 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Serge Semin, Vinod Koul, Viresh Kumar, Dan Williams,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Rob Herring, linux-mips, devicetree, dmaengine,
linux-kernel
In-Reply-To: <20200512191208.GG185537@smile.fi.intel.com>
On Tue, May 12, 2020 at 10:12:08PM +0300, Andy Shevchenko wrote:
> On Tue, May 12, 2020 at 05:08:20PM +0300, Serge Semin wrote:
> > On Fri, May 08, 2020 at 02:41:53PM +0300, Andy Shevchenko wrote:
> > > On Fri, May 08, 2020 at 01:53:03PM +0300, Serge Semin wrote:
> > > > IP core of the DW DMA controller may be synthesized with different
> > > > max burst length of the transfers per each channel. According to Synopsis
> > > > having the fixed maximum burst transactions length may provide some
> > > > performance gain. At the same time setting up the source and destination
> > > > multi size exceeding the max burst length limitation may cause a serious
> > > > problems. In our case the system just hangs up. In order to fix this
> > > > lets introduce the max burst length platform config of the DW DMA
> > > > controller device and don't let the DMA channels configuration code
> > > > exceed the burst length hardware limitation. Depending on the IP core
> > > > configuration the maximum value can vary from channel to channel.
> > > > It can be detected either in runtime from the DWC parameter registers
> > > > or from the dedicated dts property.
> > >
> > > I'm wondering what can be the scenario when your peripheral will ask something
> > > which is not supported by DMA controller?
> >
> > I may misunderstood your statement, because seeing your activity around my
> > patchsets including the SPI patchset and sometimes very helpful comments,
> > this question answer seems too obvious to see you asking it.
> >
> > No need to go far for an example. See the DW APB SSI driver. Its DMA module
> > specifies the burst length to be 16, while not all of ours channels supports it.
> > Yes, originally it has been developed for the Intel Midfield SPI, but since I
> > converted the driver into a generic code we can't use a fixed value. For instance
> > in our hardware only two DMA channels of total 16 are capable of bursting up to
> > 16 bytes (data items) at a time, the rest of them are limited with up to 4 bytes
> > burst length. While there are two SPI interfaces, each of which need to have two
> > DMA channels for communications. So I need four channels in total to allocate to
> > provide the DMA capability for all interfaces. In order to set the SPI controller
> > up with valid optimized parameters the max-burst-length is required. Otherwise we
> > can end up with buffers overrun/underrun.
>
> Right, and we come to the question which channel better to be used by SPI and
> the rest devices. Without specific filter function you can easily get into a
> case of inverted optimizations, when SPI got channels with burst = 4, while
> it's needed 16, and other hardware otherwise. Performance wise it's worse
> scenario which we may avoid in the first place, right?
If we start thinking like you said, we'll get stuck at a problem of which interfaces
should get faster DMA channels and which one should be left with slowest. In general
this task can't be solved, because without any application-specific requirement
they all are equally valuable and deserve to have the best resources allocated.
So we shouldn't assume that some interface is better or more valuable than
another, therefore in generic DMA client code any filtering is redundant.
>
> > > Peripheral needs to supply a lot of configuration parameters specific to the
> > > DMA controller in use (that's why we have struct dw_dma_slave).
> > > So, seems to me the feasible approach is supply correct data in the first place.
> >
> > How to supply a valid data if clients don't know the DMA controller limitations
> > in general?
>
> This is a good question. DMA controllers are quite different and having unified
> capabilities structure for all is almost impossible task to fulfil. That's why
> custom filter function(s) can help here. Based on compatible string you can
> implement whatever customized quirks like two functions, for example, to try 16
> burst size first and fallback to 4 if none was previously found.
Right. As I said in the previous email it's up to the corresponding platforms to
decide the criteria of the filtering including the max-burst length value.
Even though the DW DMA channels resources aren't uniform on Baikal-T1 SoC I also
won't do the filter-based channel allocation, because I can't predict the SoC
application. Some of them may be used on a platform with active SPI interface
utilization, some with specific requirements to UARTs and so on.
>
> > > If you have specific channels to acquire then you probably need to provide a
> > > custom xlate / filter functions. Because above seems a bit hackish workaround
> > > of dynamic channel allocation mechanism.
> >
> > No, I don't have a specific channel to acquire and in general you may use any
> > returned from the DMA subsystem (though some platforms may need a dedicated
> > channels to use, in this case xlate / filter is required). In our SoC any DW DMAC
> > channel can be used for any DMA-capable peripherals like SPI, I2C, UART. But the
> > their DMA settings must properly and optimally configured. It can be only done
> > if you know the DMA controller parameters like max burst length, max block-size,
> > etc.
> >
> > So no. The change proposed by this patch isn't workaround, but a useful feature,
> > moreover expected to be supported by the generic DMA subsystem.
>
> See above.
>
> > > But let's see what we can do better. Since maximum is defined on the slave side
> > > device, it probably needs to define minimum as well, otherwise it's possible
> > > that some hardware can't cope underrun bursts.
> >
> > There is no need to define minimum if such limit doesn't exists except a
> > natural 1. Moreover it doesn't exist for all DMA controllers seeing noone has
> > added such capability into the generic DMA subsystem so far.
>
> There is a contract between provider and consumer about DMA resource. That's
> why both sides should participate in fulfilling it. Theoretically it may be a
> hardware that doesn't support minimum burst available in DMA by a reason. For
> such we would need minimum to be provided as well.
I don't think 'theoretical' consideration counts when implementing something in
kernel. That 'theoretical' may never happen, but you'll end up supporting a
dummy functionality. Practicality is what kernel developers normally place
before anything else.
-Sergey
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
^ permalink raw reply
* Re: [PATCH V4 2/8] dt-bindings: clock: Add schema for QCOM IPQ apss pll
From: Bjorn Andersson @ 2020-05-12 19:56 UTC (permalink / raw)
To: Sivaprakash Murugesan
Cc: agross, mturquette, sboyd, robh+dt, jassisinghbrar, linux-arm-msm,
linux-clk, devicetree, linux-kernel
In-Reply-To: <1588573224-3038-3-git-send-email-sivaprak@codeaurora.org>
On Sun 03 May 23:20 PDT 2020, Sivaprakash Murugesan wrote:
> Add dt-binding for apss pll found on QCOM IPQ platforms
>
> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
This seems quite similar to the existing qcom,a53pll binding, can't you
just describe both in the same binding?
> ---
> .../bindings/clock/qcom,ipq-apsspll.yaml | 49 ++++++++++++++++++++++
> 1 file changed, 49 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq-apsspll.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq-apsspll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq-apsspll.yaml
> new file mode 100644
> index 0000000..dd12ec4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq-apsspll.yaml
> @@ -0,0 +1,49 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,ipq-apsspll.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm IPQ APSS PLL Binding
> +
> +maintainers:
> + - Sivaprakash Murugesan <sivaprak@codeaurora.org>
> +
> +description:
> + The APSS PLL is the main clock that feds the CPUs on QCOM IPQ platforms.
> + It can support frequencies above 1GHz.
> +
> +properties:
> + compatible:
> + const: qcom,ipq-apss-pll
Allow me to claim that this is not the last IPQ, with an APSS PLL, which
means that this compatible is no good.
I think you want a compatible on the format qcom,ipq<numbers>-a53pll.
Regards,
Bjorn
> +
> + reg:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 0
> +
> + clocks:
> + items:
> + - description: board XO clock
> +
> + clock-names:
> + items:
> + - const: xo
> +
> +required:
> + - compatible
> + - reg
> + - '#clock-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + a53pll_ipq: clock@b116000 {
> + compatible = "qcom,ipq-apss-pll";
> + reg = <0x0b116000 0x40>;
> + #clock-cells = <0>;
> + clocks = <&xo>;
> + clock-names = "xo";
> + };
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH 00/17] spi: dw: Add generic DW DMA controller support
From: Serge Semin @ 2020-05-12 20:07 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Maxim Kaurkin, Pavel Parkhomenko, Ekaterina Skachko, Vadim Vlasov,
Alexey Kolotnikov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Andy Shevchenko, Gareth Williams,
Rob Herring, linux-mips, linux-spi, devicetree, linux-kernel
In-Reply-To: <20200508133336.GK4820@sirena.org.uk>
On Fri, May 08, 2020 at 02:33:36PM +0100, Mark Brown wrote:
> On Fri, May 08, 2020 at 04:29:25PM +0300, Serge Semin wrote:
>
> > Serge Semin (17):
> > dt-bindings: spi: Convert DW SPI binding to DT schema
>
> Please don't make new feature development dependent on conversion to the
> new schema format, there's quite a backlog of reviews of schema
> conversions so it can slow things down. It's good to do the conversions
> but please do them after adding any new stuff to the binding rather than
> before.
So by saying this do you want me to revert an order of the first two patches
in the series, right? So the series would first add the DMA properties support
to the binding, then would convert the binding file to DT schema.
-Sergey
^ permalink raw reply
* Re: [PATCH V4 5/8] clk: qcom: Add ipq apss clock controller
From: Bjorn Andersson @ 2020-05-12 20:12 UTC (permalink / raw)
To: Sivaprakash Murugesan
Cc: agross, mturquette, sboyd, robh+dt, jassisinghbrar, linux-arm-msm,
linux-clk, devicetree, linux-kernel
In-Reply-To: <1588573224-3038-6-git-send-email-sivaprak@codeaurora.org>
On Sun 03 May 23:20 PDT 2020, Sivaprakash Murugesan wrote:
> The CPU on Qualcomm ipq platform is clocked primarily by a aplha PLL
> and xo which are connected to a mux and enable block.
>
> Add support for the mux and enable block which feeds the CPU on ipq
> based devices.
>
As with the A53 binding, I don't believe that this driver will support
all past, present and future IPQ APSSs. Please make it more specific.
Regards,
Bjorn
> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
> ---
> [V4]
> * Addressed review comments
> drivers/clk/qcom/Kconfig | 11 +++++
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/apss-ipq.c | 106 ++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 118 insertions(+)
> create mode 100644 drivers/clk/qcom/apss-ipq.c
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index e70aa01..8d8465e 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -97,6 +97,17 @@ config IPQ_APSS_PLL
> Say Y if you want to support CPU frequency scaling on ipq based
> devices.
>
> +config IPQ_APSS
> + tristate "IPQ APSS Clock Controller"
> + select IPQ_APSS_PLL
> + depends on QCOM_APCS_IPC || COMPILE_TEST
> + help
> + Support for APSS clock controller on IPQ platforms. The
> + APSS clock controller manages the Mux and enable block that feeds the
> + CPUs.
> + Say Y if you want to support CPU frequency scaling on
> + ipq based devices.
> +
> config IPQ_GCC_4019
> tristate "IPQ4019 Global Clock Controller"
> help
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index b4a6ba1..aab7a58 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -20,6 +20,7 @@ clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
> obj-$(CONFIG_APQ_GCC_8084) += gcc-apq8084.o
> obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o
> obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
> +obj-$(CONFIG_IPQ_APSS) += apss-ipq.o
> obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
> obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
> obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
> diff --git a/drivers/clk/qcom/apss-ipq.c b/drivers/clk/qcom/apss-ipq.c
> new file mode 100644
> index 0000000..59ed8e7
> --- /dev/null
> +++ b/drivers/clk/qcom/apss-ipq.c
> @@ -0,0 +1,106 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/err.h>
> +#include <linux/platform_device.h>
> +#include <linux/clk-provider.h>
> +#include <linux/regmap.h>
> +#include <linux/module.h>
> +
> +#include <dt-bindings/clock/qcom,apss-ipq.h>
> +
> +#include "common.h"
> +#include "clk-regmap.h"
> +#include "clk-branch.h"
> +#include "clk-alpha-pll.h"
> +#include "clk-regmap-mux.h"
> +
> +enum {
> + P_XO,
> + P_APSS_PLL_EARLY,
> +};
> +
> +static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
> + { .fw_name = "xo" },
> + { .fw_name = "pll" },
> +};
> +
> +static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
> + { P_XO, 0 },
> + { P_APSS_PLL_EARLY, 5 },
> +};
> +
> +static struct clk_regmap_mux apcs_alias0_clk_src = {
> + .reg = 0x0050,
> + .width = 3,
> + .shift = 7,
> + .parent_map = parents_apcs_alias0_clk_src_map,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "apcs_alias0_clk_src",
> + .parent_data = parents_apcs_alias0_clk_src,
> + .num_parents = 2,
> + .ops = &clk_regmap_mux_closest_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_branch apcs_alias0_core_clk = {
> + .halt_reg = 0x0058,
> + .clkr = {
> + .enable_reg = 0x0058,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "apcs_alias0_core_clk",
> + .parent_hws = (const struct clk_hw *[]){
> + &apcs_alias0_clk_src.clkr.hw },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +static const struct regmap_config apss_ipq_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x1000,
> + .fast_io = true,
> +};
> +
> +static struct clk_regmap *apss_ipq_clks[] = {
> + [APCS_ALIAS0_CLK_SRC] = &apcs_alias0_clk_src.clkr,
> + [APCS_ALIAS0_CORE_CLK] = &apcs_alias0_core_clk.clkr,
> +};
> +
> +static const struct qcom_cc_desc apss_ipq_desc = {
> + .config = &apss_ipq_regmap_config,
> + .clks = apss_ipq_clks,
> + .num_clks = ARRAY_SIZE(apss_ipq_clks),
> +};
> +
> +static int apss_ipq_probe(struct platform_device *pdev)
> +{
> + struct regmap *regmap;
> +
> + regmap = dev_get_regmap(pdev->dev.parent, NULL);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + return qcom_cc_really_probe(pdev, &apss_ipq_desc, regmap);
> +}
> +
> +static struct platform_driver apss_ipq_driver = {
> + .probe = apss_ipq_probe,
> + .driver = {
> + .name = "qcom,apss-ipq-clk",
> + },
> +};
> +
> +module_platform_driver(apss_ipq_driver);
> +
> +MODULE_DESCRIPTION("QCOM APSS IPQ CLK Driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH V4 8/8] arm64: dts: ipq6018: Add a53 pll and apcs clock
From: Bjorn Andersson @ 2020-05-12 20:24 UTC (permalink / raw)
To: Sivaprakash Murugesan
Cc: agross, mturquette, sboyd, robh+dt, jassisinghbrar, linux-arm-msm,
linux-clk, devicetree, linux-kernel
In-Reply-To: <1588573224-3038-9-git-send-email-sivaprak@codeaurora.org>
On Sun 03 May 23:20 PDT 2020, Sivaprakash Murugesan wrote:
> add support for apps pll and apcs clock.
>
> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 16 +++++++++++++---
> 1 file changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> index 1aa8d85..af2ceeb 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -294,12 +294,22 @@
> };
>
> apcs_glb: mailbox@b111000 {
> - compatible = "qcom,ipq8074-apcs-apps-global";
> - reg = <0x0b111000 0xc>;
> -
> + compatible = "qcom,ipq6018-apcs-apps-global";
> + reg = <0x0b111000 0x1000>;
My documentation states that IPQ8074 indeed has this block at
0x0b111000, but IPQ6018 it's at 0x6b111000. Can you confirm this is
correct? Same with the pll below.
Apart from that the patch looks good.
Regards,
Bjorn
> + #clock-cells = <1>;
> + clocks = <&apsspll>, <&xo>;
> + clock-names = "pll", "xo";
> #mbox-cells = <1>;
> };
>
> + apsspll: clock@b116000 {
> + compatible = "qcom,ipq-apss-pll";
> + reg = <0x0b116000 0x40>;
> + #clock-cells = <0>;
> + clocks = <&xo>;
> + clock-names = "xo";
> + };
> +
> timer {
> compatible = "arm,armv8-timer";
> interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> --
> 2.7.4
>
^ permalink raw reply
* Re: [v1] drm/bridge: ensure bridge suspend happens during PM sleep
From: Stephen Boyd @ 2020-05-12 20:26 UTC (permalink / raw)
To: Harigovindan P, devicetree, dri-devel, freedreno, linux-arm-msm
Cc: Harigovindan P, linux-kernel, robdclark, seanpaul, hoegsberg,
kalyan_t, nganji, dianders
In-Reply-To: <20200422090443.12529-1-harigovi@codeaurora.org>
The subject is not specific enough. I'd expect it to be something like:
drm/bridge: ti-sn65dsi86: ensure bridge suspend happens during PM sleep
Quoting Harigovindan P (2020-04-22 02:04:43)
> ti-sn65dsi86 bridge is enumerated as a runtime device.
>
> Adding sleep ops to force runtime_suspend when PM suspend is
> requested on the device.
>
> This change needs to be taken along with the series:
> https://patchwork.kernel.org/patch/11494309/
Why? It doesn't seem like it should be required to go along with a qcom
specific driver patch.
>
> Signed-off-by: Harigovindan P <harigovi@codeaurora.org>
> ---
Besides the subject:
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
^ permalink raw reply
* Re: [PATCH V4 7/8] mailbox: qcom: Add ipq6018 apcs compatible
From: Bjorn Andersson @ 2020-05-12 20:19 UTC (permalink / raw)
To: Sivaprakash Murugesan
Cc: agross, mturquette, sboyd, robh+dt, jassisinghbrar, linux-arm-msm,
linux-clk, devicetree, linux-kernel
In-Reply-To: <1588573224-3038-8-git-send-email-sivaprak@codeaurora.org>
On Sun 03 May 23:20 PDT 2020, Sivaprakash Murugesan wrote:
> The Qualcomm ipq6018 has apcs block, add compatible for the same.
> Also, the apcs provides a clock controller functionality similar
> to msm8916 but the clock driver is different.
>
> Create a child platform device based on the apcs compatible for the
> clock controller functionality.
>
> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
> ---
> drivers/mailbox/qcom-apcs-ipc-mailbox.c | 26 +++++++++++++++++---------
> 1 file changed, 17 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> index eeebafd..7c0c4b0 100644
> --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> @@ -45,6 +45,16 @@ static const struct mbox_chan_ops qcom_apcs_ipc_ops = {
> .send_data = qcom_apcs_ipc_send_data,
> };
>
> +static const struct of_device_id apcs_clk_match_table[] = {
> + { .compatible = "qcom,msm8916-apcs-kpss-global",
> + .data = "qcom-apcs-msm8916-clk", },
These are easier to read if you ignore the 80-char limit.
Unless Jassi's object that is.
> + { .compatible = "qcom,qcs404-apcs-apps-global",
> + .data = "qcom-apcs-msm8916-clk", },
> + { .compatible = "qcom,ipq6018-apcs-apps-global",
Add your entry on top, to maintain sort order.
> + .data = "qcom,apss-ipq-clk", },
> + {}
> +};
> +
> static int qcom_apcs_ipc_probe(struct platform_device *pdev)
> {
> struct qcom_apcs_ipc *apcs;
> @@ -54,11 +64,7 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
> void __iomem *base;
> unsigned long i;
> int ret;
> - const struct of_device_id apcs_clk_match_table[] = {
> - { .compatible = "qcom,msm8916-apcs-kpss-global", },
> - { .compatible = "qcom,qcs404-apcs-apps-global", },
> - {}
> - };
> + const struct of_device_id *clk_device;
>
> apcs = devm_kzalloc(&pdev->dev, sizeof(*apcs), GFP_KERNEL);
> if (!apcs)
> @@ -93,11 +99,12 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
> return ret;
> }
>
> - if (of_match_device(apcs_clk_match_table, &pdev->dev)) {
> + clk_device = of_match_device(apcs_clk_match_table, &pdev->dev);
Better use of_device_match_data() and get the string directly (or NULL).
> + if (clk_device) {
> apcs->clk = platform_device_register_data(&pdev->dev,
> - "qcom-apcs-msm8916-clk",
> - PLATFORM_DEVID_NONE,
> - NULL, 0);
> + (const char *)clk_device->data,
> + PLATFORM_DEVID_NONE,
> + NULL, 0);
I didn't apply the patch to look for myself, but please ensure to
maintain indentation to follow the parenthesis on the line before.
> if (IS_ERR(apcs->clk))
> dev_err(&pdev->dev, "failed to register APCS clk\n");
> }
> @@ -127,6 +134,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = {
> { .compatible = "qcom,sdm845-apss-shared", .data = (void *)12 },
> { .compatible = "qcom,sm8150-apss-shared", .data = (void *)12 },
> { .compatible = "qcom,ipq8074-apcs-apps-global", .data = (void *)8 },
> + { .compatible = "qcom,ipq6018-apcs-apps-global", .data = (void *)8 },
Add it one line up and you'll maintain partial sorting...
Regards,
Bjorn
> {}
> };
> MODULE_DEVICE_TABLE(of, qcom_apcs_ipc_of_match);
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH 01/17] dt-bindings: spi: Convert DW SPI binding to DT schema
From: Serge Semin @ 2020-05-12 20:28 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Serge Semin, Wan Ahmad Zainie, Mark Brown, Rob Herring,
Georgy Vlasov, Ramil Zaripov, Alexey Malahov, Thomas Bogendoerfer,
Paul Burton, Ralf Baechle, Arnd Bergmann, Allison Randal,
Gareth Williams, linux-mips, linux-spi, devicetree, linux-kernel
In-Reply-To: <20200508193934.GY185537@smile.fi.intel.com>
+Cc: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
On Fri, May 08, 2020 at 10:39:34PM +0300, Andy Shevchenko wrote:
> On Fri, May 08, 2020 at 04:29:26PM +0300, Serge Semin wrote:
> > Modern device tree bindings are supposed to be created as YAML-files
> > in accordance with dt-schema. This commit replaces two DW SPI legacy
> > bare text bindings with YAML file. As before the bindings file states
> > that the corresponding dts node is supposed to be compatible either
> > with generic DW APB SSI controller or with Microsemi/Amazon/Renesas
> > vendors-specific controllers, to have registers, interrupts and clocks
> > properties. Though in case of Microsemi version of the controller
> > there must be two registers resources specified. Properties like
> > clock-names, reg-io-width, cs-gpio, num-cs and SPI-specific sub-nodes
> > are optional.
>
> Can you incorporate work done here or agree with Wan how to proceed?
>
> https://lore.kernel.org/linux-spi/20200505191910.GA2970@bogus/T/#md626b5f6f2294b0ebd70995d5ed0e67a360e000b
Don't worry. I'll make sure the updates provided by Wan including the new IP
support are preserved after rebasing this series on top of the spi/for-next.
-Sergey
>
> >
> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> > Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > Cc: Paul Burton <paulburton@kernel.org>
> > Cc: Ralf Baechle <ralf@linux-mips.org>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: Allison Randal <allison@lohutok.net>
> > Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> > Cc: linux-mips@vger.kernel.org
> > ---
> > .../bindings/spi/snps,dw-apb-ssi.txt | 41 -------
> > .../bindings/spi/snps,dw-apb-ssi.yaml | 113 ++++++++++++++++++
> > .../devicetree/bindings/spi/spi-dw.txt | 24 ----
> > 3 files changed, 113 insertions(+), 65 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> > create mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> > delete mode 100644 Documentation/devicetree/bindings/spi/spi-dw.txt
> >
> > diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> > deleted file mode 100644
> > index 3ed08ee9feba..000000000000
> > --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> > +++ /dev/null
> > @@ -1,41 +0,0 @@
> > -Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
> > -
> > -Required properties:
> > -- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
> > - "jaguar2", or "amazon,alpine-dw-apb-ssi"
> > -- reg : The register base for the controller. For "mscc,<soc>-spi", a second
> > - register set is required (named ICPU_CFG:SPI_MST)
> > -- interrupts : One interrupt, used by the controller.
> > -- #address-cells : <1>, as required by generic SPI binding.
> > -- #size-cells : <0>, also as required by generic SPI binding.
> > -- clocks : phandles for the clocks, see the description of clock-names below.
> > - The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock
> > - is optional. If a single clock is specified but no clock-name, it is the
> > - "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first.
> > -
> > -Optional properties:
> > -- clock-names : Contains the names of the clocks:
> > - "ssi_clk", for the core clock used to generate the external SPI clock.
> > - "pclk", the interface clock, required for register access. If a clock domain
> > - used to enable this clock then it should be named "pclk_clkdomain".
> > -- cs-gpios : Specifies the gpio pins to be used for chipselects.
> > -- num-cs : The number of chipselects. If omitted, this will default to 4.
> > -- reg-io-width : The I/O register width (in bytes) implemented by this
> > - device. Supported values are 2 or 4 (the default).
> > -
> > -Child nodes as per the generic SPI binding.
> > -
> > -Example:
> > -
> > - spi@fff00000 {
> > - compatible = "snps,dw-apb-ssi";
> > - reg = <0xfff00000 0x1000>;
> > - interrupts = <0 154 4>;
> > - #address-cells = <1>;
> > - #size-cells = <0>;
> > - clocks = <&spi_m_clk>;
> > - num-cs = <2>;
> > - cs-gpios = <&gpio0 13 0>,
> > - <&gpio0 14 0>;
> > - };
> > -
> > diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> > new file mode 100644
> > index 000000000000..e2f6d8aa6181
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> > @@ -0,0 +1,113 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface
> > +
> > +maintainers:
> > + - Mark Brown <broonie@kernel.org>
> > +
> > +allOf:
> > + - $ref: "spi-controller.yaml#"
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - mscc,ocelot-spi
> > + - mscc,jaguar2-spi
> > + then:
> > + properties:
> > + reg:
> > + minItems: 2
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - description: Generic DW SPI controller
> > + const: snps,dw-apb-ssi
> > + - description: Microsemi Ocelot/Jaguar2 SoC SPI controller
> > + items:
> > + - enum:
> > + - mscc,ocelot-spi
> > + - mscc,jaguar2-spi
> > + - const: snps,dw-apb-ssi
> > + - description: Amazon Alpine SPI controller
> > + const: amazon,alpine-dw-apb-ssi
> > + - description: Renesas RZ/N1 SPI controlle.
> > + items:
> > + - const: renesas,rzn1-spi
> > + - const: snps,dw-apb-ssi
> > +
> > + reg:
> > + minItems: 1
> > + items:
> > + - description: DW APB SSI controller memory mapped registers
> > + - description: SPI MST region map
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + clocks:
> > + minItems: 1
> > + items:
> > + - description: SPI Controller reference clock source
> > + - description: APB interface clock source
> > +
> > + clock-names:
> > + minItems: 1
> > + items:
> > + - const: ssi_clk
> > + - const: pclk
> > +
> > + reg-io-width:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + description: I/O register width (in bytes) implemented by this device
> > + default: 4
> > + enum: [ 2, 4 ]
> > +
> > + num-cs:
> > + default: 4
> > + minimum: 1
> > + maximum: 4
> > +
> > +patternProperties:
> > + "^.*@[0-9a-f]+$":
> > + type: object
> > + properties:
> > + reg:
> > + minimum: 0
> > + maximum: 3
> > +
> > + spi-rx-bus-width:
> > + const: 1
> > +
> > + spi-tx-bus-width:
> > + const: 1
> > +
> > +unevaluatedProperties: false
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - "#address-cells"
> > + - "#size-cells"
> > + - interrupts
> > + - clocks
> > +
> > +examples:
> > + - |
> > + spi@fff00000 {
> > + compatible = "snps,dw-apb-ssi";
> > + reg = <0xfff00000 0x1000>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + interrupts = <0 154 4>;
> > + clocks = <&spi_m_clk>;
> > + num-cs = <2>;
> > + cs-gpios = <&gpio0 13 0>,
> > + <&gpio0 14 0>;
> > + };
> > +...
> > diff --git a/Documentation/devicetree/bindings/spi/spi-dw.txt b/Documentation/devicetree/bindings/spi/spi-dw.txt
> > deleted file mode 100644
> > index 7b63ed601990..000000000000
> > --- a/Documentation/devicetree/bindings/spi/spi-dw.txt
> > +++ /dev/null
> > @@ -1,24 +0,0 @@
> > -Synopsys DesignWare SPI master
> > -
> > -Required properties:
> > -- compatible: should be "snps,designware-spi"
> > -- #address-cells: see spi-bus.txt
> > -- #size-cells: see spi-bus.txt
> > -- reg: address and length of the spi master registers
> > -- interrupts: should contain one interrupt
> > -- clocks: spi clock phandle
> > -- num-cs: see spi-bus.txt
> > -
> > -Optional properties:
> > -- cs-gpios: see spi-bus.txt
> > -
> > -Example:
> > -
> > -spi: spi@4020a000 {
> > - compatible = "snps,designware-spi";
> > - interrupts = <11 1>;
> > - reg = <0x4020a000 0x1000>;
> > - clocks = <&pclk>;
> > - num-cs = <2>;
> > - cs-gpios = <&banka 0 0>;
> > -};
> > --
> > 2.25.1
> >
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
^ permalink raw reply
* Re: [PATCH 00/17] spi: dw: Add generic DW DMA controller support
From: Serge Semin @ 2020-05-12 20:30 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Maxim Kaurkin, Pavel Parkhomenko, Ekaterina Skachko, Vadim Vlasov,
Alexey Kolotnikov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Andy Shevchenko, Gareth Williams,
Rob Herring, linux-mips, linux-spi, devicetree, linux-kernel
In-Reply-To: <20200508173609.GQ4820@sirena.org.uk>
On Fri, May 08, 2020 at 06:36:09PM +0100, Mark Brown wrote:
> On Fri, May 08, 2020 at 04:29:25PM +0300, Serge Semin wrote:
> > Baikal-T1 SoC provides DW DMA controller to perform low-speed peripherals
> > Mem-to-Dev and Dev-to-Mem transaction. This is also applicable to the DW
> > APB SSI devices embedded into the SoC. Currently this type DMA device is
>
> This basically all looks good to me (without any hardware specific
> knowledge), I had a few comments but they were mostly procedural ones -
> mainly getting these bug fixes you've done merged as such. Nice work.
Thanks. I'll address the Andy's comments and send v2 after that.
-Sergey
^ permalink raw reply
* Re: [PATCH 00/17] spi: dw: Add generic DW DMA controller support
From: Serge Semin @ 2020-05-12 20:34 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Serge Semin, Mark Brown, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Maxim Kaurkin, Pavel Parkhomenko,
Ekaterina Skachko, Vadim Vlasov, Alexey Kolotnikov,
Thomas Bogendoerfer, Paul Burton, Ralf Baechle, Arnd Bergmann,
Allison Randal, Gareth Williams, Rob Herring, linux-mips,
linux-spi, devicetree, linux-kernel
In-Reply-To: <20200508191617.GR185537@smile.fi.intel.com>
On Fri, May 08, 2020 at 10:16:17PM +0300, Andy Shevchenko wrote:
> On Fri, May 08, 2020 at 06:36:09PM +0100, Mark Brown wrote:
> > On Fri, May 08, 2020 at 04:29:25PM +0300, Serge Semin wrote:
> > > Baikal-T1 SoC provides DW DMA controller to perform low-speed peripherals
> > > Mem-to-Dev and Dev-to-Mem transaction. This is also applicable to the DW
> > > APB SSI devices embedded into the SoC. Currently this type DMA device is
> >
> > This basically all looks good to me (without any hardware specific
> > knowledge), I had a few comments but they were mostly procedural ones -
> > mainly getting these bug fixes you've done merged as such. Nice work.
>
> Agree that is nice work!
> Though, can you please give us chance to review next version of the series and test on our hardware?
>
> Serge, I think you should base it on spi/for-next rather than vanilla.
Yeah, seeing there are potentially merge-conflict changes in the for-next
branch I have to do the rebase. Will be done in v2.
-Sergey
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
^ permalink raw reply
* Re: [PATCH 01/17] dt-bindings: spi: Convert DW SPI binding to DT schema
From: Andy Shevchenko @ 2020-05-12 20:35 UTC (permalink / raw)
To: Serge Semin
Cc: Andy Shevchenko, Serge Semin, Wan Ahmad Zainie, Mark Brown,
Rob Herring, Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Thomas Bogendoerfer, Paul Burton, Ralf Baechle, Arnd Bergmann,
Allison Randal, Gareth Williams, linux-mips, linux-spi,
devicetree, Linux Kernel Mailing List
In-Reply-To: <20200512202814.e6havutfpzu2gdfc@mobilestation>
On Tue, May 12, 2020 at 11:29 PM Serge Semin
<Sergey.Semin@baikalelectronics.ru> wrote:
>
> +Cc: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
>
> On Fri, May 08, 2020 at 10:39:34PM +0300, Andy Shevchenko wrote:
> > On Fri, May 08, 2020 at 04:29:26PM +0300, Serge Semin wrote:
> > > Modern device tree bindings are supposed to be created as YAML-files
> > > in accordance with dt-schema. This commit replaces two DW SPI legacy
> > > bare text bindings with YAML file. As before the bindings file states
> > > that the corresponding dts node is supposed to be compatible either
> > > with generic DW APB SSI controller or with Microsemi/Amazon/Renesas
> > > vendors-specific controllers, to have registers, interrupts and clocks
> > > properties. Though in case of Microsemi version of the controller
> > > there must be two registers resources specified. Properties like
> > > clock-names, reg-io-width, cs-gpio, num-cs and SPI-specific sub-nodes
> > > are optional.
> >
> > Can you incorporate work done here or agree with Wan how to proceed?
> >
> > https://lore.kernel.org/linux-spi/20200505191910.GA2970@bogus/T/#md626b5f6f2294b0ebd70995d5ed0e67a360e000b
>
> Don't worry. I'll make sure the updates provided by Wan including the new IP
> support are preserved after rebasing this series on top of the spi/for-next.
Thanks!
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* [PATCH 1/3] arm64: dts: rockchip: replace RK_FUNC defines in rk3326-odroid-go2.dts
From: Johan Jonker @ 2020-05-12 20:35 UTC (permalink / raw)
To: heiko
Cc: linus.walleij, robh+dt, linux-gpio, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel
The defines RK_FUNC_1 and RK_FUNC_2 are deprecated,
so replace them with the preferred form.
Restyle properties in the same line.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
index fe253669b..46826b6e2 100644
--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
@@ -543,18 +543,15 @@
};
soc_slppin_gpio: soc_slppin_gpio {
- rockchip,pins =
- <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
+ rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
};
soc_slppin_rst: soc_slppin_rst {
- rockchip,pins =
- <0 RK_PA4 RK_FUNC_2 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA4 2 &pcfg_pull_none>;
};
soc_slppin_slp: soc_slppin_slp {
- rockchip,pins =
- <0 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
};
};
};
--
2.11.0
^ permalink raw reply related
* [PATCH 2/3] dt-bindings: pinctrl: rockchip: update example
From: Johan Jonker @ 2020-05-12 20:35 UTC (permalink / raw)
To: heiko
Cc: linus.walleij, robh+dt, linux-gpio, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel
In-Reply-To: <20200512203524.7317-1-jbx6244@gmail.com>
The Rockchip dtsi and dts files have been bulk-converted for the
remaining raw gpio numbers into their descriptive counterparts and
also got rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x
mappings, so update the example as well.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
index 2113cfaa2..d3eae61a3 100644
--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.txt
@@ -110,8 +110,8 @@ pinctrl@20008000 {
uart2 {
uart2_xfer: uart2-xfer {
- rockchip,pins = <RK_GPIO1 8 1 &pcfg_pull_default>,
- <RK_GPIO1 9 1 &pcfg_pull_default>;
+ rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
+ <1 RK_PB1 1 &pcfg_pull_default>;
};
};
};
--
2.11.0
^ permalink raw reply related
* [PATCH 3/3] include: dt-bindings: rockchip: remove unused defines
From: Johan Jonker @ 2020-05-12 20:35 UTC (permalink / raw)
To: heiko
Cc: linus.walleij, robh+dt, linux-gpio, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel
In-Reply-To: <20200512203524.7317-1-jbx6244@gmail.com>
The Rockchip dtsi and dts files have been bulk-converted for the
remaining raw gpio numbers into their descriptive counterparts and
also got rid of the unhelpful RK_FUNC_x -> x and RK_GPIOx -> x
mappings, so remove the unused defines in 'rockchip.h' to prevent
that someone start using them again.
Signed-off-by: Johan Jonker <jbx6244@gmail.com>
---
include/dt-bindings/pinctrl/rockchip.h | 11 -----------
1 file changed, 11 deletions(-)
diff --git a/include/dt-bindings/pinctrl/rockchip.h b/include/dt-bindings/pinctrl/rockchip.h
index 6d6bac1c2..5f291045e 100644
--- a/include/dt-bindings/pinctrl/rockchip.h
+++ b/include/dt-bindings/pinctrl/rockchip.h
@@ -9,13 +9,6 @@
#ifndef __DT_BINDINGS_ROCKCHIP_PINCTRL_H__
#define __DT_BINDINGS_ROCKCHIP_PINCTRL_H__
-#define RK_GPIO0 0
-#define RK_GPIO1 1
-#define RK_GPIO2 2
-#define RK_GPIO3 3
-#define RK_GPIO4 4
-#define RK_GPIO6 6
-
#define RK_PA0 0
#define RK_PA1 1
#define RK_PA2 2
@@ -50,9 +43,5 @@
#define RK_PD7 31
#define RK_FUNC_GPIO 0
-#define RK_FUNC_1 1 /* deprecated */
-#define RK_FUNC_2 2 /* deprecated */
-#define RK_FUNC_3 3 /* deprecated */
-#define RK_FUNC_4 4 /* deprecated */
#endif
--
2.11.0
^ permalink raw reply related
* [PATCH v2] arm: dts: Move am33xx and am43xx mmc nodes to sdhci-omap driver
From: Faiz Abbas @ 2020-05-12 20:38 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-omap; +Cc: robh+dt, tony, bcousson, faiz_abbas
Move mmc nodes to be compatible with the sdhci-omap driver. The following
modifications are required for omap_hsmmc specific properties:
ti,non-removable: convert to the generic mmc non-removable
ti,needs-special-reset: co-opted into the sdhci-omap driver
ti,dual-volt: removed. Legacy property not used in am335x or am43xx
ti,needs-special-hs-handling: removed. Legacy property not used in am335x
or am43xx
Also since the sdhci-omap driver does not support runtime PM, explicitly
disable the mmc3 instance in the dtsi.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
---
v2: Rebased to latest mainline where all kernel dependancies have been merged.
Suspend/Resume is now supported in the sdhci-omap driver.
Tested on: am335x-evm, am335x-boneblack, am335x-sk, am335x-bone, am437x-idk,
am43xx-gp-evm, am43xx-epos-evm.
arch/arm/boot/dts/am335x-baltos.dtsi | 2 +-
arch/arm/boot/dts/am335x-boneblack-common.dtsi | 1 +
arch/arm/boot/dts/am335x-boneblack-wireless.dts | 1 -
arch/arm/boot/dts/am335x-boneblue.dts | 1 -
arch/arm/boot/dts/am335x-bonegreen-wireless.dts | 1 -
arch/arm/boot/dts/am335x-evm.dts | 3 +--
arch/arm/boot/dts/am335x-evmsk.dts | 2 +-
arch/arm/boot/dts/am335x-lxm.dts | 2 +-
arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi | 2 +-
arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts | 2 +-
arch/arm/boot/dts/am335x-pepper.dts | 4 ++--
arch/arm/boot/dts/am335x-phycore-som.dtsi | 2 +-
arch/arm/boot/dts/am33xx-l4.dtsi | 6 ++----
arch/arm/boot/dts/am33xx.dtsi | 3 ++-
arch/arm/boot/dts/am4372.dtsi | 3 ++-
arch/arm/boot/dts/am437x-cm-t43.dts | 2 +-
arch/arm/boot/dts/am437x-gp-evm.dts | 4 ++--
arch/arm/boot/dts/am437x-l4.dtsi | 5 ++---
arch/arm/boot/dts/am437x-sk-evm.dts | 2 +-
19 files changed, 22 insertions(+), 26 deletions(-)
diff --git a/arch/arm/boot/dts/am335x-baltos.dtsi b/arch/arm/boot/dts/am335x-baltos.dtsi
index 05e7b5d4a95b..04f0b1227efe 100644
--- a/arch/arm/boot/dts/am335x-baltos.dtsi
+++ b/arch/arm/boot/dts/am335x-baltos.dtsi
@@ -369,7 +369,7 @@
&mmc2 {
status = "okay";
vmmc-supply = <&wl12xx_vmmc>;
- ti,non-removable;
+ non-removable;
bus-width = <4>;
cap-power-off-card;
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/am335x-boneblack-common.dtsi b/arch/arm/boot/dts/am335x-boneblack-common.dtsi
index 91f93bc89716..dd932220a8bf 100644
--- a/arch/arm/boot/dts/am335x-boneblack-common.dtsi
+++ b/arch/arm/boot/dts/am335x-boneblack-common.dtsi
@@ -22,6 +22,7 @@
pinctrl-0 = <&emmc_pins>;
bus-width = <8>;
status = "okay";
+ non-removable;
};
&am33xx_pinmux {
diff --git a/arch/arm/boot/dts/am335x-boneblack-wireless.dts b/arch/arm/boot/dts/am335x-boneblack-wireless.dts
index 3124d94c0b3c..e07dd7979586 100644
--- a/arch/arm/boot/dts/am335x-boneblack-wireless.dts
+++ b/arch/arm/boot/dts/am335x-boneblack-wireless.dts
@@ -75,7 +75,6 @@
bus-width = <4>;
non-removable;
cap-power-off-card;
- ti,needs-special-hs-handling;
keep-power-in-suspend;
pinctrl-names = "default";
pinctrl-0 = <&mmc3_pins &wl18xx_pins>;
diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts
index 5811fb8d4fdf..83f9452c9cd3 100644
--- a/arch/arm/boot/dts/am335x-boneblue.dts
+++ b/arch/arm/boot/dts/am335x-boneblue.dts
@@ -367,7 +367,6 @@
bus-width = <4>;
non-removable;
cap-power-off-card;
- ti,needs-special-hs-handling;
keep-power-in-suspend;
pinctrl-names = "default";
pinctrl-0 = <&mmc3_pins &wl18xx_pins>;
diff --git a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts
index 4092cd193b8a..609c8db687ec 100644
--- a/arch/arm/boot/dts/am335x-bonegreen-wireless.dts
+++ b/arch/arm/boot/dts/am335x-bonegreen-wireless.dts
@@ -75,7 +75,6 @@
bus-width = <4>;
non-removable;
cap-power-off-card;
- ti,needs-special-hs-handling;
keep-power-in-suspend;
pinctrl-names = "default";
pinctrl-0 = <&mmc3_pins &wl18xx_pins>;
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 68252dab32c3..a4fc6b168a85 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -743,8 +743,7 @@
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&mmc3_pins &wlan_pins>;
- ti,non-removable;
- ti,needs-special-hs-handling;
+ non-removable;
cap-power-off-card;
keep-power-in-suspend;
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index 32f515a295ee..78b6e1f594c9 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -655,7 +655,7 @@
&mmc2 {
status = "okay";
vmmc-supply = <&wl12xx_vmmc>;
- ti,non-removable;
+ non-removable;
bus-width = <4>;
cap-power-off-card;
keep-power-in-suspend;
diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts
index fef582852820..dbedf729205c 100644
--- a/arch/arm/boot/dts/am335x-lxm.dts
+++ b/arch/arm/boot/dts/am335x-lxm.dts
@@ -339,7 +339,7 @@
pinctrl-0 = <&emmc_pins>;
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <8>;
- ti,non-removable;
+ non-removable;
status = "okay";
};
diff --git a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi
index 6495a125c01f..4e90f9c23d2e 100644
--- a/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi
+++ b/arch/arm/boot/dts/am335x-moxa-uc-2100-common.dtsi
@@ -159,7 +159,7 @@
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <8>;
pinctrl-0 = <&mmc1_pins_default>;
- ti,non-removable;
+ non-removable;
status = "okay";
};
diff --git a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts
index 244df9c5a537..f03e72cada41 100644
--- a/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts
+++ b/arch/arm/boot/dts/am335x-moxa-uc-8100-me-t.dts
@@ -451,7 +451,7 @@
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <8>;
pinctrl-0 = <&mmc2_pins_default>;
- ti,non-removable;
+ non-removable;
status = "okay";
};
diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts
index 6d7608d9377b..f9a027b47962 100644
--- a/arch/arm/boot/dts/am335x-pepper.dts
+++ b/arch/arm/boot/dts/am335x-pepper.dts
@@ -341,7 +341,7 @@
pinctrl-0 = <&emmc_pins>;
vmmc-supply = <&ldo3_reg>;
bus-width = <8>;
- ti,non-removable;
+ non-removable;
};
&mmc3 {
@@ -351,7 +351,7 @@
pinctrl-0 = <&wireless_pins>;
vmmmc-supply = <&v3v3c_reg>;
bus-width = <4>;
- ti,non-removable;
+ non-removable;
dmas = <&edma_xbar 12 0 1
&edma_xbar 13 0 2>;
dma-names = "tx", "rx";
diff --git a/arch/arm/boot/dts/am335x-phycore-som.dtsi b/arch/arm/boot/dts/am335x-phycore-som.dtsi
index 3d0672b53d77..7e46b4c02709 100644
--- a/arch/arm/boot/dts/am335x-phycore-som.dtsi
+++ b/arch/arm/boot/dts/am335x-phycore-som.dtsi
@@ -69,7 +69,7 @@
pinctrl-0 = <&emmc_pins>;
vmmc-supply = <&vmmc_reg>;
bus-width = <8>;
- ti,non-removable;
+ non-removable;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/am33xx-l4.dtsi b/arch/arm/boot/dts/am33xx-l4.dtsi
index 5ed7f3c58c0f..573ff076178b 100644
--- a/arch/arm/boot/dts/am33xx-l4.dtsi
+++ b/arch/arm/boot/dts/am33xx-l4.dtsi
@@ -1337,10 +1337,8 @@
ranges = <0x0 0x60000 0x1000>;
mmc1: mmc@0 {
- compatible = "ti,omap4-hsmmc";
- ti,dual-volt;
+ compatible = "ti,am335-sdhci";
ti,needs-special-reset;
- ti,needs-special-hs-handling;
dmas = <&edma_xbar 24 0 0
&edma_xbar 25 0 0>;
dma-names = "tx", "rx";
@@ -1818,7 +1816,7 @@
ranges = <0x0 0xd8000 0x1000>;
mmc2: mmc@0 {
- compatible = "ti,omap4-hsmmc";
+ compatible = "ti,am335-sdhci";
ti,needs-special-reset;
dmas = <&edma 2 0
&edma 3 0>;
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index a35f5052d76f..3b9d4d2d35bf 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -322,10 +322,11 @@
ranges = <0x0 0x47810000 0x1000>;
mmc3: mmc@0 {
- compatible = "ti,omap4-hsmmc";
+ compatible = "ti,am335-sdhci";
ti,needs-special-reset;
interrupts = <29>;
reg = <0x0 0x1000>;
+ status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index dba87bfaf33e..092b3d4404f4 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -316,10 +316,11 @@
ranges = <0x0 0x47810000 0x1000>;
mmc3: mmc@0 {
- compatible = "ti,omap4-hsmmc";
+ compatible = "ti,am437-sdhci";
ti,needs-special-reset;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x1000>;
+ status = "disabled";
};
};
diff --git a/arch/arm/boot/dts/am437x-cm-t43.dts b/arch/arm/boot/dts/am437x-cm-t43.dts
index 063113a5da2d..a6b4fca8626a 100644
--- a/arch/arm/boot/dts/am437x-cm-t43.dts
+++ b/arch/arm/boot/dts/am437x-cm-t43.dts
@@ -291,7 +291,7 @@
pinctrl-0 = <&emmc_pins>;
vmmc-supply = <&vmmc_3v3>;
bus-width = <8>;
- ti,non-removable;
+ non-removable;
};
&spi0 {
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index 811c8cae315b..cadf47ee337f 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -869,7 +869,7 @@
pinctrl-names = "default", "sleep";
pinctrl-0 = <&emmc_pins_default>;
pinctrl-1 = <&emmc_pins_sleep>;
- ti,non-removable;
+ non-removable;
};
&mmc3 {
@@ -886,7 +886,7 @@
pinctrl-1 = <&mmc3_pins_sleep>;
cap-power-off-card;
keep-power-in-suspend;
- ti,non-removable;
+ non-removable;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/am437x-l4.dtsi b/arch/arm/boot/dts/am437x-l4.dtsi
index 49c6a872052e..f4eb36d8b660 100644
--- a/arch/arm/boot/dts/am437x-l4.dtsi
+++ b/arch/arm/boot/dts/am437x-l4.dtsi
@@ -1086,9 +1086,8 @@
ranges = <0x0 0x60000 0x1000>;
mmc1: mmc@0 {
- compatible = "ti,omap4-hsmmc";
+ compatible = "ti,am437-sdhci";
reg = <0x0 0x1000>;
- ti,dual-volt;
ti,needs-special-reset;
dmas = <&edma 24 0>,
<&edma 25 0>;
@@ -1601,7 +1600,7 @@
ranges = <0x0 0xd8000 0x1000>;
mmc2: mmc@0 {
- compatible = "ti,omap4-hsmmc";
+ compatible = "ti,am437-sdhci";
reg = <0x0 0x1000>;
ti,needs-special-reset;
dmas = <&edma 2 0>,
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts
index 25222497f828..2416597a4f5c 100644
--- a/arch/arm/boot/dts/am437x-sk-evm.dts
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -719,7 +719,7 @@
pinctrl-1 = <&mmc3_pins_sleep>;
cap-power-off-card;
keep-power-in-suspend;
- ti,non-removable;
+ non-removable;
#address-cells = <1>;
#size-cells = <0>;
--
2.17.1
^ permalink raw reply related
* [PATCH 0/6] Add initial genpd support for omap PRM driver
From: Tony Lindgren @ 2020-05-12 20:38 UTC (permalink / raw)
To: linux-omap
Cc: Andrew F . Davis, Santosh Shilimkar, Suman Anna, Tero Kristo,
linux-kernel, linux-arm-kernel, Rob Herring, devicetree
Hi all,
Here are some changes to add genpd support to the PRM (Power and Reset
Module) driver.
Initially we just add one hardware accelerator power domain for sgx,
and one interconnect instance for l4_abe. The rest of the SoC specific
domain data is probably best added one SoC at a time based on generated
data.
Regards,
Tony
Tony Lindgren (6):
dt-bindings: omap: Update PRM binding for genpd
soc: ti: omap-prm: Add basic power domain support
soc: ti: omap-prm: Configure sgx power domain for am3 and am4
soc: ti: omap-prm: Configure omap4 and 5 l4_abe power domain
ARM: dts: Configure am3 and am4 sgx for genpd and drop platform data
ARM: dts: Configure omap4 and 5 l4_abe for genpd and drop platform
data
.../devicetree/bindings/arm/omap/prm-inst.txt | 4 +
arch/arm/boot/dts/am33xx.dtsi | 2 +
arch/arm/boot/dts/am4372.dtsi | 2 +
arch/arm/boot/dts/omap4-l4-abe.dtsi | 7 +-
arch/arm/boot/dts/omap4.dtsi | 6 +
arch/arm/boot/dts/omap5-l4-abe.dtsi | 7 +-
arch/arm/boot/dts/omap5.dtsi | 6 +
arch/arm/mach-omap2/Kconfig | 1 +
.../omap_hwmod_33xx_43xx_interconnect_data.c | 16 -
.../omap_hwmod_33xx_43xx_ipblock_data.c | 40 ---
arch/arm/mach-omap2/omap_hwmod_33xx_data.c | 2 -
arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 2 -
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 33 --
arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 31 --
drivers/soc/ti/omap_prm.c | 301 +++++++++++++++++-
15 files changed, 329 insertions(+), 131 deletions(-)
--
2.26.2
^ permalink raw reply
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