* Re: [PATCH 1/6] dt-bindings: phy: meson8b-usb2: Convert to json-schema
From: Rob Herring @ 2020-05-12 22:03 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: kishon, vkoul, devicetree, linux-amlogic, narmstrong,
linux-arm-kernel, linux-kernel, hexdump0815
In-Reply-To: <20200502114752.1048500-2-martin.blumenstingl@googlemail.com>
On Sat, May 02, 2020 at 01:47:47PM +0200, Martin Blumenstingl wrote:
> Now that we have the DT validation in place, let's convert the device
> tree bindings for the Amlogic Meson8, Meson8b, Meson8m2 and GXBB USB2
> PHY over to a YAML schema.
>
> While here, also add the fallback compatible string
> "amlogic,meson-gxbb-usb2-phy" which is already used in
> arch/arm/boot/dts/meson{,8,8b}.dtsi.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> .../phy/amlogic,meson8b-usb2-phy.yaml | 61 +++++++++++++++++++
> .../bindings/phy/meson8b-usb2-phy.txt | 28 ---------
> 2 files changed, 61 insertions(+), 28 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml
> delete mode 100644 Documentation/devicetree/bindings/phy/meson8b-usb2-phy.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml
> new file mode 100644
> index 000000000000..c2fe8c08d99e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml
> @@ -0,0 +1,61 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/phy/amlogic,meson8b-usb2-phy.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Amlogic Meson8, Meson8b, Meson8m2 and GXBB USB2 PHY
> +
> +maintainers:
> + - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - amlogic,meson8-usb2-phy
> + - amlogic,meson8b-usb2-phy
Needs 2 more spaces indent.
> + - const: amlogic,meson-mx-usb2-phy
> + - const: amlogic,meson-gxbb-usb2-phy
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 2
> +
> + clock-names:
> + items:
> + - const: usb_general
> + - const: usb
> +
> + resets:
> + minItems: 1
> +
> + "#phy-cells":
> + const: 0
> +
> + phy-supply:
> + description:
Wrong indentation.
> + Phandle to a regulator that provides power to the PHY. This
> + regulator will be managed during the PHY power on/off sequence.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - "#phy-cells"
Add:
additionalProperties: false
> +
> +examples:
> + - |
> + usb-phy@c0000000 {
> + compatible = "amlogic,meson-gxbb-usb2-phy";
> + reg = <0xc0000000 0x20>;
> + resets = <&reset_usb_phy>;
> + clocks = <&clk_usb_general>, <&reset_usb>;
> + clock-names = "usb_general", "usb";
> + phy-supply = <&usb_vbus>;
> + #phy-cells = <0>;
> + };
^ permalink raw reply
* Re: [PATCH 2/6] dt-bindings: phy: meson8b-usb2: Add compatible string for Meson8m2
From: Rob Herring @ 2020-05-12 22:03 UTC (permalink / raw)
To: Martin Blumenstingl
Cc: linux-kernel, linux-amlogic, vkoul, narmstrong, kishon,
hexdump0815, devicetree, robh+dt, linux-arm-kernel
In-Reply-To: <20200502114752.1048500-3-martin.blumenstingl@googlemail.com>
On Sat, 2 May 2020 13:47:48 +0200, Martin Blumenstingl wrote:
> The USB2 PHY on Meson8m2 is identical to the one on Meson8b but
> different to the one on Meson8. The only known difference is that Meson8
> does not set the ACA_ENABLE bit while Meson8b and Meson8m2 do.
> Add an explicit compatible string for Meson8m2 so those differences can
> be taken care of.
>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> .../devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH V2 2/3] clk: vc5: Enable addition output configurations of the Versaclock
From: Rob Herring @ 2020-05-12 22:05 UTC (permalink / raw)
To: Adam Ford
Cc: linux-clk, aford, charles.stevens, Michael Turquette,
Stephen Boyd, Marek Vasut, devicetree, linux-kernel
In-Reply-To: <20200502122126.188001-2-aford173@gmail.com>
On Sat, May 02, 2020 at 07:21:25AM -0500, Adam Ford wrote:
> The existing driver is expecting the Versaclock to be pre-programmed,
> and only sets the output frequency. Unfortunately, not all devices
> are pre-programmed, and the Versaclock chip has more options beyond
> just the frequency.
>
> This patch enables the following additional features:
>
> - Programmable voltage: 1.8V, 2.5V, or 3.3V
> - Slew Percentage of normal: 85%, 90%, or 100%
> - Output Type: LVPECL, CMOS, HCSL, or LVDS
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
> diff --git a/include/dt-bindings/clk/versaclock.h b/include/dt-bindings/clk/versaclock.h
> new file mode 100644
> index 000000000000..c6a6a0946564
> --- /dev/null
> +++ b/include/dt-bindings/clk/versaclock.h
Belongs in binding patch.
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +
> +/* This file defines field values used by the versaclock 6 family
> + * for defining output type
> + */
> +
> +#define VC5_LVPECL 0
> +#define VC5_CMOS 1
> +#define VC5_HCSL33 2
> +#define VC5_LVDS 3
> +#define VC5_CMOS2 4
> +#define VC5_CMOSD 5
> +#define VC5_HCSL25 6
> --
> 2.25.1
>
^ permalink raw reply
* Re: [PATCH] dt-bindings: vendor-prefixes: Add Vaisala
From: Rob Herring @ 2020-05-12 22:07 UTC (permalink / raw)
To: Vesa Jääskeläinen; +Cc: devicetree, Rob Herring
In-Reply-To: <20200503093355.46964-1-vesa.jaaskelainen@vaisala.com>
On Sun, 3 May 2020 12:33:55 +0300, Vesa Jääskeläinen wrote:
> Vaisala Oyj is a company based in Finland and also has subsidiaries in other
> countries. Vaisala develops, manufactures and markets innovative products and
> services for environmental and industrial measurement.
>
> https://www.vaisala.com/
>
> Signed-off-by: Vesa Jääskeläinen <vesa.jaaskelainen@vaisala.com>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH v2 1/3] dt-bindings: mailbox: Add devicetree binding for Qcom IPCC
From: Bjorn Andersson @ 2020-05-12 22:07 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: jassisinghbrar, robh+dt, linux-arm-msm, linux-kernel, devicetree
In-Reply-To: <20200508182703.29021-2-manivannan.sadhasivam@linaro.org>
On Fri 08 May 11:27 PDT 2020, Manivannan Sadhasivam wrote:
> Add devicetree YAML binding for Qualcomm Inter-Processor Communication
> Controller (IPCC) block.
>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> .../bindings/mailbox/qcom-ipcc.yaml | 77 +++++++++++++++++++
> include/dt-bindings/mailbox/qcom-ipcc.h | 33 ++++++++
> 2 files changed, 110 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
> create mode 100644 include/dt-bindings/mailbox/qcom-ipcc.h
>
> diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
> new file mode 100644
> index 000000000000..62e7bc8ceb0b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
> @@ -0,0 +1,77 @@
> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller
> +
> +maintainers:
> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> +
> +description:
> + The Inter-Processor Communication Controller (IPCC) is a centralized hardware
> + to route interrupts across various subsystems. It involves a three-level
> + addressing scheme called protocol, client and signal. For example, consider an
> + entity on the Application Processor Subsystem (APSS) that wants to listen to
> + Modem's interrupts via Shared Memory Point to Point (SMP2P) interface. In such
> + a case, the client would be Modem (client-id is 2) and the signal would be
> + SMP2P (signal-id is 2). The SMP2P itself falls under the Multiprocessor (MPROC)
> + protocol (protocol-id is 0). Refer include/dt-bindings/mailbox/qcom-ipcc.h
> + for the list of such IDs.
> +
> +properties:
> + compatible:
> + const: "qcom,ipcc"
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + interrupt-controller: true
> +
> + "#interrupt-cells":
> + const: 3
> + description:
> + The first cell is the client-id, the second cell is the signal-id and the
> + third cell is the interrupt type.
> +
> + "#mbox-cells":
> + const: 2
> + description:
> + The first cell is the client-id, and the second cell is the signal-id.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-controller
> + - "#interrupt-cells"
> + - "#mbox-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/mailbox/qcom-ipcc.h>
> +
> + mailbox: qcom,ipcc@408000 {
> + compatible = "qcom,ipcc";
> + reg = <0x408000 0x1000>;
> + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + #mbox-cells = <2>;
> + };
> +
> + smp2p-modem {
> + compatible = "qcom,smp2p";
> + interrupts-extended = <&ipcc_mproc IPCC_CLIENT_MPSS
> + IPCC_MPROC_SIGNAL_SMP2P IRQ_TYPE_EDGE_RISING>;
> + mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
> +
> + /* Other SMP2P fields */
> + };
> diff --git a/include/dt-bindings/mailbox/qcom-ipcc.h b/include/dt-bindings/mailbox/qcom-ipcc.h
> new file mode 100644
> index 000000000000..b8c04f6df57c
> --- /dev/null
> +++ b/include/dt-bindings/mailbox/qcom-ipcc.h
> @@ -0,0 +1,33 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
> + */
> +
> +#ifndef __DT_BINDINGS_MAILBOX_IPCC_H
> +#define __DT_BINDINGS_MAILBOX_IPCC_H
> +
> +/* Signal IDs for MPROC protocol */
> +#define IPCC_MPROC_SIGNAL_GLINK_QMP 0
> +#define IPCC_MPROC_SIGNAL_SMP2P 2
> +#define IPCC_MPROC_SIGNAL_PING 3
> +
> +/* Client IDs */
> +#define IPCC_CLIENT_AOP 0
> +#define IPCC_CLIENT_TZ 1
> +#define IPCC_CLIENT_MPSS 2
> +#define IPCC_CLIENT_LPASS 3
> +#define IPCC_CLIENT_SLPI 4
> +#define IPCC_CLIENT_SDC 5
> +#define IPCC_CLIENT_CDSP 6
> +#define IPCC_CLIENT_NPU 7
> +#define IPCC_CLIENT_APSS 8
> +#define IPCC_CLIENT_GPU 9
> +#define IPCC_CLIENT_CVP 10
> +#define IPCC_CLIENT_CAM 11
> +#define IPCC_CLIENT_VPU 12
> +#define IPCC_CLIENT_PCIE0 13
> +#define IPCC_CLIENT_PCIE1 14
> +#define IPCC_CLIENT_PCIE2 15
> +#define IPCC_CLIENT_SPSS 16
> +
> +#endif
> --
> 2.17.1
>
^ permalink raw reply
* Re: [PATCH v2] dt-bindings: net: renesas,ether: Sort compatible string in increasing number of the SoC
From: Rob Herring @ 2020-05-12 22:10 UTC (permalink / raw)
To: Lad Prabhakar
Cc: devicetree, linux-renesas-soc, linux-kernel, Rob Herring,
David S. Miller, Sergei Shtylyov, netdev, Geert Uytterhoeven,
Simon Horman, Lad Prabhakar
In-Reply-To: <1588519279-13364-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Sun, 3 May 2020 16:21:19 +0100, Lad Prabhakar wrote:
> Sort the items in the compatible string list in increasing number of SoC.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> Changes for v2:
> * Included renesas,ether in subject instead of sh_eth.
> * Included Reviewed-by tags.
>
> Documentation/devicetree/bindings/net/renesas,ether.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
I already applied v1.
Rob
^ permalink raw reply
* Re: [PATCH v2 1/6] dt-bindings: Add vendor prefix for Shiratech Solutions
From: Rob Herring @ 2020-05-12 22:10 UTC (permalink / raw)
To: mani
Cc: mcoquelin.stm32, robh+dt, alexandre.torgue, linux-kernel,
devicetree, linux-arm-kernel, linux-stm32
In-Reply-To: <20200503154215.23654-2-mani@kernel.org>
On Sun, 3 May 2020 21:12:10 +0530, wrote:
> From: Manivannan Sadhasivam <mani@kernel.org>
>
> This commit adds devicetree vendor prefix for Shiratech solutions,
> a SOM/embedded board manufacturing company.
>
> https://www.shiratech-solutions.com/
>
> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
> ---
> Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 3/6] dt-bindings: arm: stm32: Document Stinger96 compatible
From: Rob Herring @ 2020-05-12 22:11 UTC (permalink / raw)
To: mani
Cc: linux-stm32, robh+dt, devicetree, mcoquelin.stm32, linux-kernel,
alexandre.torgue, linux-arm-kernel
In-Reply-To: <20200503154215.23654-4-mani@kernel.org>
On Sun, 3 May 2020 21:12:12 +0530, wrote:
> From: Manivannan Sadhasivam <mani@kernel.org>
>
> Document devicetree compatible of Shiratech Stinger96 board.
>
> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
> ---
> Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 5/6] dt-bindings: arm: stm32: Document IoT Box compatible
From: Rob Herring @ 2020-05-12 22:11 UTC (permalink / raw)
To: mani
Cc: devicetree, robh+dt, linux-stm32, linux-arm-kernel, linux-kernel,
alexandre.torgue, mcoquelin.stm32
In-Reply-To: <20200503154215.23654-6-mani@kernel.org>
On Sun, 3 May 2020 21:12:14 +0530, wrote:
> From: Manivannan Sadhasivam <mani@kernel.org>
>
> Document devicetree compatible of Shiratech IoT Box.
>
> Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
> ---
> Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 2/3] mailbox: Add support for Qualcomm IPCC
From: Bjorn Andersson @ 2020-05-12 22:12 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: jassisinghbrar, robh+dt, linux-arm-msm, linux-kernel, devicetree,
Raghavendra Rao Ananta, Venkata Narendra Kumar Gutta
In-Reply-To: <20200508182703.29021-3-manivannan.sadhasivam@linaro.org>
On Fri 08 May 11:27 PDT 2020, Manivannan Sadhasivam wrote:
> Add support for the Inter-Processor Communication Controller (IPCC)
> block from Qualcomm that coordinates the interrupts (inbound & outbound)
> for Multiprocessor (MPROC), COMPUTE-Level0 (COMPUTE-L0) & COMPUTE-Level1
> (COMPUTE-L1) protocols for the Application Processor Subsystem (APSS).
>
> This driver is modeled as an irqchip+mailbox driver. The irqchip part
> helps in receiving the interrupts from the IPCC clients such as modems,
> DSPs, PCI-E etc... and forwards them to respective entities in APSS.
>
> On the other hand, the mailbox part is used to send interrupts to the IPCC
> clients from the entities of APSS.
>
> Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> [mani: moved to mailbox, added static mbox channels and cleanups]
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
This looks nice now!
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> ---
> drivers/mailbox/Kconfig | 10 ++
> drivers/mailbox/Makefile | 2 +
> drivers/mailbox/qcom-ipcc.c | 286 ++++++++++++++++++++++++++++++++++++
> 3 files changed, 298 insertions(+)
> create mode 100644 drivers/mailbox/qcom-ipcc.c
>
> diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
> index 5a577a6734cf..8e1ebdbf8eab 100644
> --- a/drivers/mailbox/Kconfig
> +++ b/drivers/mailbox/Kconfig
> @@ -236,4 +236,14 @@ config SUN6I_MSGBOX
> various Allwinner SoCs. This mailbox is used for communication
> between the application CPUs and the power management coprocessor.
>
> +config QCOM_IPCC
> + bool "Qualcomm Technologies, Inc. IPCC driver"
> + depends on ARCH_QCOM || COMPILE_TEST
> + help
> + Qualcomm Technologies, Inc. Inter-Processor Communication Controller
> + (IPCC) driver for MSM devices. The driver provides mailbox support for
> + sending interrupts to the clients. On the other hand, the driver also
> + acts as an interrupt controller for receiving interrupts from clients.
> + Say Y here if you want to build this driver.
> +
> endif
> diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
> index 2e4364ef5c47..20b66b2219aa 100644
> --- a/drivers/mailbox/Makefile
> +++ b/drivers/mailbox/Makefile
> @@ -50,3 +50,5 @@ obj-$(CONFIG_MTK_CMDQ_MBOX) += mtk-cmdq-mailbox.o
> obj-$(CONFIG_ZYNQMP_IPI_MBOX) += zynqmp-ipi-mailbox.o
>
> obj-$(CONFIG_SUN6I_MSGBOX) += sun6i-msgbox.o
> +
> +obj-$(CONFIG_QCOM_IPCC) += qcom-ipcc.o
> diff --git a/drivers/mailbox/qcom-ipcc.c b/drivers/mailbox/qcom-ipcc.c
> new file mode 100644
> index 000000000000..2d13c72944c6
> --- /dev/null
> +++ b/drivers/mailbox/qcom-ipcc.c
> @@ -0,0 +1,286 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/bitfield.h>
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/irqdomain.h>
> +#include <linux/mailbox_controller.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +
> +#include <dt-bindings/mailbox/qcom-ipcc.h>
> +
> +#define IPCC_MBOX_MAX_CHAN 48
> +
> +/* IPCC Register offsets */
> +#define IPCC_REG_SEND_ID 0x0c
> +#define IPCC_REG_RECV_ID 0x10
> +#define IPCC_REG_RECV_SIGNAL_ENABLE 0x14
> +#define IPCC_REG_RECV_SIGNAL_DISABLE 0x18
> +#define IPCC_REG_RECV_SIGNAL_CLEAR 0x1c
> +#define IPCC_REG_CLIENT_CLEAR 0x38
> +
> +#define IPCC_SIGNAL_ID_MASK GENMASK(15, 0)
> +#define IPCC_CLIENT_ID_MASK GENMASK(31, 16)
> +
> +#define IPCC_NO_PENDING_IRQ GENMASK(31, 0)
> +
> +/**
> + * struct qcom_ipcc_chan_info - Per-mailbox-channel info
> + * @client_id: The client-id to which the interrupt has to be triggered
> + * @signal_id: The signal-id to which the interrupt has to be triggered
> + */
> +struct qcom_ipcc_chan_info {
> + u16 client_id;
> + u16 signal_id;
> +};
> +
> +/**
> + * struct qcom_ipcc - Holder for the mailbox driver
> + * @dev: Device associated with this instance
> + * @base: Base address of the IPCC frame associated to APSS
> + * @irq_domain: The irq_domain associated with this instance
> + * @chan: The mailbox channels array
> + * @mchan: The per-mailbox channel info array
> + * @mbox: The mailbox controller
> + * @irq: Summary irq
> + */
> +struct qcom_ipcc {
> + struct device *dev;
> + void __iomem *base;
> + struct irq_domain *irq_domain;
> + struct mbox_chan chan[IPCC_MBOX_MAX_CHAN];
> + struct qcom_ipcc_chan_info mchan[IPCC_MBOX_MAX_CHAN];
> + struct mbox_controller mbox;
> + int irq;
> +};
> +
> +static inline struct qcom_ipcc *to_qcom_ipcc(struct mbox_controller *mbox)
> +{
> + return container_of(mbox, struct qcom_ipcc, mbox);
> +}
> +
> +static inline u32 qcom_ipcc_get_hwirq(u16 client_id, u16 signal_id)
> +{
> + return FIELD_PREP(IPCC_CLIENT_ID_MASK, client_id) |
> + FIELD_PREP(IPCC_SIGNAL_ID_MASK, signal_id);
> +}
> +
> +static irqreturn_t qcom_ipcc_irq_fn(int irq, void *data)
> +{
> + struct qcom_ipcc *ipcc = data;
> + u32 hwirq;
> + int virq;
> +
> + for (;;) {
> + hwirq = readl(ipcc->base + IPCC_REG_RECV_ID);
> + if (hwirq == IPCC_NO_PENDING_IRQ)
> + break;
> +
> + virq = irq_find_mapping(ipcc->irq_domain, hwirq);
> + writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_CLEAR);
> + generic_handle_irq(virq);
> + }
> +
> + return IRQ_HANDLED;
> +}
> +
> +static void qcom_ipcc_mask_irq(struct irq_data *irqd)
> +{
> + struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd);
> + irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
> +
> + writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_DISABLE);
> +}
> +
> +static void qcom_ipcc_unmask_irq(struct irq_data *irqd)
> +{
> + struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd);
> + irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
> +
> + writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_ENABLE);
> +}
> +
> +static struct irq_chip qcom_ipcc_irq_chip = {
> + .name = "ipcc",
> + .irq_mask = qcom_ipcc_mask_irq,
> + .irq_unmask = qcom_ipcc_unmask_irq,
> + .flags = IRQCHIP_SKIP_SET_WAKE,
> +};
> +
> +static int qcom_ipcc_domain_map(struct irq_domain *d, unsigned int irq,
> + irq_hw_number_t hw)
> +{
> + struct qcom_ipcc *ipcc = d->host_data;
> +
> + irq_set_chip_and_handler(irq, &qcom_ipcc_irq_chip, handle_level_irq);
> + irq_set_chip_data(irq, ipcc);
> + irq_set_noprobe(irq);
> +
> + return 0;
> +}
> +
> +static int qcom_ipcc_domain_xlate(struct irq_domain *d,
> + struct device_node *node, const u32 *intspec,
> + unsigned int intsize,
> + unsigned long *out_hwirq,
> + unsigned int *out_type)
> +{
> + if (intsize != 3)
> + return -EINVAL;
> +
> + *out_hwirq = qcom_ipcc_get_hwirq(intspec[0], intspec[1]);
> + *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
> +
> + return 0;
> +}
> +
> +static const struct irq_domain_ops qcom_ipcc_irq_ops = {
> + .map = qcom_ipcc_domain_map,
> + .xlate = qcom_ipcc_domain_xlate,
> +};
> +
> +static int qcom_ipcc_mbox_send_data(struct mbox_chan *chan, void *data)
> +{
> + struct qcom_ipcc *ipcc = to_qcom_ipcc(chan->mbox);
> + struct qcom_ipcc_chan_info *mchan = chan->con_priv;
> + u32 hwirq;
> +
> + hwirq = qcom_ipcc_get_hwirq(mchan->client_id, mchan->signal_id);
> + writel(hwirq, ipcc->base + IPCC_REG_SEND_ID);
> +
> + return 0;
> +}
> +
> +static struct mbox_chan *qcom_ipcc_mbox_xlate(struct mbox_controller *mbox,
> + const struct of_phandle_args *ph)
> +{
> + struct qcom_ipcc *ipcc = to_qcom_ipcc(mbox);
> + struct qcom_ipcc_chan_info *mchan;
> + struct mbox_chan *chan;
> + unsigned int i;
> +
> + if (ph->args_count != 2)
> + return ERR_PTR(-EINVAL);
> +
> + for (i = 0; i < IPCC_MBOX_MAX_CHAN; i++) {
> + chan = &ipcc->chan[i];
> + if (!chan->con_priv) {
> + mchan = &ipcc->mchan[i];
> + mchan->client_id = ph->args[0];
> + mchan->signal_id = ph->args[1];
> + chan->con_priv = mchan;
> + break;
> + }
> +
> + chan = NULL;
> + }
> +
> + return chan ?: ERR_PTR(-EBUSY);
> +}
> +
> +static const struct mbox_chan_ops ipcc_mbox_chan_ops = {
> + .send_data = qcom_ipcc_mbox_send_data,
> +};
> +
> +static int qcom_ipcc_setup_mbox(struct qcom_ipcc *ipcc)
> +{
> + struct mbox_controller *mbox;
> + struct device *dev = ipcc->dev;
> +
> + mbox = &ipcc->mbox;
> + mbox->dev = dev;
> + mbox->num_chans = IPCC_MBOX_MAX_CHAN;
> + mbox->chans = ipcc->chan;
> + mbox->ops = &ipcc_mbox_chan_ops;
> + mbox->of_xlate = qcom_ipcc_mbox_xlate;
> + mbox->txdone_irq = false;
> + mbox->txdone_poll = false;
> +
> + return devm_mbox_controller_register(dev, mbox);
> +}
> +
> +static int qcom_ipcc_probe(struct platform_device *pdev)
> +{
> + struct qcom_ipcc *ipcc;
> + int ret;
> +
> + ipcc = devm_kzalloc(&pdev->dev, sizeof(*ipcc), GFP_KERNEL);
> + if (!ipcc)
> + return -ENOMEM;
> +
> + ipcc->dev = &pdev->dev;
> +
> + ipcc->base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(ipcc->base))
> + return PTR_ERR(ipcc->base);
> +
> + ipcc->irq = platform_get_irq(pdev, 0);
> + if (ipcc->irq < 0)
> + return ipcc->irq;
> +
> + ipcc->irq_domain = irq_domain_add_tree(pdev->dev.of_node,
> + &qcom_ipcc_irq_ops, ipcc);
> + if (!ipcc->irq_domain)
> + return -ENOMEM;
> +
> + ret = qcom_ipcc_setup_mbox(ipcc);
> + if (ret)
> + goto err_mbox;
> +
> + ret = devm_request_irq(&pdev->dev, ipcc->irq, qcom_ipcc_irq_fn,
> + IRQF_TRIGGER_HIGH, "ipcc", ipcc);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "Failed to register the irq: %d\n", ret);
> + goto err_mbox;
> + }
> +
> + enable_irq_wake(ipcc->irq);
> + platform_set_drvdata(pdev, ipcc);
> +
> + return 0;
> +
> +err_mbox:
> + irq_domain_remove(ipcc->irq_domain);
> +
> + return ret;
> +}
> +
> +static int qcom_ipcc_remove(struct platform_device *pdev)
> +{
> + struct qcom_ipcc *ipcc = platform_get_drvdata(pdev);
> +
> + disable_irq_wake(ipcc->irq);
> + irq_domain_remove(ipcc->irq_domain);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id qcom_ipcc_of_match[] = {
> + { .compatible = "qcom,ipcc"},
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, qcom_ipcc_of_match);
> +
> +static struct platform_driver qcom_ipcc_driver = {
> + .probe = qcom_ipcc_probe,
> + .remove = qcom_ipcc_remove,
> + .driver = {
> + .name = "qcom-ipcc",
> + .of_match_table = qcom_ipcc_of_match,
> + },
> +};
> +
> +static int __init qcom_ipcc_init(void)
> +{
> + return platform_driver_register(&qcom_ipcc_driver);
> +}
> +arch_initcall(qcom_ipcc_init);
> +
> +MODULE_AUTHOR("Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>");
> +MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
> +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPCC driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.17.1
>
^ permalink raw reply
* Re: [PATCH 3/5] dt-bindings: iio: accel: Add bma023 compatible to bma180
From: Rob Herring @ 2020-05-12 22:15 UTC (permalink / raw)
To: Jonathan Bakker
Cc: devicetree, linux-kernel, tglx, jic23, linux-iio, gregkh, pmeerw,
linus.walleij, linux-input, lars, kstewart, knaack.h,
dmitry.torokhov, robh+dt
In-Reply-To: <BN6PR04MB0660DA2A47787A56A2FC7290A3A90@BN6PR04MB0660.namprd04.prod.outlook.com>
On Sun, 3 May 2020 10:22:04 -0700, Jonathan Bakker wrote:
> The bma023 is in the same family as the bma180 and support is
> being added to the bma180 IIO driver for it.
>
> Signed-off-by: Jonathan Bakker <xc-racer2@live.ca>
> ---
> Documentation/devicetree/bindings/iio/accel/bma180.txt | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 4/5] dt-bindings: iio: accel: Add required regulators to bma180
From: Rob Herring @ 2020-05-12 22:15 UTC (permalink / raw)
To: Jonathan Bakker
Cc: knaack.h, tglx, linus.walleij, linux-kernel, lars, jic23, robh+dt,
kstewart, pmeerw, gregkh, linux-input, dmitry.torokhov,
devicetree, linux-iio
In-Reply-To: <BN6PR04MB06609033B2E0AB157A228989A3A90@BN6PR04MB0660.namprd04.prod.outlook.com>
On Sun, 3 May 2020 10:22:05 -0700, Jonathan Bakker wrote:
> The bma180 and related chips should have two registers attached to
> them. The IIO driver currently uses them, document them here as
> well.
>
> Signed-off-by: Jonathan Bakker <xc-racer2@live.ca>
> ---
> Documentation/devicetree/bindings/iio/accel/bma180.txt | 2 ++
> 1 file changed, 2 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 3/3] MAINTAINERS: Add entry for Qualcomm IPCC driver
From: Bjorn Andersson @ 2020-05-12 22:13 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: jassisinghbrar, robh+dt, linux-arm-msm, linux-kernel, devicetree
In-Reply-To: <20200508182703.29021-4-manivannan.sadhasivam@linaro.org>
On Fri 08 May 11:27 PDT 2020, Manivannan Sadhasivam wrote:
> Add MAINTAINERS entry for Qualcomm IPCC driver and its binding.
>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> MAINTAINERS | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index e64e5db31497..cc2fb991cc0d 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -14013,6 +14013,14 @@ L: linux-arm-msm@vger.kernel.org
> S: Maintained
> F: drivers/iommu/qcom_iommu.c
>
> +QUALCOMM IPCC MAILBOX DRIVER
> +M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> +L: linux-arm-msm@vger.kernel.org
> +S: Supported
> +F: Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
> +F: drivers/mailbox/qcom-ipcc.c
> +F: include/dt-bindings/mailbox/qcom-ipcc.h
> +
> QUALCOMM RMNET DRIVER
> M: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
> M: Sean Tranchetti <stranche@codeaurora.org>
> --
> 2.17.1
>
^ permalink raw reply
* Re: [PATCH v2 01/10] dt-bindings: pinctrl: sh-pfc: Document r8a7742 PFC support
From: Rob Herring @ 2020-05-12 22:17 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Ulf Hansson, Rob Herring, linux-serial, dmaengine,
Greg Kroah-Hartman, Prabhakar, Linus Walleij, linux-mmc,
linux-gpio, Magnus Damm, Vinod Koul, Geert Uytterhoeven,
linux-renesas-soc, linux-kernel, devicetree
In-Reply-To: <1588542414-14826-2-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Sun, 3 May 2020 22:46:45 +0100, Lad Prabhakar wrote:
> Document PFC support for the RZ/G1H (R8A7742) SoC.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> .../devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 03/10] dt-bindings: serial: renesas,scifa: Document r8a7742 bindings
From: Rob Herring @ 2020-05-12 22:20 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Linus Walleij, linux-renesas-soc, linux-mmc, linux-serial,
Greg Kroah-Hartman, Vinod Koul, Rob Herring, Prabhakar,
devicetree, dmaengine, Magnus Damm, Geert Uytterhoeven,
Ulf Hansson, linux-kernel, linux-gpio
In-Reply-To: <1588542414-14826-4-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Sun, 3 May 2020 22:46:47 +0100, Lad Prabhakar wrote:
> RZ/G1H (R8A7742) SoC also has the R-Car gen2 compatible SCIFA ports,
> so document the SoC specific bindings.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> Documentation/devicetree/bindings/serial/renesas,scifa.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 05/10] dt-bindings: renesas,rcar-dmac: Document r8a7742 support
From: Rob Herring @ 2020-05-12 22:21 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Prabhakar, Geert Uytterhoeven, devicetree, linux-renesas-soc,
Ulf Hansson, Rob Herring, linux-gpio, dmaengine,
Greg Kroah-Hartman, linux-kernel, Linus Walleij, Vinod Koul,
linux-serial, Magnus Damm, linux-mmc
In-Reply-To: <1588542414-14826-6-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Sun, 3 May 2020 22:46:49 +0100, Lad Prabhakar wrote:
> Renesas RZ/G SoC also have the R-Car gen2/3 compatible DMA controllers.
> Document RZ/G1H (also known as R8A7742) SoC bindings.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 07/10] dt-bindings: arm: Document iW-RainboW-G21M-Qseven-RZG1H system on module
From: Rob Herring @ 2020-05-12 22:21 UTC (permalink / raw)
To: Lad Prabhakar
Cc: Rob Herring, dmaengine, linux-mmc, linux-serial, Linus Walleij,
linux-gpio, Geert Uytterhoeven, Vinod Koul, linux-kernel,
linux-renesas-soc, devicetree, Ulf Hansson, Greg Kroah-Hartman,
Prabhakar, Magnus Damm
In-Reply-To: <1588542414-14826-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Sun, 3 May 2020 22:46:51 +0100, Lad Prabhakar wrote:
> Document the iW-RainboW-G21M-Qseven-RZG1H device tree bindings,
> listing it as a supported system on module.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> ---
> Documentation/devicetree/bindings/arm/renesas.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 08/10] dt-bindings: arm: Document iW-RainboW-G21D-Qseven-RZG1H board
From: Rob Herring @ 2020-05-12 22:21 UTC (permalink / raw)
To: Lad Prabhakar
Cc: dmaengine, linux-kernel, linux-renesas-soc, Prabhakar,
Magnus Damm, Linus Walleij, linux-mmc, Geert Uytterhoeven,
Greg Kroah-Hartman, Ulf Hansson, linux-serial, Rob Herring,
devicetree, Vinod Koul, linux-gpio
In-Reply-To: <1588542414-14826-9-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Sun, 3 May 2020 22:46:52 +0100, Lad Prabhakar wrote:
> Document the iW-RainboW-G21D-Qseven-RZG1H device tree bindings,
> listing it as a supported board.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> ---
> Documentation/devicetree/bindings/arm/renesas.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH V2 2/3] clk: vc5: Enable addition output configurations of the Versaclock
From: Adam Ford @ 2020-05-12 22:21 UTC (permalink / raw)
To: Rob Herring
Cc: linux-clk, Adam Ford-BE, Charles Stevens, Michael Turquette,
Stephen Boyd, Marek Vasut, devicetree, Linux Kernel Mailing List
In-Reply-To: <20200512220537.GA14318@bogus>
On Tue, May 12, 2020 at 5:05 PM Rob Herring <robh@kernel.org> wrote:
>
> On Sat, May 02, 2020 at 07:21:25AM -0500, Adam Ford wrote:
> > The existing driver is expecting the Versaclock to be pre-programmed,
> > and only sets the output frequency. Unfortunately, not all devices
> > are pre-programmed, and the Versaclock chip has more options beyond
> > just the frequency.
> >
> > This patch enables the following additional features:
> >
> > - Programmable voltage: 1.8V, 2.5V, or 3.3V
> > - Slew Percentage of normal: 85%, 90%, or 100%
> > - Output Type: LVPECL, CMOS, HCSL, or LVDS
> >
> > Signed-off-by: Adam Ford <aford173@gmail.com>
>
>
> > diff --git a/include/dt-bindings/clk/versaclock.h b/include/dt-bindings/clk/versaclock.h
> > new file mode 100644
> > index 000000000000..c6a6a0946564
> > --- /dev/null
> > +++ b/include/dt-bindings/clk/versaclock.h
>
> Belongs in binding patch.
I can do that, but the binding patch will have to be applied before
the rest of the series, or the source won't build because it's
referencing the bindings. Is that OK?
adam
>
> > @@ -0,0 +1,13 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +
> > +/* This file defines field values used by the versaclock 6 family
> > + * for defining output type
> > + */
> > +
> > +#define VC5_LVPECL 0
> > +#define VC5_CMOS 1
> > +#define VC5_HCSL33 2
> > +#define VC5_LVDS 3
> > +#define VC5_CMOS2 4
> > +#define VC5_CMOSD 5
> > +#define VC5_HCSL25 6
> > --
> > 2.25.1
> >
^ permalink raw reply
* [PATCH v2 0/4] Add support for vibrator motor for TBS A711 Tablet
From: Ondrej Jirman @ 2020-05-12 22:22 UTC (permalink / raw)
To: linux-sunxi, Dmitry Torokhov, Rob Herring, Mark Rutland,
Maxime Ripard, Chen-Yu Tsai
Cc: Ondrej Jirman, Luca Weiss, Tomas Novotny, linux-input, devicetree,
linux-kernel, linux-arm-kernel
The tablet has a vibrator motor. This patch series exposes it via
input subsystem (EV_FF).
I'd like to ask input maintainers to take the patches 1 and 2.
Patches 3 and 4 should go via the sunxi tree.
The change to the vibrator driver is meant to enable toggling the
vibrator motor just via a power supply itself. There's not additional
gpio driven switch on this tablet between the power supply for the
motor and the motor.
Please take a look.
Changes in v2:
- Added DT ack tag
- Add more information to the commit log (re use of LDO for the power)
thank you and regards,
Ondrej Jirman
Ondrej Jirman (4):
dt-bindings: input: gpio-vibrator: Don't require enable-gpios
input: gpio-vibra: Allow to use vcc-supply alone to control the
vibrator
ARM: dts: sun8i-a83t-tbs-a711: Add support for the vibrator motor
ARM: dts: sun8i-a83t-tbs-a711: Increase voltage on the vibrator
.../devicetree/bindings/input/gpio-vibrator.yaml | 1 -
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 9 +++++++--
drivers/input/misc/gpio-vibra.c | 3 ++-
3 files changed, 9 insertions(+), 4 deletions(-)
--
2.26.2
^ permalink raw reply
* [PATCH v2 3/4] ARM: dts: sun8i-a83t-tbs-a711: Add support for the vibrator motor
From: Ondrej Jirman @ 2020-05-12 22:22 UTC (permalink / raw)
To: linux-sunxi, Dmitry Torokhov, Rob Herring, Mark Rutland,
Maxime Ripard, Chen-Yu Tsai
Cc: Ondrej Jirman, Luca Weiss, Tomas Novotny, linux-input, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <20200512222205.1456300-1-megous@megous.com>
The board has a vibrator mottor. Hook it to the input subsystem.
According to the PMIC specification, LDO needs to be enabled (value 0b11)
to achieve the specified max driving current of 150mA. We can't drive
the motor with just GPIO mode.
In GPIO mode the chip is probably just using the regular CMOS logic
output circuitry (typically limited to around 20-35mA, but not specified
in this datasheet).
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index bfc9bb277a49..a278a1e33930 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -99,6 +99,11 @@ panel_input: endpoint {
};
};
+ vibrator {
+ compatible = "gpio-vibrator";
+ vcc-supply = <®_ldo_io1>;
+ };
+
reg_gps: reg-gps {
compatible = "regulator-fixed";
regulator-name = "gps";
--
2.26.2
^ permalink raw reply related
* [PATCH v2 1/4] dt-bindings: input: gpio-vibrator: Don't require enable-gpios
From: Ondrej Jirman @ 2020-05-12 22:22 UTC (permalink / raw)
To: linux-sunxi, Dmitry Torokhov, Rob Herring, Mark Rutland,
Maxime Ripard, Chen-Yu Tsai
Cc: Ondrej Jirman, Luca Weiss, Tomas Novotny, linux-input, devicetree,
linux-kernel, linux-arm-kernel, Rob Herring
In-Reply-To: <20200512222205.1456300-1-megous@megous.com>
It is possible to turn the motor on/off just by enabling/disabling
the vcc-supply.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/input/gpio-vibrator.yaml | 1 -
1 file changed, 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/input/gpio-vibrator.yaml b/Documentation/devicetree/bindings/input/gpio-vibrator.yaml
index 2384465eaa19..c700b640bd53 100644
--- a/Documentation/devicetree/bindings/input/gpio-vibrator.yaml
+++ b/Documentation/devicetree/bindings/input/gpio-vibrator.yaml
@@ -24,7 +24,6 @@ properties:
required:
- compatible
- - enable-gpios
additionalProperties: false
--
2.26.2
^ permalink raw reply related
* [PATCH v2 4/4] ARM: dts: sun8i-a83t-tbs-a711: Increase voltage on the vibrator
From: Ondrej Jirman @ 2020-05-12 22:22 UTC (permalink / raw)
To: linux-sunxi, Dmitry Torokhov, Rob Herring, Mark Rutland,
Maxime Ripard, Chen-Yu Tsai
Cc: Ondrej Jirman, Luca Weiss, Tomas Novotny, linux-input, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <20200512222205.1456300-1-megous@megous.com>
Vibrator motor is weak at the current voltage. Increase the voltage.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
index a278a1e33930..1e086e979348 100644
--- a/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-tbs-a711.dts
@@ -434,8 +434,8 @@ ®_ldo_io0 {
};
®_ldo_io1 {
- regulator-min-microvolt = <3100000>;
- regulator-max-microvolt = <3100000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
regulator-name = "vcc-vb";
status = "okay";
};
--
2.26.2
^ permalink raw reply related
* [PATCH v2 2/4] input: gpio-vibra: Allow to use vcc-supply alone to control the vibrator
From: Ondrej Jirman @ 2020-05-12 22:22 UTC (permalink / raw)
To: linux-sunxi, Dmitry Torokhov, Rob Herring, Mark Rutland,
Maxime Ripard, Chen-Yu Tsai
Cc: Ondrej Jirman, Luca Weiss, Tomas Novotny, linux-input, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <20200512222205.1456300-1-megous@megous.com>
Make enable-gpio optional to allow using this driver with
boards that have vibrator connected to a power supply without
intermediate gpio based enable circuitry.
Signed-off-by: Ondrej Jirman <megous@megous.com>
---
drivers/input/misc/gpio-vibra.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/input/misc/gpio-vibra.c b/drivers/input/misc/gpio-vibra.c
index f79f75595dd7..f11877f04b43 100644
--- a/drivers/input/misc/gpio-vibra.c
+++ b/drivers/input/misc/gpio-vibra.c
@@ -121,7 +121,8 @@ static int gpio_vibrator_probe(struct platform_device *pdev)
return err;
}
- vibrator->gpio = devm_gpiod_get(&pdev->dev, "enable", GPIOD_OUT_LOW);
+ vibrator->gpio = devm_gpiod_get_optional(&pdev->dev, "enable",
+ GPIOD_OUT_LOW);
err = PTR_ERR_OR_ZERO(vibrator->gpio);
if (err) {
if (err != -EPROBE_DEFER)
--
2.26.2
^ permalink raw reply related
* [PATCH v2 0/6] phy: meson8b-usb2: small fixes and improvements
From: Martin Blumenstingl @ 2020-05-12 22:24 UTC (permalink / raw)
To: kishon, robh+dt, vkoul, devicetree, linux-amlogic
Cc: narmstrong, linux-arm-kernel, linux-kernel, hexdump0815,
Martin Blumenstingl
This is a batch of fixes and improvements for the phy-meson8b-usb2
driver:
- convert the existing dt-bindings to json-schema and add a fallback
compatible string which is already in existing .dtsi files
- differentiate between Meson8 and Meson8m2 using a new compatible
string for the latter
- simplify the code by using a MMIO regmap
- set / unset the IDDQ and ACA enable bits depending on the operating
mode (and for the latter also the compatible string)
I suggest that all of these are applied to -next because we will need a
separate .dts patch (which I already have prepared) to use the new
Meson8m2 compatible string in meson8m2.dtsi. Otherwise we will be
changing behavior in patch #4, because meson8m2.dtsi currently inherits
the Meson8 compatible string.
The number of actual Meson8 users is very small (I only know one case),
so keeping Meson8m2 working is more important to me (because I know
several users with boards that have a Meson8m2 SoC).
Changes since v1 at [0]:
- added Thomas' Tested-bys (thank you!)
- also switched to the correct email address of Thomas for Reported-by
in patch #4
- added two more spaces for the indentation of the compatible "enum",
fixed the indentation (was three instead of two spaces) of the
phy-supply property and added additionalProperties: false. All
spotted in patch #1 by Rob - thank you!
- added Rob's Acked-by to patch #2 (thank you!), after fixing up the
indentation to also use four spaces (same as in patch #1)
[0] https://patchwork.kernel.org/cover/11523811/
Martin Blumenstingl (6):
dt-bindings: phy: meson8b-usb2: Convert to json-schema
dt-bindings: phy: meson8b-usb2: Add compatible string for Meson8m2
phy: amlogic: meson8b-usb2: Use a MMIO regmap
phy: amlogic: meson8b-usb2: Don't set REG_ADP_BC_ACA_ENABLE on Meson8
phy: amlogic: meson8b-usb2: unset the IDDQ bit during PHY power-on
phy: amlogic: meson8b-usb2: Add a compatible string for Meson8m2
.../phy/amlogic,meson8b-usb2-phy.yaml | 64 ++++++++
.../bindings/phy/meson8b-usb2-phy.txt | 28 ----
drivers/phy/amlogic/Kconfig | 3 +-
drivers/phy/amlogic/phy-meson8b-usb2.c | 149 ++++++++++++------
4 files changed, 164 insertions(+), 80 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/meson8b-usb2-phy.txt
--
2.26.2
^ permalink raw reply
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