* [PATCH 14/14] arm64: dts: sparx5: Add i2c devices, i2c muxes
From: Lars Povlsen @ 2020-05-13 12:55 UTC (permalink / raw)
To: SoC Team, Arnd Bergmann, Stephen Boyd, Linus Walleij
Cc: Lars Povlsen, Steen Hegelund, Microchip Linux Driver Support,
Olof Johansson, Michael Turquette, devicetree, linux-clk,
linux-gpio, linux-arm-kernel, linux-kernel, Alexandre Belloni
In-Reply-To: <20200513125532.24585-1-lars.povlsen@microchip.com>
This patch adds i2c devices and muxes to the Sparx5 reference boards.
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 36 +++
.../boot/dts/microchip/sparx5_pcb125.dts | 4 +
.../dts/microchip/sparx5_pcb134_board.dtsi | 237 ++++++++++++++++++
.../dts/microchip/sparx5_pcb135_board.dtsi | 77 ++++++
.../boot/dts/microchip/sparx5_pcb_common.dtsi | 4 +
5 files changed, 358 insertions(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index ca4055f04ac26..b5cb3d8dc876b 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -160,7 +160,43 @@ uart2_pins: uart2-pins {
function = "uart2";
};
+ i2c_pins: i2c-pins {
+ pins = "GPIO_14", "GPIO_15";
+ function = "twi";
+ };
+
+ i2c2_pins: i2c2-pins {
+ pins = "GPIO_28", "GPIO_29";
+ function = "twi2";
+ };
+ };
+
+ i2c0: i2c@600101000 {
+ compatible = "snps,designware-i2c";
+ status = "disabled";
+ pinctrl-0 = <&i2c_pins>;
+ pinctrl-names = "default";
+ reg = <0x6 0x00101000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-sda-hold-time-ns = <300>;
+ clock-frequency = <100000>;
+ clocks = <&ahb_clk>;
};
+ i2c1: i2c@600103000 {
+ compatible = "snps,designware-i2c";
+ status = "disabled";
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-names = "default";
+ reg = <0x6 0x00103000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ i2c-sda-hold-time-ns = <300>;
+ clock-frequency = <100000>;
+ clocks = <&ahb_clk>;
+ };
};
};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
index d7f985f7ee020..91ee5b6cfc37a 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
@@ -15,3 +15,7 @@ memory@0 {
reg = <0x00000000 0x00000000 0x10000000>;
};
};
+
+&i2c1 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
index 9b2aec400101b..18a535a043686 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
@@ -7,9 +7,246 @@
#include "sparx5_pcb_common.dtsi"
/{
+ aliases {
+ i2c0 = &i2c0;
+ i2c100 = &i2c100;
+ i2c101 = &i2c101;
+ i2c102 = &i2c102;
+ i2c103 = &i2c103;
+ i2c104 = &i2c104;
+ i2c105 = &i2c105;
+ i2c106 = &i2c106;
+ i2c107 = &i2c107;
+ i2c108 = &i2c108;
+ i2c109 = &i2c109;
+ i2c110 = &i2c110;
+ i2c111 = &i2c111;
+ i2c112 = &i2c112;
+ i2c113 = &i2c113;
+ i2c114 = &i2c114;
+ i2c115 = &i2c115;
+ i2c116 = &i2c116;
+ i2c117 = &i2c117;
+ i2c118 = &i2c118;
+ i2c119 = &i2c119;
+ };
+
gpio-restart {
compatible = "gpio-restart";
gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
priority = <200>;
};
};
+
+&gpio {
+ i2cmux_pins_i: i2cmux-pins-i {
+ pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19",
+ "GPIO_20", "GPIO_22", "GPIO_36", "GPIO_35",
+ "GPIO_50", "GPIO_51", "GPIO_56", "GPIO_57";
+ function = "twi_scl_m";
+ output-low;
+ };
+ i2cmux_0: i2cmux-0 {
+ pins = "GPIO_16";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_1: i2cmux-1 {
+ pins = "GPIO_17";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_2: i2cmux-2 {
+ pins = "GPIO_18";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_3: i2cmux-3 {
+ pins = "GPIO_19";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_4: i2cmux-4 {
+ pins = "GPIO_20";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_5: i2cmux-5 {
+ pins = "GPIO_22";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_6: i2cmux-6 {
+ pins = "GPIO_36";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_7: i2cmux-7 {
+ pins = "GPIO_35";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_8: i2cmux-8 {
+ pins = "GPIO_50";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_9: i2cmux-9 {
+ pins = "GPIO_51";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_10: i2cmux-10 {
+ pins = "GPIO_56";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_11: i2cmux-11 {
+ pins = "GPIO_57";
+ function = "twi_scl_m";
+ output-high;
+ };
+};
+
+&axi {
+ i2c0_imux: i2c0-imux@0 {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c0>;
+ };
+ i2c0_emux: i2c0-emux@0 {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c0>;
+ };
+};
+
+&i2c0_imux {
+ pinctrl-names =
+ "i2c100", "i2c101", "i2c102", "i2c103",
+ "i2c104", "i2c105", "i2c106", "i2c107",
+ "i2c108", "i2c109", "i2c110", "i2c111", "idle";
+ pinctrl-0 = <&i2cmux_0>;
+ pinctrl-1 = <&i2cmux_1>;
+ pinctrl-2 = <&i2cmux_2>;
+ pinctrl-3 = <&i2cmux_3>;
+ pinctrl-4 = <&i2cmux_4>;
+ pinctrl-5 = <&i2cmux_5>;
+ pinctrl-6 = <&i2cmux_6>;
+ pinctrl-7 = <&i2cmux_7>;
+ pinctrl-8 = <&i2cmux_8>;
+ pinctrl-9 = <&i2cmux_9>;
+ pinctrl-10 = <&i2cmux_10>;
+ pinctrl-11 = <&i2cmux_11>;
+ pinctrl-12 = <&i2cmux_pins_i>;
+ i2c100: i2c_sfp1 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c101: i2c_sfp2 {
+ reg = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c102: i2c_sfp3 {
+ reg = <0x2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c103: i2c_sfp4 {
+ reg = <0x3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c104: i2c_sfp5 {
+ reg = <0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c105: i2c_sfp6 {
+ reg = <0x5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c106: i2c_sfp7 {
+ reg = <0x6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c107: i2c_sfp8 {
+ reg = <0x7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c108: i2c_sfp9 {
+ reg = <0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c109: i2c_sfp10 {
+ reg = <0x9>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c110: i2c_sfp11 {
+ reg = <0xa>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c111: i2c_sfp12 {
+ reg = <0xb>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
+
+&i2c0_emux {
+ mux-gpios = <&gpio 55 GPIO_ACTIVE_HIGH
+ &gpio 60 GPIO_ACTIVE_HIGH
+ &gpio 61 GPIO_ACTIVE_HIGH
+ &gpio 54 GPIO_ACTIVE_HIGH>;
+ idle-state = <0x8>;
+ i2c112: i2c_sfp13 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c113: i2c_sfp14 {
+ reg = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c114: i2c_sfp15 {
+ reg = <0x2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c115: i2c_sfp16 {
+ reg = <0x3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c116: i2c_sfp17 {
+ reg = <0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c117: i2c_sfp18 {
+ reg = <0x5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c118: i2c_sfp19 {
+ reg = <0x6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c119: i2c_sfp20 {
+ reg = <0x7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
index 9b2aec400101b..d71f11a10b3d2 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
@@ -7,9 +7,86 @@
#include "sparx5_pcb_common.dtsi"
/{
+ aliases {
+ i2c0 = &i2c0;
+ i2c152 = &i2c152;
+ i2c153 = &i2c153;
+ i2c154 = &i2c154;
+ i2c155 = &i2c155;
+ };
+
gpio-restart {
compatible = "gpio-restart";
gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
priority = <200>;
};
};
+
+&gpio {
+ i2cmux_pins_i: i2cmux-pins-i {
+ pins = "GPIO_35", "GPIO_36",
+ "GPIO_50", "GPIO_51";
+ function = "twi_scl_m";
+ output-low;
+ };
+ i2cmux_s29: i2cmux-0 {
+ pins = "GPIO_35";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_s30: i2cmux-1 {
+ pins = "GPIO_36";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_s31: i2cmux-2 {
+ pins = "GPIO_50";
+ function = "twi_scl_m";
+ output-high;
+ };
+ i2cmux_s32: i2cmux-3 {
+ pins = "GPIO_51";
+ function = "twi_scl_m";
+ output-high;
+ };
+};
+
+&axi {
+ i2c0_imux: i2c0-imux@0 {
+ compatible = "i2c-mux-pinctrl";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ i2c-parent = <&i2c0>;
+ };
+};
+
+&i2c0_imux {
+ pinctrl-names =
+ "i2c152", "i2c153", "i2c154", "i2c155",
+ "idle";
+ pinctrl-0 = <&i2cmux_s29>;
+ pinctrl-1 = <&i2cmux_s30>;
+ pinctrl-2 = <&i2cmux_s31>;
+ pinctrl-3 = <&i2cmux_s32>;
+ pinctrl-4 = <&i2cmux_pins_i>;
+ i2c152: i2c_sfp1 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c153: i2c_sfp2 {
+ reg = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c154: i2c_sfp3 {
+ reg = <0x2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ i2c155: i2c_sfp4 {
+ reg = <0x3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi
index 1f99d0db1284f..9d1a082de3e29 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi
@@ -13,3 +13,7 @@ &uart0 {
&uart1 {
status = "okay";
};
+
+&i2c0 {
+ status = "okay";
+};
--
2.26.2
^ permalink raw reply related
* [PATCH 10/14] dt-bindings: clock: sparx5: Add Sparx5 SoC DPLL clock
From: Lars Povlsen @ 2020-05-13 12:55 UTC (permalink / raw)
To: SoC Team, Arnd Bergmann, Stephen Boyd, Linus Walleij, Rob Herring
Cc: Lars Povlsen, Steen Hegelund, Microchip Linux Driver Support,
Olof Johansson, Michael Turquette, devicetree, linux-clk,
linux-gpio, linux-arm-kernel, linux-kernel, Alexandre Belloni
In-Reply-To: <20200513125532.24585-1-lars.povlsen@microchip.com>
This add the DT bindings documentation for the Sparx5 SoC DPLL clock
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
.../bindings/clock/microchip,sparx5-dpll.yaml | 46 +++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml
diff --git a/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml
new file mode 100644
index 0000000000000..594007d8fc59a
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/microchip,sparx5-dpll.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Sparx5 DPLL Clock
+
+maintainers:
+ - Lars Povlsen <lars.povlsen@microchip.com>
+
+description: |
+ The Sparx5 DPLL clock controller generates and supplies clock to
+ various peripherals within the SoC.
+
+ This binding uses common clock bindings
+ [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+properties:
+ compatible:
+ const: microchip,sparx5-dpll
+
+ reg:
+ items:
+ - description: dpll registers
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ # Clock provider for eMMC:
+ - |
+ clks: clks@61110000c {
+ compatible = "microchip,sparx5-dpll";
+ #clock-cells = <1>;
+ reg = <0x1110000c 0x24>;
+ };
+
+...
--
2.26.2
^ permalink raw reply related
* [PATCH 09/14] pinctrl: ocelot: Add Sparx5 SoC support
From: Lars Povlsen @ 2020-05-13 12:55 UTC (permalink / raw)
To: SoC Team, Arnd Bergmann, Stephen Boyd, Linus Walleij
Cc: Lars Povlsen, Steen Hegelund, Microchip Linux Driver Support,
Olof Johansson, Michael Turquette, devicetree, linux-clk,
linux-gpio, linux-arm-kernel, linux-kernel, Alexandre Belloni
In-Reply-To: <20200513125532.24585-1-lars.povlsen@microchip.com>
This add support for Sparx5 pinctrl, using the ocelot drives as
basis. It adds pinconfig support as well, as supported by the
platform.
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
drivers/pinctrl/pinctrl-ocelot.c | 431 ++++++++++++++++++++++++++++++-
1 file changed, 430 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c
index 95c225bc7572f..35a482dc6b1a0 100644
--- a/drivers/pinctrl/pinctrl-ocelot.c
+++ b/drivers/pinctrl/pinctrl-ocelot.c
@@ -25,6 +25,23 @@
#include "pinconf.h"
#include "pinmux.h"
+#define clrsetbits(addr, clear, set) \
+ writel((readl(addr) & ~(clear)) | (set), (addr))
+
+/* PINCONFIG bits (sparx5 only) */
+enum {
+ PINCONF_BIAS,
+ PINCONF_SCHMITT,
+ PINCONF_DRIVE_STRENGTH,
+};
+
+#define BIAS_PD_BIT BIT(4)
+#define BIAS_PU_BIT BIT(3)
+#define BIAS_BITS (BIAS_PD_BIT|BIAS_PU_BIT)
+#define SCHMITT_BIT BIT(2)
+#define DRIVE_BITS GENMASK(1, 0)
+
+/* GPIO standard registers */
#define OCELOT_GPIO_OUT_SET 0x0
#define OCELOT_GPIO_OUT_CLR 0x4
#define OCELOT_GPIO_OUT 0x8
@@ -42,12 +59,17 @@
enum {
FUNC_NONE,
FUNC_GPIO,
+ FUNC_IRQ0,
FUNC_IRQ0_IN,
FUNC_IRQ0_OUT,
+ FUNC_IRQ1,
FUNC_IRQ1_IN,
FUNC_IRQ1_OUT,
+ FUNC_EXT_IRQ,
FUNC_MIIM,
+ FUNC_PHY_LED,
FUNC_PCI_WAKE,
+ FUNC_MD,
FUNC_PTP0,
FUNC_PTP1,
FUNC_PTP2,
@@ -59,24 +81,36 @@ enum {
FUNC_SG1,
FUNC_SG2,
FUNC_SI,
+ FUNC_SI2,
FUNC_TACHO,
FUNC_TWI,
FUNC_TWI2,
+ FUNC_TWI3,
FUNC_TWI_SCL_M,
FUNC_UART,
FUNC_UART2,
+ FUNC_UART3,
+ FUNC_PLL_STAT,
+ FUNC_EMMC,
+ FUNC_REF_CLK,
+ FUNC_RCVRD_CLK,
FUNC_MAX
};
static const char *const ocelot_function_names[] = {
[FUNC_NONE] = "none",
[FUNC_GPIO] = "gpio",
+ [FUNC_IRQ0] = "irq0",
[FUNC_IRQ0_IN] = "irq0_in",
[FUNC_IRQ0_OUT] = "irq0_out",
+ [FUNC_IRQ1] = "irq1",
[FUNC_IRQ1_IN] = "irq1_in",
[FUNC_IRQ1_OUT] = "irq1_out",
+ [FUNC_EXT_IRQ] = "ext_irq",
[FUNC_MIIM] = "miim",
+ [FUNC_PHY_LED] = "phy_led",
[FUNC_PCI_WAKE] = "pci_wake",
+ [FUNC_MD] = "md",
[FUNC_PTP0] = "ptp0",
[FUNC_PTP1] = "ptp1",
[FUNC_PTP2] = "ptp2",
@@ -88,12 +122,19 @@ static const char *const ocelot_function_names[] = {
[FUNC_SG1] = "sg1",
[FUNC_SG2] = "sg2",
[FUNC_SI] = "si",
+ [FUNC_SI2] = "si2",
[FUNC_TACHO] = "tacho",
[FUNC_TWI] = "twi",
[FUNC_TWI2] = "twi2",
+ [FUNC_TWI3] = "twi3",
[FUNC_TWI_SCL_M] = "twi_scl_m",
[FUNC_UART] = "uart",
[FUNC_UART2] = "uart2",
+ [FUNC_UART3] = "uart3",
+ [FUNC_PLL_STAT] = "pll_stat",
+ [FUNC_EMMC] = "emmc",
+ [FUNC_REF_CLK] = "ref_clk",
+ [FUNC_RCVRD_CLK] = "rcvrd_clk",
};
struct ocelot_pmx_func {
@@ -111,6 +152,7 @@ struct ocelot_pinctrl {
struct pinctrl_dev *pctl;
struct gpio_chip gpio_chip;
struct regmap *map;
+ void __iomem *pincfg;
struct pinctrl_desc *desc;
struct ocelot_pmx_func func[FUNC_MAX];
u8 stride;
@@ -324,6 +366,152 @@ static const struct pinctrl_pin_desc jaguar2_pins[] = {
JAGUAR2_PIN(63),
};
+#define SPARX5_P(p, f0, f1, f2) \
+static struct ocelot_pin_caps sparx5_pin_##p = { \
+ .pin = p, \
+ .functions = { \
+ FUNC_GPIO, FUNC_##f0, FUNC_##f1, FUNC_##f2 \
+ }, \
+}
+
+SPARX5_P(0, SG0, PLL_STAT, NONE);
+SPARX5_P(1, SG0, NONE, NONE);
+SPARX5_P(2, SG0, NONE, NONE);
+SPARX5_P(3, SG0, NONE, NONE);
+SPARX5_P(4, SG1, NONE, NONE);
+SPARX5_P(5, SG1, NONE, NONE);
+SPARX5_P(6, IRQ0_IN, IRQ0_OUT, SFP);
+SPARX5_P(7, IRQ1_IN, IRQ1_OUT, SFP);
+SPARX5_P(8, PTP0, NONE, SFP);
+SPARX5_P(9, PTP1, SFP, TWI_SCL_M);
+SPARX5_P(10, UART, NONE, NONE);
+SPARX5_P(11, UART, NONE, NONE);
+SPARX5_P(12, SG1, NONE, NONE);
+SPARX5_P(13, SG1, NONE, NONE);
+SPARX5_P(14, TWI, TWI_SCL_M, NONE);
+SPARX5_P(15, TWI, NONE, NONE);
+SPARX5_P(16, SI, TWI_SCL_M, SFP);
+SPARX5_P(17, SI, TWI_SCL_M, SFP);
+SPARX5_P(18, SI, TWI_SCL_M, SFP);
+SPARX5_P(19, PCI_WAKE, TWI_SCL_M, SFP);
+SPARX5_P(20, IRQ0_OUT, TWI_SCL_M, SFP);
+SPARX5_P(21, IRQ1_OUT, TACHO, SFP);
+SPARX5_P(22, TACHO, IRQ0_OUT, TWI_SCL_M);
+SPARX5_P(23, PWM, UART3, TWI_SCL_M);
+SPARX5_P(24, PTP2, UART3, TWI_SCL_M);
+SPARX5_P(25, PTP3, SI, TWI_SCL_M);
+SPARX5_P(26, UART2, SI, TWI_SCL_M);
+SPARX5_P(27, UART2, SI, TWI_SCL_M);
+SPARX5_P(28, TWI2, SI, SFP);
+SPARX5_P(29, TWI2, SI, SFP);
+SPARX5_P(30, SG2, SI, PWM);
+SPARX5_P(31, SG2, SI, TWI_SCL_M);
+SPARX5_P(32, SG2, SI, TWI_SCL_M);
+SPARX5_P(33, SG2, SI, SFP);
+SPARX5_P(34, NONE, TWI_SCL_M, EMMC);
+SPARX5_P(35, SFP, TWI_SCL_M, EMMC);
+SPARX5_P(36, SFP, TWI_SCL_M, EMMC);
+SPARX5_P(37, SFP, NONE, EMMC);
+SPARX5_P(38, NONE, TWI_SCL_M, EMMC);
+SPARX5_P(39, SI2, TWI_SCL_M, EMMC);
+SPARX5_P(40, SI2, TWI_SCL_M, EMMC);
+SPARX5_P(41, SI2, TWI_SCL_M, EMMC);
+SPARX5_P(42, SI2, TWI_SCL_M, EMMC);
+SPARX5_P(43, SI2, TWI_SCL_M, EMMC);
+SPARX5_P(44, SI, SFP, EMMC);
+SPARX5_P(45, SI, SFP, EMMC);
+SPARX5_P(46, NONE, SFP, EMMC);
+SPARX5_P(47, NONE, SFP, EMMC);
+SPARX5_P(48, TWI3, SI, SFP);
+SPARX5_P(49, TWI3, NONE, SFP);
+SPARX5_P(50, SFP, NONE, TWI_SCL_M);
+SPARX5_P(51, SFP, SI, TWI_SCL_M);
+SPARX5_P(52, SFP, MIIM, TWI_SCL_M);
+SPARX5_P(53, SFP, MIIM, TWI_SCL_M);
+SPARX5_P(54, SFP, PTP2, TWI_SCL_M);
+SPARX5_P(55, SFP, PTP3, PCI_WAKE);
+SPARX5_P(56, MIIM, SFP, TWI_SCL_M);
+SPARX5_P(57, MIIM, SFP, TWI_SCL_M);
+SPARX5_P(58, MIIM, SFP, TWI_SCL_M);
+SPARX5_P(59, MIIM, SFP, NONE);
+SPARX5_P(60, RECO_CLK, NONE, NONE);
+SPARX5_P(61, RECO_CLK, NONE, NONE);
+SPARX5_P(62, RECO_CLK, PLL_STAT, NONE);
+SPARX5_P(63, RECO_CLK, NONE, NONE);
+
+#define SPARX5_PIN(n) { \
+ .number = n, \
+ .name = "GPIO_"#n, \
+ .drv_data = &sparx5_pin_##n \
+}
+
+static const struct pinctrl_pin_desc sparx5_pins[] = {
+ SPARX5_PIN(0),
+ SPARX5_PIN(1),
+ SPARX5_PIN(2),
+ SPARX5_PIN(3),
+ SPARX5_PIN(4),
+ SPARX5_PIN(5),
+ SPARX5_PIN(6),
+ SPARX5_PIN(7),
+ SPARX5_PIN(8),
+ SPARX5_PIN(9),
+ SPARX5_PIN(10),
+ SPARX5_PIN(11),
+ SPARX5_PIN(12),
+ SPARX5_PIN(13),
+ SPARX5_PIN(14),
+ SPARX5_PIN(15),
+ SPARX5_PIN(16),
+ SPARX5_PIN(17),
+ SPARX5_PIN(18),
+ SPARX5_PIN(19),
+ SPARX5_PIN(20),
+ SPARX5_PIN(21),
+ SPARX5_PIN(22),
+ SPARX5_PIN(23),
+ SPARX5_PIN(24),
+ SPARX5_PIN(25),
+ SPARX5_PIN(26),
+ SPARX5_PIN(27),
+ SPARX5_PIN(28),
+ SPARX5_PIN(29),
+ SPARX5_PIN(30),
+ SPARX5_PIN(31),
+ SPARX5_PIN(32),
+ SPARX5_PIN(33),
+ SPARX5_PIN(34),
+ SPARX5_PIN(35),
+ SPARX5_PIN(36),
+ SPARX5_PIN(37),
+ SPARX5_PIN(38),
+ SPARX5_PIN(39),
+ SPARX5_PIN(40),
+ SPARX5_PIN(41),
+ SPARX5_PIN(42),
+ SPARX5_PIN(43),
+ SPARX5_PIN(44),
+ SPARX5_PIN(45),
+ SPARX5_PIN(46),
+ SPARX5_PIN(47),
+ SPARX5_PIN(48),
+ SPARX5_PIN(49),
+ SPARX5_PIN(50),
+ SPARX5_PIN(51),
+ SPARX5_PIN(52),
+ SPARX5_PIN(53),
+ SPARX5_PIN(54),
+ SPARX5_PIN(55),
+ SPARX5_PIN(56),
+ SPARX5_PIN(57),
+ SPARX5_PIN(58),
+ SPARX5_PIN(59),
+ SPARX5_PIN(60),
+ SPARX5_PIN(61),
+ SPARX5_PIN(62),
+ SPARX5_PIN(63),
+};
+
static int ocelot_get_functions_count(struct pinctrl_dev *pctldev)
{
return ARRAY_SIZE(ocelot_function_names);
@@ -382,6 +570,7 @@ static int ocelot_pinmux_set_mux(struct pinctrl_dev *pctldev,
* ALT[1]
* This is racy because both registers can't be updated at the same time
* but it doesn't matter much for now.
+ * Note: ALT0/ALT1 are organized specially for 64 gpio targets
*/
regmap_update_bits(info->map, REG_ALT(0, info, pin->pin),
BIT(p), f << p);
@@ -458,6 +647,220 @@ static int ocelot_pctl_get_group_pins(struct pinctrl_dev *pctldev,
return 0;
}
+static int ocelot_hw_get_value(struct ocelot_pinctrl *info,
+ unsigned int pin,
+ unsigned int reg,
+ int *val)
+{
+ int ret = -ENOTSUPP;
+
+ if (info->pincfg) {
+ u32 regcfg = readl(info->pincfg + (pin * sizeof(u32)));
+ u32 value;
+
+ ret = 0;
+ switch (reg) {
+ case PINCONF_BIAS:
+ value = regcfg & BIAS_BITS;
+ break;
+
+ case PINCONF_SCHMITT:
+ value = regcfg & SCHMITT_BIT;
+ break;
+
+ case PINCONF_DRIVE_STRENGTH:
+ value = regcfg & DRIVE_BITS;
+ break;
+
+ default:
+ ret = -ENOTSUPP;
+ break;
+ }
+ }
+ return ret;
+}
+
+static int ocelot_hw_set_value(struct ocelot_pinctrl *info,
+ unsigned int pin,
+ unsigned int reg,
+ int val)
+{
+ int ret = -ENOTSUPP;
+
+ if (info->pincfg) {
+ void __iomem *regaddr = info->pincfg + (pin * sizeof(u32));
+
+ ret = 0;
+ switch (reg) {
+ case PINCONF_BIAS:
+ clrsetbits(regaddr, BIAS_BITS, val);
+ break;
+
+ case PINCONF_SCHMITT:
+ clrsetbits(regaddr, SCHMITT_BIT, val);
+ break;
+
+ case PINCONF_DRIVE_STRENGTH:
+ if (val <= 3)
+ clrsetbits(regaddr, DRIVE_BITS, val);
+ else
+ ret = -EINVAL;
+ break;
+
+ default:
+ ret = -ENOTSUPP;
+ break;
+ }
+ }
+ return ret;
+}
+
+static int ocelot_pinconf_get(struct pinctrl_dev *pctldev,
+ unsigned int pin, unsigned long *config)
+{
+ struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+ u32 param = pinconf_to_config_param(*config);
+ int val, err;
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ err = ocelot_hw_get_value(info, pin, PINCONF_BIAS, &val);
+ if (err)
+ return err;
+ if (param == PIN_CONFIG_BIAS_DISABLE)
+ val = (val == 0 ? true : false);
+ else if (param == PIN_CONFIG_BIAS_PULL_DOWN)
+ val = (val & BIAS_PD_BIT ? true : false);
+ else /* PIN_CONFIG_BIAS_PULL_UP */
+ val = (val & BIAS_PU_BIT ? true : false);
+ break;
+
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ err = ocelot_hw_get_value(info, pin, PINCONF_SCHMITT, &val);
+ if (err)
+ return err;
+
+ val = (val & SCHMITT_BIT ? true : false);
+ break;
+
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ err = ocelot_hw_get_value(info, pin, PINCONF_DRIVE_STRENGTH,
+ &val);
+ if (err)
+ return err;
+ break;
+
+ case PIN_CONFIG_OUTPUT:
+ err = regmap_read(info->map, REG(OCELOT_GPIO_OUT, info, pin),
+ &val);
+ if (err)
+ return err;
+ val = !!(val & BIT(pin % 32));
+ break;
+
+ case PIN_CONFIG_INPUT_ENABLE:
+ case PIN_CONFIG_OUTPUT_ENABLE:
+ err = regmap_read(info->map, REG(OCELOT_GPIO_OE, info, pin),
+ &val);
+ if (err)
+ return err;
+ val = val & BIT(pin % 32);
+ if (param == PIN_CONFIG_OUTPUT_ENABLE)
+ val = !!val;
+ else
+ val = !val;
+ break;
+
+ default:
+ return -ENOTSUPP;
+ }
+
+ *config = pinconf_to_config_packed(param, val);
+
+ return 0;
+}
+
+noinline int ocelot_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+ unsigned long *configs, unsigned int num_configs)
+{
+ struct ocelot_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
+ u32 param, arg, p;
+ int cfg, err = 0;
+
+ for (cfg = 0; cfg < num_configs; cfg++) {
+ param = pinconf_to_config_param(configs[cfg]);
+ arg = pinconf_to_config_argument(configs[cfg]);
+
+ switch (param) {
+ case PIN_CONFIG_BIAS_DISABLE:
+ case PIN_CONFIG_BIAS_PULL_UP:
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
+ (param == PIN_CONFIG_BIAS_PULL_UP) ? BIAS_PU_BIT :
+ BIAS_PD_BIT;
+
+ err = ocelot_hw_set_value(info, pin, PINCONF_BIAS, arg);
+ if (err)
+ goto err;
+
+ break;
+
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ arg = arg ? SCHMITT_BIT : 0;
+ err = ocelot_hw_set_value(info, pin, PINCONF_SCHMITT,
+ arg);
+ if (err)
+ goto err;
+
+ break;
+
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ err = ocelot_hw_set_value(info, pin,
+ PINCONF_DRIVE_STRENGTH,
+ arg);
+ if (err)
+ goto err;
+
+ break;
+
+ case PIN_CONFIG_OUTPUT_ENABLE:
+ case PIN_CONFIG_INPUT_ENABLE:
+ case PIN_CONFIG_OUTPUT:
+ p = pin % 32;
+ if (arg)
+ regmap_write(info->map,
+ REG(OCELOT_GPIO_OUT_SET, info,
+ pin),
+ BIT(p));
+ else
+ regmap_write(info->map,
+ REG(OCELOT_GPIO_OUT_CLR, info,
+ pin),
+ BIT(p));
+ regmap_update_bits(info->map,
+ REG(OCELOT_GPIO_OE, info, pin),
+ BIT(p),
+ param == PIN_CONFIG_INPUT_ENABLE ?
+ 0 : BIT(p));
+ break;
+
+ default:
+ err = -ENOTSUPP;
+ }
+ }
+err:
+ return err;
+}
+
+static const struct pinconf_ops ocelot_confops = {
+ .is_generic = true,
+ .pin_config_get = ocelot_pinconf_get,
+ .pin_config_set = ocelot_pinconf_set,
+ .pin_config_config_dbg_show = pinconf_generic_dump_config,
+};
+
static const struct pinctrl_ops ocelot_pctl_ops = {
.get_groups_count = ocelot_pctl_get_groups_count,
.get_group_name = ocelot_pctl_get_group_name,
@@ -484,6 +887,16 @@ static struct pinctrl_desc jaguar2_desc = {
.owner = THIS_MODULE,
};
+static struct pinctrl_desc sparx5_desc = {
+ .name = "sparx5-pinctrl",
+ .pins = sparx5_pins,
+ .npins = ARRAY_SIZE(sparx5_pins),
+ .pctlops = &ocelot_pctl_ops,
+ .pmxops = &ocelot_pmx_ops,
+ .confops = &ocelot_confops,
+ .owner = THIS_MODULE,
+};
+
static int ocelot_create_group_func_map(struct device *dev,
struct ocelot_pinctrl *info)
{
@@ -511,7 +924,8 @@ static int ocelot_create_group_func_map(struct device *dev,
}
for (i = 0; i < npins; i++)
- info->func[f].groups[i] = info->desc->pins[pins[i]].name;
+ info->func[f].groups[i] =
+ info->desc->pins[pins[i]].name;
}
kfree(pins);
@@ -744,6 +1158,7 @@ static int ocelot_gpiochip_register(struct platform_device *pdev,
static const struct of_device_id ocelot_pinctrl_of_match[] = {
{ .compatible = "mscc,ocelot-pinctrl", .data = &ocelot_desc },
{ .compatible = "mscc,jaguar2-pinctrl", .data = &jaguar2_desc },
+ { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc },
{},
};
@@ -752,6 +1167,7 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct ocelot_pinctrl *info;
void __iomem *base;
+ struct resource *res;
int ret;
struct regmap_config regmap_config = {
.reg_bits = 32,
@@ -773,6 +1189,7 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev)
}
info->stride = 1 + (info->desc->npins - 1) / 32;
+
regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4;
info->map = devm_regmap_init_mmio(dev, base, ®map_config);
@@ -783,6 +1200,16 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev)
dev_set_drvdata(dev, info->map);
info->dev = dev;
+ /* Pinconf registers */
+ if (info->desc->confops) {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ dev_dbg(dev, "Failed to ioremap config registers (no extended pinconf)\n");
+ else
+ info->pincfg = base;
+ }
+
ret = ocelot_pinctrl_register(pdev, info);
if (ret)
return ret;
@@ -791,6 +1218,8 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev)
if (ret)
return ret;
+ dev_info(dev, "driver registered\n");
+
return 0;
}
--
2.26.2
^ permalink raw reply related
* RE: [PATCHv2 10/10] net: eth: altera: update devicetree bindings documentation
From: Ooi, Joyce @ 2020-05-13 13:00 UTC (permalink / raw)
To: Rob Herring
Cc: Thor Thayer, David S . Miller, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org, Westergreen, Dalon, Tan, Ley Foon,
See, Chin Liang, Nguyen, Dinh, devicetree@vger.kernel.org,
Ooi, Joyce
In-Reply-To: <BL0PR11MB3057066ACAE065DC9426FAE3F2BF0@BL0PR11MB3057.namprd11.prod.outlook.com>
> -----Original Message-----
> From: Ooi, Joyce <joyce.ooi@intel.com>
> Sent: Wednesday, May 13, 2020 8:01 PM
> To: Rob Herring <robh@kernel.org>
> Cc: Thor Thayer <thor.thayer@linux.intel.com>; David S . Miller
> <davem@davemloft.net>; netdev@vger.kernel.org; linux-
> kernel@vger.kernel.org; Westergreen, Dalon <dalon.westergreen@intel.com>;
> Tan, Ley Foon <ley.foon.tan@intel.com>; See, Chin Liang
> <chin.liang.see@intel.com>; Nguyen, Dinh <dinh.nguyen@intel.com>;
> devicetree@vger.kernel.org; Ooi, Joyce <joyce.ooi@intel.com>
> Subject: RE: [PATCHv2 10/10] net: eth: altera: update devicetree bindings
> documentation
>
> > -----Original Message-----
> > From: Rob Herring <robh@kernel.org>
> > Sent: Wednesday, May 13, 2020 6:53 AM
> > To: Ooi, Joyce <joyce.ooi@intel.com>
> > Cc: Thor Thayer <thor.thayer@linux.intel.com>; David S . Miller
> > <davem@davemloft.net>; netdev@vger.kernel.org; linux-
> > kernel@vger.kernel.org; Westergreen, Dalon
> > <dalon.westergreen@intel.com>; Tan, Ley Foon <ley.foon.tan@intel.com>;
> > See, Chin Liang <chin.liang.see@intel.com>; Nguyen, Dinh
> > <dinh.nguyen@intel.com>; devicetree@vger.kernel.org
> > Subject: Re: [PATCHv2 10/10] net: eth: altera: update devicetree
> > bindings documentation
> >
> > On Mon, May 04, 2020 at 04:25:58PM +0800, Joyce Ooi wrote:
> > > From: Dalon Westergreen <dalon.westergreen@intel.com>
> > >
> > > Update devicetree bindings documentation to include msgdma
> > > prefetcher and ptp bindings.
> > >
> > > Cc: Rob Herring <robh+dt@kernel.org>
> > > Cc: devicetree@vger.kernel.org
> > > Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
> > > Signed-off-by: Joyce Ooi <joyce.ooi@intel.com>
> > > ---
> > > v2: no change
> > > ---
> > > .../devicetree/bindings/net/altera_tse.txt | 103
> > +++++++++++++++++----
> > > 1 file changed, 84 insertions(+), 19 deletions(-)
> >
> > Reviewed-by: Rob Herring <robh@kernel.org>
> >
> > One nit below.
> >
> > >
> > > diff --git a/Documentation/devicetree/bindings/net/altera_tse.txt
> > > b/Documentation/devicetree/bindings/net/altera_tse.txt
> > > index 0b7d4d3758ea..2f2d12603907 100644
> > > --- a/Documentation/devicetree/bindings/net/altera_tse.txt
> > > +++ b/Documentation/devicetree/bindings/net/altera_tse.txt
> > > @@ -2,53 +2,86 @@
> > >
> > > Required properties:
> > > - compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE,
> > > and
> > should
> > > - be "altr,tse-msgdma-1.0" for the preferred MSGDMA based
> > TSE.
> > > + be "altr,tse-msgdma-1.0" for the preferred MSGDMA based
> > TSE,
> > > + and "altr,tse-msgdma-2.0" for MSGDMA with prefetcher
> > based
> > > + implementations.
> > > ALTR is supported for legacy device trees, but is deprecated.
> > > altr should be used for all new designs.
> > > - reg: Address and length of the register set for the device. It contains
> > > the information of registers in the same order as described by
> > > reg-names
> > > - reg-names: Should contain the reg names
> > > - "control_port": MAC configuration space region
> > > - "tx_csr": xDMA Tx dispatcher control and status space region
> > > - "tx_desc": MSGDMA Tx dispatcher descriptor space region
> > > - "rx_csr" : xDMA Rx dispatcher control and status space region
> > > - "rx_desc": MSGDMA Rx dispatcher descriptor space region
> > > - "rx_resp": MSGDMA Rx dispatcher response space region
> > > - "s1": SGDMA descriptor memory
> > > - interrupts: Should contain the TSE interrupts and it's mode.
> > > - interrupt-names: Should contain the interrupt names
> > > - "rx_irq": xDMA Rx dispatcher interrupt
> > > - "tx_irq": xDMA Tx dispatcher interrupt
> > > + "rx_irq": DMA Rx dispatcher interrupt
> > > + "tx_irq": DMA Tx dispatcher interrupt
> > > - rx-fifo-depth: MAC receive FIFO buffer depth in bytes
> > > - tx-fifo-depth: MAC transmit FIFO buffer depth in bytes
> > > - phy-mode: See ethernet.txt in the same directory.
> > > - phy-handle: See ethernet.txt in the same directory.
> > > - phy-addr: See ethernet.txt in the same directory. A configuration should
> > > include phy-handle or phy-addr.
> > > -- altr,has-supplementary-unicast:
> > > - If present, TSE supports additional unicast addresses.
> > > - Otherwise additional unicast addresses are not supported.
> > > -- altr,has-hash-multicast-filter:
> > > - If present, TSE supports a hash based multicast filter.
> > > - Otherwise, hash-based multicast filtering is not supported.
> > > -
> > > - mdio device tree subnode: When the TSE has a phy connected to its local
> > > mdio, there must be device tree subnode with the following
> > > required properties:
> > > -
> > > - compatible: Must be "altr,tse-mdio".
> > > - #address-cells: Must be <1>.
> > > - #size-cells: Must be <0>.
> > >
> > > For each phy on the mdio bus, there must be a node with the
> > following
> > > fields:
> > > -
> > > - reg: phy id used to communicate to phy.
> > > - device_type: Must be "ethernet-phy".
> > >
> > > The MAC address will be determined using the optional properties
> > > defined in ethernet.txt.
> > >
> > > +- altr,has-supplementary-unicast:
> > > + If present, TSE supports additional unicast addresses.
> > > + Otherwise additional unicast addresses are not supported.
> > > +- altr,has-hash-multicast-filter:
> > > + If present, TSE supports a hash based multicast filter.
> > > + Otherwise, hash-based multicast filtering is not supported.
> > > +- altr,has-ptp:
> > > + If present, TSE supports 1588 timestamping. Currently only
> > > + supported with the msgdma prefetcher.
> > > +- altr,tx-poll-cnt:
> > > + Optional cycle count for Tx prefetcher to poll descriptor
> > > + list. If not present, defaults to 128, which at 125MHz is
> > > + roughly 1usec. Only for "altr,tse-msgdma-2.0".
> > > +- altr,rx-poll-cnt:
> > > + Optional cycle count for Tx prefetcher to poll descriptor
> > > + list. If not present, defaults to 128, which at 125MHz is
> > > + roughly 1usec. Only for "altr,tse-msgdma-2.0".
> > > +
> > > +Required registers by compatibility string:
> > > + - "altr,tse-1.0"
> > > + "control_port": MAC configuration space region
> > > + "tx_csr": DMA Tx dispatcher control and status space region
> > > + "rx_csr" : DMA Rx dispatcher control and status space region
> > > + "s1": DMA descriptor memory
> > > +
> > > + - "altr,tse-msgdma-1.0"
> > > + "control_port": MAC configuration space region
> > > + "tx_csr": DMA Tx dispatcher control and status space region
> > > + "tx_desc": DMA Tx dispatcher descriptor space region
> > > + "rx_csr" : DMA Rx dispatcher control and status space region
> > > + "rx_desc": DMA Rx dispatcher descriptor space region
> > > + "rx_resp": DMA Rx dispatcher response space region
> > > +
> > > + - "altr,tse-msgdma-2.0"
> > > + "control_port": MAC configuration space region
> > > + "tx_csr": DMA Tx dispatcher control and status space region
> > > + "tx_pref": DMA Tx prefetcher configuration space region
> > > + "rx_csr" : DMA Rx dispatcher control and status space region
> > > + "rx_pref": DMA Rx prefetcher configuration space region
> > > + "tod_ctrl": Time of Day Control register only required when
> > > + timestamping support is enabled. Timestamping is
> > > + only supported with the msgdma-2.0
> > implementation.
> > > +
> > > +Optional properties:
> > > +- local-mac-address: See ethernet.txt in the same directory.
> > > +- max-frame-size: See ethernet.txt in the same directory.
> > > +
> > > Example:
> > >
> > > tse_sub_0_eth_tse_0: ethernet@1,00000000 { @@ -86,6 +119,11
> > @@
> > > Example:
> > > device_type = "ethernet-phy";
> > > };
> > >
> > > + phy2: ethernet-phy@2 {
> > > + reg = <0x2>;
> > > + device_type = "ethernet-phy";
> > > + };
> > > +
> > > };
> > > };
> > >
> > > @@ -111,3 +149,30 @@ Example:
> > > altr,has-hash-multicast-filter;
> > > phy-handle = <&phy1>;
> > > };
> > > +
> > > +
> > > + tse_sub_2_eth_tse_0: ethernet@1,00002000 {
> >
> > What bus is this on? Usually a ',' like this is for a chip select
> > number. If just a 64-bit address, then no comma.
>
> It's a 64-bit address. I'll remove the comma for this and the one above.
Found out that the comma is actually for a chip select. It was an old way of sending between the lightweight bridge and main brigde to the FPGA.
> >
> > > + compatible = "altr,tse-msgdma-2.0";
> > > + reg = <0x00000001 0x00002000 0x00000400>,
> > > + <0x00000001 0x00002400 0x00000020>,
> > > + <0x00000001 0x00002420 0x00000020>,
> > > + <0x00000001 0x00002440 0x00000020>,
> > > + <0x00000001 0x00002460 0x00000020>,
> > > + <0x00000001 0x00002480 0x00000040>;
> > > + reg-names = "control_port", "rx_csr", "rx_pref","tx_csr",
> > "tx_pref", "tod_ctrl";
> > > + interrupt-parent = <&hps_0_arm_gic_0>;
> > > + interrupts = <0 45 4>, <0 44 4>;
> > > + interrupt-names = "rx_irq", "tx_irq";
> > > + rx-fifo-depth = <2048>;
> > > + tx-fifo-depth = <2048>;
> > > + address-bits = <48>;
> > > + max-frame-size = <1500>;
> > > + local-mac-address = [ 00 00 00 00 00 00 ];
> > > + phy-mode = "sgmii";
> > > + altr,has-supplementary-unicast;
> > > + altr,has-hash-multicast-filter;
> > > + altr,has-ptp;
> > > + altr,tx-poll-cnt = <128>;
> > > + altr,rx-poll-cnt = <32>;
> > > + phy-handle = <&phy2>;
> > > + };
> > > --
> > > 2.13.0
> > >
^ permalink raw reply
* Re: [PATCH 1/5] spi: dt-bindings: sifive: Add missing 2nd register region
From: Rob Herring @ 2020-05-13 13:02 UTC (permalink / raw)
To: Mark Brown
Cc: devicetree, Paul Walmsley, Linux USB List,
linux-kernel@vger.kernel.org, Palmer Dabbelt, linux-riscv,
Greg Kroah-Hartman, linux-spi, linux-clk
In-Reply-To: <158937185132.39109.17103954100758193517.b4-ty@kernel.org>
On Wed, May 13, 2020 at 7:10 AM Mark Brown <broonie@kernel.org> wrote:
>
> On Tue, 12 May 2020 15:45:39 -0500, Rob Herring wrote:
> > The 'reg' description and example have a 2nd register region for memory
> > mapped flash, but the schema says there is only 1 region. Fix this.
>
> Applied to
>
> https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-5.8
>
> Thanks!
>
> [1/1] spi: dt-bindings: sifive: Add missing 2nd register region
> commit: b265b5a0ba15b6e00abce9bf162926e84b4323b4
You missed my ask for an ack. This is a dependency for patch 5.
Rob
^ permalink raw reply
* [PATCH 0/3] usb: dwc3: keystone: Convert binding to YAML
From: Roger Quadros @ 2020-05-13 13:07 UTC (permalink / raw)
To: balbi; +Cc: robh+dt, vigneshr, linux-usb, devicetree, linux-kernel,
Roger Quadros
Hi Felipe,
This series converts keystone-usb.txt to YAML and prepares
for Super-Speed support for AM654 SoC.
cheers,
-roger
Roger Quadros (3):
dt-bindings: usb: convert keystone-usb.txt to YAML
dt-bindings: usb: ti,keystone-dwc3.yaml: Add USB3.0 PHY property
usb: dwc3: keystone: Turn on USB3 PHY before controller
.../devicetree/bindings/usb/keystone-usb.txt | 56 ------------
.../bindings/usb/ti,keystone-dwc3.yaml | 88 +++++++++++++++++++
drivers/usb/dwc3/dwc3-keystone.c | 47 +++++++++-
3 files changed, 134 insertions(+), 57 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/usb/keystone-usb.txt
create mode 100644 Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply
* [PATCH 1/3] dt-bindings: usb: convert keystone-usb.txt to YAML
From: Roger Quadros @ 2020-05-13 13:07 UTC (permalink / raw)
To: balbi; +Cc: robh+dt, vigneshr, linux-usb, devicetree, linux-kernel,
Roger Quadros
In-Reply-To: <20200513130709.10239-1-rogerq@ti.com>
Convert keystone-usb documentation to YAML format.
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
.../devicetree/bindings/usb/keystone-usb.txt | 56 ----------------
.../bindings/usb/ti,keystone-dwc3.yaml | 67 +++++++++++++++++++
2 files changed, 67 insertions(+), 56 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/usb/keystone-usb.txt
create mode 100644 Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml
diff --git a/Documentation/devicetree/bindings/usb/keystone-usb.txt b/Documentation/devicetree/bindings/usb/keystone-usb.txt
deleted file mode 100644
index 77df82e36138..000000000000
--- a/Documentation/devicetree/bindings/usb/keystone-usb.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-TI Keystone Soc USB Controller
-
-DWC3 GLUE
-
-Required properties:
- - compatible: should be
- "ti,keystone-dwc3" for Keystone 2 SoCs
- "ti,am654-dwc3" for AM654 SoC
- - #address-cells, #size-cells : should be '1' if the device has sub-nodes
- with 'reg' property.
- - reg : Address and length of the register set for the USB subsystem on
- the SOC.
- - interrupts : The irq number of this device that is used to interrupt the
- MPU.
- - ranges: allows valid 1:1 translation between child's address space and
- parent's address space.
-
-SoC-specific Required Properties:
-The following are mandatory properties for Keystone 2 66AK2HK, 66AK2L and 66AK2E
-SoCs only:
-
-- clocks: Clock ID for USB functional clock.
-- clock-names: Must be "usb".
-
-
-The following are mandatory properties for 66AK2G and AM654:
-
-- power-domains: Should contain a phandle to a PM domain provider node
- and an args specifier containing the USB device id
- value. This property is as per the binding,
- Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
-
-Sub-nodes:
-The dwc3 core should be added as subnode to Keystone DWC3 glue.
-- dwc3 :
- The binding details of dwc3 can be found in:
- Documentation/devicetree/bindings/usb/dwc3.txt
-
-Example:
- usb: usb@2680000 {
- compatible = "ti,keystone-dwc3";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x2680000 0x10000>;
- clocks = <&clkusb>;
- clock-names = "usb";
- interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
- ranges;
-
- dwc3@2690000 {
- compatible = "synopsys,dwc3";
- reg = <0x2690000 0x70000>;
- interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
- usb-phy = <&usb_phy>, <&usb_phy>;
- };
- };
diff --git a/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml b/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml
new file mode 100644
index 000000000000..14d2fe329b93
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml
@@ -0,0 +1,67 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/ti,keystone-dwc3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI Keystone Soc USB Controller
+
+maintainers:
+ - Roger Quadros <rogerq@ti.com>
+
+properties:
+ compatible:
+ oneOf:
+ - const: "ti,keystone-dwc3"
+ - const: "ti,am654-dwc3"
+
+ reg:
+ maxItems: 1
+ description: Address and length of the register set for the USB subsystem on
+ the SOC.
+
+ interrupts:
+ maxItems: 1
+ description: The irq number of this device that is used to interrupt the MPU.
+
+
+ clocks:
+ description: Clock ID for USB functional clock.
+
+ power-domains:
+ description: Should contain a phandle to a PM domain provider node
+ and an args specifier containing the USB device id
+ value. This property is as per the binding,
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+
+ dwc3:
+ description: This is the node representing the DWC3 controller instance
+ Documentation/devicetree/bindings/usb/dwc3.txt
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ usb: usb@2680000 {
+ compatible = "ti,keystone-dwc3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x2680000 0x10000>;
+ clocks = <&clkusb>;
+ clock-names = "usb";
+ interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
+ ranges;
+
+ dwc3@2690000 {
+ compatible = "synopsys,dwc3";
+ reg = <0x2690000 0x70000>;
+ interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
+ usb-phy = <&usb_phy>, <&usb_phy>;
+ };
+ };
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related
* [PATCH 3/3] usb: dwc3: keystone: Turn on USB3 PHY before controller
From: Roger Quadros @ 2020-05-13 13:07 UTC (permalink / raw)
To: balbi; +Cc: robh+dt, vigneshr, linux-usb, devicetree, linux-kernel,
Roger Quadros
In-Reply-To: <20200513130709.10239-1-rogerq@ti.com>
The Local Power Sleep Controller (LPSC) dependency on AM65
requires SERDES0 to be powered on before USB.
We need to power up SERDES0 power domain and hold it on
throughout the reset, init, power on sequence.
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
drivers/usb/dwc3/dwc3-keystone.c | 47 +++++++++++++++++++++++++++++++-
1 file changed, 46 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/dwc3-keystone.c b/drivers/usb/dwc3/dwc3-keystone.c
index 1e14a6f4884b..46d46f3507fc 100644
--- a/drivers/usb/dwc3/dwc3-keystone.c
+++ b/drivers/usb/dwc3/dwc3-keystone.c
@@ -14,6 +14,7 @@
#include <linux/dma-mapping.h>
#include <linux/io.h>
#include <linux/of_platform.h>
+#include <linux/phy/phy.h>
#include <linux/pm_runtime.h>
/* USBSS register offsets */
@@ -34,6 +35,7 @@
struct dwc3_keystone {
struct device *dev;
void __iomem *usbss;
+ struct phy *usb3_phy;
};
static inline u32 kdwc3_readl(void __iomem *base, u32 offset)
@@ -95,8 +97,44 @@ static int kdwc3_probe(struct platform_device *pdev)
if (IS_ERR(kdwc->usbss))
return PTR_ERR(kdwc->usbss);
- pm_runtime_enable(kdwc->dev);
+ /* PSC dependency on AM65 needs SERDES0 to be powered before USB0 */
+ kdwc->usb3_phy = devm_phy_get(dev, "usb3-phy");
+ if (IS_ERR(kdwc->usb3_phy)) {
+ error = PTR_ERR(kdwc->usb3_phy);
+ if (error == -ENOSYS || error == -ENODEV) {
+ kdwc->usb3_phy = NULL;
+ } else {
+ if (error != -EPROBE_DEFER) {
+ dev_err(dev, "couldn't get usb3 phy: %d\n",
+ error);
+ }
+
+ return error;
+ }
+ }
+
+ phy_pm_runtime_get_sync(kdwc->usb3_phy);
+
+ error = phy_reset(kdwc->usb3_phy);
+ if (error < 0) {
+ dev_err(dev, "usb3 phy reset failed: %d\n", error);
+ return error;
+ }
+
+ error = phy_init(kdwc->usb3_phy);
+ if (error < 0) {
+ dev_err(dev, "usb3 phy init failed: %d\n", error);
+ return error;
+ }
+ error = phy_power_on(kdwc->usb3_phy);
+ if (error < 0) {
+ dev_err(dev, "usb3 phy power on failed: %d\n", error);
+ phy_exit(kdwc->usb3_phy);
+ return error;
+ }
+
+ pm_runtime_enable(kdwc->dev);
error = pm_runtime_get_sync(kdwc->dev);
if (error < 0) {
dev_err(kdwc->dev, "pm_runtime_get_sync failed, error %d\n",
@@ -138,6 +176,9 @@ static int kdwc3_probe(struct platform_device *pdev)
err_irq:
pm_runtime_put_sync(kdwc->dev);
pm_runtime_disable(kdwc->dev);
+ phy_power_off(kdwc->usb3_phy);
+ phy_exit(kdwc->usb3_phy);
+ phy_pm_runtime_put_sync(kdwc->usb3_phy);
return error;
}
@@ -163,6 +204,10 @@ static int kdwc3_remove(struct platform_device *pdev)
pm_runtime_put_sync(kdwc->dev);
pm_runtime_disable(kdwc->dev);
+ phy_power_off(kdwc->usb3_phy);
+ phy_exit(kdwc->usb3_phy);
+ phy_pm_runtime_put_sync(kdwc->usb3_phy);
+
platform_set_drvdata(pdev, NULL);
return 0;
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related
* [PATCH 2/3] dt-bindings: usb: ti,keystone-dwc3.yaml: Add USB3.0 PHY property
From: Roger Quadros @ 2020-05-13 13:07 UTC (permalink / raw)
To: balbi; +Cc: robh+dt, vigneshr, linux-usb, devicetree, linux-kernel,
Roger Quadros
In-Reply-To: <20200513130709.10239-1-rogerq@ti.com>
AM654 SoC requires USB3.0 PHY to be turned on before the USB controller.
For this SoC, the 'phys' property is used to provide the USB3.0
reference.
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
.../bindings/usb/ti,keystone-dwc3.yaml | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml b/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml
index 14d2fe329b93..51c0ab01b0bc 100644
--- a/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml
@@ -34,6 +34,16 @@ properties:
value. This property is as per the binding,
Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+ phys:
+ description:
+ PHY specifier for the USB3.0 PHY. Some SoCs need the USB3.0 PHY
+ to be turned on before the controller.
+ Documentation/devicetree/bindings/phy/phy-bindings.txt
+
+ phy-names:
+ items:
+ - const: "usb3-phy"
+
dwc3:
description: This is the node representing the DWC3 controller instance
Documentation/devicetree/bindings/usb/dwc3.txt
@@ -44,6 +54,17 @@ required:
- interrupts
- clocks
+if:
+ properties:
+ compatible:
+ contains:
+ const: "ti,am654-dwc3"
+
+then:
+ required:
+ - phys
+ - phy-names
+
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply related
* [PATCH 0/5] power: Adding support for Microchip Sparx5 SoC
From: Lars Povlsen @ 2020-05-13 13:08 UTC (permalink / raw)
To: Sebastian Reichel, SoC Team
Cc: Lars Povlsen, Alexandre Belloni, Microchip Linux Driver Support,
linux-pm, devicetree, linux-kernel, linux-arm-kernel
This is an add-on series to the main SoC Sparx5 series
(Message-ID: <20200513125532.24585-1-lars.povlsen@microchip.com>).
It adds reset support for Sparx5, using the ocelot reset driver.
It is expected that the DT patches are to be taken directly by the arm-soc
maintainers.
Lars Povlsen (5):
dt-bindings: reset: ocelot: Add Sparx5 support
power: reset: ocelot: Add support for Sparx5
dt-bindings: reset: ocelot: Add documentation for
'microchip,reset-switch-core' property
power: reset: ocelot: Add support for reset switch on load time
arm64: dts: sparx5: Add reset support
.../bindings/power/reset/ocelot-reset.txt | 13 ++-
MAINTAINERS | 1 +
arch/arm64/boot/dts/microchip/sparx5.dtsi | 11 +++
drivers/power/reset/Kconfig | 3 +-
drivers/power/reset/ocelot-reset.c | 95 ++++++++++++++++---
5 files changed, 105 insertions(+), 18 deletions(-)
--
2.26.2
^ permalink raw reply
* [PATCH 1/5] dt-bindings: reset: ocelot: Add Sparx5 support
From: Lars Povlsen @ 2020-05-13 13:08 UTC (permalink / raw)
To: Sebastian Reichel, SoC Team, Rob Herring
Cc: Lars Povlsen, Alexandre Belloni, Microchip Linux Driver Support,
linux-pm, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20200513130842.24847-1-lars.povlsen@microchip.com>
This adds the support for the Sparx5 SoC.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
.../devicetree/bindings/power/reset/ocelot-reset.txt | 7 +++++--
MAINTAINERS | 1 +
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
index 1b4213eb34731..4d530d8154848 100644
--- a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
+++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
@@ -1,10 +1,13 @@
Microsemi Ocelot reset controller
The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
-SoC MIPS core.
+SoC core.
+
+The reset registers are both present in the MSCC vcoreiii MIPS and
+microchip Sparx5 armv8 SoC's.
Required Properties:
- - compatible: "mscc,ocelot-chip-reset"
+ - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset"
Example:
reset@1070008 {
diff --git a/MAINTAINERS b/MAINTAINERS
index 5aa28d6e39d4f..1db598723a1d8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11230,6 +11230,7 @@ M: Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
L: linux-mips@vger.kernel.org
S: Supported
F: Documentation/devicetree/bindings/mips/mscc.txt
+F: Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
F: arch/mips/boot/dts/mscc/
F: arch/mips/configs/generic/board-ocelot.config
F: arch/mips/generic/board-ocelot.c
--
2.26.2
^ permalink raw reply related
* [PATCH 2/5] power: reset: ocelot: Add support for Sparx5
From: Lars Povlsen @ 2020-05-13 13:08 UTC (permalink / raw)
To: Sebastian Reichel, SoC Team
Cc: Lars Povlsen, Alexandre Belloni, Microchip Linux Driver Support,
linux-pm, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20200513130842.24847-1-lars.povlsen@microchip.com>
This adds reset support for Sparx5 in the ocelot-reset driver.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
drivers/power/reset/Kconfig | 3 +-
drivers/power/reset/ocelot-reset.c | 55 +++++++++++++++++++++++-------
2 files changed, 44 insertions(+), 14 deletions(-)
diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig
index 8903803020805..9ecafbf9e64a6 100644
--- a/drivers/power/reset/Kconfig
+++ b/drivers/power/reset/Kconfig
@@ -118,10 +118,9 @@ config POWER_RESET_QCOM_PON
config POWER_RESET_OCELOT_RESET
bool "Microsemi Ocelot reset driver"
- depends on MSCC_OCELOT || COMPILE_TEST
select MFD_SYSCON
help
- This driver supports restart for Microsemi Ocelot SoC.
+ This driver supports restart for Microsemi Ocelot SoC and similar.
config POWER_RESET_PIIX4_POWEROFF
tristate "Intel PIIX4 power-off driver"
diff --git a/drivers/power/reset/ocelot-reset.c b/drivers/power/reset/ocelot-reset.c
index 419952c61fd01..f74e1dbb4ba36 100644
--- a/drivers/power/reset/ocelot-reset.c
+++ b/drivers/power/reset/ocelot-reset.c
@@ -15,15 +15,20 @@
#include <linux/reboot.h>
#include <linux/regmap.h>
+struct reset_props {
+ const char *syscon;
+ u32 protect_reg;
+ u32 vcore_protect;
+ u32 if_si_owner_bit;
+};
+
struct ocelot_reset_context {
void __iomem *base;
struct regmap *cpu_ctrl;
+ const struct reset_props *props;
struct notifier_block restart_handler;
};
-#define ICPU_CFG_CPU_SYSTEM_CTRL_RESET 0x20
-#define CORE_RST_PROTECT BIT(2)
-
#define SOFT_CHIP_RST BIT(0)
#define ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
@@ -31,7 +36,6 @@ struct ocelot_reset_context {
#define IF_SI_OWNER_SISL 0
#define IF_SI_OWNER_SIBM 1
#define IF_SI_OWNER_SIMC 2
-#define IF_SI_OWNER_OFFSET 4
static int ocelot_restart_handle(struct notifier_block *this,
unsigned long mode, void *cmd)
@@ -39,15 +43,18 @@ static int ocelot_restart_handle(struct notifier_block *this,
struct ocelot_reset_context *ctx = container_of(this, struct
ocelot_reset_context,
restart_handler);
+ u32 if_si_owner_bit = ctx->props->if_si_owner_bit;
/* Make sure the core is not protected from reset */
- regmap_update_bits(ctx->cpu_ctrl, ICPU_CFG_CPU_SYSTEM_CTRL_RESET,
- CORE_RST_PROTECT, 0);
+ regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg,
+ ctx->props->vcore_protect, 0);
/* Make the SI back to boot mode */
regmap_update_bits(ctx->cpu_ctrl, ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL,
- IF_SI_OWNER_MASK << IF_SI_OWNER_OFFSET,
- IF_SI_OWNER_SIBM << IF_SI_OWNER_OFFSET);
+ IF_SI_OWNER_MASK << if_si_owner_bit,
+ IF_SI_OWNER_SIBM << if_si_owner_bit);
+
+ pr_emerg("Resetting SoC\n");
writel(SOFT_CHIP_RST, ctx->base);
@@ -72,9 +79,13 @@ static int ocelot_reset_probe(struct platform_device *pdev)
if (IS_ERR(ctx->base))
return PTR_ERR(ctx->base);
- ctx->cpu_ctrl = syscon_regmap_lookup_by_compatible("mscc,ocelot-cpu-syscon");
- if (IS_ERR(ctx->cpu_ctrl))
+ ctx->props = device_get_match_data(dev);
+
+ ctx->cpu_ctrl = syscon_regmap_lookup_by_compatible(ctx->props->syscon);
+ if (IS_ERR(ctx->cpu_ctrl)) {
+ dev_err(dev, "No syscon map: %s\n", ctx->props->syscon);
return PTR_ERR(ctx->cpu_ctrl);
+ }
ctx->restart_handler.notifier_call = ocelot_restart_handle;
ctx->restart_handler.priority = 192;
@@ -85,9 +96,29 @@ static int ocelot_reset_probe(struct platform_device *pdev)
return err;
}
+static const struct reset_props reset_props_ocelot = {
+ .syscon = "mscc,ocelot-cpu-syscon",
+ .protect_reg = 0x20,
+ .vcore_protect = BIT(2),
+ .if_si_owner_bit = 4,
+};
+
+static const struct reset_props reset_props_sparx5 = {
+ .syscon = "microchip,sparx5-cpu-syscon",
+ .protect_reg = 0x84,
+ .vcore_protect = BIT(10),
+ .if_si_owner_bit = 6,
+};
+
static const struct of_device_id ocelot_reset_of_match[] = {
- { .compatible = "mscc,ocelot-chip-reset" },
- {}
+ {
+ .compatible = "mscc,ocelot-chip-reset",
+ .data = &reset_props_ocelot
+ }, {
+ .compatible = "microchip,sparx5-chip-reset",
+ .data = &reset_props_sparx5
+ },
+ { /*sentinel*/ }
};
static struct platform_driver ocelot_reset_driver = {
--
2.26.2
^ permalink raw reply related
* [PATCH 5/5] arm64: dts: sparx5: Add reset support
From: Lars Povlsen @ 2020-05-13 13:08 UTC (permalink / raw)
To: Sebastian Reichel, SoC Team
Cc: Lars Povlsen, Alexandre Belloni, Microchip Linux Driver Support,
linux-pm, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20200513130842.24847-1-lars.povlsen@microchip.com>
This adds reset support to the Sparx5 SoC
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index b5cb3d8dc876b..3e94ac9e7dd51 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -106,6 +106,17 @@ gic: interrupt-controller@600300000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
+ cpu_ctrl: syscon@600000000 {
+ compatible = "microchip,sparx5-cpu-syscon", "syscon";
+ reg = <0x6 0x00000000 0xd0>;
+ };
+
+ reset@611010008 {
+ compatible = "microchip,sparx5-chip-reset";
+ reg = <0x6 0x11010008 0x4>;
+ microchip,reset-switch-core;
+ };
+
uart0: serial@600100000 {
pinctrl-0 = <&uart_pins>;
pinctrl-names = "default";
--
2.26.2
^ permalink raw reply related
* [PATCH 4/5] power: reset: ocelot: Add support for reset switch on load time
From: Lars Povlsen @ 2020-05-13 13:08 UTC (permalink / raw)
To: Sebastian Reichel, SoC Team
Cc: Lars Povlsen, Alexandre Belloni, Microchip Linux Driver Support,
linux-pm, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20200513130842.24847-1-lars.povlsen@microchip.com>
This patch add support for resetting the networking switch core at
reset driver load time. It is useful in order to bring the switch core
in a known state after a reboot or after a bootloader may have been
using the switch for network access.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
drivers/power/reset/ocelot-reset.c | 40 ++++++++++++++++++++++++++++--
1 file changed, 38 insertions(+), 2 deletions(-)
diff --git a/drivers/power/reset/ocelot-reset.c b/drivers/power/reset/ocelot-reset.c
index f74e1dbb4ba36..a203c42e99d42 100644
--- a/drivers/power/reset/ocelot-reset.c
+++ b/drivers/power/reset/ocelot-reset.c
@@ -29,6 +29,7 @@ struct ocelot_reset_context {
struct notifier_block restart_handler;
};
+#define SOFT_SWC_RST BIT(1)
#define SOFT_CHIP_RST BIT(0)
#define ICPU_CFG_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
@@ -37,6 +38,32 @@ struct ocelot_reset_context {
#define IF_SI_OWNER_SIBM 1
#define IF_SI_OWNER_SIMC 2
+static int ocelot_switch_core_reset(const struct ocelot_reset_context *ctx)
+{
+
+ const char *driver = "ocelot-reset";
+ int timeout;
+
+ pr_notice("%s: Resetting Switch Core\n", driver);
+
+ /* Make sure the core is PROTECTED from reset */
+ regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg,
+ ctx->props->vcore_protect,
+ ctx->props->vcore_protect);
+
+ writel(SOFT_SWC_RST, ctx->base);
+ for (timeout = 0; timeout < 100; timeout++) {
+ if ((readl(ctx->base) & SOFT_SWC_RST) == 0) {
+ pr_debug("%s: Switch Core Reset complete.\n", driver);
+ return 0;
+ }
+ udelay(1);
+ }
+
+ pr_warn("%s: Switch Core Reset timeout!\n", driver);
+ return -ENXIO;
+}
+
static int ocelot_restart_handle(struct notifier_block *this,
unsigned long mode, void *cmd)
{
@@ -66,7 +93,6 @@ static int ocelot_reset_probe(struct platform_device *pdev)
{
struct ocelot_reset_context *ctx;
struct resource *res;
-
struct device *dev = &pdev->dev;
int err;
@@ -87,6 +113,11 @@ static int ocelot_reset_probe(struct platform_device *pdev)
return PTR_ERR(ctx->cpu_ctrl);
}
+ /* Optionally, call switch reset function */
+ if (of_property_read_bool(pdev->dev.of_node,
+ "microchip,reset-switch-core"))
+ ocelot_switch_core_reset(ctx);
+
ctx->restart_handler.notifier_call = ocelot_restart_handle;
ctx->restart_handler.priority = 192;
err = register_restart_handler(&ctx->restart_handler);
@@ -128,4 +159,9 @@ static struct platform_driver ocelot_reset_driver = {
.of_match_table = ocelot_reset_of_match,
},
};
-builtin_platform_driver(ocelot_reset_driver);
+
+static int __init reset_init(void)
+{
+ return platform_driver_register(&ocelot_reset_driver);
+}
+postcore_initcall(reset_init);
--
2.26.2
^ permalink raw reply related
* [PATCH 3/5] dt-bindings: reset: ocelot: Add documentation for 'microchip,reset-switch-core' property
From: Lars Povlsen @ 2020-05-13 13:08 UTC (permalink / raw)
To: Sebastian Reichel, SoC Team, Rob Herring
Cc: Lars Povlsen, Alexandre Belloni, Microchip Linux Driver Support,
linux-pm, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <20200513130842.24847-1-lars.povlsen@microchip.com>
This documents the 'microchip,reset-switch-core' property in the
ocelot-reset driver.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
.../devicetree/bindings/power/reset/ocelot-reset.txt | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
index 4d530d8154848..20fff03753ad2 100644
--- a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
+++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
@@ -9,9 +9,15 @@ microchip Sparx5 armv8 SoC's.
Required Properties:
- compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset"
+Optional properties:
+- microchip,reset-switch-core : Perform a switch core reset at the
+ time of driver load. This is may be used to initialize the switch
+ core to a known state (before other drivers are loaded).
+
Example:
reset@1070008 {
compatible = "mscc,ocelot-chip-reset";
reg = <0x1070008 0x4>;
+ microchip,reset-switch-core;
};
--
2.26.2
^ permalink raw reply related
* [PATCH v8 0/6] Add support for the X1830 and fix bugs for X1000
From: 周琰杰 (Zhou Yanjie) @ 2020-05-13 13:16 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, devicetree, robh+dt, mturquette, sboyd, paul,
dongsheng.qiu, yanfei.li, sernia.zhou, zhenwenjin
In-Reply-To: <1589375804-78423-1-git-send-email-zhouyanjie@wanyeetech.com>
v7->v8:
1.Rebase [3/6] on top of linux-next, because "ingenic,cgu.txt" has
been converted to "ingenic,cgu.yaml".
周琰杰 (Zhou Yanjie) (6):
clk: Ingenic: Remove unnecessary spinlock when reading registers.
clk: Ingenic: Adjust cgu code to make it compatible with X1830.
dt-bindings: clock: Add X1830 bindings.
clk: Ingenic: Add CGU driver for X1830.
dt-bindings: clock: Add and reorder ABI for X1000.
clk: X1000: Add FIXDIV for SSI clock of X1000.
.../devicetree/bindings/clock/ingenic,cgu.yaml | 2 +
drivers/clk/ingenic/Kconfig | 10 +
drivers/clk/ingenic/Makefile | 1 +
drivers/clk/ingenic/cgu.c | 28 +-
drivers/clk/ingenic/cgu.h | 4 +
drivers/clk/ingenic/jz4725b-cgu.c | 4 +
drivers/clk/ingenic/jz4740-cgu.c | 4 +
drivers/clk/ingenic/jz4770-cgu.c | 8 +-
drivers/clk/ingenic/jz4780-cgu.c | 3 +
drivers/clk/ingenic/x1000-cgu.c | 62 +++-
drivers/clk/ingenic/x1830-cgu.c | 388 +++++++++++++++++++++
include/dt-bindings/clock/x1000-cgu.h | 62 ++--
include/dt-bindings/clock/x1830-cgu.h | 53 +++
13 files changed, 580 insertions(+), 49 deletions(-)
create mode 100644 drivers/clk/ingenic/x1830-cgu.c
create mode 100644 include/dt-bindings/clock/x1830-cgu.h
--
2.7.4
^ permalink raw reply
* Add support for the X1830 and fix bugs for X1000 v8.
From: 周琰杰 (Zhou Yanjie) @ 2020-05-13 13:16 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, devicetree, robh+dt, mturquette, sboyd, paul,
dongsheng.qiu, yanfei.li, sernia.zhou, zhenwenjin
v7->v8:
1.Rebase [3/6] on top of linux-next, because "ingenic,cgu.txt" has
been converted to "ingenic,cgu.yaml".
^ permalink raw reply
* [PATCH v8 3/6] dt-bindings: clock: Add X1830 bindings.
From: 周琰杰 (Zhou Yanjie) @ 2020-05-13 13:16 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, devicetree, robh+dt, mturquette, sboyd, paul,
dongsheng.qiu, yanfei.li, sernia.zhou, zhenwenjin
In-Reply-To: <1589375804-78423-1-git-send-email-zhouyanjie@wanyeetech.com>
Add the clock bindings for the X1830 Soc from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Notes:
v1->v2:
Change my Signed-off-by from "Zhou Yanjie <zhouyanjie@zoho.com>"
to "周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>" because
the old mailbox is in an unstable state.
v2->v3:
Adjust order from [3/5] in v2 to [4/5] in v3.
v3->v4:
Adjust order from [4/5] in v3 to [3/4] in v4.
v4->v5:
Rebase on top of kernel 5.6-rc1.
v5->v6:
Add missing part of X1830's CGU.
v6->v7:
No change.
v7->v8:
Rebase on top of linux-next.
.../devicetree/bindings/clock/ingenic,cgu.yaml | 2 +
include/dt-bindings/clock/x1830-cgu.h | 53 ++++++++++++++++++++++
2 files changed, 55 insertions(+)
create mode 100644 include/dt-bindings/clock/x1830-cgu.h
diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml
index 0281cd1..a952d58 100644
--- a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml
+++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml
@@ -25,6 +25,7 @@ select:
- ingenic,jz4770-cgu
- ingenic,jz4780-cgu
- ingenic,x1000-cgu
+ - ingenic,x1830-cgu
required:
- compatible
@@ -51,6 +52,7 @@ properties:
- ingenic,jz4770-cgu
- ingenic,jz4780-cgu
- ingenic,x1000-cgu
+ - ingenic,x1830-cgu
- const: simple-mfd
minItems: 1
diff --git a/include/dt-bindings/clock/x1830-cgu.h b/include/dt-bindings/clock/x1830-cgu.h
new file mode 100644
index 00000000..f605a7b
--- /dev/null
+++ b/include/dt-bindings/clock/x1830-cgu.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides clock numbers for the ingenic,x1830-cgu DT binding.
+ *
+ * They are roughly ordered as:
+ * - external clocks
+ * - PLLs
+ * - muxes/dividers in the order they appear in the x1830 programmers manual
+ * - gates in order of their bit in the CLKGR* registers
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__
+#define __DT_BINDINGS_CLOCK_X1830_CGU_H__
+
+#define X1830_CLK_EXCLK 0
+#define X1830_CLK_RTCLK 1
+#define X1830_CLK_APLL 2
+#define X1830_CLK_MPLL 3
+#define X1830_CLK_EPLL 4
+#define X1830_CLK_VPLL 5
+#define X1830_CLK_SCLKA 6
+#define X1830_CLK_CPUMUX 7
+#define X1830_CLK_CPU 8
+#define X1830_CLK_L2CACHE 9
+#define X1830_CLK_AHB0 10
+#define X1830_CLK_AHB2PMUX 11
+#define X1830_CLK_AHB2 12
+#define X1830_CLK_PCLK 13
+#define X1830_CLK_DDR 14
+#define X1830_CLK_MAC 15
+#define X1830_CLK_LCD 16
+#define X1830_CLK_MSCMUX 17
+#define X1830_CLK_MSC0 18
+#define X1830_CLK_MSC1 19
+#define X1830_CLK_SSIPLL 20
+#define X1830_CLK_SSIPLL_DIV2 21
+#define X1830_CLK_SSIMUX 22
+#define X1830_CLK_EMC 23
+#define X1830_CLK_EFUSE 24
+#define X1830_CLK_OTG 25
+#define X1830_CLK_SSI0 26
+#define X1830_CLK_SMB0 27
+#define X1830_CLK_SMB1 28
+#define X1830_CLK_SMB2 29
+#define X1830_CLK_UART0 30
+#define X1830_CLK_UART1 31
+#define X1830_CLK_SSI1 32
+#define X1830_CLK_SFC 33
+#define X1830_CLK_PDMA 34
+#define X1830_CLK_DTRNG 35
+#define X1830_CLK_OST 36
+
+#endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */
--
2.7.4
^ permalink raw reply related
* [PATCH v8 6/6] clk: X1000: Add FIXDIV for SSI clock of X1000.
From: 周琰杰 (Zhou Yanjie) @ 2020-05-13 13:16 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, devicetree, robh+dt, mturquette, sboyd, paul,
dongsheng.qiu, yanfei.li, sernia.zhou, zhenwenjin
In-Reply-To: <1589375804-78423-1-git-send-email-zhouyanjie@wanyeetech.com>
1.The SSI clock of X1000 not like JZ4770 and JZ4780, they are not
directly derived from the output of SSIPLL, but from the clock
obtained by dividing the frequency by 2. "X1000_CLK_SSIPLL_DIV2"
is added for this purpose, and ensure that it initialized before
"X1000_CLK_SSIMUX" when initializing the clocks.
2.Clocks of LCD, OTG, EMC, EFUSE, OST, and gates of CPU, PCLK
are also added.
3.Use "CLK_OF_DECLARE_DRIVER" like the other CGU drivers.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
Notes:
v5:
New patch.
V5->v6:
Add missing part of X1000's CGU.
v6->v7:
Update commit message.
v7->v8:
No change.
drivers/clk/ingenic/x1000-cgu.c | 56 ++++++++++++++++++++++++++++++++++++-----
1 file changed, 50 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c
index c33934d..39ebd9d 100644
--- a/drivers/clk/ingenic/x1000-cgu.c
+++ b/drivers/clk/ingenic/x1000-cgu.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* X1000 SoC CGU driver
- * Copyright (c) 2019 Zhou Yanjie <zhouyanjie@zoho.com>
+ * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
*/
#include <linux/clk-provider.h>
@@ -20,6 +20,7 @@
#define CGU_REG_CLKGR 0x20
#define CGU_REG_OPCR 0x24
#define CGU_REG_DDRCDR 0x2c
+#define CGU_REG_USBCDR 0x50
#define CGU_REG_MACCDR 0x54
#define CGU_REG_I2SCDR 0x60
#define CGU_REG_LPCDR 0x64
@@ -116,9 +117,10 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
},
[X1000_CLK_CPU] = {
- "cpu", CGU_CLK_DIV,
+ "cpu", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { X1000_CLK_CPUMUX, -1, -1, -1 },
.div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 30 },
},
[X1000_CLK_L2CACHE] = {
@@ -147,9 +149,10 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
},
[X1000_CLK_PCLK] = {
- "pclk", CGU_CLK_DIV,
+ "pclk", CGU_CLK_DIV | CGU_CLK_GATE,
.parents = { X1000_CLK_AHB2PMUX, -1, -1, -1 },
.div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 28 },
},
[X1000_CLK_DDR] = {
@@ -162,12 +165,20 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
[X1000_CLK_MAC] = {
"mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
- .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
+ .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL },
.mux = { CGU_REG_MACCDR, 31, 1 },
.div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 },
.gate = { CGU_REG_CLKGR, 25 },
},
+ [X1000_CLK_LCD] = {
+ "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL },
+ .mux = { CGU_REG_LPCDR, 31, 1 },
+ .div = { CGU_REG_LPCDR, 0, 1, 8, 28, 27, 26 },
+ .gate = { CGU_REG_CLKGR, 23 },
+ },
+
[X1000_CLK_MSCMUX] = {
"msc_mux", CGU_CLK_MUX,
.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL},
@@ -188,6 +199,15 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
.gate = { CGU_REG_CLKGR, 5 },
},
+ [X1000_CLK_OTG] = {
+ "otg", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
+ .parents = { X1000_CLK_EXCLK, -1,
+ X1000_CLK_APLL, X1000_CLK_MPLL },
+ .mux = { CGU_REG_USBCDR, 30, 2 },
+ .div = { CGU_REG_USBCDR, 0, 1, 8, 29, 28, 27 },
+ .gate = { CGU_REG_CLKGR, 3 },
+ },
+
[X1000_CLK_SSIPLL] = {
"ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
.parents = { X1000_CLK_SCLKA, X1000_CLK_MPLL, -1, -1 },
@@ -195,14 +215,32 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
.div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 },
},
+ [X1000_CLK_SSIPLL_DIV2] = {
+ "ssi_pll_div2", CGU_CLK_FIXDIV,
+ .parents = { X1000_CLK_SSIPLL },
+ .fixdiv = { 2 },
+ },
+
[X1000_CLK_SSIMUX] = {
"ssi_mux", CGU_CLK_MUX,
- .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL, -1, -1 },
+ .parents = { X1000_CLK_EXCLK, X1000_CLK_SSIPLL_DIV2, -1, -1 },
.mux = { CGU_REG_SSICDR, 30, 1 },
},
/* Gate-only clocks */
+ [X1000_CLK_EMC] = {
+ "emc", CGU_CLK_GATE,
+ .parents = { X1000_CLK_AHB2, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 0 },
+ },
+
+ [X1000_CLK_EFUSE] = {
+ "efuse", CGU_CLK_GATE,
+ .parents = { X1000_CLK_AHB2, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 1 },
+ },
+
[X1000_CLK_SFC] = {
"sfc", CGU_CLK_GATE,
.parents = { X1000_CLK_SSIPLL, -1, -1, -1 },
@@ -251,6 +289,12 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
.gate = { CGU_REG_CLKGR, 19 },
},
+ [X1000_CLK_OST] = {
+ "ost", CGU_CLK_GATE,
+ .parents = { X1000_CLK_EXCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR, 20 },
+ },
+
[X1000_CLK_PDMA] = {
"pdma", CGU_CLK_GATE,
.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
@@ -277,4 +321,4 @@ static void __init x1000_cgu_init(struct device_node *np)
ingenic_cgu_register_syscore_ops(cgu);
}
-CLK_OF_DECLARE(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init);
+CLK_OF_DECLARE_DRIVER(x1000_cgu, "ingenic,x1000-cgu", x1000_cgu_init);
--
2.7.4
^ permalink raw reply related
* [PATCH v8 5/6] dt-bindings: clock: Add and reorder ABI for X1000.
From: 周琰杰 (Zhou Yanjie) @ 2020-05-13 13:16 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, devicetree, robh+dt, mturquette, sboyd, paul,
dongsheng.qiu, yanfei.li, sernia.zhou, zhenwenjin
In-Reply-To: <1589375804-78423-1-git-send-email-zhouyanjie@wanyeetech.com>
1.The SSI clock of X1000 not like JZ4770 and JZ4780, they are not
directly derived from the output of SSIPLL, but from the clock
obtained by dividing the frequency by 2. "X1000_CLK_SSIPLL_DIV2"
is added for this purpose, it must between "X1000_CLK_SSIPLL"
and "X1000_CLK_SSIMUX", otherwise an error will occurs when
initializing the clock. These ABIs are only used for X1000, and
I'm sure that no other devicetree out there is using these ABIs,
so we should be able to reorder them.
2.Clocks of LCD, OTG, EMC, EFUSE, OST are also added.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Notes:
v5:
New patch.
v5->v6:
Add missing part of X1000's CGU.
v6->v7:
No change.
v7->v8:
No change.
include/dt-bindings/clock/x1000-cgu.h | 62 +++++++++++++++++++----------------
1 file changed, 34 insertions(+), 28 deletions(-)
diff --git a/include/dt-bindings/clock/x1000-cgu.h b/include/dt-bindings/clock/x1000-cgu.h
index bbaebaf..ef6ff63 100644
--- a/include/dt-bindings/clock/x1000-cgu.h
+++ b/include/dt-bindings/clock/x1000-cgu.h
@@ -12,33 +12,39 @@
#ifndef __DT_BINDINGS_CLOCK_X1000_CGU_H__
#define __DT_BINDINGS_CLOCK_X1000_CGU_H__
-#define X1000_CLK_EXCLK 0
-#define X1000_CLK_RTCLK 1
-#define X1000_CLK_APLL 2
-#define X1000_CLK_MPLL 3
-#define X1000_CLK_SCLKA 4
-#define X1000_CLK_CPUMUX 5
-#define X1000_CLK_CPU 6
-#define X1000_CLK_L2CACHE 7
-#define X1000_CLK_AHB0 8
-#define X1000_CLK_AHB2PMUX 9
-#define X1000_CLK_AHB2 10
-#define X1000_CLK_PCLK 11
-#define X1000_CLK_DDR 12
-#define X1000_CLK_MAC 13
-#define X1000_CLK_MSCMUX 14
-#define X1000_CLK_MSC0 15
-#define X1000_CLK_MSC1 16
-#define X1000_CLK_SSIPLL 17
-#define X1000_CLK_SSIMUX 18
-#define X1000_CLK_SFC 19
-#define X1000_CLK_I2C0 20
-#define X1000_CLK_I2C1 21
-#define X1000_CLK_I2C2 22
-#define X1000_CLK_UART0 23
-#define X1000_CLK_UART1 24
-#define X1000_CLK_UART2 25
-#define X1000_CLK_SSI 26
-#define X1000_CLK_PDMA 27
+#define X1000_CLK_EXCLK 0
+#define X1000_CLK_RTCLK 1
+#define X1000_CLK_APLL 2
+#define X1000_CLK_MPLL 3
+#define X1000_CLK_SCLKA 4
+#define X1000_CLK_CPUMUX 5
+#define X1000_CLK_CPU 6
+#define X1000_CLK_L2CACHE 7
+#define X1000_CLK_AHB0 8
+#define X1000_CLK_AHB2PMUX 9
+#define X1000_CLK_AHB2 10
+#define X1000_CLK_PCLK 11
+#define X1000_CLK_DDR 12
+#define X1000_CLK_MAC 13
+#define X1000_CLK_LCD 14
+#define X1000_CLK_MSCMUX 15
+#define X1000_CLK_MSC0 16
+#define X1000_CLK_MSC1 17
+#define X1000_CLK_OTG 18
+#define X1000_CLK_SSIPLL 19
+#define X1000_CLK_SSIPLL_DIV2 20
+#define X1000_CLK_SSIMUX 21
+#define X1000_CLK_EMC 22
+#define X1000_CLK_EFUSE 23
+#define X1000_CLK_SFC 24
+#define X1000_CLK_I2C0 25
+#define X1000_CLK_I2C1 26
+#define X1000_CLK_I2C2 27
+#define X1000_CLK_UART0 28
+#define X1000_CLK_UART1 29
+#define X1000_CLK_UART2 30
+#define X1000_CLK_SSI 31
+#define X1000_CLK_OST 32
+#define X1000_CLK_PDMA 33
#endif /* __DT_BINDINGS_CLOCK_X1000_CGU_H__ */
--
2.7.4
^ permalink raw reply related
* [PATCH v8 4/6] clk: Ingenic: Add CGU driver for X1830.
From: 周琰杰 (Zhou Yanjie) @ 2020-05-13 13:16 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, devicetree, robh+dt, mturquette, sboyd, paul,
dongsheng.qiu, yanfei.li, sernia.zhou, zhenwenjin
In-Reply-To: <1589375804-78423-1-git-send-email-zhouyanjie@wanyeetech.com>
Add support for the clocks provided by the CGU in the Ingenic X1830
SoC, making use of the cgu code to do the heavy lifting.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
---
Notes:
v1->v2:
1.Use two fields (pll_reg & bypass_reg) instead of the 2-values
array (reg[2]).
2.Remove the "pll_info->version" and add a "pll_info->rate_multiplier".
3.Change my Signed-off-by from "Zhou Yanjie <zhouyanjie@zoho.com>"
to "周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>" because
the old mailbox is in an unstable state.
v2->v3:
Adjust order from [4/5] in v2 to [5/5] in v3.
v3->v4:
Adjust order from [5/5] in v3 to [4/4] in v4.
v4->v5:
Rebase on top of kernel 5.6-rc1.
v5->v6:
Add missing part of X1830's CGU.
v6->v7:
1.Adjust includes, add blank line as Paul Cercueil's suggest.
2.Move "*cgu" into x1830_cgu_init() as a local variable.
v7->v8:
No change.
drivers/clk/ingenic/Kconfig | 10 ++
drivers/clk/ingenic/Makefile | 1 +
drivers/clk/ingenic/x1830-cgu.c | 388 ++++++++++++++++++++++++++++++++++++++++
3 files changed, 399 insertions(+)
create mode 100644 drivers/clk/ingenic/x1830-cgu.c
diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig
index b4555b4..580b0cf 100644
--- a/drivers/clk/ingenic/Kconfig
+++ b/drivers/clk/ingenic/Kconfig
@@ -55,6 +55,16 @@ config INGENIC_CGU_X1000
If building for a X1000 SoC, you want to say Y here.
+config INGENIC_CGU_X1830
+ bool "Ingenic X1830 CGU driver"
+ default MACH_X1830
+ select INGENIC_CGU_COMMON
+ help
+ Support the clocks provided by the CGU hardware on Ingenic X1830
+ and compatible SoCs.
+
+ If building for a X1830 SoC, you want to say Y here.
+
config INGENIC_TCU_CLK
bool "Ingenic JZ47xx TCU clocks driver"
default MACH_INGENIC
diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile
index 8b1dad9..aaa4bff 100644
--- a/drivers/clk/ingenic/Makefile
+++ b/drivers/clk/ingenic/Makefile
@@ -5,4 +5,5 @@ obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o
obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o
+obj-$(CONFIG_INGENIC_CGU_X1830) += x1830-cgu.o
obj-$(CONFIG_INGENIC_TCU_CLK) += tcu.o
diff --git a/drivers/clk/ingenic/x1830-cgu.c b/drivers/clk/ingenic/x1830-cgu.c
new file mode 100644
index 00000000..6299ddb
--- /dev/null
+++ b/drivers/clk/ingenic/x1830-cgu.c
@@ -0,0 +1,388 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * X1830 SoC CGU driver
+ * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/of.h>
+
+#include <dt-bindings/clock/x1830-cgu.h>
+
+#include "cgu.h"
+#include "pm.h"
+
+/* CGU register offsets */
+#define CGU_REG_CPCCR 0x00
+#define CGU_REG_CPPCR 0x0c
+#define CGU_REG_APLL 0x10
+#define CGU_REG_MPLL 0x14
+#define CGU_REG_CLKGR0 0x20
+#define CGU_REG_OPCR 0x24
+#define CGU_REG_CLKGR1 0x28
+#define CGU_REG_DDRCDR 0x2c
+#define CGU_REG_USBPCR 0x3c
+#define CGU_REG_USBRDT 0x40
+#define CGU_REG_USBVBFIL 0x44
+#define CGU_REG_USBPCR1 0x48
+#define CGU_REG_MACCDR 0x54
+#define CGU_REG_EPLL 0x58
+#define CGU_REG_I2SCDR 0x60
+#define CGU_REG_LPCDR 0x64
+#define CGU_REG_MSC0CDR 0x68
+#define CGU_REG_I2SCDR1 0x70
+#define CGU_REG_SSICDR 0x74
+#define CGU_REG_CIMCDR 0x7c
+#define CGU_REG_MSC1CDR 0xa4
+#define CGU_REG_CMP_INTR 0xb0
+#define CGU_REG_CMP_INTRE 0xb4
+#define CGU_REG_DRCG 0xd0
+#define CGU_REG_CPCSR 0xd4
+#define CGU_REG_VPLL 0xe0
+#define CGU_REG_MACPHYC 0xe8
+
+/* bits within the OPCR register */
+#define OPCR_SPENDN0 BIT(7)
+#define OPCR_SPENDN1 BIT(6)
+
+static const s8 pll_od_encoding[64] = {
+ 0x0, 0x1, -1, 0x2, -1, -1, -1, 0x3,
+ -1, -1, -1, -1, -1, -1, -1, 0x4,
+ -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1, 0x5,
+ -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1, -1,
+ -1, -1, -1, -1, -1, -1, -1, 0x6,
+};
+
+static const struct ingenic_cgu_clk_info x1830_cgu_clocks[] = {
+
+ /* External clocks */
+
+ [X1830_CLK_EXCLK] = { "ext", CGU_CLK_EXT },
+ [X1830_CLK_RTCLK] = { "rtc", CGU_CLK_EXT },
+
+ /* PLLs */
+
+ [X1830_CLK_APLL] = {
+ "apll", CGU_CLK_PLL,
+ .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
+ .pll = {
+ .reg = CGU_REG_APLL,
+ .rate_multiplier = 2,
+ .m_shift = 20,
+ .m_bits = 9,
+ .m_offset = 1,
+ .n_shift = 14,
+ .n_bits = 6,
+ .n_offset = 1,
+ .od_shift = 11,
+ .od_bits = 3,
+ .od_max = 64,
+ .od_encoding = pll_od_encoding,
+ .bypass_reg = CGU_REG_CPPCR,
+ .bypass_bit = 30,
+ .enable_bit = 0,
+ .stable_bit = 3,
+ },
+ },
+
+ [X1830_CLK_MPLL] = {
+ "mpll", CGU_CLK_PLL,
+ .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
+ .pll = {
+ .reg = CGU_REG_MPLL,
+ .rate_multiplier = 2,
+ .m_shift = 20,
+ .m_bits = 9,
+ .m_offset = 1,
+ .n_shift = 14,
+ .n_bits = 6,
+ .n_offset = 1,
+ .od_shift = 11,
+ .od_bits = 3,
+ .od_max = 64,
+ .od_encoding = pll_od_encoding,
+ .bypass_reg = CGU_REG_CPPCR,
+ .bypass_bit = 28,
+ .enable_bit = 0,
+ .stable_bit = 3,
+ },
+ },
+
+ [X1830_CLK_EPLL] = {
+ "epll", CGU_CLK_PLL,
+ .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
+ .pll = {
+ .reg = CGU_REG_EPLL,
+ .rate_multiplier = 2,
+ .m_shift = 20,
+ .m_bits = 9,
+ .m_offset = 1,
+ .n_shift = 14,
+ .n_bits = 6,
+ .n_offset = 1,
+ .od_shift = 11,
+ .od_bits = 3,
+ .od_max = 64,
+ .od_encoding = pll_od_encoding,
+ .bypass_reg = CGU_REG_CPPCR,
+ .bypass_bit = 24,
+ .enable_bit = 0,
+ .stable_bit = 3,
+ },
+ },
+
+ [X1830_CLK_VPLL] = {
+ "vpll", CGU_CLK_PLL,
+ .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
+ .pll = {
+ .reg = CGU_REG_VPLL,
+ .rate_multiplier = 2,
+ .m_shift = 20,
+ .m_bits = 9,
+ .m_offset = 1,
+ .n_shift = 14,
+ .n_bits = 6,
+ .n_offset = 1,
+ .od_shift = 11,
+ .od_bits = 3,
+ .od_max = 64,
+ .od_encoding = pll_od_encoding,
+ .bypass_reg = CGU_REG_CPPCR,
+ .bypass_bit = 26,
+ .enable_bit = 0,
+ .stable_bit = 3,
+ },
+ },
+
+ /* Muxes & dividers */
+
+ [X1830_CLK_SCLKA] = {
+ "sclk_a", CGU_CLK_MUX,
+ .parents = { -1, X1830_CLK_EXCLK, X1830_CLK_APLL, -1 },
+ .mux = { CGU_REG_CPCCR, 30, 2 },
+ },
+
+ [X1830_CLK_CPUMUX] = {
+ "cpu_mux", CGU_CLK_MUX,
+ .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
+ .mux = { CGU_REG_CPCCR, 28, 2 },
+ },
+
+ [X1830_CLK_CPU] = {
+ "cpu", CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
+ .div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
+ .gate = { CGU_REG_CLKGR1, 15 },
+ },
+
+ [X1830_CLK_L2CACHE] = {
+ "l2cache", CGU_CLK_DIV,
+ .parents = { X1830_CLK_CPUMUX, -1, -1, -1 },
+ .div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
+ },
+
+ [X1830_CLK_AHB0] = {
+ "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
+ .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
+ .mux = { CGU_REG_CPCCR, 26, 2 },
+ .div = { CGU_REG_CPCCR, 8, 1, 4, 21, -1, -1 },
+ },
+
+ [X1830_CLK_AHB2PMUX] = {
+ "ahb2_apb_mux", CGU_CLK_MUX,
+ .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
+ .mux = { CGU_REG_CPCCR, 24, 2 },
+ },
+
+ [X1830_CLK_AHB2] = {
+ "ahb2", CGU_CLK_DIV,
+ .parents = { X1830_CLK_AHB2PMUX, -1, -1, -1 },
+ .div = { CGU_REG_CPCCR, 12, 1, 4, 20, -1, -1 },
+ },
+
+ [X1830_CLK_PCLK] = {
+ "pclk", CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { X1830_CLK_AHB2PMUX, -1, -1, -1 },
+ .div = { CGU_REG_CPCCR, 16, 1, 4, 20, -1, -1 },
+ .gate = { CGU_REG_CLKGR1, 14 },
+ },
+
+ [X1830_CLK_DDR] = {
+ "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { -1, X1830_CLK_SCLKA, X1830_CLK_MPLL, -1 },
+ .mux = { CGU_REG_DDRCDR, 30, 2 },
+ .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
+ .gate = { CGU_REG_CLKGR0, 31 },
+ },
+
+ [X1830_CLK_MAC] = {
+ "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL,
+ X1830_CLK_VPLL, X1830_CLK_EPLL },
+ .mux = { CGU_REG_MACCDR, 30, 2 },
+ .div = { CGU_REG_MACCDR, 0, 1, 8, 29, 28, 27 },
+ .gate = { CGU_REG_CLKGR1, 4 },
+ },
+
+ [X1830_CLK_LCD] = {
+ "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL,
+ X1830_CLK_VPLL, X1830_CLK_EPLL },
+ .mux = { CGU_REG_LPCDR, 30, 2 },
+ .div = { CGU_REG_LPCDR, 0, 1, 8, 28, 27, 26 },
+ .gate = { CGU_REG_CLKGR1, 9 },
+ },
+
+ [X1830_CLK_MSCMUX] = {
+ "msc_mux", CGU_CLK_MUX,
+ .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL,
+ X1830_CLK_VPLL, X1830_CLK_EPLL },
+ .mux = { CGU_REG_MSC0CDR, 30, 2 },
+ },
+
+ [X1830_CLK_MSC0] = {
+ "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { X1830_CLK_MSCMUX, -1, -1, -1 },
+ .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 },
+ .gate = { CGU_REG_CLKGR0, 4 },
+ },
+
+ [X1830_CLK_MSC1] = {
+ "msc1", CGU_CLK_DIV | CGU_CLK_GATE,
+ .parents = { X1830_CLK_MSCMUX, -1, -1, -1 },
+ .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 },
+ .gate = { CGU_REG_CLKGR0, 5 },
+ },
+
+ [X1830_CLK_SSIPLL] = {
+ "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
+ .parents = { X1830_CLK_SCLKA, X1830_CLK_MPLL,
+ X1830_CLK_VPLL, X1830_CLK_EPLL },
+ .mux = { CGU_REG_SSICDR, 30, 2 },
+ .div = { CGU_REG_SSICDR, 0, 1, 8, 28, 27, 26 },
+ },
+
+ [X1830_CLK_SSIPLL_DIV2] = {
+ "ssi_pll_div2", CGU_CLK_FIXDIV,
+ .parents = { X1830_CLK_SSIPLL },
+ .fixdiv = { 2 },
+ },
+
+ [X1830_CLK_SSIMUX] = {
+ "ssi_mux", CGU_CLK_MUX,
+ .parents = { X1830_CLK_EXCLK, X1830_CLK_SSIPLL_DIV2, -1, -1 },
+ .mux = { CGU_REG_SSICDR, 29, 1 },
+ },
+
+ /* Gate-only clocks */
+
+ [X1830_CLK_EMC] = {
+ "emc", CGU_CLK_GATE,
+ .parents = { X1830_CLK_AHB2, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR0, 0 },
+ },
+
+ [X1830_CLK_EFUSE] = {
+ "efuse", CGU_CLK_GATE,
+ .parents = { X1830_CLK_AHB2, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR0, 1 },
+ },
+
+ [X1830_CLK_OTG] = {
+ "otg", CGU_CLK_GATE,
+ .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR0, 3 },
+ },
+
+ [X1830_CLK_SSI0] = {
+ "ssi0", CGU_CLK_GATE,
+ .parents = { X1830_CLK_SSIMUX, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR0, 6 },
+ },
+
+ [X1830_CLK_SMB0] = {
+ "smb0", CGU_CLK_GATE,
+ .parents = { X1830_CLK_PCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR0, 7 },
+ },
+
+ [X1830_CLK_SMB1] = {
+ "smb1", CGU_CLK_GATE,
+ .parents = { X1830_CLK_PCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR0, 8 },
+ },
+
+ [X1830_CLK_SMB2] = {
+ "smb2", CGU_CLK_GATE,
+ .parents = { X1830_CLK_PCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR0, 9 },
+ },
+
+ [X1830_CLK_UART0] = {
+ "uart0", CGU_CLK_GATE,
+ .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR0, 14 },
+ },
+
+ [X1830_CLK_UART1] = {
+ "uart1", CGU_CLK_GATE,
+ .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR0, 15 },
+ },
+
+ [X1830_CLK_SSI1] = {
+ "ssi1", CGU_CLK_GATE,
+ .parents = { X1830_CLK_SSIMUX, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR0, 19 },
+ },
+
+ [X1830_CLK_SFC] = {
+ "sfc", CGU_CLK_GATE,
+ .parents = { X1830_CLK_SSIPLL, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR0, 20 },
+ },
+
+ [X1830_CLK_PDMA] = {
+ "pdma", CGU_CLK_GATE,
+ .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR0, 21 },
+ },
+
+ [X1830_CLK_DTRNG] = {
+ "dtrng", CGU_CLK_GATE,
+ .parents = { X1830_CLK_PCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR1, 1 },
+ },
+
+ [X1830_CLK_OST] = {
+ "ost", CGU_CLK_GATE,
+ .parents = { X1830_CLK_EXCLK, -1, -1, -1 },
+ .gate = { CGU_REG_CLKGR1, 11 },
+ },
+};
+
+static void __init x1830_cgu_init(struct device_node *np)
+{
+ struct ingenic_cgu *cgu;
+ int retval;
+
+ cgu = ingenic_cgu_new(x1830_cgu_clocks,
+ ARRAY_SIZE(x1830_cgu_clocks), np);
+ if (!cgu) {
+ pr_err("%s: failed to initialise CGU\n", __func__);
+ return;
+ }
+
+ retval = ingenic_cgu_register_clocks(cgu);
+ if (retval) {
+ pr_err("%s: failed to register CGU Clocks\n", __func__);
+ return;
+ }
+
+ ingenic_cgu_register_syscore_ops(cgu);
+}
+CLK_OF_DECLARE_DRIVER(x1830_cgu, "ingenic,x1830-cgu", x1830_cgu_init);
--
2.7.4
^ permalink raw reply related
* [PATCH v8 2/6] clk: Ingenic: Adjust cgu code to make it compatible with X1830.
From: 周琰杰 (Zhou Yanjie) @ 2020-05-13 13:16 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, devicetree, robh+dt, mturquette, sboyd, paul,
dongsheng.qiu, yanfei.li, sernia.zhou, zhenwenjin
In-Reply-To: <1589375804-78423-1-git-send-email-zhouyanjie@wanyeetech.com>
The PLL of X1830 Soc from Ingenic has been greatly changed,
the bypass control is placed in another register, so now two
registers may needed to control the PLL. To this end, a new
"bypass_reg" was introduced. In addition, when calculating
rate, the PLL of X1830 introduced an extra 2x multiplier,
so a new "rate_multiplier" was introduced. And adjust the
code in jz47xx-cgu.c and x1000-cgu.c, make it to be
compatible with the new cgu code.
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
---
Notes:
v2->v3:
Adjust order from [1/5] in v2 to [2/5] in v3.
v3->v4:
Merge [3/5] in v3 into this patch.
v4->v5:
Rebase on top of kernel 5.6-rc1.
v5->v6:
Revert "pll_reg" to "reg" to minimize patch as Paul Cercueil's suggest.
v6->v7:
Update commit message.
v7->v8:
No change.
drivers/clk/ingenic/cgu.c | 16 +++++++++++++---
drivers/clk/ingenic/cgu.h | 4 ++++
drivers/clk/ingenic/jz4725b-cgu.c | 4 ++++
drivers/clk/ingenic/jz4740-cgu.c | 4 ++++
drivers/clk/ingenic/jz4770-cgu.c | 8 +++++++-
drivers/clk/ingenic/jz4780-cgu.c | 3 +++
drivers/clk/ingenic/x1000-cgu.c | 6 ++++++
7 files changed, 41 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index ab1302a..d7981b6 100644
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
@@ -90,6 +90,9 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
n += pll_info->n_offset;
od_enc = ctl >> pll_info->od_shift;
od_enc &= GENMASK(pll_info->od_bits - 1, 0);
+
+ ctl = readl(cgu->base + pll_info->bypass_reg);
+
bypass = !pll_info->no_bypass_bit &&
!!(ctl & BIT(pll_info->bypass_bit));
@@ -103,7 +106,8 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
BUG_ON(od == pll_info->od_max);
od++;
- return div_u64((u64)parent_rate * m, n * od);
+ return div_u64((u64)parent_rate * m * pll_info->rate_multiplier,
+ n * od);
}
static unsigned long
@@ -136,7 +140,8 @@ ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info,
if (pod)
*pod = od;
- return div_u64((u64)parent_rate * m, n * od);
+ return div_u64((u64)parent_rate * m * pll_info->rate_multiplier,
+ n * od);
}
static inline const struct ingenic_cgu_clk_info *to_clk_info(
@@ -209,9 +214,14 @@ static int ingenic_pll_enable(struct clk_hw *hw)
u32 ctl;
spin_lock_irqsave(&cgu->lock, flags);
- ctl = readl(cgu->base + pll_info->reg);
+ ctl = readl(cgu->base + pll_info->bypass_reg);
ctl &= ~BIT(pll_info->bypass_bit);
+
+ writel(ctl, cgu->base + pll_info->bypass_reg);
+
+ ctl = readl(cgu->base + pll_info->reg);
+
ctl |= BIT(pll_info->enable_bit);
writel(ctl, cgu->base + pll_info->reg);
diff --git a/drivers/clk/ingenic/cgu.h b/drivers/clk/ingenic/cgu.h
index 0dc8004..2c75ef4 100644
--- a/drivers/clk/ingenic/cgu.h
+++ b/drivers/clk/ingenic/cgu.h
@@ -17,6 +17,7 @@
/**
* struct ingenic_cgu_pll_info - information about a PLL
* @reg: the offset of the PLL's control register within the CGU
+ * @rate_multiplier: the multiplier needed by pll rate calculation
* @m_shift: the number of bits to shift the multiplier value by (ie. the
* index of the lowest bit of the multiplier value in the PLL's
* control register)
@@ -37,6 +38,7 @@
* @od_encoding: a pointer to an array mapping post-VCO divider values to
* their encoded values in the PLL control register, or -1 for
* unsupported values
+ * @bypass_reg: the offset of the bypass control register within the CGU
* @bypass_bit: the index of the bypass bit in the PLL control register
* @enable_bit: the index of the enable bit in the PLL control register
* @stable_bit: the index of the stable bit in the PLL control register
@@ -44,10 +46,12 @@
*/
struct ingenic_cgu_pll_info {
unsigned reg;
+ unsigned rate_multiplier;
const s8 *od_encoding;
u8 m_shift, m_bits, m_offset;
u8 n_shift, n_bits, n_offset;
u8 od_shift, od_bits, od_max;
+ unsigned bypass_reg;
u8 bypass_bit;
u8 enable_bit;
u8 stable_bit;
diff --git a/drivers/clk/ingenic/jz4725b-cgu.c b/drivers/clk/ingenic/jz4725b-cgu.c
index a3b4635..8c38e72 100644
--- a/drivers/clk/ingenic/jz4725b-cgu.c
+++ b/drivers/clk/ingenic/jz4725b-cgu.c
@@ -9,7 +9,9 @@
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/of.h>
+
#include <dt-bindings/clock/jz4725b-cgu.h>
+
#include "cgu.h"
#include "pm.h"
@@ -54,6 +56,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
.parents = { JZ4725B_CLK_EXT, -1, -1, -1 },
.pll = {
.reg = CGU_REG_CPPCR,
+ .rate_multiplier = 1,
.m_shift = 23,
.m_bits = 9,
.m_offset = 2,
@@ -65,6 +68,7 @@ static const struct ingenic_cgu_clk_info jz4725b_cgu_clocks[] = {
.od_max = 4,
.od_encoding = pll_od_encoding,
.stable_bit = 10,
+ .bypass_reg = CGU_REG_CPPCR,
.bypass_bit = 9,
.enable_bit = 8,
},
diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c
index 4f0e92c..c0ac919 100644
--- a/drivers/clk/ingenic/jz4740-cgu.c
+++ b/drivers/clk/ingenic/jz4740-cgu.c
@@ -10,7 +10,9 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of.h>
+
#include <dt-bindings/clock/jz4740-cgu.h>
+
#include "cgu.h"
#include "pm.h"
@@ -69,6 +71,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
.parents = { JZ4740_CLK_EXT, -1, -1, -1 },
.pll = {
.reg = CGU_REG_CPPCR,
+ .rate_multiplier = 1,
.m_shift = 23,
.m_bits = 9,
.m_offset = 2,
@@ -80,6 +83,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
.od_max = 4,
.od_encoding = pll_od_encoding,
.stable_bit = 10,
+ .bypass_reg = CGU_REG_CPPCR,
.bypass_bit = 9,
.enable_bit = 8,
},
diff --git a/drivers/clk/ingenic/jz4770-cgu.c b/drivers/clk/ingenic/jz4770-cgu.c
index c051ecb..9ea4490 100644
--- a/drivers/clk/ingenic/jz4770-cgu.c
+++ b/drivers/clk/ingenic/jz4770-cgu.c
@@ -9,7 +9,9 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/of.h>
+
#include <dt-bindings/clock/jz4770-cgu.h>
+
#include "cgu.h"
#include "pm.h"
@@ -102,6 +104,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
.parents = { JZ4770_CLK_EXT },
.pll = {
.reg = CGU_REG_CPPCR0,
+ .rate_multiplier = 1,
.m_shift = 24,
.m_bits = 7,
.m_offset = 1,
@@ -112,6 +115,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
.od_bits = 2,
.od_max = 8,
.od_encoding = pll_od_encoding,
+ .bypass_reg = CGU_REG_CPPCR0,
.bypass_bit = 9,
.enable_bit = 8,
.stable_bit = 10,
@@ -124,6 +128,7 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
.parents = { JZ4770_CLK_EXT },
.pll = {
.reg = CGU_REG_CPPCR1,
+ .rate_multiplier = 1,
.m_shift = 24,
.m_bits = 7,
.m_offset = 1,
@@ -134,9 +139,10 @@ static const struct ingenic_cgu_clk_info jz4770_cgu_clocks[] = {
.od_bits = 2,
.od_max = 8,
.od_encoding = pll_od_encoding,
+ .bypass_reg = CGU_REG_CPPCR1,
+ .no_bypass_bit = true,
.enable_bit = 7,
.stable_bit = 6,
- .no_bypass_bit = true,
},
},
diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c
index c758f16..6c5b802 100644
--- a/drivers/clk/ingenic/jz4780-cgu.c
+++ b/drivers/clk/ingenic/jz4780-cgu.c
@@ -13,6 +13,7 @@
#include <linux/of.h>
#include <dt-bindings/clock/jz4780-cgu.h>
+
#include "cgu.h"
#include "pm.h"
@@ -266,6 +267,7 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
#define DEF_PLL(name) { \
.reg = CGU_REG_ ## name, \
+ .rate_multiplier = 1, \
.m_shift = 19, \
.m_bits = 13, \
.m_offset = 1, \
@@ -277,6 +279,7 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
.od_max = 16, \
.od_encoding = pll_od_encoding, \
.stable_bit = 6, \
+ .bypass_reg = CGU_REG_ ## name, \
.bypass_bit = 1, \
.enable_bit = 0, \
}
diff --git a/drivers/clk/ingenic/x1000-cgu.c b/drivers/clk/ingenic/x1000-cgu.c
index b22d87b..c33934d 100644
--- a/drivers/clk/ingenic/x1000-cgu.c
+++ b/drivers/clk/ingenic/x1000-cgu.c
@@ -7,7 +7,9 @@
#include <linux/clk-provider.h>
#include <linux/delay.h>
#include <linux/of.h>
+
#include <dt-bindings/clock/x1000-cgu.h>
+
#include "cgu.h"
#include "pm.h"
@@ -58,6 +60,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
.pll = {
.reg = CGU_REG_APLL,
+ .rate_multiplier = 1,
.m_shift = 24,
.m_bits = 7,
.m_offset = 1,
@@ -68,6 +71,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
.od_bits = 2,
.od_max = 8,
.od_encoding = pll_od_encoding,
+ .bypass_reg = CGU_REG_APLL,
.bypass_bit = 9,
.enable_bit = 8,
.stable_bit = 10,
@@ -79,6 +83,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
.parents = { X1000_CLK_EXCLK, -1, -1, -1 },
.pll = {
.reg = CGU_REG_MPLL,
+ .rate_multiplier = 1,
.m_shift = 24,
.m_bits = 7,
.m_offset = 1,
@@ -89,6 +94,7 @@ static const struct ingenic_cgu_clk_info x1000_cgu_clocks[] = {
.od_bits = 2,
.od_max = 8,
.od_encoding = pll_od_encoding,
+ .bypass_reg = CGU_REG_MPLL,
.bypass_bit = 6,
.enable_bit = 7,
.stable_bit = 0,
--
2.7.4
^ permalink raw reply related
* [PATCH v8 1/6] clk: Ingenic: Remove unnecessary spinlock when reading registers.
From: 周琰杰 (Zhou Yanjie) @ 2020-05-13 13:16 UTC (permalink / raw)
To: linux-clk
Cc: linux-kernel, devicetree, robh+dt, mturquette, sboyd, paul,
dongsheng.qiu, yanfei.li, sernia.zhou, zhenwenjin
In-Reply-To: <1589375804-78423-1-git-send-email-zhouyanjie@wanyeetech.com>
It is not necessary to use spinlock when reading registers,
so remove it from cgu.c.
Suggested-by: Paul Cercueil <paul@crapouillou.net>
Suggested-by: Paul Burton <paulburton@kernel.org>
Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
---
Notes:
v2:
New patch.
v2->v3:
Adjust order from [5/5] in v2 to [1/5] in v3.
v3->v4:
Remove the spinlock around ingenic_cgu_gate_get().
v4->v5:
Rebase on top of kernel 5.6-rc1.
v5->v6:
No change.
v6->v7:
No change.
v7->v8:
No change.
drivers/clk/ingenic/cgu.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index 6e96303..ab1302a 100644
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
@@ -76,16 +76,13 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
const struct ingenic_cgu_pll_info *pll_info;
unsigned m, n, od_enc, od;
bool bypass;
- unsigned long flags;
u32 ctl;
clk_info = &cgu->clock_info[ingenic_clk->idx];
BUG_ON(clk_info->type != CGU_CLK_PLL);
pll_info = &clk_info->pll;
- spin_lock_irqsave(&cgu->lock, flags);
ctl = readl(cgu->base + pll_info->reg);
- spin_unlock_irqrestore(&cgu->lock, flags);
m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0);
m += pll_info->m_offset;
@@ -259,12 +256,9 @@ static int ingenic_pll_is_enabled(struct clk_hw *hw)
struct ingenic_cgu *cgu = ingenic_clk->cgu;
const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);
const struct ingenic_cgu_pll_info *pll_info = &clk_info->pll;
- unsigned long flags;
u32 ctl;
- spin_lock_irqsave(&cgu->lock, flags);
ctl = readl(cgu->base + pll_info->reg);
- spin_unlock_irqrestore(&cgu->lock, flags);
return !!(ctl & BIT(pll_info->enable_bit));
}
@@ -562,16 +556,12 @@ static int ingenic_clk_is_enabled(struct clk_hw *hw)
struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
struct ingenic_cgu *cgu = ingenic_clk->cgu;
const struct ingenic_cgu_clk_info *clk_info;
- unsigned long flags;
int enabled = 1;
clk_info = &cgu->clock_info[ingenic_clk->idx];
- if (clk_info->type & CGU_CLK_GATE) {
- spin_lock_irqsave(&cgu->lock, flags);
+ if (clk_info->type & CGU_CLK_GATE)
enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate);
- spin_unlock_irqrestore(&cgu->lock, flags);
- }
return enabled;
}
--
2.7.4
^ permalink raw reply related
* Re: [PATCH] i2c: pxa: implement generic i2c bus recovery
From: Andrew Lunn @ 2020-05-13 13:18 UTC (permalink / raw)
To: Russell King
Cc: linux-i2c, devicetree, Gregory Clement, Jason Cooper,
linux-arm-kernel, Rob Herring, Sebastian Hesselbarth,
Vladimir Vid
In-Reply-To: <E1jYnlI-0002Nw-83@rmk-PC.armlinux.org.uk>
On Wed, May 13, 2020 at 10:33:12AM +0100, Russell King wrote:
> Implement generic GPIO-based I2C bus recovery for the PXA I2C driver.
Hi Russell
I assume this is going to be merged via i2c? So Wolfram Sang? He is
not on To: or Cc:
Andrew
^ permalink raw reply
* Re: [RFC v1 2/3] drivers: nvmem: Add driver for QTI qfprom-efuse support
From: Srinivas Kandagatla @ 2020-05-13 13:20 UTC (permalink / raw)
To: Ravi Kumar Bokka, Rob Herring
Cc: linux-kernel, devicetree, rnayak, saiprakash.ranjan, dhavalp,
mturney, sparate, c_rbokka, mkurumel
In-Reply-To: <1589307480-27508-3-git-send-email-rbokka@codeaurora.org>
On 12/05/2020 19:17, Ravi Kumar Bokka wrote:
> This patch adds new driver for QTI qfprom-efuse controller. This driver can
> access the raw qfprom regions for fuse blowing.
QTI?
>
> The current existed qfprom driver is only supports for cpufreq, thermal sensors
> drivers by read out calibration data, speed bins..etc which is stored
> by qfprom efuses.
Can you explain bit more about this QFPROM instance, Is this QFPROM part
of secure controller address space?
Is this closely tied to SoC or Secure controller version?
Any reason why this can not be integrated into qfprom driver with
specific compatible.
>
> Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
> ---
> drivers/nvmem/Kconfig | 10 +
> drivers/nvmem/Makefile | 2 +
> drivers/nvmem/qfprom-efuse.c | 476 +++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 488 insertions(+)
> create mode 100644 drivers/nvmem/qfprom-efuse.c
>
...
> diff --git a/drivers/nvmem/qfprom-efuse.c b/drivers/nvmem/qfprom-efuse.c
> new file mode 100644
> index 0000000..2e3c275
> --- /dev/null
> +++ b/drivers/nvmem/qfprom-efuse.c
> @@ -0,0 +1,476 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/nvmem-provider.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/regulator/consumer.h>
> +
> +#define QFPROM_BLOW_STATUS_BUSY 0x1
> +#define QFPROM_BLOW_STATUS_READY 0x0
> +
> +/* Blow timer clock frequency in Mhz for 10nm LPe technology */
> +#define QFPROM_BLOW_TIMER_OFFSET 0x03c
> +#define QFPROM_BLOW_TIMER_RESET_VALUE 0x0
> +
> +/* Amount of time required to hold charge to blow fuse in micro-seconds */
> +#define QFPROM_FUSE_BLOW_POLL_PERIOD 100
> +#define QFPROM_BLOW_STATUS_OFFSET 0x048
> +
> +#define QFPROM_ACCEL_OFFSET 0x044
> +
> +/**
> + * struct qfprom_efuse_platform_data - structure holding qfprom-efuse
> + * platform data
> + *
> + * @name: qfprom-efuse compatible name
??
> + * @fuse_blow_time_in_us: Should contain the wait time when doing the fuse blow
> + * @accel_value: Should contain qfprom accel value
> + * @accel_reset_value: The reset value of qfprom accel value
> + * @qfprom_blow_timer_value: The timer value of qfprom when doing efuse blow
> + * @qfprom_blow_reset_freq: The frequency required to set when fuse blowing
> + * is done
> + * @qfprom_blow_set_freq: The frequency required to set when we start the
> + * fuse blowing
> + * @qfprom_max_vol: max voltage required to set fuse blow
> + * @qfprom_min_vol: min voltage required to set fuse blow
How specific are these values per SoC?
> + */
> +struct qfprom_efuse_platform_data {
> + const char *name;
> + u8 fuse_blow_time_in_us;
> + u32 accel_value;
> + u32 accel_reset_value;
> + u32 qfprom_blow_timer_value;
> + u32 qfprom_blow_reset_freq;
> + u32 qfprom_blow_set_freq;
> + u32 qfprom_max_vol;
> + u32 qfprom_min_vol;
> +};
> +
> +/**
> + * struct qfprom_efuse_priv - structure holding qfprom-efuse attributes
> + *
> + * @qfpbase: iomapped memory space for qfprom base
> + * @qfpraw: iomapped memory space for qfprom raw fuse region
> + * @qfpmap: iomapped memory space for qfprom fuse blow timer
> +
> + * @dev: qfprom device structure
> + * @secclk: clock supply
> + * @vcc: regulator supply
> +
> + * @qfpraw_start: qfprom raw fuse start region
> + * @qfpraw_end: qfprom raw fuse end region
> + * @qfprom_efuse_platform_data: qfprom platform data
> + */
> +struct qfprom_efuse_priv {
> + void __iomem *qfpbase;
> + void __iomem *qfpraw;
> + void __iomem *qfpmap;
Why are these memory regions split? Can't you just have complete qfprom
area and add fixed offset for qfpraw within the driver?
> + struct device *dev;
> + struct clk *secclk;
> + struct regulator *vcc;
> + resource_size_t qfpraw_start;
> + resource_size_t qfpraw_end;
Why do we need to check this range? as long as we set the nvmem_config
with correct range then you should not need this check.
> + struct qfprom_efuse_platform_data efuse;
A pointer here should be good enough?
> +};
> +
...
> +/*
> + * sets the value of the blow timer, accel register and the clock
> + * and voltage settings
> + */
> +static int qfprom_enable_fuse_blowing(const struct qfprom_efuse_priv *priv)
> +{
> + int ret;
> +
> + ret = qfprom_disable_fuse_blowing(priv);
> + if (ret) {
> + dev_err(priv->dev, "qfprom_disable_fuse_blowing()\n");
> + return ret;
> + }
Why do we need to qfprom_disable_fuse_blowing() for every call to enable it?
Or are we missing some error handling in the caller?
> +
> + writel(priv->efuse.qfprom_blow_timer_value, priv->qfpmap +
> + QFPROM_BLOW_TIMER_OFFSET);
> + writel(priv->efuse.accel_value, priv->qfpmap + QFPROM_ACCEL_OFFSET);
> +
> + ret = qfprom_set_clock_settings(priv);
> + if (ret) {
> + dev_err(priv->dev, "qpfrom_set_clock_settings()\n");
> + return ret;
> + }
> +
> + ret = qfprom_set_voltage_settings(priv, priv->efuse.qfprom_min_vol,
> + priv->efuse.qfprom_max_vol);
> + if (ret) {
> + dev_err(priv->dev, "qfprom_set_voltage_settings()\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
<<
> +/*
> + * verifying to make sure address being written or read is from qfprom
> + * raw address range
> + */
> +bool addr_in_qfprom_range(const struct qfprom_efuse_priv *priv, u32 reg,
> + size_t bytes)
> +{
> + if (((reg + bytes) > reg) && (reg >= priv->qfpraw_start) &&
> + ((reg + bytes) <= priv->qfpraw_end)) {
> + return 1;
> + }
> +
> + return 0;
> +}
>>
Above function is totally redundant, nvmem core already has checks for this.
> +
> +/*
> + * API for reading from raw qfprom region
> + */
> +static int qfprom_efuse_reg_read(void *context, unsigned int reg, void *_val,
> + size_t bytes)
> +{
> + struct qfprom_efuse_priv *priv = context;
> + u32 *value = _val;
> + u32 align_check;
> + int i = 0, words = bytes / 4;
> +
> + dev_info(priv->dev,
> + "reading raw qfprom region offset: 0x%08x of size: %zd\n",
> + reg, bytes);
In general there is lot of debug info across the code, do you really
need all this? Consider removing these!
> +
> + if (bytes % 4 != 0x00) {
> + dev_err(priv->dev,
> + "Bytes: %zd to read should be word align\n",
> + bytes);
> + return -EINVAL;
> + }
This word align check is also redundant once you set nvmem_config with
correct word_size.
> +
> + if (!addr_in_qfprom_range(priv, reg, bytes)) {
> + dev_err(priv->dev,
> + "Invalid qfprom raw region offset 0x%08x & bytes %zd\n",
> + reg, bytes);
> + return -EINVAL;
> + }
> +
> + align_check = (reg & 0xF);
> +
> + if (((align_check & ~3) == align_check) && value != NULL)
> + while (words--)
> + *value++ = readl(priv->qfpbase + reg + (i++ * 4));
> +
> + else
> + dev_err(priv->dev,
> + "Invalid input parameter 0x%08x fuse blow address\n",
> + reg);
> +
> + return 0;
> +}
...
> +
> +static int qfprom_efuse_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct resource *qfpbase, *qfpraw, *qfpmap;
> + struct nvmem_device *nvmem;
> + struct nvmem_config *econfig;
> + struct qfprom_efuse_priv *priv;
> + const struct qfprom_efuse_platform_data *drvdata;
> + int ret;
> +
> + dev_info(&pdev->dev, "[%s]: Invoked\n", __func__);
> +
too much debug!
> + drvdata = of_device_get_match_data(&pdev->dev);
> + if (!drvdata)
> + return -EINVAL;
Unnecessary check as this driver will not be probed unless there is a
compatible match.
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->efuse.fuse_blow_time_in_us = drvdata->fuse_blow_time_in_us;
> + priv->efuse.accel_value = drvdata->accel_value;
> + priv->efuse.accel_reset_value = drvdata->accel_reset_value;
> + priv->efuse.qfprom_blow_timer_value = drvdata->qfprom_blow_timer_value;
> + priv->efuse.qfprom_blow_reset_freq = drvdata->qfprom_blow_reset_freq;
> + priv->efuse.qfprom_blow_set_freq = drvdata->qfprom_blow_set_freq;
> + priv->efuse.qfprom_max_vol = drvdata->qfprom_max_vol;
> + priv->efuse.qfprom_min_vol = drvdata->qfprom_min_vol;
> + priv->dev = dev;
> +
> + qfpbase = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +
> + priv->qfpbase = devm_ioremap_resource(dev, qfpbase);
> + if (IS_ERR(priv->qfpbase)) {
> + ret = PTR_ERR(priv->qfpbase);
> + goto err;
> + }
> +
> + qfpraw = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> +
> + priv->qfpraw = devm_ioremap_resource(dev, qfpraw);
> + if (IS_ERR(priv->qfpraw)) {
> + ret = PTR_ERR(priv->qfpraw);
> + goto err;
> + }
> +
> + priv->qfpraw_start = qfpraw->start - qfpbase->start;
> + priv->qfpraw_end = qfpraw->end - qfpbase->start;
> +
> + qfpmap = platform_get_resource(pdev, IORESOURCE_MEM, 2);
> +
> + priv->qfpmap = devm_ioremap_resource(dev, qfpmap);
> + if (IS_ERR(priv->qfpmap)) {
> + ret = PTR_ERR(priv->qfpmap);
> + goto err;
> + }
> +
> + priv->vcc = devm_regulator_get(&pdev->dev, "vcc");
I see no reference to this regulator in dt bindings.
> + if (IS_ERR(priv->vcc)) {
> + ret = PTR_ERR(priv->vcc);
> + if (ret == -ENODEV)
> + ret = -EPROBE_DEFER;
Can you explain what is going on here?
> +
> + goto err;
> + }
> +
> + priv->secclk = devm_clk_get(dev, "secclk");
> + if (IS_ERR(priv->secclk)) {
> + ret = PTR_ERR(priv->secclk);
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev, "secclk error getting : %d\n", ret);
> + goto err;
> + }
> +
> + ret = clk_prepare_enable(priv->secclk);
> + if (ret) {
> + dev_err(dev, "clk_prepare_enable() failed\n");
> + goto err;
> + }
> +
> + econfig = devm_kzalloc(dev, sizeof(*econfig), GFP_KERNEL);
> + if (!econfig)
Why not disabling the clk here?
> + return -ENOMEM;
> +
> + econfig->dev = dev;
> + econfig->name = "qfprom-efuse";
> + econfig->stride = 1;
> + econfig->word_size = 1;
> + econfig->reg_read = qfprom_efuse_reg_read;
> + econfig->reg_write = qfprom_efuse_reg_write;
> + econfig->size = resource_size(qfpraw);
> + econfig->priv = priv;
> +
> + nvmem = devm_nvmem_register(dev, econfig);
> +
> + return PTR_ERR_OR_ZERO(nvmem);
probably you should check the nvmem here before returning to disable the
clk properly.
> +
> +err:
> + clk_disable_unprepare(priv->secclk);
> + return ret;
> +}
> +
> +static const struct qfprom_efuse_platform_data sc7180_qfp_efuse_data = {
> + .name = "sc7180-qfprom-efuse",
Redundant.
> + .fuse_blow_time_in_us = 10,
> + .accel_value = 0xD10,
> + .accel_reset_value = 0x800,
> + .qfprom_blow_timer_value = 25,
> + .qfprom_blow_reset_freq = 19200000,
> + .qfprom_blow_set_freq = 4800000,
> + .qfprom_max_vol = 1904000,
> + .qfprom_min_vol = 1800000,
> +};
> +
> +static const struct of_device_id qfprom_efuse_of_match[] = {
> + {
> + .compatible = "qcom,sc7180-qfprom-efuse",
> + .data = &sc7180_qfp_efuse_data
> + },
> + {/* sentinel */},
> +};
> +
> +MODULE_DEVICE_TABLE(of, qfprom_efuse_of_match);
> +
> +static struct platform_driver qfprom_efuse_driver = {
> + .probe = qfprom_efuse_probe,
> + .driver = {
> + .name = "sc7180-qfprom-efuse",
> + .of_match_table = qfprom_efuse_of_match,
> + },
> +};
> +
> +module_platform_driver(qfprom_efuse_driver);
> +MODULE_DESCRIPTION("QTI QFPROM Efuse driver");
> +MODULE_LICENSE("GPL v2");
>
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