* [PATCH 06/16] ARM: dts: at91: sama5d2: Move flx0 definitions in the SoC dtsi
From: Tudor.Ambarus @ 2020-05-14 5:03 UTC (permalink / raw)
To: alexandre.belloni, Ludovic.Desroches, Nicolas.Ferre
Cc: robh+dt, devicetree, linux-arm-kernel, linux-kernel,
Codrin.Ciubotariu, Tudor.Ambarus
In-Reply-To: <20200514050301.147442-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
There is a single functional change in this patch. With the move of the
flx0 uart5 definition in the SoC dtsi, the uart5 from
at91-sama5d27_wlsom1_ek.dts inherits the following optional property:
atmel,fifo-size = <32>;
This particular change was tested by Codrin.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Tested-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
---
arch/arm/boot/dts/at91-kizbox3_common.dtsi | 13 ------
arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts | 12 ------
arch/arm/boot/dts/at91-sama5d2_icp.dts | 6 ---
arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 7 ----
arch/arm/boot/dts/at91-sama5d2_xplained.dts | 7 +---
arch/arm/boot/dts/sama5d2.dtsi | 40 +++++++++++++++++++
6 files changed, 41 insertions(+), 44 deletions(-)
diff --git a/arch/arm/boot/dts/at91-kizbox3_common.dtsi b/arch/arm/boot/dts/at91-kizbox3_common.dtsi
index 4351a8d32225..7c3076e245ef 100644
--- a/arch/arm/boot/dts/at91-kizbox3_common.dtsi
+++ b/arch/arm/boot/dts/at91-kizbox3_common.dtsi
@@ -299,21 +299,8 @@
status = "disabled";
uart5: serial@200 {
- compatible = "atmel,at91sam9260-usart";
- reg = <0x200 0x400>;
- interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
- dmas = <&dma0
- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
- | AT91_XDMAC_DT_PERID(11))>,
- <&dma0
- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
- | AT91_XDMAC_DT_PERID(12))>;
- dma-names = "tx", "rx";
- clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
- clock-names = "usart";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx0_default>;
- atmel,fifo-size = <32>;
atmel,use-dma-rx;
atmel,use-dma-tx;
status = "disabled";
diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts
index 6b8461278950..6b38fa3f5568 100644
--- a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts
@@ -77,18 +77,6 @@
status = "okay";
uart5: serial@200 {
- compatible = "atmel,at91sam9260-usart";
- reg = <0x200 0x200>;
- interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
- dmas = <&dma0
- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
- AT91_XDMAC_DT_PERID(11))>,
- <&dma0
- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
- AT91_XDMAC_DT_PERID(12))>;
- dma-names = "tx", "rx";
- clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
- clock-names = "usart";
pinctrl-0 = <&pinctrl_flx0_default>;
pinctrl-names = "default";
atmel,use-dma-rx;
diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts
index 23f413afb333..4a01ab8e7e70 100644
--- a/arch/arm/boot/dts/at91-sama5d2_icp.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts
@@ -105,15 +105,9 @@
status = "okay";
spi2: spi@400 {
- compatible = "atmel,at91rm9200-spi";
- reg = <0x400 0x200>;
- interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
- clock-names = "spi_clk";
cs-gpios = <&pioA PIN_PC0 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus2_spi &pinctrl_ksz_spi_cs>;
- atmel,fifo-size = <16>;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
index 32435ce1dab2..8ad3a9c6c536 100644
--- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
@@ -191,20 +191,13 @@
status = "okay";
i2c2: i2c@600 {
- compatible = "atmel,sama5d2-i2c";
- reg = <0x600 0x200>;
- interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <0>, <0>;
dma-names = "tx", "rx";
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_flx0_default>;
pinctrl-1 = <&pinctrl_flx0_gpio>;
sda-gpios = <&pioA PIN_PB28 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PB29 GPIO_ACTIVE_HIGH>;
- atmel,fifo-size = <16>;
status = "okay";
};
};
diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index a5046f8257ad..da4442715ea5 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -327,14 +327,9 @@
status = "disabled"; /* conflict with ISC_D2 & ISC_D3 data pins */
uart5: serial@200 {
- compatible = "atmel,at91sam9260-usart";
- reg = <0x200 0x200>;
- interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
- clock-names = "usart";
+ dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flx0_default>;
- atmel,fifo-size = <32>;
status = "okay";
};
};
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 79ed7bd02df6..acb91908bd74 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -635,6 +635,46 @@
#size-cells = <1>;
ranges = <0x0 0xf8034000 0x800>;
status = "disabled";
+
+ uart5: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
+ clock-names = "usart";
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(11))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(12))>;
+ dma-names = "tx", "rx";
+ atmel,fifo-size = <32>;
+ status = "disabled";
+ };
+
+ spi2: spi@400 {
+ compatible = "atmel,at91rm9200-spi";
+ reg = <0x400 0x200>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
+ clock-names = "spi_clk";
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@600 {
+ compatible = "atmel,sama5d2-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
};
flx1: flexcom@f8038000 {
--
2.23.0
^ permalink raw reply related
* [PATCH 04/16] ARM: dts: at91: sama5d2: Move flx2 definitions in the SoC dtsi
From: Tudor.Ambarus @ 2020-05-14 5:03 UTC (permalink / raw)
To: alexandre.belloni, Ludovic.Desroches, Nicolas.Ferre
Cc: robh+dt, devicetree, linux-arm-kernel, linux-kernel,
Codrin.Ciubotariu, Tudor.Ambarus
In-Reply-To: <20200514050301.147442-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
The Flexcom IP is part of the sama5d2 SoC. Move the flx2 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
arch/arm/boot/dts/at91-sama5d2_icp.dts | 12 ------------
arch/arm/boot/dts/sama5d2.dtsi | 18 ++++++++++++++++++
2 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts
index 8a4336e12a60..23f413afb333 100644
--- a/arch/arm/boot/dts/at91-sama5d2_icp.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts
@@ -160,18 +160,6 @@
status = "okay";
uart7: serial@200 {
- compatible = "atmel,at91sam9260-usart";
- reg = <0x200 0x200>;
- interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
- dmas = <&dma0
- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
- AT91_XDMAC_DT_PERID(15))>,
- <&dma0
- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
- AT91_XDMAC_DT_PERID(16))>;
- dma-names = "tx", "rx";
- clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
- clock-names = "usart";
pinctrl-0 = <&pinctrl_flx2_default>;
pinctrl-names = "default";
atmel,use-dma-rx;
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 5e84cde8226a..89064225e9aa 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -794,6 +794,24 @@
#size-cells = <1>;
ranges = <0x0 0xfc010000 0x800>;
status = "disabled";
+
+ uart7: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
+ clock-names = "usart";
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(15))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(16))>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
};
flx3: flexcom@fc014000 {
--
2.23.0
^ permalink raw reply related
* [PATCH 05/16] ARM: dts: at91: sama5d2: Move flx1 definitions in the SoC dtsi
From: Tudor.Ambarus @ 2020-05-14 5:03 UTC (permalink / raw)
To: alexandre.belloni, Ludovic.Desroches, Nicolas.Ferre
Cc: robh+dt, devicetree, linux-arm-kernel, linux-kernel,
Codrin.Ciubotariu, Tudor.Ambarus
In-Reply-To: <20200514050301.147442-1-tudor.ambarus@microchip.com>
From: Tudor Ambarus <tudor.ambarus@microchip.com>
The Flexcom IP is part of the sama5d2 SoC. Move the flx0 node together
with its function definitions in sama5d2.dtsi. Boards will just fill
the pins and enable the desired functions.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 7 -----
arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi | 12 ---------
arch/arm/boot/dts/sama5d2.dtsi | 29 +++++++++++++++++++++
3 files changed, 29 insertions(+), 19 deletions(-)
diff --git a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
index abbf14e29d85..a0deff15fb9a 100644
--- a/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d27_som1_ek.dts
@@ -126,20 +126,13 @@
status = "okay";
i2c3: i2c@600 {
- compatible = "atmel,sama5d2-i2c";
- reg = <0x600 0x200>;
- interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <0>, <0>;
dma-names = "tx", "rx";
i2c-analog-filter;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mikrobus_i2c>;
- atmel,fifo-size = <16>;
status = "okay";
};
};
diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
index bea3d60b9722..a06700e53e4c 100644
--- a/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
+++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1.dtsi
@@ -36,18 +36,6 @@
atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
uart6: serial@200 {
- compatible = "atmel,at91sam9260-usart";
- reg = <0x200 0x200>;
- interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
- dmas = <&dma0
- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
- AT91_XDMAC_DT_PERID(13))>,
- <&dma0
- (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
- AT91_XDMAC_DT_PERID(14))>;
- dma-names = "tx", "rx";
- clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
- clock-names = "usart";
pinctrl-0 = <&pinctrl_flx1_default>;
pinctrl-names = "default";
};
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 89064225e9aa..79ed7bd02df6 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -645,6 +645,35 @@
#size-cells = <1>;
ranges = <0x0 0xf8038000 0x800>;
status = "disabled";
+
+ uart6: serial@200 {
+ compatible = "atmel,at91sam9260-usart";
+ reg = <0x200 0x200>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
+ clock-names = "usart";
+ dmas = <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(13))>,
+ <&dma0
+ (AT91_XDMAC_DT_MEM_IF(0) |
+ AT91_XDMAC_DT_PER_IF(1) |
+ AT91_XDMAC_DT_PERID(14))>;
+ dma-names = "tx", "rx";
+ status = "disabled";
+ };
+
+ i2c3: i2c@600 {
+ compatible = "atmel,sama5d2-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
+ atmel,fifo-size = <16>;
+ status = "disabled";
+ };
};
securam: sram@f8044000 {
--
2.23.0
^ permalink raw reply related
* Re: [PATCH 1/2] dt-bindings: pinctrl: qcom: Add sm8250 pinctrl bindings
From: Bjorn Andersson @ 2020-05-14 6:04 UTC (permalink / raw)
To: Rob Herring
Cc: Linus Walleij, linux-kernel, linux-arm-msm, linux-gpio,
devicetree
In-Reply-To: <20200429213453.GA32114@bogus>
On Wed 29 Apr 14:34 PDT 2020, Rob Herring wrote:
> On Thu, Apr 16, 2020 at 11:19:06PM -0700, Bjorn Andersson wrote:
> > diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm8250-pinctrl.yaml
[..]
> > +#PIN CONFIGURATION NODES
> > +patternProperties:
> > + '^.*$':
> > + if:
> > + type: object
> > + then:
>
> Needs a $ref to the standard properties.
>
> Would be good to show a child node in the example too. (And try having
> an error in a standard property type to verify you get an error).
>
Finally looked into this. By $ref'ing pinmux-node.yaml I can drop pins
and function from below properties, and by $ref'ing pincfg-node.yaml I
can drop the pinconf entries listed.
But how do I $ref both?
What's the appropriate method for amending pins, function and
drive-strength with the more specific value set? Should I both $ref them
and list them here?
How do I limit which standard properties are actually supported in this
binding?
Thanks,
Bjorn
> > + properties:
> > + pins:
> > + description:
> > + List of gpio pins affected by the properties specified in this
> > + subnode.
> > + items:
> > + oneOf:
> > + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
> > + - enum: [ sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
> > + minItems: 1
> > + maxItems: 36
> > +
> > + function:
> > + description:
> > + Specify the alternative function to be configured for the specified
> > + pins.
> > +
> > + enum: [ aoss_cti, atest, audio_ref, cam_mclk, cci_async, cci_i2c,
> > + cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4, cri_trng,
> > + cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
> > + ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
> > + ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
> > + mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
> > + mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck, mi2s1_ws,
> > + mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, pci_e0, pci_e1,
> > + pci_e2, phase_flag, pll_bist, pll_bypassnl, pll_clk, pll_reset,
> > + pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qspi0, qspi1, qspi2, qspi3,
> > + qspi_clk, qspi_cs, qup0, qup1, qup10, qup11, qup12, qup13, qup14,
> > + qup15, qup16, qup17, qup18, qup19, qup2, qup3, qup4, qup5, qup6,
> > + qup7, qup8, qup9, qup_l4, qup_l5, qup_l6, sd_write, sdc40, sdc41,
> > + sdc42, sdc43, sdc4_clk, sdc4_cmd, sec_mi2s, sp_cmu, tgu_ch0, tgu_ch1,
> > + tgu_ch2, tgu_ch3, tsense_pwm1, tsense_pwm2, tsif0_clk, tsif0_data,
> > + tsif0_en, tsif0_error, tsif0_sync, tsif1_clk, tsif1_data, tsif1_en,
> > + tsif1_error, tsif1_sync, usb2phy_ac, usb_phy, vsense_trigger ]
> > +
> > + drive-strength:
> > + enum: [2, 4, 6, 8, 10, 12, 14, 16]
> > + default: 2
> > + description:
> > + Selects the drive strength for the specified pins, in mA.
> > +
> > + bias-pull-down: true
> > +
> > + bias-pull-up: true
> > +
> > + bias-disable: true
> > +
> > + output-high: true
> > +
> > + output-low: true
> > +
> > + required:
> > + - pins
> > + - function
> > +
> > + additionalProperties: false
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - reg-names
> > + - interrupts
> > + - interrupt-controller
> > + - '#interrupt-cells'
> > + - gpio-controller
> > + - '#gpio-cells'
> > + - gpio-ranges
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + pinctrl@1f00000 {
> > + compatible = "qcom,sm8250-pinctrl";
> > + reg = <0x0f100000 0x300000>,
> > + <0x0f500000 0x300000>,
> > + <0x0f900000 0x300000>;
> > + reg-names = "west", "south", "north";
> > + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + gpio-ranges = <&tlmm 0 0 180>;
> > + wakeup-parent = <&pdc>;
> > + };
> > --
> > 2.24.0
> >
^ permalink raw reply
* Re: [PATCHv1 01/19] kobject: increase allowed number of uevent variables
From: Greg Kroah-Hartman @ 2020-05-14 6:11 UTC (permalink / raw)
To: Sebastian Reichel
Cc: Sebastian Reichel, Rob Herring, Rafael J . Wysocki, linux-pm,
devicetree, linux-kernel, kernel
In-Reply-To: <20200513185615.508236-2-sebastian.reichel@collabora.com>
On Wed, May 13, 2020 at 08:55:57PM +0200, Sebastian Reichel wrote:
> SBS battery driver exposes 32 power supply properties now,
> which will result in uevent failure on (un)plugging the
> battery. Other drivers (e.g. bq27xxx) are also coming close
> to this limit, so increase it.
>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> ---
> include/linux/kobject.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/linux/kobject.h b/include/linux/kobject.h
> index e2ca0a292e21..75e822569e39 100644
> --- a/include/linux/kobject.h
> +++ b/include/linux/kobject.h
> @@ -29,7 +29,7 @@
> #include <linux/uidgid.h>
>
> #define UEVENT_HELPER_PATH_LEN 256
> -#define UEVENT_NUM_ENVP 32 /* number of env pointers */
> +#define UEVENT_NUM_ENVP 64 /* number of env pointers */
> #define UEVENT_BUFFER_SIZE 2048 /* buffer for the variables */
>
> #ifdef CONFIG_UEVENT_HELPER
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
^ permalink raw reply
* [PATCH V3 0/8] Tegra XUSB charger detect support
From: Nagarjuna Kristam @ 2020-05-14 6:22 UTC (permalink / raw)
To: balbi, gregkh, thierry.reding, jonathanh, mark.rutland, robh+dt,
kishon
Cc: devicetree, linux-tegra, linux-usb, linux-kernel,
Nagarjuna Kristam
This patch series adds charger detect support on XUSB hardware used in
Tegra210 and Tegra186 SoCs.
This patchset is composed with :
- dt bindings of XUSB Pad Controller
- Tegra XUSB device mode driver to add vbus_draw support
- Tegra PHY driver for charger detect support
Tests done:
- Connect USB cable from ubuntu host to micro-B port of DUT to detect
SDP_TYPE charger
- Connect USB cable from external powered USB hub(which inturn connects
to ubuntu host) to micro-B port of DUT to detect CDP_TYPE charger.
- Connect USB cable from USB charger to micro-B port of DUT to detect
DCP_TYPE charger.
DUT: Jetson-tx1, Jetson tx2.
V3:
- Added ACKed-by details for PHY driver and DT changes.
- Functions and its arguments are aligned.
- Tabs are used for alignment of MACRO's
- For vbus_draw USDC callback, usb_phy set_power error is propogated.
- Fixed various comments given by thierry.
V2:
- Added ACKed-by details for DT patches.
- All patches rebased.
Nagarjuna Kristam (8):
dt-bindings: phy: tegra-xusb: Add charger-detect property
usb: gadget: tegra-xudc: Add vbus_draw support
phy: tegra: xusb: Add support for UTMI pad power control
phy: tegra: xusb: Add USB2 pad power control support for Tegra210
phy: tegra: xusb: Add soc ops API to enable UTMI PAD protection
phy: tegra: xusb: Add support for charger detect
phy: tegra: xusb: Enable charger detect for Tegra186
phy: tegra: xusb: Enable charger detect for Tegra210
.../bindings/phy/nvidia,tegra124-xusb-padctl.txt | 4 +
drivers/phy/tegra/Makefile | 2 +-
drivers/phy/tegra/cd.c | 283 +++++++++++++++++++++
drivers/phy/tegra/xusb-tegra186.c | 92 +++++--
drivers/phy/tegra/xusb-tegra210.c | 223 +++++++++++-----
drivers/phy/tegra/xusb.c | 80 ++++++
drivers/phy/tegra/xusb.h | 22 ++
drivers/usb/gadget/udc/tegra-xudc.c | 17 ++
8 files changed, 638 insertions(+), 85 deletions(-)
create mode 100644 drivers/phy/tegra/cd.c
--
2.7.4
^ permalink raw reply
* [PATCH V3 1/8] dt-bindings: phy: tegra-xusb: Add charger-detect property
From: Nagarjuna Kristam @ 2020-05-14 6:22 UTC (permalink / raw)
To: balbi, gregkh, thierry.reding, jonathanh, mark.rutland, robh+dt,
kishon
Cc: devicetree, linux-tegra, linux-usb, linux-kernel,
Nagarjuna Kristam
In-Reply-To: <1589437363-16727-1-git-send-email-nkristam@nvidia.com>
Add nvidia,charger-detect boolean property for Tegra210 and Tegra186
platforms. This property is used to inform driver to perform charger
detection on corresponding USB 2 port.
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Thierry Reding <treding@nvidia.com>
---
V3:
- Added Acked-by updates to commit message.
---
V2:
- Added Acked-by updates to commit message.
---
Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
index 38c5fa2..9b2d2dd 100644
--- a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
+++ b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
@@ -190,6 +190,10 @@ Required properties for OTG/Peripheral capable USB2 ports:
and peripheral roles. Connector should be added as subnode.
See usb/usb-conn-gpio.txt.
+Optional properties for OTG/Peripheral capable USB2 ports:
+- nvidia,charger-detect: A boolean property whose presence inform driver to
+ perform charger-detect activity.
+
Optional properties:
- nvidia,internal: A boolean property whose presence determines that a port
is internal. In the absence of this property the port is considered to be
--
2.7.4
^ permalink raw reply related
* [PATCH 1/2] dt-bindings: rtc: Convert MXC RTC to json-schema
From: Anson Huang @ 2020-05-14 6:13 UTC (permalink / raw)
To: a.zummo, alexandre.belloni, robh+dt, tremyfr, p.bruenn, linux-rtc,
devicetree, linux-kernel
Cc: Linux-imx
Convert the MXC RTC binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
Documentation/devicetree/bindings/rtc/rtc-mxc.txt | 26 ----------
Documentation/devicetree/bindings/rtc/rtc-mxc.yaml | 59 ++++++++++++++++++++++
2 files changed, 59 insertions(+), 26 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/rtc/rtc-mxc.txt
create mode 100644 Documentation/devicetree/bindings/rtc/rtc-mxc.yaml
diff --git a/Documentation/devicetree/bindings/rtc/rtc-mxc.txt b/Documentation/devicetree/bindings/rtc/rtc-mxc.txt
deleted file mode 100644
index 5bcd31d..0000000
--- a/Documentation/devicetree/bindings/rtc/rtc-mxc.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-* Real Time Clock of the i.MX SoCs
-
-RTC controller for the i.MX SoCs
-
-Required properties:
-- compatible: Should be "fsl,imx1-rtc" or "fsl,imx21-rtc".
-- reg: physical base address of the controller and length of memory mapped
- region.
-- interrupts: IRQ line for the RTC.
-- clocks: should contain two entries:
- * one for the input reference
- * one for the the SoC RTC
-- clock-names: should contain:
- * "ref" for the input reference clock
- * "ipg" for the SoC RTC clock
-
-Example:
-
-rtc@10007000 {
- compatible = "fsl,imx21-rtc";
- reg = <0x10007000 0x1000>;
- interrupts = <22>;
- clocks = <&clks IMX27_CLK_CKIL>,
- <&clks IMX27_CLK_RTC_IPG_GATE>;
- clock-names = "ref", "ipg";
-};
diff --git a/Documentation/devicetree/bindings/rtc/rtc-mxc.yaml b/Documentation/devicetree/bindings/rtc/rtc-mxc.yaml
new file mode 100644
index 0000000..d5c5ccd
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/rtc-mxc.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/rtc-mxc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Real Time Clock of the i.MX SoCs
+
+allOf:
+ - $ref: "rtc.yaml#"
+
+maintainers:
+ - Philippe Reynes <tremyfr@gmail.com>
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx1-rtc
+ - fsl,imx21-rtc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: input reference
+ - description: the SoC RTC clock
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: ref
+ - const: ipg
+ maxItems: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx27-clock.h>
+
+ rtc@10007000 {
+ compatible = "fsl,imx21-rtc";
+ reg = <0x10007000 0x1000>;
+ interrupts = <22>;
+ clocks = <&clks IMX27_CLK_CKIL>,
+ <&clks IMX27_CLK_RTC_IPG_GATE>;
+ clock-names = "ref", "ipg";
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH V3 4/8] phy: tegra: xusb: Add USB2 pad power control support for Tegra210
From: Nagarjuna Kristam @ 2020-05-14 6:22 UTC (permalink / raw)
To: balbi, gregkh, thierry.reding, jonathanh, mark.rutland, robh+dt,
kishon
Cc: devicetree, linux-tegra, linux-usb, linux-kernel,
Nagarjuna Kristam
In-Reply-To: <1589437363-16727-1-git-send-email-nkristam@nvidia.com>
Add USB2 pad power on and off API's for TEgra210 and provide its control
via soc ops. It can be used by operations like charger detect to power on
and off USB2 pad if needed.
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
---
V3:
- Added Acked-by updates to commit message.
---
V2:
- Patch re-based.
---
drivers/phy/tegra/xusb-tegra210.c | 190 ++++++++++++++++++++++++++------------
1 file changed, 133 insertions(+), 57 deletions(-)
diff --git a/drivers/phy/tegra/xusb-tegra210.c b/drivers/phy/tegra/xusb-tegra210.c
index 66bd461..caf0890 100644
--- a/drivers/phy/tegra/xusb-tegra210.c
+++ b/drivers/phy/tegra/xusb-tegra210.c
@@ -994,6 +994,128 @@ static int tegra210_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl,
return 0;
}
+static void tegra210_usb2_bias_pad_power_on(struct tegra_xusb_usb2_pad *pad)
+{
+ struct tegra_xusb_padctl *padctl = pad->base.padctl;
+ u32 value;
+
+ if (pad->enable++ > 0)
+ return;
+
+ dev_dbg(padctl->dev, "power on BIAS PAD & USB2 tracking\n");
+
+ if (clk_prepare_enable(pad->clk))
+ dev_warn(padctl->dev, "failed to enable BIAS PAD & USB2 tracking\n");
+
+ value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
+ value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK <<
+ XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT) |
+ (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK <<
+ XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT));
+ value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL <<
+ XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT) |
+ (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL <<
+ XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT);
+ padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
+ value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD;
+ padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
+
+ udelay(1);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
+ value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK;
+ padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
+
+ udelay(50);
+}
+
+static void tegra210_usb2_bias_pad_power_off(struct tegra_xusb_usb2_pad *pad)
+{
+ struct tegra_xusb_padctl *padctl = pad->base.padctl;
+ u32 value;
+
+ if (WARN_ON(pad->enable == 0))
+ return;
+
+ if (--pad->enable > 0)
+ return;
+
+ dev_dbg(padctl->dev, "power off USB2 tracking\n");
+
+ value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
+ value |= XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD;
+ padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
+
+ clk_disable_unprepare(pad->clk);
+}
+
+/* must be called under padctl->lock */
+void tegra210_usb2_pad_power_on(struct phy *phy)
+{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
+ struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ unsigned int index = lane->index;
+ u32 value;
+
+ if (!phy)
+ return;
+
+ if (usb2->powered_on)
+ return;
+
+ dev_info(padctl->dev, "power on UTMI pads %d\n", index);
+
+ tegra210_usb2_bias_pad_power_on(pad);
+
+ udelay(2);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
+ value &= ~XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD;
+ padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
+
+ value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
+ value &= ~XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR;
+ padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
+
+ usb2->powered_on = true;
+}
+
+/* must be called under padctl->lock */
+void tegra210_usb2_pad_power_down(struct phy *phy)
+{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
+ struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ unsigned int index = lane->index;
+ u32 value;
+
+ if (!phy)
+ return;
+
+ if (!usb2->powered_on)
+ return;
+
+ dev_info(padctl->dev, "power down UTMI pad %d\n", index);
+
+ value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
+ value |= XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD;
+ padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
+
+ value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
+ value |= XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR;
+ padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
+
+ udelay(2);
+
+ tegra210_usb2_bias_pad_power_off(pad);
+ usb2->powered_on = false;
+}
+
static int tegra210_usb2_phy_set_mode(struct phy *phy, enum phy_mode mode,
int submode)
{
@@ -1037,7 +1159,6 @@ static int tegra210_usb2_phy_power_on(struct phy *phy)
{
struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
- struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad);
struct tegra_xusb_padctl *padctl = lane->pad->padctl;
struct tegra210_xusb_padctl *priv;
struct tegra_xusb_usb2_port *port;
@@ -1053,6 +1174,8 @@ static int tegra210_usb2_phy_power_on(struct phy *phy)
priv = to_tegra210_xusb_padctl(padctl);
+ mutex_lock(&padctl->lock);
+
if (port->usb3_port_fake != -1) {
value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(
@@ -1148,62 +1271,21 @@ static int tegra210_usb2_phy_power_on(struct phy *phy)
if (port->supply && port->mode == USB_DR_MODE_HOST) {
err = regulator_enable(port->supply);
- if (err)
+ if (err) {
+ mutex_unlock(&padctl->lock);
return err;
+ }
}
- mutex_lock(&padctl->lock);
-
- if (pad->enable > 0) {
- pad->enable++;
- mutex_unlock(&padctl->lock);
- return 0;
- }
-
- err = clk_prepare_enable(pad->clk);
- if (err)
- goto disable_regulator;
+ tegra210_usb2_pad_power_on(phy);
- value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
- value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK <<
- XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT) |
- (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK <<
- XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT));
- value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL <<
- XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT) |
- (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL <<
- XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT);
- padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
- value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD;
- padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
-
- udelay(1);
-
- value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
- value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK;
- padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
-
- udelay(50);
-
- clk_disable_unprepare(pad->clk);
-
- pad->enable++;
mutex_unlock(&padctl->lock);
-
return 0;
-
-disable_regulator:
- regulator_disable(port->supply);
- mutex_unlock(&padctl->lock);
- return err;
}
static int tegra210_usb2_phy_power_off(struct phy *phy)
{
struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
- struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad);
struct tegra_xusb_padctl *padctl = lane->pad->padctl;
struct tegra_xusb_usb2_port *port;
u32 value;
@@ -1217,6 +1299,8 @@ static int tegra210_usb2_phy_power_off(struct phy *phy)
mutex_lock(&padctl->lock);
+ tegra210_usb2_pad_power_down(phy);
+
if (port->usb3_port_fake != -1) {
value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(
@@ -1243,18 +1327,8 @@ static int tegra210_usb2_phy_power_off(struct phy *phy)
padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
}
- if (WARN_ON(pad->enable == 0))
- goto out;
-
- if (--pad->enable > 0)
- goto out;
-
- value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
- value |= XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD;
- padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
-
-out:
regulator_disable(port->supply);
+
mutex_unlock(&padctl->lock);
return 0;
}
@@ -2215,6 +2289,8 @@ static const struct tegra_xusb_padctl_ops tegra210_xusb_padctl_ops = {
.hsic_set_idle = tegra210_hsic_set_idle,
.vbus_override = tegra210_xusb_padctl_vbus_override,
.utmi_port_reset = tegra210_utmi_port_reset,
+ .utmi_pad_power_on = tegra210_usb2_pad_power_on,
+ .utmi_pad_power_down = tegra210_usb2_pad_power_down,
};
static const char * const tegra210_xusb_padctl_supply_names[] = {
--
2.7.4
^ permalink raw reply related
* [PATCH V3 6/8] phy: tegra: xusb: Add support for charger detect
From: Nagarjuna Kristam @ 2020-05-14 6:22 UTC (permalink / raw)
To: balbi, gregkh, thierry.reding, jonathanh, mark.rutland, robh+dt,
kishon
Cc: devicetree, linux-tegra, linux-usb, linux-kernel,
Nagarjuna Kristam
In-Reply-To: <1589437363-16727-1-git-send-email-nkristam@nvidia.com>
Perform charger-detect operation if corresponding dt property is enabled.
Update usb-phy with the detected charger state and max current values.
Register charger-detect API's of usb-phy to provide needed functionalities.
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
---
V3:
- Allighed functions and its arguments.
- replaced spaced by tabs for MACRO definition allignments.
- Unified primary and secondary charger detect API's.
- Used readl_poll_timeout instead of while loop condition check for register.
- Fixed other comments as per inputs from Thierry.
---
V2:
- Patch re-based.
---
drivers/phy/tegra/Makefile | 2 +-
drivers/phy/tegra/cd.c | 283 +++++++++++++++++++++++++++++++++++++++++++++
drivers/phy/tegra/xusb.c | 80 +++++++++++++
drivers/phy/tegra/xusb.h | 7 ++
4 files changed, 371 insertions(+), 1 deletion(-)
create mode 100644 drivers/phy/tegra/cd.c
diff --git a/drivers/phy/tegra/Makefile b/drivers/phy/tegra/Makefile
index 89b8406..befdfc4 100644
--- a/drivers/phy/tegra/Makefile
+++ b/drivers/phy/tegra/Makefile
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_PHY_TEGRA_XUSB) += phy-tegra-xusb.o
-phy-tegra-xusb-y += xusb.o
+phy-tegra-xusb-y += xusb.o cd.o
phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_124_SOC) += xusb-tegra124.o
phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_132_SOC) += xusb-tegra124.o
phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o
diff --git a/drivers/phy/tegra/cd.c b/drivers/phy/tegra/cd.c
new file mode 100644
index 0000000..fddbe4c
--- /dev/null
+++ b/drivers/phy/tegra/cd.c
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+ */
+
+#include <linux/delay.h>
+#include <linux/iopoll.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+
+#include "xusb.h"
+
+/* Data contact detection timeout */
+#define TDCD_TIMEOUT_MS 400
+
+#define USB2_BATTERY_CHRG_OTGPADX_CTL0(x) (0x80 + (x) * 0x40)
+#define PD_CHG (1 << 0)
+#define VDCD_DET_FILTER_EN (1 << 4)
+#define VDAT_DET (1 << 5)
+#define VDAT_DET_FILTER_EN (1 << 8)
+#define OP_SINK_EN (1 << 9)
+#define OP_SRC_EN (1 << 10)
+#define ON_SINK_EN (1 << 11)
+#define ON_SRC_EN (1 << 12)
+#define OP_I_SRC_EN (1 << 13)
+#define ZIP_FILTER_EN (1 << 21)
+#define ZIN_FILTER_EN (1 << 25)
+#define DCD_DETECTED (1 << 26)
+
+#define USB2_BATTERY_CHRG_OTGPADX_CTL1(x) (0x84 + (x) * 0x40)
+#define PD_VREG (1 << 6)
+#define VREG_LEV(x) (((x) & 0x3) << 7)
+#define VREG_DIR(x) (((x) & 0x3) << 11)
+#define VREG_DIR_IN VREG_DIR(1)
+#define VREG_DIR_OUT VREG_DIR(2)
+#define USBOP_RPD_OVRD (1 << 16)
+#define USBOP_RPD_OVRD_VAL (1 << 17)
+#define USBOP_RPU_OVRD (1 << 18)
+#define USBOP_RPU_OVRD_VAL (1 << 19)
+#define USBON_RPD_OVRD (1 << 20)
+#define USBON_RPD_OVRD_VAL (1 << 21)
+#define USBON_RPU_OVRD (1 << 22)
+#define USBON_RPU_OVRD_VAL (1 << 23)
+
+#define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x88 + (x) * 0x40)
+#define USB2_OTG_PD2 (1 << 27)
+#define USB2_OTG_PD2_OVRD_EN (1 << 28)
+#define USB2_OTG_PD_ZI (1 << 29)
+
+#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0 (0x280)
+#define TDCD_DBNC(x) (((x) & 0x7ff) << 0)
+
+static void
+tegra_xusb_padctl_set_debounce_time(struct tegra_xusb_padctl *padctl,
+ u32 debounce)
+{
+ u32 value;
+
+ value = padctl_readl(padctl,
+ XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0);
+ value &= ~(TDCD_DBNC(0));
+ value |= TDCD_DBNC(debounce);
+ padctl_writel(padctl, value,
+ XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0);
+}
+
+static void
+tegra_xusb_padctl_charger_detect_on(struct tegra_xusb_padctl *padctl, u32 index)
+{
+ u32 value;
+
+ value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
+ value &= ~USB2_OTG_PD_ZI;
+ padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
+
+ value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
+ value |= (USB2_OTG_PD2 | USB2_OTG_PD2_OVRD_EN);
+ padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
+
+ value = padctl_readl(padctl, USB2_BATTERY_CHRG_OTGPADX_CTL0(index));
+ value &= ~PD_CHG;
+ padctl_writel(padctl, value, USB2_BATTERY_CHRG_OTGPADX_CTL0(index));
+
+ /* Set DP/DN Pull up/down to zero by default */
+ value = padctl_readl(padctl, USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
+ value &= ~(USBOP_RPD_OVRD_VAL | USBOP_RPU_OVRD_VAL |
+ USBON_RPD_OVRD_VAL | USBON_RPU_OVRD_VAL);
+ value |= (USBOP_RPD_OVRD | USBOP_RPU_OVRD |
+ USBON_RPD_OVRD | USBON_RPU_OVRD);
+ padctl_writel(padctl, value, USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
+
+ /* Disable DP/DN as src/sink */
+ value = padctl_readl(padctl, USB2_BATTERY_CHRG_OTGPADX_CTL0(index));
+ value &= ~(OP_SRC_EN | ON_SINK_EN |
+ ON_SRC_EN | OP_SINK_EN);
+ padctl_writel(padctl, value, USB2_BATTERY_CHRG_OTGPADX_CTL0(index));
+}
+
+static void
+tegra_xusb_padctl_charger_detect_off(struct tegra_xusb_padctl *padctl,
+ u32 index)
+{
+ u32 value;
+
+ value = padctl_readl(padctl, USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
+ value &= ~(USBOP_RPD_OVRD | USBOP_RPU_OVRD |
+ USBON_RPD_OVRD | USBON_RPU_OVRD);
+ padctl_writel(padctl, value, USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
+
+ /* power down necessary stuff */
+ value = padctl_readl(padctl, USB2_BATTERY_CHRG_OTGPADX_CTL0(index));
+ value |= PD_CHG;
+ padctl_writel(padctl, value, USB2_BATTERY_CHRG_OTGPADX_CTL0(index));
+
+ value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
+ value &= ~(USB2_OTG_PD2 | USB2_OTG_PD2_OVRD_EN);
+ padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
+}
+
+
+static void tegra_xusb_padctl_detect_filters(struct tegra_xusb_padctl *padctl,
+ u32 index, bool on)
+{
+ u32 value;
+
+ if (on) {
+ value = padctl_readl(padctl,
+ USB2_BATTERY_CHRG_OTGPADX_CTL0(index));
+ value |= (VDCD_DET_FILTER_EN | VDAT_DET_FILTER_EN |
+ ZIP_FILTER_EN | ZIN_FILTER_EN);
+ padctl_writel(padctl, value,
+ USB2_BATTERY_CHRG_OTGPADX_CTL0(index));
+ } else {
+ value = padctl_readl(padctl,
+ USB2_BATTERY_CHRG_OTGPADX_CTL0(index));
+ value &= ~(VDCD_DET_FILTER_EN | VDAT_DET_FILTER_EN |
+ ZIP_FILTER_EN | ZIN_FILTER_EN);
+ padctl_writel(padctl, value,
+ USB2_BATTERY_CHRG_OTGPADX_CTL0(index));
+ }
+}
+
+static void tegra_xusb_padctl_dcd(struct tegra_xusb_padctl *padctl, u32 index)
+{
+ u32 value;
+ unsigned int offset;
+ bool ret = false;
+
+ /* Turn on IDP_SRC */
+ value = padctl_readl(padctl, USB2_BATTERY_CHRG_OTGPADX_CTL0(index));
+ value |= OP_I_SRC_EN;
+ padctl_writel(padctl, value, USB2_BATTERY_CHRG_OTGPADX_CTL0(index));
+
+ /* Turn on D- pull-down resistor */
+ value = padctl_readl(padctl, USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
+ value |= USBON_RPD_OVRD_VAL;
+ padctl_writel(padctl, value, USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
+
+ /* Wait for TDCD_DBNC (DCD debounce), refer to BC1.2 spec Table 5 */
+ usleep_range(10000, 20000);
+
+ offset = USB2_BATTERY_CHRG_OTGPADX_CTL0(index);
+ ret = readl_poll_timeout(padctl->regs + offset, value,
+ value & DCD_DETECTED, 20000,
+ TDCD_TIMEOUT_MS * 1000);
+ if (!ret)
+ dev_warn(padctl->dev, "%s: DCD timeout.", __func__);
+
+ /* Turn off IP_SRC, clear DCD DETECTED*/
+ value = padctl_readl(padctl, USB2_BATTERY_CHRG_OTGPADX_CTL0(index));
+ value &= ~OP_I_SRC_EN;
+ value |= DCD_DETECTED;
+ padctl_writel(padctl, value, USB2_BATTERY_CHRG_OTGPADX_CTL0(index));
+
+ /* Turn off D- pull-down resistor */
+ value = padctl_readl(padctl, USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
+ value &= ~USBON_RPD_OVRD_VAL;
+ padctl_writel(padctl, value, USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
+
+ dev_dbg(padctl->dev, "DCD detected: %d\n", !ret);
+}
+
+static bool
+tegra_xusb_padctl_primary_secondary(struct tegra_xusb_padctl *padctl, u32 index,
+ bool is_primary)
+{
+ u32 value;
+ u32 config = is_primary ? (OP_SRC_EN | ON_SINK_EN) :
+ (ON_SRC_EN | OP_SINK_EN);
+ bool ret = false;
+
+ if (is_primary)
+ /* data contact detection */
+ tegra_xusb_padctl_dcd(padctl, index);
+
+ /* Source D- to D+ */
+ value = padctl_readl(padctl, USB2_BATTERY_CHRG_OTGPADX_CTL0(index));
+ value |= config;
+ padctl_writel(padctl, value, USB2_BATTERY_CHRG_OTGPADX_CTL0(index));
+
+ /*
+ * Wait for TVDPSRC_ON/TVDMSRC_ON(D+/- voltage source on time),
+ * refer to BC1.2 spec Table 5
+ */
+ msleep(40);
+
+ value = padctl_readl(padctl, USB2_BATTERY_CHRG_OTGPADX_CTL0(index));
+ if (is_primary)
+ ret = !!(value & VDAT_DET);
+ else
+ ret = !(value & VDAT_DET);
+
+ /* Turn off ON_SRC, OP_SINK, clear VDAT, ZIP status change */
+ value = padctl_readl(padctl, USB2_BATTERY_CHRG_OTGPADX_CTL0(index));
+ value &= ~config;
+ padctl_writel(padctl, value, USB2_BATTERY_CHRG_OTGPADX_CTL0(index));
+
+ return ret;
+}
+
+static const char *const chrg_types[] = {
+ [UNKNOWN_TYPE] = "Unknown Type",
+ [SDP_TYPE] = "SDP Type",
+ [DCP_TYPE] = "DCP Type",
+ [CDP_TYPE] = "CDP Type",
+ [ACA_TYPE] = "ACA Type",
+};
+
+enum usb_charger_type
+tegra_xusb_padctl_charger_detect(struct tegra_xusb_port *port)
+{
+ struct tegra_xusb_padctl *padctl = port->padctl;
+ struct phy *phy = port->lane->pad->lanes[port->index];
+ struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(port->lane);
+ u32 index = port->index;
+ enum usb_charger_type chrg_type;
+ bool pad_power_off = false;
+
+ mutex_lock(&padctl->lock);
+
+ if (!usb2->powered_on) {
+ padctl->soc->ops->utmi_pad_power_on(phy);
+ pad_power_off = true;
+ }
+
+ tegra_xusb_padctl_charger_detect_on(padctl, index);
+ tegra_xusb_padctl_set_debounce_time(padctl, 10);
+ tegra_xusb_padctl_detect_filters(padctl, index, true);
+
+ if (tegra_xusb_padctl_primary_secondary(padctl, index, true)) {
+ /*
+ * wait 20ms (max of TVDMSRC_DIS) for D- to be disabled
+ * from host side, before we perform secondary detection.
+ * Some hosts may not respond well if we do secondary
+ * detection right after primary detection.
+ */
+ msleep(20);
+
+ if (tegra_xusb_padctl_primary_secondary(padctl, index, false))
+ chrg_type = CDP_TYPE;
+ else
+ chrg_type = DCP_TYPE;
+ } else {
+ chrg_type = SDP_TYPE;
+ }
+
+ dev_dbg(&port->dev, "charger detected of type %s",
+ chrg_types[chrg_type]);
+
+ tegra_xusb_padctl_detect_filters(padctl, index, false);
+ tegra_xusb_padctl_charger_detect_off(padctl, index);
+
+ if (pad_power_off)
+ padctl->soc->ops->utmi_pad_power_down(phy);
+
+ mutex_unlock(&padctl->lock);
+ return chrg_type;
+}
+
+MODULE_AUTHOR("Nagarjuna Kristam <nkristam@nvidia.com>");
+MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB charger detect driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/phy/tegra/xusb.c b/drivers/phy/tegra/xusb.c
index de4a46f..7252982 100644
--- a/drivers/phy/tegra/xusb.c
+++ b/drivers/phy/tegra/xusb.c
@@ -591,6 +591,50 @@ static enum usb_phy_events to_usb_phy_event(enum usb_role role)
}
}
+#define VON_DIV2P0_DET BIT(0)
+#define VON_DIV2P7_DET BIT(1)
+#define VOP_DIV2P0_DET BIT(2)
+#define VOP_DIV2P7_DET BIT(3)
+
+#define VREG_CUR_LEVEL_0 500
+#define VREG_CUR_LEVEL_1 900
+#define VREG_CUR_LEVEL_2 1500
+#define VREG_CUR_LEVEL_3 2000
+
+#define IS_CUR_IN_RANGE(ma, low, high) \
+ ((ma >= VREG_CUR_LEVEL_##low) && (ma <= (VREG_CUR_LEVEL_##high - 1)))
+#define VREG_LVL(ma, level) IS_CUR_IN_RANGE(ma, level, level + 1)
+
+static void tegra_xusb_padctl_vbus_pad_portection(struct tegra_xusb_port *port)
+{
+ struct tegra_xusb_padctl *padctl = port->padctl;
+ int level = 0;
+ enum tegra_vbus_dir dir = TEGRA_VBUS_SINK;
+ int max_ua, min_ua;
+
+ if (!padctl->soc->ops->utmi_pad_set_protection)
+ return;
+
+ usb_phy_get_charger_current(&port->usb_phy, &min_ua, &max_ua);
+
+ if (max_ua == 0) {
+ level = -1;
+ dir = TEGRA_VBUS_DEFAULT;
+ } else if (VREG_LVL(max_ua, 0)) {
+ level = 0;
+ } else if (VREG_LVL(max_ua, 1)) {
+ level = 1;
+ } else if (VREG_LVL(max_ua, 2)) {
+ level = 2;
+ } else if (max_ua >= VREG_CUR_LEVEL_3) {
+ level = 3;
+ } else {
+ return;
+ }
+
+ padctl->soc->ops->utmi_pad_set_protection(port, level, dir);
+}
+
static void tegra_xusb_usb_phy_work(struct work_struct *work)
{
struct tegra_xusb_port *port = container_of(work,
@@ -598,6 +642,10 @@ static void tegra_xusb_usb_phy_work(struct work_struct *work)
usb_phy_work);
enum usb_role role = usb_role_switch_get_role(port->usb_role_sw);
+ /* Set role to none, if charger is DCP type */
+ if (port->chrg_type == DCP_TYPE)
+ role = USB_ROLE_NONE;
+
usb_phy_set_event(&port->usb_phy, to_usb_phy_event(role));
dev_dbg(&port->dev, "%s(): calling notifier for role %s\n", __func__,
@@ -610,9 +658,26 @@ static int tegra_xusb_role_sw_set(struct usb_role_switch *sw,
enum usb_role role)
{
struct tegra_xusb_port *port = usb_role_switch_get_drvdata(sw);
+ enum usb_charger_state charger_state;
dev_dbg(&port->dev, "%s(): role %s\n", __func__, usb_roles[role]);
+ /* Do charger detect if role is Device and charger detect is enabled */
+ if (port->charger_detect) {
+ if (role == USB_ROLE_DEVICE)
+ port->chrg_type =
+ tegra_xusb_padctl_charger_detect(port);
+ else
+ port->chrg_type = UNKNOWN_TYPE;
+
+ charger_state = (port->chrg_type == UNKNOWN_TYPE) ?
+ USB_CHARGER_ABSENT : USB_CHARGER_PRESENT;
+
+ usb_phy_set_charger_state(&port->usb_phy, charger_state);
+
+ tegra_xusb_padctl_vbus_pad_portection(port);
+ }
+
schedule_work(&port->usb_phy_work);
return 0;
@@ -643,6 +708,14 @@ static int tegra_xusb_set_host(struct usb_otg *otg, struct usb_bus *host)
return 0;
}
+static enum usb_charger_type tegra_xusb_charger_detect(struct usb_phy *usb_phy)
+{
+ struct tegra_xusb_port *port = container_of(usb_phy,
+ struct tegra_xusb_port,
+ usb_phy);
+
+ return port->chrg_type;
+}
static int tegra_xusb_setup_usb_role_switch(struct tegra_xusb_port *port)
{
@@ -693,6 +766,9 @@ static int tegra_xusb_setup_usb_role_switch(struct tegra_xusb_port *port)
port->usb_phy.otg->set_peripheral = tegra_xusb_set_peripheral;
port->usb_phy.otg->set_host = tegra_xusb_set_host;
+ if (port->charger_detect)
+ port->usb_phy.charger_detect = tegra_xusb_charger_detect;
+
err = usb_add_phy_dev(&port->usb_phy);
if (err < 0) {
dev_err(&port->dev, "Failed to add USB PHY: %d\n", err);
@@ -727,6 +803,10 @@ static int tegra_xusb_usb2_port_parse_dt(struct tegra_xusb_usb2_port *usb2)
usb2->mode = USB_DR_MODE_HOST;
}
+ if (port->padctl->soc->supports_charger_detect &&
+ of_property_read_bool(np, "nvidia,charger-detect"))
+ port->charger_detect = true;
+
/* usb-role-switch property is mandatory for OTG/Peripheral modes */
if (usb2->mode == USB_DR_MODE_PERIPHERAL ||
usb2->mode == USB_DR_MODE_OTG) {
diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h
index 475bcc6..7b9a798 100644
--- a/drivers/phy/tegra/xusb.h
+++ b/drivers/phy/tegra/xusb.h
@@ -282,6 +282,9 @@ struct tegra_xusb_port {
struct work_struct usb_phy_work;
struct usb_phy usb_phy;
+ bool charger_detect;
+ enum usb_charger_type chrg_type;
+
const struct tegra_xusb_port_ops *ops;
};
@@ -306,6 +309,9 @@ struct tegra_xusb_port *
tegra_xusb_find_port(struct tegra_xusb_padctl *padctl, const char *type,
unsigned int index);
+enum usb_charger_type tegra_xusb_padctl_charger_detect(
+ struct tegra_xusb_port *port);
+
struct tegra_xusb_usb2_port {
struct tegra_xusb_port base;
@@ -430,6 +436,7 @@ struct tegra_xusb_padctl_soc {
unsigned int num_supplies;
bool supports_gen2;
bool need_fake_usb3_port;
+ bool supports_charger_detect;
};
struct tegra_xusb_padctl {
--
2.7.4
^ permalink raw reply related
* [PATCH V3 8/8] phy: tegra: xusb: Enable charger detect for Tegra210
From: Nagarjuna Kristam @ 2020-05-14 6:22 UTC (permalink / raw)
To: balbi, gregkh, thierry.reding, jonathanh, mark.rutland, robh+dt,
kishon
Cc: devicetree, linux-tegra, linux-usb, linux-kernel,
Nagarjuna Kristam
In-Reply-To: <1589437363-16727-1-git-send-email-nkristam@nvidia.com>
Tegra210 SoC supports charger detect, set corresponding soc flag.
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
---
V3:
- Used supports_charger_detect name instead of charger_detect.
- Added Acked-by updates to commit message.
---
V2:
- Patch re-based.
---
drivers/phy/tegra/xusb-tegra210.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/phy/tegra/xusb-tegra210.c b/drivers/phy/tegra/xusb-tegra210.c
index 80c4349..db2a1ab 100644
--- a/drivers/phy/tegra/xusb-tegra210.c
+++ b/drivers/phy/tegra/xusb-tegra210.c
@@ -2353,6 +2353,7 @@ const struct tegra_xusb_padctl_soc tegra210_xusb_padctl_soc = {
.supply_names = tegra210_xusb_padctl_supply_names,
.num_supplies = ARRAY_SIZE(tegra210_xusb_padctl_supply_names),
.need_fake_usb3_port = true,
+ .supports_charger_detect = true,
};
EXPORT_SYMBOL_GPL(tegra210_xusb_padctl_soc);
--
2.7.4
^ permalink raw reply related
* [PATCH V3 7/8] phy: tegra: xusb: Enable charger detect for Tegra186
From: Nagarjuna Kristam @ 2020-05-14 6:22 UTC (permalink / raw)
To: balbi, gregkh, thierry.reding, jonathanh, mark.rutland, robh+dt,
kishon
Cc: devicetree, linux-tegra, linux-usb, linux-kernel,
Nagarjuna Kristam
In-Reply-To: <1589437363-16727-1-git-send-email-nkristam@nvidia.com>
Tegra186 SoC supports charger detect, set corresponding soc flag.
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
---
V3:
- Used supports_charger_detect name instead of charger_detect.
- Added Acked-by updates to commit message.
---
V2:
- Patch re-based.
---
drivers/phy/tegra/xusb-tegra186.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c
index 59b78a7..da61721 100644
--- a/drivers/phy/tegra/xusb-tegra186.c
+++ b/drivers/phy/tegra/xusb-tegra186.c
@@ -1041,6 +1041,7 @@ const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = {
.ops = &tegra186_xusb_padctl_ops,
.supply_names = tegra186_xusb_padctl_supply_names,
.num_supplies = ARRAY_SIZE(tegra186_xusb_padctl_supply_names),
+ .supports_charger_detect = true,
};
EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc);
#endif
--
2.7.4
^ permalink raw reply related
* [PATCH V3 5/8] phy: tegra: xusb: Add soc ops API to enable UTMI PAD protection
From: Nagarjuna Kristam @ 2020-05-14 6:22 UTC (permalink / raw)
To: balbi, gregkh, thierry.reding, jonathanh, mark.rutland, robh+dt,
kishon
Cc: devicetree, linux-tegra, linux-usb, linux-kernel,
Nagarjuna Kristam
In-Reply-To: <1589437363-16727-1-git-send-email-nkristam@nvidia.com>
When USB charger is enabled, UTMI PAD needs to be protected according
to the direction and current level. Add support for the same on Tegra210
and Tegra186.
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
---
V3:
- Alligned function and its arguments.
- Fixed other comments from Thierry.
---
V2:
- Commit message coorected.
- Patch re-based.
---
drivers/phy/tegra/xusb-tegra186.c | 40 +++++++++++++++++++++++++++++++++++++++
drivers/phy/tegra/xusb-tegra210.c | 32 +++++++++++++++++++++++++++++++
drivers/phy/tegra/xusb.h | 13 +++++++++++++
3 files changed, 85 insertions(+)
diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c
index f862254..59b78a7 100644
--- a/drivers/phy/tegra/xusb-tegra186.c
+++ b/drivers/phy/tegra/xusb-tegra186.c
@@ -68,6 +68,13 @@
#define PORTX_SPEED_SUPPORT_MASK (0x3)
#define PORT_SPEED_SUPPORT_GEN1 (0x0)
+#define USB2_BATTERY_CHRG_OTGPADX_CTL1(x) (0x84 + (x) * 0x40)
+#define PD_VREG (1 << 6)
+#define VREG_LEV(x) (((x) & 0x3) << 7)
+#define VREG_DIR(x) (((x) & 0x3) << 11)
+#define VREG_DIR_IN VREG_DIR(1)
+#define VREG_DIR_OUT VREG_DIR(2)
+
#define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x88 + (x) * 0x40)
#define HS_CURR_LEVEL(x) ((x) & 0x3f)
#define TERM_SEL BIT(25)
@@ -289,6 +296,37 @@ static void tegra_phy_xusb_utmi_pad_power_down(struct phy *phy)
usb2->powered_on = false;
}
+static void
+tegra186_xusb_padctl_utmi_pad_set_protection(struct tegra_xusb_port *port,
+ int level,
+ enum tegra_vbus_dir dir)
+{
+ u32 value;
+ struct tegra_xusb_padctl *padctl = port->padctl;
+ unsigned int index = port->index;
+
+ value = padctl_readl(padctl, USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
+
+ if (level < 0) {
+ /* disable pad protection */
+ value |= PD_VREG;
+ value &= ~VREG_LEV(~0);
+ value &= ~VREG_DIR(~0);
+ } else {
+ if (dir == TEGRA_VBUS_SOURCE)
+ value |= VREG_DIR_OUT;
+ else if (dir == TEGRA_VBUS_SINK)
+ value |= VREG_DIR_IN;
+
+ value &= ~PD_VREG;
+ value &= ~VREG_DIR(~0);
+ value &= ~VREG_LEV(~0);
+ value |= VREG_LEV(level);
+ }
+
+ padctl_writel(padctl, value, USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
+}
+
static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
bool status)
{
@@ -935,6 +973,8 @@ static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = {
.vbus_override = tegra186_xusb_padctl_vbus_override,
.utmi_pad_power_on = tegra_phy_xusb_utmi_pad_power_on,
.utmi_pad_power_down = tegra_phy_xusb_utmi_pad_power_down,
+ .utmi_pad_set_protection =
+ tegra186_xusb_padctl_utmi_pad_set_protection,
};
#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
diff --git a/drivers/phy/tegra/xusb-tegra210.c b/drivers/phy/tegra/xusb-tegra210.c
index caf0890..80c4349 100644
--- a/drivers/phy/tegra/xusb-tegra210.c
+++ b/drivers/phy/tegra/xusb-tegra210.c
@@ -74,6 +74,8 @@
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK 0x3
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_VAL 0x1
#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18 (1 << 6)
+#define USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV(x) (((x) & 0x3) << 7)
+#define USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_DIR(x) (((x) & 0x3) << 11)
#define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x088 + (x) * 0x40)
#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI (1 << 29)
@@ -1116,6 +1118,34 @@ void tegra210_usb2_pad_power_down(struct phy *phy)
usb2->powered_on = false;
}
+static void
+tegra210_xusb_padctl_utmi_pad_set_protection(struct tegra_xusb_port *port,
+ int level,
+ enum tegra_vbus_dir dir)
+{
+ u32 value;
+ struct tegra_xusb_padctl *padctl = port->padctl;
+ unsigned int index = port->index;
+
+ value = padctl_readl(padctl,
+ XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
+
+ if (level < 0) {
+ /* disable pad protection */
+ value |= XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18;
+ value &= USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV(~0);
+ value &= ~USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_DIR(~0);
+ } else {
+ value &= ~XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18;
+ value &= ~USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_DIR(~0);
+ value &= USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV(~0);
+ value |= USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV(level);
+ }
+
+ padctl_writel(padctl, value,
+ XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
+}
+
static int tegra210_usb2_phy_set_mode(struct phy *phy, enum phy_mode mode,
int submode)
{
@@ -2291,6 +2321,8 @@ static const struct tegra_xusb_padctl_ops tegra210_xusb_padctl_ops = {
.utmi_port_reset = tegra210_utmi_port_reset,
.utmi_pad_power_on = tegra210_usb2_pad_power_on,
.utmi_pad_power_down = tegra210_usb2_pad_power_down,
+ .utmi_pad_set_protection =
+ tegra210_xusb_padctl_utmi_pad_set_protection,
};
static const char * const tegra210_xusb_padctl_supply_names[] = {
diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h
index 6995fc4..475bcc6 100644
--- a/drivers/phy/tegra/xusb.h
+++ b/drivers/phy/tegra/xusb.h
@@ -259,6 +259,17 @@ to_sata_pad(struct tegra_xusb_pad *pad)
*/
struct tegra_xusb_port_ops;
+/*
+ * Tegra OTG port VBUS direction:
+ * default (based on port capability) or
+ * as source or sink
+ */
+enum tegra_vbus_dir {
+ TEGRA_VBUS_DEFAULT,
+ TEGRA_VBUS_SOURCE,
+ TEGRA_VBUS_SINK
+};
+
struct tegra_xusb_port {
struct tegra_xusb_padctl *padctl;
struct tegra_xusb_lane *lane;
@@ -398,6 +409,8 @@ struct tegra_xusb_padctl_ops {
int (*utmi_port_reset)(struct phy *phy);
void (*utmi_pad_power_on)(struct phy *phy);
void (*utmi_pad_power_down)(struct phy *phy);
+ void (*utmi_pad_set_protection)(struct tegra_xusb_port *port,
+ int level, enum tegra_vbus_dir dir);
};
struct tegra_xusb_padctl_soc {
--
2.7.4
^ permalink raw reply related
* [PATCH V3 3/8] phy: tegra: xusb: Add support for UTMI pad power control
From: Nagarjuna Kristam @ 2020-05-14 6:22 UTC (permalink / raw)
To: balbi, gregkh, thierry.reding, jonathanh, mark.rutland, robh+dt,
kishon
Cc: devicetree, linux-tegra, linux-usb, linux-kernel,
Nagarjuna Kristam
In-Reply-To: <1589437363-16727-1-git-send-email-nkristam@nvidia.com>
Add support for UTMI pad power on and off API's via soc ops. These API
can be used by operations like charger detect to power on and off UTMI
pad if needed. Update powered_on flag in the pad power control API's.
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
---
V3:
- Added Acked-by updates to commit message.
---
V2:
- Patch re-based.
---
drivers/phy/tegra/xusb-tegra186.c | 51 ++++++++++++++++++---------------------
drivers/phy/tegra/xusb.h | 2 ++
2 files changed, 26 insertions(+), 27 deletions(-)
diff --git a/drivers/phy/tegra/xusb-tegra186.c b/drivers/phy/tegra/xusb-tegra186.c
index 5d64f69..f862254 100644
--- a/drivers/phy/tegra/xusb-tegra186.c
+++ b/drivers/phy/tegra/xusb-tegra186.c
@@ -192,12 +192,8 @@ static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl)
u32 value;
int err;
- mutex_lock(&padctl->lock);
-
- if (priv->bias_pad_enable++ > 0) {
- mutex_unlock(&padctl->lock);
+ if (priv->bias_pad_enable++ > 0)
return;
- }
err = clk_prepare_enable(priv->usb2_trk_clk);
if (err < 0)
@@ -221,8 +217,6 @@ static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl)
value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
value &= ~USB2_PD_TRK;
padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
-
- mutex_unlock(&padctl->lock);
}
static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl)
@@ -230,44 +224,29 @@ static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl)
struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
u32 value;
- mutex_lock(&padctl->lock);
-
- if (WARN_ON(priv->bias_pad_enable == 0)) {
- mutex_unlock(&padctl->lock);
+ if (WARN_ON(priv->bias_pad_enable == 0))
return;
- }
- if (--priv->bias_pad_enable > 0) {
- mutex_unlock(&padctl->lock);
+ if (--priv->bias_pad_enable > 0)
return;
- }
value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
value |= USB2_PD_TRK;
padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
clk_disable_unprepare(priv->usb2_trk_clk);
-
- mutex_unlock(&padctl->lock);
}
static void tegra_phy_xusb_utmi_pad_power_on(struct phy *phy)
{
struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
struct tegra_xusb_padctl *padctl = lane->pad->padctl;
- struct tegra_xusb_usb2_port *port;
- struct device *dev = padctl->dev;
+ struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
unsigned int index = lane->index;
u32 value;
- if (!phy)
- return;
-
- port = tegra_xusb_find_usb2_port(padctl, index);
- if (!port) {
- dev_err(dev, "no port found for USB2 lane %u\n", index);
+ if (!phy || usb2->powered_on)
return;
- }
tegra186_utmi_bias_pad_power_on(padctl);
@@ -280,16 +259,19 @@ static void tegra_phy_xusb_utmi_pad_power_on(struct phy *phy)
value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
value &= ~USB2_OTG_PD_DR;
padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
+
+ usb2->powered_on = true;
}
static void tegra_phy_xusb_utmi_pad_power_down(struct phy *phy)
{
struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+ struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
unsigned int index = lane->index;
u32 value;
- if (!phy)
+ if (!phy || !usb2->powered_on)
return;
value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
@@ -303,6 +285,8 @@ static void tegra_phy_xusb_utmi_pad_power_down(struct phy *phy)
udelay(2);
tegra186_utmi_bias_pad_power_off(padctl);
+
+ usb2->powered_on = false;
}
static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
@@ -413,6 +397,8 @@ static int tegra186_utmi_phy_power_on(struct phy *phy)
return -ENODEV;
}
+ mutex_lock(&padctl->lock);
+
value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
value &= ~(USB2_PORT_MASK << USB2_PORT_SHIFT(index));
value |= (PORT_XUSB << USB2_PORT_SHIFT(index));
@@ -464,14 +450,23 @@ static int tegra186_utmi_phy_power_on(struct phy *phy)
/* TODO: pad power saving */
tegra_phy_xusb_utmi_pad_power_on(phy);
+
+ mutex_unlock(&padctl->lock);
return 0;
}
static int tegra186_utmi_phy_power_off(struct phy *phy)
{
+ struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
+ struct tegra_xusb_padctl *padctl = lane->pad->padctl;
+
+ mutex_lock(&padctl->lock);
+
/* TODO: pad power saving */
tegra_phy_xusb_utmi_pad_power_down(phy);
+ mutex_unlock(&padctl->lock);
+
return 0;
}
@@ -938,6 +933,8 @@ static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = {
.probe = tegra186_xusb_padctl_probe,
.remove = tegra186_xusb_padctl_remove,
.vbus_override = tegra186_xusb_padctl_vbus_override,
+ .utmi_pad_power_on = tegra_phy_xusb_utmi_pad_power_on,
+ .utmi_pad_power_down = tegra_phy_xusb_utmi_pad_power_down,
};
#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
diff --git a/drivers/phy/tegra/xusb.h b/drivers/phy/tegra/xusb.h
index ea35af7..6995fc4 100644
--- a/drivers/phy/tegra/xusb.h
+++ b/drivers/phy/tegra/xusb.h
@@ -396,6 +396,8 @@ struct tegra_xusb_padctl_ops {
unsigned int index, bool enable);
int (*vbus_override)(struct tegra_xusb_padctl *padctl, bool set);
int (*utmi_port_reset)(struct phy *phy);
+ void (*utmi_pad_power_on)(struct phy *phy);
+ void (*utmi_pad_power_down)(struct phy *phy);
};
struct tegra_xusb_padctl_soc {
--
2.7.4
^ permalink raw reply related
* [PATCH V3 2/8] usb: gadget: tegra-xudc: Add vbus_draw support
From: Nagarjuna Kristam @ 2020-05-14 6:22 UTC (permalink / raw)
To: balbi, gregkh, thierry.reding, jonathanh, mark.rutland, robh+dt,
kishon
Cc: devicetree, linux-tegra, linux-usb, linux-kernel,
Nagarjuna Kristam
In-Reply-To: <1589437363-16727-1-git-send-email-nkristam@nvidia.com>
Register vbus_draw to gadget ops and update corresponding vbus
draw current to usb_phy.
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
---
V3:
- Propogated usb_phy->set_power error to vbus_draw caller.
---
V2:
- Patch re-based.
---
drivers/usb/gadget/udc/tegra-xudc.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/usb/gadget/udc/tegra-xudc.c b/drivers/usb/gadget/udc/tegra-xudc.c
index 52a6add..53e2d1c 100644
--- a/drivers/usb/gadget/udc/tegra-xudc.c
+++ b/drivers/usb/gadget/udc/tegra-xudc.c
@@ -492,6 +492,7 @@ struct tegra_xudc {
bool powergated;
struct usb_phy **usbphy;
+ struct usb_phy *curr_usbphy;
struct notifier_block vbus_nb;
struct completion disconnect_complete;
@@ -719,6 +720,7 @@ static int tegra_xudc_vbus_notify(struct notifier_block *nb,
if (!xudc->suspended && phy_index != -1) {
xudc->curr_utmi_phy = xudc->utmi_phy[phy_index];
xudc->curr_usb3_phy = xudc->usb3_phy[phy_index];
+ xudc->curr_usbphy = usbphy;
schedule_work(&xudc->usb_role_sw_work);
}
@@ -2042,6 +2044,20 @@ static int tegra_xudc_gadget_stop(struct usb_gadget *gadget)
return 0;
}
+static int tegra_xudc_gadget_vbus_draw(struct usb_gadget *gadget,
+ unsigned int m_a)
+{
+ int ret = 0;
+ struct tegra_xudc *xudc = to_xudc(gadget);
+
+ dev_dbg(xudc->dev, "%s: %u mA\n", __func__, m_a);
+
+ if (xudc->curr_usbphy->chg_type == SDP_TYPE)
+ ret = usb_phy_set_power(xudc->curr_usbphy, m_a);
+
+ return ret;
+}
+
static int tegra_xudc_set_selfpowered(struct usb_gadget *gadget, int is_on)
{
struct tegra_xudc *xudc = to_xudc(gadget);
@@ -2058,6 +2074,7 @@ static struct usb_gadget_ops tegra_xudc_gadget_ops = {
.pullup = tegra_xudc_gadget_pullup,
.udc_start = tegra_xudc_gadget_start,
.udc_stop = tegra_xudc_gadget_stop,
+ .vbus_draw = tegra_xudc_gadget_vbus_draw,
.set_selfpowered = tegra_xudc_set_selfpowered,
};
--
2.7.4
^ permalink raw reply related
* [PATCH 2/2] dt-bindings: rtc: Convert MXC RTC V2 to json-schema
From: Anson Huang @ 2020-05-14 6:13 UTC (permalink / raw)
To: a.zummo, alexandre.belloni, robh+dt, tremyfr, p.bruenn, linux-rtc,
devicetree, linux-kernel
Cc: Linux-imx
In-Reply-To: <1589436805-22923-1-git-send-email-Anson.Huang@nxp.com>
Convert the MXC RTC V2 binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
.../devicetree/bindings/rtc/rtc-mxc_v2.txt | 17 --------
.../devicetree/bindings/rtc/rtc-mxc_v2.yaml | 46 ++++++++++++++++++++++
2 files changed, 46 insertions(+), 17 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt
create mode 100644 Documentation/devicetree/bindings/rtc/rtc-mxc_v2.yaml
diff --git a/Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt b/Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt
deleted file mode 100644
index 79d7e87..0000000
--- a/Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-* i.MX53 Secure Real Time Clock (SRTC)
-
-Required properties:
-- compatible: should be: "fsl,imx53-rtc"
-- reg: physical base address of the controller and length of memory mapped
- region.
-- clocks: should contain the phandle for the rtc clock
-- interrupts: rtc alarm interrupt
-
-Example:
-
-rtc@53fa4000 {
- compatible = "fsl,imx53-rtc";
- reg = <0x53fa4000 0x4000>;
- interrupts = <24>;
- clocks = <&clks IMX5_CLK_SRTC_GATE>;
-};
diff --git a/Documentation/devicetree/bindings/rtc/rtc-mxc_v2.yaml b/Documentation/devicetree/bindings/rtc/rtc-mxc_v2.yaml
new file mode 100644
index 0000000..2d1a306
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/rtc-mxc_v2.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/rtc-mxc_v2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: i.MX53 Secure Real Time Clock (SRTC)
+
+allOf:
+ - $ref: "rtc.yaml#"
+
+maintainers:
+ - Patrick Bruenn <p.bruenn@beckhoff.com>
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx53-rtc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx5-clock.h>
+
+ rtc@53fa4000 {
+ compatible = "fsl,imx53-rtc";
+ reg = <0x53fa4000 0x4000>;
+ interrupts = <24>;
+ clocks = <&clks IMX5_CLK_SRTC_GATE>;
+ };
--
2.7.4
^ permalink raw reply related
* Re: [PATCH 6/4] dt-bindings: display: renesas: lvds: RZ/G2E needs renesas,companion too
From: Geert Uytterhoeven @ 2020-05-14 6:44 UTC (permalink / raw)
To: Laurent Pinchart
Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas, Rob Herring, DRI Development, Fabrizio Castro
In-Reply-To: <20200513233908.23629-1-laurent.pinchart+renesas@ideasonboard.com>
On Thu, May 14, 2020 at 1:39 AM Laurent Pinchart
<laurent.pinchart+renesas@ideasonboard.com> wrote:
> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Document RZ/G2E support for property renesas,companion.
>
> Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> --- a/Documentation/devicetree/bindings/display/bridge/renesas,lvds.yaml
> +++ b/Documentation/devicetree/bindings/display/bridge/renesas,lvds.yaml
> @@ -81,9 +81,9 @@ properties:
> $ref: /schemas/types.yaml#/definitions/phandle
> description:
> phandle to the companion LVDS encoder. This property is mandatory
> - for the first LVDS encoder on D3 and E3 SoCs, and shall point to
> - the second encoder to be used as a companion in dual-link mode. It
> - shall not be set for any other LVDS encoder.
> + for the first LVDS encoder on D3, R-Car E3 and RZ/G2E SoCs, and shall
R-Car D3 and E3, and RZ/G2E SoCs
> + point to the second encoder to be used as a companion in dual-link mode.
> + It shall not be set for any other LVDS encoder.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH V5 2/7] soc: qcom-geni-se: Add interconnect support to fix earlycon crash
From: Akash Asthana @ 2020-05-14 6:45 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: gregkh, agross, bjorn.andersson, wsa, broonie, mark.rutland,
robh+dt, linux-i2c, linux-spi, devicetree, swboyd, mgautam,
linux-arm-msm, linux-serial, dianders, evgreen, georgi.djakov
In-Reply-To: <20200508175938.GB4525@google.com>
Hi Matthias,
On 5/8/2020 11:29 PM, Matthias Kaehlcke wrote:
> Hi Akash,
>
> overall this looks good to me, a few comments inline
>
> On Fri, May 08, 2020 at 12:03:34PM +0530, Akash Asthana wrote:
>> QUP core clock is shared among all the SE drivers present on particular
>> QUP wrapper, the system will reset(unclocked access) if earlycon used after
>> QUP core clock is put to 0 from other SE drivers before real console comes
>> up.
>>
>> As earlycon can't vote for it's QUP core need, to fix this add ICC
>> support to common/QUP wrapper driver and put vote for QUP core from
>> probe on behalf of earlycon and remove vote during earlycon exit call.
>>
>> Signed-off-by: Akash Asthana <akashast@codeaurora.org>
>> Reported-by: Matthias Kaehlcke <mka@chromium.org>
>> ---
>> Change in V3:
>> - Add geni_remove_earlycon_icc_vote API that will be used by earlycon
>> exit function to remove ICC vote for earlyconsole.
>> - Remove suspend/resume hook for geni-se driver as we are no longer
>> removing earlyconsole ICC vote from system suspend, we are removing
>> from earlycon exit.
>>
>> Change in V4:
>> - As per Matthias comment make 'earlycon_wrapper' as static structure.
>>
>> Changes in V5:
>> - Vote for core path only after checking whether "qcom_geni" earlycon is
>> actually present or not by traversing over structure "console_drivers".
>>
>> drivers/soc/qcom/qcom-geni-se.c | 63 +++++++++++++++++++++++++++++++++++
>> drivers/tty/serial/qcom_geni_serial.c | 7 ++++
>> include/linux/qcom-geni-se.h | 2 ++
>> 3 files changed, 72 insertions(+)
>>
>> diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c
>> index 63403bf..66fe6f2 100644
>> --- a/drivers/soc/qcom/qcom-geni-se.c
>> +++ b/drivers/soc/qcom/qcom-geni-se.c
>> @@ -3,6 +3,7 @@
>>
>> #include <linux/acpi.h>
>> #include <linux/clk.h>
>> +#include <linux/console.h>
>> #include <linux/slab.h>
>> #include <linux/dma-mapping.h>
>> #include <linux/io.h>
>> @@ -90,11 +91,14 @@ struct geni_wrapper {
>> struct device *dev;
>> void __iomem *base;
>> struct clk_bulk_data ahb_clks[NUM_AHB_CLKS];
>> + struct geni_icc_path to_core;
>> };
>>
>> static const char * const icc_path_names[] = {"qup-core", "qup-config",
>> "qup-memory"};
>>
>> +static struct geni_wrapper *earlycon_wrapper;
>> +
>> #define QUP_HW_VER_REG 0x4
>>
>> /* Common SE registers */
>> @@ -812,11 +816,33 @@ int geni_icc_disable(struct geni_se *se)
>> }
>> EXPORT_SYMBOL(geni_icc_disable);
>>
>> +void geni_remove_earlycon_icc_vote(void)
>> +{
>> + struct geni_wrapper *wrapper = earlycon_wrapper;
>> + struct device_node *parent = of_get_next_parent(wrapper->dev->of_node);
> Do we need to check that earlycon_wrapper != NULL before dereferencing it?
> In theory this should not happen, but better be safe.
Ok, I will add NULL check.
>
>> + struct device_node *child;
>> +
>> + for_each_child_of_node(parent, child) {
>> + if (of_device_is_compatible(child, "qcom,geni-se-qup")) {
>> + wrapper = platform_get_drvdata(of_find_device_by_node(
>> + child));
>> + icc_put(wrapper->to_core.path);
>> + wrapper->to_core.path = NULL;
> nit: setting the path to NULL isn't really needed IIUC.
icc_put just free the path and don't reinitialize the path to NULL, if
the path is used after it is put target will crash. So just for safety I
am setting this path to NULL.
>
>> + }
>> + }
>> + of_node_put(parent);
>> +
>> + earlycon_wrapper = NULL;
>> +}
>> +EXPORT_SYMBOL(geni_remove_earlycon_icc_vote);
>> +
>> static int geni_se_probe(struct platform_device *pdev)
>> {
>> struct device *dev = &pdev->dev;
>> struct resource *res;
>> struct geni_wrapper *wrapper;
>> + struct console *bcon;
>> + int earlycon_present = 0;
> use bool & true/false
>
> The variable is only used when CONFIG_SERIAL_EARLYCON is set, I think
> you need to add '__maybe_unused' to avoid a compiler warning then earlycon
> support is disabled.
>
> bikeshed: 'has_earlycon' would be slightly more concise (feel free to ignore).
Ok
>
>> int ret;
>>
>> wrapper = devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL);
>> @@ -839,6 +865,43 @@ static int geni_se_probe(struct platform_device *pdev)
>> }
>> }
>>
>> +#ifdef CONFIG_SERIAL_EARLYCON
>> + if (console_drivers)
> The loop should have curly braces ("use braces when a loop contains more than
> a single simple statement"), even though the compiler doesn't need them in
> this case. This is not a loop, but I was told by a maintainer that it equally
> applies, which makes sense.
>
> You could avoid one level of indentation through:
Ok
>
> if (!console_drivers)
> goto exit;
I think I can omit this extra check because "for_each_console" will take
care of this.
>
>> + for_each_console(bcon)
> ditto (braces)
>
>> + if (!strcmp(bcon->name, "qcom_geni")) {
>> + earlycon_present = 1;
>> + break;
>> + }
>> + if (!earlycon_present)
>> + goto exit;
>> +
>> + wrapper->to_core.path = devm_of_icc_get(dev, "qup-core");
>> + if (IS_ERR(wrapper->to_core.path))
>> + return PTR_ERR(wrapper->to_core.path);
>> + /*
>> + * Put minmal BW request on core clocks on behalf of early console.
>> + * The vote will be removed earlycon exit function.
>> + *
>> + * Note: We are putting vote on each QUP wrapper instead only to which
>> + * earlycon is connected because QUP core clock of different wrapper
>> + * share same voltage domain. If core1 is put to 0, then core2 will
>> + * also run at 0, if not voted. Default ICC vote will be removed ASA
>> + * we touch any of the core clock.
>> + * core1 = core2 = max(core1, core2)
>> + */
>> + ret = icc_set_bw(wrapper->to_core.path, GENI_DEFAULT_BW,
>> + GENI_DEFAULT_BW);
> nit: the indentation is a bit odd. Align with 'wrapper->to_core.path' or a
> nearby tab stop?
ok
Thanks for providing the feedback.
Regards,
Akash
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [PATCH V5 2/7] soc: qcom-geni-se: Add interconnect support to fix earlycon crash
From: Akash Asthana @ 2020-05-14 7:03 UTC (permalink / raw)
To: Matthias Kaehlcke
Cc: gregkh, agross, bjorn.andersson, wsa, broonie, mark.rutland,
robh+dt, linux-i2c, linux-spi, devicetree, swboyd, mgautam,
linux-arm-msm, linux-serial, dianders, evgreen, georgi.djakov
In-Reply-To: <20200508191454.GH4525@google.com>
Hi Matthias,
>> The loop should have curly braces ("use braces when a loop contains more than
>> a single simple statement"), even though the compiler doesn't need them in
>> this case. This is not a loop, but I was told by a maintainer that it equally
>> applies, which makes sense.
>>
>> You could avoid one level of indentation through:
>>
>> if (!console_drivers)
>> goto exit;
>>
>>> + for_each_console(bcon)
> Actually the NULL check of 'console_drivers' is not needed:
>
> #define for_each_console(con) \
> for (con = console_drivers; con != NULL; con = con->next)
Ok, I will remove this check.
Regards,
Akash
>
> see also:
>
> commit caa72c3bc584bc28b557bcf1a47532a7a6f37e6f
> Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Date: Mon Feb 3 15:31:25 2020 +0200
>
> console: Drop double check for console_drivers being non-NULL
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH 2/2] dt-bindings: pwm: Convert imx tpm pwm to json-schema
From: Anson Huang @ 2020-05-14 6:54 UTC (permalink / raw)
To: thierry.reding, u.kleine-koenig, robh+dt, shawnguo, s.hauer,
kernel, festevam, p.zabel, linux-pwm, devicetree,
linux-arm-kernel, linux-kernel
Cc: Linux-imx
In-Reply-To: <1589439259-28510-1-git-send-email-Anson.Huang@nxp.com>
Convert the imx tpm pwm binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
.../devicetree/bindings/pwm/imx-tpm-pwm.txt | 22 ---------
.../devicetree/bindings/pwm/imx-tpm-pwm.yaml | 55 ++++++++++++++++++++++
2 files changed, 55 insertions(+), 22 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt
create mode 100644 Documentation/devicetree/bindings/pwm/imx-tpm-pwm.yaml
diff --git a/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt
deleted file mode 100644
index 5bf2095..0000000
--- a/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-Freescale i.MX TPM PWM controller
-
-Required properties:
-- compatible : Should be "fsl,imx7ulp-pwm".
-- reg: Physical base address and length of the controller's registers.
-- #pwm-cells: Should be 3. See pwm.yaml in this directory for a description of the cells format.
-- clocks : The clock provided by the SoC to drive the PWM.
-- interrupts: The interrupt for the PWM controller.
-
-Note: The TPM counter and period counter are shared between multiple channels, so all channels
-should use same period setting.
-
-Example:
-
-tpm4: pwm@40250000 {
- compatible = "fsl,imx7ulp-pwm";
- reg = <0x40250000 0x1000>;
- assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
- assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
- clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
- #pwm-cells = <3>;
-};
diff --git a/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.yaml b/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.yaml
new file mode 100644
index 0000000..fe9ef42
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/imx-tpm-pwm.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/imx-tpm-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX TPM PWM controller
+
+maintainers:
+ - Anson Huang <anson.huang@nxp.com>
+
+description: |
+ The TPM counter and period counter are shared between multiple
+ channels, so all channels should use same period setting.
+
+properties:
+ "#pwm-cells":
+ const: 3
+
+ compatible:
+ enum:
+ - fsl,imx7ulp-pwm
+
+ reg:
+ maxItems: 1
+
+ assigned-clocks:
+ maxItems: 1
+
+ assigned-clock-parents:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - "#pwm-cells"
+ - compatible
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx7ulp-clock.h>
+
+ pwm@40250000 {
+ compatible = "fsl,imx7ulp-pwm";
+ reg = <0x40250000 0x1000>;
+ assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
+ assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
+ clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
+ #pwm-cells = <3>;
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH 1/2] dt-bindings: pwm: Convert imx pwm to json-schema
From: Anson Huang @ 2020-05-14 6:54 UTC (permalink / raw)
To: thierry.reding, u.kleine-koenig, robh+dt, shawnguo, s.hauer,
kernel, festevam, p.zabel, linux-pwm, devicetree,
linux-arm-kernel, linux-kernel
Cc: Linux-imx
Convert the imx pwm binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
Documentation/devicetree/bindings/pwm/imx-pwm.txt | 27 ---------
Documentation/devicetree/bindings/pwm/imx-pwm.yaml | 66 ++++++++++++++++++++++
2 files changed, 66 insertions(+), 27 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pwm/imx-pwm.txt
create mode 100644 Documentation/devicetree/bindings/pwm/imx-pwm.yaml
diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.txt b/Documentation/devicetree/bindings/pwm/imx-pwm.txt
deleted file mode 100644
index 22f1c3d..0000000
--- a/Documentation/devicetree/bindings/pwm/imx-pwm.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-Freescale i.MX PWM controller
-
-Required properties:
-- compatible : should be "fsl,<soc>-pwm" and one of the following
- compatible strings:
- - "fsl,imx1-pwm" for PWM compatible with the one integrated on i.MX1
- - "fsl,imx27-pwm" for PWM compatible with the one integrated on i.MX27
-- reg: physical base address and length of the controller's registers
-- #pwm-cells: 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.yaml
- in this directory for a description of the cells format.
-- clocks : Clock specifiers for both ipg and per clocks.
-- clock-names : Clock names should include both "ipg" and "per"
-See the clock consumer binding,
- Documentation/devicetree/bindings/clock/clock-bindings.txt
-- interrupts: The interrupt for the pwm controller
-
-Example:
-
-pwm1: pwm@53fb4000 {
- #pwm-cells = <3>;
- compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
- reg = <0x53fb4000 0x4000>;
- clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
- <&clks IMX5_CLK_PWM1_HF_GATE>;
- clock-names = "ipg", "per";
- interrupts = <61>;
-};
diff --git a/Documentation/devicetree/bindings/pwm/imx-pwm.yaml b/Documentation/devicetree/bindings/pwm/imx-pwm.yaml
new file mode 100644
index 0000000..4b62af2
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/imx-pwm.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/imx-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX PWM controller
+
+maintainers:
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+properties:
+ "#pwm-cells":
+ description: |
+ Should be 2 for i.MX1 and 3 for i.MX27 and newer SoCs. See pwm.yaml
+ in this directory for a description of the cells format.
+ enum:
+ - 2
+ - 3
+
+ compatible:
+ enum:
+ - fsl,imx1-pwm
+ - fsl,imx27-pwm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: SoC PWM ipg clock
+ - description: SoC PWM per clock
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: ipg
+ - const: per
+ maxItems: 2
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - "#pwm-cells"
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx5-clock.h>
+
+ pwm@53fb4000 {
+ #pwm-cells = <3>;
+ compatible = "fsl,imx27-pwm";
+ reg = <0x53fb4000 0x4000>;
+ clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
+ <&clks IMX5_CLK_PWM1_HF_GATE>;
+ clock-names = "ipg", "per";
+ interrupts = <61>;
+ };
--
2.7.4
^ permalink raw reply related
* Re: [PATCH V3 6/8] phy: tegra: xusb: Add support for charger detect
From: Chunfeng Yun @ 2020-05-14 7:02 UTC (permalink / raw)
To: Nagarjuna Kristam
Cc: balbi, gregkh, thierry.reding, jonathanh, mark.rutland, robh+dt,
kishon, devicetree, linux-tegra, linux-usb, linux-kernel
In-Reply-To: <1589437363-16727-7-git-send-email-nkristam@nvidia.com>
On Thu, 2020-05-14 at 11:52 +0530, Nagarjuna Kristam wrote:
> Perform charger-detect operation if corresponding dt property is enabled.
> Update usb-phy with the detected charger state and max current values.
> Register charger-detect API's of usb-phy to provide needed functionalities.
>
> Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
> ---
> V3:
> - Allighed functions and its arguments.
> - replaced spaced by tabs for MACRO definition allignments.
> - Unified primary and secondary charger detect API's.
> - Used readl_poll_timeout instead of while loop condition check for register.
> - Fixed other comments as per inputs from Thierry.
> ---
> V2:
> - Patch re-based.
> ---
> drivers/phy/tegra/Makefile | 2 +-
> drivers/phy/tegra/cd.c | 283 +++++++++++++++++++++++++++++++++++++++++++++
> drivers/phy/tegra/xusb.c | 80 +++++++++++++
> drivers/phy/tegra/xusb.h | 7 ++
> 4 files changed, 371 insertions(+), 1 deletion(-)
> create mode 100644 drivers/phy/tegra/cd.c
>
> diff --git a/drivers/phy/tegra/Makefile b/drivers/phy/tegra/Makefile
> index 89b8406..befdfc4 100644
> --- a/drivers/phy/tegra/Makefile
> +++ b/drivers/phy/tegra/Makefile
> @@ -1,7 +1,7 @@
> # SPDX-License-Identifier: GPL-2.0-only
> obj-$(CONFIG_PHY_TEGRA_XUSB) += phy-tegra-xusb.o
>
> -phy-tegra-xusb-y += xusb.o
> +phy-tegra-xusb-y += xusb.o cd.o
> phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_124_SOC) += xusb-tegra124.o
> phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_132_SOC) += xusb-tegra124.o
> phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o
> diff --git a/drivers/phy/tegra/cd.c b/drivers/phy/tegra/cd.c
> new file mode 100644
> index 0000000..fddbe4c
> --- /dev/null
> +++ b/drivers/phy/tegra/cd.c
> @@ -0,0 +1,283 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/iopoll.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/phy/phy.h>
> +
> +#include "xusb.h"
> +
> +/* Data contact detection timeout */
> +#define TDCD_TIMEOUT_MS 400
> +
> +#define USB2_BATTERY_CHRG_OTGPADX_CTL0(x) (0x80 + (x) * 0x40)
> +#define PD_CHG (1 << 0)
> +#define VDCD_DET_FILTER_EN (1 << 4)
> +#define VDAT_DET (1 << 5)
> +#define VDAT_DET_FILTER_EN (1 << 8)
> +#define OP_SINK_EN (1 << 9)
> +#define OP_SRC_EN (1 << 10)
> +#define ON_SINK_EN (1 << 11)
> +#define ON_SRC_EN (1 << 12)
> +#define OP_I_SRC_EN (1 << 13)
> +#define ZIP_FILTER_EN (1 << 21)
> +#define ZIN_FILTER_EN (1 << 25)
> +#define DCD_DETECTED (1 << 26)
Use BIT() ?
> +
> +#define USB2_BATTERY_CHRG_OTGPADX_CTL1(x) (0x84 + (x) * 0x40)
> +#define PD_VREG (1 << 6)
> +#define VREG_LEV(x) (((x) & 0x3) << 7)
> +#define VREG_DIR(x) (((x) & 0x3) << 11)
> +#define VREG_DIR_IN VREG_DIR(1)
> +#define VREG_DIR_OUT VREG_DIR(2)
> +#define USBOP_RPD_OVRD (1 << 16)
> +#define USBOP_RPD_OVRD_VAL (1 << 17)
> +#define USBOP_RPU_OVRD (1 << 18)
> +#define USBOP_RPU_OVRD_VAL (1 << 19)
> +#define USBON_RPD_OVRD (1 << 20)
> +#define USBON_RPD_OVRD_VAL (1 << 21)
> +#define USBON_RPU_OVRD (1 << 22)
> +#define USBON_RPU_OVRD_VAL (1 << 23)
> +
> +#define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x88 + (x) * 0x40)
> +#define USB2_OTG_PD2 (1 << 27)
> +#define USB2_OTG_PD2_OVRD_EN (1 << 28)
> +#define USB2_OTG_PD_ZI (1 << 29)
> +
> +#define XUSB_PADCTL_USB2_BATTERY_CHRG_TDCD_DBNC_TIMER_0 (0x280)
> +#define TDCD_DBNC(x) (((x) & 0x7ff) << 0)
> +
> +static void
> +tegra_xusb_padctl_set_debounce_time(struct tegra_xusb_padctl *padctl,
> + u32 debounce)
^ permalink raw reply
* Re: [PATCH 3/3] drm/bridge: Introduce LT9611 DSI to HDMI bridge
From: Vinod Koul @ 2020-05-14 7:06 UTC (permalink / raw)
To: Emil Velikov
Cc: Daniel Vetter, David Airlie, Rob Clark, devicetree,
Jernej Skrabec, Neil Armstrong, linux-arm-msm, Jonas Karlman,
Linux-Kernel@Vger. Kernel. Org, ML dri-devel, Bjorn Andersson,
Andrzej Hajda, Rob Herring, Laurent Pinchart
In-Reply-To: <CACvgo502+8YroB5QtnGYFeSu92s_vpe_M3cPFeuC77u9xpanXQ@mail.gmail.com>
Hello Emil,
Thanks for the comments.
On 13-05-20, 20:20, Emil Velikov wrote:
> Hi Vinod,
>
> Few high-level comments:
> - handful of functions always return 0 and the return value is never
> checked - switch to return void
Sure makes sense, will do
> - annotate all (nearly) arrays as static const
Will do
> - consistently use multi_reg_write - in some cases non-const array
> will be fine, overwriting a few entries as needed
Okay that makes sense
> - there is very partial comments about the registers/values - missing docs or?
yeah am not a big fan either, problem is documentation.
Well the spec I have doesn't have register names and few registers are
missing :( I have few name created but naming registers turned nasty
super quick.. Do let me know if you have suggestions, I will give it one
more shot though
> Personally I'm in favour of using symbolic names, instead of
> hex+comment. Considering how partial the comments are, current
> approach is perfectly fine.
>
> On Wed, 13 May 2020 at 11:06, Vinod Koul <vkoul@kernel.org> wrote:
> >
> > Lontium Lt9611 is a DSI to HDMI bridge which supports two DSI ports and
> > I2S port as an input and HDMI port as output
> >
> > Co-developed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
>
> > --- /dev/null
> > +++ b/drivers/gpu/drm/bridge/lt9611.c
>
> Please add a vendor prefix to the filename.
Okay
> > +struct lt9611_mode {
> > + u16 hdisplay;
> > + u16 vdisplay;
> > + u8 fps;
> We all enjoy the odd fps game, but let's use vrefresh here.
Sure will change
> > +static int lt9611_mipi_input_digital(struct lt9611 *lt9611,
> > + const struct drm_display_mode *mode)
> > +{
> > + regmap_write(lt9611->regmap, 0x8300, LT9611_4LANES);
> > +
> > + if (mode->hdisplay == 3840)
> > + regmap_write(lt9611->regmap, 0x830a, 0x03);
> > + else
> > + regmap_write(lt9611->regmap, 0x830a, 0x00);
> > +
> > + regmap_write(lt9611->regmap, 0x824f, 0x80);
> > + regmap_write(lt9611->regmap, 0x8250, 0x10);
> > + regmap_write(lt9611->regmap, 0x8302, 0x0a);
> > + regmap_write(lt9611->regmap, 0x8306, 0x0a);
> Create an (non-const) array, overwriting the [1] entry for 3840 mode?
So array is the recommendation, I dont have much liking for them but I
can see they would be useful here, so will change this and other
instances and we can use regmap_multi_reg_write() while taking care of
static const for non modified arrays
>
> > +
> > + return 0;
> Kill return type.
Yup, here and other places
> > + regmap_write(lt9611->regmap, 0x82e3, pclk >> 17); /* pclk[19:16] */
> > + regmap_write(lt9611->regmap, 0x82e4, pclk >> 9); /* pclk[15:8] */
> > + regmap_write(lt9611->regmap, 0x82e5, pclk >> 1); /* pclk[7:0] */
> Comment does not match the code.
> We're discarding the LSB, so we cannot realistically be writing
> pclk[7:0]. Similar applies for the other two.
Thanks for pointing, will fix it up
> > + /* v_act */
> > + ret = regmap_read(lt9611->regmap, 0x8282, &temp);
> > + if (ret)
> > + goto end;
> > +
> > + v_act = temp << 8;
> > + ret = regmap_read(lt9611->regmap, 0x8283, &temp);
> > + if (ret)
> > + goto end;
> > + v_act = v_act + temp;
> > +
> Having a helper for the above "result = read(x) << 8 | read(x+1)"
> would be great.
> This way one doesn't have to repeat the pattern 4-5 times.
will add
> > +static int lt9611_read_edid(struct lt9611 *lt9611)
> > +{
> > + unsigned int temp;
> > + int ret = 0;
> > + int i, j;
> > +
> > + memset(lt9611->edid_buf, 0, EDID_SEG_SIZE);
> How about:
> memset(lt9611->edid_buf, 0, sizeof(lt9611->edid_buf));
>
> Then again, do we need the memset()? We are allocating the memory with
> devm_kzalloc()
Yes but lt9611_read_edid() is called multiple times so would make sense
to memset it, will modify this to sizeof.
> > +
> > + regmap_write(lt9611->regmap, 0x8503, 0xc9);
> > +
> > + /* 0xA0 is EDID device address */
> > + regmap_write(lt9611->regmap, 0x8504, 0xa0);
> > + /* 0x00 is EDID offset address */
> > + regmap_write(lt9611->regmap, 0x8505, 0x00);
> > + /* length for read */
> > + regmap_write(lt9611->regmap, 0x8506, 0x20);
> Is this the same 32 as seen in the loops below? #define and use consistently?
Sure will use defines here and other places
> > + if (block > 1)
> > + return -EINVAL;
> > +
> > + if (block == 0) {
> > + /* always read 2 edid blocks once */
> Please mention why that's a good idea. From memory - there aren't many
> other drivers that do this.
Okay will find the reason for this and
>
> > + ret = lt9611_read_edid(lt9611);
> > + if (ret) {
> > + dev_err(lt9611->dev, "edid read failed\n");
> > + return ret;
> > + }
> > + }
> > +
> > + if (block % 2 == 0)
> > + memcpy(buf, lt9611->edid_buf, len);
> > + else
> > + memcpy(buf, lt9611->edid_buf + 128, len);
> The above can be written as:
> memcpy(buf, lt9611->edid_buf + (block * 128), len);
correct
> > + /* Attach secondary DSI, if specified */
> > + if (lt9611->dsi1_node) {
> > + lt9611->dsi1 = lt9611_attach_dsi(lt9611, lt9611->dsi1_node);
> > + if (IS_ERR(lt9611->dsi1)) {
> > + ret = PTR_ERR(lt9611->dsi1);
> > + goto err_unregister_dsi0;
> > + }
> > + }
> > +
> > + return 0;
> > +
> > +err_unregister_dsi0:
> Missing detach? If possible directly use lt9611_bridge_detach().
will update
> > +static int lt9611_read_device_rev(struct lt9611 *lt9611)
> > +{
> > + unsigned int rev;
> > + int ret;
> > +
> > + regmap_write(lt9611->regmap, 0x80ee, 0x01);
> > + ret = regmap_read(lt9611->regmap, 0x8002, &rev);
> > + if (ret)
> > + dev_err(lt9611->dev, "failed to read revision: %d\n", ret);
> > +
> The "failed" message will be followed by printing random kernel memory.
> Initialize rev to some dummy number or omit the dev_info.
Am printing the 'ret' error code here and not the uninitialized rev, so
I guess this one should be fine
> > + ret = lt9611_parse_dt(&client->dev, lt9611);
> > + if (ret) {
> > + dev_err(dev, "failed to parse device tree\n");
> > + return ret;
> > + }
> > +
> > + ret = lt9611_gpio_init(lt9611);
> > + if (ret < 0)
> Missing of_node_put() here and for the next few error paths.
Yes this should be replaced by jump to of_node_put below
> > +static const struct of_device_id lt9611_match_table[] = {
> > + {.compatible = "lontium,lt9611"},
> In the above two - add space after { and before }. Pretty sure
Correct, will fix this.
> ./scripts/checkpatch.pl will complain about those.
> Might want to double-check for other issues reported by said tool.
Somehow that was not the case :( I always run checkpatch.pl with
--strict option. I have 1 warn about 80 char limit for a error message
which I have ignored :)
--
~Vinod
^ permalink raw reply
* revised product enquiry
From: Franziska Glas @ 2020-05-14 7:14 UTC (permalink / raw)
To: devicetree
[-- Attachment #1: Type: text/plain, Size: 433 bytes --]
Hope you are keeping safe,
Please find attached a new purchase request for May
Review the order and let us know the prices, delivery date, item
specification and revert to us
immediately.
I hope this time production will be faster.
I´ll be waiting for your confirmation
Best Regards
(Ms) Franziska Glas
Hosmed Oy
Ennekuja 1
02270 ESPOO
Tel. +358 20 7755 330
Fax +358 20 7755 339
sales@datacom.com.tw
[-- Attachment #2: scan_004768.pdf.zip --]
[-- Type: application/zip, Size: 25070 bytes --]
^ permalink raw reply
* Re: [PATCH 5/4] dt-bindings: display: bridge: thc63lvd1024: Document dual-output mode
From: Jacopo Mondi @ 2020-05-14 7:18 UTC (permalink / raw)
To: Laurent Pinchart; +Cc: dri-devel, devicetree, linux-renesas-soc, Rob Herring
In-Reply-To: <20200513232127.21798-1-laurent.pinchart+renesas@ideasonboard.com>
Hi Laurent,
On Thu, May 14, 2020 at 02:21:27AM +0300, Laurent Pinchart wrote:
> The DT binding support both dual-input and dual-output mode, but only
> dual-input is documented. Document dual-output mode.
>
> Suggested-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Thanks
Acked-by: Jacopo Mondi <jacopo@jmondi.org>
> ---
> .../display/bridge/thine,thc63lvd1024.yaml | 16 +++++++++++-----
> 1 file changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.yaml b/Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.yaml
> index 469ac4a34273..fedd3460d6f6 100644
> --- a/Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.yaml
> +++ b/Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.yaml
> @@ -30,11 +30,17 @@ properties:
> This device has four video ports. Their connections are modeled using the
> OF graph bindings specified in Documentation/devicetree/bindings/graph.txt.
>
> - The device can operate in single-link mode or dual-link mode. In
> - single-link mode, all pixels are received on port@0, and port@1 shall not
> - contain any endpoint. In dual-link mode, even-numbered pixels are
> - received on port@0 and odd-numbered pixels on port@1, and both port@0 and
> - port@1 shall contain endpoints.
> + The device can operate in single or dual input and output modes.
> +
> + When operating in single input mode, all pixels are received on port@0,
> + and port@1 shall not contain any endpoint. In dual input mode,
> + even-numbered pixels are received on port@0 and odd-numbered pixels on
> + port@1, and both port@0 and port@1 shall contain endpoints.
> +
> + When operating in single output mode all pixels are output from the first
> + CMOS/TTL port and port@3 shall not contain any endpoint. In dual output
> + mode pixels are output from both CMOS/TTL ports and both port@2 and
> + port@3 shall contain endpoints.
>
> properties:
> '#address-cells':
> --
> Regards,
>
> Laurent Pinchart
>
^ permalink raw reply
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