* Re: [PATCH v9 2/4] media: i2c: Add MAX9286 driver
From: Kieran Bingham @ 2020-05-14 9:53 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: linux-renesas-soc, linux-media, devicetree, linux-kernel,
Mauro Carvalho Chehab, Kieran Bingham, Laurent Pinchart,
Jacopo Mondi, Niklas Söderlund, sakari.ailus, Hans Verkuil,
Hyun Kwon, Rob Herring, Jacopo Mondi, Laurent Pinchart,
Niklas Söderlund
In-Reply-To: <20200512174056.GH5526@Mani-XPS-13-9360>
Hi Mani,
On 12/05/2020 18:40, Manivannan Sadhasivam wrote:
> Hi Kieran,
>
> On Tue, May 12, 2020 at 04:51:03PM +0100, Kieran Bingham wrote:
>> The MAX9286 is a 4-channel GMSL deserializer with coax or STP input and
>> CSI-2 output. The device supports multicamera streaming applications,
>> and features the ability to synchronise the attached cameras.
>>
>> CSI-2 output can be configured with 1 to 4 lanes, and a control channel
>> is supported over I2C, which implements an I2C mux to facilitate
>> communications with connected cameras across the reverse control
>> channel.
>>
>> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
>> Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
>> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
>> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
>>
>> --
>> v2:
>> - Fix MAINTAINERS entry
>>
>> This posting is released with the following modifications to work
>> without Sakari's VC developments:
>> - max9286_g_mbus_config() re-instated
>> - max9286_get_frame_desc() is not bus/csi aware
>> - max9286_{get,set}_routing() removed
>>
>> v3:
>> - Initialise notifier with v4l2_async_notifier_init
>> - Update for new mbus csi2 format V4L2_MBUS_CSI2_DPHY
>>
>> v4: - Re-introduce required code to function with the VC series.
>>
>> - Implement max9286_get_routing, max9286_set_routing
>> - Remove max9286_g_mbus_config
>>
>> v5: (internal release)
>> - Fix printk formatting for hex value
>> - max9286->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE (add |)
>> - MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER -> MEDIA_ENT_F_VID_IF_BRIDGE
>> - Remove 'device is bound' workaround
>>
>> v6:
>> - v4l2_subdev_krouting instead of v4l2_subdev_routing separated
>> to allow integration without the VC/V4L2-Mux series.
>> - convert sd_to_max9286 to inline function
>> - rename max9286_device to max9286_priv
>> - Cleanup the v4l2_async_notifier
>> - Extend MODULE_AUTHOR
>> - Replace of_graph_get_endpoint_by_regs with fwnode_graph_get_endpoint_by_id
>> - Pass default bus type when parsing fwnode endpoint (Manivannan Sadhasivam)
>> - Use new YAML file reference in MAINTAINERS
>> - Parse new i2c-mux node in max9286_get_i2c_by_id
>> (This could/should be refactored to parse these separately first)
>> - Spelling and calculation fixes in the FSYNC_LOCKED check comments
>> - Identify each enabled i2c-mux channel in a single pass
>> - max9286: Improve mux-state readbility [v2]
>> - Fix frame sync lock durations
>> - Add comment to describe /why/ we must open the mux in s_stream
>> - use -EXDEV as return code for failed link synchronisation.
>> - Fix reference counting of the dt nodeS
>> - Convert to probe_new for I2C
>> - Remove redundant max9286_i2c_mux_state
>> - Provide optional enable-gpio (max9286-pwdn)
>>
>> v7:
>> [Kieran]
>> - Ensure powerdown lines are optional
>> - Add a 4ms power-up delay
>> - Add max9286_check_config_link() to core
>> - Add GPIO chip controller for GPIO0OUT and GPIO1OUT
>> - Fix GPIO registration
>> - max9286: Split out async registration
>> (fixes regulator -EPROBE_DEFERs failures)
>> - Collect all V4L2 registrations
>> - balance v4l2_async refcnting
>> - Rename max9286_v4l2_async_ => max9286_v4l2_notifier_
>>
>> [Jacopo]
>> - Remove redundanct MAXIM_I2C_SPEED macros
>> - Move notifiers operations
>> - Add delay after reverse channel reconfiguration
>> - Move link setup to completion
>> - Fix up max9286_check_config_link() implementation
>> - Remove redundant dual configuration of reverse channel
>>
>> v8:
>>
>> [Kieran]
>> - Update the bound_sources mask on unbind
>> - Convert probe kzalloc usage to devm_ variant
>> - Fix up cleanup path from GPIO PowerDown registration
>> - cleanup GPIO device registration fail path
>> - Convert to use devm_regulator_get()
>> - Fit max9286_parse_dt print on one line
>> - Move multi-device workarounds out of upstream driver
>> - Remove I2C mod-table
>> - Lock format changes
>> - Describe pad index usage
>> - Remove poc_enabled workaround
>> - Rename the max9286_gpio to be more explicit on it's actions.
>> - Move max9286_init_format call
>> - Rework probe sequence and simplify error paths.
>> - Simplify i2c comments
>> - Implement Pixelrate control
>> - Disable overlap window
>>
>> [Jacopo]
>> - Adapt Kconfig to latest upstream changes
>> - Put of node on error
>> - Calculate pixel rate
>> - Simplify overlap window disablement
>>
>> v9:
>>
>> [Kieran]
>> - Kconfig: Depend on OF
>> - Re-sort addition to Makefile
>> ---
>> MAINTAINERS | 10 +
>> drivers/media/i2c/Kconfig | 13 +
>> drivers/media/i2c/Makefile | 1 +
>> drivers/media/i2c/max9286.c | 1332 +++++++++++++++++++++++++++++++++++
>> 4 files changed, 1356 insertions(+)
>> create mode 100644 drivers/media/i2c/max9286.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index a7bb6e22d5da..99e3bf7760fd 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -10274,6 +10274,16 @@ F: Documentation/hwmon/max6697.rst
>> F: drivers/hwmon/max6697.c
>> F: include/linux/platform_data/max6697.h
>>
>> +MAX9286 QUAD GMSL DESERIALIZER DRIVER
>> +M: Jacopo Mondi <jacopo+renesas@jmondi.org>
>> +M: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
>> +M: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
>> +M: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
>> +L: linux-media@vger.kernel.org
>> +S: Maintained
>> +F: Documentation/devicetree/bindings/media/i2c/maxim,max9286.yaml
>> +F: drivers/media/i2c/max9286.c
>> +
>> MAX9860 MONO AUDIO VOICE CODEC DRIVER
>> M: Peter Rosin <peda@axentia.se>
>> L: alsa-devel@alsa-project.org (moderated for non-subscribers)
>> diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
>> index 3abc80373ec0..2e390f41f6da 100644
>> --- a/drivers/media/i2c/Kconfig
>> +++ b/drivers/media/i2c/Kconfig
>> @@ -464,6 +464,19 @@ config VIDEO_VPX3220
>> To compile this driver as a module, choose M here: the
>> module will be called vpx3220.
>>
>> +config VIDEO_MAX9286
>> + tristate "Maxim MAX9286 GMSL deserializer support"
>> + depends on I2C && I2C_MUX
>> + depends on OF
>> + select V4L2_FWNODE
>> + select VIDEO_V4L2_SUBDEV_API
>> + select MEDIA_CONTROLLER
>> + help
>> + This driver supports the Maxim MAX9286 GMSL deserializer.
>> +
>> + To compile this driver as a module, choose M here: the
>> + module will be called max9286.
>> +
>> comment "Video and audio decoders"
>>
>> config VIDEO_SAA717X
>> diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
>> index 77bf7d0b691f..f0b001ee4b05 100644
>> --- a/drivers/media/i2c/Makefile
>> +++ b/drivers/media/i2c/Makefile
>> @@ -117,6 +117,7 @@ obj-$(CONFIG_VIDEO_IMX274) += imx274.o
>> obj-$(CONFIG_VIDEO_IMX290) += imx290.o
>> obj-$(CONFIG_VIDEO_IMX319) += imx319.o
>> obj-$(CONFIG_VIDEO_IMX355) += imx355.o
>> +obj-$(CONFIG_VIDEO_MAX9286) += max9286.o
>> obj-$(CONFIG_VIDEO_ST_MIPID02) += st-mipid02.o
>>
>> obj-$(CONFIG_SDR_MAX2175) += max2175.o
>> diff --git a/drivers/media/i2c/max9286.c b/drivers/media/i2c/max9286.c
>> new file mode 100644
>> index 000000000000..481d65f2b51d
>> --- /dev/null
>> +++ b/drivers/media/i2c/max9286.c
>> @@ -0,0 +1,1332 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Maxim MAX9286 GMSL Deserializer Driver
>> + *
>> + * Copyright (C) 2017-2019 Jacopo Mondi
>> + * Copyright (C) 2017-2019 Kieran Bingham
>> + * Copyright (C) 2017-2019 Laurent Pinchart
>> + * Copyright (C) 2017-2019 Niklas Söderlund
>> + * Copyright (C) 2016 Renesas Electronics Corporation
>> + * Copyright (C) 2015 Cogent Embedded, Inc.
>> + */
>> +
>> +#include <linux/delay.h>
>> +#include <linux/device.h>
>> +#include <linux/fwnode.h>
>> +#include <linux/gpio/consumer.h>
>> +#include <linux/gpio/driver.h>
>> +#include <linux/i2c.h>
>> +#include <linux/i2c-mux.h>
>> +#include <linux/module.h>
>> +#include <linux/mutex.h>
>> +#include <linux/of_graph.h>
>> +#include <linux/regulator/consumer.h>
>> +#include <linux/slab.h>
>> +
>> +#include <media/v4l2-async.h>
>> +#include <media/v4l2-ctrls.h>
>> +#include <media/v4l2-device.h>
>> +#include <media/v4l2-fwnode.h>
>> +#include <media/v4l2-subdev.h>
>> +
>> +/* Register 0x00 */
>> +#define MAX9286_MSTLINKSEL_AUTO (7 << 5)
>> +#define MAX9286_MSTLINKSEL(n) ((n) << 5)
>> +#define MAX9286_EN_VS_GEN BIT(4)
>> +#define MAX9286_LINKEN(n) (1 << (n))
>> +/* Register 0x01 */
>> +#define MAX9286_FSYNCMODE_ECU (3 << 6)
>> +#define MAX9286_FSYNCMODE_EXT (2 << 6)
>> +#define MAX9286_FSYNCMODE_INT_OUT (1 << 6)
>> +#define MAX9286_FSYNCMODE_INT_HIZ (0 << 6)
>> +#define MAX9286_GPIEN BIT(5)
>> +#define MAX9286_ENLMO_RSTFSYNC BIT(2)
>> +#define MAX9286_FSYNCMETH_AUTO (2 << 0)
>> +#define MAX9286_FSYNCMETH_SEMI_AUTO (1 << 0)
>> +#define MAX9286_FSYNCMETH_MANUAL (0 << 0)
>> +#define MAX9286_REG_FSYNC_PERIOD_L 0x06
>> +#define MAX9286_REG_FSYNC_PERIOD_M 0x07
>> +#define MAX9286_REG_FSYNC_PERIOD_H 0x08
>> +/* Register 0x0a */
>> +#define MAX9286_FWDCCEN(n) (1 << ((n) + 4))
>> +#define MAX9286_REVCCEN(n) (1 << (n))
>> +/* Register 0x0c */
>> +#define MAX9286_HVEN BIT(7)
>> +#define MAX9286_EDC_6BIT_HAMMING (2 << 5)
>> +#define MAX9286_EDC_6BIT_CRC (1 << 5)
>> +#define MAX9286_EDC_1BIT_PARITY (0 << 5)
>> +#define MAX9286_DESEL BIT(4)
>> +#define MAX9286_INVVS BIT(3)
>> +#define MAX9286_INVHS BIT(2)
>> +#define MAX9286_HVSRC_D0 (2 << 0)
>> +#define MAX9286_HVSRC_D14 (1 << 0)
>> +#define MAX9286_HVSRC_D18 (0 << 0)
>> +/* Register 0x0f */
>> +#define MAX9286_0X0F_RESERVED BIT(3)
>> +/* Register 0x12 */
>> +#define MAX9286_CSILANECNT(n) (((n) - 1) << 6)
>> +#define MAX9286_CSIDBL BIT(5)
>> +#define MAX9286_DBL BIT(4)
>> +#define MAX9286_DATATYPE_USER_8BIT (11 << 0)
>> +#define MAX9286_DATATYPE_USER_YUV_12BIT (10 << 0)
>> +#define MAX9286_DATATYPE_USER_24BIT (9 << 0)
>> +#define MAX9286_DATATYPE_RAW14 (8 << 0)
>> +#define MAX9286_DATATYPE_RAW11 (7 << 0)
>> +#define MAX9286_DATATYPE_RAW10 (6 << 0)
>> +#define MAX9286_DATATYPE_RAW8 (5 << 0)
>> +#define MAX9286_DATATYPE_YUV422_10BIT (4 << 0)
>> +#define MAX9286_DATATYPE_YUV422_8BIT (3 << 0)
>> +#define MAX9286_DATATYPE_RGB555 (2 << 0)
>> +#define MAX9286_DATATYPE_RGB565 (1 << 0)
>> +#define MAX9286_DATATYPE_RGB888 (0 << 0)
>> +/* Register 0x15 */
>> +#define MAX9286_VC(n) ((n) << 5)
>> +#define MAX9286_VCTYPE BIT(4)
>> +#define MAX9286_CSIOUTEN BIT(3)
>> +#define MAX9286_0X15_RESV (3 << 0)
>> +/* Register 0x1b */
>> +#define MAX9286_SWITCHIN(n) (1 << ((n) + 4))
>> +#define MAX9286_ENEQ(n) (1 << (n))
>> +/* Register 0x27 */
>> +#define MAX9286_LOCKED BIT(7)
>> +/* Register 0x31 */
>> +#define MAX9286_FSYNC_LOCKED BIT(6)
>> +/* Register 0x34 */
>> +#define MAX9286_I2CLOCACK BIT(7)
>> +#define MAX9286_I2CSLVSH_1046NS_469NS (3 << 5)
>> +#define MAX9286_I2CSLVSH_938NS_352NS (2 << 5)
>> +#define MAX9286_I2CSLVSH_469NS_234NS (1 << 5)
>> +#define MAX9286_I2CSLVSH_352NS_117NS (0 << 5)
>> +#define MAX9286_I2CMSTBT_837KBPS (7 << 2)
>> +#define MAX9286_I2CMSTBT_533KBPS (6 << 2)
>> +#define MAX9286_I2CMSTBT_339KBPS (5 << 2)
>> +#define MAX9286_I2CMSTBT_173KBPS (4 << 2)
>> +#define MAX9286_I2CMSTBT_105KBPS (3 << 2)
>> +#define MAX9286_I2CMSTBT_84KBPS (2 << 2)
>> +#define MAX9286_I2CMSTBT_28KBPS (1 << 2)
>> +#define MAX9286_I2CMSTBT_8KBPS (0 << 2)
>> +#define MAX9286_I2CSLVTO_NONE (3 << 0)
>> +#define MAX9286_I2CSLVTO_1024US (2 << 0)
>> +#define MAX9286_I2CSLVTO_256US (1 << 0)
>> +#define MAX9286_I2CSLVTO_64US (0 << 0)
>> +/* Register 0x3b */
>> +#define MAX9286_REV_TRF(n) ((n) << 4)
>> +#define MAX9286_REV_AMP(n) ((((n) - 30) / 10) << 1) /* in mV */
>> +#define MAX9286_REV_AMP_X BIT(0)
>> +/* Register 0x3f */
>> +#define MAX9286_EN_REV_CFG BIT(6)
>> +#define MAX9286_REV_FLEN(n) ((n) - 20)
>> +/* Register 0x49 */
>> +#define MAX9286_VIDEO_DETECT_MASK 0x0f
>> +/* Register 0x69 */
>> +#define MAX9286_LFLTBMONMASKED BIT(7)
>> +#define MAX9286_LOCKMONMASKED BIT(6)
>> +#define MAX9286_AUTOCOMBACKEN BIT(5)
>> +#define MAX9286_AUTOMASKEN BIT(4)
>> +#define MAX9286_MASKLINK(n) ((n) << 0)
>> +
>> +/*
>> + * The sink and source pads are created to match the OF graph port numbers so
>> + * that their indexes can be used interchangeably.
>> + */
>> +#define MAX9286_NUM_GMSL 4
>> +#define MAX9286_N_SINKS 4
>> +#define MAX9286_N_PADS 5
>> +#define MAX9286_SRC_PAD 4
>> +
>> +struct max9286_source {
>> + struct v4l2_async_subdev asd;
>> + struct v4l2_subdev *sd;
>> + struct fwnode_handle *fwnode;
>> +};
>> +
>> +#define asd_to_max9286_source(_asd) \
>> + container_of(_asd, struct max9286_source, asd)
>> +
>> +struct max9286_priv {
>> + struct i2c_client *client;
>> + struct gpio_desc *gpiod_pwdn;
>> + struct v4l2_subdev sd;
>> + struct media_pad pads[MAX9286_N_PADS];
>> + struct regulator *regulator;
>> +
>> + struct gpio_chip gpio;
>> + u8 gpio_state;
>> +
>> + struct i2c_mux_core *mux;
>> + unsigned int mux_channel;
>> + bool mux_open;
>> +
>> + struct v4l2_ctrl_handler ctrls;
>> + struct v4l2_ctrl *pixelrate;
>> +
>> + struct v4l2_mbus_framefmt fmt[MAX9286_N_SINKS];
>> +
>> + /* Protects controls and fmt structures */
>> + struct mutex mutex;
>> +
>> + unsigned int nsources;
>> + unsigned int source_mask;
>> + unsigned int route_mask;
>> + unsigned int bound_sources;
>> + unsigned int csi2_data_lanes;
>> + struct max9286_source sources[MAX9286_NUM_GMSL];
>> + struct v4l2_async_notifier notifier;
>> +};
>> +
>> +static struct max9286_source *next_source(struct max9286_priv *priv,
>> + struct max9286_source *source)
>> +{
>> + if (!source)
>> + source = &priv->sources[0];
>> + else
>> + source++;
>> +
>> + for (; source < &priv->sources[MAX9286_NUM_GMSL]; source++) {
>> + if (source->fwnode)
>> + return source;
>> + }
>> +
>> + return NULL;
>> +}
>> +
>> +#define for_each_source(priv, source) \
>> + for ((source) = NULL; ((source) = next_source((priv), (source))); )
>> +
>> +#define to_index(priv, source) ((source) - &(priv)->sources[0])
>> +
>> +static inline struct max9286_priv *sd_to_max9286(struct v4l2_subdev *sd)
>> +{
>> + return container_of(sd, struct max9286_priv, sd);
>> +}
>> +
>> +/* -----------------------------------------------------------------------------
>> + * I2C IO
>> + */
>> +
>> +static int max9286_read(struct max9286_priv *priv, u8 reg)
>> +{
>> + int ret;
>> +
>> + ret = i2c_smbus_read_byte_data(priv->client, reg);
>> + if (ret < 0)
>> + dev_err(&priv->client->dev,
>> + "%s: register 0x%02x read failed (%d)\n",
>> + __func__, reg, ret);
>> +
>> + return ret;
>> +}
>> +
>> +static int max9286_write(struct max9286_priv *priv, u8 reg, u8 val)
>> +{
>> + int ret;
>> +
>> + ret = i2c_smbus_write_byte_data(priv->client, reg, val);
>> + if (ret < 0)
>> + dev_err(&priv->client->dev,
>> + "%s: register 0x%02x write failed (%d)\n",
>> + __func__, reg, ret);
>> +
>> + return ret;
>> +}
>> +
>> +/* -----------------------------------------------------------------------------
>> + * I2C Multiplexer
>> + */
>> +
>> +static void max9286_i2c_mux_configure(struct max9286_priv *priv, u8 conf)
>> +{
>> + max9286_write(priv, 0x0a, conf);
>> +
>> + /*
>> + * We must sleep after any change to the forward or reverse channel
>> + * configuration.
>> + */
>> + usleep_range(3000, 5000);
>> +}
>> +
>> +static void max9286_i2c_mux_open(struct max9286_priv *priv)
>> +{
>> + /* Open all channels on the MAX9286 */
>> + max9286_i2c_mux_configure(priv, 0xff);
>> +
>> + priv->mux_open = true;
>> +}
>> +
>> +static void max9286_i2c_mux_close(struct max9286_priv *priv)
>> +{
>> + /*
>> + * Ensure that both the forward and reverse channel are disabled on the
>> + * mux, and that the channel ID is invalidated to ensure we reconfigure
>> + * on the next max9286_i2c_mux_select() call.
>> + */
>> + max9286_i2c_mux_configure(priv, 0x00);
>> +
>> + priv->mux_open = false;
>> + priv->mux_channel = -1;
>> +}
>> +
>> +static int max9286_i2c_mux_select(struct i2c_mux_core *muxc, u32 chan)
>> +{
>> + struct max9286_priv *priv = i2c_mux_priv(muxc);
>> +
>> + /* Channel select is disabled when configured in the opened state. */
>> + if (priv->mux_open)
>> + return 0;
>> +
>> + if (priv->mux_channel == chan)
>> + return 0;
>> +
>> + priv->mux_channel = chan;
>> +
>> + max9286_i2c_mux_configure(priv,
>> + MAX9286_FWDCCEN(chan) |
>> + MAX9286_REVCCEN(chan));
>> +
>> + return 0;
>> +}
>> +
>> +static int max9286_i2c_mux_init(struct max9286_priv *priv)
>> +{
>> + struct max9286_source *source;
>> + int ret;
>> +
>> + if (!i2c_check_functionality(priv->client->adapter,
>> + I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
>> + return -ENODEV;
>> +
>> + priv->mux = i2c_mux_alloc(priv->client->adapter, &priv->client->dev,
>> + priv->nsources, 0, I2C_MUX_LOCKED,
>> + max9286_i2c_mux_select, NULL);
>> + if (!priv->mux)
>> + return -ENOMEM;
>> +
>> + priv->mux->priv = priv;
>> +
>> + for_each_source(priv, source) {
>> + unsigned int index = to_index(priv, source);
>> +
>> + ret = i2c_mux_add_adapter(priv->mux, 0, index, 0);
>> + if (ret < 0)
>> + goto error;
>> + }
>> +
>> + return 0;
>> +
>> +error:
>> + i2c_mux_del_adapters(priv->mux);
>> + return ret;
>> +}
>> +
>> +static void max9286_configure_i2c(struct max9286_priv *priv, bool localack)
>> +{
>> + u8 config = MAX9286_I2CSLVSH_469NS_234NS | MAX9286_I2CSLVTO_1024US |
>> + MAX9286_I2CMSTBT_105KBPS;
>> +
>> + if (localack)
>> + config |= MAX9286_I2CLOCACK;
>> +
>> + max9286_write(priv, 0x34, config);
>> + usleep_range(3000, 5000);
>> +}
>> +
>> +/*
>> + * max9286_check_video_links() - Make sure video links are detected and locked
>> + *
>> + * Performs safety checks on video link status. Make sure they are detected
>> + * and all enabled links are locked.
>> + *
>> + * Returns 0 for success, -EIO for errors.
>> + */
>> +static int max9286_check_video_links(struct max9286_priv *priv)
>> +{
>> + unsigned int i;
>> + int ret;
>> +
>> + /*
>> + * Make sure valid video links are detected.
>> + * The delay is not characterized in de-serializer manual, wait up
>> + * to 5 ms.
>> + */
>> + for (i = 0; i < 10; i++) {
>> + ret = max9286_read(priv, 0x49);
>> + if (ret < 0)
>> + return -EIO;
>> +
>> + if ((ret & MAX9286_VIDEO_DETECT_MASK) == priv->source_mask)
>> + break;
>> +
>> + usleep_range(350, 500);
>> + }
>> +
>> + if (i == 10) {
>> + dev_err(&priv->client->dev,
>> + "Unable to detect video links: 0x%02x\n", ret);
>> + return -EIO;
>> + }
>> +
>> + /* Make sure all enabled links are locked (4ms max). */
>> + for (i = 0; i < 10; i++) {
>> + ret = max9286_read(priv, 0x27);
>> + if (ret < 0)
>> + return -EIO;
>> +
>> + if (ret & MAX9286_LOCKED)
>> + break;
>> +
>> + usleep_range(350, 450);
>> + }
>> +
>> + if (i == 10) {
>> + dev_err(&priv->client->dev, "Not all enabled links locked\n");
>> + return -EIO;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +/*
>> + * max9286_check_config_link() - Detect and wait for configuration links
>> + *
>> + * Determine if the configuration channel is up and settled for a link.
>> + *
>> + * Returns 0 for success, -EIO for errors.
>> + */
>> +static int max9286_check_config_link(struct max9286_priv *priv,
>> + unsigned int source_mask)
>> +{
>> + unsigned int conflink_mask = (source_mask & 0x0f) << 4;
>> + unsigned int i;
>> + int ret;
>> +
>> + /*
>> + * Make sure requested configuration links are detected.
>> + * The delay is not characterized in the chip manual: wait up
>> + * to 5 milliseconds.
>> + */
>> + for (i = 0; i < 10; i++) {
>> + ret = max9286_read(priv, 0x49) & 0xf0;
>> + if (ret < 0)
>> + return -EIO;
>> +
>> + if (ret == conflink_mask)
>> + break;
>> +
>> + usleep_range(350, 500);
>> + }
>> +
>> + if (ret != conflink_mask) {
>> + dev_err(&priv->client->dev,
>> + "Unable to detect configuration links: 0x%02x expected 0x%02x\n",
>> + ret, conflink_mask);
>> + return -EIO;
>> + }
>> +
>> + dev_info(&priv->client->dev,
>> + "Successfully detected configuration links after %u loops: 0x%02x\n",
>> + i, conflink_mask);
>> +
>> + return 0;
>> +}
>> +
>> +/* -----------------------------------------------------------------------------
>> + * V4L2 Subdev
>> + */
>> +
>> +static int max9286_set_pixelrate(struct max9286_priv *priv)
>> +{
>> + struct max9286_source *source = NULL;
>> + u64 pixelrate = 0;
>> +
>> + for_each_source(priv, source) {
>> + struct v4l2_ctrl *ctrl;
>> + u64 source_rate = 0;
>> +
>> + /* Pixel rate is mandatory to be reported by sources. */
>> + ctrl = v4l2_ctrl_find(source->sd->ctrl_handler,
>> + V4L2_CID_PIXEL_RATE);
>> + if (!ctrl) {
>> + pixelrate = 0;
>> + break;
>> + }
>> +
>> + /* All source must report the same pixel rate. */
>> + source_rate = v4l2_ctrl_g_ctrl_int64(ctrl);
>> + if (!pixelrate) {
>> + pixelrate = source_rate;
>> + } else if (pixelrate != source_rate) {
>> + dev_err(&priv->client->dev,
>> + "Unable to calculate pixel rate\n");
>> + return -EINVAL;
>> + }
>> + }
>> +
>> + if (!pixelrate) {
>> + dev_err(&priv->client->dev,
>> + "No pixel rate control available in sources\n");
>> + return -EINVAL;
>> + }
>> +
>> + /*
>> + * The CSI-2 transmitter pixel rate is the single source rate multiplied
>> + * by the number of available sources.
>> + */
>> + return v4l2_ctrl_s_ctrl_int64(priv->pixelrate,
>> + pixelrate * priv->nsources);
>> +}
>> +
>> +static int max9286_notify_bound(struct v4l2_async_notifier *notifier,
>> + struct v4l2_subdev *subdev,
>> + struct v4l2_async_subdev *asd)
>> +{
>> + struct max9286_priv *priv = sd_to_max9286(notifier->sd);
>> + struct max9286_source *source = asd_to_max9286_source(asd);
>> + unsigned int index = to_index(priv, source);
>> + unsigned int src_pad;
>> + int ret;
>> +
>> + ret = media_entity_get_fwnode_pad(&subdev->entity,
>> + source->fwnode,
>> + MEDIA_PAD_FL_SOURCE);
>> + if (ret < 0) {
>> + dev_err(&priv->client->dev,
>> + "Failed to find pad for %s\n", subdev->name);
>> + return ret;
>> + }
>> +
>> + priv->bound_sources |= BIT(index);
>> + source->sd = subdev;
>> + src_pad = ret;
>> +
>> + ret = media_create_pad_link(&source->sd->entity, src_pad,
>> + &priv->sd.entity, index,
>> + MEDIA_LNK_FL_ENABLED |
>> + MEDIA_LNK_FL_IMMUTABLE);
>> + if (ret) {
>> + dev_err(&priv->client->dev,
>> + "Unable to link %s:%u -> %s:%u\n",
>> + source->sd->name, src_pad, priv->sd.name, index);
>> + return ret;
>> + }
>> +
>> + dev_dbg(&priv->client->dev, "Bound %s pad: %u on index %u\n",
>> + subdev->name, src_pad, index);
>> +
>> + /*
>> + * We can only register v4l2_async_notifiers, which do not provide a
>> + * means to register a complete callback. bound_sources allows us to
>> + * identify when all remote serializers have completed their probe.
>> + */
>> + if (priv->bound_sources != priv->source_mask)
>> + return 0;
>> +
>> + /*
>> + * All enabled sources have probed and enabled their reverse control
>> + * channels:
>> + *
>> + * - Verify all configuration links are properly detected
>> + * - Disable auto-ack as communication on the control channel are now
>> + * stable.
>> + */
>> + max9286_check_config_link(priv, priv->source_mask);
>> +
>> + /*
>> + * Re-configure I2C with local acknowledge disabled after cameras have
>> + * probed.
>> + */
>> + max9286_configure_i2c(priv, false);
>> +
>> + return max9286_set_pixelrate(priv);
>> +}
>> +
>> +static void max9286_notify_unbind(struct v4l2_async_notifier *notifier,
>> + struct v4l2_subdev *subdev,
>> + struct v4l2_async_subdev *asd)
>> +{
>> + struct max9286_priv *priv = sd_to_max9286(notifier->sd);
>> + struct max9286_source *source = asd_to_max9286_source(asd);
>> + unsigned int index = to_index(priv, source);
>> +
>> + source->sd = NULL;
>> + priv->bound_sources &= ~BIT(index);
>> +}
>> +
>> +static const struct v4l2_async_notifier_operations max9286_notify_ops = {
>> + .bound = max9286_notify_bound,
>> + .unbind = max9286_notify_unbind,
>> +};
>> +
>> +static int max9286_v4l2_notifier_register(struct max9286_priv *priv)
>> +{
>> + struct device *dev = &priv->client->dev;
>> + struct max9286_source *source = NULL;
>> + int ret;
>> +
>> + if (!priv->nsources)
>> + return 0;
>> +
>> + v4l2_async_notifier_init(&priv->notifier);
>> +
>> + for_each_source(priv, source) {
>> + unsigned int i = to_index(priv, source);
>> +
>> + source->asd.match_type = V4L2_ASYNC_MATCH_FWNODE;
>> + source->asd.match.fwnode = source->fwnode;
>> +
>> + ret = v4l2_async_notifier_add_subdev(&priv->notifier,
>> + &source->asd);
>> + if (ret) {
>> + dev_err(dev, "Failed to add subdev for source %d", i);
>> + v4l2_async_notifier_cleanup(&priv->notifier);
>> + return ret;
>> + }
>> +
>> + /*
>> + * Balance the reference counting handled through
>> + * v4l2_async_notifier_cleanup()
>> + */
>> + fwnode_handle_get(source->fwnode);
>> + }
>> +
>> + priv->notifier.ops = &max9286_notify_ops;
>> +
>> + ret = v4l2_async_subdev_notifier_register(&priv->sd, &priv->notifier);
>> + if (ret) {
>> + dev_err(dev, "Failed to register subdev_notifier");
>> + v4l2_async_notifier_cleanup(&priv->notifier);
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static void max9286_v4l2_notifier_unregister(struct max9286_priv *priv)
>> +{
>> + if (!priv->nsources)
>> + return;
>> +
>> + v4l2_async_notifier_unregister(&priv->notifier);
>> + v4l2_async_notifier_cleanup(&priv->notifier);
>> +}
>> +
>> +static int max9286_s_stream(struct v4l2_subdev *sd, int enable)
>> +{
>> + struct max9286_priv *priv = sd_to_max9286(sd);
>> + struct max9286_source *source;
>> + unsigned int i;
>> + bool sync = false;
>> + int ret;
>> +
>> + if (enable) {
>> + /*
>> + * The frame sync between cameras is transmitted across the
>> + * reverse channel as GPIO. We must open all channels while
>> + * streaming to allow this synchronisation signal to be shared.
>> + */
>> + max9286_i2c_mux_open(priv);
>> +
>> + /* Start all cameras. */
>> + for_each_source(priv, source) {
>> + ret = v4l2_subdev_call(source->sd, video, s_stream, 1);
>> + if (ret)
>> + return ret;
>> + }
>> +
>> + ret = max9286_check_video_links(priv);
>> + if (ret)
>> + return ret;
>> +
>> + /*
>> + * Wait until frame synchronization is locked.
>> + *
>> + * Manual says frame sync locking should take ~6 VTS.
>> + * From practical experience at least 8 are required. Give
>> + * 12 complete frames time (~400ms at 30 fps) to achieve frame
>> + * locking before returning error.
>> + */
>> + for (i = 0; i < 40; i++) {
>> + if (max9286_read(priv, 0x31) & MAX9286_FSYNC_LOCKED) {
>> + sync = true;
>> + break;
>> + }
>> + usleep_range(9000, 11000);
>> + }
>> +
>> + if (!sync) {
>> + dev_err(&priv->client->dev,
>> + "Failed to get frame synchronization\n");
>> + return -EXDEV; /* Invalid cross-device link */
>> + }
>> +
>> + /*
>> + * Enable CSI output, VC set according to link number.
>> + * Bit 7 must be set (chip manual says it's 0 and reserved).
>> + */
>> + max9286_write(priv, 0x15, 0x80 | MAX9286_VCTYPE |
>> + MAX9286_CSIOUTEN | MAX9286_0X15_RESV);
>> + } else {
>> + max9286_write(priv, 0x15, MAX9286_VCTYPE | MAX9286_0X15_RESV);
>> +
>> + /* Stop all cameras. */
>> + for_each_source(priv, source)
>> + v4l2_subdev_call(source->sd, video, s_stream, 0);
>> +
>> + max9286_i2c_mux_close(priv);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int max9286_enum_mbus_code(struct v4l2_subdev *sd,
>> + struct v4l2_subdev_pad_config *cfg,
>> + struct v4l2_subdev_mbus_code_enum *code)
>> +{
>> + if (code->pad || code->index > 0)
>> + return -EINVAL;
>> +
>> + code->code = MEDIA_BUS_FMT_UYVY8_2X8;
>> +
>> + return 0;
>> +}
>> +
>> +static struct v4l2_mbus_framefmt *
>> +max9286_get_pad_format(struct max9286_priv *priv,
>> + struct v4l2_subdev_pad_config *cfg,
>> + unsigned int pad, u32 which)
>> +{
>> + switch (which) {
>> + case V4L2_SUBDEV_FORMAT_TRY:
>> + return v4l2_subdev_get_try_format(&priv->sd, cfg, pad);
>> + case V4L2_SUBDEV_FORMAT_ACTIVE:
>> + return &priv->fmt[pad];
>> + default:
>> + return NULL;
>> + }
>> +}
>> +
>> +static int max9286_set_fmt(struct v4l2_subdev *sd,
>> + struct v4l2_subdev_pad_config *cfg,
>> + struct v4l2_subdev_format *format)
>> +{
>> + struct max9286_priv *priv = sd_to_max9286(sd);
>> + struct v4l2_mbus_framefmt *cfg_fmt;
>> +
>> + if (format->pad >= MAX9286_SRC_PAD)
>> + return -EINVAL;
>> +
>> + /* Refuse non YUV422 formats as we hardcode DT to 8 bit YUV422 */
>> + switch (format->format.code) {
>> + case MEDIA_BUS_FMT_UYVY8_2X8:
>> + case MEDIA_BUS_FMT_VYUY8_2X8:
>> + case MEDIA_BUS_FMT_YUYV8_2X8:
>> + case MEDIA_BUS_FMT_YVYU8_2X8:
>> + break;
>> + default:
>> + format->format.code = MEDIA_BUS_FMT_YUYV8_2X8;
>
> Is there any reason for not setting default format to MEDIA_BUS_FMT_UYVY8_2X8?
>
No good reason no, and I see that in max9286_enum_mbus_code(), we
currently code to MEDIA_BUS_FMT_YUYV8_2X8, and that's the value that we
init to, so that would be a better default indeed.
I'll update this for v10.
> Thanks,
> Mani
>
>> + break;
>> + }
>> +
>> + cfg_fmt = max9286_get_pad_format(priv, cfg, format->pad, format->which);
>> + if (!cfg_fmt)
>> + return -EINVAL;
>> +
>> + mutex_lock(&priv->mutex);
>> + *cfg_fmt = format->format;
>> + mutex_unlock(&priv->mutex);
>> +
>> + return 0;
>> +}
>> +
>> +static int max9286_get_fmt(struct v4l2_subdev *sd,
>> + struct v4l2_subdev_pad_config *cfg,
>> + struct v4l2_subdev_format *format)
>> +{
>> + struct max9286_priv *priv = sd_to_max9286(sd);
>> + struct v4l2_mbus_framefmt *cfg_fmt;
>> +
>> + if (format->pad >= MAX9286_SRC_PAD)
>> + return -EINVAL;
>> +
>> + cfg_fmt = max9286_get_pad_format(priv, cfg, format->pad, format->which);
>> + if (!cfg_fmt)
>> + return -EINVAL;
>> +
>> + mutex_lock(&priv->mutex);
>> + format->format = *cfg_fmt;
>> + mutex_unlock(&priv->mutex);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct v4l2_subdev_video_ops max9286_video_ops = {
>> + .s_stream = max9286_s_stream,
>> +};
>> +
>> +static const struct v4l2_subdev_pad_ops max9286_pad_ops = {
>> + .enum_mbus_code = max9286_enum_mbus_code,
>> + .get_fmt = max9286_get_fmt,
>> + .set_fmt = max9286_set_fmt,
>> +};
>> +
>> +static const struct v4l2_subdev_ops max9286_subdev_ops = {
>> + .video = &max9286_video_ops,
>> + .pad = &max9286_pad_ops,
>> +};
>> +
>> +static void max9286_init_format(struct v4l2_mbus_framefmt *fmt)
>> +{
>> + fmt->width = 1280;
>> + fmt->height = 800;
>> + fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
>> + fmt->colorspace = V4L2_COLORSPACE_SRGB;
>> + fmt->field = V4L2_FIELD_NONE;
>> + fmt->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
>> + fmt->quantization = V4L2_QUANTIZATION_DEFAULT;
>> + fmt->xfer_func = V4L2_XFER_FUNC_DEFAULT;
>> +}
>> +
>> +static int max9286_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
>> +{
>> + struct v4l2_mbus_framefmt *format;
>> + unsigned int i;
>> +
>> + for (i = 0; i < MAX9286_N_SINKS; i++) {
>> + format = v4l2_subdev_get_try_format(subdev, fh->pad, i);
>> + max9286_init_format(format);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static const struct v4l2_subdev_internal_ops max9286_subdev_internal_ops = {
>> + .open = max9286_open,
>> +};
>> +
>> +static int max9286_s_ctrl(struct v4l2_ctrl *ctrl)
>> +{
>> + switch (ctrl->id) {
>> + case V4L2_CID_PIXEL_RATE:
>> + return 0;
>> + default:
>> + return -EINVAL;
>> + }
>> +}
>> +
>> +static const struct v4l2_ctrl_ops max9286_ctrl_ops = {
>> + .s_ctrl = max9286_s_ctrl,
>> +};
>> +
>> +static int max9286_v4l2_register(struct max9286_priv *priv)
>> +{
>> + struct device *dev = &priv->client->dev;
>> + struct fwnode_handle *ep;
>> + int ret;
>> + int i;
>> +
>> + /* Register v4l2 async notifiers for connected Camera subdevices */
>> + ret = max9286_v4l2_notifier_register(priv);
>> + if (ret) {
>> + dev_err(dev, "Unable to register V4L2 async notifiers\n");
>> + return ret;
>> + }
>> +
>> + /* Configure V4L2 for the MAX9286 itself */
>> +
>> + for (i = 0; i < MAX9286_N_SINKS; i++)
>> + max9286_init_format(&priv->fmt[i]);
>> +
>> + v4l2_i2c_subdev_init(&priv->sd, priv->client, &max9286_subdev_ops);
>> + priv->sd.internal_ops = &max9286_subdev_internal_ops;
>> + priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
>> +
>> + v4l2_ctrl_handler_init(&priv->ctrls, 1);
>> + priv->pixelrate = v4l2_ctrl_new_std(&priv->ctrls,
>> + &max9286_ctrl_ops,
>> + V4L2_CID_PIXEL_RATE,
>> + 1, INT_MAX, 1, 50000000);
>> +
>> + priv->sd.ctrl_handler = &priv->ctrls;
>> + ret = priv->ctrls.error;
>> + if (ret)
>> + goto err_async;
>> +
>> + priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
>> +
>> + priv->pads[MAX9286_SRC_PAD].flags = MEDIA_PAD_FL_SOURCE;
>> + for (i = 0; i < MAX9286_SRC_PAD; i++)
>> + priv->pads[i].flags = MEDIA_PAD_FL_SINK;
>> + ret = media_entity_pads_init(&priv->sd.entity, MAX9286_N_PADS,
>> + priv->pads);
>> + if (ret)
>> + goto err_async;
>> +
>> + ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), MAX9286_SRC_PAD,
>> + 0, 0);
>> + if (!ep) {
>> + dev_err(dev, "Unable to retrieve endpoint on \"port@4\"\n");
>> + ret = -ENOENT;
>> + goto err_async;
>> + }
>> + priv->sd.fwnode = ep;
>> +
>> + ret = v4l2_async_register_subdev(&priv->sd);
>> + if (ret < 0) {
>> + dev_err(dev, "Unable to register subdevice\n");
>> + goto err_put_node;
>> + }
>> +
>> + return 0;
>> +
>> +err_put_node:
>> + fwnode_handle_put(ep);
>> +err_async:
>> + max9286_v4l2_notifier_unregister(priv);
>> +
>> + return ret;
>> +}
>> +
>> +static void max9286_v4l2_unregister(struct max9286_priv *priv)
>> +{
>> + fwnode_handle_put(priv->sd.fwnode);
>> + v4l2_async_unregister_subdev(&priv->sd);
>> + max9286_v4l2_notifier_unregister(priv);
>> +}
>> +
>> +/* -----------------------------------------------------------------------------
>> + * Probe/Remove
>> + */
>> +
>> +static int max9286_setup(struct max9286_priv *priv)
>> +{
>> + /*
>> + * Link ordering values for all enabled links combinations. Orders must
>> + * be assigned sequentially from 0 to the number of enabled links
>> + * without leaving any hole for disabled links. We thus assign orders to
>> + * enabled links first, and use the remaining order values for disabled
>> + * links are all links must have a different order value;
>> + */
>> + static const u8 link_order[] = {
>> + (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xxxx */
>> + (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xxx0 */
>> + (3 << 6) | (2 << 4) | (0 << 2) | (1 << 0), /* xx0x */
>> + (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* xx10 */
>> + (3 << 6) | (0 << 4) | (2 << 2) | (1 << 0), /* x0xx */
>> + (3 << 6) | (1 << 4) | (2 << 2) | (0 << 0), /* x1x0 */
>> + (3 << 6) | (1 << 4) | (0 << 2) | (2 << 0), /* x10x */
>> + (3 << 6) | (1 << 4) | (1 << 2) | (0 << 0), /* x210 */
>> + (0 << 6) | (3 << 4) | (2 << 2) | (1 << 0), /* 0xxx */
>> + (1 << 6) | (3 << 4) | (2 << 2) | (0 << 0), /* 1xx0 */
>> + (1 << 6) | (3 << 4) | (0 << 2) | (2 << 0), /* 1x0x */
>> + (2 << 6) | (3 << 4) | (1 << 2) | (0 << 0), /* 2x10 */
>> + (1 << 6) | (0 << 4) | (3 << 2) | (2 << 0), /* 10xx */
>> + (2 << 6) | (1 << 4) | (3 << 2) | (0 << 0), /* 21x0 */
>> + (2 << 6) | (1 << 4) | (0 << 2) | (3 << 0), /* 210x */
>> + (3 << 6) | (2 << 4) | (1 << 2) | (0 << 0), /* 3210 */
>> + };
>> +
>> + /*
>> + * Set the I2C bus speed.
>> + *
>> + * Enable I2C Local Acknowledge during the probe sequences of the camera
>> + * only. This should be disabled after the mux is initialised.
>> + */
>> + max9286_configure_i2c(priv, true);
>> +
>> + /*
>> + * Reverse channel setup.
>> + *
>> + * - Enable custom reverse channel configuration (through register 0x3f)
>> + * and set the first pulse length to 35 clock cycles.
>> + * - Increase the reverse channel amplitude to 170mV to accommodate the
>> + * high threshold enabled by the serializer driver.
>> + */
>> + max9286_write(priv, 0x3f, MAX9286_EN_REV_CFG | MAX9286_REV_FLEN(35));
>> + max9286_write(priv, 0x3b, MAX9286_REV_TRF(1) | MAX9286_REV_AMP(70) |
>> + MAX9286_REV_AMP_X);
>> + usleep_range(2000, 2500);
>> +
>> + /*
>> + * Enable GMSL links, mask unused ones and autodetect link
>> + * used as CSI clock source.
>> + */
>> + max9286_write(priv, 0x00, MAX9286_MSTLINKSEL_AUTO | priv->route_mask);
>> + max9286_write(priv, 0x0b, link_order[priv->route_mask]);
>> + max9286_write(priv, 0x69, (0xf & ~priv->route_mask));
>> +
>> + /*
>> + * Video format setup:
>> + * Disable CSI output, VC is set according to Link number.
>> + */
>> + max9286_write(priv, 0x15, MAX9286_VCTYPE | MAX9286_0X15_RESV);
>> +
>> + /* Enable CSI-2 Lane D0-D3 only, DBL mode, YUV422 8-bit. */
>> + max9286_write(priv, 0x12, MAX9286_CSIDBL | MAX9286_DBL |
>> + MAX9286_CSILANECNT(priv->csi2_data_lanes) |
>> + MAX9286_DATATYPE_YUV422_8BIT);
>> +
>> + /* Automatic: FRAMESYNC taken from the slowest Link. */
>> + max9286_write(priv, 0x01, MAX9286_FSYNCMODE_INT_HIZ |
>> + MAX9286_FSYNCMETH_AUTO);
>> +
>> + /* Enable HS/VS encoding, use D14/15 for HS/VS, invert VS. */
>> + max9286_write(priv, 0x0c, MAX9286_HVEN | MAX9286_INVVS |
>> + MAX9286_HVSRC_D14);
>> +
>> + /*
>> + * The overlap window seems to provide additional validation by tracking
>> + * the delay between vsync and frame sync, generating an error if the
>> + * delay is bigger than the programmed window, though it's not yet clear
>> + * what value should be set.
>> + *
>> + * As it's an optional value and can be disabled, we do so by setting
>> + * a 0 overlap value.
>> + */
>> + max9286_write(priv, 0x63, 0);
>> + max9286_write(priv, 0x64, 0);
>> +
>> + /*
>> + * Wait for 2ms to allow the link to resynchronize after the
>> + * configuration change.
>> + */
>> + usleep_range(2000, 5000);
>> +
>> + return 0;
>> +}
>> +
>> +static void max9286_gpio_set(struct gpio_chip *chip,
>> + unsigned int offset, int value)
>> +{
>> + struct max9286_priv *priv = gpiochip_get_data(chip);
>> +
>> + if (value)
>> + priv->gpio_state |= BIT(offset);
>> + else
>> + priv->gpio_state &= ~BIT(offset);
>> +
>> + max9286_write(priv, 0x0f, MAX9286_0X0F_RESERVED | priv->gpio_state);
>> +}
>> +
>> +static int max9286_gpio_get(struct gpio_chip *chip, unsigned int offset)
>> +{
>> + struct max9286_priv *priv = gpiochip_get_data(chip);
>> +
>> + return priv->gpio_state & BIT(offset);
>> +}
>> +
>> +static int max9286_register_gpio(struct max9286_priv *priv)
>> +{
>> + struct device *dev = &priv->client->dev;
>> + struct gpio_chip *gpio = &priv->gpio;
>> + int ret;
>> +
>> + static const char * const names[] = {
>> + "GPIO0OUT",
>> + "GPIO1OUT",
>> + };
>> +
>> + /* Configure the GPIO */
>> + gpio->label = dev_name(dev);
>> + gpio->parent = dev;
>> + gpio->owner = THIS_MODULE;
>> + gpio->of_node = dev->of_node;
>> + gpio->ngpio = 2;
>> + gpio->base = -1;
>> + gpio->set = max9286_gpio_set;
>> + gpio->get = max9286_gpio_get;
>> + gpio->can_sleep = true;
>> + gpio->names = names;
>> +
>> + /* GPIO values default to high */
>> + priv->gpio_state = BIT(0) | BIT(1);
>> +
>> + ret = devm_gpiochip_add_data(dev, gpio, priv);
>> + if (ret)
>> + dev_err(dev, "Unable to create gpio_chip\n");
>> +
>> + return ret;
>> +}
>> +
>> +static int max9286_init(struct device *dev)
>> +{
>> + struct max9286_priv *priv;
>> + struct i2c_client *client;
>> + int ret;
>> +
>> + client = to_i2c_client(dev);
>> + priv = i2c_get_clientdata(client);
>> +
>> + /* Enable the bus power. */
>> + ret = regulator_enable(priv->regulator);
>> + if (ret < 0) {
>> + dev_err(&client->dev, "Unable to turn PoC on\n");
>> + return ret;
>> + }
>> +
>> + ret = max9286_setup(priv);
>> + if (ret) {
>> + dev_err(dev, "Unable to setup max9286\n");
>> + goto err_regulator;
>> + }
>> +
>> + /*
>> + * Register all V4L2 interactions for the MAX9286 and notifiers for
>> + * any subdevices connected.
>> + */
>> + ret = max9286_v4l2_register(priv);
>> + if (ret) {
>> + dev_err(dev, "Failed to register with V4L2\n");
>> + goto err_regulator;
>> + }
>> +
>> + ret = max9286_i2c_mux_init(priv);
>> + if (ret) {
>> + dev_err(dev, "Unable to initialize I2C multiplexer\n");
>> + goto err_v4l2_register;
>> + }
>> +
>> + /* Leave the mux channels disabled until they are selected. */
>> + max9286_i2c_mux_close(priv);
>> +
>> + return 0;
>> +
>> +err_v4l2_register:
>> + max9286_v4l2_unregister(priv);
>> +err_regulator:
>> + regulator_disable(priv->regulator);
>> +
>> + return ret;
>> +}
>> +
>> +static void max9286_cleanup_dt(struct max9286_priv *priv)
>> +{
>> + struct max9286_source *source;
>> +
>> + for_each_source(priv, source) {
>> + fwnode_handle_put(source->fwnode);
>> + source->fwnode = NULL;
>> + }
>> +}
>> +
>> +static int max9286_parse_dt(struct max9286_priv *priv)
>> +{
>> + struct device *dev = &priv->client->dev;
>> + struct device_node *i2c_mux;
>> + struct device_node *node = NULL;
>> + unsigned int i2c_mux_mask = 0;
>> +
>> + of_node_get(dev->of_node);
>> + i2c_mux = of_find_node_by_name(dev->of_node, "i2c-mux");
>> + if (!i2c_mux) {
>> + dev_err(dev, "Failed to find i2c-mux node\n");
>> + of_node_put(dev->of_node);
>> + return -EINVAL;
>> + }
>> +
>> + /* Identify which i2c-mux channels are enabled */
>> + for_each_child_of_node(i2c_mux, node) {
>> + u32 id = 0;
>> +
>> + of_property_read_u32(node, "reg", &id);
>> + if (id >= MAX9286_NUM_GMSL)
>> + continue;
>> +
>> + if (!of_device_is_available(node)) {
>> + dev_dbg(dev, "Skipping disabled I2C bus port %u\n", id);
>> + continue;
>> + }
>> +
>> + i2c_mux_mask |= BIT(id);
>> + }
>> + of_node_put(node);
>> + of_node_put(i2c_mux);
>> +
>> + /* Parse the endpoints */
>> + for_each_endpoint_of_node(dev->of_node, node) {
>> + struct max9286_source *source;
>> + struct of_endpoint ep;
>> +
>> + of_graph_parse_endpoint(node, &ep);
>> + dev_dbg(dev, "Endpoint %pOF on port %d",
>> + ep.local_node, ep.port);
>> +
>> + if (ep.port > MAX9286_NUM_GMSL) {
>> + dev_err(dev, "Invalid endpoint %s on port %d",
>> + of_node_full_name(ep.local_node), ep.port);
>> + continue;
>> + }
>> +
>> + /* For the source endpoint just parse the bus configuration. */
>> + if (ep.port == MAX9286_SRC_PAD) {
>> + struct v4l2_fwnode_endpoint vep = {
>> + .bus_type = V4L2_MBUS_CSI2_DPHY
>> + };
>> + int ret;
>> +
>> + ret = v4l2_fwnode_endpoint_parse(
>> + of_fwnode_handle(node), &vep);
>> + if (ret) {
>> + of_node_put(node);
>> + of_node_put(dev->of_node);
>> + return ret;
>> + }
>> +
>> + if (vep.bus_type != V4L2_MBUS_CSI2_DPHY) {
>> + dev_err(dev,
>> + "Media bus %u type not supported\n",
>> + vep.bus_type);
>> + v4l2_fwnode_endpoint_free(&vep);
>> + of_node_put(node);
>> + of_node_put(dev->of_node);
>> + return -EINVAL;
>> + }
>> +
>> + priv->csi2_data_lanes =
>> + vep.bus.mipi_csi2.num_data_lanes;
>> + v4l2_fwnode_endpoint_free(&vep);
>> +
>> + continue;
>> + }
>> +
>> + /* Skip if the corresponding GMSL link is unavailable. */
>> + if (!(i2c_mux_mask & BIT(ep.port)))
>> + continue;
>> +
>> + if (priv->sources[ep.port].fwnode) {
>> + dev_err(dev,
>> + "Multiple port endpoints are not supported: %d",
>> + ep.port);
>> +
>> + continue;
>> + }
>> +
>> + source = &priv->sources[ep.port];
>> + source->fwnode = fwnode_graph_get_remote_endpoint(
>> + of_fwnode_handle(node));
>> + if (!source->fwnode) {
>> + dev_err(dev,
>> + "Endpoint %pOF has no remote endpoint connection\n",
>> + ep.local_node);
>> +
>> + continue;
>> + }
>> +
>> + priv->source_mask |= BIT(ep.port);
>> + priv->nsources++;
>> + }
>> + of_node_put(node);
>> + of_node_put(dev->of_node);
>> +
>> + priv->route_mask = priv->source_mask;
>> +
>> + return 0;
>> +}
>> +
>> +static int max9286_probe(struct i2c_client *client)
>> +{
>> + struct max9286_priv *priv;
>> + int ret;
>> +
>> + priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
>> + if (!priv)
>> + return -ENOMEM;
>> +
>> + mutex_init(&priv->mutex);
>> +
>> + priv->client = client;
>> + i2c_set_clientdata(client, priv);
>> +
>> + priv->gpiod_pwdn = devm_gpiod_get_optional(&client->dev, "enable",
>> + GPIOD_OUT_HIGH);
>> + if (IS_ERR(priv->gpiod_pwdn))
>> + return PTR_ERR(priv->gpiod_pwdn);
>> +
>> + gpiod_set_consumer_name(priv->gpiod_pwdn, "max9286-pwdn");
>> + gpiod_set_value_cansleep(priv->gpiod_pwdn, 1);
>> +
>> + /* Wait at least 4ms before the I2C lines latch to the address */
>> + if (priv->gpiod_pwdn)
>> + usleep_range(4000, 5000);
>> +
>> + /*
>> + * The MAX9286 starts by default with all ports enabled, we disable all
>> + * ports early to ensure that all channels are disabled if we error out
>> + * and keep the bus consistent.
>> + */
>> + max9286_i2c_mux_close(priv);
>> +
>> + /*
>> + * The MAX9286 initialises with auto-acknowledge enabled by default.
>> + * This can be invasive to other transactions on the same bus, so
>> + * disable it early. It will be enabled only as and when needed.
>> + */
>> + max9286_configure_i2c(priv, false);
>> +
>> + ret = max9286_register_gpio(priv);
>> + if (ret)
>> + goto err_powerdown;
>> +
>> + priv->regulator = devm_regulator_get(&client->dev, "poc");
>> + if (IS_ERR(priv->regulator)) {
>> + if (PTR_ERR(priv->regulator) != -EPROBE_DEFER)
>> + dev_err(&client->dev,
>> + "Unable to get PoC regulator (%ld)\n",
>> + PTR_ERR(priv->regulator));
>> + ret = PTR_ERR(priv->regulator);
>> + goto err_powerdown;
>> + }
>> +
>> + ret = max9286_parse_dt(priv);
>> + if (ret)
>> + goto err_powerdown;
>> +
>> + ret = max9286_init(&client->dev);
>> + if (ret < 0)
>> + goto err_cleanup_dt;
>> +
>> + return 0;
>> +
>> +err_cleanup_dt:
>> + max9286_cleanup_dt(priv);
>> +err_powerdown:
>> + gpiod_set_value_cansleep(priv->gpiod_pwdn, 0);
>> +
>> + return ret;
>> +}
>> +
>> +static int max9286_remove(struct i2c_client *client)
>> +{
>> + struct max9286_priv *priv = i2c_get_clientdata(client);
>> +
>> + i2c_mux_del_adapters(priv->mux);
>> +
>> + max9286_v4l2_unregister(priv);
>> +
>> + regulator_disable(priv->regulator);
>> +
>> + gpiod_set_value_cansleep(priv->gpiod_pwdn, 0);
>> +
>> + max9286_cleanup_dt(priv);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id max9286_dt_ids[] = {
>> + { .compatible = "maxim,max9286" },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, max9286_dt_ids);
>> +
>> +static struct i2c_driver max9286_i2c_driver = {
>> + .driver = {
>> + .name = "max9286",
>> + .of_match_table = of_match_ptr(max9286_dt_ids),
>> + },
>> + .probe_new = max9286_probe,
>> + .remove = max9286_remove,
>> +};
>> +
>> +module_i2c_driver(max9286_i2c_driver);
>> +
>> +MODULE_DESCRIPTION("Maxim MAX9286 GMSL Deserializer Driver");
>> +MODULE_AUTHOR("Jacopo Mondi, Kieran Bingham, Laurent Pinchart, Niklas Söderlund, Vladimir Barinov");
>> +MODULE_LICENSE("GPL");
>> --
>> 2.25.1
>>
^ permalink raw reply
* Re: [PATCH V3 0/8] Tegra XUSB charger detect support
From: Nagarjuna Kristam @ 2020-05-14 9:46 UTC (permalink / raw)
To: Felipe Balbi, gregkh, thierry.reding, jonathanh, mark.rutland,
robh+dt, kishon
Cc: devicetree, linux-tegra, linux-usb, linux-kernel
In-Reply-To: <87wo5e4zzi.fsf@kernel.org>
On 14-05-2020 15:09, Felipe Balbi wrote:
> Nagarjuna Kristam<nkristam@nvidia.com> writes:
>
>> This patch series adds charger detect support on XUSB hardware used in
>> Tegra210 and Tegra186 SoCs.
>>
>> This patchset is composed with :
>> - dt bindings of XUSB Pad Controller
>> - Tegra XUSB device mode driver to add vbus_draw support
>> - Tegra PHY driver for charger detect support
>>
>> Tests done:
>> - Connect USB cable from ubuntu host to micro-B port of DUT to detect
>> SDP_TYPE charger
>> - Connect USB cable from external powered USB hub(which inturn connects
>> to ubuntu host) to micro-B port of DUT to detect CDP_TYPE charger.
>> - Connect USB cable from USB charger to micro-B port of DUT to detect
>> DCP_TYPE charger.
>> DUT: Jetson-tx1, Jetson tx2.
>>
>> V3:
>> - Added ACKed-by details for PHY driver and DT changes.
>> - Functions and its arguments are aligned.
>> - Tabs are used for alignment of MACRO's
>> - For vbus_draw USDC callback, usb_phy set_power error is propogated.
>> - Fixed various comments given by thierry.
>> V2:
>> - Added ACKed-by details for DT patches.
>> - All patches rebased.
>>
>> Nagarjuna Kristam (8):
>> dt-bindings: phy: tegra-xusb: Add charger-detect property
>> usb: gadget: tegra-xudc: Add vbus_draw support
>> phy: tegra: xusb: Add support for UTMI pad power control
>> phy: tegra: xusb: Add USB2 pad power control support for Tegra210
>> phy: tegra: xusb: Add soc ops API to enable UTMI PAD protection
>> phy: tegra: xusb: Add support for charger detect
>> phy: tegra: xusb: Enable charger detect for Tegra186
>> phy: tegra: xusb: Enable charger detect for Tegra210
> Is there a hard-dependency between gadget and phy patches?
>
> -- balbiNo dependency. They can be merged independently.
- Nagarjuna
^ permalink raw reply
* Re: [PATCH] fixup! dt-bindings: media: i2c: Add bindings for Maxima Integrated MAX9286
From: Kieran Bingham @ 2020-05-14 9:43 UTC (permalink / raw)
To: Jacopo Mondi, devicetree, linux-media, Rob Herring,
linux-renesas-soc, laurent.pinchart+renesas, niklas.soderlund
Cc: Hans Verkuil, sakari.ailus, mchehab, Manivannan Sadhasivam,
Hyun Kwon
In-Reply-To: <20200513125445.54132-1-jacopo+renesas@jmondi.org>
Hi Jacopo,
On 13/05/2020 13:54, Jacopo Mondi wrote:
> Subject: [PATCH] fixup! dt-bindings: media: i2c: Add bindings for Maxima Integrated MAX9286
>
> Temporary fixup to ease review. To be squashed into v10 if accepted.
>
> Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
> ---
>
> While fixing Rob's reported bug on v9 I realized thanks to a
> dt_binding_check warning that the i2c-mux child nodes where under-specified.
>
> This fixup epxands the i2c-mux child nodes description and updates the
> example to match our currently-out-of-tree DTS files for GMSL platforms.
>
> dt_binding_check still reports a warning:
>
> Documentation/devicetree/bindings/media/i2c/maxim,max9286.example.dt.yaml: camera@51: reg: [[81, 97]] is too short
> Documentation/devicetree/bindings/media/i2c/maxim,max9286.example.dt.yaml: camera@52: reg: [[82, 98]] is too short
> Documentation/devicetree/bindings/media/i2c/maxim,max9286.example.dt.yaml: camera@53: reg: [[83, 99]] is too short
> Documentation/devicetree/bindings/media/i2c/maxim,max9286.example.dt.yaml: camera@54: reg: [[84, 100]] is too short
Is too short? That seems odd. We accept 1, 2, or 3 values in the reg
(for the serializer, camera, mcu addresses) but those values are
specific to the camera device, and are managed by that driver and
shouldn't be validated here.
>
> Which I was not able to silence.
> ---
> .../bindings/media/i2c/maxim,max9286.yaml | 86 +++++++++++++++++--
> 1 file changed, 77 insertions(+), 9 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/media/i2c/maxim,max9286.yaml b/Documentation/devicetree/bindings/media/i2c/maxim,max9286.yaml
> index f9d3e5712c59..d9bd19caed2f 100644
> --- a/Documentation/devicetree/bindings/media/i2c/maxim,max9286.yaml
> +++ b/Documentation/devicetree/bindings/media/i2c/maxim,max9286.yaml
> @@ -130,9 +130,7 @@ properties:
> description: |
> Each GMSL link is modelled as a child bus of an i2c bus
> multiplexer/switch, in accordance with bindings described in
> - Documentation/devicetree/bindings/i2c/i2c-mux.txt. The serializer
> - device on the remote end of the GMSL link shall be modelled as a child
> - node of the corresponding I2C bus.
> + Documentation/devicetree/bindings/i2c/i2c-mux.txt.
>
> properties:
> '#address-cells':
> @@ -141,7 +139,74 @@ properties:
> '#size-cells':
> const: 0
>
> - additionalProperties: false
> + patternProperties:
> + "^i2c@[0-3]$":
> + type: object
> + description: |
> + Child node of the i2c bus multiplexer which represents a GMSL link.
> + Each serializer device on the GMSL link remote end is represented with
> + an i2c-mux child node. The MAX9286 chip supports up to 4 GMSL
> + channels.
> +
> + properties:
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 0
> +
> + reg:
> + description: The index of the GMSL channel.
> + maxItems: 1
> +
> + patternProperties:
> + "^camera@[0-9]+":
This value after @ represents a non 0x prefixed hex value, where your
regex will only match numerical values.
"^camera@[a-f0-9]+":
is likely therefore required.
I see other uses of this patternProperties also terminate the regex with
a $ (end of line) but that confuses me, as the node is often presented
with the opening brace after the name and identifier:
(i.e.)
camera@52 {
But perhaps the validator extracts the node name and reg and matches on
that directly in which case it would be
"^camera@[a-f0-9]+$":
> + type: object
> + description: |
> + The remote camera device, composed by a GMSL serializer and a
> + connected video source.
> +
> + properties:
> + compatible:
> + description: The remote device compatible string.
> +
> + reg:
> + description: |
> + The I2C addresses to be assigned to the remote devices through
> + address reprogramming. The number of entries depends on the
> + requirements of the currently connected remote device.
> +
> + port:
> + type: object
> +
> + properties:
> + endpoint:
> + type: object
> +
> + properties:
> + remote-endpoint:
> + description: phandle to the MAX9286 sink endpoint.
> +
> + required:
> + - remote-endpoint
> +
> + additionalProperties: false
> +
> + required:
> + - endpoint
> +
> + additionalProperties: false
> +
> + required:
> + - compatible
> + - reg
> + - port
> +
> + additionalProperties: false
> +
> + additionalProperties: false
> +
> + additionalProperties: false
>
Wow, is it required to specify additionalProperties: false quite so many
times?
> required:
> - compatible
> @@ -220,11 +285,11 @@ examples:
> i2c@0 {
> #address-cells = <1>;
> #size-cells = <0>;
> -
> reg = <0>;
>
> camera@51 {
> - reg = <0x51>;
> + compatible = "imi,rdacm20";
> + reg = <0x51 0x61>;
>
> port {
> rdacm20_out0: endpoint {
> @@ -241,7 +306,8 @@ examples:
> reg = <1>;
>
> camera@52 {
> - reg = <0x52>;
> + compatible = "imi,rdacm20";
> + reg = <0x52 0x62>;
>
> port {
> rdacm20_out1: endpoint {
> @@ -257,7 +323,8 @@ examples:
> reg = <2>;
>
> camera@53 {
> - reg = <0x53>;
> + compatible = "imi,rdacm20";
> + reg = <0x53 0x63>;
>
> port {
> rdacm20_out2: endpoint {
> @@ -273,7 +340,8 @@ examples:
> reg = <3>;
>
> camera@54 {
> - reg = <0x54>;
> + compatible = "imi,rdacm20";
> + reg = <0x54 0x64>;
>
> port {
> rdacm20_out3: endpoint {
> --
> 2.26.2
>
^ permalink raw reply
* Re: [PATCH V3 0/8] Tegra XUSB charger detect support
From: Felipe Balbi @ 2020-05-14 9:39 UTC (permalink / raw)
To: Nagarjuna Kristam, gregkh, thierry.reding, jonathanh,
mark.rutland, robh+dt, kishon
Cc: devicetree, linux-tegra, linux-usb, linux-kernel,
Nagarjuna Kristam
In-Reply-To: <1589437363-16727-1-git-send-email-nkristam@nvidia.com>
[-- Attachment #1: Type: text/plain, Size: 1696 bytes --]
Nagarjuna Kristam <nkristam@nvidia.com> writes:
> This patch series adds charger detect support on XUSB hardware used in
> Tegra210 and Tegra186 SoCs.
>
> This patchset is composed with :
> - dt bindings of XUSB Pad Controller
> - Tegra XUSB device mode driver to add vbus_draw support
> - Tegra PHY driver for charger detect support
>
> Tests done:
> - Connect USB cable from ubuntu host to micro-B port of DUT to detect
> SDP_TYPE charger
> - Connect USB cable from external powered USB hub(which inturn connects
> to ubuntu host) to micro-B port of DUT to detect CDP_TYPE charger.
> - Connect USB cable from USB charger to micro-B port of DUT to detect
> DCP_TYPE charger.
> DUT: Jetson-tx1, Jetson tx2.
>
> V3:
> - Added ACKed-by details for PHY driver and DT changes.
> - Functions and its arguments are aligned.
> - Tabs are used for alignment of MACRO's
> - For vbus_draw USDC callback, usb_phy set_power error is propogated.
> - Fixed various comments given by thierry.
> V2:
> - Added ACKed-by details for DT patches.
> - All patches rebased.
>
> Nagarjuna Kristam (8):
> dt-bindings: phy: tegra-xusb: Add charger-detect property
> usb: gadget: tegra-xudc: Add vbus_draw support
> phy: tegra: xusb: Add support for UTMI pad power control
> phy: tegra: xusb: Add USB2 pad power control support for Tegra210
> phy: tegra: xusb: Add soc ops API to enable UTMI PAD protection
> phy: tegra: xusb: Add support for charger detect
> phy: tegra: xusb: Enable charger detect for Tegra186
> phy: tegra: xusb: Enable charger detect for Tegra210
Is there a hard-dependency between gadget and phy patches?
--
balbi
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 832 bytes --]
^ permalink raw reply
* Re: [PATCH v2 6/6] dt-bindings: drm: bridge: adi,adv7511.txt: convert to yaml
From: Ricardo Cañuelo @ 2020-05-14 9:36 UTC (permalink / raw)
To: Laurent Pinchart
Cc: kernel, devicetree, linux-arm-kernel, geert+renesas, robh+dt,
xuwei5
In-Reply-To: <20200514015412.GF7425@pendragon.ideasonboard.com>
Hi Laurent, thanks for the thorough review. Some comments below:
On jue 14-05-2020 04:54:12, Laurent Pinchart wrote:
> > +description: |
> > + The ADV7511, ADV7511W and ADV7513 are HDMI audio and video
> > + transmitters compatible with HDMI 1.4 and DVI 1.0. They support color
> > + space conversion, S/PDIF, CEC and HDCP. They support RGB input
> > + interface.
>
> I would write the last sentence as "The transmitter input is parallel
> RGB or YUV data." as YUV is also supported.
Ok.
> > + adi,input-colorspace:
> > + description: Input color space.
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/string
> > + - enum: [ rgb, yuv422, yuv444 ]
>
> Isn't string implied ? Can't you write
>
> adi,input-colorspace:
> description: Input color space.
> enum: [ rgb, yuv422, yuv444 ]
example-schema.yaml says that
Vendor specific properties have slightly different schema
requirements than common properties. They must have at least a type
definition and 'description'.
However, dt_binding_check doesn't seem to enforce this rule for string
properties, and I saw a couple of vendor-specific string properties in
other bindings that don't define the type either, so I'm going to follow
your suggestion but only for string properties, the rest need a type
definition.
I noticed I can remove the "allOf" keywords from these too.
> > + adi,embedded-sync:
> > + description:
> > + The input uses synchronization signals embedded in the data
> > + stream (similar to BT.656). Defaults to 0 (separate H/V
> > + synchronization signals).
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - enum: [ 0, 1 ]
> > + - default: 0
>
> This be a boolean property (it is read as a bool by the driver, the
> property being absent means false, the property being present means
> true).
You're completely right.
> > + ports:
> > + description:
> > + The ADV7511(W)/13 has two video ports and one audio port. This node
> > + models their connections as documented in
> > + Documentation/devicetree/bindings/media/video-interfaces.txt
> > + Documentation/devicetree/bindings/graph.txt
> > + type: object
> > + properties:
> > + port@0:
> > + description: Video port for the RGB, YUV or DSI input.
>
> s/RGB, YUV or DSI/RGB or YUV/
Ok.
> > +if:
> > + not:
> > + properties:
> > + adi,input-colorspace:
> > + contains:
> > + enum: [ rgb, yuv444 ]
> > + adi,input-clock:
> > + contains:
> > + const: 1x
>
> As both properties take a single value, I think you can omit
> "contains:".
I think it's required here, removing it makes the test fail.
> > +required:
> > + - compatible
> > + - reg
> > + - ports
> > + - adi,input-depth
> > + - adi,input-colorspace
> > + - adi,input-clock
>
> Shouldn't the power supplies be required ?
Good question. The original binding is not completely clear on
this. There's a "Required properties" section at the top that doesn't
include the supplies, the supplies block for the ADV7511/11w/13 looks
like a gray area in that regard, while the same block for ADV7533/35 is
more explicit in that they are required, and they are not listed in the
"Optional properties" section.
However, most of the DTs that use this binding don't define any
supplies. And AFAICT from looking at the code, regulator_get() will use
a dummy regulator and show a warning for every expected regulator that's
not defined in the DT.
If we want to be more strict and require the definition of all the
supplies, there will be many more DTs changes in the series, and I'm not
sure I'll be able to do that in a reasonable amount of time. I'm looking
at them and it's not always clear which regulators to use or if they are
even defined.
> > +description: |
> > + The ADV7533 and ADV7535 are HDMI audio and video transmitters
> > + compatible with HDMI 1.4 and DVI 1.0. They support color space
> > + conversion, S/PDIF, CEC and HDCP. They support DSI for input pixels.
>
> I would write the last sentence as "The transmitter input is MIPI DSI.".
>
> ...
>
> > + Disables the interal timing generator. The chip will rely on the
>
> s/interal/internal/
>
> > + sync signals in the DSI data lanes, rather than generate its own
>
> s/generate/generating/
>
> ...
>
> > + properties:
> > + port@0:
> > + description:
> > + Video port for the RGB, YUV or DSI input. The remote endpoint
>
> s/RGB, YUV or //
Ok.
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + reg = <0>;
> > + adv7511w_in: endpoint {
> > + remote-endpoint = <&dpi_out>;
> > + };
> > + };
> > +
> > + port@1 {
> > + reg = <1>;
> > + adv7511_out: endpoint {
> > + remote-endpoint = <&hdmi_connector_in>;
> > + };
> > + };
>
> The name of the two endpoints doesn't match the adv7533. The remote
> endpoint phandle for port 0 should have dsi in its name.
Oops, thanks for catching these.
Cheers,
Ricardo
^ permalink raw reply
* RE: [PATCH v4 0/4] dt-bindings: phy: add r8a77961 support
From: Yoshihiro Shimoda @ 2020-05-14 9:26 UTC (permalink / raw)
To: kishon@ti.com, robh+dt@kernel.org
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
In-Reply-To: <1585301636-24399-1-git-send-email-yoshihiro.shimoda.uh@renesas.com>
Hi Kishon,
> From: Yoshihiro Shimoda, Sent: Friday, March 27, 2020 6:34 PM
>
> This patch adds USBPHY 2.0/3.0 devices support for r8a77961
> (R-Car M3-W+).
Would you apply this patch series to your repository?
Or, should I resend?
JFYI:
https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=262633
Best regards,
Yoshihiro Shimoda
> Changes from v3:
> - Retain a description of #phy-cell in patch 1/4.
> - Add Reviewed-by in patch 1/4 and 3/4.
> https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=262507
>
> Changes from v2:
> - Modify json-schema files which Geert-san was pointed out.
> https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=261847
>
> Changes from v1:
> - Rebase these patches on top of my patches of convert bindings to
> json-schema.
> - Add Reviewed-by.
> https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=261195
>
> Yoshihiro Shimoda (4):
> dt-bindings: phy: renesas: usb2-phy: convert bindings to json-schema
> dt-bindings: phy: renesas: usb2-phy: add r8a77961 support
> dt-bindings: phy: renesas: usb3-phy: convert bindings to json-schema
> dt-bindings: phy: renesas: usb3-phy: add r8a77961 support
>
> .../devicetree/bindings/phy/rcar-gen3-phy-usb2.txt | 70 ------------
> .../devicetree/bindings/phy/rcar-gen3-phy-usb3.txt | 52 ---------
> .../devicetree/bindings/phy/renesas,usb2-phy.yaml | 117 +++++++++++++++++++++
> .../devicetree/bindings/phy/renesas,usb3-phy.yaml | 79 ++++++++++++++
> 4 files changed, 196 insertions(+), 122 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb2.txt
> delete mode 100644 Documentation/devicetree/bindings/phy/rcar-gen3-phy-usb3.txt
> create mode 100644 Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
> create mode 100644 Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml
>
> --
> 2.7.4
^ permalink raw reply
* [PATCH 4/7] dt-bindings: pinctrl: realtek: Add Realtek DHC SoC rtd1195 and rtd1295.
From: TY Chang @ 2020-05-14 9:21 UTC (permalink / raw)
To: linux-realtek-soc, afaerber
Cc: linus.walleij, linux-gpio, robh+dt, devicetree, linux-kernel
In-Reply-To: <20200514092125.6875-1-tychang@realtek.com>
Add compatible string for RTD1195 and RTD1295.
Signed-off-by: TY Chang <tychang@realtek.com>
---
.../bindings/pinctrl/realtek,rtd-pinctrl.yaml | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/realtek,rtd-pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/realtek,rtd-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/realtek,rtd-pinctrl.yaml
new file mode 100644
index 000000000000..5af5fc8fe633
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/realtek,rtd-pinctrl.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/realtek,rtd-pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Realtek DHC pin control
+
+maintainers:
+ - Andreas Farber <afaerber@suse.de>
+
+properties:
+ compatible:
+ enum:
+ - realtek,rtd1195-iso-pinctrl
+ - realtek,rtd1195-crt-pinctrl
+ - realtek,rtd1295-iso-pinctrl
+ - realtek,rtd1295-sb2-pinctrl
+ - realtek,rtd1295-disp-pinctrl
+ - realtek,rtd1295-cr-pinctrl
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ iso_pinctrl: pinctrl@300 {
+ compatible = "realtek,rtd1195-iso-pinctrl";
+ reg = <0x300 0x14>;
+ }
+ - |
+ crt_pinctrl: pinctrl@300 {
+ compatible = "realtek,rtd1195-crt-pinctrl";
+ reg = <0x300 0x78>;
+ }
+ - |
+ iso_pinctrl: pinctrl@300 {
+ compatible = "realtek,rtd1295-iso-pinctrl";
+ reg = <0x300 0x24>;
+ }
+ - |
+ sb2_pinctrl: pinctrl@900 {
+ compatible = "realtek,rtd1295-sb2-pinctrl";
+ reg = <0x900 0x100>;
+ }
+ - |
+ disp_pinctrl: pinctrl@4d000 {
+ compatible = "realtek,rtd1295-disp-pinctrl";
+ reg = <0x4d000 0x100>;
+ };
+ - |
+ cr_pinctrl: pinctrl@12600 {
+ compatible = "realtek,rtd1295-cr-pinctrl";
+ reg = <0x12600 0x100>;
+ };
+
--
2.26.2
^ permalink raw reply related
* [PATCH 0/7] pinctrl: update realtek DHC pinctrl driver
From: TY Chang @ 2020-05-14 9:21 UTC (permalink / raw)
To: linux-realtek-soc, afaerber
Cc: linus.walleij, linux-gpio, robh+dt, devicetree, linux-kernel
Hi Andreas,
This series update Realtek DHC pinctrl driver with the following details:
* add missed pins
* add pin configuration feature
* add realtek DHC pinctrl documentation
* fix the warnings checked by running scripts/checkpatch.pl
* move realtek DHC pinctrl driver to realtek directory
* add suspend/resume callback function
Cc: Andreas Färber <afaerber@suse.de>
TY Chang (7):
pinctrl: realtek: rtd1295: Add missed pins.
pinctrl: realtek: rtd1295: Add pin configs.
pinctrl: realtek: rtd1195: Add missed pins and pin configs.
dt-bindings: pinctrl: realtek: Add Realtek DHC SoC rtd1195 and
rtd1295.
pinctrl: realtek: DHC: Fix pinctrl driver coding style according to
checkpatch.pl.
pinctrl: realtek: DHC: Move pinctrl drivers to realtek directory and
rename.
pinctrl: realtek: DHC: Add suspend/resume callback function.
.../bindings/pinctrl/realtek,rtd-pinctrl.yaml | 59 ++
drivers/pinctrl/Kconfig | 10 +-
drivers/pinctrl/Makefile | 2 +-
drivers/pinctrl/pinctrl-rtd119x.c | 383 ---------
drivers/pinctrl/realtek/Kconfig | 14 +
drivers/pinctrl/realtek/Makefile | 3 +
drivers/pinctrl/realtek/pinctrl-rtd.c | 600 +++++++++++++
.../pinctrl/{ => realtek}/pinctrl-rtd1195.h | 490 ++++++++---
.../pinctrl/{ => realtek}/pinctrl-rtd1295.h | 805 +++++++++++++++---
9 files changed, 1733 insertions(+), 633 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pinctrl/realtek,rtd-pinctrl.yaml
delete mode 100644 drivers/pinctrl/pinctrl-rtd119x.c
create mode 100644 drivers/pinctrl/realtek/Kconfig
create mode 100644 drivers/pinctrl/realtek/Makefile
create mode 100644 drivers/pinctrl/realtek/pinctrl-rtd.c
rename drivers/pinctrl/{ => realtek}/pinctrl-rtd1195.h (64%)
rename drivers/pinctrl/{ => realtek}/pinctrl-rtd1295.h (62%)
--
2.26.2
^ permalink raw reply
* [PATCH 2/7] pinctrl: realtek: rtd1295: Add pin configs.
From: TY Chang @ 2020-05-14 9:21 UTC (permalink / raw)
To: linux-realtek-soc, afaerber
Cc: linus.walleij, linux-gpio, robh+dt, devicetree, linux-kernel
In-Reply-To: <20200514092125.6875-1-tychang@realtek.com>
Add pin configs for Realtek DHC SoC RTD1295 pinctrl driver.
Signed-off-by: TY Chang <tychang@realtek.com>
---
drivers/pinctrl/pinctrl-rtd119x.c | 160 +++++++++++++++++++++++++++++-
drivers/pinctrl/pinctrl-rtd1295.h | 159 +++++++++++++++++++++++++++++
2 files changed, 317 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rtd119x.c b/drivers/pinctrl/pinctrl-rtd119x.c
index 60bf8c283a7a..52b16d610e13 100644
--- a/drivers/pinctrl/pinctrl-rtd119x.c
+++ b/drivers/pinctrl/pinctrl-rtd119x.c
@@ -36,6 +36,17 @@ struct rtd119x_pin_mux_desc {
u32 mux_value;
};
+struct rtd119x_pin_config_desc {
+ const char *name;
+ unsigned int reg_offset;
+ unsigned int base_bit;
+ unsigned int pud_en_offset;
+ unsigned int pud_sel_offset;
+ unsigned int curr_offset;
+ unsigned int smt_offset;
+ unsigned int curr_type;
+};
+
struct rtd119x_pin_desc {
const char *name;
unsigned int mux_offset;
@@ -43,6 +54,20 @@ struct rtd119x_pin_desc {
const struct rtd119x_pin_mux_desc *functions;
};
+#define RTK_PIN_CONFIG(_name, _reg_off, _base_bit, _pud_en_off, \
+ _pud_sel_off, _curr_off, _smt_off, _curr_type) \
+ { \
+ .name = # _name, \
+ .reg_offset = _reg_off, \
+ .base_bit = _base_bit, \
+ .pud_en_offset = _pud_en_off, \
+ .pud_sel_offset = _pud_sel_off, \
+ .curr_offset = _curr_off, \
+ .smt_offset = _smt_off, \
+ .curr_type = _curr_type, \
+ }
+
+
#define RTK_PIN_MUX(_name, _mux_off, _mux_mask, ...) \
{ \
.name = # _name, \
@@ -68,8 +93,15 @@ struct rtd119x_pinctrl_desc {
unsigned int num_functions;
const struct rtd119x_pin_desc *muxes;
unsigned int num_muxes;
+ const struct rtd119x_pin_config_desc *configs;
+ unsigned int num_configs;
};
+#define PCONF_UNSUPP 0xffffffff
+#define PADDRI_4_8 1
+#define PADDRI_2_4 0
+
+
#include "pinctrl-rtd1195.h"
#include "pinctrl-rtd1295.h"
@@ -165,6 +197,19 @@ static const struct rtd119x_pin_desc *rtd119x_pinctrl_find_mux(struct rtd119x_pi
return NULL;
}
+static const struct rtd119x_pin_config_desc *rtd119x_pinctrl_find_config(struct rtd119x_pinctrl *data, const char *name)
+{
+ int i;
+
+ for (i = 0; i < data->info->num_configs; i++) {
+ if (strcmp(data->info->configs[i].name, name) == 0)
+ return &data->info->configs[i];
+ }
+
+ return NULL;
+}
+
+
static int rtd119x_pinctrl_set_one_mux(struct pinctrl_dev *pcdev,
unsigned int pin, const char *func_name)
{
@@ -247,10 +292,100 @@ static const struct pinmux_ops rtd119x_pinmux_ops = {
.gpio_request_enable = rtd119x_pinctrl_gpio_request_enable,
};
+
+static int rtd119x_pconf_parse_conf(struct rtd119x_pinctrl *data,
+ const struct rtd119x_pin_config_desc *config_desc, enum pin_config_param param,
+ enum pin_config_param arg)
+{
+ u8 set_val = 0;
+ u16 strength;
+ u32 val, mask;
+ int pulsel_off, pulen_off, smt_off, curr_off;
+
+ smt_off = config_desc->base_bit + config_desc->smt_offset;
+ curr_off = config_desc->base_bit + config_desc->curr_offset;
+ pulsel_off = config_desc->base_bit + config_desc->pud_sel_offset;
+ pulen_off = config_desc->base_bit + config_desc->pud_en_offset;
+
+ switch (param) {
+ case PIN_CONFIG_INPUT_SCHMITT:
+ case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+ set_val = arg;
+ if (set_val)
+ set_val = 1;
+ else
+ set_val = 0;
+
+ val = readl(data->base + config_desc->reg_offset);
+ mask = 1 << smt_off;
+ val = (val & ~mask) | (set_val << smt_off);
+ writel(val, data->base + config_desc->reg_offset);
+ break;
+ case PIN_CONFIG_DRIVE_STRENGTH:
+ strength = arg;
+ switch (config_desc->curr_type) {
+ case PADDRI_4_8:
+ if (strength == 4)
+ set_val = 0;
+ else if (strength == 8)
+ set_val = 1;
+ else
+ return -EINVAL;
+ break;
+ case PADDRI_2_4:
+ if (strength == 2)
+ set_val = 0;
+ else if (strength == 4)
+ set_val = 1;
+ else
+ return -EINVAL;
+ break;
+ case PCONF_UNSUPP:
+ pr_err("[%s] not support drive strength\n", config_desc->name);
+ return -ENOTSUPP;
+ break;
+ default:
+ return -EINVAL;
+ }
+ val = readl(data->base + config_desc->reg_offset);
+ mask = 1 << curr_off;
+ val = (val & ~mask) | (set_val << curr_off);
+ writel(val, data->base + config_desc->reg_offset);
+ break;
+ case PIN_CONFIG_DRIVE_PUSH_PULL:
+ val = readl(data->base + config_desc->reg_offset);
+ mask = 1 << pulen_off;
+ val = (val & ~mask) | (1 << pulen_off);
+ writel(val, data->base + config_desc->reg_offset);
+ break;
+ case PIN_CONFIG_BIAS_DISABLE:
+ val = readl(data->base + config_desc->reg_offset);
+ mask = 1 << pulen_off;
+ val = val & ~mask;
+ writel(val, data->base + config_desc->reg_offset);
+ break;
+ case PIN_CONFIG_BIAS_PULL_UP:
+ val = readl(data->base + config_desc->reg_offset);
+ mask = (1 << pulen_off) | (1 << pulsel_off);
+ val = (val & ~mask) | (1 << pulen_off) | (1 << pulsel_off);
+ writel(val, data->base + config_desc->reg_offset);
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ val = readl(data->base + config_desc->reg_offset);
+ mask = (1 << pulen_off) | (0 << pulsel_off);
+ val = (val & ~mask) | (1 << pulen_off);
+ writel(val, data->base + config_desc->reg_offset);
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
static int rtd119x_pin_config_get(struct pinctrl_dev *pcdev, unsigned pinnr,
unsigned long *config)
{
- //struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
unsigned int param = pinconf_to_config_param(*config);
unsigned int arg = 0;
@@ -266,11 +401,32 @@ static int rtd119x_pin_config_get(struct pinctrl_dev *pcdev, unsigned pinnr,
static int rtd119x_pin_config_set(struct pinctrl_dev *pcdev, unsigned pinnr,
unsigned long *configs, unsigned num_configs)
{
- //struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+ struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+ const struct rtd119x_pin_config_desc *config_desc;
+ const struct pinctrl_pin_desc *pin_desc;
+ const char *pin_name;
+ int i;
+
+ pin_desc = rtd119x_pinctrl_get_pin_by_number(data, pinnr);
+ if (!pin_desc)
+ return -ENOTSUPP;
+
+ pin_name = pin_desc->name;
+ config_desc = rtd119x_pinctrl_find_config(data, pin_name);
+ if (!config_desc)
+ return -ENOTSUPP;
+
+ for (i = 0; i < num_configs; i++) {
+ rtd119x_pconf_parse_conf(data, config_desc,
+ pinconf_to_config_param(configs[i]),
+ pinconf_to_config_argument(configs[i]));
+ }
return 0;
}
+
+
static const struct pinconf_ops rtd119x_pinconf_ops = {
.is_generic = true,
.pin_config_get = rtd119x_pin_config_get,
diff --git a/drivers/pinctrl/pinctrl-rtd1295.h b/drivers/pinctrl/pinctrl-rtd1295.h
index 383870adb42f..0232c5d8b353 100644
--- a/drivers/pinctrl/pinctrl-rtd1295.h
+++ b/drivers/pinctrl/pinctrl-rtd1295.h
@@ -415,6 +415,44 @@ static const struct rtd119x_pin_desc rtd1295_iso_muxes[] = {
RTK_PIN_FUNC(0x2 << 12, "uart2_1")),
};
+static const struct rtd119x_pin_config_desc rtd1295_iso_configs[] = {
+ RTK_PIN_CONFIG(iso_gpio_2, 0x0, 0, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(iso_gpio_3, 0x0, 4, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(ir_rx, 0x0, 8, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(iso_gpio_4, 0x0, 12, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(iso_gpio_5, 0x0, 16, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(iso_gpio_7, 0x0, 20, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(i2c_sda_0, 0x0, 24, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(i2c_scl_0, 0x0, 28, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(ur1_rx, 0x4, 0, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(ur1_tx, 0x4, 4, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(ur1_rts_n, 0x4, 8, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(ur1_cts_n, 0x4, 12, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(ur0_rx, 0x4, 16, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(ur0_tx, 0x4, 20, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(etn_led_link, 0x4, 24, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(etn_led_rxtx, 0x4, 28, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(i2c_sda_6, 0x8, 12, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(i2c_scl_6, 0x8, 16, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(ir_tx, 0x8, 20, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(i2c_sda_1, 0x8, 24, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(i2c_scl_1, 0x8, 28, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(hdmi_hpd, 0xc, 12, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(nat_led_0, 0xc, 16, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(nat_led_1, 0xc, 20, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(nat_led_2, 0xc, 24, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(nat_led_3, 0xc, 28, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(iso_gpio_21, 0x18, 0, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(iso_gpio_22, 0x18, 4, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(iso_gpio_23, 0x18, 8, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(iso_gpio_24, 0x18, 12, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(iso_gpio_25, 0x18, 16, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(iso_gpio_33, 0x20, 0, 1, 0, 2, 3, 2),
+ RTK_PIN_CONFIG(iso_gpio_34, 0x20, 4, 1, 0, 2, 3, 2),
+};
+
+
+
static const struct rtd119x_pinctrl_desc rtd1295_iso_pinctrl_desc = {
.pins = rtd1295_iso_pins,
.num_pins = ARRAY_SIZE(rtd1295_iso_pins),
@@ -424,6 +462,8 @@ static const struct rtd119x_pinctrl_desc rtd1295_iso_pinctrl_desc = {
.num_functions = ARRAY_SIZE(rtd1295_iso_pin_functions),
.muxes = rtd1295_iso_muxes,
.num_muxes = ARRAY_SIZE(rtd1295_iso_muxes),
+ .configs = rtd1295_iso_configs,
+ .num_configs = ARRAY_SIZE(rtd1295_iso_configs),
};
/* SB2 */
@@ -979,6 +1019,64 @@ static const struct rtd119x_pin_desc rtd1295_sb2_muxes[] = {
RTK_PIN_FUNC(0x1 << 22, "rgmii")),
};
+static const struct rtd119x_pin_config_desc rtd1295_sb2_configs[] = {
+ RTK_PIN_CONFIG(tp0_clk, 0x28, 0, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(tp0_sync, 0x28, 4, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(tp0_valid, 0x28, 8, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(tp0_data, 0x28, 12, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(tp1_clk, 0x2C, 0, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(tp1_sync, 0x2C, 4, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(tp1_valid, 0x2C, 8, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(tp1_data, 0x2C, 12, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(i2c_sda_4, 0x30, 8, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(i2c_scl_4, 0x30, 12, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(i2c_sda_5, 0x30, 16, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(i2c_scl_5, 0x30, 20, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(gpio_0, 0x34, 0, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(gpio_1, 0x34, 4, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(gpio_2, 0x34, 8, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(gpio_3, 0x34, 12, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(gpio_4, 0x34, 16, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(gpio_5, 0x34, 20, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(gpio_6, 0x34, 24, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(gpio_7, 0x34, 28, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(gpio_8, 0x38, 0, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(gpio_9, 0x38, 4, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(usb_id, 0x38, 8, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(sensor_stb_0, 0x38, 12, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(sensor_stb_1, 0x38, 16, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(sensor_rst, 0x38, 20, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(sensor_cko_0, 0x38, 24, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(sensor_cko_1, 0x38, 28, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii0_txc, 0x64, 0, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii0_tx_ctl, 0x64, 4, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii0_txd_0, 0x64, 8, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii0_txd_1, 0x64, 12, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii0_txd_2, 0x64, 16, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii0_txd_3, 0x64, 20, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii0_rxc, 0x64, 24, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii0_rx_ctl, 0x64, 28, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii0_rxd_0, 0x68, 0, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii0_rxd_1, 0x68, 4, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii0_rxd_2, 0x68, 8, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii0_rxd_3, 0x68, 12, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii0_mdio, 0x68, 16, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii0_mdc, 0x68, 20, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii1_txc, 0x74, 0, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii1_tx_ctl, 0x74, 4, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii1_txd_0, 0x74, 8, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii1_txd_1, 0x74, 12, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii1_txd_2, 0x74, 16, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii1_txd_3, 0x74, 20, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii1_rxc, 0x74, 24, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii1_rx_ctl, 0x74, 28, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii1_rxd_0, 0x78, 0, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii1_rxd_1, 0x78, 4, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii1_rxd_2, 0x78, 8, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(rgmii1_rxd_3, 0x78, 12, 1, 0, 2, 3, PADDRI_4_8),
+};
+
+
static const struct rtd119x_pinctrl_desc rtd1295_sb2_pinctrl_desc = {
.pins = rtd1295_sb2_pins,
.num_pins = ARRAY_SIZE(rtd1295_sb2_pins),
@@ -988,6 +1086,8 @@ static const struct rtd119x_pinctrl_desc rtd1295_sb2_pinctrl_desc = {
.num_functions = ARRAY_SIZE(rtd1295_sb2_pin_functions),
.muxes = rtd1295_sb2_muxes,
.num_muxes = ARRAY_SIZE(rtd1295_sb2_muxes),
+ .configs = rtd1295_sb2_configs,
+ .num_configs = ARRAY_SIZE(rtd1295_sb2_configs),
};
/* Disp */
@@ -1105,6 +1205,20 @@ static const struct rtd119x_pin_desc rtd1295_disp_muxes[] = {
RTK_PIN_FUNC(0x2 << 18, "ai")),
};
+static const struct rtd119x_pin_config_desc rtd1295_disp_configs[] = {
+ RTK_PIN_CONFIG(spdif, 0x0, 0, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(dmic_clk, 0x0, 4, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(dmic_data, 0x0, 8, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(ao_lrck, 0x4, 0, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(ao_bck, 0x4, 4, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(aock, 0x4, 8, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(ao_sd_0, 0x4, 12, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(ao_sd_1, 0x4, 16, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(ao_sd_2, 0x4, 20, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(ao_sd_3, 0x4, 24, 1, 0, 2, 3, PADDRI_2_4),
+};
+
+
static const struct rtd119x_pinctrl_desc rtd1295_disp_pinctrl_desc = {
.pins = rtd1295_disp_pins,
.num_pins = ARRAY_SIZE(rtd1295_disp_pins),
@@ -1114,6 +1228,8 @@ static const struct rtd119x_pinctrl_desc rtd1295_disp_pinctrl_desc = {
.num_functions = ARRAY_SIZE(rtd1295_disp_pin_functions),
.muxes = rtd1295_disp_muxes,
.num_muxes = ARRAY_SIZE(rtd1295_disp_muxes),
+ .configs = rtd1295_disp_configs,
+ .num_configs = ARRAY_SIZE(rtd1295_disp_configs),
};
/* CR */
@@ -1480,6 +1596,47 @@ static const struct rtd119x_pin_desc rtd1295_cr_muxes[] = {
RTK_PIN_FUNC(0x1 << 12, "pll_test")),
};
+static const struct rtd119x_pin_config_desc rtd1295_cr_configs[] = {
+ RTK_PIN_CONFIG(nf_dqs, 0x8, 0, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(nf_ale, 0x8, 4, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(nf_ce_n_0, 0x8, 8, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(nf_ce_n_1, 0x8, 12, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(nf_rdy, 0x8, 16, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(nf_rd_n, 0x8, 20, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(nf_wr_n, 0x8, 24, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(nf_cle, 0x8, 28, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(nf_dd_0, 0xc, 0, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(nf_dd_1, 0xc, 4, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(nf_dd_2, 0xc, 8, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(nf_dd_3, 0xc, 12, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(nf_dd_4, 0xc, 16, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(nf_dd_5, 0xc, 20, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(nf_dd_6, 0xc, 24, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(nf_dd_7, 0xc, 28, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(mmc_cmd, 0x10, 0, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(mmc_clk, 0x10, 4, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(mmc_wp, 0x10, 8, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(mmc_cd, 0x10, 12, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(mmc_data_0, 0x10, 16, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(mmc_data_1, 0x10, 20, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(mmc_data_2, 0x10, 24, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(mmc_data_3, 0x10, 28, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(sdio_cmd, 0x14, 0, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(sdio_clk, 0x14, 4, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(sdio_data_0, 0x14, 16, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(sdio_data_1, 0x14, 20, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(sdio_data_2, 0x14, 24, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(sdio_data_3, 0x14, 28, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(emmc_dd_sb, 0x18, 0, 1, 0, 2, 3, PCONF_UNSUPP),
+ RTK_PIN_CONFIG(pcie_clkreq_0, 0x18, 4, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(pcie_clkreq_1, 0x18, 8, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(prob_0, 0x18, 12, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(prob_1, 0x18, 16, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(prob_2, 0x18, 20, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(prob_3, 0x18, 24, 1, 0, 2, 3, PADDRI_4_8),
+};
+
+
static const struct rtd119x_pinctrl_desc rtd1295_cr_pinctrl_desc = {
.pins = rtd1295_cr_pins,
.num_pins = ARRAY_SIZE(rtd1295_cr_pins),
@@ -1489,6 +1646,8 @@ static const struct rtd119x_pinctrl_desc rtd1295_cr_pinctrl_desc = {
.num_functions = ARRAY_SIZE(rtd1295_cr_pin_functions),
.muxes = rtd1295_cr_muxes,
.num_muxes = ARRAY_SIZE(rtd1295_cr_muxes),
+ .configs = rtd1295_cr_configs,
+ .num_configs = ARRAY_SIZE(rtd1295_cr_configs),
};
#endif
--
2.26.2
^ permalink raw reply related
* [PATCH 1/7] pinctrl: realtek: rtd1295: Add missed pins.
From: TY Chang @ 2020-05-14 9:21 UTC (permalink / raw)
To: linux-realtek-soc, afaerber
Cc: linus.walleij, linux-gpio, robh+dt, devicetree, linux-kernel
In-Reply-To: <20200514092125.6875-1-tychang@realtek.com>
The current Realtek DHC SoC RTD1295 pinctrl driver missed some
pins definition that may make the pin group does not mux completely.
Signed-off-by: TY Chang <tychang@realtek.com>
---
drivers/pinctrl/pinctrl-rtd119x.c | 4 +-
drivers/pinctrl/pinctrl-rtd1295.h | 192 +++++++++++++++++++++++++-----
2 files changed, 161 insertions(+), 35 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rtd119x.c b/drivers/pinctrl/pinctrl-rtd119x.c
index d69716243297..60bf8c283a7a 100644
--- a/drivers/pinctrl/pinctrl-rtd119x.c
+++ b/drivers/pinctrl/pinctrl-rtd119x.c
@@ -304,7 +304,7 @@ static void rtd119x_pinctrl_selftest(struct rtd119x_pinctrl *data)
/* Check for function */
for (k = 0; k < data->info->num_functions; k++) {
if (strcmp(data->info->functions[k].name,
- data->info->muxes[i].functions[j].name) == 0)
+ data->info->muxes[i].functions[j].name) == 0)
break;
}
if (k == data->info->num_functions)
@@ -314,7 +314,7 @@ static void rtd119x_pinctrl_selftest(struct rtd119x_pinctrl *data)
/* Check for duplicate mux value - assumption: ascending order */
if (j > 0 && data->info->muxes[i].functions[j].mux_value
- <= data->info->muxes[i].functions[j - 1].mux_value)
+ < data->info->muxes[i].functions[j - 1].mux_value)
dev_warn(data->pcdev->dev, "Mux %s function %s has unexpected value\n",
data->info->muxes[i].name,
data->info->muxes[i].functions[j].name);
diff --git a/drivers/pinctrl/pinctrl-rtd1295.h b/drivers/pinctrl/pinctrl-rtd1295.h
index 57d8129f12b2..383870adb42f 100644
--- a/drivers/pinctrl/pinctrl-rtd1295.h
+++ b/drivers/pinctrl/pinctrl-rtd1295.h
@@ -37,6 +37,12 @@ enum rtd1295_iso_pins {
RTD1295_NAT_LED_3,
RTD1295_ISO_GPIO_33,
RTD1295_ISO_GPIO_34,
+ RTD1295_PWM_23_LOC0,
+ RTD1295_PWM_01_LOC0,
+ RTD1295_PWM_23_LOC1,
+ RTD1295_PWM_01_LOC1,
+ RTD1295_EJTAG_AVCPU_LOC,
+ RTD1295_UR2_LOC,
};
static const struct pinctrl_pin_desc rtd1295_iso_pins[] = {
@@ -75,6 +81,12 @@ static const struct pinctrl_pin_desc rtd1295_iso_pins[] = {
PINCTRL_PIN(RTD1295_NAT_LED_3, "nat_led_3"),
PINCTRL_PIN(RTD1295_ISO_GPIO_33, "iso_gpio_33"),
PINCTRL_PIN(RTD1295_ISO_GPIO_34, "iso_gpio_34"),
+ PINCTRL_PIN(RTD1295_PWM_23_LOC0, "pwm_23_loc0"),
+ PINCTRL_PIN(RTD1295_PWM_01_LOC0, "pwm_01_loc0"),
+ PINCTRL_PIN(RTD1295_PWM_23_LOC1, "pwm_23_loc1"),
+ PINCTRL_PIN(RTD1295_PWM_01_LOC1, "pwm_01_loc1"),
+ PINCTRL_PIN(RTD1295_EJTAG_AVCPU_LOC, "ejtag_avcpu_loc"),
+ PINCTRL_PIN(RTD1295_UR2_LOC, "ur2_loc"),
};
static const unsigned int rtd1295_iso_gpio_0_pins[] = { RTD1295_ISO_GPIO_0 };
@@ -112,6 +124,12 @@ static const unsigned int rtd1295_nat_led_2_pins[] = { RTD1295_NAT_LED_2 };
static const unsigned int rtd1295_nat_led_3_pins[] = { RTD1295_NAT_LED_3 };
static const unsigned int rtd1295_iso_gpio_33_pins[] = { RTD1295_ISO_GPIO_33 };
static const unsigned int rtd1295_iso_gpio_34_pins[] = { RTD1295_ISO_GPIO_34 };
+static const unsigned int rtd1295_pwm_23_loc0_pins[] = { RTD1295_PWM_23_LOC0 };
+static const unsigned int rtd1295_pwm_01_loc0_pins[] = { RTD1295_PWM_01_LOC0 };
+static const unsigned int rtd1295_pwm_23_loc1_pins[] = { RTD1295_PWM_23_LOC1 };
+static const unsigned int rtd1295_pwm_01_loc1_pins[] = { RTD1295_PWM_01_LOC1 };
+static const unsigned int rtd1295_ejtag_avcpu_loc_pins[] = { RTD1295_EJTAG_AVCPU_LOC };
+static const unsigned int rtd1295_ur2_loc_pins[] = { RTD1295_UR2_LOC };
static const unsigned int rtd1295_i2c0_pins[] = { RTD1295_I2C_SCL_0, RTD1295_I2C_SDA_0 };
static const unsigned int rtd1295_i2c1_pins[] = { RTD1295_I2C_SCL_1, RTD1295_I2C_SDA_1 };
@@ -164,6 +182,12 @@ static const struct rtd119x_pin_group_desc rtd1295_iso_pin_groups[] = {
RTD1295_GROUP(nat_led_3),
RTD1295_GROUP(iso_gpio_33),
RTD1295_GROUP(iso_gpio_34),
+ RTD1295_GROUP(pwm_23_loc0),
+ RTD1295_GROUP(pwm_01_loc0),
+ RTD1295_GROUP(pwm_23_loc1),
+ RTD1295_GROUP(pwm_01_loc1),
+ RTD1295_GROUP(ejtag_avcpu_loc),
+ RTD1295_GROUP(ur2_loc),
RTD1295_GROUP(i2c0),
RTD1295_GROUP(i2c1),
@@ -192,14 +216,25 @@ static const char * const rtd1295_iso_i2c6_groups[] = { "i2c_scl_6", "i2c_sda_6"
static const char * const rtd1295_iso_ir_rx_groups[] = { "ir_rx" };
static const char * const rtd1295_iso_ir_tx_groups[] = { "ir_tx" };
static const char * const rtd1295_iso_nat_led_groups[] = { "nat_led_0", "nat_led_1", "nat_led_2", "nat_led_3" };
-static const char * const rtd1295_iso_pwm_groups[] = { "etn_led_link", "etn_led_rxtx", "nat_led_0", "nat_led_1" };
+static const char * const rtd1295_iso_pwm_1_groups[] = { "etn_led_link", "etn_led_rxtx", "nat_led_0", "nat_led_1" };
+static const char * const rtd1295_iso_pwm_0_groups[] = { "iso_gpio_21", "iso_gpio_22", "iso_gpio_23", "iso_gpio_24" };
static const char * const rtd1295_iso_rtc_groups[] = { "iso_gpio_25" };
static const char * const rtd1295_iso_sc_groups[] = { "nat_led_0", "nat_led_1", "nat_led_2", "nat_led_3" };
static const char * const rtd1295_iso_standby_dbg_groups[] = { "iso_gpio_2", "iso_gpio_3", "ir_rx" };
static const char * const rtd1295_iso_uart0_groups[] = { "ur0_rx", "ur0_tx", "uart0" };
static const char * const rtd1295_iso_uart1_groups[] = { "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n", "uart1" };
-static const char * const rtd1295_iso_uart2_0_groups[] = { "iso_gpio_2", "iso_gpio_3", "iso_gpio_4", "iso_gpio_5" };
-static const char * const rtd1295_iso_uart2_1_groups[] = { "iso_gpio_23", "iso_gpio_24", "iso_gpio_33", "iso_gpio_34" };
+static const char * const rtd1295_iso_uart2_0_groups[] = { "iso_gpio_2", "iso_gpio_3", "iso_gpio_4", "iso_gpio_5", "ur2_loc" };
+static const char * const rtd1295_iso_uart2_1_groups[] = { "iso_gpio_23", "iso_gpio_24", "iso_gpio_33", "iso_gpio_34", "ur2_loc" };
+static const char * const rtd1295_iso_pwm_01_loc0_normal_groups[] = { "pwm_01_loc0" };
+static const char * const rtd1295_iso_pwm_23_loc0_normal_groups[] = { "pwm_23_loc0" };
+static const char * const rtd1295_iso_pwm_01_loc0_open_drain_groups[] = { "pwm_01_loc0" };
+static const char * const rtd1295_iso_pwm_23_loc0_open_drain_groups[] = { "pwm_23_loc0" };
+static const char * const rtd1295_iso_pwm_01_loc1_normal_groups[] = { "pwm_01_loc1" };
+static const char * const rtd1295_iso_pwm_23_loc1_normal_groups[] = { "pwm_23_loc1" };
+static const char * const rtd1295_iso_pwm_01_loc1_open_drain_groups[] = { "pwm_01_loc1" };
+static const char * const rtd1295_iso_pwm_23_loc1_open_drain_groups[] = { "pwm_23_loc1" };
+static const char * const rtd1295_iso_acpu_ejtag_loc_nf_groups[] = { "ejtag_avcpu_loc" };
+
#define RTD1295_FUNC(_name) \
{ \
@@ -219,7 +254,8 @@ static const struct rtd119x_pin_func_desc rtd1295_iso_pin_functions[] = {
RTD1295_FUNC(ir_rx),
RTD1295_FUNC(ir_tx),
RTD1295_FUNC(nat_led),
- RTD1295_FUNC(pwm),
+ RTD1295_FUNC(pwm_0),
+ RTD1295_FUNC(pwm_1),
RTD1295_FUNC(rtc),
RTD1295_FUNC(sc),
RTD1295_FUNC(standby_dbg),
@@ -227,6 +263,15 @@ static const struct rtd119x_pin_func_desc rtd1295_iso_pin_functions[] = {
RTD1295_FUNC(uart1),
RTD1295_FUNC(uart2_0),
RTD1295_FUNC(uart2_1),
+ RTD1295_FUNC(pwm_01_loc0_normal),
+ RTD1295_FUNC(pwm_23_loc0_normal),
+ RTD1295_FUNC(pwm_01_loc0_open_drain),
+ RTD1295_FUNC(pwm_23_loc0_open_drain),
+ RTD1295_FUNC(pwm_01_loc1_normal),
+ RTD1295_FUNC(pwm_23_loc1_normal),
+ RTD1295_FUNC(pwm_01_loc1_open_drain),
+ RTD1295_FUNC(pwm_23_loc1_open_drain),
+ RTD1295_FUNC(acpu_ejtag_loc_nf),
};
#undef RTD1295_FUNC
@@ -278,11 +323,11 @@ static const struct rtd119x_pin_desc rtd1295_iso_muxes[] = {
RTK_PIN_MUX(etn_led_link, 0x10, GENMASK(27, 26),
RTK_PIN_FUNC(0x0 << 26, "gpio"),
RTK_PIN_FUNC(0x1 << 26, "etn_led"),
- RTK_PIN_FUNC(0x2 << 26, "pwm")),
+ RTK_PIN_FUNC(0x2 << 26, "pwm_1")),
RTK_PIN_MUX(etn_led_rxtx, 0x10, GENMASK(29, 28),
RTK_PIN_FUNC(0x0 << 28, "gpio"),
RTK_PIN_FUNC(0x1 << 28, "etn_led"),
- RTK_PIN_FUNC(0x2 << 28, "pwm")),
+ RTK_PIN_FUNC(0x2 << 28, "pwm_1")),
RTK_PIN_MUX(i2c_scl_6, 0x14, GENMASK(1, 0),
RTK_PIN_FUNC(0x0 << 0, "gpio"),
@@ -311,12 +356,12 @@ static const struct rtd119x_pin_desc rtd1295_iso_muxes[] = {
RTK_PIN_MUX(nat_led_0, 0x14, GENMASK(17, 16),
RTK_PIN_FUNC(0x0 << 16, "gpio"),
RTK_PIN_FUNC(0x1 << 16, "nat_led"),
- RTK_PIN_FUNC(0x2 << 16, "pwm"),
+ RTK_PIN_FUNC(0x2 << 16, "pwm_1"),
RTK_PIN_FUNC(0x3 << 16, "sc")),
RTK_PIN_MUX(nat_led_1, 0x14, GENMASK(19, 18),
RTK_PIN_FUNC(0x0 << 18, "gpio"),
RTK_PIN_FUNC(0x1 << 18, "nat_led"),
- RTK_PIN_FUNC(0x2 << 18, "pwm"),
+ RTK_PIN_FUNC(0x2 << 18, "pwm_1"),
RTK_PIN_FUNC(0x3 << 18, "sc")),
RTK_PIN_MUX(nat_led_2, 0x14, GENMASK(21, 20),
RTK_PIN_FUNC(0x0 << 20, "gpio"),
@@ -326,20 +371,38 @@ static const struct rtd119x_pin_desc rtd1295_iso_muxes[] = {
RTK_PIN_FUNC(0x0 << 22, "gpio"),
RTK_PIN_FUNC(0x1 << 22, "nat_led"),
RTK_PIN_FUNC(0x3 << 22, "sc")),
+ RTK_PIN_MUX(pwm_23_loc0, 0x14, GENMASK(24, 24),
+ RTK_PIN_FUNC(0x0 << 24, "pwm_23_loc0_normal"),
+ RTK_PIN_FUNC(0x1 << 24, "pwm_23_loc0_open_drain")),
+ RTK_PIN_MUX(pwm_01_loc0, 0x14, GENMASK(25, 25),
+ RTK_PIN_FUNC(0x0 << 25, "pwm_01_loc0_normal"),
+ RTK_PIN_FUNC(0x1 << 25, "pwm_01_loc0_open_drain")),
+ RTK_PIN_MUX(pwm_23_loc1, 0x14, GENMASK(26, 26),
+ RTK_PIN_FUNC(0x0 << 26, "pwm_23_loc1_normal"),
+ RTK_PIN_FUNC(0x1 << 26, "pwm_23_loc1_open_drain")),
+ RTK_PIN_MUX(pwm_01_loc1, 0x14, GENMASK(27, 27),
+ RTK_PIN_FUNC(0x0 << 27, "pwm_01_loc1_normal"),
+ RTK_PIN_FUNC(0x1 << 27, "pwm_01_loc1_open_drain")),
+ RTK_PIN_MUX(ejtag_avcpu_loc, 0x14, GENMASK(29, 28),
+ RTK_PIN_FUNC(0x1 << 28, "acpu_ejtag_loc_iso"),
+ RTK_PIN_FUNC(0x2 << 28, "acpu_ejtag_loc_nf")),
+ RTK_PIN_MUX(ur2_loc, 0x14, GENMASK(31, 30),
+ RTK_PIN_FUNC(0x1 << 30, "uart2_0"),
+ RTK_PIN_FUNC(0x2 << 30, "uart2_1")),
RTK_PIN_MUX(iso_gpio_21, 0x1c, GENMASK(1, 0),
RTK_PIN_FUNC(0x0 << 0, "gpio"),
- RTK_PIN_FUNC(0x1 << 0, "pwm")),
+ RTK_PIN_FUNC(0x1 << 0, "pwm_0")),
RTK_PIN_MUX(iso_gpio_22, 0x1c, GENMASK(3, 2),
RTK_PIN_FUNC(0x0 << 2, "gpio"),
- RTK_PIN_FUNC(0x1 << 2, "pwm")),
+ RTK_PIN_FUNC(0x1 << 2, "pwm_0")),
RTK_PIN_MUX(iso_gpio_23, 0x1c, GENMASK(5, 4),
RTK_PIN_FUNC(0x0 << 4, "gpio"),
- RTK_PIN_FUNC(0x1 << 4, "pwm"),
+ RTK_PIN_FUNC(0x1 << 4, "pwm_0"),
RTK_PIN_FUNC(0x2 << 4, "uart2_1")),
RTK_PIN_MUX(iso_gpio_24, 0x1c, GENMASK(7, 6),
RTK_PIN_FUNC(0x0 << 6, "gpio"),
- RTK_PIN_FUNC(0x1 << 6, "pwm"),
+ RTK_PIN_FUNC(0x1 << 6, "pwm_0"),
RTK_PIN_FUNC(0x2 << 6, "uart2_1")),
RTK_PIN_MUX(iso_gpio_25, 0x1c, GENMASK(9, 8),
RTK_PIN_FUNC(0x0 << 8, "gpio"),
@@ -420,6 +483,11 @@ enum rtd1295_sb2_pins {
RTD1295_RGMII1_RXD_1,
RTD1295_RGMII1_RXD_2,
RTD1295_RGMII1_RXD_3,
+ RTD1295_HI_LOC,
+ RTD1295_EJTAG_SCPU_LOC,
+ RTD1295_SF_EN,
+ RTD1295_TP0_LOC,
+ RTD1295_TP1_LOC,
};
static const struct pinctrl_pin_desc rtd1295_sb2_pins[] = {
@@ -477,6 +545,11 @@ static const struct pinctrl_pin_desc rtd1295_sb2_pins[] = {
PINCTRL_PIN(RTD1295_RGMII1_RXD_1, "rgmii1_rxd_1"),
PINCTRL_PIN(RTD1295_RGMII1_RXD_2, "rgmii1_rxd_2"),
PINCTRL_PIN(RTD1295_RGMII1_RXD_3, "rgmii1_rxd_3"),
+ PINCTRL_PIN(RTD1295_HI_LOC, "hif_loc"),
+ PINCTRL_PIN(RTD1295_EJTAG_SCPU_LOC, "ejtag_scpu_loc"),
+ PINCTRL_PIN(RTD1295_SF_EN, "sf_en"),
+ PINCTRL_PIN(RTD1295_TP0_LOC, "tp0_loc"),
+ PINCTRL_PIN(RTD1295_TP1_LOC, "tp1_loc"),
};
static const unsigned int rtd1295_gpio_0_pins[] = { RTD1295_GPIO_0 };
@@ -533,6 +606,16 @@ static const unsigned int rtd1295_rgmii1_rxd_0_pins[] = { RTD1295_RGMII1_RXD_0 }
static const unsigned int rtd1295_rgmii1_rxd_1_pins[] = { RTD1295_RGMII1_RXD_1 };
static const unsigned int rtd1295_rgmii1_rxd_2_pins[] = { RTD1295_RGMII1_RXD_2 };
static const unsigned int rtd1295_rgmii1_rxd_3_pins[] = { RTD1295_RGMII1_RXD_3 };
+static const unsigned int rtd1295_hif_loc_pins[] = { RTD1295_HI_LOC };
+static const unsigned int rtd1295_ejtag_scpu_loc_pins[] = { RTD1295_EJTAG_SCPU_LOC };
+static const unsigned int rtd1295_sf_en_pins[] = { RTD1295_SF_EN };
+static const unsigned int rtd1295_tp0_loc_pins[] = { RTD1295_TP0_LOC };
+static const unsigned int rtd1295_tp1_loc_pins[] = { RTD1295_TP1_LOC };
+
+
+
+
+
static const struct rtd119x_pin_group_desc rtd1295_sb2_pin_groups[] = {
RTD1295_GROUP(gpio_0),
@@ -589,6 +672,11 @@ static const struct rtd119x_pin_group_desc rtd1295_sb2_pin_groups[] = {
RTD1295_GROUP(rgmii1_rxd_1),
RTD1295_GROUP(rgmii1_rxd_2),
RTD1295_GROUP(rgmii1_rxd_3),
+ RTD1295_GROUP(hif_loc),
+ RTD1295_GROUP(ejtag_scpu_loc),
+ RTD1295_GROUP(sf_en),
+ RTD1295_GROUP(tp0_loc),
+ RTD1295_GROUP(tp1_loc),
};
static const char * const rtd1295_sb2_gpio_groups[] = {
@@ -619,17 +707,23 @@ static const char * const rtd1295_sb2_rgmii_groups[] = {
"rgmii1_txc", "rgmii1_tx_ctl", "rgmii1_txd_0", "rgmii1_txd_1", "rgmii1_txd_2", "rgmii1_txd_3",
"rgmii1_rxc", "rgmii1_rx_ctl", "rgmii1_rxd_0", "rgmii1_rxd_1", "rgmii1_rxd_2", "rgmii1_rxd_3",
};
-static const char * const rtd1295_sb2_scpu_ejtag_loc_gpio_groups[] = { "gpio_4", "gpio_5", "gpio_6", "gpio_7", "gpio_8" };
+
+static const char * const rtd1295_sb2_scpu_ejtag_loc_gpio_groups[] = { "gpio_4", "gpio_5", "gpio_6", "gpio_7", "gpio_8", "ejtag_scpu_loc" };
+static const char * const rtd1295_sb2_scpu_ejtag_loc_cr_groups[] = { "ejtag_scpu_loc" };
static const char * const rtd1295_sb2_sensor_cko_output_groups[] = { "sensor_cko_0", "sensor_cko_1" };
static const char * const rtd1295_sb2_spi_groups[] = { "gpio_0", "gpio_1", "gpio_2", "gpio_3" };
static const char * const rtd1295_sb2_test_loop_dis_groups[] = { "usb_id" };
-static const char * const rtd1295_sb2_tp0_loc_rgmii0_tx_groups[] = { "rgmii0_txd_0", "rgmii0_txd_1", "rgmii0_txd_2", "rgmii0_txd_3" };
-static const char * const rtd1295_sb2_tp0_loc_tp0_groups[] = { "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk" };
-static const char * const rtd1295_sb2_tp0_loc_tp1_groups[] = { "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk" };
-static const char * const rtd1295_sb2_tp1_loc_rgmii0_rx_groups[] = { "rgmii0_rxd_0", "rgmii0_rxd_1", "rgmii0_rxd_2", "rgmii0_rxd_3" };
-static const char * const rtd1295_sb2_tp1_loc_tp0_groups[] = { "tp1_data", "tp1_sync", "tp1_valid", "tp1_clk" };
-static const char * const rtd1295_sb2_tp1_loc_tp1_groups[] = { "tp1_data", "tp1_sync", "tp1_valid", "tp1_clk" };
+static const char * const rtd1295_sb2_tp0_loc_rgmii0_tx_groups[] = { "rgmii0_txd_0", "rgmii0_txd_1", "rgmii0_txd_2", "rgmii0_txd_3", "tp0_loc" };
+static const char * const rtd1295_sb2_tp0_loc_tp0_groups[] = { "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk", "tp0_loc" };
+static const char * const rtd1295_sb2_tp0_loc_tp1_groups[] = { "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk", "tp0_loc" };
+static const char * const rtd1295_sb2_tp1_loc_rgmii0_rx_groups[] = { "rgmii0_rxd_0", "rgmii0_rxd_1", "rgmii0_rxd_2", "rgmii0_rxd_3", "tp1_loc" };
+static const char * const rtd1295_sb2_tp1_loc_tp0_groups[] = { "tp1_data", "tp1_sync", "tp1_valid", "tp1_clk", "tp1_loc" };
+static const char * const rtd1295_sb2_tp1_loc_tp1_groups[] = { "tp1_data", "tp1_sync", "tp1_valid", "tp1_clk", "tp1_loc" };
static const char * const rtd1295_sb2_usb_clock_output_groups[] = { "sensor_cko_1" };
+static const char * const rtd1295_sb2_hif_loc_misc_groups[] = { "hif_loc" };
+static const char * const rtd1295_sb2_hif_loc_nf_groups[] = { "hif_loc" };
+
+
#define RTD1295_FUNC(_name) \
{ \
@@ -661,6 +755,9 @@ static const struct rtd119x_pin_func_desc rtd1295_sb2_pin_functions[] = {
RTD1295_FUNC(tp1_loc_tp0),
RTD1295_FUNC(tp1_loc_tp1),
RTD1295_FUNC(usb_clock_output),
+ RTD1295_FUNC(hif_loc_misc),
+ RTD1295_FUNC(hif_loc_nf),
+ RTD1295_FUNC(scpu_ejtag_loc_cr),
};
#undef RTD1295_FUNC
@@ -759,6 +856,12 @@ static const struct rtd119x_pin_desc rtd1295_sb2_muxes[] = {
RTK_PIN_MUX(usb_id, 0x0c, GENMASK(17, 16),
RTK_PIN_FUNC(0x0 << 16, "gpio"),
RTK_PIN_FUNC(0x2 << 16, "test_loop_dis")),
+ RTK_PIN_MUX(hif_loc, 0x0c, GENMASK(19, 18),
+ RTK_PIN_FUNC(0x1 << 18, "hif_loc_misc"),
+ RTK_PIN_FUNC(0x2 << 18, "hif_loc_nf")),
+ RTK_PIN_MUX(ejtag_scpu_loc, 0x0c, GENMASK(21, 20),
+ RTK_PIN_FUNC(0x1 << 20, "scpu_ejtag_loc_gpio"),
+ RTK_PIN_FUNC(0x2 << 20, "scpu_ejtag_loc_cr")),
RTK_PIN_MUX(sensor_stb_1, 0x0c, GENMASK(23, 22),
RTK_PIN_FUNC(0x0 << 22, "gpio")),
RTK_PIN_MUX(sensor_stb_0, 0x0c, GENMASK(25, 24),
@@ -773,6 +876,18 @@ static const struct rtd119x_pin_desc rtd1295_sb2_muxes[] = {
RTK_PIN_FUNC(0x0 << 30, "gpio"),
RTK_PIN_FUNC(0x1 << 30, "sensor_cko_output")),
+ RTK_PIN_MUX(sf_en, 0x14, GENMASK(0, 0),
+ RTK_PIN_FUNC(0x0 << 0, "gpio"),
+ RTK_PIN_FUNC(0x1 << 0, "spi")),
+ RTK_PIN_MUX(tp0_loc, 0x14, GENMASK(7, 7),
+ RTK_PIN_FUNC(0x0 << 7, "tp0_loc_tp0"),
+ RTK_PIN_FUNC(0x0 << 7, "tp0_loc_tp1"),
+ RTK_PIN_FUNC(0x1 << 7, "tp0_loc_rgmii0_tx")),
+ RTK_PIN_MUX(tp1_loc, 0x14, GENMASK(8, 8),
+ RTK_PIN_FUNC(0x0 << 8, "tp1_loc_tp1"),
+ RTK_PIN_FUNC(0x0 << 8, "tp1_loc_tp0"),
+ RTK_PIN_FUNC(0x1 << 8, "tp1_loc_rgmii0_rx")),
+
RTK_PIN_MUX(rgmii0_txc, 0x6c, GENMASK(1, 0),
RTK_PIN_FUNC(0x0 << 0, "gpio"),
RTK_PIN_FUNC(0x1 << 0, "rgmii")),
@@ -1041,6 +1156,7 @@ enum rtd1295_cr_pins {
RTD1295_PROB_1,
RTD1295_PROB_2,
RTD1295_PROB_3,
+ RTD1295_SDIO_LOC,
};
static const struct pinctrl_pin_desc rtd1295_cr_pins[] = {
@@ -1081,6 +1197,7 @@ static const struct pinctrl_pin_desc rtd1295_cr_pins[] = {
PINCTRL_PIN(RTD1295_PROB_1, "prob_1"),
PINCTRL_PIN(RTD1295_PROB_2, "prob_2"),
PINCTRL_PIN(RTD1295_PROB_3, "prob_3"),
+ PINCTRL_PIN(RTD1295_SDIO_LOC, "sdio_loc"),
};
static const unsigned int rtd1295_nf_cle_pins[] = { RTD1295_NF_CLE };
@@ -1120,6 +1237,8 @@ static const unsigned int rtd1295_prob_0_pins[] = { RTD1295_PROB_0 };
static const unsigned int rtd1295_prob_1_pins[] = { RTD1295_PROB_1 };
static const unsigned int rtd1295_prob_2_pins[] = { RTD1295_PROB_2 };
static const unsigned int rtd1295_prob_3_pins[] = { RTD1295_PROB_3 };
+static const unsigned int rtd1295_sdio_loc_pins[] = { RTD1295_SDIO_LOC };
+
static const struct rtd119x_pin_group_desc rtd1295_cr_pin_groups[] = {
RTD1295_GROUP(nf_cle),
@@ -1159,6 +1278,7 @@ static const struct rtd119x_pin_group_desc rtd1295_cr_pin_groups[] = {
RTD1295_GROUP(prob_1),
RTD1295_GROUP(prob_2),
RTD1295_GROUP(prob_3),
+ RTD1295_GROUP(sdio_loc),
};
static const char * const rtd1295_cr_gpio_groups[] = {
@@ -1180,7 +1300,9 @@ static const char * const rtd1295_cr_pcie_groups[] = { "pcie_clkreq_0", "pcie_cl
static const char * const rtd1295_cr_pll_test_groups[] = { "prob_0", "prob_1", "prob_2", "prob_3" };
static const char * const rtd1295_cr_scpu_ejtag_loc_cr_groups[] = { "mmc_cmd", "mmc_clk", "mmc_wp", "mmc_data_0", "mmc_data_3" };
static const char * const rtd1295_cr_sd_card_groups[] = { "mmc_cmd", "mmc_clk", "mmc_wp", "mmc_cd", "mmc_data_0", "mmc_data_1", "mmc_data_2", "mmc_data_3" };
-static const char * const rtd1295_cr_sdio_groups[] = { "sdio_cmd", "sdio_clk", "sdio_data_0", "sdio_data_1", "sdio_data_2", "sdio_data_3", "mmc_cmd", "mmc_clk", "mmc_data_0", "mmc_data_1", "mmc_data_2", "mmc_data_3" };
+static const char * const rtd1295_cr_sdio_0_groups[] = { "sdio_cmd", "sdio_clk", "sdio_data_0", "sdio_data_1", "sdio_data_2", "sdio_data_3" };
+static const char * const rtd1295_cr_sdio_1_groups[] = { "mmc_cmd", "mmc_clk", "mmc_data_0", "mmc_data_1", "mmc_data_2", "mmc_data_3" };
+
#define RTD1295_FUNC(_name) \
{ \
@@ -1200,7 +1322,8 @@ static const struct rtd119x_pin_func_desc rtd1295_cr_pin_functions[] = {
RTD1295_FUNC(pll_test),
RTD1295_FUNC(scpu_ejtag_loc_cr),
RTD1295_FUNC(sd_card),
- RTD1295_FUNC(sdio),
+ RTD1295_FUNC(sdio_0),
+ RTD1295_FUNC(sdio_1),
};
#undef RTD1295_FUNC
@@ -1277,34 +1400,34 @@ static const struct rtd119x_pin_desc rtd1295_cr_muxes[] = {
RTK_PIN_MUX(sdio_cmd, 0x04, GENMASK(1, 0),
RTK_PIN_FUNC(0x0 << 0, "gpio"),
- RTK_PIN_FUNC(0x1 << 0, "sdio")),
+ RTK_PIN_FUNC(0x1 << 0, "sdio_0")),
RTK_PIN_MUX(sdio_clk, 0x04, GENMASK(3, 2),
RTK_PIN_FUNC(0x0 << 2, "gpio"),
- RTK_PIN_FUNC(0x1 << 2, "sdio")),
+ RTK_PIN_FUNC(0x1 << 2, "sdio_0")),
RTK_PIN_MUX(sdio_data_0, 0x04, GENMASK(5, 4),
RTK_PIN_FUNC(0x0 << 4, "gpio"),
- RTK_PIN_FUNC(0x1 << 4, "sdio")),
+ RTK_PIN_FUNC(0x1 << 4, "sdio_0")),
RTK_PIN_MUX(sdio_data_1, 0x04, GENMASK(7, 6),
RTK_PIN_FUNC(0x0 << 6, "gpio"),
- RTK_PIN_FUNC(0x1 << 6, "sdio")),
+ RTK_PIN_FUNC(0x1 << 6, "sdio_0")),
RTK_PIN_MUX(sdio_data_2, 0x04, GENMASK(9, 8),
RTK_PIN_FUNC(0x0 << 8, "gpio"),
- RTK_PIN_FUNC(0x1 << 8, "sdio")),
+ RTK_PIN_FUNC(0x1 << 8, "sdio_0")),
RTK_PIN_MUX(sdio_data_3, 0x04, GENMASK(11, 10),
RTK_PIN_FUNC(0x0 << 10, "gpio"),
- RTK_PIN_FUNC(0x1 << 10, "sdio")),
+ RTK_PIN_FUNC(0x1 << 10, "sdio_0")),
RTK_PIN_MUX(emmc_dd_sb, 0x04, GENMASK(13, 12),
RTK_PIN_FUNC(0x0 << 12, "gpio"),
RTK_PIN_FUNC(0x2 << 12, "emmc")),
RTK_PIN_MUX(mmc_cmd, 0x04, GENMASK(17, 16),
RTK_PIN_FUNC(0x0 << 16, "gpio"),
RTK_PIN_FUNC(0x1 << 16, "sd_card"),
- RTK_PIN_FUNC(0x2 << 16, "sdio"),
+ RTK_PIN_FUNC(0x2 << 16, "sdio_1"),
RTK_PIN_FUNC(0x3 << 16, "scpu_ejtag_loc_cr")),
RTK_PIN_MUX(mmc_clk, 0x04, GENMASK(19, 18),
RTK_PIN_FUNC(0x0 << 18, "gpio"),
RTK_PIN_FUNC(0x1 << 18, "sd_card"),
- RTK_PIN_FUNC(0x2 << 18, "sdio"),
+ RTK_PIN_FUNC(0x2 << 18, "sdio_1"),
RTK_PIN_FUNC(0x3 << 18, "scpu_ejtag_loc_cr")),
RTK_PIN_MUX(mmc_wp, 0x04, GENMASK(21, 20),
RTK_PIN_FUNC(0x0 << 20, "gpio"),
@@ -1316,22 +1439,25 @@ static const struct rtd119x_pin_desc rtd1295_cr_muxes[] = {
RTK_PIN_MUX(mmc_data_0, 0x04, GENMASK(25, 24),
RTK_PIN_FUNC(0x0 << 24, "gpio"),
RTK_PIN_FUNC(0x1 << 24, "sd_card"),
- RTK_PIN_FUNC(0x2 << 24, "sdio"),
+ RTK_PIN_FUNC(0x2 << 24, "sdio_1"),
RTK_PIN_FUNC(0x3 << 24, "scpu_ejtag_loc_cr")),
RTK_PIN_MUX(mmc_data_1, 0x04, GENMASK(27, 26),
RTK_PIN_FUNC(0x0 << 26, "gpio"),
RTK_PIN_FUNC(0x1 << 26, "sd_card"),
- RTK_PIN_FUNC(0x2 << 26, "sdio")),
+ RTK_PIN_FUNC(0x2 << 26, "sdio_1")),
RTK_PIN_MUX(mmc_data_2, 0x04, GENMASK(29, 28),
RTK_PIN_FUNC(0x0 << 28, "gpio"),
RTK_PIN_FUNC(0x1 << 28, "sd_card"),
- RTK_PIN_FUNC(0x2 << 28, "sdio")),
+ RTK_PIN_FUNC(0x2 << 28, "sdio_1")),
RTK_PIN_MUX(mmc_data_3, 0x04, GENMASK(31, 30),
RTK_PIN_FUNC(0x0 << 30, "gpio"),
RTK_PIN_FUNC(0x1 << 30, "sd_card"),
- RTK_PIN_FUNC(0x2 << 30, "sdio"),
+ RTK_PIN_FUNC(0x2 << 30, "sdio_1"),
RTK_PIN_FUNC(0x3 << 30, "scpu_ejtag_loc_cr")),
+ RTK_PIN_MUX(sdio_loc, 0x1c, GENMASK(1, 0),
+ RTK_PIN_FUNC(0x0 << 0, "sdio_0"),
+ RTK_PIN_FUNC(0x1 << 0, "sdio_1")),
RTK_PIN_MUX(pcie_clkreq_0, 0x1c, GENMASK(3, 2),
RTK_PIN_FUNC(0x0 << 2, "gpio"),
RTK_PIN_FUNC(0x1 << 2, "pcie")),
--
2.26.2
^ permalink raw reply related
* [PATCH 7/7] pinctrl: realtek: DHC: Add suspend/resume callback function.
From: TY Chang @ 2020-05-14 9:21 UTC (permalink / raw)
To: linux-realtek-soc, afaerber
Cc: linus.walleij, linux-gpio, robh+dt, devicetree, linux-kernel
In-Reply-To: <20200514092125.6875-1-tychang@realtek.com>
Add suspend and resume callback function for
Realtek DHC SoC pinctrl driver.
Signed-off-by: TY Chang <tychang@realtek.com>
---
drivers/pinctrl/realtek/pinctrl-rtd.c | 39 +++++++++++++
drivers/pinctrl/realtek/pinctrl-rtd1195.h | 33 +++++++++++
drivers/pinctrl/realtek/pinctrl-rtd1295.h | 67 ++++++++++++++++++++++-
3 files changed, 138 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.c b/drivers/pinctrl/realtek/pinctrl-rtd.c
index 4d9740f875ff..f327453b01df 100644
--- a/drivers/pinctrl/realtek/pinctrl-rtd.c
+++ b/drivers/pinctrl/realtek/pinctrl-rtd.c
@@ -57,6 +57,12 @@ struct rtd_pin_desc {
const struct rtd_pin_mux_desc *functions;
};
+struct rtd_pin_reg_list {
+ unsigned int reg_offset;
+ unsigned int val;
+};
+
+
#define RTK_PIN_CONFIG(_name, _reg_off, _base_bit, _pud_en_off, \
_pud_sel_off, _curr_off, _smt_off, _curr_type) \
{ \
@@ -98,6 +104,8 @@ struct rtd_pinctrl_desc {
unsigned int num_muxes;
const struct rtd_pin_config_desc *configs;
unsigned int num_configs;
+ struct rtd_pin_reg_list *lists;
+ unsigned int num_regs;
};
#define PCONF_UNSUPP 0xffffffff
@@ -549,8 +557,39 @@ static int rtd_pinctrl_probe(struct platform_device *pdev)
return 0;
}
+static int rtd_pinctrl_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct rtd_pinctrl *data = platform_get_drvdata(pdev);
+ struct rtd_pin_reg_list *list;
+ int i;
+
+ for (i = 0; i < data->info->num_regs; i++) {
+ list = &data->info->lists[i];
+ list->val = readl(data->base + list->reg_offset);
+ }
+
+ return 0;
+}
+
+static int rtd_pinctrl_resume(struct platform_device *pdev)
+{
+ struct rtd_pinctrl *data = platform_get_drvdata(pdev);
+ const struct rtd_pin_reg_list *list;
+ int i;
+
+ for (i = 0; i < data->info->num_regs; i++) {
+ list = &data->info->lists[i];
+ writel(list->val, data->base + list->reg_offset);
+ }
+
+ return 0;
+}
+
+
static struct platform_driver rtd_pinctrl_driver = {
.probe = rtd_pinctrl_probe,
+ .suspend = rtd_pinctrl_suspend,
+ .resume = rtd_pinctrl_resume,
.driver = {
.name = "rtd-pinctrl",
.of_match_table = rtd_pinctrl_dt_ids,
diff --git a/drivers/pinctrl/realtek/pinctrl-rtd1195.h b/drivers/pinctrl/realtek/pinctrl-rtd1195.h
index 74139345083c..c9d6e7894d66 100644
--- a/drivers/pinctrl/realtek/pinctrl-rtd1195.h
+++ b/drivers/pinctrl/realtek/pinctrl-rtd1195.h
@@ -358,6 +358,16 @@ static const struct rtd_pin_config_desc rtd1195_iso_configs[] = {
};
+static struct rtd_pin_reg_list rtd1195_iso_reg_lists[] = {
+ {.reg_offset = 0x0},
+ {.reg_offset = 0x4},
+ {.reg_offset = 0x8},
+ {.reg_offset = 0xc},
+ {.reg_offset = 0x10},
+ {.reg_offset = 0x14},
+};
+
+
static const struct rtd_pinctrl_desc rtd1195_iso_pinctrl_desc = {
.pins = rtd1195_iso_pins,
.num_pins = ARRAY_SIZE(rtd1195_iso_pins),
@@ -369,6 +379,8 @@ static const struct rtd_pinctrl_desc rtd1195_iso_pinctrl_desc = {
.num_muxes = ARRAY_SIZE(rtd1195_iso_muxes),
.configs = rtd1195_iso_configs,
.num_configs = ARRAY_SIZE(rtd1195_iso_configs),
+ .lists = rtd1195_iso_reg_lists,
+ .num_regs = ARRAY_SIZE(rtd1195_iso_reg_lists),
};
/* CRT */
@@ -1110,6 +1122,25 @@ static const struct rtd_pin_config_desc rtd1195_crt_configs[] = {
RTK_PIN_CONFIG(sensor_cko_1, 0x9c, 28, 1, 0, 2, 3, PADDRI_2_4),
};
+static struct rtd_pin_reg_list rtd1195_crt_reg_lists[] = {
+ {.reg_offset = 0x60},
+ {.reg_offset = 0x64},
+ {.reg_offset = 0x68},
+ {.reg_offset = 0x6c},
+ {.reg_offset = 0x70},
+ {.reg_offset = 0x74},
+ {.reg_offset = 0x78},
+ {.reg_offset = 0x7c},
+ {.reg_offset = 0x80},
+ {.reg_offset = 0x84},
+ {.reg_offset = 0x88},
+ {.reg_offset = 0x8c},
+ {.reg_offset = 0x90},
+ {.reg_offset = 0x94},
+ {.reg_offset = 0x98},
+ {.reg_offset = 0x9c},
+};
+
static const struct rtd_pinctrl_desc rtd1195_crt_pinctrl_desc = {
.pins = rtd1195_crt_pins,
@@ -1122,6 +1153,8 @@ static const struct rtd_pinctrl_desc rtd1195_crt_pinctrl_desc = {
.num_muxes = ARRAY_SIZE(rtd1195_crt_muxes),
.configs = rtd1195_crt_configs,
.num_configs = ARRAY_SIZE(rtd1195_crt_configs),
+ .lists = rtd1195_crt_reg_lists,
+ .num_regs = ARRAY_SIZE(rtd1195_crt_reg_lists),
};
#endif
diff --git a/drivers/pinctrl/realtek/pinctrl-rtd1295.h b/drivers/pinctrl/realtek/pinctrl-rtd1295.h
index 14d46baa97d8..7cd12f66e02f 100644
--- a/drivers/pinctrl/realtek/pinctrl-rtd1295.h
+++ b/drivers/pinctrl/realtek/pinctrl-rtd1295.h
@@ -525,7 +525,17 @@ static const struct rtd_pin_config_desc rtd1295_iso_configs[] = {
RTK_PIN_CONFIG(iso_gpio_34, 0x20, 4, 1, 0, 2, 3, 2),
};
-
+static struct rtd_pin_reg_list rtd1295_iso_reg_lists[] = {
+ {.reg_offset = 0x0},
+ {.reg_offset = 0x4},
+ {.reg_offset = 0x8},
+ {.reg_offset = 0xc},
+ {.reg_offset = 0x10},
+ {.reg_offset = 0x14},
+ {.reg_offset = 0x18},
+ {.reg_offset = 0x1c},
+ {.reg_offset = 0x20},
+};
static const struct rtd_pinctrl_desc rtd1295_iso_pinctrl_desc = {
.pins = rtd1295_iso_pins,
@@ -538,6 +548,8 @@ static const struct rtd_pinctrl_desc rtd1295_iso_pinctrl_desc = {
.num_muxes = ARRAY_SIZE(rtd1295_iso_muxes),
.configs = rtd1295_iso_configs,
.num_configs = ARRAY_SIZE(rtd1295_iso_configs),
+ .lists = rtd1295_iso_reg_lists,
+ .num_regs = ARRAY_SIZE(rtd1295_iso_reg_lists),
};
/* SB2 */
@@ -1225,6 +1237,28 @@ static const struct rtd_pin_config_desc rtd1295_sb2_configs[] = {
RTK_PIN_CONFIG(rgmii1_rxd_3, 0x78, 12, 1, 0, 2, 3, PADDRI_4_8),
};
+static struct rtd_pin_reg_list rtd1295_sb2_reg_lists[] = {
+ {.reg_offset = 0x8},
+ {.reg_offset = 0xc},
+ {.reg_offset = 0x10},
+ {.reg_offset = 0x14},
+ {.reg_offset = 0x28},
+ {.reg_offset = 0x14},
+ {.reg_offset = 0x2c},
+ {.reg_offset = 0x30},
+ {.reg_offset = 0x34},
+ {.reg_offset = 0x38},
+ {.reg_offset = 0x3c},
+ {.reg_offset = 0x60},
+ {.reg_offset = 0x64},
+ {.reg_offset = 0x68},
+ {.reg_offset = 0x6c},
+ {.reg_offset = 0x70},
+ {.reg_offset = 0x74},
+ {.reg_offset = 0x78},
+ {.reg_offset = 0x7c},
+};
+
static const struct rtd_pinctrl_desc rtd1295_sb2_pinctrl_desc = {
.pins = rtd1295_sb2_pins,
@@ -1237,6 +1271,8 @@ static const struct rtd_pinctrl_desc rtd1295_sb2_pinctrl_desc = {
.num_muxes = ARRAY_SIZE(rtd1295_sb2_muxes),
.configs = rtd1295_sb2_configs,
.num_configs = ARRAY_SIZE(rtd1295_sb2_configs),
+ .lists = rtd1295_sb2_reg_lists,
+ .num_regs = ARRAY_SIZE(rtd1295_sb2_reg_lists),
};
/* Disp */
@@ -1373,6 +1409,12 @@ static const struct rtd_pin_config_desc rtd1295_disp_configs[] = {
RTK_PIN_CONFIG(ao_sd_3, 0x4, 24, 1, 0, 2, 3, PADDRI_2_4),
};
+static struct rtd_pin_reg_list rtd1295_disp_reg_lists[] = {
+ {.reg_offset = 0x0},
+ {.reg_offset = 0x4},
+ {.reg_offset = 0x8},
+};
+
static const struct rtd_pinctrl_desc rtd1295_disp_pinctrl_desc = {
.pins = rtd1295_disp_pins,
@@ -1385,6 +1427,8 @@ static const struct rtd_pinctrl_desc rtd1295_disp_pinctrl_desc = {
.num_muxes = ARRAY_SIZE(rtd1295_disp_muxes),
.configs = rtd1295_disp_configs,
.num_configs = ARRAY_SIZE(rtd1295_disp_configs),
+ .lists = rtd1295_disp_reg_lists,
+ .num_regs = ARRAY_SIZE(rtd1295_disp_reg_lists),
};
/* CR */
@@ -1825,6 +1869,25 @@ static const struct rtd_pin_config_desc rtd1295_cr_configs[] = {
RTK_PIN_CONFIG(prob_3, 0x18, 24, 1, 0, 2, 3, PADDRI_4_8),
};
+static struct rtd_pin_reg_list rtd1295_cr_reg_lists[] = {
+ {.reg_offset = 0x0},
+ {.reg_offset = 0x4},
+ {.reg_offset = 0x8},
+ {.reg_offset = 0xc},
+ {.reg_offset = 0x10},
+ {.reg_offset = 0x14},
+ {.reg_offset = 0x18},
+ {.reg_offset = 0x1c},
+ {.reg_offset = 0x20},
+ {.reg_offset = 0x24},
+ {.reg_offset = 0x28},
+ {.reg_offset = 0x2c},
+ {.reg_offset = 0x30},
+ {.reg_offset = 0x34},
+ {.reg_offset = 0x38},
+ {.reg_offset = 0x3c},
+ {.reg_offset = 0x40},
+};
static const struct rtd_pinctrl_desc rtd1295_cr_pinctrl_desc = {
.pins = rtd1295_cr_pins,
@@ -1837,6 +1900,8 @@ static const struct rtd_pinctrl_desc rtd1295_cr_pinctrl_desc = {
.num_muxes = ARRAY_SIZE(rtd1295_cr_muxes),
.configs = rtd1295_cr_configs,
.num_configs = ARRAY_SIZE(rtd1295_cr_configs),
+ .lists = rtd1295_cr_reg_lists,
+ .num_regs = ARRAY_SIZE(rtd1295_cr_reg_lists),
};
#endif
--
2.26.2
^ permalink raw reply related
* [PATCH 5/7] pinctrl: realtek: DHC: Fix pinctrl driver coding style according to checkpatch.pl.
From: TY Chang @ 2020-05-14 9:21 UTC (permalink / raw)
To: linux-realtek-soc, afaerber
Cc: linus.walleij, linux-gpio, robh+dt, devicetree, linux-kernel
In-Reply-To: <20200514092125.6875-1-tychang@realtek.com>
Fix Realtek DHC SoC pinctrl driver coding style.
Signed-off-by: TY Chang <tychang@realtek.com>
---
drivers/pinctrl/pinctrl-rtd1195.h | 131 +++++++---
drivers/pinctrl/pinctrl-rtd119x.c | 124 +++++----
drivers/pinctrl/pinctrl-rtd1295.h | 407 ++++++++++++++++++++++--------
3 files changed, 466 insertions(+), 196 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rtd1195.h b/drivers/pinctrl/pinctrl-rtd1195.h
index 9f3471d02221..f0dd91f416e8 100644
--- a/drivers/pinctrl/pinctrl-rtd1195.h
+++ b/drivers/pinctrl/pinctrl-rtd1195.h
@@ -1,3 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause */
+
+/*
+ * Realtek RTD1195 pin controller driver
+ *
+ * Copyright (c) 2019 Realtek Semiconductor Corp.
+ */
+
#ifndef PINCTRL_RTD1195_H
#define PINCTRL_RTD1195_H
@@ -76,15 +84,20 @@ static const unsigned int rtd1195_ur1_cts_n_pins[] = { RTD1195_ISO_UR1_CTS_N };
static const unsigned int rtd1195_ur1_rts_n_pins[] = { RTD1195_ISO_UR1_RTS_N };
static const unsigned int rtd1195_i2c_scl_0_pins[] = { RTD1195_ISO_I2C_SCL_0 };
static const unsigned int rtd1195_i2c_sda_0_pins[] = { RTD1195_ISO_I2C_SDA_0 };
-static const unsigned int rtd1195_etn_led_link_pins[] = { RTD1195_ISO_ETN_LED_LINK };
-static const unsigned int rtd1195_etn_led_rxtx_pins[] = { RTD1195_ISO_ETN_LED_RXTX };
+static const unsigned int rtd1195_etn_led_link_pins[] = {
+ RTD1195_ISO_ETN_LED_LINK };
+static const unsigned int rtd1195_etn_led_rxtx_pins[] = {
+ RTD1195_ISO_ETN_LED_RXTX };
static const unsigned int rtd1195_i2c_scl_6_pins[] = { RTD1195_ISO_I2C_SCL_6 };
static const unsigned int rtd1195_i2c_sda_6_pins[] = { RTD1195_ISO_I2C_SDA_6 };
static const unsigned int rtd1195_ai_loc_pins[] = { RTD1195_ISO_AI_LOC };
-static const unsigned int rtd1195_ejtag_avcpu_loc_pins[] = { RTD1195_ISO_EJTAG_AVCPU_LOC };
+static const unsigned int rtd1195_ejtag_avcpu_loc_pins[] = {
+ RTD1195_ISO_EJTAG_AVCPU_LOC };
static const unsigned int rtd1195_ur1_loc_pins[] = { RTD1195_ISO_UR1_LOC };
-static const unsigned int rtd1195_pwm_01_open_drain_pins[] = { RTD1195_ISO_PWM_01_OPEN_DRAIN };
-static const unsigned int rtd1195_pwm_23_open_drain_pins[] = { RTD1195_ISO_PWM_23_OPEN_DRAIN };
+static const unsigned int rtd1195_pwm_01_open_drain_pins[] = {
+ RTD1195_ISO_PWM_01_OPEN_DRAIN };
+static const unsigned int rtd1195_pwm_23_open_drain_pins[] = {
+ RTD1195_ISO_PWM_23_OPEN_DRAIN };
#define RTD1195_GROUP(_name) \
@@ -148,26 +161,46 @@ static const char * const rtd1195_iso_avcpu_ejtag_misc_loc_groups[] = {
"ejtag_avcpu_loc"
};
-
-static const char * const rtd1195_iso_etn_led_groups[] = { "etn_led_link", "etn_led_rxtx" };
-static const char * const rtd1195_iso_i2c0_groups[] = { "i2c_scl_0", "i2c_sda_0" };
+static const char * const rtd1195_iso_etn_led_groups[] = {
+ "etn_led_link", "etn_led_rxtx"
+};
+static const char * const rtd1195_iso_i2c0_groups[] = {
+ "i2c_scl_0", "i2c_sda_0"
+};
static const char * const rtd1195_iso_i2c2_groups[] = { "vfd_d" };
static const char * const rtd1195_iso_i2c3_groups[] = { "ir_tx" };
-static const char * const rtd1195_iso_i2c6_groups[] = { "i2c_scl_6", "i2c_sda_6" };
+static const char * const rtd1195_iso_i2c6_groups[] = {
+ "i2c_scl_6", "i2c_sda_6"
+};
static const char * const rtd1195_iso_ir_rx_groups[] = { "ir_rx" };
static const char * const rtd1195_iso_ir_tx_groups[] = { "ir_tx" };
static const char * const rtd1195_iso_pwm_groups[] = {
"ur0_rx", "ur0_tx", "ur1_rx", "ur1_tx", "etn_led_link", "etn_led_rxtx"
};
-static const char * const rtd1195_iso_standby_dbg_groups[] = { "ir_rx", "usb0", "usb1" };
+static const char * const rtd1195_iso_standby_dbg_groups[] = {
+ "ir_rx", "usb0", "usb1"
+};
static const char * const rtd1195_iso_uart0_groups[] = { "ur0_rx", "ur0_tx" };
-static const char * const rtd1195_iso_uart1_groups[] = { "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n", "ur1_loc" };
+static const char * const rtd1195_iso_uart1_groups[] = {
+ "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n", "ur1_loc"
+};
static const char * const rtd1195_iso_ur1_misc_groups[] = { "ur1_loc" };
-static const char * const rtd1195_iso_vfd_groups[] = { "vfd_cs_n", "vfd_clk", "vfd_d" };
-static const char * const rtd1195_iso_pwm_01_normal_groups[] = { "pwm_01_open_drain" };
-static const char * const rtd1195_iso_pwm_23_normal_groups[] = { "pwm_23_open_drain" };
-static const char * const rtd1195_iso_pwm_01_open_drain_groups[] = { "pwm_01_open_drain" };
-static const char * const rtd1195_iso_pwm_23_open_drain_groups[] = { "pwm_23_open_drain" };
+static const char * const rtd1195_iso_vfd_groups[] = {
+ "vfd_cs_n", "vfd_clk", "vfd_d"
+};
+static const char * const rtd1195_iso_pwm_01_normal_groups[] = {
+ "pwm_01_open_drain"
+};
+static const char * const rtd1195_iso_pwm_23_normal_groups[] = {
+ "pwm_23_open_drain"
+};
+static const char * const rtd1195_iso_pwm_01_open_drain_groups[] = {
+ "pwm_01_open_drain"
+};
+static const char * const rtd1195_iso_pwm_23_open_drain_groups[] = {
+ "pwm_23_open_drain"
+
+};
@@ -527,12 +560,17 @@ static const unsigned int rtd1195_i2c_scl_1_pins[] = { RTD1195_I2C_SCL_1 };
static const unsigned int rtd1195_i2c_sda_1_pins[] = { RTD1195_I2C_SDA_1 };
static const unsigned int rtd1195_i2c_scl_4_pins[] = { RTD1195_I2C_SCL_4 };
static const unsigned int rtd1195_i2c_sda_4_pins[] = { RTD1195_I2C_SDA_4 };
-static const unsigned int rtd1195_sensor_cko_0_pins[] = { RTD1195_SENSOR_CKO_0 };
-static const unsigned int rtd1195_sensor_cko_1_pins[] = { RTD1195_SENSOR_CKO_1 };
+static const unsigned int rtd1195_sensor_cko_0_pins[] = {
+ RTD1195_SENSOR_CKO_0 };
+static const unsigned int rtd1195_sensor_cko_1_pins[] = {
+ RTD1195_SENSOR_CKO_1 };
static const unsigned int rtd1195_sensor_rst_pins[] = { RTD1195_SENSOR_RST };
-static const unsigned int rtd1195_sensor_stb_0_pins[] = { RTD1195_SENSOR_STB_0 };
-static const unsigned int rtd1195_sensor_stb_1_pins[] = { RTD1195_SENSOR_STB_1 };
-static const unsigned int rtd1195_ejtag_scpu_loc_pins[] = { RTD1195_EJTAG_SCPU_LOC };
+static const unsigned int rtd1195_sensor_stb_0_pins[] = {
+ RTD1195_SENSOR_STB_0 };
+static const unsigned int rtd1195_sensor_stb_1_pins[] = {
+ RTD1195_SENSOR_STB_1 };
+static const unsigned int rtd1195_ejtag_scpu_loc_pins[] = {
+ RTD1195_EJTAG_SCPU_LOC };
static const unsigned int rtd1195_hif_loc_pins[] = { RTD1195_HI_LOC };
static const unsigned int rtd1195_ao_loc_pins[] = { RTD1195_AO_LOC };
@@ -617,11 +655,14 @@ static const struct rtd119x_pin_group_desc rtd1195_crt_pin_groups[] = {
static const char * const rtd1195_crt_gpio_groups[] = {
"gpio_0", "gpio_1", "gpio_2", "gpio_3",
"gpio_4", "gpio_5", "gpio_6", "gpio_7", "gpio_8",
- "nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3", "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7",
- "nf_rdy", "nf_rd_n", "nf_wr_n", "nf_ale", "nf_cle", "nf_ce_n_0", "nf_ce_n_1",
+ "nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3",
+ "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7",
+ "nf_rdy", "nf_rd_n", "nf_wr_n", "nf_ale",
+ "nf_cle", "nf_ce_n_0", "nf_ce_n_1",
"mmc_data_0", "mmc_data_1", "mmc_data_2", "mmc_data_3",
"mmc_clk", "mmc_cmd", "mmc_wp", "mmc_cd",
- "sdio_clk", "sdio_data_0", "sdio_data_1", "sdio_data_2", "sdio_data_3", "sdio_cmd",
+ "sdio_clk", "sdio_data_0", "sdio_data_1",
+ "sdio_data_2", "sdio_data_3", "sdio_cmd",
"i2c_scl_5", "i2c_sda_5",
"tp1_data", "tp1_clk", "tp1_valid", "tp1_sync",
"tp0_data", "tp0_clk", "tp0_valid", "tp0_sync",
@@ -649,7 +690,8 @@ static const char * const rtd1195_crt_avcpu_ejtag_misc_groups[] = {
};
static const char * const rtd1195_crt_cpu_loop_groups[] = { "usb_id" };
static const char * const rtd1195_crt_emmc_groups[] = {
- "nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3", "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7",
+ "nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3",
+ "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7",
"nf_rdy", "nf_rd_n", "nf_wr_n", "nf_ale", "nf_cle",
};
static const char * const rtd1195_crt_gspi_groups[] = {
@@ -664,30 +706,45 @@ static const char * const rtd1195_crt_hif_misc_groups[] = {
};
-static const char * const rtd1195_crt_i2c1_groups[] = { "i2c_scl_1", "i2c_sda_1" };
-static const char * const rtd1195_crt_i2c2_groups[] = { "tp1_sync", "tp1_clk" };
-static const char * const rtd1195_crt_i2c3_groups[] = { "tp1_data", "tp1_valid" };
-static const char * const rtd1195_crt_i2c4_groups[] = { "i2c_scl_4", "i2c_sda_4" };
-static const char * const rtd1195_crt_i2c5_groups[] = { "i2c_scl_5", "i2c_sda_5" };
+static const char * const rtd1195_crt_i2c1_groups[] = {
+ "i2c_scl_1", "i2c_sda_1"
+};
+static const char * const rtd1195_crt_i2c2_groups[] = {
+ "tp1_sync", "tp1_clk"
+};
+static const char * const rtd1195_crt_i2c3_groups[] = {
+ "tp1_data", "tp1_valid" };
+static const char * const rtd1195_crt_i2c4_groups[] = {
+ "i2c_scl_4", "i2c_sda_4"
+};
+static const char * const rtd1195_crt_i2c5_groups[] = {
+ "i2c_scl_5", "i2c_sda_5"
+};
static const char * const rtd1195_crt_mmc_groups[] = {
"mmc_data_0", "mmc_data_1", "mmc_data_2", "mmc_data_3",
"mmc_clk", "mmc_cmd", "mmc_wp", "mmc_cd",
};
static const char * const rtd1195_crt_nand_groups[] = {
- "nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3", "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7",
- "nf_rdy", "nf_rd_n", "nf_wr_n", "nf_ale", "nf_cle", "nf_ce_n_0", "nf_ce_n_1",
+ "nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3",
+ "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7",
+ "nf_rdy", "nf_rd_n", "nf_wr_n", "nf_ale",
+ "nf_cle", "nf_ce_n_0", "nf_ce_n_1",
};
static const char * const rtd1195_crt_scpu_ejtag_gpio_groups[] = {
"gpio_4", "gpio_5", "gpio_6", "gpio_7", "gpio_8", "ejtag_scpu_loc"
};
static const char * const rtd1195_crt_scpu_ejtag_cr_groups[] = {
- "mmc_data_0", "mmc_data_3", "mmc_clk", "mmc_cmd", "mmc_wp", "ejtag_scpu_loc"
+ "mmc_data_0", "mmc_data_3", "mmc_clk",
+ "mmc_cmd", "mmc_wp", "ejtag_scpu_loc"
};
static const char * const rtd1195_crt_sdio_groups[] = {
- "sdio_clk", "sdio_data_0", "sdio_data_1", "sdio_data_2", "sdio_data_3", "sdio_cmd",
+ "sdio_clk", "sdio_data_0", "sdio_data_1",
+ "sdio_data_2", "sdio_data_3", "sdio_cmd",
+};
+static const char * const rtd1195_crt_sensor_groups[] = {
+ "sensor_cko_0", "sensor_cko_1"
};
-static const char * const rtd1195_crt_sensor_groups[] = { "sensor_cko_0", "sensor_cko_1" };
static const char * const rtd1195_crt_spdif_groups[] = { "spdif" };
static const char * const rtd1195_crt_tp0_groups[] = {
"tp0_data", "tp0_clk", "tp0_valid", "tp0_sync",
@@ -695,7 +752,9 @@ static const char * const rtd1195_crt_tp0_groups[] = {
static const char * const rtd1195_crt_tp1_groups[] = {
"tp1_data", "tp1_clk", "tp1_valid", "tp1_sync",
};
-static const char * const rtd1195_crt_uart1_groups[] = { "gpio_0", "gpio_1", "gpio_2", "gpio_3" };
+static const char * const rtd1195_crt_uart1_groups[] = {
+ "gpio_0", "gpio_1", "gpio_2", "gpio_3"
+};
static const char * const rtd1195_crt_usb_groups[] = { "sensor_cko_1" };
#define RTD1195_FUNC(_name) \
diff --git a/drivers/pinctrl/pinctrl-rtd119x.c b/drivers/pinctrl/pinctrl-rtd119x.c
index 52b16d610e13..bda0d1328eb8 100644
--- a/drivers/pinctrl/pinctrl-rtd119x.c
+++ b/drivers/pinctrl/pinctrl-rtd119x.c
@@ -1,9 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
+
/*
- * Copyright (c) 2017 Andreas Färber
+ * Realtek DHC pin controller driver
*
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (c) 2019 Realtek Semiconductor Corp.
*/
+
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/module.h>
@@ -120,7 +123,7 @@ static int rtd119x_pinctrl_get_groups_count(struct pinctrl_dev *pcdev)
}
static const char *rtd119x_pinctrl_get_group_name(struct pinctrl_dev *pcdev,
- unsigned selector)
+ unsigned int selector)
{
struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
@@ -128,7 +131,8 @@ static const char *rtd119x_pinctrl_get_group_name(struct pinctrl_dev *pcdev,
}
static int rtd119x_pinctrl_get_group_pins(struct pinctrl_dev *pcdev,
- unsigned selector, const unsigned **pins, unsigned *num_pins)
+ unsigned int selector, const unsigned int **pins,
+ unsigned int *num_pins)
{
struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
@@ -154,7 +158,7 @@ static int rtd119x_pinctrl_get_functions_count(struct pinctrl_dev *pcdev)
}
static const char *rtd119x_pinctrl_get_function_name(struct pinctrl_dev *pcdev,
- unsigned selector)
+ unsigned int selector)
{
struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
@@ -162,8 +166,8 @@ static const char *rtd119x_pinctrl_get_function_name(struct pinctrl_dev *pcdev,
}
static int rtd119x_pinctrl_get_function_groups(struct pinctrl_dev *pcdev,
- unsigned selector, const char * const **groups,
- unsigned * const num_groups)
+ unsigned int selector, const char * const **groups,
+ unsigned int * const num_groups)
{
struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
@@ -173,7 +177,8 @@ static int rtd119x_pinctrl_get_function_groups(struct pinctrl_dev *pcdev,
return 0;
}
-static const struct pinctrl_pin_desc *rtd119x_pinctrl_get_pin_by_number(struct rtd119x_pinctrl *data, int number)
+static const struct pinctrl_pin_desc *rtd119x_pinctrl_get_pin_by_number(
+ struct rtd119x_pinctrl *data, int number)
{
int i;
@@ -185,7 +190,8 @@ static const struct pinctrl_pin_desc *rtd119x_pinctrl_get_pin_by_number(struct r
return NULL;
}
-static const struct rtd119x_pin_desc *rtd119x_pinctrl_find_mux(struct rtd119x_pinctrl *data, const char *name)
+static const struct rtd119x_pin_desc *rtd119x_pinctrl_find_mux(
+ struct rtd119x_pinctrl *data, const char *name)
{
int i;
@@ -197,7 +203,8 @@ static const struct rtd119x_pin_desc *rtd119x_pinctrl_find_mux(struct rtd119x_pi
return NULL;
}
-static const struct rtd119x_pin_config_desc *rtd119x_pinctrl_find_config(struct rtd119x_pinctrl *data, const char *name)
+static const struct rtd119x_pin_config_desc *rtd119x_pinctrl_find_config(
+ struct rtd119x_pinctrl *data, const char *name)
{
int i;
@@ -231,7 +238,8 @@ static int rtd119x_pinctrl_set_one_mux(struct pinctrl_dev *pcdev,
return -ENOTSUPP;
if (!mux->functions) {
- dev_err(pcdev->dev, "No functions available for pin %s\n", pin_name);
+ dev_err(pcdev->dev,
+ "No functions available for pin %s\n", pin_name);
return -ENOTSUPP;
}
@@ -246,12 +254,13 @@ static int rtd119x_pinctrl_set_one_mux(struct pinctrl_dev *pcdev,
return 0;
}
- dev_err(pcdev->dev, "No function %s available for pin %s\n", func_name, pin_name);
+ dev_err(pcdev->dev, "No function %s available for pin %s\n",
+ func_name, pin_name);
return -EINVAL;
}
static int rtd119x_pinctrl_set_mux(struct pinctrl_dev *pcdev,
- unsigned function, unsigned group)
+ unsigned int function, unsigned int group)
{
struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
const unsigned int *pins;
@@ -265,7 +274,8 @@ static int rtd119x_pinctrl_set_mux(struct pinctrl_dev *pcdev,
ret = rtd119x_pinctrl_get_group_pins(pcdev, group, &pins, &num_pins);
if (ret) {
- dev_err(pcdev->dev, "Getting pins for group %s failed\n", group_name);
+ dev_err(pcdev->dev, "Getting pins for group %s failed\n",
+ group_name);
return ret;
}
@@ -279,7 +289,7 @@ static int rtd119x_pinctrl_set_mux(struct pinctrl_dev *pcdev,
}
static int rtd119x_pinctrl_gpio_request_enable(struct pinctrl_dev *pcdev,
- struct pinctrl_gpio_range *range, unsigned offset)
+ struct pinctrl_gpio_range *range, unsigned int offset)
{
return rtd119x_pinctrl_set_one_mux(pcdev, offset, "gpio");
}
@@ -292,10 +302,9 @@ static const struct pinmux_ops rtd119x_pinmux_ops = {
.gpio_request_enable = rtd119x_pinctrl_gpio_request_enable,
};
-
static int rtd119x_pconf_parse_conf(struct rtd119x_pinctrl *data,
- const struct rtd119x_pin_config_desc *config_desc, enum pin_config_param param,
- enum pin_config_param arg)
+ const struct rtd119x_pin_config_desc *config_desc,
+ enum pin_config_param param, enum pin_config_param arg)
{
u8 set_val = 0;
u16 strength;
@@ -341,9 +350,9 @@ static int rtd119x_pconf_parse_conf(struct rtd119x_pinctrl *data,
return -EINVAL;
break;
case PCONF_UNSUPP:
- pr_err("[%s] not support drive strength\n", config_desc->name);
+ dev_err(data->pcdev->dev, "[%s] not support drive strength\n",
+ config_desc->name);
return -ENOTSUPP;
- break;
default:
return -EINVAL;
}
@@ -383,7 +392,7 @@ static int rtd119x_pconf_parse_conf(struct rtd119x_pinctrl *data,
return 0;
}
-static int rtd119x_pin_config_get(struct pinctrl_dev *pcdev, unsigned pinnr,
+static int rtd119x_pin_config_get(struct pinctrl_dev *pcdev, unsigned int pinnr,
unsigned long *config)
{
unsigned int param = pinconf_to_config_param(*config);
@@ -398,8 +407,8 @@ static int rtd119x_pin_config_get(struct pinctrl_dev *pcdev, unsigned pinnr,
return 0;
}
-static int rtd119x_pin_config_set(struct pinctrl_dev *pcdev, unsigned pinnr,
- unsigned long *configs, unsigned num_configs)
+static int rtd119x_pin_config_set(struct pinctrl_dev *pcdev, unsigned int pinnr,
+ unsigned long *configs, unsigned int num_configs)
{
struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
const struct rtd119x_pin_config_desc *config_desc;
@@ -436,55 +445,66 @@ static const struct pinconf_ops rtd119x_pinconf_ops = {
static void rtd119x_pinctrl_selftest(struct rtd119x_pinctrl *data)
{
int i, j, k;
+ const struct rtd119x_pinctrl_desc *info = data->info;
- for (i = 0; i < data->info->num_muxes; i++) {
+ for (i = 0; i < info->num_muxes; i++) {
/* Check for pin */
- for (j = 0; j < data->info->num_pins; j++) {
- if (strcmp(data->info->pins[j].name, data->info->muxes[i].name) == 0)
+ for (j = 0; j < info->num_pins; j++) {
+ if (strcmp(info->pins[j].name,
+ info->muxes[i].name) == 0)
break;
}
- if (j == data->info->num_pins)
+ if (j == info->num_pins)
dev_warn(data->pcdev->dev, "Mux %s lacking matching pin\n",
- data->info->muxes[i].name);
+ info->muxes[i].name);
/* Check for group */
- for (j = 0; j < data->info->num_groups; j++) {
- if (strcmp(data->info->groups[j].name, data->info->muxes[i].name) == 0)
+ for (j = 0; j < info->num_groups; j++) {
+ if (strcmp(info->groups[j].name,
+ info->muxes[i].name) == 0)
break;
}
- if (j == data->info->num_groups)
+ if (j == info->num_groups)
dev_warn(data->pcdev->dev, "Mux %s lacking matching group\n",
- data->info->muxes[i].name);
+ info->muxes[i].name);
- for (j = 0; data->info->muxes[i].functions[j].name; j++) {
+ for (j = 0; info->muxes[i].functions[j].name; j++) {
/* Check for function */
- for (k = 0; k < data->info->num_functions; k++) {
- if (strcmp(data->info->functions[k].name,
- data->info->muxes[i].functions[j].name) == 0)
+ for (k = 0; k < info->num_functions; k++) {
+ if (strcmp(info->functions[k].name,
+ info->muxes[i].functions[j].name) == 0)
break;
}
- if (k == data->info->num_functions)
+ if (k == info->num_functions)
dev_warn(data->pcdev->dev, "Mux %s lacking function %s\n",
- data->info->muxes[i].name,
- data->info->muxes[i].functions[j].name);
-
- /* Check for duplicate mux value - assumption: ascending order */
- if (j > 0 && data->info->muxes[i].functions[j].mux_value
- < data->info->muxes[i].functions[j - 1].mux_value)
+ info->muxes[i].name,
+ info->muxes[i].functions[j].name);
+
+ /* Check for duplicate mux value
+ *- assumption: ascending order
+ */
+ if (j > 0 && info->muxes[i].functions[j].mux_value
+ < info->muxes[i].functions[j - 1].mux_value)
dev_warn(data->pcdev->dev, "Mux %s function %s has unexpected value\n",
- data->info->muxes[i].name,
- data->info->muxes[i].functions[j].name);
+ info->muxes[i].name,
+ info->muxes[i].functions[j].name);
}
}
}
static const struct of_device_id rtd119x_pinctrl_dt_ids[] = {
- { .compatible = "realtek,rtd1195-iso-pinctrl", .data = &rtd1195_iso_pinctrl_desc },
- { .compatible = "realtek,rtd1195-crt-pinctrl", .data = &rtd1195_crt_pinctrl_desc },
- { .compatible = "realtek,rtd1295-iso-pinctrl", .data = &rtd1295_iso_pinctrl_desc },
- { .compatible = "realtek,rtd1295-sb2-pinctrl", .data = &rtd1295_sb2_pinctrl_desc },
- { .compatible = "realtek,rtd1295-disp-pinctrl", .data = &rtd1295_disp_pinctrl_desc },
- { .compatible = "realtek,rtd1295-cr-pinctrl", .data = &rtd1295_cr_pinctrl_desc },
+ { .compatible = "realtek,rtd1195-iso-pinctrl",
+ .data = &rtd1195_iso_pinctrl_desc },
+ { .compatible = "realtek,rtd1195-crt-pinctrl",
+ .data = &rtd1195_crt_pinctrl_desc },
+ { .compatible = "realtek,rtd1295-iso-pinctrl",
+ .data = &rtd1295_iso_pinctrl_desc },
+ { .compatible = "realtek,rtd1295-sb2-pinctrl",
+ .data = &rtd1295_sb2_pinctrl_desc },
+ { .compatible = "realtek,rtd1295-disp-pinctrl",
+ .data = &rtd1295_disp_pinctrl_desc },
+ { .compatible = "realtek,rtd1295-cr-pinctrl",
+ .data = &rtd1295_cr_pinctrl_desc },
{ }
};
@@ -537,3 +557,5 @@ static struct platform_driver rtd119x_pinctrl_driver = {
},
};
builtin_platform_driver(rtd119x_pinctrl_driver);
+MODULE_DESCRIPTION("rtk pinctrl driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/pinctrl-rtd1295.h b/drivers/pinctrl/pinctrl-rtd1295.h
index 0232c5d8b353..f27debc96bb6 100644
--- a/drivers/pinctrl/pinctrl-rtd1295.h
+++ b/drivers/pinctrl/pinctrl-rtd1295.h
@@ -1,3 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause */
+
+/*
+ * Realtek pin controller driver
+ *
+ * Copyright (c) 2019 Realtek Semiconductor Corp.
+ */
+
#ifndef PINCTRL_RTD1295_H
#define PINCTRL_RTD1295_H
@@ -116,8 +124,10 @@ static const unsigned int rtd1295_iso_gpio_23_pins[] = { RTD1295_ISO_GPIO_23 };
static const unsigned int rtd1295_iso_gpio_24_pins[] = { RTD1295_ISO_GPIO_24 };
static const unsigned int rtd1295_iso_gpio_25_pins[] = { RTD1295_ISO_GPIO_25 };
static const unsigned int rtd1295_i2c_sda_6_pins[] = { RTD1295_I2C_SDA_6 };
-static const unsigned int rtd1295_etn_led_link_pins[] = { RTD1295_ETN_LED_LINK };
-static const unsigned int rtd1295_etn_led_rxtx_pins[] = { RTD1295_ETN_LED_RXTX };
+static const unsigned int rtd1295_etn_led_link_pins[] = {
+ RTD1295_ETN_LED_LINK };
+static const unsigned int rtd1295_etn_led_rxtx_pins[] = {
+ RTD1295_ETN_LED_RXTX };
static const unsigned int rtd1295_nat_led_0_pins[] = { RTD1295_NAT_LED_0 };
static const unsigned int rtd1295_nat_led_1_pins[] = { RTD1295_NAT_LED_1 };
static const unsigned int rtd1295_nat_led_2_pins[] = { RTD1295_NAT_LED_2 };
@@ -128,16 +138,31 @@ static const unsigned int rtd1295_pwm_23_loc0_pins[] = { RTD1295_PWM_23_LOC0 };
static const unsigned int rtd1295_pwm_01_loc0_pins[] = { RTD1295_PWM_01_LOC0 };
static const unsigned int rtd1295_pwm_23_loc1_pins[] = { RTD1295_PWM_23_LOC1 };
static const unsigned int rtd1295_pwm_01_loc1_pins[] = { RTD1295_PWM_01_LOC1 };
-static const unsigned int rtd1295_ejtag_avcpu_loc_pins[] = { RTD1295_EJTAG_AVCPU_LOC };
+static const unsigned int rtd1295_ejtag_avcpu_loc_pins[] = {
+ RTD1295_EJTAG_AVCPU_LOC };
static const unsigned int rtd1295_ur2_loc_pins[] = { RTD1295_UR2_LOC };
-static const unsigned int rtd1295_i2c0_pins[] = { RTD1295_I2C_SCL_0, RTD1295_I2C_SDA_0 };
-static const unsigned int rtd1295_i2c1_pins[] = { RTD1295_I2C_SCL_1, RTD1295_I2C_SDA_1 };
-static const unsigned int rtd1295_i2c6_pins[] = { RTD1295_I2C_SCL_6, RTD1295_I2C_SDA_6 };
-static const unsigned int rtd1295_uart0_pins[] = { RTD1295_UR0_RX, RTD1295_UR0_TX };
-static const unsigned int rtd1295_uart1_pins[] = { RTD1295_UR1_RX, RTD1295_UR1_TX };
-static const unsigned int rtd1295_uart2_0_pins[] = { RTD1295_ISO_GPIO_2, RTD1295_ISO_GPIO_3, RTD1295_ISO_GPIO_4, RTD1295_ISO_GPIO_5 };
-static const unsigned int rtd1295_uart2_1_pins[] = { RTD1295_ISO_GPIO_23, RTD1295_ISO_GPIO_24, RTD1295_ISO_GPIO_33, RTD1295_ISO_GPIO_34 };
+static const unsigned int rtd1295_i2c0_pins[] = {
+ RTD1295_I2C_SCL_0, RTD1295_I2C_SDA_0
+};
+static const unsigned int rtd1295_i2c1_pins[] = {
+ RTD1295_I2C_SCL_1, RTD1295_I2C_SDA_1
+};
+static const unsigned int rtd1295_i2c6_pins[] = {
+ RTD1295_I2C_SCL_6, RTD1295_I2C_SDA_6
+};
+static const unsigned int rtd1295_uart0_pins[] = {
+ RTD1295_UR0_RX, RTD1295_UR0_TX };
+static const unsigned int rtd1295_uart1_pins[] = {
+ RTD1295_UR1_RX, RTD1295_UR1_TX };
+static const unsigned int rtd1295_uart2_0_pins[] = {
+ RTD1295_ISO_GPIO_2, RTD1295_ISO_GPIO_3,
+ RTD1295_ISO_GPIO_4, RTD1295_ISO_GPIO_5
+};
+static const unsigned int rtd1295_uart2_1_pins[] = {
+ RTD1295_ISO_GPIO_23, RTD1295_ISO_GPIO_24,
+ RTD1295_ISO_GPIO_33, RTD1295_ISO_GPIO_34
+};
#define RTD1295_GROUP(_name) \
{ \
@@ -199,41 +224,90 @@ static const struct rtd119x_pin_group_desc rtd1295_iso_pin_groups[] = {
};
static const char * const rtd1295_iso_gpio_groups[] = {
- "iso_gpio_2", "iso_gpio_3", "iso_gpio_4", "iso_gpio_5", "hdmi_hpd", "iso_gpio_7",
- "ir_rx", "ir_tx", "ur0_rx", "ur0_tx", "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n",
+ "iso_gpio_2", "iso_gpio_3", "iso_gpio_4",
+ "iso_gpio_5", "hdmi_hpd", "iso_gpio_7",
+ "ir_rx", "ir_tx", "ur0_rx", "ur0_tx",
+ "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n",
"i2c_scl_0", "i2c_sda_0", "i2c_scl_1", "i2c_sda_1", "i2c_scl_6",
- "iso_gpio_21", "iso_gpio_22", "iso_gpio_23", "iso_gpio_24", "iso_gpio_25",
+ "iso_gpio_21", "iso_gpio_22", "iso_gpio_23",
+ "iso_gpio_24", "iso_gpio_25",
"i2c_sda_6", "etn_led_link", "etn_led_rxtx",
"nat_led_0", "nat_led_1", "nat_led_2", "nat_led_3",
"iso_gpio_33", "iso_gpio_34"
};
-static const char * const rtd1295_iso_acpu_ejtag_loc_iso_groups[] = { "iso_gpio_2", "iso_gpio_3", "iso_gpio_4", "iso_gpio_5", "iso_gpio_7" };
+static const char * const rtd1295_iso_acpu_ejtag_loc_iso_groups[] = {
+ "iso_gpio_2", "iso_gpio_3", "iso_gpio_4", "iso_gpio_5", "iso_gpio_7"
+};
static const char * const rtd1295_iso_edp_hpd_groups[] = { "iso_gpio_7" };
-static const char * const rtd1295_iso_etn_led_groups[] = { "etn_led_link", "etn_led_rxtx" };
-static const char * const rtd1295_iso_i2c0_groups[] = { "i2c_scl_0", "i2c_sda_0", "i2c0" };
-static const char * const rtd1295_iso_i2c1_groups[] = { "i2c_scl_1", "i2c_sda_1", "i2c1" };
-static const char * const rtd1295_iso_i2c6_groups[] = { "i2c_scl_6", "i2c_sda_6", "i2c6" };
+static const char * const rtd1295_iso_etn_led_groups[] = {
+ "etn_led_link", "etn_led_rxtx"
+};
+static const char * const rtd1295_iso_i2c0_groups[] = {
+ "i2c_scl_0", "i2c_sda_0", "i2c0"
+};
+static const char * const rtd1295_iso_i2c1_groups[] = {
+ "i2c_scl_1", "i2c_sda_1", "i2c1"
+};
+static const char * const rtd1295_iso_i2c6_groups[] = {
+ "i2c_scl_6", "i2c_sda_6", "i2c6"
+};
static const char * const rtd1295_iso_ir_rx_groups[] = { "ir_rx" };
static const char * const rtd1295_iso_ir_tx_groups[] = { "ir_tx" };
-static const char * const rtd1295_iso_nat_led_groups[] = { "nat_led_0", "nat_led_1", "nat_led_2", "nat_led_3" };
-static const char * const rtd1295_iso_pwm_1_groups[] = { "etn_led_link", "etn_led_rxtx", "nat_led_0", "nat_led_1" };
-static const char * const rtd1295_iso_pwm_0_groups[] = { "iso_gpio_21", "iso_gpio_22", "iso_gpio_23", "iso_gpio_24" };
+static const char * const rtd1295_iso_nat_led_groups[] = {
+ "nat_led_0", "nat_led_1", "nat_led_2", "nat_led_3"
+};
+static const char * const rtd1295_iso_pwm_1_groups[] = {
+ "etn_led_link", "etn_led_rxtx", "nat_led_0", "nat_led_1"
+};
+static const char * const rtd1295_iso_pwm_0_groups[] = {
+ "iso_gpio_21", "iso_gpio_22", "iso_gpio_23", "iso_gpio_24"
+};
static const char * const rtd1295_iso_rtc_groups[] = { "iso_gpio_25" };
-static const char * const rtd1295_iso_sc_groups[] = { "nat_led_0", "nat_led_1", "nat_led_2", "nat_led_3" };
-static const char * const rtd1295_iso_standby_dbg_groups[] = { "iso_gpio_2", "iso_gpio_3", "ir_rx" };
-static const char * const rtd1295_iso_uart0_groups[] = { "ur0_rx", "ur0_tx", "uart0" };
-static const char * const rtd1295_iso_uart1_groups[] = { "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n", "uart1" };
-static const char * const rtd1295_iso_uart2_0_groups[] = { "iso_gpio_2", "iso_gpio_3", "iso_gpio_4", "iso_gpio_5", "ur2_loc" };
-static const char * const rtd1295_iso_uart2_1_groups[] = { "iso_gpio_23", "iso_gpio_24", "iso_gpio_33", "iso_gpio_34", "ur2_loc" };
-static const char * const rtd1295_iso_pwm_01_loc0_normal_groups[] = { "pwm_01_loc0" };
-static const char * const rtd1295_iso_pwm_23_loc0_normal_groups[] = { "pwm_23_loc0" };
-static const char * const rtd1295_iso_pwm_01_loc0_open_drain_groups[] = { "pwm_01_loc0" };
-static const char * const rtd1295_iso_pwm_23_loc0_open_drain_groups[] = { "pwm_23_loc0" };
-static const char * const rtd1295_iso_pwm_01_loc1_normal_groups[] = { "pwm_01_loc1" };
-static const char * const rtd1295_iso_pwm_23_loc1_normal_groups[] = { "pwm_23_loc1" };
-static const char * const rtd1295_iso_pwm_01_loc1_open_drain_groups[] = { "pwm_01_loc1" };
-static const char * const rtd1295_iso_pwm_23_loc1_open_drain_groups[] = { "pwm_23_loc1" };
-static const char * const rtd1295_iso_acpu_ejtag_loc_nf_groups[] = { "ejtag_avcpu_loc" };
+static const char * const rtd1295_iso_sc_groups[] = {
+ "nat_led_0", "nat_led_1", "nat_led_2", "nat_led_3"
+};
+static const char * const rtd1295_iso_standby_dbg_groups[] = {
+ "iso_gpio_2", "iso_gpio_3", "ir_rx"
+};
+static const char * const rtd1295_iso_uart0_groups[] = {
+ "ur0_rx", "ur0_tx", "uart0"
+};
+static const char * const rtd1295_iso_uart1_groups[] = {
+ "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n", "uart1"
+};
+static const char * const rtd1295_iso_uart2_0_groups[] = {
+ "iso_gpio_2", "iso_gpio_3", "iso_gpio_4", "iso_gpio_5", "ur2_loc"
+};
+static const char * const rtd1295_iso_uart2_1_groups[] = {
+ "iso_gpio_23", "iso_gpio_24", "iso_gpio_33", "iso_gpio_34", "ur2_loc"
+};
+static const char * const rtd1295_iso_pwm_01_loc0_normal_groups[] = {
+ "pwm_01_loc0"
+};
+static const char * const rtd1295_iso_pwm_23_loc0_normal_groups[] = {
+ "pwm_23_loc0"
+};
+static const char * const rtd1295_iso_pwm_01_loc0_open_drain_groups[] = {
+ "pwm_01_loc0"
+};
+static const char * const rtd1295_iso_pwm_23_loc0_open_drain_groups[] = {
+ "pwm_23_loc0"
+};
+static const char * const rtd1295_iso_pwm_01_loc1_normal_groups[] = {
+ "pwm_01_loc1"
+};
+static const char * const rtd1295_iso_pwm_23_loc1_normal_groups[] = {
+ "pwm_23_loc1"
+};
+static const char * const rtd1295_iso_pwm_01_loc1_open_drain_groups[] = {
+ "pwm_01_loc1"
+};
+static const char * const rtd1295_iso_pwm_23_loc1_open_drain_groups[] = {
+ "pwm_23_loc1"
+};
+static const char * const rtd1295_iso_acpu_ejtag_loc_nf_groups[] = {
+ "ejtag_avcpu_loc"
+};
#define RTD1295_FUNC(_name) \
@@ -608,11 +682,15 @@ static const unsigned int rtd1295_i2c_sda_4_pins[] = { RTD1295_I2C_SDA_4 };
static const unsigned int rtd1295_i2c_scl_5_pins[] = { RTD1295_I2C_SCL_5 };
static const unsigned int rtd1295_i2c_sda_5_pins[] = { RTD1295_I2C_SDA_5 };
static const unsigned int rtd1295_usb_id_pins[] = { RTD1295_USB_ID };
-static const unsigned int rtd1295_sensor_cko_0_pins[] = { RTD1295_SENSOR_CKO_0 };
-static const unsigned int rtd1295_sensor_cko_1_pins[] = { RTD1295_SENSOR_CKO_1 };
+static const unsigned int rtd1295_sensor_cko_0_pins[] = {
+ RTD1295_SENSOR_CKO_0 };
+static const unsigned int rtd1295_sensor_cko_1_pins[] = {
+ RTD1295_SENSOR_CKO_1 };
static const unsigned int rtd1295_sensor_rst_pins[] = { RTD1295_SENSOR_RST };
-static const unsigned int rtd1295_sensor_stb_0_pins[] = { RTD1295_SENSOR_STB_0 };
-static const unsigned int rtd1295_sensor_stb_1_pins[] = { RTD1295_SENSOR_STB_1 };
+static const unsigned int rtd1295_sensor_stb_0_pins[] = {
+ RTD1295_SENSOR_STB_0 };
+static const unsigned int rtd1295_sensor_stb_1_pins[] = {
+ RTD1295_SENSOR_STB_1 };
static const unsigned int rtd1295_tp0_data_pins[] = { RTD1295_TP0_DATA };
static const unsigned int rtd1295_tp0_clk_pins[] = { RTD1295_TP0_CLK };
static const unsigned int rtd1295_tp0_valid_pins[] = { RTD1295_TP0_VALID };
@@ -621,33 +699,54 @@ static const unsigned int rtd1295_tp1_data_pins[] = { RTD1295_TP1_DATA };
static const unsigned int rtd1295_tp1_clk_pins[] = { RTD1295_TP1_CLK };
static const unsigned int rtd1295_tp1_valid_pins[] = { RTD1295_TP1_VALID };
static const unsigned int rtd1295_rgmii0_txc_pins[] = { RTD1295_RGMII0_TXC };
-static const unsigned int rtd1295_rgmii0_tx_ctl_pins[] = { RTD1295_RGMII0_TX_CTL };
-static const unsigned int rtd1295_rgmii0_txd_0_pins[] = { RTD1295_RGMII0_TXD_0 };
-static const unsigned int rtd1295_rgmii0_txd_1_pins[] = { RTD1295_RGMII0_TXD_1 };
-static const unsigned int rtd1295_rgmii0_txd_2_pins[] = { RTD1295_RGMII0_TXD_2 };
-static const unsigned int rtd1295_rgmii0_txd_3_pins[] = { RTD1295_RGMII0_TXD_3 };
+static const unsigned int rtd1295_rgmii0_tx_ctl_pins[] = {
+ RTD1295_RGMII0_TX_CTL };
+static const unsigned int rtd1295_rgmii0_txd_0_pins[] = {
+ RTD1295_RGMII0_TXD_0 };
+static const unsigned int rtd1295_rgmii0_txd_1_pins[] = {
+ RTD1295_RGMII0_TXD_1 };
+static const unsigned int rtd1295_rgmii0_txd_2_pins[] = {
+ RTD1295_RGMII0_TXD_2 };
+static const unsigned int rtd1295_rgmii0_txd_3_pins[] = {
+ RTD1295_RGMII0_TXD_3 };
static const unsigned int rtd1295_rgmii0_rxc_pins[] = { RTD1295_RGMII0_RXC };
-static const unsigned int rtd1295_rgmii0_rx_ctl_pins[] = { RTD1295_RGMII0_RX_CTL };
-static const unsigned int rtd1295_rgmii0_rxd_0_pins[] = { RTD1295_RGMII0_RXD_0 };
-static const unsigned int rtd1295_rgmii0_rxd_1_pins[] = { RTD1295_RGMII0_RXD_1 };
-static const unsigned int rtd1295_rgmii0_rxd_2_pins[] = { RTD1295_RGMII0_RXD_2 };
-static const unsigned int rtd1295_rgmii0_rxd_3_pins[] = { RTD1295_RGMII0_RXD_3 };
+static const unsigned int rtd1295_rgmii0_rx_ctl_pins[] = {
+ RTD1295_RGMII0_RX_CTL };
+static const unsigned int rtd1295_rgmii0_rxd_0_pins[] = {
+ RTD1295_RGMII0_RXD_0 };
+static const unsigned int rtd1295_rgmii0_rxd_1_pins[] = {
+ RTD1295_RGMII0_RXD_1 };
+static const unsigned int rtd1295_rgmii0_rxd_2_pins[] = {
+ RTD1295_RGMII0_RXD_2 };
+static const unsigned int rtd1295_rgmii0_rxd_3_pins[] = {
+ RTD1295_RGMII0_RXD_3 };
static const unsigned int rtd1295_rgmii0_mdio_pins[] = { RTD1295_RGMII0_MDIO };
static const unsigned int rtd1295_rgmii0_mdc_pins[] = { RTD1295_RGMII0_MDC };
static const unsigned int rtd1295_rgmii1_txc_pins[] = { RTD1295_RGMII1_TXC };
-static const unsigned int rtd1295_rgmii1_tx_ctl_pins[] = { RTD1295_RGMII1_TX_CTL };
-static const unsigned int rtd1295_rgmii1_txd_0_pins[] = { RTD1295_RGMII1_TXD_0 };
-static const unsigned int rtd1295_rgmii1_txd_1_pins[] = { RTD1295_RGMII1_TXD_1 };
-static const unsigned int rtd1295_rgmii1_txd_2_pins[] = { RTD1295_RGMII1_TXD_2 };
-static const unsigned int rtd1295_rgmii1_txd_3_pins[] = { RTD1295_RGMII1_TXD_3 };
+static const unsigned int rtd1295_rgmii1_tx_ctl_pins[] = {
+ RTD1295_RGMII1_TX_CTL };
+static const unsigned int rtd1295_rgmii1_txd_0_pins[] = {
+ RTD1295_RGMII1_TXD_0 };
+static const unsigned int rtd1295_rgmii1_txd_1_pins[] = {
+ RTD1295_RGMII1_TXD_1 };
+static const unsigned int rtd1295_rgmii1_txd_2_pins[] = {
+ RTD1295_RGMII1_TXD_2 };
+static const unsigned int rtd1295_rgmii1_txd_3_pins[] = {
+ RTD1295_RGMII1_TXD_3 };
static const unsigned int rtd1295_rgmii1_rxc_pins[] = { RTD1295_RGMII1_RXC };
-static const unsigned int rtd1295_rgmii1_rx_ctl_pins[] = { RTD1295_RGMII1_RX_CTL };
-static const unsigned int rtd1295_rgmii1_rxd_0_pins[] = { RTD1295_RGMII1_RXD_0 };
-static const unsigned int rtd1295_rgmii1_rxd_1_pins[] = { RTD1295_RGMII1_RXD_1 };
-static const unsigned int rtd1295_rgmii1_rxd_2_pins[] = { RTD1295_RGMII1_RXD_2 };
-static const unsigned int rtd1295_rgmii1_rxd_3_pins[] = { RTD1295_RGMII1_RXD_3 };
+static const unsigned int rtd1295_rgmii1_rx_ctl_pins[] = {
+ RTD1295_RGMII1_RX_CTL };
+static const unsigned int rtd1295_rgmii1_rxd_0_pins[] = {
+ RTD1295_RGMII1_RXD_0 };
+static const unsigned int rtd1295_rgmii1_rxd_1_pins[] = {
+ RTD1295_RGMII1_RXD_1 };
+static const unsigned int rtd1295_rgmii1_rxd_2_pins[] = {
+ RTD1295_RGMII1_RXD_2 };
+static const unsigned int rtd1295_rgmii1_rxd_3_pins[] = {
+ RTD1295_RGMII1_RXD_3 };
static const unsigned int rtd1295_hif_loc_pins[] = { RTD1295_HI_LOC };
-static const unsigned int rtd1295_ejtag_scpu_loc_pins[] = { RTD1295_EJTAG_SCPU_LOC };
+static const unsigned int rtd1295_ejtag_scpu_loc_pins[] = {
+ RTD1295_EJTAG_SCPU_LOC };
static const unsigned int rtd1295_sf_en_pins[] = { RTD1295_SF_EN };
static const unsigned int rtd1295_tp0_loc_pins[] = { RTD1295_TP0_LOC };
static const unsigned int rtd1295_tp1_loc_pins[] = { RTD1295_TP1_LOC };
@@ -720,46 +819,96 @@ static const struct rtd119x_pin_group_desc rtd1295_sb2_pin_groups[] = {
};
static const char * const rtd1295_sb2_gpio_groups[] = {
- "gpio_0", "gpio_1", "gpio_2", "gpio_3", "gpio_4", "gpio_5", "gpio_6", "gpio_7", "gpio_8", "gpio_9",
+ "gpio_0", "gpio_1", "gpio_2", "gpio_3", "gpio_4",
+ "gpio_5", "gpio_6", "gpio_7", "gpio_8", "gpio_9",
"i2c_scl_4", "i2c_sda_4", "i2c_scl_5", "i2c_sda_5", "usb_id",
- "sensor_cko_0", "sensor_cko_1", "sensor_rst", "sensor_stb_0", "sensor_stb_1",
+ "sensor_cko_0", "sensor_cko_1", "sensor_rst",
+ "sensor_stb_0", "sensor_stb_1",
"tp0_data", "tp0_clk", "tp0_valid", "tp0_sync",
"tp1_data", "tp1_clk", "tp1_valid", "tp1_sync",
- "rgmii0_txc", "rgmii0_tx_ctl", "rgmii0_txd_0", "rgmii0_txd_1", "rgmii0_txd_2", "rgmii0_txd_3",
- "rgmii0_rxc", "rgmii0_rx_ctl", "rgmii0_rxd_0", "rgmii0_rxd_1", "rgmii0_rxd_2", "rgmii0_rxd_3",
+ "rgmii0_txc", "rgmii0_tx_ctl", "rgmii0_txd_0",
+ "rgmii0_txd_1", "rgmii0_txd_2", "rgmii0_txd_3",
+ "rgmii0_rxc", "rgmii0_rx_ctl", "rgmii0_rxd_0",
+ "rgmii0_rxd_1", "rgmii0_rxd_2", "rgmii0_rxd_3",
"rgmii0_mdio", "rgmii0_mdc",
- "rgmii1_txc", "rgmii1_tx_ctl", "rgmii1_txd_0", "rgmii1_txd_1", "rgmii1_txd_2", "rgmii1_txd_3",
- "rgmii1_rxc", "rgmii1_rx_ctl", "rgmii1_rxd_0", "rgmii1_rxd_1", "rgmii1_rxd_2", "rgmii1_rxd_3",
+ "rgmii1_txc", "rgmii1_tx_ctl", "rgmii1_txd_0",
+ "rgmii1_txd_1", "rgmii1_txd_2", "rgmii1_txd_3",
+ "rgmii1_rxc", "rgmii1_rx_ctl", "rgmii1_rxd_0",
+ "rgmii1_rxd_1", "rgmii1_rxd_2", "rgmii1_rxd_3",
+};
+static const char * const rtd1295_sb2_ai_groups[] = {
+ "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk"
};
-static const char * const rtd1295_sb2_ai_groups[] = { "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk" };
static const char * const rtd1295_sb2_dc_fan_sensor_groups[] = { "gpio_9" };
-static const char * const rtd1295_sb2_eth_gpy_groups[] = { "rgmii0_mdio", "rgmii0_mdc" };
-static const char * const rtd1295_sb2_gspi_groups[] = { "gpio_4", "gpio_5", "gpio_6", "gpio_7" };
-static const char * const rtd1295_sb2_i2c2_groups[] = { "tp1_sync", "tp1_clk" };
-static const char * const rtd1295_sb2_i2c3_groups[] = { "tp1_data", "tp1_valid" };
-static const char * const rtd1295_sb2_i2c4_groups[] = { "i2c_scl_4", "i2c_sda_4" };
-static const char * const rtd1295_sb2_i2c5_groups[] = { "i2c_scl_5", "i2c_sda_5" };
-static const char * const rtd1295_sb2_nand_groups[] = { "i2c_sda_5", "i2c_scl_5" };
+static const char * const rtd1295_sb2_eth_gpy_groups[] = {
+ "rgmii0_mdio", "rgmii0_mdc"
+};
+static const char * const rtd1295_sb2_gspi_groups[] = {
+ "gpio_4", "gpio_5", "gpio_6", "gpio_7"
+};
+static const char * const rtd1295_sb2_i2c2_groups[] = {
+ "tp1_sync", "tp1_clk"
+};
+static const char * const rtd1295_sb2_i2c3_groups[] = {
+ "tp1_data", "tp1_valid"
+};
+static const char * const rtd1295_sb2_i2c4_groups[] = {
+ "i2c_scl_4", "i2c_sda_4"
+};
+static const char * const rtd1295_sb2_i2c5_groups[] = {
+ "i2c_scl_5", "i2c_sda_5"
+};
+static const char * const rtd1295_sb2_nand_groups[] = {
+ "i2c_sda_5", "i2c_scl_5"
+};
static const char * const rtd1295_sb2_rgmii_groups[] = {
- "rgmii0_txc", "rgmii0_tx_ctl", "rgmii0_txd_0", "rgmii0_txd_1", "rgmii0_txd_2", "rgmii0_txd_3",
- "rgmii0_rxc", "rgmii0_rx_ctl", "rgmii0_rxd_0", "rgmii0_rxd_1", "rgmii0_rxd_2", "rgmii0_rxd_3",
+ "rgmii0_txc", "rgmii0_tx_ctl", "rgmii0_txd_0",
+ "rgmii0_txd_1", "rgmii0_txd_2", "rgmii0_txd_3",
+ "rgmii0_rxc", "rgmii0_rx_ctl", "rgmii0_rxd_0",
+ "rgmii0_rxd_1", "rgmii0_rxd_2", "rgmii0_rxd_3",
"rgmii0_mdio", "rgmii0_mdc",
- "rgmii1_txc", "rgmii1_tx_ctl", "rgmii1_txd_0", "rgmii1_txd_1", "rgmii1_txd_2", "rgmii1_txd_3",
- "rgmii1_rxc", "rgmii1_rx_ctl", "rgmii1_rxd_0", "rgmii1_rxd_1", "rgmii1_rxd_2", "rgmii1_rxd_3",
+ "rgmii1_txc", "rgmii1_tx_ctl", "rgmii1_txd_0",
+ "rgmii1_txd_1", "rgmii1_txd_2", "rgmii1_txd_3",
+ "rgmii1_rxc", "rgmii1_rx_ctl", "rgmii1_rxd_0",
+ "rgmii1_rxd_1", "rgmii1_rxd_2", "rgmii1_rxd_3",
};
-static const char * const rtd1295_sb2_scpu_ejtag_loc_gpio_groups[] = { "gpio_4", "gpio_5", "gpio_6", "gpio_7", "gpio_8", "ejtag_scpu_loc" };
-static const char * const rtd1295_sb2_scpu_ejtag_loc_cr_groups[] = { "ejtag_scpu_loc" };
-static const char * const rtd1295_sb2_sensor_cko_output_groups[] = { "sensor_cko_0", "sensor_cko_1" };
-static const char * const rtd1295_sb2_spi_groups[] = { "gpio_0", "gpio_1", "gpio_2", "gpio_3" };
+static const char * const rtd1295_sb2_scpu_ejtag_loc_gpio_groups[] = {
+ "gpio_4", "gpio_5", "gpio_6", "gpio_7", "gpio_8", "ejtag_scpu_loc"
+};
+static const char * const rtd1295_sb2_scpu_ejtag_loc_cr_groups[] = {
+ "ejtag_scpu_loc"
+};
+static const char * const rtd1295_sb2_sensor_cko_output_groups[] = {
+ "sensor_cko_0", "sensor_cko_1"
+};
+static const char * const rtd1295_sb2_spi_groups[] = {
+ "gpio_0", "gpio_1", "gpio_2", "gpio_3"
+};
static const char * const rtd1295_sb2_test_loop_dis_groups[] = { "usb_id" };
-static const char * const rtd1295_sb2_tp0_loc_rgmii0_tx_groups[] = { "rgmii0_txd_0", "rgmii0_txd_1", "rgmii0_txd_2", "rgmii0_txd_3", "tp0_loc" };
-static const char * const rtd1295_sb2_tp0_loc_tp0_groups[] = { "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk", "tp0_loc" };
-static const char * const rtd1295_sb2_tp0_loc_tp1_groups[] = { "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk", "tp0_loc" };
-static const char * const rtd1295_sb2_tp1_loc_rgmii0_rx_groups[] = { "rgmii0_rxd_0", "rgmii0_rxd_1", "rgmii0_rxd_2", "rgmii0_rxd_3", "tp1_loc" };
-static const char * const rtd1295_sb2_tp1_loc_tp0_groups[] = { "tp1_data", "tp1_sync", "tp1_valid", "tp1_clk", "tp1_loc" };
-static const char * const rtd1295_sb2_tp1_loc_tp1_groups[] = { "tp1_data", "tp1_sync", "tp1_valid", "tp1_clk", "tp1_loc" };
-static const char * const rtd1295_sb2_usb_clock_output_groups[] = { "sensor_cko_1" };
+static const char * const rtd1295_sb2_tp0_loc_rgmii0_tx_groups[] = {
+ "rgmii0_txd_0", "rgmii0_txd_1", "rgmii0_txd_2",
+ "rgmii0_txd_3", "tp0_loc"
+};
+static const char * const rtd1295_sb2_tp0_loc_tp0_groups[] = {
+ "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk", "tp0_loc"
+};
+static const char * const rtd1295_sb2_tp0_loc_tp1_groups[] = {
+ "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk", "tp0_loc"
+};
+static const char * const rtd1295_sb2_tp1_loc_rgmii0_rx_groups[] = {
+ "rgmii0_rxd_0", "rgmii0_rxd_1", "rgmii0_rxd_2",
+ "rgmii0_rxd_3", "tp1_loc"
+};
+static const char * const rtd1295_sb2_tp1_loc_tp0_groups[] = {
+ "tp1_data", "tp1_sync", "tp1_valid", "tp1_clk", "tp1_loc"
+};
+static const char * const rtd1295_sb2_tp1_loc_tp1_groups[] = {
+ "tp1_data", "tp1_sync", "tp1_valid", "tp1_clk", "tp1_loc"
+};
+static const char * const rtd1295_sb2_usb_clock_output_groups[] = {
+ "sensor_cko_1"
+};
static const char * const rtd1295_sb2_hif_loc_misc_groups[] = { "hif_loc" };
static const char * const rtd1295_sb2_hif_loc_nf_groups[] = { "hif_loc" };
@@ -1146,9 +1295,15 @@ static const char * const rtd1295_disp_gpio_groups[] = {
"spdif", "dmic_clk", "dmic_data",
"ao_lrck", "ao_bck", "aock", "ao_sd_0", "ao_sd_1", "ao_sd_2", "ao_sd_3",
};
-static const char * const rtd1295_disp_ai_groups[] = { "dmic_clk", "dmic_data", "ao_sd_2", "ao_sd_3" };
-static const char * const rtd1295_disp_ao_groups[] = { "ao_lrck", "ao_bck", "aock", "ao_sd_0", "ao_sd_1", "ao_sd_2", "ao_sd_3" };
-static const char * const rtd1295_disp_dmic_groups[] = { "dmic_clk", "dmic_data" };
+static const char * const rtd1295_disp_ai_groups[] = {
+ "dmic_clk", "dmic_data", "ao_sd_2", "ao_sd_3"
+};
+static const char * const rtd1295_disp_ao_groups[] = {
+ "ao_lrck", "ao_bck", "aock", "ao_sd_0", "ao_sd_1", "ao_sd_2", "ao_sd_3"
+};
+static const char * const rtd1295_disp_dmic_groups[] = {
+ "dmic_clk", "dmic_data"
+};
static const char * const rtd1295_disp_spdif_out_groups[] = { "spdif" };
#define RTD1295_FUNC(_name) \
@@ -1347,8 +1502,10 @@ static const unsigned int rtd1295_sdio_data_0_pins[] = { RTD1295_SDIO_DATA_0 };
static const unsigned int rtd1295_sdio_data_1_pins[] = { RTD1295_SDIO_DATA_1 };
static const unsigned int rtd1295_sdio_data_2_pins[] = { RTD1295_SDIO_DATA_2 };
static const unsigned int rtd1295_sdio_data_3_pins[] = { RTD1295_SDIO_DATA_3 };
-static const unsigned int rtd1295_pcie_clkreq_0_pins[] = { RTD1295_PCIE_CLKREQ_0 };
-static const unsigned int rtd1295_pcie_clkreq_1_pins[] = { RTD1295_PCIE_CLKREQ_1 };
+static const unsigned int rtd1295_pcie_clkreq_0_pins[] = {
+ RTD1295_PCIE_CLKREQ_0 };
+static const unsigned int rtd1295_pcie_clkreq_1_pins[] = {
+ RTD1295_PCIE_CLKREQ_1 };
static const unsigned int rtd1295_prob_0_pins[] = { RTD1295_PROB_0 };
static const unsigned int rtd1295_prob_1_pins[] = { RTD1295_PROB_1 };
static const unsigned int rtd1295_prob_2_pins[] = { RTD1295_PROB_2 };
@@ -1399,25 +1556,57 @@ static const struct rtd119x_pin_group_desc rtd1295_cr_pin_groups[] = {
static const char * const rtd1295_cr_gpio_groups[] = {
"nf_cle", "nf_ale", "nf_rd_n", "nf_wr_n", "nf_rdy",
- "nf_dd_7", "nf_dd_6", "nf_dd_5", "nf_dd_4", "nf_dd_3", "nf_dd_2", "nf_dd_1", "nf_dd_0",
+ "nf_dd_7", "nf_dd_6", "nf_dd_5", "nf_dd_4",
+ "nf_dd_3", "nf_dd_2", "nf_dd_1", "nf_dd_0",
"nf_dqs", "nf_ce_n_0", "nf_ce_n_1",
"emmc_dd_sb",
- "mmc_cmd", "mmc_clk", "mmc_wp", "mmc_cd", "mmc_data_0", "mmc_data_1", "mmc_data_2", "mmc_data_3",
- "sdio_cmd", "sdio_clk", "sdio_data_0", "sdio_data_1", "sdio_data_2", "sdio_data_3",
+ "mmc_cmd", "mmc_clk", "mmc_wp", "mmc_cd", "mmc_data_0",
+ "mmc_data_1", "mmc_data_2", "mmc_data_3",
+ "sdio_cmd", "sdio_clk", "sdio_data_0", "sdio_data_1",
+ "sdio_data_2", "sdio_data_3",
"pcie_clkreq_0", "pcie_clkreq_1",
"prob_0", "prob_1", "prob_2", "prob_3",
};
-static const char * const rtd1295_cr_avcpu_ej_groups[] = { "nf_rdy", "nf_rd_n", "nf_dd_5", "nf_dd_6", "nf_dd_7" };
-static const char * const rtd1295_cr_emmc_groups[] = { "nf_rdy", "nf_rd_n", "nf_cle", "nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3", "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7", "emmc_dd_db" };
-static const char * const rtd1295_cr_hif_groups[] = { "nf_wr_n", "nf_ale", "nf_cle", "nf_dd_4" };
-static const char * const rtd1295_cr_nand_groups[] = { "nf_dqs", "nf_rdy", "nf_rd_n", "nf_wr_n", "nf_ale", "nf_cle", "nf_ce_n_0", "nf_ce_n_1", "nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3", "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7" };
-static const char * const rtd1295_cr_p2s_groups[] = { "prob_0", "prob_1" };
-static const char * const rtd1295_cr_pcie_groups[] = { "pcie_clkreq_0", "pcie_clkreq_1" };
-static const char * const rtd1295_cr_pll_test_groups[] = { "prob_0", "prob_1", "prob_2", "prob_3" };
-static const char * const rtd1295_cr_scpu_ejtag_loc_cr_groups[] = { "mmc_cmd", "mmc_clk", "mmc_wp", "mmc_data_0", "mmc_data_3" };
-static const char * const rtd1295_cr_sd_card_groups[] = { "mmc_cmd", "mmc_clk", "mmc_wp", "mmc_cd", "mmc_data_0", "mmc_data_1", "mmc_data_2", "mmc_data_3" };
-static const char * const rtd1295_cr_sdio_0_groups[] = { "sdio_cmd", "sdio_clk", "sdio_data_0", "sdio_data_1", "sdio_data_2", "sdio_data_3" };
-static const char * const rtd1295_cr_sdio_1_groups[] = { "mmc_cmd", "mmc_clk", "mmc_data_0", "mmc_data_1", "mmc_data_2", "mmc_data_3" };
+static const char * const rtd1295_cr_avcpu_ej_groups[] = {
+ "nf_rdy", "nf_rd_n", "nf_dd_5", "nf_dd_6", "nf_dd_7"
+};
+static const char * const rtd1295_cr_emmc_groups[] = {
+ "nf_rdy", "nf_rd_n", "nf_cle", "nf_dd_0", "nf_dd_1",
+ "nf_dd_2", "nf_dd_3", "nf_dd_4", "nf_dd_5", "nf_dd_6",
+ "nf_dd_7", "emmc_dd_db"
+};
+static const char * const rtd1295_cr_hif_groups[] = {
+ "nf_wr_n", "nf_ale", "nf_cle", "nf_dd_4"
+};
+static const char * const rtd1295_cr_nand_groups[] = {
+ "nf_dqs", "nf_rdy", "nf_rd_n", "nf_wr_n", "nf_ale", "nf_cle",
+ "nf_ce_n_0", "nf_ce_n_1", "nf_dd_0", "nf_dd_1", "nf_dd_2",
+ "nf_dd_3", "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7"
+};
+static const char * const rtd1295_cr_p2s_groups[] = {
+ "prob_0", "prob_1"
+};
+static const char * const rtd1295_cr_pcie_groups[] = {
+ "pcie_clkreq_0", "pcie_clkreq_1"
+};
+static const char * const rtd1295_cr_pll_test_groups[] = {
+ "prob_0", "prob_1", "prob_2", "prob_3"
+};
+static const char * const rtd1295_cr_scpu_ejtag_loc_cr_groups[] = {
+ "mmc_cmd", "mmc_clk", "mmc_wp", "mmc_data_0", "mmc_data_3"
+};
+static const char * const rtd1295_cr_sd_card_groups[] = {
+ "mmc_cmd", "mmc_clk", "mmc_wp", "mmc_cd", "mmc_data_0",
+ "mmc_data_1", "mmc_data_2", "mmc_data_3"
+};
+static const char * const rtd1295_cr_sdio_0_groups[] = {
+ "sdio_cmd", "sdio_clk", "sdio_data_0",
+ "sdio_data_1", "sdio_data_2", "sdio_data_3"
+};
+static const char * const rtd1295_cr_sdio_1_groups[] = {
+ "mmc_cmd", "mmc_clk", "mmc_data_0",
+ "mmc_data_1", "mmc_data_2", "mmc_data_3"
+};
#define RTD1295_FUNC(_name) \
--
2.26.2
^ permalink raw reply related
* [PATCH 3/7] pinctrl: realtek: rtd1195: Add missed pins and pin configs.
From: TY Chang @ 2020-05-14 9:21 UTC (permalink / raw)
To: linux-realtek-soc, afaerber
Cc: linus.walleij, linux-gpio, robh+dt, devicetree, linux-kernel
In-Reply-To: <20200514092125.6875-1-tychang@realtek.com>
Add missed pins and pin configs for Realtek DHC SoC RTD1195 pinctrl driver.
Signed-off-by: TY Chang <tychang@realtek.com>
---
drivers/pinctrl/pinctrl-rtd1195.h | 332 +++++++++++++++++++++++-------
1 file changed, 258 insertions(+), 74 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-rtd1195.h b/drivers/pinctrl/pinctrl-rtd1195.h
index 8eaab8a0dbf3..9f3471d02221 100644
--- a/drivers/pinctrl/pinctrl-rtd1195.h
+++ b/drivers/pinctrl/pinctrl-rtd1195.h
@@ -23,6 +23,11 @@ enum rtd1195_iso_pins {
RTD1195_ISO_ETN_LED_RXTX,
RTD1195_ISO_I2C_SCL_6,
RTD1195_ISO_I2C_SDA_6,
+ RTD1195_ISO_AI_LOC,
+ RTD1195_ISO_EJTAG_AVCPU_LOC,
+ RTD1195_ISO_UR1_LOC,
+ RTD1195_ISO_PWM_01_OPEN_DRAIN,
+ RTD1195_ISO_PWM_23_OPEN_DRAIN,
};
static const struct pinctrl_pin_desc rtd1195_iso_pins[] = {
@@ -47,6 +52,11 @@ static const struct pinctrl_pin_desc rtd1195_iso_pins[] = {
PINCTRL_PIN(RTD1195_ISO_ETN_LED_RXTX, "etn_led_rxtx"),
PINCTRL_PIN(RTD1195_ISO_I2C_SCL_6, "i2c_scl_6"),
PINCTRL_PIN(RTD1195_ISO_I2C_SDA_6, "i2c_sda_6"),
+ PINCTRL_PIN(RTD1195_ISO_AI_LOC, "ai_loc"),
+ PINCTRL_PIN(RTD1195_ISO_EJTAG_AVCPU_LOC, "ejtag_avcpu_loc"),
+ PINCTRL_PIN(RTD1195_ISO_UR1_LOC, "ur1_loc"),
+ PINCTRL_PIN(RTD1195_ISO_PWM_01_OPEN_DRAIN, "pwm_01_open_drain"),
+ PINCTRL_PIN(RTD1195_ISO_PWM_23_OPEN_DRAIN, "pwm_23_open_drain"),
};
static const unsigned int rtd1195_iso_gpio_0_pins[] = { RTD1195_ISO_GPIO_0 };
@@ -70,6 +80,12 @@ static const unsigned int rtd1195_etn_led_link_pins[] = { RTD1195_ISO_ETN_LED_LI
static const unsigned int rtd1195_etn_led_rxtx_pins[] = { RTD1195_ISO_ETN_LED_RXTX };
static const unsigned int rtd1195_i2c_scl_6_pins[] = { RTD1195_ISO_I2C_SCL_6 };
static const unsigned int rtd1195_i2c_sda_6_pins[] = { RTD1195_ISO_I2C_SDA_6 };
+static const unsigned int rtd1195_ai_loc_pins[] = { RTD1195_ISO_AI_LOC };
+static const unsigned int rtd1195_ejtag_avcpu_loc_pins[] = { RTD1195_ISO_EJTAG_AVCPU_LOC };
+static const unsigned int rtd1195_ur1_loc_pins[] = { RTD1195_ISO_UR1_LOC };
+static const unsigned int rtd1195_pwm_01_open_drain_pins[] = { RTD1195_ISO_PWM_01_OPEN_DRAIN };
+static const unsigned int rtd1195_pwm_23_open_drain_pins[] = { RTD1195_ISO_PWM_23_OPEN_DRAIN };
+
#define RTD1195_GROUP(_name) \
{ \
@@ -100,6 +116,11 @@ static const struct rtd119x_pin_group_desc rtd1195_iso_pin_groups[] = {
RTD1195_GROUP(etn_led_rxtx),
RTD1195_GROUP(i2c_scl_6),
RTD1195_GROUP(i2c_sda_6),
+ RTD1195_GROUP(ai_loc),
+ RTD1195_GROUP(ejtag_avcpu_loc),
+ RTD1195_GROUP(ur1_loc),
+ RTD1195_GROUP(pwm_01_open_drain),
+ RTD1195_GROUP(pwm_23_open_drain),
};
static const char * const rtd1195_iso_gpio_groups[] = {
@@ -112,13 +133,22 @@ static const char * const rtd1195_iso_gpio_groups[] = {
"etn_led_link", "etn_led_rxtx",
"i2c_scl_6", "i2c_sda_6",
};
-static const char * const rtd1195_iso_ai_groups[] = {
- "usb0", "usb1", "vfd_cs_n", "vfd_clk",
- "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n"
+static const char * const rtd1195_iso_ai_ur1_groups[] = {
+ "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n", "ai_loc"
+};
+
+static const char * const rtd1195_iso_ai_vfd_groups[] = {
+ "usb0", "usb1", "vfd_cs_n", "vfd_clk", "ai_loc"
+};
+
+static const char * const rtd1195_iso_avcpu_ejtag_iso_groups[] = {
+ "vfd_cs_n", "vfd_clk", "vfd_d", "usb0", "usb1", "ejtag_avcpu_loc"
};
-static const char * const rtd1195_iso_avcpu_ejtag_groups[] = {
- "vfd_cs_n", "vfd_clk", "vfd_d", "usb0", "usb1"
+static const char * const rtd1195_iso_avcpu_ejtag_misc_loc_groups[] = {
+ "ejtag_avcpu_loc"
};
+
+
static const char * const rtd1195_iso_etn_led_groups[] = { "etn_led_link", "etn_led_rxtx" };
static const char * const rtd1195_iso_i2c0_groups[] = { "i2c_scl_0", "i2c_sda_0" };
static const char * const rtd1195_iso_i2c2_groups[] = { "vfd_d" };
@@ -131,8 +161,16 @@ static const char * const rtd1195_iso_pwm_groups[] = {
};
static const char * const rtd1195_iso_standby_dbg_groups[] = { "ir_rx", "usb0", "usb1" };
static const char * const rtd1195_iso_uart0_groups[] = { "ur0_rx", "ur0_tx" };
-static const char * const rtd1195_iso_uart1_groups[] = { "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n" };
+static const char * const rtd1195_iso_uart1_groups[] = { "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n", "ur1_loc" };
+static const char * const rtd1195_iso_ur1_misc_groups[] = { "ur1_loc" };
static const char * const rtd1195_iso_vfd_groups[] = { "vfd_cs_n", "vfd_clk", "vfd_d" };
+static const char * const rtd1195_iso_pwm_01_normal_groups[] = { "pwm_01_open_drain" };
+static const char * const rtd1195_iso_pwm_23_normal_groups[] = { "pwm_23_open_drain" };
+static const char * const rtd1195_iso_pwm_01_open_drain_groups[] = { "pwm_01_open_drain" };
+static const char * const rtd1195_iso_pwm_23_open_drain_groups[] = { "pwm_23_open_drain" };
+
+
+
#define RTD1195_FUNC(_name) \
{ \
@@ -143,8 +181,10 @@ static const char * const rtd1195_iso_vfd_groups[] = { "vfd_cs_n", "vfd_clk", "v
static const struct rtd119x_pin_func_desc rtd1195_iso_pin_functions[] = {
RTD1195_FUNC(gpio),
- RTD1195_FUNC(ai),
- RTD1195_FUNC(avcpu_ejtag),
+ RTD1195_FUNC(ai_ur1),
+ RTD1195_FUNC(ai_vfd),
+ RTD1195_FUNC(avcpu_ejtag_iso),
+ RTD1195_FUNC(avcpu_ejtag_misc_loc),
RTD1195_FUNC(etn_led),
RTD1195_FUNC(i2c0),
RTD1195_FUNC(i2c2),
@@ -156,7 +196,12 @@ static const struct rtd119x_pin_func_desc rtd1195_iso_pin_functions[] = {
RTD1195_FUNC(standby_dbg),
RTD1195_FUNC(uart0),
RTD1195_FUNC(uart1),
+ RTD1195_FUNC(ur1_misc),
RTD1195_FUNC(vfd),
+ RTD1195_FUNC(pwm_01_normal),
+ RTD1195_FUNC(pwm_23_normal),
+ RTD1195_FUNC(pwm_01_open_drain),
+ RTD1195_FUNC(pwm_23_open_drain),
};
#undef RTD1195_FUNC
@@ -166,17 +211,17 @@ static const struct rtd119x_pin_desc rtd1195_iso_muxes[] = {
RTK_PIN_FUNC(0x0 << 0, "gpio"),
RTK_PIN_FUNC(0x1 << 0, "vfd"),
RTK_PIN_FUNC(0x2 << 0, "i2c2"),
- RTK_PIN_FUNC(0x3 << 0, "avcpu_ejtag")),
+ RTK_PIN_FUNC(0x3 << 0, "avcpu_ejtag_iso")),
RTK_PIN_MUX(vfd_clk, 0x10, GENMASK(3, 2),
RTK_PIN_FUNC(0x0 << 2, "gpio"),
RTK_PIN_FUNC(0x1 << 2, "vfd"),
- RTK_PIN_FUNC(0x2 << 2, "ai"),
- RTK_PIN_FUNC(0x3 << 2, "avcpu_ejtag")),
+ RTK_PIN_FUNC(0x2 << 2, "ai_vfd"),
+ RTK_PIN_FUNC(0x3 << 2, "avcpu_ejtag_iso")),
RTK_PIN_MUX(vfd_cs_n, 0x10, GENMASK(5, 4),
RTK_PIN_FUNC(0x0 << 4, "gpio"),
RTK_PIN_FUNC(0x1 << 4, "vfd"),
- RTK_PIN_FUNC(0x2 << 4, "ai"),
- RTK_PIN_FUNC(0x3 << 4, "avcpu_ejtag")),
+ RTK_PIN_FUNC(0x2 << 4, "ai_vfd"),
+ RTK_PIN_FUNC(0x3 << 4, "avcpu_ejtag_iso")),
RTK_PIN_MUX(ir_rx, 0x10, GENMASK(7, 6),
RTK_PIN_FUNC(0x0 << 6, "gpio"),
RTK_PIN_FUNC(0x1 << 6, "ir_rx"),
@@ -184,31 +229,31 @@ static const struct rtd119x_pin_desc rtd1195_iso_muxes[] = {
RTK_PIN_MUX(usb0, 0x10, GENMASK(9, 8),
RTK_PIN_FUNC(0x0 << 8, "gpio"),
RTK_PIN_FUNC(0x1 << 8, "standby_dbg"),
- RTK_PIN_FUNC(0x2 << 8, "ai"),
- RTK_PIN_FUNC(0x3 << 8, "avcpu_ejtag")),
+ RTK_PIN_FUNC(0x2 << 8, "ai_vfd"),
+ RTK_PIN_FUNC(0x3 << 8, "avcpu_ejtag_iso")),
RTK_PIN_MUX(usb1, 0x10, GENMASK(11, 10),
RTK_PIN_FUNC(0x0 << 10, "gpio"),
RTK_PIN_FUNC(0x1 << 10, "standby_dbg"),
- RTK_PIN_FUNC(0x2 << 10, "ai"),
- RTK_PIN_FUNC(0x3 << 10, "avcpu_ejtag")),
+ RTK_PIN_FUNC(0x2 << 10, "ai_vfd"),
+ RTK_PIN_FUNC(0x3 << 10, "avcpu_ejtag_iso")),
RTK_PIN_MUX(ur1_rx, 0x10, GENMASK(13, 12),
RTK_PIN_FUNC(0x0 << 12, "gpio"),
RTK_PIN_FUNC(0x1 << 12, "uart1"),
- RTK_PIN_FUNC(0x2 << 12, "ai"),
+ RTK_PIN_FUNC(0x2 << 12, "ai_ur1"),
RTK_PIN_FUNC(0x3 << 12, "pwm")),
RTK_PIN_MUX(ur1_tx, 0x10, GENMASK(15, 14),
RTK_PIN_FUNC(0x0 << 14, "gpio"),
RTK_PIN_FUNC(0x1 << 14, "uart1"),
- RTK_PIN_FUNC(0x2 << 14, "ai"),
+ RTK_PIN_FUNC(0x2 << 14, "ai_ur1"),
RTK_PIN_FUNC(0x3 << 14, "pwm")),
RTK_PIN_MUX(ur1_rts_n, 0x10, GENMASK(17, 16),
RTK_PIN_FUNC(0x0 << 16, "gpio"),
RTK_PIN_FUNC(0x1 << 16, "uart1"),
- RTK_PIN_FUNC(0x2 << 16, "ai")),
+ RTK_PIN_FUNC(0x2 << 16, "ai_ur1")),
RTK_PIN_MUX(ur1_cts_n, 0x10, GENMASK(19, 18),
RTK_PIN_FUNC(0x0 << 18, "gpio"),
RTK_PIN_FUNC(0x1 << 18, "uart1"),
- RTK_PIN_FUNC(0x2 << 18, "ai")),
+ RTK_PIN_FUNC(0x2 << 18, "ai_ur1")),
RTK_PIN_MUX(ur0_rx, 0x10, GENMASK(21, 20),
RTK_PIN_FUNC(0x0 << 20, "gpio"),
RTK_PIN_FUNC(0x1 << 20, "uart0"),
@@ -242,13 +287,44 @@ static const struct rtd119x_pin_desc rtd1195_iso_muxes[] = {
RTK_PIN_FUNC(0x0 << 4, "gpio"),
RTK_PIN_FUNC(0x1 << 4, "ir_tx"),
RTK_PIN_FUNC(0x2 << 4, "i2c3")),
- /* pwm_23_open_drain_switch */
- /* pwm_01_open_drain_switch */
- /* ur1_loc */
- /* ejtag_avcpu_loc */
- /* ai_loc */
+ RTK_PIN_MUX(pwm_23_open_drain, 0x14, GENMASK(24, 24),
+ RTK_PIN_FUNC(0x0 << 24, "pwm_23_normal"),
+ RTK_PIN_FUNC(0x1 << 24, "pwm_23_open_drain")),
+ RTK_PIN_MUX(pwm_01_open_drain, 0x14, GENMASK(25, 25),
+ RTK_PIN_FUNC(0x0 << 25, "pwm_01_normal"),
+ RTK_PIN_FUNC(0x1 << 25, "pwm_01_open_drain")),
+ RTK_PIN_MUX(ur1_loc, 0x14, GENMASK(27, 26),
+ RTK_PIN_FUNC(0x1 << 26, "uart1"),
+ RTK_PIN_FUNC(0x2 << 26, "ur1_misc")),
+ RTK_PIN_MUX(ejtag_avcpu_loc, 0x14, GENMASK(29, 28),
+ RTK_PIN_FUNC(0x1 << 28, "avcpu_ejtag_iso"),
+ RTK_PIN_FUNC(0x2 << 28, "avcpu_ejtag_misc_loc")),
+ RTK_PIN_MUX(ai_loc, 0x14, GENMASK(31, 30),
+ RTK_PIN_FUNC(0x1 << 30, "ai_ur1"),
+ RTK_PIN_FUNC(0x2 << 30, "ai_vfd")),
+};
+
+static const struct rtd119x_pin_config_desc rtd1195_iso_configs[] = {
+ RTK_PIN_CONFIG(ir_rx, 0x0, 8, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(vfd_cs_n, 0x0, 12, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(vfd_clk, 0x0, 16, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(vfd_d, 0x0, 20, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(i2c_sda_0, 0x0, 24, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(i2c_scl_0, 0x0, 28, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(ur1_rx, 0x4, 0, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(ur1_tx, 0x4, 4, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(ur1_rts_n, 0x4, 8, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(ur1_cts_n, 0x4, 12, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(ur0_rx, 0x4, 16, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(ur0_tx, 0x4, 20, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(etn_led_link, 0x4, 24, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(etn_led_rxtx, 0x4, 28, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(i2c_sda_6, 0x8, 12, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(i2c_scl_6, 0x8, 16, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(ir_tx, 0x8, 20, 1, 0, 2, 3, PADDRI_2_4),
};
+
static const struct rtd119x_pinctrl_desc rtd1195_iso_pinctrl_desc = {
.pins = rtd1195_iso_pins,
.num_pins = ARRAY_SIZE(rtd1195_iso_pins),
@@ -258,6 +334,8 @@ static const struct rtd119x_pinctrl_desc rtd1195_iso_pinctrl_desc = {
.num_functions = ARRAY_SIZE(rtd1195_iso_pin_functions),
.muxes = rtd1195_iso_muxes,
.num_muxes = ARRAY_SIZE(rtd1195_iso_muxes),
+ .configs = rtd1195_iso_configs,
+ .num_configs = ARRAY_SIZE(rtd1195_iso_configs),
};
/* CRT */
@@ -323,6 +401,9 @@ enum rtd1195_crt_pins {
RTD1195_SENSOR_RST,
RTD1195_SENSOR_STB_0,
RTD1195_SENSOR_STB_1,
+ RTD1195_EJTAG_SCPU_LOC,
+ RTD1195_HI_LOC,
+ RTD1195_AO_LOC,
};
static const struct pinctrl_pin_desc rtd1195_crt_pins[] = {
@@ -386,6 +467,9 @@ static const struct pinctrl_pin_desc rtd1195_crt_pins[] = {
PINCTRL_PIN(RTD1195_SENSOR_RST, "sensor_rst"),
PINCTRL_PIN(RTD1195_SENSOR_STB_0, "sensor_stb_0"),
PINCTRL_PIN(RTD1195_SENSOR_STB_1, "sensor_stb_1"),
+ PINCTRL_PIN(RTD1195_EJTAG_SCPU_LOC, "ejtag_scpu_loc"),
+ PINCTRL_PIN(RTD1195_HI_LOC, "hif_loc"),
+ PINCTRL_PIN(RTD1195_AO_LOC, "ao_loc"),
};
static const unsigned int rtd1195_gpio_0_pins[] = { RTD1195_GPIO_0 };
@@ -448,6 +532,14 @@ static const unsigned int rtd1195_sensor_cko_1_pins[] = { RTD1195_SENSOR_CKO_1 }
static const unsigned int rtd1195_sensor_rst_pins[] = { RTD1195_SENSOR_RST };
static const unsigned int rtd1195_sensor_stb_0_pins[] = { RTD1195_SENSOR_STB_0 };
static const unsigned int rtd1195_sensor_stb_1_pins[] = { RTD1195_SENSOR_STB_1 };
+static const unsigned int rtd1195_ejtag_scpu_loc_pins[] = { RTD1195_EJTAG_SCPU_LOC };
+static const unsigned int rtd1195_hif_loc_pins[] = { RTD1195_HI_LOC };
+static const unsigned int rtd1195_ao_loc_pins[] = { RTD1195_AO_LOC };
+
+
+
+
+
#define RTD1195_GROUP(_name) \
{ \
@@ -517,6 +609,9 @@ static const struct rtd119x_pin_group_desc rtd1195_crt_pin_groups[] = {
RTD1195_GROUP(sensor_rst),
RTD1195_GROUP(sensor_stb_0),
RTD1195_GROUP(sensor_stb_1),
+ RTD1195_GROUP(ejtag_scpu_loc),
+ RTD1195_GROUP(hif_loc),
+ RTD1195_GROUP(ao_loc),
};
static const char * const rtd1195_crt_gpio_groups[] = {
@@ -540,11 +635,16 @@ static const char * const rtd1195_crt_gpio_groups[] = {
"sensor_stb_0", "sensor_stb_1",
};
-static const char * const rtd1195_crt_ao_groups[] = {
- "gpio_4", "gpio_5", "gpio_6", "gpio_7",
- "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk",
+static const char * const rtd1195_crt_ao_tp0_groups[] = {
+ "tp0_data", "tp0_sync", "tp0_valid", "tp0_clk", "ao_loc"
+};
+
+static const char * const rtd1195_crt_ao_gpio_groups[] = {
+ "gpio_4", "gpio_5", "gpio_6", "gpio_7", "ao_loc"
};
-static const char * const rtd1195_crt_avcpu_ejtag_groups[] = {
+
+
+static const char * const rtd1195_crt_avcpu_ejtag_misc_groups[] = {
"nf_rdy", "nf_rd_n", "nf_dd_5", "nf_dd_6", "nf_dd_7"
};
static const char * const rtd1195_crt_cpu_loop_groups[] = { "usb_id" };
@@ -555,10 +655,15 @@ static const char * const rtd1195_crt_emmc_groups[] = {
static const char * const rtd1195_crt_gspi_groups[] = {
"gpio_0", "gpio_1", "gpio_2", "gpio_3",
};
-static const char * const rtd1195_crt_hif_groups[] = {
- "gpio_0", "gpio_1", "gpio_2", "gpio_3",
- "nf_dd_4", "nf_wr_n", "nf_ale", "nf_cle",
+static const char * const rtd1195_crt_hif_nf_groups[] = {
+ "nf_dd_4", "nf_wr_n", "nf_ale", "nf_cle", "hif_loc"
};
+
+static const char * const rtd1195_crt_hif_misc_groups[] = {
+ "gpio_0", "gpio_1", "gpio_2", "gpio_3", "hif_loc"
+};
+
+
static const char * const rtd1195_crt_i2c1_groups[] = { "i2c_scl_1", "i2c_sda_1" };
static const char * const rtd1195_crt_i2c2_groups[] = { "tp1_sync", "tp1_clk" };
static const char * const rtd1195_crt_i2c3_groups[] = { "tp1_data", "tp1_valid" };
@@ -572,9 +677,13 @@ static const char * const rtd1195_crt_nand_groups[] = {
"nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3", "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7",
"nf_rdy", "nf_rd_n", "nf_wr_n", "nf_ale", "nf_cle", "nf_ce_n_0", "nf_ce_n_1",
};
-static const char * const rtd1195_crt_scpu_ejtag_groups[] = {
- "mmc_data_0", "mmc_data_3", "mmc_clk", "mmc_cmd", "mmc_wp"
+static const char * const rtd1195_crt_scpu_ejtag_gpio_groups[] = {
+ "gpio_4", "gpio_5", "gpio_6", "gpio_7", "gpio_8", "ejtag_scpu_loc"
+};
+static const char * const rtd1195_crt_scpu_ejtag_cr_groups[] = {
+ "mmc_data_0", "mmc_data_3", "mmc_clk", "mmc_cmd", "mmc_wp", "ejtag_scpu_loc"
};
+
static const char * const rtd1195_crt_sdio_groups[] = {
"sdio_clk", "sdio_data_0", "sdio_data_1", "sdio_data_2", "sdio_data_3", "sdio_cmd",
};
@@ -598,12 +707,14 @@ static const char * const rtd1195_crt_usb_groups[] = { "sensor_cko_1" };
static const struct rtd119x_pin_func_desc rtd1195_crt_pin_functions[] = {
RTD1195_FUNC(gpio),
- RTD1195_FUNC(ao),
- RTD1195_FUNC(avcpu_ejtag),
+ RTD1195_FUNC(ao_tp0),
+ RTD1195_FUNC(ao_gpio),
+ RTD1195_FUNC(avcpu_ejtag_misc),
RTD1195_FUNC(cpu_loop),
RTD1195_FUNC(emmc),
RTD1195_FUNC(gspi),
- RTD1195_FUNC(hif),
+ RTD1195_FUNC(hif_misc),
+ RTD1195_FUNC(hif_nf),
RTD1195_FUNC(i2c1),
RTD1195_FUNC(i2c2),
RTD1195_FUNC(i2c3),
@@ -611,7 +722,8 @@ static const struct rtd119x_pin_func_desc rtd1195_crt_pin_functions[] = {
RTD1195_FUNC(i2c5),
RTD1195_FUNC(mmc),
RTD1195_FUNC(nand),
- RTD1195_FUNC(scpu_ejtag),
+ RTD1195_FUNC(scpu_ejtag_gpio),
+ RTD1195_FUNC(scpu_ejtag_cr),
RTD1195_FUNC(sdio),
RTD1195_FUNC(sensor),
RTD1195_FUNC(spdif),
@@ -628,27 +740,27 @@ static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = {
RTK_PIN_FUNC(0x0 << 2, "gpio"),
RTK_PIN_FUNC(0x1 << 2, "nand"),
RTK_PIN_FUNC(0x2 << 2, "emmc"),
- RTK_PIN_FUNC(0x3 << 2, "avcpu_ejtag")),
+ RTK_PIN_FUNC(0x3 << 2, "avcpu_ejtag_misc")),
RTK_PIN_MUX(nf_rd_n, 0x60, GENMASK(5, 4),
RTK_PIN_FUNC(0x0 << 4, "gpio"),
RTK_PIN_FUNC(0x1 << 4, "nand"),
RTK_PIN_FUNC(0x2 << 4, "emmc"),
- RTK_PIN_FUNC(0x3 << 4, "avcpu_ejtag")),
+ RTK_PIN_FUNC(0x3 << 4, "avcpu_ejtag_misc")),
RTK_PIN_MUX(nf_wr_n, 0x60, GENMASK(7, 6),
RTK_PIN_FUNC(0x0 << 6, "gpio"),
RTK_PIN_FUNC(0x1 << 6, "nand"),
RTK_PIN_FUNC(0x2 << 6, "emmc"),
- RTK_PIN_FUNC(0x3 << 6, "hif")),
+ RTK_PIN_FUNC(0x3 << 6, "hif_nf")),
RTK_PIN_MUX(nf_ale, 0x60, GENMASK(9, 8),
RTK_PIN_FUNC(0x0 << 8, "gpio"),
RTK_PIN_FUNC(0x1 << 8, "nand"),
RTK_PIN_FUNC(0x2 << 8, "emmc"),
- RTK_PIN_FUNC(0x3 << 8, "hif")),
+ RTK_PIN_FUNC(0x3 << 8, "hif_nf")),
RTK_PIN_MUX(nf_cle, 0x60, GENMASK(11, 10),
RTK_PIN_FUNC(0x0 << 10, "gpio"),
RTK_PIN_FUNC(0x1 << 10, "nand"),
RTK_PIN_FUNC(0x2 << 10, "emmc"),
- RTK_PIN_FUNC(0x3 << 10, "hif")),
+ RTK_PIN_FUNC(0x3 << 10, "hif_nf")),
RTK_PIN_MUX(nf_ce_n_0, 0x60, GENMASK(13, 12),
RTK_PIN_FUNC(0x0 << 12, "gpio"),
RTK_PIN_FUNC(0x1 << 12, "nand")),
@@ -675,22 +787,22 @@ static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = {
RTK_PIN_FUNC(0x0 << 24, "gpio"),
RTK_PIN_FUNC(0x1 << 24, "nand"),
RTK_PIN_FUNC(0x2 << 24, "emmc"),
- RTK_PIN_FUNC(0x3 << 24, "hif")),
+ RTK_PIN_FUNC(0x3 << 24, "hif_nf")),
RTK_PIN_MUX(nf_dd_5, 0x60, GENMASK(27, 26),
RTK_PIN_FUNC(0x0 << 26, "gpio"),
RTK_PIN_FUNC(0x1 << 26, "nand"),
RTK_PIN_FUNC(0x2 << 26, "emmc"),
- RTK_PIN_FUNC(0x3 << 26, "avcpu_ejtag")),
+ RTK_PIN_FUNC(0x3 << 26, "avcpu_ejtag_misc")),
RTK_PIN_MUX(nf_dd_6, 0x60, GENMASK(29, 28),
RTK_PIN_FUNC(0x0 << 28, "gpio"),
RTK_PIN_FUNC(0x1 << 28, "nand"),
RTK_PIN_FUNC(0x2 << 28, "emmc"),
- RTK_PIN_FUNC(0x3 << 28, "avcpu_ejtag")),
+ RTK_PIN_FUNC(0x3 << 28, "avcpu_ejtag_misc")),
RTK_PIN_MUX(nf_dd_7, 0x60, GENMASK(31, 30),
RTK_PIN_FUNC(0x0 << 30, "gpio"),
RTK_PIN_FUNC(0x1 << 30, "nand"),
RTK_PIN_FUNC(0x2 << 30, "emmc"),
- RTK_PIN_FUNC(0x3 << 30, "avcpu_ejtag")),
+ RTK_PIN_FUNC(0x3 << 30, "avcpu_ejtag_misc")),
RTK_PIN_MUX(sdio_cmd, 0x64, GENMASK(1, 0),
RTK_PIN_FUNC(0x0 << 0, "gpio"),
@@ -714,22 +826,22 @@ static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = {
RTK_PIN_MUX(mmc_cmd, 0x64, GENMASK(17, 16),
RTK_PIN_FUNC(0x0 << 16, "gpio"),
RTK_PIN_FUNC(0x1 << 16, "mmc"),
- RTK_PIN_FUNC(0x3 << 16, "scpu_ejtag")),
+ RTK_PIN_FUNC(0x3 << 16, "scpu_ejtag_cr")),
RTK_PIN_MUX(mmc_clk, 0x64, GENMASK(19, 18),
RTK_PIN_FUNC(0x0 << 18, "gpio"),
RTK_PIN_FUNC(0x1 << 18, "mmc"),
- RTK_PIN_FUNC(0x3 << 18, "scpu_ejtag")),
+ RTK_PIN_FUNC(0x3 << 18, "scpu_ejtag_cr")),
RTK_PIN_MUX(mmc_wp, 0x64, GENMASK(21, 20),
RTK_PIN_FUNC(0x0 << 20, "gpio"),
RTK_PIN_FUNC(0x1 << 20, "mmc"),
- RTK_PIN_FUNC(0x3 << 20, "scpu_ejtag")),
+ RTK_PIN_FUNC(0x3 << 20, "scpu_ejtag_cr")),
RTK_PIN_MUX(mmc_cd, 0x64, GENMASK(23, 22),
RTK_PIN_FUNC(0x0 << 22, "gpio"),
RTK_PIN_FUNC(0x1 << 22, "mmc")),
RTK_PIN_MUX(mmc_data_0, 0x64, GENMASK(25, 24),
RTK_PIN_FUNC(0x0 << 24, "gpio"),
RTK_PIN_FUNC(0x1 << 24, "mmc"),
- RTK_PIN_FUNC(0x3 << 24, "scpu_ejtag")),
+ RTK_PIN_FUNC(0x3 << 24, "scpu_ejtag_cr")),
RTK_PIN_MUX(mmc_data_1, 0x64, GENMASK(27, 26),
RTK_PIN_FUNC(0x0 << 26, "gpio"),
RTK_PIN_FUNC(0x1 << 26, "mmc")),
@@ -739,28 +851,28 @@ static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = {
RTK_PIN_MUX(mmc_data_3, 0x64, GENMASK(31, 30),
RTK_PIN_FUNC(0x0 << 30, "gpio"),
RTK_PIN_FUNC(0x1 << 30, "mmc"),
- RTK_PIN_FUNC(0x3 << 30, "scpu_ejtag")),
+ RTK_PIN_FUNC(0x3 << 30, "scpu_ejtag_cr")),
RTK_PIN_MUX(tp0_data, 0x68, GENMASK(1, 0),
RTK_PIN_FUNC(0x0 << 0, "tp0"),
RTK_PIN_FUNC(0x1 << 0, "tp1"),
RTK_PIN_FUNC(0x2 << 0, "gpio"),
- RTK_PIN_FUNC(0x3 << 0, "ao")),
+ RTK_PIN_FUNC(0x3 << 0, "ao_tp0")),
RTK_PIN_MUX(tp0_sync, 0x68, GENMASK(3, 2),
RTK_PIN_FUNC(0x0 << 2, "tp0"),
RTK_PIN_FUNC(0x1 << 2, "tp1"),
RTK_PIN_FUNC(0x2 << 2, "gpio"),
- RTK_PIN_FUNC(0x3 << 2, "ao")),
+ RTK_PIN_FUNC(0x3 << 2, "ao_tp0")),
RTK_PIN_MUX(tp0_valid, 0x68, GENMASK(5, 4),
RTK_PIN_FUNC(0x0 << 4, "tp0"),
RTK_PIN_FUNC(0x1 << 4, "tp1"),
RTK_PIN_FUNC(0x2 << 4, "gpio"),
- RTK_PIN_FUNC(0x3 << 4, "ao")),
+ RTK_PIN_FUNC(0x3 << 4, "ao_tp0")),
RTK_PIN_MUX(tp0_clk, 0x68, GENMASK(7, 6),
RTK_PIN_FUNC(0x0 << 6, "tp0"),
RTK_PIN_FUNC(0x1 << 6, "tp1"),
RTK_PIN_FUNC(0x2 << 6, "gpio"),
- RTK_PIN_FUNC(0x3 << 6, "ao")),
+ RTK_PIN_FUNC(0x3 << 6, "ao_tp0")),
RTK_PIN_MUX(tp1_data, 0x68, GENMASK(17, 16),
RTK_PIN_FUNC(0x0 << 16, "tp1"),
RTK_PIN_FUNC(0x1 << 16, "tp0"),
@@ -810,8 +922,12 @@ static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = {
RTK_PIN_MUX(usb_id, 0x6c, GENMASK(17, 16),
RTK_PIN_FUNC(0x1 << 16, "gpio"),
RTK_PIN_FUNC(0x2 << 16, "cpu_loop")),
- /* hi_loc */
- /* ejtag_scpu_loc */
+ RTK_PIN_MUX(hif_loc, 0x6c, GENMASK(19, 18),
+ RTK_PIN_FUNC(0x1 << 18, "hif_misc"),
+ RTK_PIN_FUNC(0x2 << 18, "hif_nf")),
+ RTK_PIN_MUX(ejtag_scpu_loc, 0x6c, GENMASK(21, 20),
+ RTK_PIN_FUNC(0x1 << 20, "scpu_ejtag_gpio"),
+ RTK_PIN_FUNC(0x2 << 20, "scpu_ejtag_cr")),
RTK_PIN_MUX(sensor_stb_1, 0x6c, GENMASK(23, 22),
RTK_PIN_FUNC(0x0 << 22, "gpio")),
RTK_PIN_MUX(sensor_stb_0, 0x6c, GENMASK(25, 24),
@@ -829,47 +945,113 @@ static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = {
RTK_PIN_MUX(gpio_0, 0x70, GENMASK(2, 0),
RTK_PIN_FUNC(0x1 << 0, "gpio"),
RTK_PIN_FUNC(0x2 << 0, "uart1"),
- RTK_PIN_FUNC(0x3 << 0, "hif"),
+ RTK_PIN_FUNC(0x3 << 0, "hif_misc"),
RTK_PIN_FUNC(0x4 << 0, "gspi")),
RTK_PIN_MUX(gpio_1, 0x70, GENMASK(5, 3),
RTK_PIN_FUNC(0x1 << 3, "gpio"),
RTK_PIN_FUNC(0x2 << 3, "uart1"),
- RTK_PIN_FUNC(0x3 << 3, "hif"),
+ RTK_PIN_FUNC(0x3 << 3, "hif_misc"),
RTK_PIN_FUNC(0x4 << 3, "gspi")),
RTK_PIN_MUX(gpio_2, 0x70, GENMASK(8, 6),
RTK_PIN_FUNC(0x1 << 6, "gpio"),
RTK_PIN_FUNC(0x2 << 6, "uart1"),
- RTK_PIN_FUNC(0x3 << 6, "hif"),
+ RTK_PIN_FUNC(0x3 << 6, "hif_misc"),
RTK_PIN_FUNC(0x4 << 6, "gspi")),
RTK_PIN_MUX(gpio_3, 0x70, GENMASK(11, 9),
RTK_PIN_FUNC(0x1 << 9, "gpio"),
RTK_PIN_FUNC(0x2 << 9, "uart1"),
- RTK_PIN_FUNC(0x3 << 9, "hif"),
+ RTK_PIN_FUNC(0x3 << 9, "hif_misc"),
RTK_PIN_FUNC(0x4 << 9, "gspi")),
RTK_PIN_MUX(gpio_4, 0x70, GENMASK(13, 12),
RTK_PIN_FUNC(0x1 << 12, "gpio"),
- RTK_PIN_FUNC(0x2 << 12, "scpu_ejtag"),
- RTK_PIN_FUNC(0x3 << 12, "ao")),
+ RTK_PIN_FUNC(0x2 << 12, "scpu_ejtag_gpio"),
+ RTK_PIN_FUNC(0x3 << 12, "ao_gpio")),
RTK_PIN_MUX(gpio_5, 0x70, GENMASK(15, 14),
RTK_PIN_FUNC(0x1 << 14, "gpio"),
- RTK_PIN_FUNC(0x2 << 14, "scpu_ejtag"),
- RTK_PIN_FUNC(0x3 << 14, "ao")),
+ RTK_PIN_FUNC(0x2 << 14, "scpu_ejtag_gpio"),
+ RTK_PIN_FUNC(0x3 << 14, "ao_gpio")),
RTK_PIN_MUX(gpio_6, 0x70, GENMASK(17, 16),
RTK_PIN_FUNC(0x1 << 16, "gpio"),
- RTK_PIN_FUNC(0x2 << 16, "scpu_ejtag"),
- RTK_PIN_FUNC(0x3 << 16, "ao")),
+ RTK_PIN_FUNC(0x2 << 16, "scpu_ejtag_gpio"),
+ RTK_PIN_FUNC(0x3 << 16, "ao_gpio")),
RTK_PIN_MUX(gpio_7, 0x70, GENMASK(19, 18),
RTK_PIN_FUNC(0x1 << 18, "gpio"),
- RTK_PIN_FUNC(0x2 << 18, "scpu_ejtag"),
- RTK_PIN_FUNC(0x3 << 18, "ao")),
+ RTK_PIN_FUNC(0x2 << 18, "scpu_ejtag_gpio"),
+ RTK_PIN_FUNC(0x3 << 18, "ao_gpio")),
RTK_PIN_MUX(gpio_8, 0x70, GENMASK(21, 20),
RTK_PIN_FUNC(0x1 << 20, "gpio"),
- RTK_PIN_FUNC(0x2 << 20, "scpu_ejtag")),
+ RTK_PIN_FUNC(0x2 << 20, "scpu_ejtag_gpio")),
+ RTK_PIN_MUX(ao_loc, 0x74, GENMASK(3, 2),
+ RTK_PIN_FUNC(0x1 << 2, "ao_tp0"),
+ RTK_PIN_FUNC(0x2 << 2, "ao_gpio")),
+};
- /* sf_en */
- /* ao_loc */
+static const struct rtd119x_pin_config_desc rtd1195_crt_configs[] = {
+ RTK_PIN_CONFIG(nf_ale, 0x78, 4, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(nf_ce_n_0, 0x78, 8, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(nf_ce_n_1, 0x78, 12, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(nf_rdy, 0x78, 16, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(nf_rd_n, 0x78, 20, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(nf_wr_n, 0x78, 24, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(nf_cle, 0x78, 28, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(nf_dd_0, 0x7c, 0, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(nf_dd_1, 0x7c, 4, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(nf_dd_2, 0x7c, 8, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(nf_dd_3, 0x7c, 12, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(nf_dd_4, 0x7c, 16, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(nf_dd_5, 0x7c, 20, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(nf_dd_6, 0x7c, 24, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(nf_dd_7, 0x7c, 28, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(mmc_cmd, 0x80, 0, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(mmc_clk, 0x80, 4, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(mmc_wp, 0x80, 8, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(mmc_cd, 0x80, 12, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(mmc_data_0, 0x80, 16, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(mmc_data_1, 0x80, 20, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(mmc_data_2, 0x80, 24, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(mmc_data_3, 0x80, 28, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(sdio_cmd, 0x84, 0, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(sdio_clk, 0x84, 4, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(sdio_wp, 0x84, 8, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(sdio_cd, 0x84, 12, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(sdio_data_0, 0x84, 16, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(sdio_data_1, 0x84, 20, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(sdio_data_2, 0x84, 24, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(sdio_data_3, 0x84, 28, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(spdif, 0x88, 0, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(tp0_clk, 0x8c, 0, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(tp0_sync, 0x8c, 4, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(tp0_valid, 0x8c, 8, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(tp0_data, 0x8c, 12, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(tp1_clk, 0x90, 0, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(tp1_sync, 0x90, 4, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(tp1_valid, 0x90, 8, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(tp1_data, 0x90, 12, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(i2c_sda_1, 0x94, 0, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(i2c_scl_1, 0x94, 4, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(i2c_sda_4, 0x94, 8, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(i2c_scl_4, 0x94, 12, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(i2c_sda_5, 0x94, 16, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(i2c_scl_5, 0x94, 20, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(gpio_0, 0x98, 0, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(gpio_1, 0x98, 4, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(gpio_2, 0x98, 8, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(gpio_3, 0x98, 12, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(gpio_4, 0x98, 16, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(gpio_5, 0x98, 20, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(gpio_6, 0x98, 24, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(gpio_7, 0x98, 28, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(gpio_8, 0x9c, 0, 1, 0, 2, 3, PADDRI_4_8),
+ RTK_PIN_CONFIG(hdmi_hpd, 0x9c, 4, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(usb_id, 0x9c, 8, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(sensor_stb_0, 0x9c, 12, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(sensor_stb_1, 0x9c, 16, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(sensor_rst, 0x9c, 20, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(sensor_cko_0, 0x9c, 24, 1, 0, 2, 3, PADDRI_2_4),
+ RTK_PIN_CONFIG(sensor_cko_1, 0x9c, 28, 1, 0, 2, 3, PADDRI_2_4),
};
+
static const struct rtd119x_pinctrl_desc rtd1195_crt_pinctrl_desc = {
.pins = rtd1195_crt_pins,
.num_pins = ARRAY_SIZE(rtd1195_crt_pins),
@@ -879,6 +1061,8 @@ static const struct rtd119x_pinctrl_desc rtd1195_crt_pinctrl_desc = {
.num_functions = ARRAY_SIZE(rtd1195_crt_pin_functions),
.muxes = rtd1195_crt_muxes,
.num_muxes = ARRAY_SIZE(rtd1195_crt_muxes),
+ .configs = rtd1195_crt_configs,
+ .num_configs = ARRAY_SIZE(rtd1195_crt_configs),
};
#endif
--
2.26.2
^ permalink raw reply related
* [PATCH 6/7] pinctrl: realtek: DHC: Move pinctrl drivers to realtek directory and rename.
From: TY Chang @ 2020-05-14 9:21 UTC (permalink / raw)
To: linux-realtek-soc, afaerber
Cc: linus.walleij, linux-gpio, robh+dt, devicetree, linux-kernel
In-Reply-To: <20200514092125.6875-1-tychang@realtek.com>
Move Realtek DHC SoC pinctrl drivers to realtek directory and
rename pinctrl-rtd119x.c to pinctrl-rtd.c.
Signed-off-by: TY Chang <tychang@realtek.com>
---
drivers/pinctrl/Kconfig | 10 +-
drivers/pinctrl/Makefile | 2 +-
drivers/pinctrl/realtek/Kconfig | 14 ++
drivers/pinctrl/realtek/Makefile | 3 +
.../pinctrl-rtd.c} | 166 +++++++++---------
.../pinctrl/{ => realtek}/pinctrl-rtd1195.h | 20 +--
.../pinctrl/{ => realtek}/pinctrl-rtd1295.h | 40 ++---
7 files changed, 132 insertions(+), 123 deletions(-)
create mode 100644 drivers/pinctrl/realtek/Kconfig
create mode 100644 drivers/pinctrl/realtek/Makefile
rename drivers/pinctrl/{pinctrl-rtd119x.c => realtek/pinctrl-rtd.c} (69%)
rename drivers/pinctrl/{ => realtek}/pinctrl-rtd1195.h (98%)
rename drivers/pinctrl/{ => realtek}/pinctrl-rtd1295.h (98%)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 311fe1eafe76..a3e1d45a604c 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -198,15 +198,6 @@ config PINCTRL_OXNAS
select GPIOLIB_IRQCHIP
select MFD_SYSCON
-config PINCTRL_REALTEK
- bool "Realtek RTD129x pinctrl driver"
- depends on OF
- depends on ARCH_REALTEK || COMPILE_TEST
- select GENERIC_PINCONF
- select PINMUX
- help
- This selects pinctrl driver for Realtek RTD1295 platforms.
-
config PINCTRL_ROCKCHIP
bool
select PINMUX
@@ -430,6 +421,7 @@ source "drivers/pinctrl/mediatek/Kconfig"
source "drivers/pinctrl/zte/Kconfig"
source "drivers/pinctrl/meson/Kconfig"
source "drivers/pinctrl/cirrus/Kconfig"
+source "drivers/pinctrl/realtek/Kconfig"
config PINCTRL_XWAY
bool
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index d4bec880c9bc..2bda2e19da8b 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -27,7 +27,6 @@ obj-$(CONFIG_PINCTRL_OXNAS) += pinctrl-oxnas.o
obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
-obj-$(CONFIG_PINCTRL_REALTEK) += pinctrl-rtd119x.o
obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o
obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o
@@ -73,3 +72,4 @@ obj-$(CONFIG_ARCH_VT8500) += vt8500/
obj-y += mediatek/
obj-$(CONFIG_PINCTRL_ZX) += zte/
obj-y += cirrus/
+obj-y += realtek/
\ No newline at end of file
diff --git a/drivers/pinctrl/realtek/Kconfig b/drivers/pinctrl/realtek/Kconfig
new file mode 100644
index 000000000000..12c05799d223
--- /dev/null
+++ b/drivers/pinctrl/realtek/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config PINCTRL_REALTEK_DHC
+ bool "Realtek DHC pinctrl driver"
+ depends on OF
+ depends on ARCH_REALTEK || COMPILE_TEST
+ select GENERIC_PINCONF
+ select PINMUX
+ help
+ This is the pinctrl, pinmux, pinconf driver for
+ Realtek DHC SoC platforms.
+
+
+
diff --git a/drivers/pinctrl/realtek/Makefile b/drivers/pinctrl/realtek/Makefile
new file mode 100644
index 000000000000..0d18245ead77
--- /dev/null
+++ b/drivers/pinctrl/realtek/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+# Realtek pin control drivers
+obj-$(CONFIG_PINCTRL_REALTEK_DHC) += pinctrl-rtd.o
diff --git a/drivers/pinctrl/pinctrl-rtd119x.c b/drivers/pinctrl/realtek/pinctrl-rtd.c
similarity index 69%
rename from drivers/pinctrl/pinctrl-rtd119x.c
rename to drivers/pinctrl/realtek/pinctrl-rtd.c
index bda0d1328eb8..4d9740f875ff 100644
--- a/drivers/pinctrl/pinctrl-rtd119x.c
+++ b/drivers/pinctrl/realtek/pinctrl-rtd.c
@@ -19,27 +19,27 @@
#include <linux/pinctrl/pinmux.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
-#include "core.h"
-#include "pinctrl-utils.h"
+#include "../core.h"
+#include "../pinctrl-utils.h"
-struct rtd119x_pin_group_desc {
+struct rtd_pin_group_desc {
const char *name;
const unsigned int *pins;
unsigned int num_pins;
};
-struct rtd119x_pin_func_desc {
+struct rtd_pin_func_desc {
const char *name;
const char * const *groups;
unsigned int num_groups;
};
-struct rtd119x_pin_mux_desc {
+struct rtd_pin_mux_desc {
const char *name;
u32 mux_value;
};
-struct rtd119x_pin_config_desc {
+struct rtd_pin_config_desc {
const char *name;
unsigned int reg_offset;
unsigned int base_bit;
@@ -50,11 +50,11 @@ struct rtd119x_pin_config_desc {
unsigned int curr_type;
};
-struct rtd119x_pin_desc {
+struct rtd_pin_desc {
const char *name;
unsigned int mux_offset;
u32 mux_mask;
- const struct rtd119x_pin_mux_desc *functions;
+ const struct rtd_pin_mux_desc *functions;
};
#define RTK_PIN_CONFIG(_name, _reg_off, _base_bit, _pud_en_off, \
@@ -76,7 +76,7 @@ struct rtd119x_pin_desc {
.name = # _name, \
.mux_offset = _mux_off, \
.mux_mask = _mux_mask, \
- .functions = (const struct rtd119x_pin_mux_desc []) { \
+ .functions = (const struct rtd_pin_mux_desc []) { \
__VA_ARGS__, { } \
}, \
}
@@ -87,16 +87,16 @@ struct rtd119x_pin_desc {
.mux_value = _mux_val, \
}
-struct rtd119x_pinctrl_desc {
+struct rtd_pinctrl_desc {
const struct pinctrl_pin_desc *pins;
unsigned int num_pins;
- const struct rtd119x_pin_group_desc *groups;
+ const struct rtd_pin_group_desc *groups;
unsigned int num_groups;
- const struct rtd119x_pin_func_desc *functions;
+ const struct rtd_pin_func_desc *functions;
unsigned int num_functions;
- const struct rtd119x_pin_desc *muxes;
+ const struct rtd_pin_desc *muxes;
unsigned int num_muxes;
- const struct rtd119x_pin_config_desc *configs;
+ const struct rtd_pin_config_desc *configs;
unsigned int num_configs;
};
@@ -108,33 +108,33 @@ struct rtd119x_pinctrl_desc {
#include "pinctrl-rtd1195.h"
#include "pinctrl-rtd1295.h"
-struct rtd119x_pinctrl {
+struct rtd_pinctrl {
struct pinctrl_dev *pcdev;
void __iomem *base;
struct pinctrl_desc desc;
- const struct rtd119x_pinctrl_desc *info;
+ const struct rtd_pinctrl_desc *info;
};
-static int rtd119x_pinctrl_get_groups_count(struct pinctrl_dev *pcdev)
+static int rtd_pinctrl_get_groups_count(struct pinctrl_dev *pcdev)
{
- struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+ struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
return data->info->num_groups;
}
-static const char *rtd119x_pinctrl_get_group_name(struct pinctrl_dev *pcdev,
+static const char *rtd_pinctrl_get_group_name(struct pinctrl_dev *pcdev,
unsigned int selector)
{
- struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+ struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
return data->info->groups[selector].name;
}
-static int rtd119x_pinctrl_get_group_pins(struct pinctrl_dev *pcdev,
+static int rtd_pinctrl_get_group_pins(struct pinctrl_dev *pcdev,
unsigned int selector, const unsigned int **pins,
unsigned int *num_pins)
{
- struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+ struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
*pins = data->info->groups[selector].pins;
*num_pins = data->info->groups[selector].num_pins;
@@ -142,34 +142,34 @@ static int rtd119x_pinctrl_get_group_pins(struct pinctrl_dev *pcdev,
return 0;
}
-static const struct pinctrl_ops rtd119x_pinctrl_ops = {
+static const struct pinctrl_ops rtd_pinctrl_ops = {
.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
.dt_free_map = pinctrl_utils_free_map,
- .get_groups_count = rtd119x_pinctrl_get_groups_count,
- .get_group_name = rtd119x_pinctrl_get_group_name,
- .get_group_pins = rtd119x_pinctrl_get_group_pins,
+ .get_groups_count = rtd_pinctrl_get_groups_count,
+ .get_group_name = rtd_pinctrl_get_group_name,
+ .get_group_pins = rtd_pinctrl_get_group_pins,
};
-static int rtd119x_pinctrl_get_functions_count(struct pinctrl_dev *pcdev)
+static int rtd_pinctrl_get_functions_count(struct pinctrl_dev *pcdev)
{
- struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+ struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
return data->info->num_functions;
}
-static const char *rtd119x_pinctrl_get_function_name(struct pinctrl_dev *pcdev,
+static const char *rtd_pinctrl_get_function_name(struct pinctrl_dev *pcdev,
unsigned int selector)
{
- struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+ struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
return data->info->functions[selector].name;
}
-static int rtd119x_pinctrl_get_function_groups(struct pinctrl_dev *pcdev,
+static int rtd_pinctrl_get_function_groups(struct pinctrl_dev *pcdev,
unsigned int selector, const char * const **groups,
unsigned int * const num_groups)
{
- struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+ struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
*groups = data->info->functions[selector].groups;
*num_groups = data->info->functions[selector].num_groups;
@@ -177,8 +177,8 @@ static int rtd119x_pinctrl_get_function_groups(struct pinctrl_dev *pcdev,
return 0;
}
-static const struct pinctrl_pin_desc *rtd119x_pinctrl_get_pin_by_number(
- struct rtd119x_pinctrl *data, int number)
+static const struct pinctrl_pin_desc *rtd_pinctrl_get_pin_by_number(
+ struct rtd_pinctrl *data, int number)
{
int i;
@@ -190,8 +190,8 @@ static const struct pinctrl_pin_desc *rtd119x_pinctrl_get_pin_by_number(
return NULL;
}
-static const struct rtd119x_pin_desc *rtd119x_pinctrl_find_mux(
- struct rtd119x_pinctrl *data, const char *name)
+static const struct rtd_pin_desc *rtd_pinctrl_find_mux(
+ struct rtd_pinctrl *data, const char *name)
{
int i;
@@ -203,8 +203,8 @@ static const struct rtd119x_pin_desc *rtd119x_pinctrl_find_mux(
return NULL;
}
-static const struct rtd119x_pin_config_desc *rtd119x_pinctrl_find_config(
- struct rtd119x_pinctrl *data, const char *name)
+static const struct rtd_pin_config_desc *rtd_pinctrl_find_config(
+ struct rtd_pinctrl *data, const char *name)
{
int i;
@@ -217,23 +217,23 @@ static const struct rtd119x_pin_config_desc *rtd119x_pinctrl_find_config(
}
-static int rtd119x_pinctrl_set_one_mux(struct pinctrl_dev *pcdev,
+static int rtd_pinctrl_set_one_mux(struct pinctrl_dev *pcdev,
unsigned int pin, const char *func_name)
{
- struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+ struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
const struct pinctrl_pin_desc *pin_desc;
- const struct rtd119x_pin_desc *mux;
+ const struct rtd_pin_desc *mux;
const char *pin_name;
u32 val;
int i;
- pin_desc = rtd119x_pinctrl_get_pin_by_number(data, pin);
+ pin_desc = rtd_pinctrl_get_pin_by_number(data, pin);
if (!pin_desc)
return -ENOTSUPP;
pin_name = pin_desc->name;
- mux = rtd119x_pinctrl_find_mux(data, pin_name);
+ mux = rtd_pinctrl_find_mux(data, pin_name);
if (!mux)
return -ENOTSUPP;
@@ -259,10 +259,10 @@ static int rtd119x_pinctrl_set_one_mux(struct pinctrl_dev *pcdev,
return -EINVAL;
}
-static int rtd119x_pinctrl_set_mux(struct pinctrl_dev *pcdev,
+static int rtd_pinctrl_set_mux(struct pinctrl_dev *pcdev,
unsigned int function, unsigned int group)
{
- struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+ struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
const unsigned int *pins;
unsigned int num_pins;
const char *func_name;
@@ -272,7 +272,7 @@ static int rtd119x_pinctrl_set_mux(struct pinctrl_dev *pcdev,
func_name = data->info->functions[function].name;
group_name = data->info->groups[group].name;
- ret = rtd119x_pinctrl_get_group_pins(pcdev, group, &pins, &num_pins);
+ ret = rtd_pinctrl_get_group_pins(pcdev, group, &pins, &num_pins);
if (ret) {
dev_err(pcdev->dev, "Getting pins for group %s failed\n",
group_name);
@@ -280,7 +280,7 @@ static int rtd119x_pinctrl_set_mux(struct pinctrl_dev *pcdev,
}
for (i = 0; i < num_pins; i++) {
- ret = rtd119x_pinctrl_set_one_mux(pcdev, pins[i], func_name);
+ ret = rtd_pinctrl_set_one_mux(pcdev, pins[i], func_name);
if (ret)
return ret;
}
@@ -288,22 +288,22 @@ static int rtd119x_pinctrl_set_mux(struct pinctrl_dev *pcdev,
return 0;
}
-static int rtd119x_pinctrl_gpio_request_enable(struct pinctrl_dev *pcdev,
+static int rtd_pinctrl_gpio_request_enable(struct pinctrl_dev *pcdev,
struct pinctrl_gpio_range *range, unsigned int offset)
{
- return rtd119x_pinctrl_set_one_mux(pcdev, offset, "gpio");
+ return rtd_pinctrl_set_one_mux(pcdev, offset, "gpio");
}
-static const struct pinmux_ops rtd119x_pinmux_ops = {
- .get_functions_count = rtd119x_pinctrl_get_functions_count,
- .get_function_name = rtd119x_pinctrl_get_function_name,
- .get_function_groups = rtd119x_pinctrl_get_function_groups,
- .set_mux = rtd119x_pinctrl_set_mux,
- .gpio_request_enable = rtd119x_pinctrl_gpio_request_enable,
+static const struct pinmux_ops rtd_pinmux_ops = {
+ .get_functions_count = rtd_pinctrl_get_functions_count,
+ .get_function_name = rtd_pinctrl_get_function_name,
+ .get_function_groups = rtd_pinctrl_get_function_groups,
+ .set_mux = rtd_pinctrl_set_mux,
+ .gpio_request_enable = rtd_pinctrl_gpio_request_enable,
};
-static int rtd119x_pconf_parse_conf(struct rtd119x_pinctrl *data,
- const struct rtd119x_pin_config_desc *config_desc,
+static int rtd_pconf_parse_conf(struct rtd_pinctrl *data,
+ const struct rtd_pin_config_desc *config_desc,
enum pin_config_param param, enum pin_config_param arg)
{
u8 set_val = 0;
@@ -392,7 +392,7 @@ static int rtd119x_pconf_parse_conf(struct rtd119x_pinctrl *data,
return 0;
}
-static int rtd119x_pin_config_get(struct pinctrl_dev *pcdev, unsigned int pinnr,
+static int rtd_pin_config_get(struct pinctrl_dev *pcdev, unsigned int pinnr,
unsigned long *config)
{
unsigned int param = pinconf_to_config_param(*config);
@@ -407,26 +407,26 @@ static int rtd119x_pin_config_get(struct pinctrl_dev *pcdev, unsigned int pinnr,
return 0;
}
-static int rtd119x_pin_config_set(struct pinctrl_dev *pcdev, unsigned int pinnr,
+static int rtd_pin_config_set(struct pinctrl_dev *pcdev, unsigned int pinnr,
unsigned long *configs, unsigned int num_configs)
{
- struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
- const struct rtd119x_pin_config_desc *config_desc;
+ struct rtd_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+ const struct rtd_pin_config_desc *config_desc;
const struct pinctrl_pin_desc *pin_desc;
const char *pin_name;
int i;
- pin_desc = rtd119x_pinctrl_get_pin_by_number(data, pinnr);
+ pin_desc = rtd_pinctrl_get_pin_by_number(data, pinnr);
if (!pin_desc)
return -ENOTSUPP;
pin_name = pin_desc->name;
- config_desc = rtd119x_pinctrl_find_config(data, pin_name);
+ config_desc = rtd_pinctrl_find_config(data, pin_name);
if (!config_desc)
return -ENOTSUPP;
for (i = 0; i < num_configs; i++) {
- rtd119x_pconf_parse_conf(data, config_desc,
+ rtd_pconf_parse_conf(data, config_desc,
pinconf_to_config_param(configs[i]),
pinconf_to_config_argument(configs[i]));
}
@@ -436,16 +436,16 @@ static int rtd119x_pin_config_set(struct pinctrl_dev *pcdev, unsigned int pinnr,
-static const struct pinconf_ops rtd119x_pinconf_ops = {
+static const struct pinconf_ops rtd_pinconf_ops = {
.is_generic = true,
- .pin_config_get = rtd119x_pin_config_get,
- .pin_config_set = rtd119x_pin_config_set,
+ .pin_config_get = rtd_pin_config_get,
+ .pin_config_set = rtd_pin_config_set,
};
-static void rtd119x_pinctrl_selftest(struct rtd119x_pinctrl *data)
+static void rtd_pinctrl_selftest(struct rtd_pinctrl *data)
{
int i, j, k;
- const struct rtd119x_pinctrl_desc *info = data->info;
+ const struct rtd_pinctrl_desc *info = data->info;
for (i = 0; i < info->num_muxes; i++) {
/* Check for pin */
@@ -492,7 +492,7 @@ static void rtd119x_pinctrl_selftest(struct rtd119x_pinctrl *data)
}
}
-static const struct of_device_id rtd119x_pinctrl_dt_ids[] = {
+static const struct of_device_id rtd_pinctrl_dt_ids[] = {
{ .compatible = "realtek,rtd1195-iso-pinctrl",
.data = &rtd1195_iso_pinctrl_desc },
{ .compatible = "realtek,rtd1195-crt-pinctrl",
@@ -508,12 +508,12 @@ static const struct of_device_id rtd119x_pinctrl_dt_ids[] = {
{ }
};
-static int rtd119x_pinctrl_probe(struct platform_device *pdev)
+static int rtd_pinctrl_probe(struct platform_device *pdev)
{
- struct rtd119x_pinctrl *data;
+ struct rtd_pinctrl *data;
const struct of_device_id *match;
- match = of_match_node(rtd119x_pinctrl_dt_ids, pdev->dev.of_node);
+ match = of_match_node(rtd_pinctrl_dt_ids, pdev->dev.of_node);
if (!match)
return -EINVAL;
@@ -529,9 +529,9 @@ static int rtd119x_pinctrl_probe(struct platform_device *pdev)
data->desc.name = "foo";
data->desc.pins = data->info->pins;
data->desc.npins = data->info->num_pins;
- data->desc.pctlops = &rtd119x_pinctrl_ops;
- data->desc.pmxops = &rtd119x_pinmux_ops;
- data->desc.confops = &rtd119x_pinconf_ops;
+ data->desc.pctlops = &rtd_pinctrl_ops;
+ data->desc.pmxops = &rtd_pinmux_ops;
+ data->desc.confops = &rtd_pinconf_ops;
data->desc.custom_params = NULL;
data->desc.num_custom_params = 0;
data->desc.owner = THIS_MODULE;
@@ -542,20 +542,20 @@ static int rtd119x_pinctrl_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, data);
- rtd119x_pinctrl_selftest(data);
+ rtd_pinctrl_selftest(data);
dev_info(&pdev->dev, "probed\n");
return 0;
}
-static struct platform_driver rtd119x_pinctrl_driver = {
- .probe = rtd119x_pinctrl_probe,
+static struct platform_driver rtd_pinctrl_driver = {
+ .probe = rtd_pinctrl_probe,
.driver = {
- .name = "rtd1295-pinctrl",
- .of_match_table = rtd119x_pinctrl_dt_ids,
+ .name = "rtd-pinctrl",
+ .of_match_table = rtd_pinctrl_dt_ids,
},
};
-builtin_platform_driver(rtd119x_pinctrl_driver);
-MODULE_DESCRIPTION("rtk pinctrl driver");
+builtin_platform_driver(rtd_pinctrl_driver);
+MODULE_DESCRIPTION("rtd pinctrl driver");
MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/pinctrl-rtd1195.h b/drivers/pinctrl/realtek/pinctrl-rtd1195.h
similarity index 98%
rename from drivers/pinctrl/pinctrl-rtd1195.h
rename to drivers/pinctrl/realtek/pinctrl-rtd1195.h
index f0dd91f416e8..74139345083c 100644
--- a/drivers/pinctrl/pinctrl-rtd1195.h
+++ b/drivers/pinctrl/realtek/pinctrl-rtd1195.h
@@ -107,7 +107,7 @@ static const unsigned int rtd1195_pwm_23_open_drain_pins[] = {
.num_pins = ARRAY_SIZE(rtd1195_ ## _name ## _pins), \
}
-static const struct rtd119x_pin_group_desc rtd1195_iso_pin_groups[] = {
+static const struct rtd_pin_group_desc rtd1195_iso_pin_groups[] = {
RTD1195_GROUP(iso_gpio_0),
RTD1195_GROUP(iso_gpio_1),
RTD1195_GROUP(usb0),
@@ -212,7 +212,7 @@ static const char * const rtd1195_iso_pwm_23_open_drain_groups[] = {
.num_groups = ARRAY_SIZE(rtd1195_iso_ ## _name ## _groups), \
}
-static const struct rtd119x_pin_func_desc rtd1195_iso_pin_functions[] = {
+static const struct rtd_pin_func_desc rtd1195_iso_pin_functions[] = {
RTD1195_FUNC(gpio),
RTD1195_FUNC(ai_ur1),
RTD1195_FUNC(ai_vfd),
@@ -239,7 +239,7 @@ static const struct rtd119x_pin_func_desc rtd1195_iso_pin_functions[] = {
#undef RTD1195_FUNC
-static const struct rtd119x_pin_desc rtd1195_iso_muxes[] = {
+static const struct rtd_pin_desc rtd1195_iso_muxes[] = {
RTK_PIN_MUX(vfd_d, 0x10, GENMASK(1, 0),
RTK_PIN_FUNC(0x0 << 0, "gpio"),
RTK_PIN_FUNC(0x1 << 0, "vfd"),
@@ -337,7 +337,7 @@ static const struct rtd119x_pin_desc rtd1195_iso_muxes[] = {
RTK_PIN_FUNC(0x2 << 30, "ai_vfd")),
};
-static const struct rtd119x_pin_config_desc rtd1195_iso_configs[] = {
+static const struct rtd_pin_config_desc rtd1195_iso_configs[] = {
RTK_PIN_CONFIG(ir_rx, 0x0, 8, 1, 0, 2, 3, PADDRI_2_4),
RTK_PIN_CONFIG(vfd_cs_n, 0x0, 12, 1, 0, 2, 3, PADDRI_2_4),
RTK_PIN_CONFIG(vfd_clk, 0x0, 16, 1, 0, 2, 3, PADDRI_2_4),
@@ -358,7 +358,7 @@ static const struct rtd119x_pin_config_desc rtd1195_iso_configs[] = {
};
-static const struct rtd119x_pinctrl_desc rtd1195_iso_pinctrl_desc = {
+static const struct rtd_pinctrl_desc rtd1195_iso_pinctrl_desc = {
.pins = rtd1195_iso_pins,
.num_pins = ARRAY_SIZE(rtd1195_iso_pins),
.groups = rtd1195_iso_pin_groups,
@@ -586,7 +586,7 @@ static const unsigned int rtd1195_ao_loc_pins[] = { RTD1195_AO_LOC };
.num_pins = ARRAY_SIZE(rtd1195_ ## _name ## _pins), \
}
-static const struct rtd119x_pin_group_desc rtd1195_crt_pin_groups[] = {
+static const struct rtd_pin_group_desc rtd1195_crt_pin_groups[] = {
RTD1195_GROUP(gpio_0),
RTD1195_GROUP(gpio_1),
RTD1195_GROUP(gpio_2),
@@ -764,7 +764,7 @@ static const char * const rtd1195_crt_usb_groups[] = { "sensor_cko_1" };
.num_groups = ARRAY_SIZE(rtd1195_crt_ ## _name ## _groups), \
}
-static const struct rtd119x_pin_func_desc rtd1195_crt_pin_functions[] = {
+static const struct rtd_pin_func_desc rtd1195_crt_pin_functions[] = {
RTD1195_FUNC(gpio),
RTD1195_FUNC(ao_tp0),
RTD1195_FUNC(ao_gpio),
@@ -794,7 +794,7 @@ static const struct rtd119x_pin_func_desc rtd1195_crt_pin_functions[] = {
#undef RTD1195_FUNC
-static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = {
+static const struct rtd_pin_desc rtd1195_crt_muxes[] = {
RTK_PIN_MUX(nf_rdy, 0x60, GENMASK(3, 2),
RTK_PIN_FUNC(0x0 << 2, "gpio"),
RTK_PIN_FUNC(0x1 << 2, "nand"),
@@ -1045,7 +1045,7 @@ static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = {
RTK_PIN_FUNC(0x2 << 2, "ao_gpio")),
};
-static const struct rtd119x_pin_config_desc rtd1195_crt_configs[] = {
+static const struct rtd_pin_config_desc rtd1195_crt_configs[] = {
RTK_PIN_CONFIG(nf_ale, 0x78, 4, 1, 0, 2, 3, PADDRI_4_8),
RTK_PIN_CONFIG(nf_ce_n_0, 0x78, 8, 1, 0, 2, 3, PADDRI_4_8),
RTK_PIN_CONFIG(nf_ce_n_1, 0x78, 12, 1, 0, 2, 3, PADDRI_4_8),
@@ -1111,7 +1111,7 @@ static const struct rtd119x_pin_config_desc rtd1195_crt_configs[] = {
};
-static const struct rtd119x_pinctrl_desc rtd1195_crt_pinctrl_desc = {
+static const struct rtd_pinctrl_desc rtd1195_crt_pinctrl_desc = {
.pins = rtd1195_crt_pins,
.num_pins = ARRAY_SIZE(rtd1195_crt_pins),
.groups = rtd1195_crt_pin_groups,
diff --git a/drivers/pinctrl/pinctrl-rtd1295.h b/drivers/pinctrl/realtek/pinctrl-rtd1295.h
similarity index 98%
rename from drivers/pinctrl/pinctrl-rtd1295.h
rename to drivers/pinctrl/realtek/pinctrl-rtd1295.h
index f27debc96bb6..14d46baa97d8 100644
--- a/drivers/pinctrl/pinctrl-rtd1295.h
+++ b/drivers/pinctrl/realtek/pinctrl-rtd1295.h
@@ -171,7 +171,7 @@ static const unsigned int rtd1295_uart2_1_pins[] = {
.num_pins = ARRAY_SIZE(rtd1295_ ## _name ## _pins), \
}
-static const struct rtd119x_pin_group_desc rtd1295_iso_pin_groups[] = {
+static const struct rtd_pin_group_desc rtd1295_iso_pin_groups[] = {
RTD1295_GROUP(iso_gpio_0),
RTD1295_GROUP(iso_gpio_1),
RTD1295_GROUP(iso_gpio_2),
@@ -317,7 +317,7 @@ static const char * const rtd1295_iso_acpu_ejtag_loc_nf_groups[] = {
.num_groups = ARRAY_SIZE(rtd1295_iso_ ## _name ## _groups), \
}
-static const struct rtd119x_pin_func_desc rtd1295_iso_pin_functions[] = {
+static const struct rtd_pin_func_desc rtd1295_iso_pin_functions[] = {
RTD1295_FUNC(gpio),
RTD1295_FUNC(acpu_ejtag_loc_iso),
RTD1295_FUNC(edp_hpd),
@@ -350,7 +350,7 @@ static const struct rtd119x_pin_func_desc rtd1295_iso_pin_functions[] = {
#undef RTD1295_FUNC
-static const struct rtd119x_pin_desc rtd1295_iso_muxes[] = {
+static const struct rtd_pin_desc rtd1295_iso_muxes[] = {
RTK_PIN_MUX(iso_gpio_4, 0x10, GENMASK(1, 0),
RTK_PIN_FUNC(0x0 << 0, "gpio"),
RTK_PIN_FUNC(0x1 << 0, "uart2_0"),
@@ -489,7 +489,7 @@ static const struct rtd119x_pin_desc rtd1295_iso_muxes[] = {
RTK_PIN_FUNC(0x2 << 12, "uart2_1")),
};
-static const struct rtd119x_pin_config_desc rtd1295_iso_configs[] = {
+static const struct rtd_pin_config_desc rtd1295_iso_configs[] = {
RTK_PIN_CONFIG(iso_gpio_2, 0x0, 0, 1, 0, 2, 3, PADDRI_2_4),
RTK_PIN_CONFIG(iso_gpio_3, 0x0, 4, 1, 0, 2, 3, PADDRI_2_4),
RTK_PIN_CONFIG(ir_rx, 0x0, 8, 1, 0, 2, 3, PADDRI_2_4),
@@ -527,7 +527,7 @@ static const struct rtd119x_pin_config_desc rtd1295_iso_configs[] = {
-static const struct rtd119x_pinctrl_desc rtd1295_iso_pinctrl_desc = {
+static const struct rtd_pinctrl_desc rtd1295_iso_pinctrl_desc = {
.pins = rtd1295_iso_pins,
.num_pins = ARRAY_SIZE(rtd1295_iso_pins),
.groups = rtd1295_iso_pin_groups,
@@ -756,7 +756,7 @@ static const unsigned int rtd1295_tp1_loc_pins[] = { RTD1295_TP1_LOC };
-static const struct rtd119x_pin_group_desc rtd1295_sb2_pin_groups[] = {
+static const struct rtd_pin_group_desc rtd1295_sb2_pin_groups[] = {
RTD1295_GROUP(gpio_0),
RTD1295_GROUP(gpio_1),
RTD1295_GROUP(gpio_2),
@@ -921,7 +921,7 @@ static const char * const rtd1295_sb2_hif_loc_nf_groups[] = { "hif_loc" };
.num_groups = ARRAY_SIZE(rtd1295_sb2_ ## _name ## _groups), \
}
-static const struct rtd119x_pin_func_desc rtd1295_sb2_pin_functions[] = {
+static const struct rtd_pin_func_desc rtd1295_sb2_pin_functions[] = {
RTD1295_FUNC(gpio),
RTD1295_FUNC(ai),
RTD1295_FUNC(dc_fan_sensor),
@@ -951,7 +951,7 @@ static const struct rtd119x_pin_func_desc rtd1295_sb2_pin_functions[] = {
#undef RTD1295_FUNC
-static const struct rtd119x_pin_desc rtd1295_sb2_muxes[] = {
+static const struct rtd_pin_desc rtd1295_sb2_muxes[] = {
RTK_PIN_MUX(tp0_data, 0x08, GENMASK(2, 0),
RTK_PIN_FUNC(0x0 << 0, "gpio"),
RTK_PIN_FUNC(0x1 << 0, "tp0_loc_tp0"),
@@ -1168,7 +1168,7 @@ static const struct rtd119x_pin_desc rtd1295_sb2_muxes[] = {
RTK_PIN_FUNC(0x1 << 22, "rgmii")),
};
-static const struct rtd119x_pin_config_desc rtd1295_sb2_configs[] = {
+static const struct rtd_pin_config_desc rtd1295_sb2_configs[] = {
RTK_PIN_CONFIG(tp0_clk, 0x28, 0, 1, 0, 2, 3, PADDRI_4_8),
RTK_PIN_CONFIG(tp0_sync, 0x28, 4, 1, 0, 2, 3, PADDRI_4_8),
RTK_PIN_CONFIG(tp0_valid, 0x28, 8, 1, 0, 2, 3, PADDRI_4_8),
@@ -1226,7 +1226,7 @@ static const struct rtd119x_pin_config_desc rtd1295_sb2_configs[] = {
};
-static const struct rtd119x_pinctrl_desc rtd1295_sb2_pinctrl_desc = {
+static const struct rtd_pinctrl_desc rtd1295_sb2_pinctrl_desc = {
.pins = rtd1295_sb2_pins,
.num_pins = ARRAY_SIZE(rtd1295_sb2_pins),
.groups = rtd1295_sb2_pin_groups,
@@ -1278,7 +1278,7 @@ static const unsigned int rtd1295_ao_sd_1_pins[] = { RTD1295_AO_SD_1 };
static const unsigned int rtd1295_ao_sd_2_pins[] = { RTD1295_AO_SD_2 };
static const unsigned int rtd1295_ao_sd_3_pins[] = { RTD1295_AO_SD_3 };
-static const struct rtd119x_pin_group_desc rtd1295_disp_pin_groups[] = {
+static const struct rtd_pin_group_desc rtd1295_disp_pin_groups[] = {
RTD1295_GROUP(spdif),
RTD1295_GROUP(dmic_clk),
RTD1295_GROUP(dmic_data),
@@ -1313,7 +1313,7 @@ static const char * const rtd1295_disp_spdif_out_groups[] = { "spdif" };
.num_groups = ARRAY_SIZE(rtd1295_disp_ ## _name ## _groups), \
}
-static const struct rtd119x_pin_func_desc rtd1295_disp_pin_functions[] = {
+static const struct rtd_pin_func_desc rtd1295_disp_pin_functions[] = {
RTD1295_FUNC(gpio),
RTD1295_FUNC(ai),
RTD1295_FUNC(ao),
@@ -1323,7 +1323,7 @@ static const struct rtd119x_pin_func_desc rtd1295_disp_pin_functions[] = {
#undef RTD1295_FUNC
-static const struct rtd119x_pin_desc rtd1295_disp_muxes[] = {
+static const struct rtd_pin_desc rtd1295_disp_muxes[] = {
RTK_PIN_MUX(spdif, 0x08, GENMASK(1, 0),
RTK_PIN_FUNC(0x0 << 0, "gpio"),
RTK_PIN_FUNC(0x1 << 0, "spdif_out")),
@@ -1360,7 +1360,7 @@ static const struct rtd119x_pin_desc rtd1295_disp_muxes[] = {
RTK_PIN_FUNC(0x2 << 18, "ai")),
};
-static const struct rtd119x_pin_config_desc rtd1295_disp_configs[] = {
+static const struct rtd_pin_config_desc rtd1295_disp_configs[] = {
RTK_PIN_CONFIG(spdif, 0x0, 0, 1, 0, 2, 3, PADDRI_2_4),
RTK_PIN_CONFIG(dmic_clk, 0x0, 4, 1, 0, 2, 3, PADDRI_2_4),
RTK_PIN_CONFIG(dmic_data, 0x0, 8, 1, 0, 2, 3, PADDRI_2_4),
@@ -1374,7 +1374,7 @@ static const struct rtd119x_pin_config_desc rtd1295_disp_configs[] = {
};
-static const struct rtd119x_pinctrl_desc rtd1295_disp_pinctrl_desc = {
+static const struct rtd_pinctrl_desc rtd1295_disp_pinctrl_desc = {
.pins = rtd1295_disp_pins,
.num_pins = ARRAY_SIZE(rtd1295_disp_pins),
.groups = rtd1295_disp_pin_groups,
@@ -1513,7 +1513,7 @@ static const unsigned int rtd1295_prob_3_pins[] = { RTD1295_PROB_3 };
static const unsigned int rtd1295_sdio_loc_pins[] = { RTD1295_SDIO_LOC };
-static const struct rtd119x_pin_group_desc rtd1295_cr_pin_groups[] = {
+static const struct rtd_pin_group_desc rtd1295_cr_pin_groups[] = {
RTD1295_GROUP(nf_cle),
RTD1295_GROUP(nf_ale),
RTD1295_GROUP(nf_rd_n),
@@ -1616,7 +1616,7 @@ static const char * const rtd1295_cr_sdio_1_groups[] = {
.num_groups = ARRAY_SIZE(rtd1295_cr_ ## _name ## _groups), \
}
-static const struct rtd119x_pin_func_desc rtd1295_cr_pin_functions[] = {
+static const struct rtd_pin_func_desc rtd1295_cr_pin_functions[] = {
RTD1295_FUNC(gpio),
RTD1295_FUNC(avcpu_ej),
RTD1295_FUNC(emmc),
@@ -1633,7 +1633,7 @@ static const struct rtd119x_pin_func_desc rtd1295_cr_pin_functions[] = {
#undef RTD1295_FUNC
-static const struct rtd119x_pin_desc rtd1295_cr_muxes[] = {
+static const struct rtd_pin_desc rtd1295_cr_muxes[] = {
RTK_PIN_MUX(nf_dqs, 0x00, GENMASK(1, 0),
RTK_PIN_FUNC(0x0 << 0, "gpio"),
RTK_PIN_FUNC(0x1 << 0, "nand")),
@@ -1785,7 +1785,7 @@ static const struct rtd119x_pin_desc rtd1295_cr_muxes[] = {
RTK_PIN_FUNC(0x1 << 12, "pll_test")),
};
-static const struct rtd119x_pin_config_desc rtd1295_cr_configs[] = {
+static const struct rtd_pin_config_desc rtd1295_cr_configs[] = {
RTK_PIN_CONFIG(nf_dqs, 0x8, 0, 1, 0, 2, 3, PCONF_UNSUPP),
RTK_PIN_CONFIG(nf_ale, 0x8, 4, 1, 0, 2, 3, PCONF_UNSUPP),
RTK_PIN_CONFIG(nf_ce_n_0, 0x8, 8, 1, 0, 2, 3, PCONF_UNSUPP),
@@ -1826,7 +1826,7 @@ static const struct rtd119x_pin_config_desc rtd1295_cr_configs[] = {
};
-static const struct rtd119x_pinctrl_desc rtd1295_cr_pinctrl_desc = {
+static const struct rtd_pinctrl_desc rtd1295_cr_pinctrl_desc = {
.pins = rtd1295_cr_pins,
.num_pins = ARRAY_SIZE(rtd1295_cr_pins),
.groups = rtd1295_cr_pin_groups,
--
2.26.2
^ permalink raw reply related
* Re: [PATCH v3 3/5] ARM: dts: stm32: enable ltdc binding with ili9341 on stm32429-disco board
From: dillon min @ 2020-05-14 9:17 UTC (permalink / raw)
To: Linus Walleij
Cc: Rob Herring, Maxime Coquelin, Alexandre TORGUE,
thierry.reding@gmail.com, Sam Ravnborg, Dave Airlie,
Daniel Vetter, Michael Turquette, Stephen Boyd,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-stm32, Linux ARM, linux-kernel@vger.kernel.org,
open list:DRM PANEL DRIVERS, linux-clk
In-Reply-To: <CACRpkda5VjjBdbruXTi33QBNb=VU6vK2zDE8yyQXoWw7=NQFeg@mail.gmail.com>
Hi, Linus,
thanks for reviewing.
On Thu, May 14, 2020 at 4:24 PM Linus Walleij <linus.walleij@linaro.org> wrote:
>
> On Tue, May 12, 2020 at 9:04 AM <dillon.minfei@gmail.com> wrote:
>
> > From: dillon min <dillon.minfei@gmail.com>
> >
> > Enable the ltdc & ili9341 on stm32429-disco board.
> >
> > Signed-off-by: dillon min <dillon.minfei@gmail.com>
>
> This mostly looks good but...
>
> > +&spi5 {
> > + status = "okay";
> > + pinctrl-0 = <&spi5_pins>;
> > + pinctrl-names = "default";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + cs-gpios = <&gpioc 2 GPIO_ACTIVE_LOW>;
> > + dmas = <&dma2 3 2 0x400 0x0>,
> > + <&dma2 4 2 0x400 0x0>;
> > + dma-names = "rx", "tx";
>
> These DMA assignments seem to be SoC things and should
> rather be in the DTS(I) file where &spi5 is defined, right?
> stm32f429.dtsi I suppose?
>
> It is likely the same no matter which device is using spi5.
>
> Yours,
> Linus Walleij
Yes, the dma assignments can be moved to stm32f429.dtsi file.
i will change it.
thanks.
best regards.
dillon,
^ permalink raw reply
* Re: [PATCH 5/6] tty/sysrq: Add configurable handler to signal a process
From: kbuild test robot @ 2020-05-14 9:06 UTC (permalink / raw)
To: Andrzej Pietrasiewicz, linux-input, devicetree
Cc: kbuild-all, Dmitry Torokhov, Rob Herring, Greg Kroah-Hartman,
Jiri Slaby, andrzej.p, kernel
In-Reply-To: <20200511135918.8203-6-andrzej.p@collabora.com>
[-- Attachment #1: Type: text/plain, Size: 2902 bytes --]
Hi Andrzej,
I love your patch! Yet something to improve:
[auto build test ERROR on 2ef96a5bb12be62ef75b5828c0aab838ebb29cb8]
url: https://github.com/0day-ci/linux/commits/Andrzej-Pietrasiewicz/Magic-SysRq-extensions/20200514-151142
base: 2ef96a5bb12be62ef75b5828c0aab838ebb29cb8
config: alpha-defconfig (attached as .config)
compiler: alpha-linux-gcc (GCC) 9.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day GCC_VERSION=9.3.0 make.cross ARCH=alpha
If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>, old ones prefixed by <<):
drivers/tty/sysrq.c: In function 'sysrq_str_to_signal':
>> drivers/tty/sysrq.c:791:17: error: 'SIGSTKFLT' undeclared (first use in this function); did you mean 'SIGSTKSZ'?
791 | {"SIGSTKFLT", SIGSTKFLT},
| ^~~~~~~~~
| SIGSTKSZ
drivers/tty/sysrq.c:791:17: note: each undeclared identifier is reported only once for each function it appears in
vim +791 drivers/tty/sysrq.c
771
772 static void sysrq_str_to_signal(void)
773 {
774 static const struct signal_search signals[] = {
775 {"SIGHUP", SIGHUP},
776 {"SIGINT", SIGINT},
777 {"SIGQUIT", SIGQUIT},
778 {"SIGILL", SIGILL},
779 {"SIGTRAP", SIGTRAP},
780 {"SIGABRT", SIGABRT},
781 {"SIGIOT", SIGIOT},
782 {"SIGBUS", SIGBUS},
783 {"SIGFPE", SIGFPE},
784 {"SIGKILL", SIGKILL},
785 {"SIGUSR1", SIGUSR1},
786 {"SIGSEGV", SIGSEGV},
787 {"SIGUSR2", SIGUSR2},
788 {"SIGPIPE", SIGPIPE},
789 {"SIGALRM", SIGALRM},
790 {"SIGTERM", SIGTERM},
> 791 {"SIGSTKFLT", SIGSTKFLT},
792 {"SIGCHLD", SIGCHLD},
793 {"SIGCONT", SIGCONT},
794 {"SIGSTOP", SIGSTOP},
795 {"SIGTSTP", SIGTSTP},
796 {"SIGTTIN", SIGTTIN},
797 {"SIGTTOU", SIGTTOU},
798 {"SIGURG", SIGURG},
799 {"SIGXCPU", SIGXCPU},
800 {"SIGXFSZ", SIGXFSZ},
801 {"SIGVTALRM", SIGVTALRM},
802 {"SIGPROF", SIGPROF},
803 {"SIGWINCH", SIGWINCH},
804 {"SIGIO", SIGIO},
805 {"SIGPOLL", SIGPOLL},
806 {"SIGPWR", SIGPWR},
807 {"SIGSYS", SIGSYS},
808 };
809 int i;
810
811 if (!sysrq_signal)
812 return;
813
814 for (i = 0; i < ARRAY_SIZE(signals); ++i)
815 if (!strcmp(signals[i].name, sysrq_signal))
816 break;
817
818 if (i >= ARRAY_SIZE(signals)) {
819 pr_err("Unknown signal name %s", sysrq_signal);
820
821 return;
822 }
823
824 sysrq_signal_code = signals[i].code;
825 }
826
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 13719 bytes --]
^ permalink raw reply
* Re: [PATCH v3] dt-bindings: mfd: Convert stmfx bindings to json-schema
From: Lee Jones @ 2020-05-14 9:00 UTC (permalink / raw)
To: Benjamin GAIGNARD
Cc: Rob Herring, robh+dt@kernel.org, mark.rutland@arm.co,
Alexandre TORGUE, linus.walleij@linaro.org, Amelie DELAUNAY,
devicetree@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org
In-Reply-To: <70ee04c9-4f65-6909-32bc-a379c21a031e@st.com>
On Thu, 14 May 2020, Benjamin GAIGNARD wrote:
>
>
> On 2/26/20 5:21 PM, Rob Herring wrote:
> > On Thu, 20 Feb 2020 17:22:46 +0100, Benjamin Gaignard wrote:
> >> Convert stmfx bindings to json-schema
> >>
> >> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> >> ---
> >> .../devicetree/bindings/mfd/st,stmfx.yaml | 124 +++++++++++++++++++++
> >> Documentation/devicetree/bindings/mfd/stmfx.txt | 28 -----
> >> .../devicetree/bindings/pinctrl/pinctrl-stmfx.txt | 116 -------------------
> >> 3 files changed, 124 insertions(+), 144 deletions(-)
> >> create mode 100644 Documentation/devicetree/bindings/mfd/st,stmfx.yaml
> >> delete mode 100644 Documentation/devicetree/bindings/mfd/stmfx.txt
> >> delete mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-stmfx.txt
> >>
> Hi Lee, Rob,
>
> I haven't been able to found this patch in -next branches, can one of
> you merge it ?
>
> Thanks,
> Benjamin
> > Reviewed-by: Rob Herring <robh@kernel.org>
Rob,
We should agree on a process going forward. Do you take DT document
changes or should I? Up until we moved to YAML formatting, I took
them but responsibly seems to have migrated over to you since then.
I don't mind either way.
--
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* Re: [PATCH v2 1/5] printk: honor the max_reason field in kmsg_dumper
From: Petr Mladek @ 2020-05-14 8:49 UTC (permalink / raw)
To: Pavel Tatashin
Cc: jmorris, sashal, linux-kernel, sergey.senozhatsky, rostedt,
keescook, anton, ccross, tony.luck, robh+dt, devicetree
In-Reply-To: <20200505154510.93506-2-pasha.tatashin@soleen.com>
On Tue 2020-05-05 11:45:06, Pavel Tatashin wrote:
> kmsg_dump() allows to dump kmesg buffer for various system events: oops,
> panic, reboot, etc. It provides an interface to register a callback call
> for clients, and in that callback interface there is a field "max_reason"
> which gets ignored unless always_kmsg_dump is passed as kernel parameter.
>
> Allow clients to decide max_reason, and keep the current behavior when
> max_reason is not set.
>
> Signed-off-by: Pavel Tatashin <pasha.tatashin@soleen.com>
> ---
> include/linux/kmsg_dump.h | 1 +
> kernel/printk/printk.c | 15 +++++++++++----
> 2 files changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/include/linux/kmsg_dump.h b/include/linux/kmsg_dump.h
> index 2e7a1e032c71..cfc042066be7 100644
> --- a/include/linux/kmsg_dump.h
> +++ b/include/linux/kmsg_dump.h
> @@ -28,6 +28,7 @@ enum kmsg_dump_reason {
> KMSG_DUMP_RESTART,
> KMSG_DUMP_HALT,
> KMSG_DUMP_POWEROFF,
> + KMSG_DUMP_MAX
> };
>
> /**
> diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c
> index 9a9b6156270b..1aab69a8a2bf 100644
> --- a/kernel/printk/printk.c
> +++ b/kernel/printk/printk.c
> @@ -3157,12 +3157,19 @@ void kmsg_dump(enum kmsg_dump_reason reason)
> struct kmsg_dumper *dumper;
> unsigned long flags;
>
> - if ((reason > KMSG_DUMP_OOPS) && !always_kmsg_dump)
> - return;
> -
> rcu_read_lock();
> list_for_each_entry_rcu(dumper, &dump_list, list) {
> - if (dumper->max_reason && reason > dumper->max_reason)
> + enum kmsg_dump_reason cur_reason = dumper->max_reason;
If this code is still in the next version, please, rename this variable
to max_reason or so.
"cur" is ambiguous. It might be current dumper or current message
which confused me later in the code ;-)
Best Regards,
Petr
> +
> + /*
> + * If client has not provided a specific max_reason, default
> + * to KMSG_DUMP_OOPS, unless always_kmsg_dump was set.
> + */
> + if (cur_reason == KMSG_DUMP_UNDEF) {
> + cur_reason = always_kmsg_dump ? KMSG_DUMP_MAX :
> + KMSG_DUMP_OOPS;
> + }
> + if (reason > cur_reason)
> continue;
>
> /* initialize iterator with data about the stored records */
> --
> 2.25.1
^ permalink raw reply
* Re: [RESEND PATCH] thermal: mediatek: add suspend/resume callback
From: Michael Kao @ 2020-05-14 8:46 UTC (permalink / raw)
To: Zhang Rui, Daniel Lezcano
Cc: Eduardo Valentin, Daniel Lezcano, Rob Herring, Mark Rutland,
Matthias Brugger, hsinyi@chromium.org, linux-pm@vger.kernel.org,
srv_heupstream, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
Louis Yu (游政錕)
In-Reply-To: <20200408090558.12410-2-michael.kao@mediatek.com>
On Wed, 2020-04-08 at 17:05 +0800, Michael Kao (高振翔) wrote:
> From: Louis Yu <louis.yu@mediatek.com>
>
> Add suspend/resume callback to disable/enable Mediatek thermal sensor
> respectively. Since thermal power domain is off in suspend, thermal driver
> needs re-initialization during resume.
>
> Signed-off-by: Louis Yu <louis.yu@mediatek.com>
> Signed-off-by: Michael Kao <michael.kao@mediatek.com>
> ---
> drivers/thermal/mtk_thermal.c | 152 ++++++++++++++++++++++++++++++----
> 1 file changed, 134 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c
> index 76e30603d4d5..36fd35fac733 100644
> --- a/drivers/thermal/mtk_thermal.c
> +++ b/drivers/thermal/mtk_thermal.c
> @@ -22,6 +22,7 @@
> #include <linux/thermal.h>
> #include <linux/reset.h>
> #include <linux/types.h>
> +#include <linux/iopoll.h>
>
> /* AUXADC Registers */
> #define AUXADC_CON1_SET_V 0x008
> @@ -31,6 +32,8 @@
>
> #define APMIXED_SYS_TS_CON1 0x604
>
> +#define APMIXED_SYS_TS_CON1_BUFFER_OFF 0x30
> +
> /* Thermal Controller Registers */
> #define TEMP_MONCTL0 0x000
> #define TEMP_MONCTL1 0x004
> @@ -38,6 +41,7 @@
> #define TEMP_MONIDET0 0x014
> #define TEMP_MONIDET1 0x018
> #define TEMP_MSRCTL0 0x038
> +#define TEMP_MSRCTL1 0x03c
> #define TEMP_AHBPOLL 0x040
> #define TEMP_AHBTO 0x044
> #define TEMP_ADCPNP0 0x048
> @@ -87,6 +91,9 @@
> #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5)
> #define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit)
>
> +#define TEMP_MSRCTL1_BUS_STA (BIT(0) | BIT(7))
> +#define TEMP_MSRCTL1_SENSING_POINTS_PAUSE 0x10E
> +
> /* MT8173 thermal sensors */
> #define MT8173_TS1 0
> #define MT8173_TS2 1
> @@ -250,6 +257,10 @@ struct mtk_thermal_data {
> struct mtk_thermal {
> struct device *dev;
> void __iomem *thermal_base;
> + void __iomem *apmixed_base;
> + void __iomem *auxadc_base;
> + u64 apmixed_phys_base;
> + u64 auxadc_phys_base;
>
> struct clk *clk_peri_therm;
> struct clk *clk_auxadc;
> @@ -541,13 +552,13 @@ static int raw_to_mcelsius(struct mtk_thermal *mt, int sensno, s32 raw)
> }
>
> /**
> - * mtk_thermal_get_bank - get bank
> + * mtk_thermal_lock_bank - get bank
> * @bank: The bank
> *
> * The bank registers are banked, we have to select a bank in the
> * PTPCORESEL register to access it.
> */
> -static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
> +static void mtk_thermal_lock_bank(struct mtk_thermal_bank *bank)
> {
> struct mtk_thermal *mt = bank->mt;
> u32 val;
> @@ -563,12 +574,12 @@ static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
> }
>
> /**
> - * mtk_thermal_put_bank - release bank
> + * mtk_thermal_unlock_bank - release bank
> * @bank: The bank
> *
> - * release a bank previously taken with mtk_thermal_get_bank,
> + * release a bank previously taken with mtk_thermal_lock_bank,
> */
> -static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
> +static void mtk_thermal_unlock_bank(struct mtk_thermal_bank *bank)
> {
> struct mtk_thermal *mt = bank->mt;
>
> @@ -622,11 +633,11 @@ static int mtk_read_temp(void *data, int *temperature)
> for (i = 0; i < mt->conf->num_banks; i++) {
> struct mtk_thermal_bank *bank = &mt->banks[i];
>
> - mtk_thermal_get_bank(bank);
> + mtk_thermal_lock_bank(bank);
>
> tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
>
> - mtk_thermal_put_bank(bank);
> + mtk_thermal_unlock_bank(bank);
> }
>
> *temperature = tempmax;
> @@ -652,7 +663,7 @@ static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
> bank->id = num;
> bank->mt = mt;
>
> - mtk_thermal_get_bank(bank);
> + mtk_thermal_lock_bank(bank);
>
> /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
> writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
> @@ -743,7 +754,43 @@ static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
> TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
> controller_base + TEMP_ADCWRITECTRL);
>
> - mtk_thermal_put_bank(bank);
> + mtk_thermal_unlock_bank(bank);
> +}
> +
> +static int mtk_thermal_disable_sensing(struct mtk_thermal *mt, int num)
> +{
> + struct mtk_thermal_bank *bank = &mt->banks[num];
> + u32 val;
> + unsigned long timeout;
> + void __iomem *addr;
> + int ret = 0;
> +
> + bank->id = num;
> + bank->mt = mt;
> +
> + mtk_thermal_lock_bank(bank);
> +
> + val = readl(mt->thermal_base + TEMP_MSRCTL1);
> + /* pause periodic temperature measurement for sensing points */
> + writel(val | TEMP_MSRCTL1_SENSING_POINTS_PAUSE,
> + mt->thermal_base + TEMP_MSRCTL1);
> +
> + /* wait until temperature measurement bus idle */
> + timeout = jiffies + HZ;
> + addr = mt->thermal_base + TEMP_MSRCTL1;
> +
> + ret = readl_poll_timeout(addr, val, (val & TEMP_MSRCTL1_BUS_STA) == 0x0,
> + 0, timeout);
> + if (ret < 0)
> + goto out;
> +
> + /* disable periodic temperature measurement on sensing points */
> + writel(0x0, mt->thermal_base + TEMP_MONCTL0);
> +
> +out:
> + mtk_thermal_unlock_bank(bank);
> +
> + return ret;
> }
>
> static u64 of_get_phys_base(struct device_node *np)
> @@ -868,7 +915,6 @@ static int mtk_thermal_probe(struct platform_device *pdev)
> struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
> struct mtk_thermal *mt;
> struct resource *res;
> - u64 auxadc_phys_base, apmixed_phys_base;
> struct thermal_zone_device *tzdev;
>
> mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
> @@ -904,11 +950,11 @@ static int mtk_thermal_probe(struct platform_device *pdev)
> return -ENODEV;
> }
>
> - auxadc_phys_base = of_get_phys_base(auxadc);
> + mt->auxadc_phys_base = of_get_phys_base(auxadc);
>
> of_node_put(auxadc);
>
> - if (auxadc_phys_base == OF_BAD_ADDR) {
> + if (mt->auxadc_phys_base == OF_BAD_ADDR) {
> dev_err(&pdev->dev, "Can't get auxadc phys address\n");
> return -EINVAL;
> }
> @@ -919,11 +965,12 @@ static int mtk_thermal_probe(struct platform_device *pdev)
> return -ENODEV;
> }
>
> - apmixed_phys_base = of_get_phys_base(apmixedsys);
> + mt->apmixed_phys_base = of_get_phys_base(apmixedsys);
> + mt->apmixed_base = of_iomap(apmixedsys, 0);
>
> of_node_put(apmixedsys);
>
> - if (apmixed_phys_base == OF_BAD_ADDR) {
> + if (mt->apmixed_phys_base == OF_BAD_ADDR) {
> dev_err(&pdev->dev, "Can't get auxadc phys address\n");
> return -EINVAL;
> }
> @@ -935,19 +982,19 @@ static int mtk_thermal_probe(struct platform_device *pdev)
> ret = clk_prepare_enable(mt->clk_auxadc);
> if (ret) {
> dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
> - return ret;
> + goto err_disable_clk_auxadc;
> }
>
> ret = clk_prepare_enable(mt->clk_peri_therm);
> if (ret) {
> dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
> - goto err_disable_clk_auxadc;
> + goto err_disable_clk_peri_therm;
> }
>
> for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
> for (i = 0; i < mt->conf->num_banks; i++)
> - mtk_thermal_init_bank(mt, i, apmixed_phys_base,
> - auxadc_phys_base, ctrl_id);
> + mtk_thermal_init_bank(mt, i, mt->apmixed_phys_base,
> + mt->auxadc_phys_base, ctrl_id);
>
> platform_set_drvdata(pdev, mt);
>
> @@ -978,11 +1025,80 @@ static int mtk_thermal_remove(struct platform_device *pdev)
> return 0;
> }
>
> +static int __maybe_unused mtk_thermal_suspend(struct device *dev)
> +{
> + struct platform_device *pdev = to_platform_device(dev);
> + struct mtk_thermal *mt = platform_get_drvdata(pdev);
> + int i, ret;
> +
> + for (i = 0; i < mt->conf->num_banks; i++) {
> + ret = mtk_thermal_disable_sensing(mt, i);
> + if (ret)
> + goto out;
> + }
> +
> + /* disable buffer */
> + writel(readl(mt->apmixed_base + APMIXED_SYS_TS_CON1) |
> + APMIXED_SYS_TS_CON1_BUFFER_OFF,
> + mt->apmixed_base + APMIXED_SYS_TS_CON1);
> +
> + clk_disable_unprepare(mt->clk_peri_therm);
> + clk_disable_unprepare(mt->clk_auxadc);
> +
> + return 0;
> +
> +out:
> + dev_err(&pdev->dev, "Failed to wait until bus idle\n");
> +
> + return ret;
> +}
> +
> +static int __maybe_unused mtk_thermal_resume(struct device *dev)
> +{
> + struct platform_device *pdev = to_platform_device(dev);
> + struct mtk_thermal *mt = platform_get_drvdata(pdev);
> + int i, ret, ctrl_id;
> +
> + ret = device_reset(&pdev->dev);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(mt->clk_auxadc);
> + if (ret) {
> + dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
> + goto err_disable_clk_auxadc;
> + }
> +
> + ret = clk_prepare_enable(mt->clk_peri_therm);
> + if (ret) {
> + dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
> + goto err_disable_clk_peri_therm;
> + }
> +
> + for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
> + for (i = 0; i < mt->conf->num_banks; i++)
> + mtk_thermal_init_bank(mt, i, mt->apmixed_phys_base,
> + mt->auxadc_phys_base, ctrl_id);
> +
> + return 0;
> +
> +err_disable_clk_peri_therm:
> + clk_disable_unprepare(mt->clk_peri_therm);
> +err_disable_clk_auxadc:
> + clk_disable_unprepare(mt->clk_auxadc);
> +
> + return ret;
> +}
> +
> +static SIMPLE_DEV_PM_OPS(mtk_thermal_pm_ops,
> + mtk_thermal_suspend, mtk_thermal_resume);
> +
> static struct platform_driver mtk_thermal_driver = {
> .probe = mtk_thermal_probe,
> .remove = mtk_thermal_remove,
> .driver = {
> .name = "mtk-thermal",
> + .pm = &mtk_thermal_pm_ops,
> .of_match_table = mtk_thermal_of_match,
> },
> };
> --
> 2.18.0
>
Hi Daniel,
Just gently ping. Many thanks.
^ permalink raw reply
* Re: [PATCH 11/17] spi: dw: Fix native CS being unset
From: Linus Walleij @ 2020-05-14 8:31 UTC (permalink / raw)
To: Serge Semin
Cc: Serge Semin, Gregory Clement, Mark Brown, Charles Keepax,
Georgy Vlasov, Ramil Zaripov, Alexey Malahov, Thomas Bogendoerfer,
Paul Burton, Ralf Baechle, Arnd Bergmann, Allison Randal,
Andy Shevchenko, Gareth Williams, Rob Herring, linux-mips,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Phil Edworthy, Thomas Gleixner, Alexios Zavras, Thor Thayer,
wuxu.wu, Xinwei Kong, Jarkko Nikula, linux-spi,
linux-kernel@vger.kernel.org
In-Reply-To: <20200513001347.dyt357erev7vzy3l@mobilestation>
On Wed, May 13, 2020 at 2:13 AM Serge Semin
<Sergey.Semin@baikalelectronics.ru> wrote:
> > This is the correct fix now but I an afraid not correct before
> > commit 3e5ec1db8bfe.
>
> Sorry, but that's "enable" flag propagation from basic spi_set_cs() to the HW CS
> setting callback is a nightmare. In Russia there is a common saying for such
> cases, which can be translated as "you can't figure it out without a bottle of
> vodka".)
>
> Actually the fix is correct no matter whether commit 3e5ec1db8bfe is applied or
> not. At least I don't see a connection between them.
OK that seems to hold given the resoning below so:
Acked-by: Linus Walleij <linus.walleij@linaro.org>
> > What I can't help but asking is: can the native chip select even
> > handle active high chip select if not backed by a GPIO?
> > Which register would set that polarity?
>
> No. DW APB SSI doesn't support active-high mode of the native CS's.
We had some related discussion what to do with this case
when a controller can support active high CS if and only if
it is using a GPIO instead of the native CS. We didn't really
figure it out, I suppose ideally we should use two flags in the
master but that exercise is for another day.
Yours.
Linus Walleij
^ permalink raw reply
* Re: [PATCH v3 3/5] ARM: dts: stm32: enable ltdc binding with ili9341 on stm32429-disco board
From: Linus Walleij @ 2020-05-14 8:24 UTC (permalink / raw)
To: dillon.minfei
Cc: Rob Herring, Maxime Coquelin, Alexandre TORGUE,
thierry.reding@gmail.com, Sam Ravnborg, Dave Airlie,
Daniel Vetter, Michael Turquette, Stephen Boyd,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-stm32, Linux ARM, linux-kernel@vger.kernel.org,
open list:DRM PANEL DRIVERS, linux-clk
In-Reply-To: <1589267017-17294-4-git-send-email-dillon.minfei@gmail.com>
On Tue, May 12, 2020 at 9:04 AM <dillon.minfei@gmail.com> wrote:
> From: dillon min <dillon.minfei@gmail.com>
>
> Enable the ltdc & ili9341 on stm32429-disco board.
>
> Signed-off-by: dillon min <dillon.minfei@gmail.com>
This mostly looks good but...
> +&spi5 {
> + status = "okay";
> + pinctrl-0 = <&spi5_pins>;
> + pinctrl-names = "default";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cs-gpios = <&gpioc 2 GPIO_ACTIVE_LOW>;
> + dmas = <&dma2 3 2 0x400 0x0>,
> + <&dma2 4 2 0x400 0x0>;
> + dma-names = "rx", "tx";
These DMA assignments seem to be SoC things and should
rather be in the DTS(I) file where &spi5 is defined, right?
stm32f429.dtsi I suppose?
It is likely the same no matter which device is using spi5.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v3 2/5] dt-bindings: display: panel: Add ilitek ili9341 panel bindings
From: Linus Walleij @ 2020-05-14 8:21 UTC (permalink / raw)
To: dillon.minfei
Cc: Rob Herring, Maxime Coquelin, Alexandre TORGUE,
thierry.reding@gmail.com, Sam Ravnborg, Dave Airlie,
Daniel Vetter, Michael Turquette, Stephen Boyd,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-stm32, Linux ARM, linux-kernel@vger.kernel.org,
open list:DRM PANEL DRIVERS, linux-clk
In-Reply-To: <1589267017-17294-3-git-send-email-dillon.minfei@gmail.com>
On Tue, May 12, 2020 at 9:03 AM <dillon.minfei@gmail.com> wrote:
> From: dillon min <dillon.minfei@gmail.com>
>
> Add documentation for "ilitek,ili9341" panel.
>
> Signed-off-by: dillon min <dillon.minfei@gmail.com>
This looks good to me.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v3 5/5] drm/panel: Add ilitek ili9341 driver
From: Linus Walleij @ 2020-05-14 8:14 UTC (permalink / raw)
To: dillon.minfei
Cc: Rob Herring, Maxime Coquelin, Alexandre TORGUE,
thierry.reding@gmail.com, Sam Ravnborg, Dave Airlie,
Daniel Vetter, Michael Turquette, Stephen Boyd,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-stm32, Linux ARM, linux-kernel@vger.kernel.org,
open list:DRM PANEL DRIVERS, linux-clk
In-Reply-To: <1589267017-17294-6-git-send-email-dillon.minfei@gmail.com>
Hi Dillon,
thanks for your patch! Overall this looks like a good start.
On Tue, May 12, 2020 at 9:04 AM <dillon.minfei@gmail.com> wrote:
> #define ILI9341_SLEEP_OUT 0x11 /* Sleep out register */
This is not a register, also just use MIPI_DCS_EXIT_SLEEP_MODE
in the code.
> +#define ILI9341_DFC 0xb6 /* Display Function Control
> + * register
> + */
This commenting style doesn't work, either just put it after /* the define */
and don't care if the line gets a bit long and checkpatch complains,
or
/*
* Put it above the define like this
*/
#define FOO 0x00
> +/**
> + * struct ili9341_config - the system specific ILI9341 configuration
Nice with this per-system config, it makes the driver easy to maintain
for new users.
> +static int ili9341_dpi_init(struct ili9341 *ili)
> +{
> + ili9341_command(ili, 0xca, 0xc3, 0x08, 0x50);
This stuff is a bit hard to understand, don't you think?
But given that register 0xCA seems undocumented I don't
know if there is anything more you can do, so it is OK
I suppose.
> + ili9341_command(ili, ILI9341_POWERB, 0x00, 0xc1, 0x30);
This command is described in the manual page 196.
Version: V1.11
Document No.: ILI9341_DS_V1.11.pdf
https://dflund.se/~triad/ILI9341_v1.11.pdf
And this goes for all the below commands. Please add some more defines
from the datasheet and have less magic numbers in the driver.
> + ili9341_command(ili, ILI9341_POWER_SEQ, 0x64, 0x03, 0x12, 0x81);
> + ili9341_command(ili, ILI9341_DTCA, 0x85, 0x00, 0x78);
> + ili9341_command(ili, ILI9341_POWERA, 0x39, 0x2c, 0x00, 0x34, 0x02);
> + ili9341_command(ili, ILI9341_PRC, 0x20);
> + ili9341_command(ili, ILI9341_DTCB, 0x00, 0x00);
> + ili9341_command(ili, ILI9341_FRC, 0x00, 0x1b);
> + ili9341_command(ili, ILI9341_DFC, 0x0a, 0xa2);
> + ili9341_command(ili, ILI9341_POWER1, 0x10);
> + ili9341_command(ili, ILI9341_POWER2, 0x10);
> + ili9341_command(ili, ILI9341_VCOM1, 0x45, 0x15);
> + ili9341_command(ili, ILI9341_VCOM2, 0x90);
> + ili9341_command(ili, ILI9341_MAC, 0xc8);
> + ili9341_command(ili, ILI9341_3GAMMA_EN, 0x00);
> + ili9341_command(ili, ILI9341_RGB_INTERFACE, 0xc2);
> + ili9341_command(ili, ILI9341_DFC, 0x0a, 0xa7, 0x27, 0x04);
> + ili9341_command(ili, ILI9341_COLUMN_ADDR, 0x00, 0x00, 0x00, 0xef);
> + ili9341_command(ili, ILI9341_PAGE_ADDR, 0x00, 0x00, 0x01, 0x3f);
> + ili9341_command(ili, ILI9341_INTERFACE, 0x01, 0x00, 0x06);
> + if (ili->input == ILI9341_INPUT_PRGB_18_BITS)
> + ili9341_command(ili, ILI9341_PIXEL_FORMAT, 0x66);
> + else
> + ili9341_command(ili, ILI9341_PIXEL_FORMAT, 0x56);
> + ili9341_command(ili, ILI9341_GRAM);
> + msleep(200);
I think some of the above should not be hardcoded but should instead
be stored in fields in struct ili9341_config. I know it can be a bit
tedious but it makes things much more clear.
> + ili9341_command(ili, ILI9341_GAMMA, 0x01);
> + ili9341_command(ili, ILI9341_PGAMMA, 0x0f, 0x29, 0x24, 0x0c, 0x0e,
> + 0x09, 0x4e, 0x78, 0x3c, 0x09,
> + 0x13, 0x05, 0x17, 0x11, 0x00);
> + ili9341_command(ili, ILI9341_NGAMMA, 0x00, 0x16, 0x1b, 0x04, 0x11,
> + 0x07, 0x31, 0x33, 0x42, 0x05,
> + 0x0c, 0x0a, 0x28, 0x2f, 0x0f);
This should definately be in ili9341_config, as it is a screen property.
In the long run I would like these panels to support setting gamma
from userspace etc but it is a big tedious work to get that right
so hard-coding a default per-variant is fine.
You can check in e.g. panel-novatek-nt35510.c how I encoded
such sequences in per-variant data.
> +static int ili9341_dpi_power_off(struct ili9341 *ili)
> +{
> + /* Disable power */
> + if (!IS_ERR(ili->vcc))
> + return regulator_disable(ili->vcc);
> +
> + return 0;
> +}
Usually you should also assert RESET when disabling
power.
> +/* This is the only mode listed for parallel RGB in the datasheet */
> +static const struct drm_display_mode rgb_240x320_mode = {
> + .clock = 6100,
> + .hdisplay = 240,
> + .hsync_start = 240 + 10,
> + .hsync_end = 240 + 10 + 10,
> + .htotal = 240 + 10 + 10 + 20,
> + .vdisplay = 320,
> + .vsync_start = 320 + 4,
> + .vsync_end = 320 + 4 + 2,
> + .vtotal = 320 + 4 + 2 + 2,
> + .vrefresh = 60,
> + .flags = 0,
> + .width_mm = 65,
> + .height_mm = 50,
The width and height should certainly be om the ili9341_config
as it is a per-panel property. You can just fill in in in
the below .get_modes() function. Or assign the whole
mode as part of the ili9341_config if that is easier.
> + return drm_panel_add(&ili->panel);
> +}
> +
> +
> +
Surplus whitespace here.
> + mipi_dbi_command(dbi, MIPI_DCS_SET_DISPLAY_OFF);
> +
> + mipi_dbi_command(dbi, ILI9341_POWERB, 0x00, 0xc1, 0x30);
> + mipi_dbi_command(dbi, ILI9341_POWER_SEQ, 0x64, 0x03, 0x12, 0x81);
Some of these are just copies of the above init sequence, so it makes
even more sense to just have these settings stored in
ili9341_config.
> + mipi_dbi_command(dbi, ILI9341_DTCA, 0x85, 0x00, 0x78);
> + mipi_dbi_command(dbi, ILI9341_POWERA, 0x39, 0x2c, 0x00, 0x34, 0x02);
> + mipi_dbi_command(dbi, ILI9341_PRC, 0x20);
> + mipi_dbi_command(dbi, ILI9341_DTCB, 0x00, 0x00);
> +
> + /* Power Control */
> + mipi_dbi_command(dbi, ILI9341_POWER1, 0x23);
> + mipi_dbi_command(dbi, ILI9341_POWER2, 0x10);
> + /* VCOM */
> + mipi_dbi_command(dbi, ILI9341_VCOM1, 0x3e, 0x28);
> + mipi_dbi_command(dbi, ILI9341_VCOM2, 0x86);
> +
> + /* Memory Access Control */
> + mipi_dbi_command(dbi, MIPI_DCS_SET_PIXEL_FORMAT,
> + MIPI_DCS_PIXEL_FMT_16BIT);
> +
> + /* Frame Rate */
> + mipi_dbi_command(dbi, ILI9341_FRC, 0x00, 0x1b);
> +
> + /* Gamma */
> + mipi_dbi_command(dbi, ILI9341_3GAMMA_EN, 0x00);
> + mipi_dbi_command(dbi, MIPI_DCS_SET_GAMMA_CURVE, 0x01);
> + mipi_dbi_command(dbi, ILI9341_PGAMMA,
> + 0x0f, 0x31, 0x2b, 0x0c, 0x0e, 0x08, 0x4e, 0xf1,
> + 0x37, 0x07, 0x10, 0x03, 0x0e, 0x09, 0x00);
> + mipi_dbi_command(dbi, ILI9341_NGAMMA,
> + 0x00, 0x0e, 0x14, 0x03, 0x11, 0x07, 0x31, 0xc1,
> + 0x48, 0x08, 0x0f, 0x0c, 0x31, 0x36, 0x0f);
It seems to be copies of the stuff above, but why is there a different
gamma if you use DBI?
I suspect only one of them is really needed and it is not even
necessary to set if up in two places.
> +out_enable:
> + switch (dbidev->rotation) {
> + default:
> + addr_mode = ILI9341_MADCTL_MX;
> + break;> +out_enable:
> + switch (dbidev->rotation) {
> + default:
> + addr_mode = ILI9341_MADCTL_MX;
> + break;
> + case 90:
> + addr_mode = ILI9341_MADCTL_MV;
> + break;
> + case 180:
> + addr_mode = ILI9341_MADCTL_MY;
> + break;
> + case 270:
> + addr_mode = ILI9341_MADCTL_MV | ILI9341_MADCTL_MY |
> + ILI9341_MADCTL_MX;
> + break;
> + }
> + addr_mode |= ILI9341_MADCTL_BGR;
> + mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
> + mipi_dbi_enable_flush(dbidev, crtc_state, plane_state);
> + DRM_DEBUG_KMS("initialized display serial interface\n");
> +out_exit:
> + drm_dev_exit(idx);
> +}
> +
> + case 90:
> + addr_mode = ILI9341_MADCTL_MV;
> + break;
> + case 180:
> + addr_mode = ILI9341_MADCTL_MY;
> + break;
> + case 270:
> + addr_mode = ILI9341_MADCTL_MV | ILI9341_MADCTL_MY |
> + ILI9341_MADCTL_MX;
> + break;
> + }
> + addr_mode |= ILI9341_MADCTL_BGR;
> + mipi_dbi_command(dbi, MIPI_DCS_SET_ADDRESS_MODE, addr_mode);
Since you use MIPI_DCS_* define here, check if this applies
to more of the commands above so you don't need custom
defines for them. e.g.
ILI9341_SLEEP_OUT 0x11 = MIPI_DCS_EXIT_SLEEP_MODE
and that isn't even a register right, it is just a command?
(Noted in the beginning.)
Yours,
Linus Walleij
^ permalink raw reply
* Re: [v4,7/7] thermal: mediatek: use spinlock to protect PTPCORESEL
From: Daniel Lezcano @ 2020-05-14 8:08 UTC (permalink / raw)
To: Michael Kao, Matthias Brugger
Cc: Zhang Rui, Eduardo Valentin, Rob Herring, Mark Rutland, hsinyi,
linux-pm, srv_heupstream, devicetree, linux-mediatek,
linux-kernel, linux-arm-kernel
In-Reply-To: <1589439322.11120.2.camel@mtksdccf07>
On 14/05/2020 08:55, Michael Kao wrote:
> On Mon, 2020-03-23 at 20:15 +0800, Michael Kao wrote:
>> From: "michael.kao" <michael.kao@mediatek.com>
>>
>> The driver of thermal and svs will use the
>> same register for the project which should select
>> bank before reading sensor value.
>>
>> Signed-off-by: Michael Kao <michael.kao@mediatek.com>
>> ---
>> drivers/thermal/mtk_thermal.c | 9 ++++-----
>> 1 file changed, 4 insertions(+), 5 deletions(-)
>>
[ ... ]
> Hi Matthias,
Those patches fall under the thermal framework umbrella.
Thanks
-- Daniel
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* Re: [PATCH 2/6] soc: ti: omap-prm: Add basic power domain support
From: Tero Kristo @ 2020-05-14 8:04 UTC (permalink / raw)
To: Tony Lindgren, linux-omap
Cc: Andrew F . Davis, Santosh Shilimkar, Suman Anna, linux-kernel,
linux-arm-kernel, Rob Herring, devicetree
In-Reply-To: <20200512203852.29499-3-tony@atomide.com>
On 12/05/2020 23:38, Tony Lindgren wrote:
> The PRM controller has currently only support for resets while the power
> domains are still handled in the platform code.
>
> Let's add basic power domain support to enable and disable a PRM
> controlled power domain if configured in the devicetree. This can be
> used for various hardware accelerators, and interconnect instances.
>
> Further support can be added later on as needed for runtime configuration
> based on domain-idle-states.
>
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> ---
> arch/arm/mach-omap2/Kconfig | 1 +
> drivers/soc/ti/omap_prm.c | 281 +++++++++++++++++++++++++++++++++++-
> 2 files changed, 281 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -7,6 +7,7 @@ config ARCH_OMAP2
> depends on ARCH_MULTI_V6
> select ARCH_OMAP2PLUS
> select CPU_V6
> + select PM_GENERIC_DOMAINS if PM
> select SOC_HAS_OMAP2_SDRC
>
> config ARCH_OMAP3
> diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c
> --- a/drivers/soc/ti/omap_prm.c
> +++ b/drivers/soc/ti/omap_prm.c
> @@ -6,18 +6,50 @@
> * Tero Kristo <t-kristo@ti.com>
> */
>
> +#include <linux/clk.h>
> #include <linux/kernel.h>
> #include <linux/device.h>
> #include <linux/io.h>
> #include <linux/iopoll.h>
> +#include <linux/module.h>
> #include <linux/of.h>
> #include <linux/of_device.h>
> #include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> #include <linux/reset-controller.h>
> #include <linux/delay.h>
>
> #include <linux/platform_data/ti-prm.h>
>
> +enum omap_prm_clocks {
> + OMAP_PRM_FCK,
> + OMAP_PRM_ICK,
> + OMAP_PRM_NR_CLOCKS,
> +};
> +
> +enum omap_prm_domain_mode {
> + OMAP_PRMD_OFF,
> + OMAP_PRMD_RETENTION,
> + OMAP_PRMD_ON_INACTIVE,
> + OMAP_PRMD_ON_ACTIVE,
> +};
> +
> +struct omap_prm_domain_map {
> + unsigned int usable_modes; /* Mask of hardware supported modes */
> + unsigned long statechange:1; /* Optional low-power state change */
> + unsigned long logicretstate:1; /* Optional logic off mode */
> +};
> +
> +struct omap_prm_domain {
> + struct device *dev;
> + struct omap_prm *prm;
> + struct generic_pm_domain pd;
> + void __iomem *pwrstctrl;
> + void __iomem *pwrstst;
I think the pwrstst is not really used as of now, it is just part of
couple of dev_dbg prints.
> + const struct omap_prm_domain_map *cap;
> + u32 pwrstctrl_saved;
> +};
> +
> struct omap_rst_map {
> s8 rst;
> s8 st;
> @@ -27,6 +59,9 @@ struct omap_prm_data {
> u32 base;
> const char *name;
> const char *clkdm_name;
> + u16 pwrstctrl;
> + u16 pwrstst;
> + const struct omap_prm_domain_map *dmap;
> u16 rstctrl;
> u16 rstst;
> const struct omap_rst_map *rstmap;
> @@ -36,6 +71,8 @@ struct omap_prm_data {
> struct omap_prm {
> const struct omap_prm_data *data;
> void __iomem *base;
> + struct clk *clocks[OMAP_PRM_NR_CLOCKS];
> + struct omap_prm_domain *prmd;
> };
>
> struct omap_reset_data {
> @@ -47,6 +84,7 @@ struct omap_reset_data {
> struct device *dev;
> };
>
> +#define genpd_to_prm_domain(gpd) container_of(gpd, struct omap_prm_domain, pd)
> #define to_omap_reset_data(p) container_of((p), struct omap_reset_data, rcdev)
>
> #define OMAP_MAX_RESETS 8
> @@ -58,6 +96,40 @@ struct omap_reset_data {
>
> #define OMAP_PRM_HAS_RESETS (OMAP_PRM_HAS_RSTCTRL | OMAP_PRM_HAS_RSTST)
>
> +#define PRM_LOGICRETSTATE BIT(2)
> +#define PRM_LOWPOWERSTATECHANGE BIT(4)
> +#define PRM_POWERSTATE_MASK OMAP_PRMD_ON_ACTIVE
> +
> +static const struct __maybe_unused
> +omap_prm_domain_map omap_prm_all = {
> + .usable_modes = BIT(OMAP_PRMD_ON_ACTIVE) | BIT(OMAP_PRMD_ON_INACTIVE) |
> + BIT(OMAP_PRMD_RETENTION) | BIT(OMAP_PRMD_OFF),
> + .statechange = 1,
> + .logicretstate = 1,
> +};
> +
> +static const struct __maybe_unused
> +omap_prm_domain_map omap_prm_noinact = {
> + .usable_modes = BIT(OMAP_PRMD_ON_ACTIVE) | BIT(OMAP_PRMD_RETENTION) |
> + BIT(OMAP_PRMD_OFF),
> + .statechange = 1,
> + .logicretstate = 1,
> +};
> +
> +static const struct __maybe_unused
> +omap_prm_domain_map omap_prm_nooff = {
> + .usable_modes = BIT(OMAP_PRMD_ON_ACTIVE) | BIT(OMAP_PRMD_ON_INACTIVE) |
> + BIT(OMAP_PRMD_RETENTION),
> + .statechange = 1,
> + .logicretstate = 1,
> +};
> +
> +static const struct __maybe_unused
> +omap_prm_domain_map omap_prm_onoff_noauto = {
> + .usable_modes = BIT(OMAP_PRMD_ON_ACTIVE) | BIT(OMAP_PRMD_OFF),
> + .statechange = 1,
> +};
> +
> static const struct omap_rst_map rst_map_0[] = {
> { .rst = 0, .st = 0 },
> { .rst = -1 },
> @@ -151,6 +223,152 @@ static const struct of_device_id omap_prm_id_table[] = {
> { },
> };
>
> +static int omap_prm_domain_power_on(struct generic_pm_domain *domain)
> +{
> + struct omap_prm_domain *prmd;
> + u32 v;
> +
> + prmd = genpd_to_prm_domain(domain);
> + if (!prmd->cap)
> + return 0;
> +
> + dev_dbg(prmd->dev, "%s: %s: old state: pwrstctrl: %08x pwrstst: %08x\n",
> + __func__, prmd->pd.name, readl_relaxed(prmd->pwrstctrl),
> + readl_relaxed(prmd->pwrstst));
> +
> + if (prmd->pwrstctrl_saved)
> + v = prmd->pwrstctrl_saved;
> + else
> + v = readl_relaxed(prmd->pwrstctrl);
> +
> + writel_relaxed(v | OMAP_PRMD_ON_ACTIVE, prmd->pwrstctrl);
> + dev_dbg(prmd->dev, "%s: %s: new state pwrstctrl: %08x\n",
> + __func__, prmd->pd.name, readl_relaxed(prmd->pwrstctrl));
Should we wait for the transition to complete here?
> +
> + return 0;
> +}
> +
> +/* No need to check for holes in the mask for the lowest mode */
> +static int omap_prm_domain_find_lowest(struct omap_prm_domain *prmd)
> +{
> + return __ffs(prmd->cap->usable_modes);
> +}
> +
> +static int omap_prm_domain_power_off(struct generic_pm_domain *domain)
> +{
> + struct omap_prm_domain *prmd;
> + u32 v;
> +
> + prmd = genpd_to_prm_domain(domain);
> + if (!prmd->cap)
> + return 0;
> +
> + v = readl_relaxed(prmd->pwrstctrl);
> + prmd->pwrstctrl_saved = v;
> +
> + dev_dbg(prmd->dev, "%s: %s: old state: pwrstctrl: %08x pwrstst: %08x\n",
> + __func__, prmd->pd.name, v, readl_relaxed(prmd->pwrstst));
> +
> + v &= ~PRM_POWERSTATE_MASK;
> + v |= omap_prm_domain_find_lowest(prmd);
> +
> + if (prmd->cap->statechange)
> + v |= PRM_LOWPOWERSTATECHANGE;
> + if (prmd->cap->logicretstate)
> + v &= ~PRM_LOGICRETSTATE;
> + else
> + v |= PRM_LOGICRETSTATE;
> +
> + writel_relaxed(v, prmd->pwrstctrl);
Should we wait for the transition to complete here?
> +
> + dev_dbg(prmd->dev, "%s: %s new state pwrstctrl: %08x\n",
> + __func__, prmd->pd.name, readl_relaxed(prmd->pwrstctrl));
> +
> + return 0;
> +}
> +
> +static int omap_prm_domain_attach_dev(struct generic_pm_domain *domain,
> + struct device *dev)
> +{
> + struct generic_pm_domain_data *genpd_data;
> + struct of_phandle_args pd_args;
> + struct omap_prm_domain *prmd;
> + struct device_node *np;
> + int ret;
> +
> + prmd = genpd_to_prm_domain(domain);
> + np = dev->of_node;
> +
> + ret = of_parse_phandle_with_args(np, "power-domains",
> + "#power-domain-cells", 0, &pd_args);
> + if (ret < 0)
> + return ret;
> +
> + if (pd_args.args_count != 0)
> + dev_warn(dev, "%s: unusupported #power-domain-cells: %i\n",
> + prmd->pd.name, pd_args.args_count);
> +
> + genpd_data = dev_gpd_data(dev);
> + genpd_data->data = NULL;
> +
> + return 0;
> +}
> +
> +static void omap_prm_domain_detach_dev(struct generic_pm_domain *domain,
> + struct device *dev)
> +{
> + struct generic_pm_domain_data *genpd_data;
> + struct omap_prm_domain *prmd;
> +
> + prmd = genpd_to_prm_domain(domain);
> +
> + genpd_data = dev_gpd_data(dev);
> + genpd_data->data = NULL;
> +}
> +
> +static int omap_prm_domain_init(struct device *dev, struct omap_prm *prm)
> +{
> + struct omap_prm_domain *prmd;
> + struct device_node *np = dev->of_node;
> + const struct omap_prm_data *data;
> + const char *name;
> + int error;
> +
> + if (!of_find_property(dev->of_node, "#power-domain-cells", NULL))
> + return 0;
> +
> + of_node_put(dev->of_node);
> +
> + prmd = devm_kzalloc(dev, sizeof(*prmd), GFP_KERNEL);
> + if (!prmd)
> + return -ENOMEM;
> +
> + data = prm->data;
> + name = devm_kasprintf(dev, GFP_KERNEL, "prm_%s",
> + data->name);
> +
> + prmd->dev = dev;
> + prmd->prm = prm;
> + prmd->cap = prmd->prm->data->dmap;
> + prmd->pwrstctrl = prmd->prm->base + prmd->prm->data->pwrstctrl;
> + prmd->pwrstst = prmd->prm->base + prmd->prm->data->pwrstst;
> +
> + prmd->pd.name = name;
> + prmd->pd.power_on = omap_prm_domain_power_on;
> + prmd->pd.power_off = omap_prm_domain_power_off;
> + prmd->pd.attach_dev = omap_prm_domain_attach_dev;
> + prmd->pd.detach_dev = omap_prm_domain_detach_dev;
> +
> + pm_genpd_init(&prmd->pd, NULL, true);
> + error = of_genpd_add_provider_simple(np, &prmd->pd);
> + if (error)
> + pm_genpd_remove(&prmd->pd);
> + else
> + prm->prmd = prmd;
> +
> + return error;
> +}
> +
> static bool _is_valid_reset(struct omap_reset_data *reset, unsigned long id)
> {
> if (reset->mask & BIT(id))
> @@ -345,12 +563,48 @@ static int omap_prm_reset_init(struct platform_device *pdev,
> return devm_reset_controller_register(&pdev->dev, &reset->rcdev);
> }
>
Is any of the following clock handling needed, and if yes, whats its
purpose?
It looks like this is only used for ABE clkctrl handling on omap4/omap5
(at least for now), but afaik, ABE clkctrl is read only so this code
would effectively do nothing (and potentially just even fail.)
-Tero
> +static int omap_prm_init_clock(struct device *dev, struct omap_prm *prm,
> + const char *name, enum omap_prm_clocks index)
> +{
> + struct clk *clock;
> + int error;
> +
> + clock = devm_clk_get(dev, name);
> + if (IS_ERR(clock)) {
> + if (PTR_ERR(clock) == -ENOENT)
> + error = 0;
> + else
> + error = PTR_ERR(prm->clocks[index]);
> +
> + goto out_done;
> + }
> +
> + error = clk_prepare_enable(clock);
> +
> +out_done:
> + prm->clocks[index] = clock;
> +
> + return error;
> +}
> +
> +static void omap_prm_disable_clocks(struct omap_prm *prm)
> +{
> + int i;
> +
> + for (i = 0; i < OMAP_PRM_NR_CLOCKS; i++) {
> + if (IS_ERR(prm->clocks[i]))
> + continue;
> + clk_disable_unprepare(prm->clocks[i]);
> + }
> +}
> +
> static int omap_prm_probe(struct platform_device *pdev)
> {
> struct resource *res;
> const struct omap_prm_data *data;
> struct omap_prm *prm;
> const struct of_device_id *match;
> + int ret;
>
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> if (!res)
> @@ -378,7 +632,32 @@ static int omap_prm_probe(struct platform_device *pdev)
> if (IS_ERR(prm->base))
> return PTR_ERR(prm->base);
>
> - return omap_prm_reset_init(pdev, prm);
> + ret = omap_prm_init_clock(&pdev->dev, prm, "fck", OMAP_PRM_FCK);
> + if (ret)
> + goto err_disable;
> +
> + ret = omap_prm_init_clock(&pdev->dev, prm, "ick", OMAP_PRM_ICK);
> + if (ret)
> + goto err_disable;
> +
> + ret = omap_prm_domain_init(&pdev->dev, prm);
> + if (ret)
> + goto err_disable;
> +
> + ret = omap_prm_reset_init(pdev, prm);
> + if (ret)
> + goto err_domain;
> +
> + return 0;
> +
> +err_domain:
> + of_genpd_del_provider(pdev->dev.of_node);
> + pm_genpd_remove(&prm->prmd->pd);
> +
> +err_disable:
> + omap_prm_disable_clocks(prm);
> +
> + return ret;
> }
>
> static struct platform_driver omap_prm_driver = {
>
--
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