* Re: [PATCH v4 06/10] dt-bindings: mtd: update STM32 FMC2 NAND controller documentation
From: Christophe Kerello @ 2020-05-14 16:34 UTC (permalink / raw)
To: Rob Herring
Cc: miquel.raynal, richard, vigneshr, mark.rutland, gregkh,
boris.brezillon, linux-mtd, linux-kernel, linux-stm32, devicetree,
marex
In-Reply-To: <20200514150028.GB28489@bogus>
Hi Rob,
On 5/14/20 5:00 PM, Rob Herring wrote:
> On Wed, May 06, 2020 at 11:11:15AM +0200, Christophe Kerello wrote:
>> These bindings can be used on SOCs where the FMC2 NAND controller is
>> in standalone. In case that the FMC2 embeds 2 controllers (an external
>> bus controller and a raw NAND controller), the register base and the
>> clock will be defined in the parent node. It is the reason why the
>> register base address and the clock are now optional.
>>
>> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
>> ---
>> .../devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml | 19 ++++++++++---------
>> 1 file changed, 10 insertions(+), 9 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml b/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml
>> index b059267..68fac1a 100644
>> --- a/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml
>> +++ b/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml
>> @@ -18,13 +18,15 @@ properties:
>>
>> reg:
>> items:
>> - - description: Registers
>> + - description: Registers (optional)
>
> The only thing that can be optional are the last entries. You have to do
> a 'oneOf' with 6 entries and 7 entries.
Ok, so the way to describe the reg property in my case should be:
reg:
oneOf:
- description: FMC2 embeds the NFC controller in standalone.
items:
- description: Registers
- description: Chip select 0 data
- description: Chip select 0 command
- description: Chip select 0 address space
- description: Chip select 1 data
- description: Chip select 1 command
- description: Chip select 1 address space
- description: FMC2 embeds the NFC controller and the EBI
controller.
items:
- description: Chip select 0 data
- description: Chip select 0 command
- description: Chip select 0 address space
- description: Chip select 1 data
- description: Chip select 1 command
- description: Chip select 1 address space
>
> And where's your new compatible string for this different h/w?
From NFC controller point of view, it is the same HW.
In the case that we have 2 controllers embedded, the register base is
shared.
The NFC driver will check at probe time the compatible string of its
parent node.
In case that it is "st,stm32mp1-fmc2-ebi", then the driver will find the
register base in the parent node (EBI node), otherwise it will find it
in the NFC node.
Is it better to have 2 compatible strings (one for each reg description)
than checking the parent's compatible string and have only one
compatible string?
Regards,
Christophe Kerello.
>
>> - description: Chip select 0 data
>> - description: Chip select 0 command
>> - description: Chip select 0 address space
>> - description: Chip select 1 data
>> - description: Chip select 1 command
>> - description: Chip select 1 address space
>> + minItems: 6
>> + maxItems: 7
>>
>> interrupts:
>> maxItems: 1
>> @@ -61,7 +63,6 @@ required:
>> - compatible
>> - reg
>> - interrupts
>> - - clocks
>>
>> examples:
>> - |
>> @@ -77,13 +78,13 @@ examples:
>> <0x81000000 0x1000>,
>> <0x89010000 0x1000>,
>> <0x89020000 0x1000>;
>> - interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
>> - dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
>> - <&mdma1 20 0x10 0x12000a08 0x0 0x0>,
>> - <&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
>> - dma-names = "tx", "rx", "ecc";
>> - clocks = <&rcc FMC_K>;
>> - resets = <&rcc FMC_R>;
>> + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
>> + dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
>> + <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
>> + <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
>> + dma-names = "tx", "rx", "ecc";
>> + clocks = <&rcc FMC_K>;
>> + resets = <&rcc FMC_R>;
>> #address-cells = <1>;
>> #size-cells = <0>;
>>
>> --
>> 1.9.1
>>
^ permalink raw reply
* Re: [PATCH v4 07/10] dt-bindings: memory-controller: add STM32 FMC2 EBI controller documentation
From: Christophe Kerello @ 2020-05-14 16:37 UTC (permalink / raw)
To: Rob Herring
Cc: miquel.raynal, richard, vigneshr, mark.rutland, gregkh,
boris.brezillon, linux-mtd, linux-kernel, linux-stm32, devicetree,
marex
In-Reply-To: <20200514150730.GA10372@bogus>
Hi Rob,
On 5/14/20 5:07 PM, Rob Herring wrote:
> On Wed, May 06, 2020 at 11:11:16AM +0200, Christophe Kerello wrote:
>> This patch adds the documentation of the device tree bindings for the STM32
>> FMC2 EBI controller.
>>
>> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
>> ---
>> Changes in v4:
>> - fix filename: st,stm32-fmc2-ebi.yaml
>>
>> Changes in v3:
>> - pattern name has been modified
>> - vendor properties have been modified
>> - s/_/-/
>> - add unit suffix (-ns) on timing properties
>>
>> .../memory-controllers/st,stm32-fmc2-ebi.yaml | 261 +++++++++++++++++++++
>> 1 file changed, 261 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
>> new file mode 100644
>> index 0000000..bf130c3
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/memory-controllers/st,stm32-fmc2-ebi.yaml
>> @@ -0,0 +1,261 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: STMicroelectronics Flexible Memory Controller 2 (FMC2) Bindings
>> +
>> +description: |
>> + The FMC2 functional block makes the interface with: synchronous and
>> + asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
>> + peripherals) and NAND flash memories.
>> + Its main purposes are:
>> + - to translate AXI transactions into the appropriate external device
>> + protocol
>> + - to meet the access time requirements of the external devices
>> + All external devices share the addresses, data and control signals with the
>> + controller. Each external device is accessed by means of a unique Chip
>> + Select. The FMC2 performs only one access at a time to an external device.
>> +
>> +maintainers:
>> + - Christophe Kerello <christophe.kerello@st.com>
>> +
>> +properties:
>> + compatible:
>> + const: st,stm32mp1-fmc2-ebi
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + maxItems: 1
>> +
>> + resets:
>> + maxItems: 1
>> +
>> + "#address-cells":
>> + const: 2
>> +
>> + "#size-cells":
>> + const: 1
>> +
>> + ranges:
>> + description: |
>> + Reflects the memory layout with four integer values per bank. Format:
>> + <bank-number> 0 <address of the bank> <size>
>> +
>> +patternProperties:
>> + "^.*@[0-4],[a-f0-9]+$":
>> + type: object
>> +
>> + properties:
>> + reg:
>> + description: Bank number, base address and size of the device.
>> +
>> + st,fmc2-ebi-cs-transaction-type:
>> + description: |
>> + Select one of the transactions type supported
>
> Indent should be 2 more than 'description'.
Ok, it will be part of v5.
>
>> + 0: Asynchronous mode 1 SRAM/FRAM.
>> + 1: Asynchronous mode 1 PSRAM.
>> + 2: Asynchronous mode A SRAM/FRAM.
>> + 3: Asynchronous mode A PSRAM.
>> + 4: Asynchronous mode 2 NOR.
>> + 5: Asynchronous mode B NOR.
>> + 6: Asynchronous mode C NOR.
>> + 7: Asynchronous mode D NOR.
>> + 8: Synchronous read synchronous write PSRAM.
>> + 9: Synchronous read asynchronous write PSRAM.
>> + 10: Synchronous read synchronous write NOR.
>> + 11: Synchronous read asynchronous write NOR.
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + minimum: 0
>> + maximum: 11
>> +
>> + st,fmc2-ebi-cs-cclk-enable:
>> + description: Continuous clock enable (first bank must be configured
>> + in synchronous mode). The FMC_CLK is generated continuously
>> + during asynchronous and synchronous access. By default, the
>> + FMC_CLK is only generated during synchronous access.
>
> Indent 2 more than 'description'. You can run this through yaml-format
> in dtschema repo and it will re-flow everything for you.
Ok, it will be part of v5.
Regards,
Christophe Kerello.
>
> With these fixed,
>
> Reviewed-by: Rob Herring <robh@kernel.org>
>
>
>> + $ref: /schemas/types.yaml#/definitions/flag
>> +
>> + st,fmc2-ebi-cs-mux-enable:
>> + description: Address/Data multiplexed on databus (valid only with
>> + NOR and PSRAM transactions type). By default, Address/Data
>> + are not multiplexed.
>> + $ref: /schemas/types.yaml#/definitions/flag
>> +
>> + st,fmc2-ebi-cs-buswidth:
>> + description: Data bus width
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + enum: [ 8, 16 ]
>> + default: 16
>> +
>> + st,fmc2-ebi-cs-waitpol-high:
>> + description: Wait signal polarity (NWAIT signal active high).
>> + By default, NWAIT is active low.
>> + $ref: /schemas/types.yaml#/definitions/flag
>> +
>> + st,fmc2-ebi-cs-waitcfg-enable:
>> + description: The NWAIT signal indicates wheither the data from the
>> + device are valid or if a wait state must be inserted when
>> + accessing the device in synchronous mode. By default, the
>> + NWAIT signal is active one data cycle before wait state.
>> + $ref: /schemas/types.yaml#/definitions/flag
>> +
>> + st,fmc2-ebi-cs-wait-enable:
>> + description: The NWAIT signal is enabled (its level is taken into
>> + account after the programmed latency period to insert wait
>> + states if asserted). By default, the NWAIT signal is
>> + disabled.
>> + $ref: /schemas/types.yaml#/definitions/flag
>> +
>> + st,fmc2-ebi-cs-asyncwait-enable:
>> + description: The NWAIT signal is taken into account during asynchronous
>> + transactions. By default, the NWAIT signal is not taken
>> + into account during asynchronous transactions.
>> + $ref: /schemas/types.yaml#/definitions/flag
>> +
>> + st,fmc2-ebi-cs-cpsize:
>> + description: CRAM page size. The controller splits the burst access
>> + when the memory page is reached. By default, no burst
>> + split when crossing page boundary.
>> + $ref: /schemas/types.yaml#/definitions/uint32
>> + enum: [ 0, 128, 256, 512, 1024 ]
>> + default: 0
>> +
>> + st,fmc2-ebi-cs-byte-lane-setup-ns:
>> + description: This property configures the byte lane setup timing
>> + defined in nanoseconds from NBLx low to Chip Select NEx
>> + low.
>> +
>> + st,fmc2-ebi-cs-address-setup-ns:
>> + description: This property defines the duration of the address setup
>> + phase in nanoseconds used for asynchronous read/write
>> + transactions.
>> +
>> + st,fmc2-ebi-cs-address-hold-ns:
>> + description: This property defines the duration of the address hold
>> + phase in nanoseconds used for asynchronous multiplexed
>> + read/write transactions.
>> +
>> + st,fmc2-ebi-cs-data-setup-ns:
>> + description: This property defines the duration of the data setup phase
>> + in nanoseconds used for asynchronous read/write
>> + transactions.
>> +
>> + st,fmc2-ebi-cs-bus-turnaround-ns:
>> + description: This property defines the delay in nanoseconds between the
>> + end of current read/write transaction and the next
>> + transaction.
>> +
>> + st,fmc2-ebi-cs-data-hold-ns:
>> + description: This property defines the duration of the data hold phase
>> + in nanoseconds used for asynchronous read/write
>> + transactions.
>> +
>> + st,fmc2-ebi-cs-clk-period-ns:
>> + description: This property defines the FMC_CLK output signal period in
>> + nanoseconds.
>> +
>> + st,fmc2-ebi-cs-data-latency-ns:
>> + description: This property defines the data latency before reading or
>> + writing the first data in nanoseconds.
>> +
>> + st,fmc2_ebi-cs-write-address-setup-ns:
>> + description: This property defines the duration of the address setup
>> + phase in nanoseconds used for asynchronous write
>> + transactions.
>> +
>> + st,fmc2-ebi-cs-write-address-hold-ns:
>> + description: This property defines the duration of the address hold
>> + phase in nanoseconds used for asynchronous multiplexed
>> + write transactions.
>> +
>> + st,fmc2-ebi-cs-write-data-setup-ns:
>> + description: This property defines the duration of the data setup
>> + phase in nanoseconds used for asynchronous write
>> + transactions.
>> +
>> + st,fmc2-ebi-cs-write-bus-turnaround-ns:
>> + description: This property defines the delay between the end of current
>> + write transaction and the next transaction in nanoseconds.
>> +
>> + st,fmc2-ebi-cs-write-data-hold-ns:
>> + description: This property defines the duration of the data hold phase
>> + in nanoseconds used for asynchronous write transactions.
>> +
>> + st,fmc2-ebi-cs-max-low-pulse-ns:
>> + description: This property defines the maximum chip select low pulse
>> + duration in nanoseconds for synchronous transactions. When
>> + this timing reaches 0, the controller splits the current
>> + access, toggles NE to allow device refresh and restarts a
>> + new access.
>> +
>> + required:
>> + - reg
>> +
>> +required:
>> + - "#address-cells"
>> + - "#size-cells"
>> + - compatible
>> + - reg
>> + - clocks
>> + - ranges
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> + #include <dt-bindings/clock/stm32mp1-clks.h>
>> + #include <dt-bindings/reset/stm32mp1-resets.h>
>> + memory-controller@58002000 {
>> + #address-cells = <2>;
>> + #size-cells = <1>;
>> + compatible = "st,stm32mp1-fmc2-ebi";
>> + reg = <0x58002000 0x1000>;
>> + clocks = <&rcc FMC_K>;
>> + resets = <&rcc FMC_R>;
>> +
>> + ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
>> + <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
>> + <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
>> + <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
>> + <4 0 0x80000000 0x10000000>; /* NAND */
>> +
>> + psram@0,0 {
>> + compatible = "mtd-ram";
>> + reg = <0 0x00000000 0x100000>;
>> + bank-width = <2>;
>> +
>> + st,fmc2-ebi-cs-transaction-type = <1>;
>> + st,fmc2-ebi-cs-address-setup-ns = <60>;
>> + st,fmc2-ebi-cs-data-setup-ns = <30>;
>> + st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
>> + };
>> +
>> + nand-controller@4,0 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + compatible = "st,stm32mp15-fmc2";
>> + reg = <4 0x00000000 0x1000>,
>> + <4 0x08010000 0x1000>,
>> + <4 0x08020000 0x1000>,
>> + <4 0x01000000 0x1000>,
>> + <4 0x09010000 0x1000>,
>> + <4 0x09020000 0x1000>;
>> + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
>> + dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
>> + <&mdma1 20 0x2 0x12000a08 0x0 0x0>,
>> + <&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
>> + dma-names = "tx", "rx", "ecc";
>> +
>> + nand@0 {
>> + reg = <0>;
>> + nand-on-flash-bbt;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + };
>> + };
>> + };
>> +
>> +...
>> --
>> 1.9.1
>>
^ permalink raw reply
* [PATCH v1] make implementation of read16, read32 and write32 optional fix
From: amirmizi6 @ 2020-05-14 16:48 UTC (permalink / raw)
To: Eyal.Cohen, jarkko.sakkinen, oshrialkoby85, alexander.steffen,
robh+dt, "benoit.houyere, peterhuewe, christophe-h.richard,
jgg, arnd, gregkh
Cc: devicetree, linux-kernel, linux-integrity, oshri.alkoby,
tmaimon77, gcwilson, kgoldman, Dan.Morav, oren.tanami,
shmulik.hager, amir.mizinski, Amir Mizinski
From: Amir Mizinski <amirmizi6@gmail.com>
This patch fix compilation error for newly added CR50 SPI driver found in previous submission.
Amir Mizinski (1):
tpm: tpm_tis: make implementation of read16, read32 and write32
optional fix
drivers/char/tpm/tpm_tis_spi.h | 4 ----
drivers/char/tpm/tpm_tis_spi_cr50.c | 3 ---
2 files changed, 7 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH v1] tpm: tpm_tis: make implementation of read16, read32 and write32 optional fix
From: amirmizi6 @ 2020-05-14 16:48 UTC (permalink / raw)
To: Eyal.Cohen, jarkko.sakkinen, oshrialkoby85, alexander.steffen,
robh+dt, "benoit.houyere, peterhuewe, christophe-h.richard,
jgg, arnd, gregkh
Cc: devicetree, linux-kernel, linux-integrity, oshri.alkoby,
tmaimon77, gcwilson, kgoldman, Dan.Morav, oren.tanami,
shmulik.hager, amir.mizinski, Amir Mizinski, kbuild test robot
In-Reply-To: <20200514164825.35377-1-amirmizi6@gmail.com>
From: Amir Mizinski <amirmizi6@gmail.com>
Removed SPI extern function definitions and unused callback functions for
CR50 driver.
Fixes: fa05dc792ea0 ("tpm: tpm_tis: make implementation of read16, read32 and write32 optional")
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Amir Mizinski <amirmizi6@gmail.com>
---
drivers/char/tpm/tpm_tis_spi.h | 4 ----
drivers/char/tpm/tpm_tis_spi_cr50.c | 3 ---
2 files changed, 7 deletions(-)
diff --git a/drivers/char/tpm/tpm_tis_spi.h b/drivers/char/tpm/tpm_tis_spi.h
index bba7397..d0f66f6 100644
--- a/drivers/char/tpm/tpm_tis_spi.h
+++ b/drivers/char/tpm/tpm_tis_spi.h
@@ -31,10 +31,6 @@ extern int tpm_tis_spi_init(struct spi_device *spi, struct tpm_tis_spi_phy *phy,
extern int tpm_tis_spi_transfer(struct tpm_tis_data *data, u32 addr, u16 len,
u8 *in, const u8 *out);
-extern int tpm_tis_spi_read16(struct tpm_tis_data *data, u32 addr, u16 *result);
-extern int tpm_tis_spi_read32(struct tpm_tis_data *data, u32 addr, u32 *result);
-extern int tpm_tis_spi_write32(struct tpm_tis_data *data, u32 addr, u32 value);
-
#ifdef CONFIG_TCG_TIS_SPI_CR50
extern int cr50_spi_probe(struct spi_device *spi);
#else
diff --git a/drivers/char/tpm/tpm_tis_spi_cr50.c b/drivers/char/tpm/tpm_tis_spi_cr50.c
index 37d72e8..f339d20 100644
--- a/drivers/char/tpm/tpm_tis_spi_cr50.c
+++ b/drivers/char/tpm/tpm_tis_spi_cr50.c
@@ -215,9 +215,6 @@ static int tpm_tis_spi_cr50_write_bytes(struct tpm_tis_data *data, u32 addr,
static const struct tpm_tis_phy_ops tpm_spi_cr50_phy_ops = {
.read_bytes = tpm_tis_spi_cr50_read_bytes,
.write_bytes = tpm_tis_spi_cr50_write_bytes,
- .read16 = tpm_tis_spi_read16,
- .read32 = tpm_tis_spi_read32,
- .write32 = tpm_tis_spi_write32,
};
static void cr50_print_fw_version(struct tpm_tis_data *data)
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v5 0/5] remoteproc: qcom: PIL info support
From: Vinod Koul @ 2020-05-14 16:53 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, Ohad Ben-Cohen, Rob Herring, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel
In-Reply-To: <20200513055641.1413100-1-bjorn.andersson@linaro.org>
On 12-05-20, 22:56, Bjorn Andersson wrote:
> Introduce support for filling out the relocation information in IMEM, to aid
> post mortem debug tools to locate the various remoteprocs.
Reviewed-by: Vinod Koul <vkoul@kernel.org>
--
~Vinod
^ permalink raw reply
* Re: [PATCH 3/4] hwspinlock: qcom: Allow mmio usage in addition to syscon
From: Bjorn Andersson @ 2020-05-14 17:00 UTC (permalink / raw)
To: Vinod Koul
Cc: Andy Gross, Ohad Ben-Cohen, Baolin Wang, Rob Herring,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel
In-Reply-To: <20200514141523.GW14092@vkoul-mobl>
On Thu 14 May 07:15 PDT 2020, Vinod Koul wrote:
> On 12-05-20, 17:54, Bjorn Andersson wrote:
> > In all modern Qualcomm platforms the mutex region of the TCSR is forked
> > off into its own block, all with a offset of 0 and stride of 4096. So
> > add support for directly memory mapping this register space, to avoid
> > the need to represent this block using a syscon.
> >
> > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > ---
> > drivers/hwspinlock/qcom_hwspinlock.c | 72 +++++++++++++++++++++-------
> > 1 file changed, 56 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/hwspinlock/qcom_hwspinlock.c b/drivers/hwspinlock/qcom_hwspinlock.c
> > index f0da544b14d2..d8d4d729816c 100644
> > --- a/drivers/hwspinlock/qcom_hwspinlock.c
> > +++ b/drivers/hwspinlock/qcom_hwspinlock.c
> > @@ -70,41 +70,81 @@ static const struct of_device_id qcom_hwspinlock_of_match[] = {
> > };
> > MODULE_DEVICE_TABLE(of, qcom_hwspinlock_of_match);
> >
> > -static int qcom_hwspinlock_probe(struct platform_device *pdev)
> > +static struct regmap *qcom_hwspinlock_probe_syscon(struct platform_device *pdev,
> > + u32 *base, u32 *stride)
> > {
> > - struct hwspinlock_device *bank;
> > struct device_node *syscon;
> > - struct reg_field field;
> > struct regmap *regmap;
> > - size_t array_size;
> > - u32 stride;
> > - u32 base;
> > int ret;
> > - int i;
> >
> > syscon = of_parse_phandle(pdev->dev.of_node, "syscon", 0);
> > - if (!syscon) {
> > - dev_err(&pdev->dev, "no syscon property\n");
>
> any reason to drop the log?
>
Given that we first check for the syscon and then fall back to trying to
use the reg, keeping this line would cause this log line to always show
up on targets putting this under /soc.
So I think it's better to drop the line and then require the presence of
either syscon or reg using the DT schema.
> > - return -ENODEV;
> > - }
> > + if (!syscon)
> > + return ERR_PTR(-ENODEV);
> >
> > regmap = syscon_node_to_regmap(syscon);
> > of_node_put(syscon);
> > if (IS_ERR(regmap))
> > - return PTR_ERR(regmap);
> > + return regmap;
> >
> > - ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, &base);
> > + ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, base);
> > if (ret < 0) {
> > dev_err(&pdev->dev, "no offset in syscon\n");
> > - return -EINVAL;
> > + return ERR_PTR(-EINVAL);
> > }
> >
> > - ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 2, &stride);
> > + ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 2, stride);
> > if (ret < 0) {
> > dev_err(&pdev->dev, "no stride syscon\n");
> > - return -EINVAL;
> > + return ERR_PTR(-EINVAL);
> > }
> >
> > + return regmap;
> > +}
> > +
> > +static const struct regmap_config tcsr_mutex_config = {
> > + .reg_bits = 32,
> > + .reg_stride = 4,
> > + .val_bits = 32,
> > + .max_register = 0x40000,
> > + .fast_io = true,
> > +};
> > +
> > +static struct regmap *qcom_hwspinlock_probe_mmio(struct platform_device *pdev,
> > + u32 *offset, u32 *stride)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct resource *res;
> > + void __iomem *base;
> > +
> > + /* All modern platform has offset 0 and stride of 4k */
> > + *offset = 0;
> > + *stride = 0x1000;
>
> Wouldn't it make sense to read this from DT rather than code in kernel?
>
I did consider this as well as platform specific compatibles, but
realized that pretty much all 64-bit targets have these values. So given
that we still can represent this using the syscon approach I don't think
we need to add yet another mechanism to specify these.
Thanks,
Bjorn
^ permalink raw reply
* [PATCHv1] ARM: dts/imx6q-bx50v3: Set display interface clock parents
From: Sebastian Reichel @ 2020-05-14 17:02 UTC (permalink / raw)
To: Sebastian Reichel, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team
Cc: Rob Herring, devicetree, linux-kernel, kernel, Robert Beckett,
stable, Ian Ray, Sebastian Reichel
From: Robert Beckett <bob.beckett@collabora.com>
Avoid LDB and IPU DI clocks both using the same parent. LDB requires
pasthrough clock to avoid breaking timing while IPU DI does not.
Force IPU DI clocks to use IMX6QDL_CLK_PLL2_PFD0_352M as parent
and LDB to use IMX6QDL_CLK_PLL5_VIDEO_DIV.
This fixes an issue where attempting atomic modeset while using
HDMI and display port at the same time causes LDB clock programming
to destroy the programming of HDMI that was done during the same
modeset.
Cc: stable@vger.kernel.org
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
[Use IMX6QDL_CLK_PLL2_PFD0_352M instead of IMX6QDL_CLK_PLL2_PFD2_396M
originally chosen by Robert Beckett to avoid affecting eMMC clock
by DRM atomic updates]
Signed-off-by: Ian Ray <ian.ray@ge.com>
[Squash Robert's and Ian's commits for bisectability, update patch
description and add stable tag]
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
arch/arm/boot/dts/imx6q-b450v3.dts | 7 -------
arch/arm/boot/dts/imx6q-b650v3.dts | 7 -------
arch/arm/boot/dts/imx6q-b850v3.dts | 11 -----------
arch/arm/boot/dts/imx6q-bx50v3.dtsi | 15 +++++++++++++++
4 files changed, 15 insertions(+), 25 deletions(-)
diff --git a/arch/arm/boot/dts/imx6q-b450v3.dts b/arch/arm/boot/dts/imx6q-b450v3.dts
index 95b8f2d71821..fb0980190aa0 100644
--- a/arch/arm/boot/dts/imx6q-b450v3.dts
+++ b/arch/arm/boot/dts/imx6q-b450v3.dts
@@ -65,13 +65,6 @@ panel_in_lvds0: endpoint {
};
};
-&clks {
- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
- <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
- <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
-};
-
&ldb {
status = "okay";
diff --git a/arch/arm/boot/dts/imx6q-b650v3.dts b/arch/arm/boot/dts/imx6q-b650v3.dts
index 611cb7ae7e55..8f762d9c5ae9 100644
--- a/arch/arm/boot/dts/imx6q-b650v3.dts
+++ b/arch/arm/boot/dts/imx6q-b650v3.dts
@@ -65,13 +65,6 @@ panel_in_lvds0: endpoint {
};
};
-&clks {
- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
- <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
- <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
-};
-
&ldb {
status = "okay";
diff --git a/arch/arm/boot/dts/imx6q-b850v3.dts b/arch/arm/boot/dts/imx6q-b850v3.dts
index e4cb118f88c6..1ea64ecf4291 100644
--- a/arch/arm/boot/dts/imx6q-b850v3.dts
+++ b/arch/arm/boot/dts/imx6q-b850v3.dts
@@ -53,17 +53,6 @@ chosen {
};
};
-&clks {
- assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
- <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
- <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
- <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
- assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
- <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
- <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
- <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
-};
-
&ldb {
fsl,dual-channel;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
index fa27dcdf06f1..1938b04199c4 100644
--- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi
+++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
@@ -377,3 +377,18 @@ pci_root: root@0,0 {
#interrupt-cells = <1>;
};
};
+
+&clks {
+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
+ <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
+ <&clks IMX6QDL_CLK_IPU1_DI1_PRE_SEL>,
+ <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>,
+ <&clks IMX6QDL_CLK_IPU2_DI1_PRE_SEL>;
+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+ <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
+ <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
+ <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
+ <&clks IMX6QDL_CLK_PLL2_PFD0_352M>,
+ <&clks IMX6QDL_CLK_PLL2_PFD0_352M>;
+};
--
2.26.2
^ permalink raw reply related
* [PATCH] arm64: dts: qcom: msm8916-samsung-a3u: add nodes for display panel
From: michael.srba @ 2020-05-14 17:01 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson
Cc: Rob Herring, linux-arm-msm, devicetree, linux-kernel,
~postmarketos/upstreaming, Michael Srba
From: Michael Srba <michael.srba@seznam.cz>
This patch wires up display support on Samsung Galaxy A3 2015.
Signed-off-by: Michael Srba <michael.srba@seznam.cz>
---
.../qcom/msm8916-samsung-a2015-common.dtsi | 44 +++++++++++++++
.../boot/dts/qcom/msm8916-samsung-a3u-eur.dts | 54 +++++++++++++++++++
2 files changed, 98 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
index af812f76e8be..2a64aa269f52 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
@@ -72,6 +72,24 @@ phy {
};
};
+ mdss@1a00000 {
+ dsi@1a98000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdda-supply = <&pm8916_l2>;
+ vddio-supply = <&pm8916_l6>;
+
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&mdss_default>;
+ pinctrl-1 = <&mdss_sleep>;
+ };
+
+ dsi-phy@1a98300 {
+ vddio-supply = <&pm8916_l6>;
+ };
+ };
+
wcnss@a21b000 {
status = "okay";
};
@@ -172,6 +190,32 @@ pinconf {
bias-disable;
};
};
+
+ pmx-mdss {
+ mdss_default: mdss-default {
+ pinmux {
+ function = "gpio";
+ pins = "gpio25";
+ };
+ pinconf {
+ pins = "gpio25";
+ drive-strength = <8>;
+ bias-disable;
+ };
+ };
+
+ mdss_sleep: mdss-sleep {
+ pinmux {
+ function = "gpio";
+ pins = "gpio25";
+ };
+ pinconf {
+ pins = "gpio25";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+ };
};
&smd_rpm_regulators {
diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts
index d10f7ac5089f..b46c87289033 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts
+++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts
@@ -7,4 +7,58 @@
/ {
model = "Samsung Galaxy A3U (EUR)";
compatible = "samsung,a3u-eur", "qcom,msm8916";
+
+ reg_panel_vdd3: regulator-panel-vdd3 {
+ compatible = "regulator-fixed";
+ regulator-name = "panel_vdd3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ gpio = <&msmgpio 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&panel_vdd3_default>;
+ };
+};
+
+&dsi0 {
+ panel@0 {
+ reg = <0>;
+
+ compatible = "samsung,s6e88a0-ams452ef01";
+
+ vdd3-supply = <®_panel_vdd3>;
+ vci-supply = <&pm8916_l17>;
+ reset-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ };
+
+ ports {
+ port@1 {
+ dsi0_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ data-lanes = <0 1>;
+ };
+ };
+ };
+};
+
+&msmgpio {
+ panel_vdd3_default: panel-vdd3-default {
+ pinmux {
+ function = "gpio";
+ pins = "gpio9";
+ };
+ pinconf {
+ pins = "gpio9";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
};
--
2.24.0
^ permalink raw reply related
* Re: [PATCH v3 1/3] ASoC: tlv320adcx140: Add controls for PDM clk
From: Mark Brown @ 2020-05-14 17:05 UTC (permalink / raw)
To: lgirdwood, tiwai, Dan Murphy, perex; +Cc: devicetree, linux-kernel, alsa-devel
In-Reply-To: <20200514123338.20392-1-dmurphy@ti.com>
On Thu, 14 May 2020 07:33:36 -0500, Dan Murphy wrote:
> Add ALSA controls to configure the PDM clocks.
> The clocks need to be configurable to accommodate various microphones
> that use clocks for low power/low resolution modes to high power/high
> resolution modes.
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-5.8
Thanks!
[1/3] ASoC: tlv320adcx140: Add controls for PDM clk
commit: 7cfa610205d95357f9eface292dc70fce7571f65
[2/3] ASoC: tlv320adcx140: Add device tree property for PDM edges
commit: 75b0adbb0806a141b0b5f074cd6bd58bb9870c0d
[3/3] ASoC: tlv320adcx140: Configure PDM sampling edge
commit: 79fc48e41e39d7a98c5f8ae37f613d7ff9953c86
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
^ permalink raw reply
* [PATCH] of/platform: Avoid compilation warning
From: Miquel Raynal @ 2020-05-14 17:07 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, devicetree
Cc: Thomas Petazzoni, linux-kernel, Miquel Raynal
The of_find_device_by_node() helper has its dummy counterpart for when
CONFIG_OF is not enabled. However, it is clearly stated in the kernel
documentation that it "takes a reference to the embedded struct device
which needs to be dropped after use". Which means the of_dev_put()
helper might have to be called afterwards. Unfortunately, there is no
of_dev_put() dummy function if OF_CONFIG is not enabled which seems
odd in this case. The of_dev_put() helper is pretty simple, it just
checks the validity of the single argument and calls put_device() on
it. One can just call put_device() directly to avoid any build issue
but I find much more accurate in this case to create the dummy
helper.
With this helper, a file using of_find_device_by_node() can also call
of_dev_put() without triggering the following:
error: implicit declaration of function ‘of_dev_put’; did you mean ‘of_node_put’? [-Werror=implicit-function-declaration]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
include/linux/of_platform.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/of_platform.h b/include/linux/of_platform.h
index 84a966623e78..84d9e60e517e 100644
--- a/include/linux/of_platform.h
+++ b/include/linux/of_platform.h
@@ -54,11 +54,13 @@ extern struct platform_device *of_device_alloc(struct device_node *np,
struct device *parent);
#ifdef CONFIG_OF
extern struct platform_device *of_find_device_by_node(struct device_node *np);
+extern void of_dev_put(struct platform_device *dev);
#else
static inline struct platform_device *of_find_device_by_node(struct device_node *np)
{
return NULL;
}
+static inline void of_dev_put(struct platform_device *dev) { }
#endif
/* Platform devices and busses creation */
--
2.20.1
^ permalink raw reply related
* Re: [PATCH 3/4] hwspinlock: qcom: Allow mmio usage in addition to syscon
From: Bjorn Andersson @ 2020-05-14 17:06 UTC (permalink / raw)
To: Baolin Wang
Cc: Andy Gross, Ohad Ben-Cohen, Rob Herring, linux-arm-msm,
linux-remoteproc, Devicetree List, LKML
In-Reply-To: <CADBw62oF=o4xxar8yO+xwhLa3h2oD_GD_tWhFo1DDTJGgFnEjg@mail.gmail.com>
On Tue 12 May 20:57 PDT 2020, Baolin Wang wrote:
> On Wed, May 13, 2020 at 8:55 AM Bjorn Andersson
> <bjorn.andersson@linaro.org> wrote:
> >
> > In all modern Qualcomm platforms the mutex region of the TCSR is forked
> > off into its own block, all with a offset of 0 and stride of 4096. So
> > add support for directly memory mapping this register space, to avoid
> > the need to represent this block using a syscon.
> >
> > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > ---
> > drivers/hwspinlock/qcom_hwspinlock.c | 72 +++++++++++++++++++++-------
> > 1 file changed, 56 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/hwspinlock/qcom_hwspinlock.c b/drivers/hwspinlock/qcom_hwspinlock.c
[..]
> > +static struct regmap *qcom_hwspinlock_probe_mmio(struct platform_device *pdev,
> > + u32 *offset, u32 *stride)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct resource *res;
> > + void __iomem *base;
> > +
> > + /* All modern platform has offset 0 and stride of 4k */
> > + *offset = 0;
> > + *stride = 0x1000;
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + base = devm_ioremap_resource(&pdev->dev, res);
>
> I think you can use devm_platform_ioremap_resource(pdev, 0) to
> simplify your code, otherwise looks good to me.
You're right, I better fix this before someone with Coccinelle get the
chance ;)
> Reviewed-by: Baolin Wang <baolin.wang7@gmail.com>
>
Thanks,
Bjorn
^ permalink raw reply
* Re: [PATCH v2 0/4] clk: qcom: gdsc: Handle supply regulators
From: Vinod Koul @ 2020-05-14 17:11 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, Michael Turquette, Stephen Boyd, Rob Herring,
linux-arm-msm, linux-clk, devicetree, linux-kernel
In-Reply-To: <20200417070044.1376212-1-bjorn.andersson@linaro.org>
On 17-04-20, 00:00, Bjorn Andersson wrote:
> Handle supply regulators for GDSCs to allow probe deferral when regulators are
> not yet present/enabled and to allow the GDSC to enable/disable dependencies as
> needed.
Reviewed-by: Vinod Koul <vkoul@kernel.org>
--
~Vinod
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: c630: Specify UFS device reset
From: Vinod Koul @ 2020-05-14 17:12 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, Rob Herring, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20200406060049.227029-1-bjorn.andersson@linaro.org>
On 05-04-20, 23:00, Bjorn Andersson wrote:
> On some device the reset line for the UFS memory needs to be tickled in
> order for UFS to initialize properly, add this to the ufs_mem_hc node.
Reviewed-by: Vinod Koul <vkoul@kernel.org>
--
~Vinod
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: c630: Specify UFS device reset
From: Vinod Koul @ 2020-05-14 17:13 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, Rob Herring, linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <20200406060049.227029-1-bjorn.andersson@linaro.org>
On 05-04-20, 23:00, Bjorn Andersson wrote:
> On some device the reset line for the UFS memory needs to be tickled in
> order for UFS to initialize properly, add this to the ufs_mem_hc node.
Reviewed-by: Vinod Koul <vkoul@kernel.org>
--
~Vinod
^ permalink raw reply
* Re: [PATCH v7 2/4] usb: dwc3: qcom: Add interconnect support in dwc3 driver
From: Matthias Kaehlcke @ 2020-05-14 17:13 UTC (permalink / raw)
To: Felipe Balbi
Cc: Sandeep Maheswaram, Andy Gross, Bjorn Andersson,
Greg Kroah-Hartman, Rob Herring, Mark Rutland, Stephen Boyd,
Doug Anderson, linux-arm-msm, linux-usb, devicetree, linux-kernel,
Manu Gautam, Chandana Kishori Chiluveru, Viresh Kumar,
Georgi Djakov
In-Reply-To: <875zcy4uuj.fsf@kernel.org>
On Thu, May 14, 2020 at 02:30:28PM +0300, Felipe Balbi wrote:
> Felipe Balbi <balbi@kernel.org> writes:
>
> > Hi,
> >
> > Sandeep Maheswaram <sanm@codeaurora.org> writes:
> >> +static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom)
> >> +{
> >> + struct device *dev = qcom->dev;
> >> + int ret;
> >> +
> >> + if (!device_is_bound(&qcom->dwc3->dev))
> >> + return -EPROBE_DEFER;
> >
> > this breaks allmodconfig. I'm dropping this series from my queue for
> > this merge window.
>
> Sorry, I meant this patch ;-)
I guess that's due to INTERCONNECT being a module. There is currently a
discussion about this with Viresh and Georgi in response to another
automated build failure. Viresh suggests changing CONFIG_INTERCONNECT
from tristate to bool, which seems sensible to me given that interconnect
is a core subsystem.
Let's hold back with this patch/series then until that is sorted out.
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: c630: Add WiFi node
From: Vinod Koul @ 2020-05-14 17:14 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, Rob Herring, Mark Rutland, linux-arm-msm, devicetree,
linux-kernel
In-Reply-To: <20191018055841.3729591-1-bjorn.andersson@linaro.org>
On 17-10-19, 22:58, Bjorn Andersson wrote:
> Specify regulators and enable the &wifi node. The firmware uses the 8
> bit version of the host capability message, so specify this quirk.
Reviewed-by: Vinod Koul <vkoul@kernel.org>
--
~Vinod
^ permalink raw reply
* Re: [PATCH v1] arm64: dts: qcom: apq8016-sbc-d3: Add Qualcomm APQ8016 SBC + D3 mezzanine
From: Vinod Koul @ 2020-05-14 17:22 UTC (permalink / raw)
To: Robert Foss
Cc: agross, bjorn.andersson, robh+dt, linux-arm-msm, devicetree,
linux-kernel
In-Reply-To: <20200422111014.616233-1-robert.foss@linaro.org>
On 22-04-20, 13:10, Robert Foss wrote:
> Add device treee support for the Qualcomm APQ8016 SBC, otherwise known as
> the Dragonboard 410c with the D3 mezzanine expansion board.
>
> The D3 mezzanine ships in a kit with a OmniVision 5640 sensor module,
> which is what this DT targets.
>
> Signed-off-by: Robert Foss <robert.foss@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/apq8016-sbc-d3.dts | 45 +++++++++++++++++++++
> 2 files changed, 46 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc-d3.dts
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index cc103f7020fd..025362471929 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc-d3.dtb
> dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
> dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
> dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
> diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-d3.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc-d3.dts
> new file mode 100644
> index 000000000000..1b85adeeada1
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-d3.dts
> @@ -0,0 +1,45 @@
> +// SPDX-License-Identifier: GPL-2.0-only
Dual BSD + GPL please
> +/*
> + * Copyright (c) 2015, The Linux Foundation. All rights reserved.
we are in 2020 now :)
> + */
> +
> +/dts-v1/;
> +
> +#include "apq8016-sbc.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. APQ 8016 SBC w/ D3 Mezzanine";
> + compatible = "qcom,apq8016-sbc", "qcom,apq8016", "qcom,sbc";
> +};
> +
> +&cci_i2c0 {
> + /delete-node/ camera_rear@3b;
> +
> + camera_rear@76 {
> + compatible = "ovti,ov5640";
> + reg = <0x76>;
> +
> + enable-gpios = <&msmgpio 34 GPIO_ACTIVE_HIGH>;
> + reset-gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&camera_rear_default>;
> +
> + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>;
> + clock-names = "xclk";
> + clock-frequency = <23880000>;
> +
> + vdddo-supply = <&camera_vdddo_1v8>;
> + vdda-supply = <&camera_vdda_2v8>;
> + vddd-supply = <&camera_vddd_1v5>;
> +
> + status = "ok";
> +
> + port {
> + ov5640_ep: endpoint {
> + clock-lanes = <1>;
> + data-lanes = <0 2>;
> + remote-endpoint = <&csiphy0_ep>;
> + };
> + };
> + };
> +};
> --
> 2.25.1
--
~Vinod
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: msm8916-samsung-a3u: add nodes for display panel
From: Bjorn Andersson @ 2020-05-14 17:23 UTC (permalink / raw)
To: michael.srba
Cc: Andy Gross, Rob Herring, linux-arm-msm, devicetree, linux-kernel,
~postmarketos/upstreaming
In-Reply-To: <20200514170129.10902-1-michael.srba@seznam.cz>
On Thu 14 May 10:01 PDT 2020, michael.srba@seznam.cz wrote:
> From: Michael Srba <michael.srba@seznam.cz>
>
> This patch wires up display support on Samsung Galaxy A3 2015.
>
> Signed-off-by: Michael Srba <michael.srba@seznam.cz>
>
> ---
> .../qcom/msm8916-samsung-a2015-common.dtsi | 44 +++++++++++++++
> .../boot/dts/qcom/msm8916-samsung-a3u-eur.dts | 54 +++++++++++++++++++
> 2 files changed, 98 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
> index af812f76e8be..2a64aa269f52 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
> @@ -72,6 +72,24 @@ phy {
> };
> };
>
> + mdss@1a00000 {
> + dsi@1a98000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + vdda-supply = <&pm8916_l2>;
> + vddio-supply = <&pm8916_l6>;
> +
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&mdss_default>;
> + pinctrl-1 = <&mdss_sleep>;
> + };
> +
> + dsi-phy@1a98300 {
> + vddio-supply = <&pm8916_l6>;
> + };
> + };
> +
> wcnss@a21b000 {
> status = "okay";
> };
> @@ -172,6 +190,32 @@ pinconf {
> bias-disable;
> };
> };
> +
> + pmx-mdss {
> + mdss_default: mdss-default {
> + pinmux {
> + function = "gpio";
> + pins = "gpio25";
> + };
> + pinconf {
> + pins = "gpio25";
> + drive-strength = <8>;
> + bias-disable;
> + };
> + };
Fyi, when you have a state with a single set of properties you don't
need the pinmux/pinconf level here, you can directly do:
mdss_default: mdss-default {
pins = "gpio25";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
But this looks good, applied towards v5.8.
Regards,
Bjorn
^ permalink raw reply
* Re: [PATCHv8 0/6] n_gsm serdev support and GNSS driver for droid4
From: Tony Lindgren @ 2020-05-14 17:31 UTC (permalink / raw)
To: Pavel Machek
Cc: Greg Kroah-Hartman, Johan Hovold, Rob Herring, Lee Jones,
Jiri Slaby, Merlijn Wajer, Peter Hurley, Sebastian Reichel,
linux-serial, devicetree, linux-kernel, linux-omap
In-Reply-To: <20200513190942.GA2626@duo.ucw.cz>
* Pavel Machek <pavel@denx.de> [200513 19:10]:
> Hi!
>
> > Here's the updated set of these patches fixed up for Johan's and
> > Pavel's earlier comments.
> >
> > This series does the following:
> >
> > 1. Adds functions to n_gsm.c for serdev-ngsm.c driver to use
> >
> > 2. Adds a generic serdev-ngsm.c driver that brings up the TS 27.010
> > TTY ports configured in devicetree with help of n_gsm.c
> >
> > 3. Allows the use of standard Linux device drivers for dedicated
> > TS 27.010 channels for devices like GNSS and ALSA found on some
> > modems for example
>
> > 4. Adds a gnss-motmdm consumer driver for the GNSS device found on
> > the Motorola Mapphone MDM6600 modem on devices like droid4
>
> It does one thing ... it turns Droid 4 into useful phone!
Right, a minor detail I forgot :)
> Thanks a lot. I believe these are same patches as in
> droid4-pending-v5.7 branch, so whole series is
>
> Tested-by: Pavel Machek <pavel@ucw.cz>
>
> Getting this into 5.8 would be nice :-).
>
> > Now without the chardev support, the /dev/gsmtty* using apps need
> > to use "U1234AT+CFUN?" format for the packets. The advantage is
> > less kernel code, and we keep the existing /dev/gsmtty* interface.
> >
> > If we still really need the custom chardev support, that can now
> > be added as needed with the channel specific consumer driver(s),
> > but looks like this won't be needed based on Pavel's ofono work.
>
> These work for me, and I have patched ofono with basic
> functionality. It is no longer possible to use minicom for debugging,
> but printf can be used instead, so that's not much of a problem.
>
> I have adjusted ofono code, and moved away from normal AT support
> code. More API changes would not be welcome :-).
There is no need for a new API or API changes as we now use the
existing n_gsm tty interface for /dev/gsmtty* devices that have
been around for years.
Regards,
Tony
^ permalink raw reply
* Re: [PATCH 3/4] hwspinlock: qcom: Allow mmio usage in addition to syscon
From: Vinod Koul @ 2020-05-14 17:32 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, Ohad Ben-Cohen, Baolin Wang, Rob Herring,
linux-arm-msm, linux-remoteproc, devicetree, linux-kernel
In-Reply-To: <20200514170013.GX2165@builder.lan>
On 14-05-20, 10:00, Bjorn Andersson wrote:
> On Thu 14 May 07:15 PDT 2020, Vinod Koul wrote:
>
> > On 12-05-20, 17:54, Bjorn Andersson wrote:
> > > In all modern Qualcomm platforms the mutex region of the TCSR is forked
> > > off into its own block, all with a offset of 0 and stride of 4096. So
> > > add support for directly memory mapping this register space, to avoid
> > > the need to represent this block using a syscon.
> > >
> > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > > ---
> > > drivers/hwspinlock/qcom_hwspinlock.c | 72 +++++++++++++++++++++-------
> > > 1 file changed, 56 insertions(+), 16 deletions(-)
> > >
> > > diff --git a/drivers/hwspinlock/qcom_hwspinlock.c b/drivers/hwspinlock/qcom_hwspinlock.c
> > > index f0da544b14d2..d8d4d729816c 100644
> > > --- a/drivers/hwspinlock/qcom_hwspinlock.c
> > > +++ b/drivers/hwspinlock/qcom_hwspinlock.c
> > > @@ -70,41 +70,81 @@ static const struct of_device_id qcom_hwspinlock_of_match[] = {
> > > };
> > > MODULE_DEVICE_TABLE(of, qcom_hwspinlock_of_match);
> > >
> > > -static int qcom_hwspinlock_probe(struct platform_device *pdev)
> > > +static struct regmap *qcom_hwspinlock_probe_syscon(struct platform_device *pdev,
> > > + u32 *base, u32 *stride)
> > > {
> > > - struct hwspinlock_device *bank;
> > > struct device_node *syscon;
> > > - struct reg_field field;
> > > struct regmap *regmap;
> > > - size_t array_size;
> > > - u32 stride;
> > > - u32 base;
> > > int ret;
> > > - int i;
> > >
> > > syscon = of_parse_phandle(pdev->dev.of_node, "syscon", 0);
> > > - if (!syscon) {
> > > - dev_err(&pdev->dev, "no syscon property\n");
> >
> > any reason to drop the log?
> >
>
> Given that we first check for the syscon and then fall back to trying to
> use the reg, keeping this line would cause this log line to always show
> up on targets putting this under /soc.
>
> So I think it's better to drop the line and then require the presence of
> either syscon or reg using the DT schema.
ok
> > > - return -ENODEV;
> > > - }
> > > + if (!syscon)
> > > + return ERR_PTR(-ENODEV);
> > >
> > > regmap = syscon_node_to_regmap(syscon);
> > > of_node_put(syscon);
> > > if (IS_ERR(regmap))
> > > - return PTR_ERR(regmap);
> > > + return regmap;
> > >
> > > - ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, &base);
> > > + ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1, base);
> > > if (ret < 0) {
> > > dev_err(&pdev->dev, "no offset in syscon\n");
> > > - return -EINVAL;
> > > + return ERR_PTR(-EINVAL);
> > > }
> > >
> > > - ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 2, &stride);
> > > + ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 2, stride);
> > > if (ret < 0) {
> > > dev_err(&pdev->dev, "no stride syscon\n");
> > > - return -EINVAL;
> > > + return ERR_PTR(-EINVAL);
> > > }
> > >
> > > + return regmap;
> > > +}
> > > +
> > > +static const struct regmap_config tcsr_mutex_config = {
> > > + .reg_bits = 32,
> > > + .reg_stride = 4,
> > > + .val_bits = 32,
> > > + .max_register = 0x40000,
> > > + .fast_io = true,
> > > +};
> > > +
> > > +static struct regmap *qcom_hwspinlock_probe_mmio(struct platform_device *pdev,
> > > + u32 *offset, u32 *stride)
> > > +{
> > > + struct device *dev = &pdev->dev;
> > > + struct resource *res;
> > > + void __iomem *base;
> > > +
> > > + /* All modern platform has offset 0 and stride of 4k */
> > > + *offset = 0;
> > > + *stride = 0x1000;
> >
> > Wouldn't it make sense to read this from DT rather than code in kernel?
> >
>
> I did consider this as well as platform specific compatibles, but
> realized that pretty much all 64-bit targets have these values. So given
> that we still can represent this using the syscon approach I don't think
> we need to add yet another mechanism to specify these.
Sounds good.
Reviewed-by: Vinod Koul <vkoul@kernel.org>
--
~Vinod
^ permalink raw reply
* Re: [PATCH 1/3] arm64: dts: qcom: msm8916: avoid using _ in node names
From: Bjorn Andersson @ 2020-05-14 17:31 UTC (permalink / raw)
To: Stephan Gerhold
Cc: Andy Gross, linux-arm-msm, devicetree, ~postmarketos/upstreaming
In-Reply-To: <20200514112754.148919-1-stephan@gerhold.net>
On Thu 14 May 04:27 PDT 2020, Stephan Gerhold wrote:
> Many nodes in the MSM8916 device trees use '_' in node names
> (especially pinctrl), even though (seemingly) '-' is preferred now.
> Make this more consistent by replacing '_' with '-' where possible.
>
> Similar naming is used for pinctrl in newer device trees (e.g. sdm845.dtsi).
>
> Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Looks good, series applied for v5.8.
Thanks,
Bjorn
> ---
> See also: https://lore.kernel.org/linux-arm-msm/20200512182959.GJ57962@builder.lan/
> ---
> .../boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi | 14 +-
> .../boot/dts/qcom/apq8016-sbc-soc-pins.dtsi | 12 +-
> arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 8 +-
> .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 2 +-
> arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 181 +++++++++---------
> .../qcom/msm8916-samsung-a2015-common.dtsi | 6 +-
> arch/arm64/boot/dts/qcom/msm8916.dtsi | 10 +-
> 7 files changed, 116 insertions(+), 117 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
> index aff218c1b7b6..41907938014c 100644
> --- a/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
> +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-pmic-pins.dtsi
> @@ -4,7 +4,7 @@
>
> &pm8916_gpios {
>
> - usb_hub_reset_pm: usb_hub_reset_pm {
> + usb_hub_reset_pm: usb-hub-reset-pm {
> pinconf {
> pins = "gpio3";
> function = PMIC_GPIO_FUNC_NORMAL;
> @@ -13,7 +13,7 @@ pinconf {
> };
> };
>
> - usb_hub_reset_pm_device: usb_hub_reset_pm_device {
> + usb_hub_reset_pm_device: usb-hub-reset-pm-device {
> pinconf {
> pins = "gpio3";
> function = PMIC_GPIO_FUNC_NORMAL;
> @@ -21,7 +21,7 @@ pinconf {
> };
> };
>
> - usb_sw_sel_pm: usb_sw_sel_pm {
> + usb_sw_sel_pm: usb-sw-sel-pm {
> pinconf {
> pins = "gpio4";
> function = PMIC_GPIO_FUNC_NORMAL;
> @@ -31,7 +31,7 @@ pinconf {
> };
> };
>
> - usb_sw_sel_pm_device: usb_sw_sel_pm_device {
> + usb_sw_sel_pm_device: usb-sw-sel-pm-device {
> pinconf {
> pins = "gpio4";
> function = PMIC_GPIO_FUNC_NORMAL;
> @@ -41,7 +41,7 @@ pinconf {
> };
> };
>
> - pm8916_gpios_leds: pm8916_gpios_leds {
> + pm8916_gpios_leds: pm8916-gpios-leds {
> pinconf {
> pins = "gpio1", "gpio2";
> function = PMIC_GPIO_FUNC_NORMAL;
> @@ -55,7 +55,7 @@ &pm8916_mpps {
> pinctrl-names = "default";
> pinctrl-0 = <&ls_exp_gpio_f>;
>
> - ls_exp_gpio_f: pm8916_mpp4 {
> + ls_exp_gpio_f: pm8916-mpp4 {
> pinconf {
> pins = "mpp4";
> function = "digital";
> @@ -64,7 +64,7 @@ pinconf {
> };
> };
>
> - pm8916_mpps_leds: pm8916_mpps_leds {
> + pm8916_mpps_leds: pm8916-mpps-leds {
> pinconf {
> pins = "mpp2", "mpp3";
> function = "digital";
> diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
> index 21d0822f1ca6..ac00beec102f 100644
> --- a/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
> +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-soc-pins.dtsi
> @@ -4,7 +4,7 @@
>
> &msmgpio {
>
> - msmgpio_leds: msmgpio_leds {
> + msmgpio_leds: msmgpio-leds {
> pinconf {
> pins = "gpio21", "gpio120";
> function = "gpio";
> @@ -26,7 +26,7 @@ pinconf {
> };
> };
>
> - adv7533_int_active: adv533_int_active {
> + adv7533_int_active: adv533-int-active {
> pinmux {
> function = "gpio";
> pins = "gpio31";
> @@ -38,7 +38,7 @@ pinconf {
> };
> };
>
> - adv7533_int_suspend: adv7533_int_suspend {
> + adv7533_int_suspend: adv7533-int-suspend {
> pinmux {
> function = "gpio";
> pins = "gpio31";
> @@ -50,7 +50,7 @@ pinconf {
> };
> };
>
> - adv7533_switch_active: adv7533_switch_active {
> + adv7533_switch_active: adv7533-switch-active {
> pinmux {
> function = "gpio";
> pins = "gpio32";
> @@ -62,7 +62,7 @@ pinconf {
> };
> };
>
> - adv7533_switch_suspend: adv7533_switch_suspend {
> + adv7533_switch_suspend: adv7533-switch-suspend {
> pinmux {
> function = "gpio";
> pins = "gpio32";
> @@ -74,7 +74,7 @@ pinconf {
> };
> };
>
> - msm_key_volp_n_default: msm_key_volp_n_default {
> + msm_key_volp_n_default: msm-key-volp-n-default {
> pinmux {
> function = "gpio";
> pins = "gpio107";
> diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
> index 7377bf73390a..08c7538b9c9f 100644
> --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
> +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
> @@ -51,7 +51,7 @@ chosen {
> stdout-path = "serial0";
> };
>
> - camera_vdddo_1v8: camera_vdddo_1v8 {
> + camera_vdddo_1v8: camera-vdddo-1v8 {
> compatible = "regulator-fixed";
> regulator-name = "camera_vdddo";
> regulator-min-microvolt = <1800000>;
> @@ -59,7 +59,7 @@ camera_vdddo_1v8: camera_vdddo_1v8 {
> regulator-always-on;
> };
>
> - camera_vdda_2v8: camera_vdda_2v8 {
> + camera_vdda_2v8: camera-vdda-2v8 {
> compatible = "regulator-fixed";
> regulator-name = "camera_vdda";
> regulator-min-microvolt = <2800000>;
> @@ -67,7 +67,7 @@ camera_vdda_2v8: camera_vdda_2v8 {
> regulator-always-on;
> };
>
> - camera_vddd_1v5: camera_vddd_1v5 {
> + camera_vddd_1v5: camera-vddd-1v5 {
> compatible = "regulator-fixed";
> regulator-name = "camera_vddd";
> regulator-min-microvolt = <1500000>;
> @@ -566,7 +566,7 @@ hdmi_con: endpoint {
> };
> };
>
> - gpio_keys {
> + gpio-keys {
> compatible = "gpio-keys";
> #address-cells = <1>;
> #size-cells = <0>;
> diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts
> index 691eb1a87bc9..d5230cb76eb1 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts
> +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts
> @@ -109,7 +109,7 @@ volume-up {
> };
>
> &msmgpio {
> - gpio_keys_default: gpio_keys_default {
> + gpio_keys_default: gpio-keys-default {
> pinmux {
> function = "gpio";
> pins = "gpio107";
> diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
> index 31886860766a..e9c00367f7fd 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
> @@ -5,7 +5,7 @@
>
> &msmgpio {
>
> - blsp1_uart1_default: blsp1_uart1_default {
> + blsp1_uart1_default: blsp1-uart1-default {
> pinmux {
> function = "blsp_uart1";
> // TX, RX, CTS_N, RTS_N
> @@ -20,7 +20,7 @@ pinconf {
> };
> };
>
> - blsp1_uart1_sleep: blsp1_uart1_sleep {
> + blsp1_uart1_sleep: blsp1-uart1-sleep {
> pinmux {
> function = "gpio";
> pins = "gpio0", "gpio1",
> @@ -34,7 +34,7 @@ pinconf {
> };
> };
>
> - blsp1_uart2_default: blsp1_uart2_default {
> + blsp1_uart2_default: blsp1-uart2-default {
> pinmux {
> function = "blsp_uart2";
> pins = "gpio4", "gpio5";
> @@ -46,7 +46,7 @@ pinconf {
> };
> };
>
> - blsp1_uart2_sleep: blsp1_uart2_sleep {
> + blsp1_uart2_sleep: blsp1-uart2-sleep {
> pinmux {
> function = "gpio";
> pins = "gpio4", "gpio5";
> @@ -58,12 +58,12 @@ pinconf {
> };
> };
>
> - spi1_default: spi1_default {
> + spi1_default: spi1-default {
> pinmux {
> function = "blsp_spi1";
> pins = "gpio0", "gpio1", "gpio3";
> };
> - pinmux_cs {
> + pinmux-cs {
> function = "gpio";
> pins = "gpio2";
> };
> @@ -72,7 +72,7 @@ pinconf {
> drive-strength = <12>;
> bias-disable;
> };
> - pinconf_cs {
> + pinconf-cs {
> pins = "gpio2";
> drive-strength = <16>;
> bias-disable;
> @@ -80,7 +80,7 @@ pinconf_cs {
> };
> };
>
> - spi1_sleep: spi1_sleep {
> + spi1_sleep: spi1-sleep {
> pinmux {
> function = "gpio";
> pins = "gpio0", "gpio1", "gpio2", "gpio3";
> @@ -92,12 +92,12 @@ pinconf {
> };
> };
>
> - spi2_default: spi2_default {
> + spi2_default: spi2-default {
> pinmux {
> function = "blsp_spi2";
> pins = "gpio4", "gpio5", "gpio7";
> };
> - pinmux_cs {
> + pinmux-cs {
> function = "gpio";
> pins = "gpio6";
> };
> @@ -106,7 +106,7 @@ pinconf {
> drive-strength = <12>;
> bias-disable;
> };
> - pinconf_cs {
> + pinconf-cs {
> pins = "gpio6";
> drive-strength = <16>;
> bias-disable;
> @@ -114,7 +114,7 @@ pinconf_cs {
> };
> };
>
> - spi2_sleep: spi2_sleep {
> + spi2_sleep: spi2-sleep {
> pinmux {
> function = "gpio";
> pins = "gpio4", "gpio5", "gpio6", "gpio7";
> @@ -126,12 +126,12 @@ pinconf {
> };
> };
>
> - spi3_default: spi3_default {
> + spi3_default: spi3-default {
> pinmux {
> function = "blsp_spi3";
> pins = "gpio8", "gpio9", "gpio11";
> };
> - pinmux_cs {
> + pinmux-cs {
> function = "gpio";
> pins = "gpio10";
> };
> @@ -140,7 +140,7 @@ pinconf {
> drive-strength = <12>;
> bias-disable;
> };
> - pinconf_cs {
> + pinconf-cs {
> pins = "gpio10";
> drive-strength = <16>;
> bias-disable;
> @@ -148,7 +148,7 @@ pinconf_cs {
> };
> };
>
> - spi3_sleep: spi3_sleep {
> + spi3_sleep: spi3-sleep {
> pinmux {
> function = "gpio";
> pins = "gpio8", "gpio9", "gpio10", "gpio11";
> @@ -160,12 +160,12 @@ pinconf {
> };
> };
>
> - spi4_default: spi4_default {
> + spi4_default: spi4-default {
> pinmux {
> function = "blsp_spi4";
> pins = "gpio12", "gpio13", "gpio15";
> };
> - pinmux_cs {
> + pinmux-cs {
> function = "gpio";
> pins = "gpio14";
> };
> @@ -174,7 +174,7 @@ pinconf {
> drive-strength = <12>;
> bias-disable;
> };
> - pinconf_cs {
> + pinconf-cs {
> pins = "gpio14";
> drive-strength = <16>;
> bias-disable;
> @@ -182,7 +182,7 @@ pinconf_cs {
> };
> };
>
> - spi4_sleep: spi4_sleep {
> + spi4_sleep: spi4-sleep {
> pinmux {
> function = "gpio";
> pins = "gpio12", "gpio13", "gpio14", "gpio15";
> @@ -194,12 +194,12 @@ pinconf {
> };
> };
>
> - spi5_default: spi5_default {
> + spi5_default: spi5-default {
> pinmux {
> function = "blsp_spi5";
> pins = "gpio16", "gpio17", "gpio19";
> };
> - pinmux_cs {
> + pinmux-cs {
> function = "gpio";
> pins = "gpio18";
> };
> @@ -208,7 +208,7 @@ pinconf {
> drive-strength = <12>;
> bias-disable;
> };
> - pinconf_cs {
> + pinconf-cs {
> pins = "gpio18";
> drive-strength = <16>;
> bias-disable;
> @@ -216,7 +216,7 @@ pinconf_cs {
> };
> };
>
> - spi5_sleep: spi5_sleep {
> + spi5_sleep: spi5-sleep {
> pinmux {
> function = "gpio";
> pins = "gpio16", "gpio17", "gpio18", "gpio19";
> @@ -228,12 +228,12 @@ pinconf {
> };
> };
>
> - spi6_default: spi6_default {
> + spi6_default: spi6-default {
> pinmux {
> function = "blsp_spi6";
> pins = "gpio20", "gpio21", "gpio23";
> };
> - pinmux_cs {
> + pinmux-cs {
> function = "gpio";
> pins = "gpio22";
> };
> @@ -242,7 +242,7 @@ pinconf {
> drive-strength = <12>;
> bias-disable;
> };
> - pinconf_cs {
> + pinconf-cs {
> pins = "gpio22";
> drive-strength = <16>;
> bias-disable;
> @@ -250,7 +250,7 @@ pinconf_cs {
> };
> };
>
> - spi6_sleep: spi6_sleep {
> + spi6_sleep: spi6-sleep {
> pinmux {
> function = "gpio";
> pins = "gpio20", "gpio21", "gpio22", "gpio23";
> @@ -262,7 +262,7 @@ pinconf {
> };
> };
>
> - i2c1_default: i2c1_default {
> + i2c1_default: i2c1-default {
> pinmux {
> function = "blsp_i2c1";
> pins = "gpio2", "gpio3";
> @@ -274,7 +274,7 @@ pinconf {
> };
> };
>
> - i2c1_sleep: i2c1_sleep {
> + i2c1_sleep: i2c1-sleep {
> pinmux {
> function = "gpio";
> pins = "gpio2", "gpio3";
> @@ -286,7 +286,7 @@ pinconf {
> };
> };
>
> - i2c2_default: i2c2_default {
> + i2c2_default: i2c2-default {
> pinmux {
> function = "blsp_i2c2";
> pins = "gpio6", "gpio7";
> @@ -298,7 +298,7 @@ pinconf {
> };
> };
>
> - i2c2_sleep: i2c2_sleep {
> + i2c2_sleep: i2c2-sleep {
> pinmux {
> function = "gpio";
> pins = "gpio6", "gpio7";
> @@ -310,7 +310,7 @@ pinconf {
> };
> };
>
> - i2c4_default: i2c4_default {
> + i2c4_default: i2c4-default {
> pinmux {
> function = "blsp_i2c4";
> pins = "gpio14", "gpio15";
> @@ -322,7 +322,7 @@ pinconf {
> };
> };
>
> - i2c4_sleep: i2c4_sleep {
> + i2c4_sleep: i2c4-sleep {
> pinmux {
> function = "gpio";
> pins = "gpio14", "gpio15";
> @@ -334,7 +334,7 @@ pinconf {
> };
> };
>
> - i2c5_default: i2c5_default {
> + i2c5_default: i2c5-default {
> pinmux {
> function = "blsp_i2c5";
> pins = "gpio18", "gpio19";
> @@ -346,7 +346,7 @@ pinconf {
> };
> };
>
> - i2c5_sleep: i2c5_sleep {
> + i2c5_sleep: i2c5-sleep {
> pinmux {
> function = "gpio";
> pins = "gpio18", "gpio19";
> @@ -358,7 +358,7 @@ pinconf {
> };
> };
>
> - i2c6_default: i2c6_default {
> + i2c6_default: i2c6-default {
> pinmux {
> function = "blsp_i2c6";
> pins = "gpio22", "gpio23";
> @@ -370,7 +370,7 @@ pinconf {
> };
> };
>
> - i2c6_sleep: i2c6_sleep {
> + i2c6_sleep: i2c6-sleep {
> pinmux {
> function = "gpio";
> pins = "gpio22", "gpio23";
> @@ -382,8 +382,8 @@ pinconf {
> };
> };
>
> - pmx_sdc1_clk {
> - sdc1_clk_on: clk_on {
> + pmx-sdc1-clk {
> + sdc1_clk_on: clk-on {
> pinmux {
> pins = "sdc1_clk";
> };
> @@ -393,7 +393,7 @@ pinconf {
> drive-strength = <16>;
> };
> };
> - sdc1_clk_off: clk_off {
> + sdc1_clk_off: clk-off {
> pinmux {
> pins = "sdc1_clk";
> };
> @@ -405,8 +405,8 @@ pinconf {
> };
> };
>
> - pmx_sdc1_cmd {
> - sdc1_cmd_on: cmd_on {
> + pmx-sdc1-cmd {
> + sdc1_cmd_on: cmd-on {
> pinmux {
> pins = "sdc1_cmd";
> };
> @@ -416,7 +416,7 @@ pinconf {
> drive-strength = <10>;
> };
> };
> - sdc1_cmd_off: cmd_off {
> + sdc1_cmd_off: cmd-off {
> pinmux {
> pins = "sdc1_cmd";
> };
> @@ -428,8 +428,8 @@ pinconf {
> };
> };
>
> - pmx_sdc1_data {
> - sdc1_data_on: data_on {
> + pmx-sdc1-data {
> + sdc1_data_on: data-on {
> pinmux {
> pins = "sdc1_data";
> };
> @@ -439,7 +439,7 @@ pinconf {
> drive-strength = <10>;
> };
> };
> - sdc1_data_off: data_off {
> + sdc1_data_off: data-off {
> pinmux {
> pins = "sdc1_data";
> };
> @@ -451,8 +451,8 @@ pinconf {
> };
> };
>
> - pmx_sdc2_clk {
> - sdc2_clk_on: clk_on {
> + pmx-sdc2-clk {
> + sdc2_clk_on: clk-on {
> pinmux {
> pins = "sdc2_clk";
> };
> @@ -462,7 +462,7 @@ pinconf {
> drive-strength = <16>;
> };
> };
> - sdc2_clk_off: clk_off {
> + sdc2_clk_off: clk-off {
> pinmux {
> pins = "sdc2_clk";
> };
> @@ -474,8 +474,8 @@ pinconf {
> };
> };
>
> - pmx_sdc2_cmd {
> - sdc2_cmd_on: cmd_on {
> + pmx-sdc2-cmd {
> + sdc2_cmd_on: cmd-on {
> pinmux {
> pins = "sdc2_cmd";
> };
> @@ -485,7 +485,7 @@ pinconf {
> drive-strength = <10>;
> };
> };
> - sdc2_cmd_off: cmd_off {
> + sdc2_cmd_off: cmd-off {
> pinmux {
> pins = "sdc2_cmd";
> };
> @@ -497,8 +497,8 @@ pinconf {
> };
> };
>
> - pmx_sdc2_data {
> - sdc2_data_on: data_on {
> + pmx-sdc2-data {
> + sdc2_data_on: data-on {
> pinmux {
> pins = "sdc2_data";
> };
> @@ -508,7 +508,7 @@ pinconf {
> drive-strength = <10>;
> };
> };
> - sdc2_data_off: data_off {
> + sdc2_data_off: data-off {
> pinmux {
> pins = "sdc2_data";
> };
> @@ -520,8 +520,8 @@ pinconf {
> };
> };
>
> - pmx_sdc2_cd_pin {
> - sdc2_cd_on: cd_on {
> + pmx-sdc2-cd-pin {
> + sdc2_cd_on: cd-on {
> pinmux {
> function = "gpio";
> pins = "gpio38";
> @@ -532,7 +532,7 @@ pinconf {
> bias-pull-up;
> };
> };
> - sdc2_cd_off: cd_off {
> + sdc2_cd_off: cd-off {
> pinmux {
> function = "gpio";
> pins = "gpio38";
> @@ -546,7 +546,7 @@ pinconf {
> };
>
> cdc-pdm-lines {
> - cdc_pdm_lines_act: pdm_lines_on {
> + cdc_pdm_lines_act: pdm-lines-on {
> pinmux {
> function = "cdc_pdm0";
> pins = "gpio63", "gpio64", "gpio65", "gpio66",
> @@ -559,7 +559,7 @@ pinconf {
> bias-pull-none;
> };
> };
> - cdc_pdm_lines_sus: pdm_lines_off {
> + cdc_pdm_lines_sus: pdm-lines-off {
> pinmux {
> function = "cdc_pdm0";
> pins = "gpio63", "gpio64", "gpio65", "gpio66",
> @@ -575,7 +575,7 @@ pinconf {
> };
>
> ext-pri-tlmm-lines {
> - ext_pri_tlmm_lines_act: ext_pa_on {
> + ext_pri_tlmm_lines_act: ext-pa-on {
> pinmux {
> function = "pri_mi2s";
> pins = "gpio113", "gpio114", "gpio115",
> @@ -589,7 +589,7 @@ pinconf {
> };
> };
>
> - ext_pri_tlmm_lines_sus: ext_pa_off {
> + ext_pri_tlmm_lines_sus: ext-pa-off {
> pinmux {
> function = "pri_mi2s";
> pins = "gpio113", "gpio114", "gpio115",
> @@ -605,7 +605,7 @@ pinconf {
> };
>
> ext-pri-ws-line {
> - ext_pri_ws_act: ext_pa_on {
> + ext_pri_ws_act: ext-pa-on {
> pinmux {
> function = "pri_mi2s_ws";
> pins = "gpio110";
> @@ -617,7 +617,7 @@ pinconf {
> };
> };
>
> - ext_pri_ws_sus: ext_pa_off {
> + ext_pri_ws_sus: ext-pa-off {
> pinmux {
> function = "pri_mi2s_ws";
> pins = "gpio110";
> @@ -631,7 +631,7 @@ pinconf {
> };
>
> ext-mclk-tlmm-lines {
> - ext_mclk_tlmm_lines_act: mclk_lines_on {
> + ext_mclk_tlmm_lines_act: mclk-lines-on {
> pinmux {
> function = "pri_mi2s";
> pins = "gpio116";
> @@ -642,7 +642,7 @@ pinconf {
> bias-pull-none;
> };
> };
> - ext_mclk_tlmm_lines_sus: mclk_lines_off {
> + ext_mclk_tlmm_lines_sus: mclk-lines-off {
> pinmux {
> function = "pri_mi2s";
> pins = "gpio116";
> @@ -657,7 +657,7 @@ pinconf {
>
> /* secondary Mi2S */
> ext-sec-tlmm-lines {
> - ext_sec_tlmm_lines_act: tlmm_lines_on {
> + ext_sec_tlmm_lines_act: tlmm-lines-on {
> pinmux {
> function = "sec_mi2s";
> pins = "gpio112", "gpio117", "gpio118",
> @@ -670,7 +670,7 @@ pinconf {
> bias-pull-none;
> };
> };
> - ext_sec_tlmm_lines_sus: tlmm_lines_off {
> + ext_sec_tlmm_lines_sus: tlmm-lines-off {
> pinmux {
> function = "sec_mi2s";
> pins = "gpio112", "gpio117", "gpio118",
> @@ -686,12 +686,12 @@ pinconf {
> };
>
> cdc-dmic-lines {
> - cdc_dmic_lines_act: dmic_lines_on {
> - pinmux_dmic0_clk {
> + cdc_dmic_lines_act: dmic-lines-on {
> + pinmux-dmic0-clk {
> function = "dmic0_clk";
> pins = "gpio0";
> };
> - pinmux_dmic0_data {
> + pinmux-dmic0-data {
> function = "dmic0_data";
> pins = "gpio1";
> };
> @@ -700,12 +700,12 @@ pinconf {
> drive-strength = <8>;
> };
> };
> - cdc_dmic_lines_sus: dmic_lines_off {
> - pinmux_dmic0_clk {
> + cdc_dmic_lines_sus: dmic-lines-off {
> + pinmux-dmic0-clk {
> function = "dmic0_clk";
> pins = "gpio0";
> };
> - pinmux_dmic0_data {
> + pinmux-dmic0-data {
> function = "dmic0_data";
> pins = "gpio1";
> };
> @@ -722,7 +722,6 @@ pinmux {
> pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
> function = "wcss_wlan";
> };
> -
> pinconf {
> pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
> drive-strength = <6>;
> @@ -730,7 +729,7 @@ pinconf {
> };
> };
>
> - cci0_default: cci0_default {
> + cci0_default: cci0-default {
> pinmux {
> function = "cci_i2c";
> pins = "gpio29", "gpio30";
> @@ -742,64 +741,64 @@ pinconf {
> };
> };
>
> - camera_front_default: camera_front_default {
> - pinmux_pwdn {
> + camera_front_default: camera-front-default {
> + pinmux-pwdn {
> function = "gpio";
> pins = "gpio33";
> };
> - pinconf_pwdn {
> + pinconf-pwdn {
> pins = "gpio33";
> drive-strength = <16>;
> bias-disable;
> };
>
> - pinmux_rst {
> + pinmux-rst {
> function = "gpio";
> pins = "gpio28";
> };
> - pinconf_rst {
> + pinconf-rst {
> pins = "gpio28";
> drive-strength = <16>;
> bias-disable;
> };
>
> - pinmux_mclk1 {
> + pinmux-mclk1 {
> function = "cam_mclk1";
> pins = "gpio27";
> };
> - pinconf_mclk1 {
> + pinconf-mclk1 {
> pins = "gpio27";
> drive-strength = <16>;
> bias-disable;
> };
> };
>
> - camera_rear_default: camera_rear_default {
> - pinmux_pwdn {
> + camera_rear_default: camera-rear-default {
> + pinmux-pwdn {
> function = "gpio";
> pins = "gpio34";
> };
> - pinconf_pwdn {
> + pinconf-pwdn {
> pins = "gpio34";
> drive-strength = <16>;
> bias-disable;
> };
>
> - pinmux_rst {
> + pinmux-rst {
> function = "gpio";
> pins = "gpio35";
> };
> - pinconf_rst {
> + pinconf-rst {
> pins = "gpio35";
> drive-strength = <16>;
> bias-disable;
> };
>
> - pinmux_mclk0 {
> + pinmux-mclk0 {
> function = "cam_mclk0";
> pins = "gpio26";
> };
> - pinconf_mclk0 {
> + pinconf-mclk0 {
> pins = "gpio26";
> drive-strength = <16>;
> bias-disable;
> diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
> index 8b5060f4fe0b..6f921e6054e1 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
> @@ -150,7 +150,7 @@ muic: sm5502@25 {
> };
>
> &msmgpio {
> - gpio_keys_default: gpio_keys_default {
> + gpio_keys_default: gpio-keys-default {
> pinmux {
> function = "gpio";
> pins = "gpio107", "gpio109";
> @@ -162,7 +162,7 @@ pinconf {
> };
> };
>
> - gpio_hall_sensor_default: gpio_hall_sensor_default {
> + gpio_hall_sensor_default: gpio-hall-sensor-default {
> pinmux {
> function = "gpio";
> pins = "gpio52";
> @@ -174,7 +174,7 @@ pinconf {
> };
> };
>
> - muic_int_default: muic_int_default {
> + muic_int_default: muic-int-default {
> pinmux {
> function = "gpio";
> pins = "gpio12";
> diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> index cf9ce4a9c912..69129c0b20aa 100644
> --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
> @@ -340,7 +340,7 @@ modem_alert0: trip-point0 {
>
> };
>
> - cpu_opp_table: cpu_opp_table {
> + cpu_opp_table: cpu-opp-table {
> compatible = "operating-points-v2";
> opp-shared;
>
> @@ -358,7 +358,7 @@ opp-998400000 {
> };
> };
>
> - gpu_opp_table: opp_table {
> + gpu_opp_table: gpu-opp-table {
> compatible = "operating-points-v2";
>
> opp-400000000 {
> @@ -378,13 +378,13 @@ timer {
> };
>
> clocks {
> - xo_board: xo_board {
> + xo_board: xo-board {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> clock-frequency = <19200000>;
> };
>
> - sleep_clk: sleep_clk {
> + sleep_clk: sleep-clk {
> compatible = "fixed-clock";
> #clock-cells = <0>;
> clock-frequency = <32768>;
> @@ -1783,7 +1783,7 @@ rpm {
> qcom,ipc = <&apcs 8 0>;
> qcom,smd-edge = <15>;
>
> - rpm_requests {
> + rpm-requests {
> compatible = "qcom,rpm-msm8916";
> qcom,smd-channels = "rpm_requests";
>
> --
> 2.26.2
>
^ permalink raw reply
* [PATCH net-next 0/2] DP83822 Fiber enablement
From: Dan Murphy @ 2020-05-14 17:30 UTC (permalink / raw)
To: andrew, f.fainelli, hkallweit1, davem
Cc: robh, netdev, linux-kernel, devicetree, Dan Murphy
Hello
The DP83822 Ethernet PHY has the ability to connect via a Fiber port. The
DP83825 or DP83826 do not have this ability. In order to keep the same
driver the DP83822 and the 825/826 phy_driver call backs need to be changed
so that the DP83822 has it's own call back for config_init and adds a probe
call back.
A devicetree binding was added to set the signal polarity for the fiber
connection. This property is only applicable in fiber mode and is optional
in fiber mode.
Dan
Dan Murphy (2):
dt-bindings: net: dp83822: Add TI dp83822 phy
net: phy: DP83822: Add ability to advertise Fiber connection
.../devicetree/bindings/net/ti,dp83822.yaml | 49 ++++++
drivers/net/phy/dp83822.c | 140 +++++++++++++++++-
2 files changed, 181 insertions(+), 8 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/ti,dp83822.yaml
--
2.26.2
^ permalink raw reply
* [PATCH net-next 1/2] dt-bindings: net: dp83822: Add TI dp83822 phy
From: Dan Murphy @ 2020-05-14 17:30 UTC (permalink / raw)
To: andrew, f.fainelli, hkallweit1, davem
Cc: robh, netdev, linux-kernel, devicetree, Dan Murphy, Rob Herring
In-Reply-To: <20200514173055.15013-1-dmurphy@ti.com>
Add a dt binding for the TI dp83822 ethernet phy device.
CC: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
.../devicetree/bindings/net/ti,dp83822.yaml | 49 +++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/ti,dp83822.yaml
diff --git a/Documentation/devicetree/bindings/net/ti,dp83822.yaml b/Documentation/devicetree/bindings/net/ti,dp83822.yaml
new file mode 100644
index 000000000000..60afd43ad3b6
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ti,dp83822.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
+# Copyright (C) 2020 Texas Instruments Incorporated
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/net/ti,dp83822.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: TI DP83822 ethernet PHY
+
+allOf:
+ - $ref: "ethernet-controller.yaml#"
+
+maintainers:
+ - Dan Murphy <dmurphy@ti.com>
+
+description: |
+ The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
+ provides all of the physical layer functions needed to transmit and receive
+ data over standard, twisted-pair cables or to connect to an external,
+ fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
+ connect to a MAC through a standard MII, RMII, or RGMII interface
+
+ Specifications about the charger can be found at:
+ http://www.ti.com/lit/ds/symlink/dp83822i.pdf
+
+properties:
+ reg:
+ maxItems: 1
+
+ ti,signal-polarity-low:
+ type: boolean
+ description: |
+ DP83822 PHY in Fiber mode only.
+ Sets the DP83822 to detect a link drop condition when the signal goes
+ high. If not set then link drop will occur when the signal goes low.
+
+required:
+ - reg
+
+examples:
+ - |
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,signal-polarity-low;
+ };
+ };
--
2.26.2
^ permalink raw reply related
* [PATCH net-next 2/2] net: phy: DP83822: Add ability to advertise Fiber connection
From: Dan Murphy @ 2020-05-14 17:30 UTC (permalink / raw)
To: andrew, f.fainelli, hkallweit1, davem
Cc: robh, netdev, linux-kernel, devicetree, Dan Murphy
In-Reply-To: <20200514173055.15013-1-dmurphy@ti.com>
The DP83822 can be configured to use a Fiber connection. The strap
register is read to determine if the device has been configured to use
a fiber connection. With the fiber connection the PHY can be configured
to detect whether the fiber connection is active by either a high signal
or a low signal.
Fiber mode is only applicable to the DP83822 so rework the PHY match
table so that non-fiber PHYs can still use the same driver but not call
or use any of the fiber features.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
---
drivers/net/phy/dp83822.c | 140 +++++++++++++++++++++++++++++++++++---
1 file changed, 132 insertions(+), 8 deletions(-)
diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c
index 1dd19d0cb269..fe7443bc8b06 100644
--- a/drivers/net/phy/dp83822.c
+++ b/drivers/net/phy/dp83822.c
@@ -27,6 +27,11 @@
#define MII_DP83822_MISR1 0x12
#define MII_DP83822_MISR2 0x13
#define MII_DP83822_RESET_CTRL 0x1f
+#define MII_DP83822_GENCFG 0x465
+#define MII_DP83822_SOR1 0x467
+
+/* GENCFG */
+#define DP83822_SIG_DET_POLARITY BIT(0)
#define DP83822_HW_RESET BIT(15)
#define DP83822_SW_RESET BIT(14)
@@ -77,6 +82,21 @@
#define DP83822_WOL_INDICATION_SEL BIT(8)
#define DP83822_WOL_CLR_INDICATION BIT(11)
+/* SOR1 bits */
+#define DP83822_FX_EN_STRAP BIT(11)
+#define DP83822_FX_DUPLEX_STRAP BIT(0)
+
+#define MII_DP83822_FIBER_ADVERTISE (SUPPORTED_AUI | SUPPORTED_FIBRE | \
+ SUPPORTED_BNC | SUPPORTED_Pause | \
+ SUPPORTED_Asym_Pause | \
+ SUPPORTED_100baseT_Full)
+
+struct dp83822_private {
+ bool fx_signal_detect_low;
+ int fx_enabled;
+ u16 fx_duplex_mode;
+};
+
static int dp83822_ack_interrupt(struct phy_device *phydev)
{
int err;
@@ -255,7 +275,7 @@ static int dp83822_config_intr(struct phy_device *phydev)
return phy_write(phydev, MII_DP83822_PHYSCR, physcr_status);
}
-static int dp83822_config_init(struct phy_device *phydev)
+static int dp8382x_disable_wol(struct phy_device *phydev)
{
int value = DP83822_WOL_EN | DP83822_WOL_MAGIC_EN |
DP83822_WOL_SECURE_ON;
@@ -264,6 +284,41 @@ static int dp83822_config_init(struct phy_device *phydev)
MII_DP83822_WOL_CFG, value);
}
+static int dp83822_config_init(struct phy_device *phydev)
+{
+ struct dp83822_private *dp83822 = phydev->priv;
+ int err = 0;
+
+ if (dp83822->fx_enabled) {
+ linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
+ phydev->supported);
+ linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
+ phydev->advertising);
+
+ /* Auto negotiation is not available in fiber mode */
+ phydev->autoneg = AUTONEG_DISABLE;
+ phydev->speed = SPEED_100;
+ phydev->duplex = DUPLEX_FULL;
+
+ /* Setup fiber advertisement */
+ err = phy_modify_changed(phydev, MII_ADVERTISE,
+ ADVERTISE_1000XFULL |
+ ADVERTISE_1000XPAUSE |
+ ADVERTISE_1000XPSE_ASYM,
+ MII_DP83822_FIBER_ADVERTISE);
+
+ if (err < 0)
+ return err;
+ }
+
+ return dp8382x_disable_wol(phydev);
+}
+
+static int dp8382x_config_init(struct phy_device *phydev)
+{
+ return dp8382x_disable_wol(phydev);
+}
+
static int dp83822_phy_reset(struct phy_device *phydev)
{
int err;
@@ -272,7 +327,60 @@ static int dp83822_phy_reset(struct phy_device *phydev)
if (err < 0)
return err;
- dp83822_config_init(phydev);
+ return phydev->drv->config_init(phydev);
+}
+
+#ifdef CONFIG_OF_MDIO
+static int dp83822_of_init(struct phy_device *phydev)
+{
+ struct dp83822_private *dp83822 = phydev->priv;
+ struct device *dev = &phydev->mdio.dev;
+
+ if (dp83822->fx_enabled)
+ dp83822->fx_signal_detect_low = device_property_present(dev,
+ "ti,signal-polarity-low");
+
+ return 0;
+}
+#else
+static int dp83822_of_init(struct phy_device *phydev)
+{
+ return 0;
+}
+#endif /* CONFIG_OF_MDIO */
+
+static int dp83822_read_straps(struct phy_device *phydev)
+{
+ struct dp83822_private *dp83822 = phydev->priv;
+ u16 val;
+
+ val = phy_read_mmd(phydev, DP83822_DEVADDR, MII_DP83822_SOR1);
+ if (val < 0)
+ return val;
+
+ dp83822->fx_enabled = val & DP83822_FX_EN_STRAP;
+ dp83822->fx_duplex_mode = val & DP83822_FX_DUPLEX_STRAP;
+
+ return 0;
+}
+
+static int dp83822_probe(struct phy_device *phydev)
+{
+ struct dp83822_private *dp83822;
+ int ret;
+
+ dp83822 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83822),
+ GFP_KERNEL);
+ if (!dp83822)
+ return -ENOMEM;
+
+ phydev->priv = dp83822;
+
+ ret = dp83822_read_straps(phydev);
+ if (ret)
+ return ret;
+
+ dp83822_of_init(phydev);
return 0;
}
@@ -308,6 +416,7 @@ static int dp83822_resume(struct phy_device *phydev)
PHY_ID_MATCH_MODEL(_id), \
.name = (_name), \
/* PHY_BASIC_FEATURES */ \
+ .probe = dp83822_probe, \
.soft_reset = dp83822_phy_reset, \
.config_init = dp83822_config_init, \
.get_wol = dp83822_get_wol, \
@@ -318,14 +427,29 @@ static int dp83822_resume(struct phy_device *phydev)
.resume = dp83822_resume, \
}
+#define DP8382X_PHY_DRIVER(_id, _name) \
+ { \
+ PHY_ID_MATCH_MODEL(_id), \
+ .name = (_name), \
+ /* PHY_BASIC_FEATURES */ \
+ .soft_reset = dp83822_phy_reset, \
+ .config_init = dp8382x_config_init, \
+ .get_wol = dp83822_get_wol, \
+ .set_wol = dp83822_set_wol, \
+ .ack_interrupt = dp83822_ack_interrupt, \
+ .config_intr = dp83822_config_intr, \
+ .suspend = dp83822_suspend, \
+ .resume = dp83822_resume, \
+ }
+
static struct phy_driver dp83822_driver[] = {
DP83822_PHY_DRIVER(DP83822_PHY_ID, "TI DP83822"),
- DP83822_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"),
- DP83822_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"),
- DP83822_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"),
- DP83822_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"),
- DP83822_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"),
- DP83822_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"),
+ DP8382X_PHY_DRIVER(DP83825I_PHY_ID, "TI DP83825I"),
+ DP8382X_PHY_DRIVER(DP83826C_PHY_ID, "TI DP83826C"),
+ DP8382X_PHY_DRIVER(DP83826NC_PHY_ID, "TI DP83826NC"),
+ DP8382X_PHY_DRIVER(DP83825S_PHY_ID, "TI DP83825S"),
+ DP8382X_PHY_DRIVER(DP83825CM_PHY_ID, "TI DP83825M"),
+ DP8382X_PHY_DRIVER(DP83825CS_PHY_ID, "TI DP83825CS"),
};
module_phy_driver(dp83822_driver);
--
2.26.2
^ permalink raw reply related
* Re: [PATCH v4 06/10] dt-bindings: mtd: update STM32 FMC2 NAND controller documentation
From: Rob Herring @ 2020-05-14 17:55 UTC (permalink / raw)
To: Christophe Kerello
Cc: Miquèl Raynal, Richard Weinberger, Vignesh R, Mark Rutland,
Greg Kroah-Hartman, Boris Brezillon, MTD Maling List,
linux-kernel@vger.kernel.org, linux-stm32, devicetree,
Marek Vašut
In-Reply-To: <9ffc04cf-137f-5ee5-57ff-39a876abfb34@st.com>
On Thu, May 14, 2020 at 11:35 AM Christophe Kerello
<christophe.kerello@st.com> wrote:
>
> Hi Rob,
>
> On 5/14/20 5:00 PM, Rob Herring wrote:
> > On Wed, May 06, 2020 at 11:11:15AM +0200, Christophe Kerello wrote:
> >> These bindings can be used on SOCs where the FMC2 NAND controller is
> >> in standalone. In case that the FMC2 embeds 2 controllers (an external
> >> bus controller and a raw NAND controller), the register base and the
> >> clock will be defined in the parent node. It is the reason why the
> >> register base address and the clock are now optional.
> >>
> >> Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
> >> ---
> >> .../devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml | 19 ++++++++++---------
> >> 1 file changed, 10 insertions(+), 9 deletions(-)
> >>
> >> diff --git a/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml b/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml
> >> index b059267..68fac1a 100644
> >> --- a/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml
> >> +++ b/Documentation/devicetree/bindings/mtd/st,stm32-fmc2-nand.yaml
> >> @@ -18,13 +18,15 @@ properties:
> >>
> >> reg:
> >> items:
> >> - - description: Registers
> >> + - description: Registers (optional)
> >
> > The only thing that can be optional are the last entries. You have to do
> > a 'oneOf' with 6 entries and 7 entries.
>
> Ok, so the way to describe the reg property in my case should be:
> reg:
> oneOf:
> - description: FMC2 embeds the NFC controller in standalone.
> items:
> - description: Registers
> - description: Chip select 0 data
> - description: Chip select 0 command
> - description: Chip select 0 address space
> - description: Chip select 1 data
> - description: Chip select 1 command
> - description: Chip select 1 address space
>
> - description: FMC2 embeds the NFC controller and the EBI
> controller.
> items:
> - description: Chip select 0 data
> - description: Chip select 0 command
> - description: Chip select 0 address space
> - description: Chip select 1 data
> - description: Chip select 1 command
> - description: Chip select 1 address space
>
> >
> > And where's your new compatible string for this different h/w?
>
> From NFC controller point of view, it is the same HW.
That's what everyone says until they have some quirk or integration
difference to handle.
> In the case that we have 2 controllers embedded, the register base is
> shared.
> The NFC driver will check at probe time the compatible string of its
> parent node.
> In case that it is "st,stm32mp1-fmc2-ebi", then the driver will find the
> register base in the parent node (EBI node), otherwise it will find it
> in the NFC node.
> Is it better to have 2 compatible strings (one for each reg description)
> than checking the parent's compatible string and have only one
> compatible string?
Why not just put the register base into the child node too? While
overlapping 'reg' regions for siblings is bad, it's fine for child
nodes. I guess since there are chip selects for the child nodes that
may not work here.
It doesn't hurt to have another compatible. You can always make the
old one a fallback. With different compatibles you can make sure reg
has the right number of entries.
Rob
^ permalink raw reply
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