* [PATCH v2 5/7] iio: accel: bma180: Add support for bma023
From: Jonathan Bakker @ 2020-05-14 20:48 UTC (permalink / raw)
To: jic23, knaack.h, lars, pmeerw, robh+dt, linus.walleij, kstewart,
tglx, linux-iio, devicetree, linux-kernel
Cc: Jonathan Bakker
In-Reply-To: <20200514204901.3199-1-xc-racer2@live.ca>
The bma023 chip is similar enough to the bma180 and bma25x that the
same driver can support all of them. The biggest differences are
the lack of a temperature channel and no low power but still working
mode.
The bma150 is a close relative of the bma023, but it does have a
temperature channel so support is not added for it.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Jonathan Bakker <xc-racer2@live.ca>
---
Changes from v1
- Added R-b tag
---
drivers/iio/accel/Kconfig | 6 +-
drivers/iio/accel/bma180.c | 123 +++++++++++++++++++++++++++++++++++--
2 files changed, 122 insertions(+), 7 deletions(-)
diff --git a/drivers/iio/accel/Kconfig b/drivers/iio/accel/Kconfig
index 09e8c51f854a..60d1be99f93b 100644
--- a/drivers/iio/accel/Kconfig
+++ b/drivers/iio/accel/Kconfig
@@ -89,13 +89,13 @@ config ADXL372_I2C
module will be called adxl372_i2c.
config BMA180
- tristate "Bosch BMA180/BMA25x 3-Axis Accelerometer Driver"
+ tristate "Bosch BMA023/BMA180/BMA25x 3-Axis Accelerometer Driver"
depends on I2C && INPUT_BMA150=n
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
help
- Say Y here if you want to build a driver for the Bosch BMA180 or
- BMA25x triaxial acceleration sensor.
+ Say Y here if you want to build a driver for the Bosch BMA023, BMA180
+ or BMA25x triaxial acceleration sensor.
To compile this driver as a module, choose M here: the
module will be called bma180.
diff --git a/drivers/iio/accel/bma180.c b/drivers/iio/accel/bma180.c
index 75440dd83ec4..19d4f174a890 100644
--- a/drivers/iio/accel/bma180.c
+++ b/drivers/iio/accel/bma180.c
@@ -7,6 +7,7 @@
* Support for BMA250 (c) Peter Meerwald <pmeerw@pmeerw.net>
*
* SPI is not supported by driver
+ * BMA023: 7-bit I2C slave address 0x38
* BMA180: 7-bit I2C slave address 0x40 or 0x41
* BMA250: 7-bit I2C slave address 0x18 or 0x19
* BMA254: 7-bit I2C slave address 0x18 or 0x19
@@ -33,6 +34,7 @@
#define BMA180_IRQ_NAME "bma180_event"
enum chip_ids {
+ BMA023,
BMA180,
BMA250,
BMA254,
@@ -64,6 +66,18 @@ struct bma180_part_info {
};
/* Register set */
+#define BMA023_CTRL_REG0 0x0a
+#define BMA023_CTRL_REG1 0x0b
+#define BMA023_CTRL_REG2 0x14
+#define BMA023_CTRL_REG3 0x15
+
+#define BMA023_RANGE_MASK GENMASK(4, 3) /* Range of accel values */
+#define BMA023_BW_MASK GENMASK(2, 0) /* Accel bandwidth */
+#define BMA023_SLEEP BIT(0)
+#define BMA023_INT_RESET_MASK BIT(6)
+#define BMA023_NEW_DATA_INT BIT(5) /* Intr every new accel data is ready */
+#define BMA023_RESET_VAL BIT(1)
+
#define BMA180_CHIP_ID 0x00 /* Need to distinguish BMA180 from other */
#define BMA180_ACC_X_LSB 0x02 /* First of 6 registers of accel data */
#define BMA180_TEMP 0x08
@@ -94,6 +108,7 @@ struct bma180_part_info {
/* We have to write this value in reset register to do soft reset */
#define BMA180_RESET_VAL 0xb6
+#define BMA023_ID_REG_VAL 0x02
#define BMA180_ID_REG_VAL 0x03
#define BMA250_ID_REG_VAL 0x03
#define BMA254_ID_REG_VAL 0xfa /* 250 decimal */
@@ -156,6 +171,9 @@ enum bma180_chan {
TEMP
};
+static int bma023_bw_table[] = { 25, 50, 100, 190, 375, 750, 1500 }; /* Hz */
+static int bma023_scale_table[] = { 2452, 4903, 9709, };
+
static int bma180_bw_table[] = { 10, 20, 40, 75, 150, 300 }; /* Hz */
static int bma180_scale_table[] = { 1275, 1863, 2452, 3727, 4903, 9709, 19417 };
@@ -350,17 +368,37 @@ static int bma180_chip_init(struct bma180_data *data)
*/
msleep(20);
- ret = bma180_set_new_data_intr_state(data, false);
+ return bma180_set_new_data_intr_state(data, false);
+}
+
+static int bma023_chip_config(struct bma180_data *data)
+{
+ int ret = bma180_chip_init(data);
+
if (ret)
- return ret;
+ goto err;
+
+ ret = bma180_set_bw(data, 50); /* 50 Hz */
+ if (ret)
+ goto err;
+ ret = bma180_set_scale(data, 2452); /* 2 G */
+ if (ret)
+ goto err;
- return bma180_set_pmode(data, false);
+ return 0;
+
+err:
+ dev_err(&data->client->dev, "failed to config the chip\n");
+ return ret;
}
static int bma180_chip_config(struct bma180_data *data)
{
int ret = bma180_chip_init(data);
+ if (ret)
+ goto err;
+ ret = bma180_set_pmode(data, false);
if (ret)
goto err;
ret = bma180_set_bits(data, BMA180_CTRL_REG0, BMA180_DIS_WAKE_UP, 1);
@@ -390,6 +428,9 @@ static int bma25x_chip_config(struct bma180_data *data)
{
int ret = bma180_chip_init(data);
+ if (ret)
+ goto err;
+ ret = bma180_set_pmode(data, false);
if (ret)
goto err;
ret = bma180_set_bw(data, 16); /* 16 Hz */
@@ -414,6 +455,17 @@ static int bma25x_chip_config(struct bma180_data *data)
return ret;
}
+static void bma023_chip_disable(struct bma180_data *data)
+{
+ if (bma180_set_sleep_state(data, true))
+ goto err;
+
+ return;
+
+err:
+ dev_err(&data->client->dev, "failed to disable the chip\n");
+}
+
static void bma180_chip_disable(struct bma180_data *data)
{
if (bma180_set_new_data_intr_state(data, false))
@@ -610,6 +662,11 @@ static const struct iio_enum bma180_power_mode_enum = {
.set = bma180_set_power_mode,
};
+static const struct iio_chan_spec_ext_info bma023_ext_info[] = {
+ IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bma180_accel_get_mount_matrix),
+ { }
+};
+
static const struct iio_chan_spec_ext_info bma180_ext_info[] = {
IIO_ENUM("power_mode", true, &bma180_power_mode_enum),
IIO_ENUM_AVAILABLE("power_mode", &bma180_power_mode_enum),
@@ -617,6 +674,23 @@ static const struct iio_chan_spec_ext_info bma180_ext_info[] = {
{ }
};
+#define BMA023_ACC_CHANNEL(_axis, _bits) { \
+ .type = IIO_ACCEL, \
+ .modified = 1, \
+ .channel2 = IIO_MOD_##_axis, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
+ BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
+ .scan_index = AXIS_##_axis, \
+ .scan_type = { \
+ .sign = 's', \
+ .realbits = _bits, \
+ .storagebits = 16, \
+ .shift = 16 - _bits, \
+ }, \
+ .ext_info = bma023_ext_info, \
+}
+
#define BMA180_ACC_CHANNEL(_axis, _bits) { \
.type = IIO_ACCEL, \
.modified = 1, \
@@ -646,6 +720,13 @@ static const struct iio_chan_spec_ext_info bma180_ext_info[] = {
}, \
}
+static const struct iio_chan_spec bma023_channels[] = {
+ BMA023_ACC_CHANNEL(X, 10),
+ BMA023_ACC_CHANNEL(Y, 10),
+ BMA023_ACC_CHANNEL(Z, 10),
+ IIO_CHAN_SOFT_TIMESTAMP(4),
+};
+
static const struct iio_chan_spec bma180_channels[] = {
BMA180_ACC_CHANNEL(X, 14),
BMA180_ACC_CHANNEL(Y, 14),
@@ -671,6 +752,35 @@ static const struct iio_chan_spec bma254_channels[] = {
};
static const struct bma180_part_info bma180_part_info[] = {
+ [BMA023] = {
+ .chip_id = BMA023_ID_REG_VAL,
+ .channels = bma023_channels,
+ .num_channels = ARRAY_SIZE(bma023_channels),
+ .scale_table = bma023_scale_table,
+ .num_scales = ARRAY_SIZE(bma023_scale_table),
+ .bw_table = bma023_bw_table,
+ .num_bw = ARRAY_SIZE(bma023_bw_table),
+ /* No temperature channel */
+ .center_temp = 0,
+ .int_reset_reg = BMA023_CTRL_REG0,
+ .int_reset_mask = BMA023_INT_RESET_MASK,
+ .sleep_reg = BMA023_CTRL_REG0,
+ .sleep_mask = BMA023_SLEEP,
+ .bw_reg = BMA023_CTRL_REG2,
+ .bw_mask = BMA023_BW_MASK,
+ .scale_reg = BMA023_CTRL_REG2,
+ .scale_mask = BMA023_RANGE_MASK,
+ /* No power mode on bma023 */
+ .power_reg = 0,
+ .power_mask = 0,
+ .lowpower_val = 0,
+ .int_enable_reg = BMA023_CTRL_REG3,
+ .int_enable_mask = BMA023_NEW_DATA_INT,
+ .softreset_reg = BMA023_CTRL_REG0,
+ .softreset_val = BMA023_RESET_VAL,
+ .chip_config = bma023_chip_config,
+ .chip_disable = bma023_chip_disable,
+ },
[BMA180] = {
.chip_id = BMA180_ID_REG_VAL,
.channels = bma180_channels,
@@ -994,6 +1104,7 @@ static SIMPLE_DEV_PM_OPS(bma180_pm_ops, bma180_suspend, bma180_resume);
#endif
static const struct i2c_device_id bma180_ids[] = {
+ { "bma023", BMA023 },
{ "bma180", BMA180 },
{ "bma250", BMA250 },
{ "bma254", BMA254 },
@@ -1003,6 +1114,10 @@ static const struct i2c_device_id bma180_ids[] = {
MODULE_DEVICE_TABLE(i2c, bma180_ids);
static const struct of_device_id bma180_of_match[] = {
+ {
+ .compatible = "bosch,bma023",
+ .data = (void *)BMA023
+ },
{
.compatible = "bosch,bma180",
.data = (void *)BMA180
@@ -1034,5 +1149,5 @@ module_i2c_driver(bma180_driver);
MODULE_AUTHOR("Kravchenko Oleksandr <x0199363@ti.com>");
MODULE_AUTHOR("Texas Instruments, Inc.");
-MODULE_DESCRIPTION("Bosch BMA180/BMA25x triaxial acceleration sensor");
+MODULE_DESCRIPTION("Bosch BMA023/BMA180/BMA25x triaxial acceleration sensor");
MODULE_LICENSE("GPL");
--
2.20.1
^ permalink raw reply related
* [PATCH v2 6/7] iio: accel: bma180: Rename center_temp to temp_offset
From: Jonathan Bakker @ 2020-05-14 20:49 UTC (permalink / raw)
To: jic23, knaack.h, lars, pmeerw, robh+dt, linus.walleij, kstewart,
tglx, linux-iio, devicetree, linux-kernel
Cc: Jonathan Bakker
In-Reply-To: <20200514204901.3199-1-xc-racer2@live.ca>
The bma180 driver is being extended to support the bma150.
Its temperature channel is unsigned so the center_temp naming
no longer makes.
Signed-off-by: Jonathan Bakker <xc-racer2@live.ca>
---
drivers/iio/accel/bma180.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/iio/accel/bma180.c b/drivers/iio/accel/bma180.c
index 19d4f174a890..23da0a79b0c4 100644
--- a/drivers/iio/accel/bma180.c
+++ b/drivers/iio/accel/bma180.c
@@ -50,7 +50,7 @@ struct bma180_part_info {
unsigned int num_scales;
const int *bw_table;
unsigned int num_bw;
- int center_temp;
+ int temp_offset;
u8 int_reset_reg, int_reset_mask;
u8 sleep_reg, sleep_mask;
@@ -584,7 +584,7 @@ static int bma180_read_raw(struct iio_dev *indio_dev,
return -EINVAL;
}
case IIO_CHAN_INFO_OFFSET:
- *val = data->part_info->center_temp;
+ *val = data->part_info->temp_offset;
return IIO_VAL_INT;
default:
return -EINVAL;
@@ -761,7 +761,7 @@ static const struct bma180_part_info bma180_part_info[] = {
.bw_table = bma023_bw_table,
.num_bw = ARRAY_SIZE(bma023_bw_table),
/* No temperature channel */
- .center_temp = 0,
+ .temp_offset = 0,
.int_reset_reg = BMA023_CTRL_REG0,
.int_reset_mask = BMA023_INT_RESET_MASK,
.sleep_reg = BMA023_CTRL_REG0,
@@ -789,7 +789,7 @@ static const struct bma180_part_info bma180_part_info[] = {
.num_scales = ARRAY_SIZE(bma180_scale_table),
.bw_table = bma180_bw_table,
.num_bw = ARRAY_SIZE(bma180_bw_table),
- .center_temp = 48, /* 0 LSB @ 24 degree C */
+ .temp_offset = 48, /* 0 LSB @ 24 degree C */
.int_reset_reg = BMA180_CTRL_REG0,
.int_reset_mask = BMA180_RESET_INT,
.sleep_reg = BMA180_CTRL_REG0,
@@ -816,7 +816,7 @@ static const struct bma180_part_info bma180_part_info[] = {
.num_scales = ARRAY_SIZE(bma25x_scale_table),
.bw_table = bma25x_bw_table,
.num_bw = ARRAY_SIZE(bma25x_bw_table),
- .center_temp = 48, /* 0 LSB @ 24 degree C */
+ .temp_offset = 48, /* 0 LSB @ 24 degree C */
.int_reset_reg = BMA250_INT_RESET_REG,
.int_reset_mask = BMA250_INT_RESET_MASK,
.sleep_reg = BMA250_POWER_REG,
@@ -845,7 +845,7 @@ static const struct bma180_part_info bma180_part_info[] = {
.num_scales = ARRAY_SIZE(bma25x_scale_table),
.bw_table = bma25x_bw_table,
.num_bw = ARRAY_SIZE(bma25x_bw_table),
- .center_temp = 46, /* 0 LSB @ 23 degree C */
+ .temp_offset = 46, /* 0 LSB @ 23 degree C */
.int_reset_reg = BMA254_INT_RESET_REG,
.int_reset_mask = BMA254_INT_RESET_MASK,
.sleep_reg = BMA254_POWER_REG,
--
2.20.1
^ permalink raw reply related
* [PATCH v2 7/7] iio: accel: Add bma150/smb380 support to bma180
From: Jonathan Bakker @ 2020-05-14 20:49 UTC (permalink / raw)
To: jic23, knaack.h, lars, pmeerw, robh+dt, linus.walleij, kstewart,
tglx, linux-iio, devicetree, linux-kernel
Cc: Jonathan Bakker
In-Reply-To: <20200514204901.3199-1-xc-racer2@live.ca>
The bma150/smb380 are very similar to the bma023 but have a temperature
channel as well.
Signed-off-by: Jonathan Bakker <xc-racer2@live.ca>
---
drivers/iio/accel/Kconfig | 6 ++--
drivers/iio/accel/bma180.c | 71 +++++++++++++++++++++++++++++++++++---
2 files changed, 70 insertions(+), 7 deletions(-)
diff --git a/drivers/iio/accel/Kconfig b/drivers/iio/accel/Kconfig
index 60d1be99f93b..109ae0c8b35d 100644
--- a/drivers/iio/accel/Kconfig
+++ b/drivers/iio/accel/Kconfig
@@ -89,13 +89,13 @@ config ADXL372_I2C
module will be called adxl372_i2c.
config BMA180
- tristate "Bosch BMA023/BMA180/BMA25x 3-Axis Accelerometer Driver"
+ tristate "Bosch BMA023/BMA1x0/BMA25x 3-Axis Accelerometer Driver"
depends on I2C && INPUT_BMA150=n
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
help
- Say Y here if you want to build a driver for the Bosch BMA023, BMA180
- or BMA25x triaxial acceleration sensor.
+ Say Y here if you want to build a driver for the Bosch BMA023, BMA150
+ BMA180, SMB380, or BMA25x triaxial acceleration sensor.
To compile this driver as a module, choose M here: the
module will be called bma180.
diff --git a/drivers/iio/accel/bma180.c b/drivers/iio/accel/bma180.c
index 23da0a79b0c4..265722e4b13f 100644
--- a/drivers/iio/accel/bma180.c
+++ b/drivers/iio/accel/bma180.c
@@ -7,7 +7,7 @@
* Support for BMA250 (c) Peter Meerwald <pmeerw@pmeerw.net>
*
* SPI is not supported by driver
- * BMA023: 7-bit I2C slave address 0x38
+ * BMA023/BMA150/SMB380: 7-bit I2C slave address 0x38
* BMA180: 7-bit I2C slave address 0x40 or 0x41
* BMA250: 7-bit I2C slave address 0x18 or 0x19
* BMA254: 7-bit I2C slave address 0x18 or 0x19
@@ -35,6 +35,7 @@
enum chip_ids {
BMA023,
+ BMA150,
BMA180,
BMA250,
BMA254,
@@ -565,8 +566,12 @@ static int bma180_read_raw(struct iio_dev *indio_dev,
iio_device_release_direct_mode(indio_dev);
if (ret < 0)
return ret;
- *val = sign_extend32(ret >> chan->scan_type.shift,
- chan->scan_type.realbits - 1);
+ if (chan->scan_type.sign == 's') {
+ *val = sign_extend32(ret >> chan->scan_type.shift,
+ chan->scan_type.realbits - 1);
+ } else {
+ *val = ret;
+ }
return IIO_VAL_INT;
case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
*val = data->bw;
@@ -691,6 +696,18 @@ static const struct iio_chan_spec_ext_info bma180_ext_info[] = {
.ext_info = bma023_ext_info, \
}
+#define BMA150_TEMP_CHANNEL { \
+ .type = IIO_TEMP, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
+ BIT(IIO_CHAN_INFO_SCALE) | BIT(IIO_CHAN_INFO_OFFSET), \
+ .scan_index = TEMP, \
+ .scan_type = { \
+ .sign = 'u', \
+ .realbits = 8, \
+ .storagebits = 16, \
+ }, \
+}
+
#define BMA180_ACC_CHANNEL(_axis, _bits) { \
.type = IIO_ACCEL, \
.modified = 1, \
@@ -727,6 +744,14 @@ static const struct iio_chan_spec bma023_channels[] = {
IIO_CHAN_SOFT_TIMESTAMP(4),
};
+static const struct iio_chan_spec bma150_channels[] = {
+ BMA023_ACC_CHANNEL(X, 10),
+ BMA023_ACC_CHANNEL(Y, 10),
+ BMA023_ACC_CHANNEL(Z, 10),
+ BMA150_TEMP_CHANNEL,
+ IIO_CHAN_SOFT_TIMESTAMP(4),
+};
+
static const struct iio_chan_spec bma180_channels[] = {
BMA180_ACC_CHANNEL(X, 14),
BMA180_ACC_CHANNEL(Y, 14),
@@ -781,6 +806,34 @@ static const struct bma180_part_info bma180_part_info[] = {
.chip_config = bma023_chip_config,
.chip_disable = bma023_chip_disable,
},
+ [BMA150] = {
+ .chip_id = BMA023_ID_REG_VAL,
+ .channels = bma150_channels,
+ .num_channels = ARRAY_SIZE(bma150_channels),
+ .scale_table = bma023_scale_table,
+ .num_scales = ARRAY_SIZE(bma023_scale_table),
+ .bw_table = bma023_bw_table,
+ .num_bw = ARRAY_SIZE(bma023_bw_table),
+ .temp_offset = -60, /* 0 LSB @ -30 degree C */
+ .int_reset_reg = BMA023_CTRL_REG0,
+ .int_reset_mask = BMA023_INT_RESET_MASK,
+ .sleep_reg = BMA023_CTRL_REG0,
+ .sleep_mask = BMA023_SLEEP,
+ .bw_reg = BMA023_CTRL_REG2,
+ .bw_mask = BMA023_BW_MASK,
+ .scale_reg = BMA023_CTRL_REG2,
+ .scale_mask = BMA023_RANGE_MASK,
+ /* No power mode on bma150 */
+ .power_reg = 0,
+ .power_mask = 0,
+ .lowpower_val = 0,
+ .int_enable_reg = BMA023_CTRL_REG3,
+ .int_enable_mask = BMA023_NEW_DATA_INT,
+ .softreset_reg = BMA023_CTRL_REG0,
+ .softreset_val = BMA023_RESET_VAL,
+ .chip_config = bma023_chip_config,
+ .chip_disable = bma023_chip_disable,
+ },
[BMA180] = {
.chip_id = BMA180_ID_REG_VAL,
.channels = bma180_channels,
@@ -1105,9 +1158,11 @@ static SIMPLE_DEV_PM_OPS(bma180_pm_ops, bma180_suspend, bma180_resume);
static const struct i2c_device_id bma180_ids[] = {
{ "bma023", BMA023 },
+ { "bma150", BMA150 },
{ "bma180", BMA180 },
{ "bma250", BMA250 },
{ "bma254", BMA254 },
+ { "smb380", BMA150 },
{ }
};
@@ -1118,6 +1173,10 @@ static const struct of_device_id bma180_of_match[] = {
.compatible = "bosch,bma023",
.data = (void *)BMA023
},
+ {
+ .compatible = "bosch,bma150",
+ .data = (void *)BMA150
+ },
{
.compatible = "bosch,bma180",
.data = (void *)BMA180
@@ -1130,6 +1189,10 @@ static const struct of_device_id bma180_of_match[] = {
.compatible = "bosch,bma254",
.data = (void *)BMA254
},
+ {
+ .compatible = "bosch,smb380",
+ .data = (void *)BMA150
+ },
{ }
};
MODULE_DEVICE_TABLE(of, bma180_of_match);
@@ -1149,5 +1212,5 @@ module_i2c_driver(bma180_driver);
MODULE_AUTHOR("Kravchenko Oleksandr <x0199363@ti.com>");
MODULE_AUTHOR("Texas Instruments, Inc.");
-MODULE_DESCRIPTION("Bosch BMA023/BMA180/BMA25x triaxial acceleration sensor");
+MODULE_DESCRIPTION("Bosch BMA023/BMA1x0/BMA25x triaxial acceleration sensor");
MODULE_LICENSE("GPL");
--
2.20.1
^ permalink raw reply related
* [PATCH v2 2/7] iio: accel: Make bma180 conflict with input's bma150
From: Jonathan Bakker @ 2020-05-14 20:48 UTC (permalink / raw)
To: jic23, knaack.h, lars, pmeerw, robh+dt, linus.walleij, kstewart,
tglx, linux-iio, devicetree, linux-kernel
Cc: Jonathan Bakker
In-Reply-To: <20200514204901.3199-1-xc-racer2@live.ca>
The bma180 IIO driver is being extended for support for the chips
support by input's bma150 driver (bma023, bma150, smb380). Don't
allow both drivers to be enabled simultaneously as they're for the
same hardware.
Signed-off-by: Jonathan Bakker <xc-racer2@live.ca>
---
drivers/iio/accel/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iio/accel/Kconfig b/drivers/iio/accel/Kconfig
index 5d91a6dda894..09e8c51f854a 100644
--- a/drivers/iio/accel/Kconfig
+++ b/drivers/iio/accel/Kconfig
@@ -90,7 +90,7 @@ config ADXL372_I2C
config BMA180
tristate "Bosch BMA180/BMA25x 3-Axis Accelerometer Driver"
- depends on I2C
+ depends on I2C && INPUT_BMA150=n
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
help
--
2.20.1
^ permalink raw reply related
* [PATCH v2 0/7] iio: accel: Add bma150 family support to bma180
From: Jonathan Bakker @ 2020-05-14 20:48 UTC (permalink / raw)
To: jic23, knaack.h, lars, pmeerw, robh+dt, linus.walleij, kstewart,
tglx, linux-iio, devicetree, linux-kernel
Cc: Jonathan Bakker
This patchset adds support for the bma023, bma150, and smb380 three
axis accelerometers to the bma180 IIO driver. The bma023 is found
on several ~2010 phones, including the first-gen Galaxy S series.
The bma023 differs from later chips (bma180, bma25x) in that it
has no low power but still working mode and no temperature
channel. The bma150 is very similar to the bma023, but has a
temperature channel.
As these chips are also supported by an input driver, the bma180 IIO
driver now explicitly conflicts with INPUT_BMA150 in the Kconfig.
While I was at it, I noticed that the dt binding doc was missing
the regulators, so I've added those in.
The patches have been tested on a GT-i9000 with a bma023. The interrupt
pin is not connected on this board so the trigger was not tested. The
bma150 was only tested by changing the compatible and confirming that
the accelerometer channels were working.
Changes from v1:
-Added patches for bma150 and smb380 variants
-Add R-b and A-b tags
-Change so BMA180 and INPUT_BMA150 conflict rather than removing
the i2c ids from the input driver when the iio driver is enabled
Jonathan Bakker (7):
iio: accel: bma180: Prepare for different reset values
iio: accel: Make bma180 conflict with input's bma150
dt-bindings: iio: accel: Add bma150 family compatibles to bma180
dt-bindings: iio: accel: Add required regulators to bma180
iio: accel: bma180: Add support for bma023
iio: accel: bma180: Rename center_temp to temp_offset
iio: accel: Add bma150/smb380 support to bma180
.../devicetree/bindings/iio/accel/bma180.txt | 8 +-
drivers/iio/accel/Kconfig | 8 +-
drivers/iio/accel/bma180.c | 208 ++++++++++++++++--
3 files changed, 206 insertions(+), 18 deletions(-)
--
2.20.1
^ permalink raw reply
* Re: [PATCH v3 02/16] mfd: mfd-core: Don't overwrite the dma_mask of the child device
From: Michael Walle @ 2020-05-14 20:45 UTC (permalink / raw)
To: Mark Brown
Cc: Robin Murphy, Andy Shevchenko, linux-gpio, devicetree,
linux-kernel, linux-hwmon, linux-pwm, linux-watchdog,
linux-arm-kernel, Linus Walleij, Bartosz Golaszewski, Rob Herring,
Jean Delvare, Guenter Roeck, Lee Jones, Thierry Reding,
Uwe Kleine-König, Wim Van Sebroeck, Shawn Guo, Li Yang,
Thomas Gleixner, Jason Cooper, Marc Zyngier, Greg Kroah-Hartman
In-Reply-To: <20200428152543.GI5677@sirena.org.uk>
Am 2020-04-28 17:25, schrieb Mark Brown:
> On Tue, Apr 28, 2020 at 03:49:49PM +0100, Robin Murphy wrote:
>
>> For better or worse, the platform bus is the dumping ground for random
>> crap,
>> so we just have to deal with all the abstraction breakage that leaks
>> out of
>> that.
>
> The reason we're using the platform bus for this is that historically
> people were creating buses which were essentially carbon copies of the
> platform bus with the name changed and it was felt that rather than
> duplicate code it was better to just use platform devices with no MMIO
> ranges defined. If there's some assumptions about DMA for platform
> devices floating about somewhere it might be reasonable to revisit this
> and create a non-DMA variant of platform devices since there is a
> meaningful difference.
Was there any conclusion? Should I keep or drop this patch in the next
version
of this series?
--
-michael
^ permalink raw reply
* Re: [PATCH V3 3/8] clk: qcom: Add A53 PLL support for ipq6018 devices
From: Stephen Boyd @ 2020-05-14 20:40 UTC (permalink / raw)
To: Sivaprakash Murugesan, agross, bjorn.andersson, devicetree,
jassisinghbrar, linux-arm-msm, linux-clk, linux-kernel,
mturquette, robh+dt
In-Reply-To: <4025e5c3-b532-d235-f73b-2b86055bdde2@codeaurora.org>
Quoting Sivaprakash Murugesan (2020-04-22 03:44:33)
> On 4/22/2020 2:30 PM, Stephen Boyd wrote:
> > Quoting Sivaprakash Murugesan (2020-04-13 19:55:17)
> >> diff --git a/drivers/clk/qcom/a53-pll.c b/drivers/clk/qcom/a53-pll.c
> >> index 45cfc57..a95351c 100644
> >> --- a/drivers/clk/qcom/a53-pll.c
> >> +++ b/drivers/clk/qcom/a53-pll.c
> >> @@ -57,30 +146,26 @@ static int qcom_a53pll_probe(struct platform_device *pdev)
> >> if (IS_ERR(regmap))
> >> return PTR_ERR(regmap);
> >>
> >> - pll->l_reg = 0x04;
> >> - pll->m_reg = 0x08;
> >> - pll->n_reg = 0x0c;
> >> - pll->config_reg = 0x14;
> >> - pll->mode_reg = 0x00;
> >> - pll->status_reg = 0x1c;
> >> - pll->status_bit = 16;
> >> - pll->freq_tbl = a53pll_freq;
> >> -
> >> - init.name = "a53pll";
> >> - init.parent_names = (const char *[]){ "xo" };
> >> - init.num_parents = 1;
> >> - init.ops = &clk_pll_sr2_ops;
> >> - init.flags = CLK_IS_CRITICAL;
> > Please document why a clk is critical.
> ok
> >
> >> - pll->clkr.hw.init = &init;
> >> -
> >> - ret = devm_clk_register_regmap(dev, &pll->clkr);
> >> + if (pll_data->flags & PLL_IS_ALPHA) {
> >> + struct clk_alpha_pll *alpha_pll =
> >> + pll_data->a53pll.alpha_pll.pll;
> >> + struct alpha_pll_config *alpha_pll_config =
> >> + pll_data->a53pll.alpha_pll.pll_config;
> >> +
> >> + clk_alpha_pll_configure(alpha_pll, regmap, alpha_pll_config);
> >> + clkr = &pll_data->a53pll.alpha_pll.pll->clkr;
> >> + } else {
> >> + clkr = &pll_data->a53pll.pll->clkr;
> >> + }
> > Sorry, the design is confusing.
>
> The basic idea is to add support for various PLLs available to clock the
> A53 core.
>
> if this messing up the code, can the alpha pll support be moved to a
> separate file?
>
> It would be very helpful if you provide your input on this.
Isn't the alpha PLL support already in a different file? Is it sometimes
an alpha pll and other times it is something else?
^ permalink raw reply
* [PATCH v4 05/10] dt-bindings: PCI: qcom: Add ext reset
From: Ansuel Smith @ 2020-05-14 20:07 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Ansuel Smith, Rob Herring, Andy Gross, Bjorn Helgaas, Rob Herring,
Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi, Andrew Murray,
Philipp Zabel, linux-arm-msm, linux-pci, devicetree, linux-kernel
In-Reply-To: <20200514200712.12232-1-ansuelsmth@gmail.com>
Document ext reset used in ipq8064 SoC by qcom PCIe driver.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/pci/qcom,pcie.txt | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index becdbdc0fffa..6efcef040741 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -179,6 +179,7 @@
- "pwr" PWR reset
- "ahb" AHB reset
- "phy_ahb" PHY AHB reset
+ - "ext" EXT reset
- reset-names:
Usage: required for ipq8074
@@ -287,8 +288,9 @@
<&gcc PCIE_HCLK_RESET>,
<&gcc PCIE_POR_RESET>,
<&gcc PCIE_PCI_RESET>,
- <&gcc PCIE_PHY_RESET>;
- reset-names = "axi", "ahb", "por", "pci", "phy";
+ <&gcc PCIE_PHY_RESET>,
+ <&gcc PCIE_EXT_RESET>;
+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
pinctrl-0 = <&pcie_pins_default>;
pinctrl-names = "default";
};
--
2.25.1
^ permalink raw reply related
* [PATCH v4 02/10] dt-bindings: PCI: qcom: Add missing clks
From: Ansuel Smith @ 2020-05-14 20:07 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Ansuel Smith, Rob Herring, Andy Gross, Bjorn Helgaas, Rob Herring,
Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi, Andrew Murray,
Philipp Zabel, linux-arm-msm, linux-pci, devicetree, linux-kernel
In-Reply-To: <20200514200712.12232-1-ansuelsmth@gmail.com>
Document missing clks used in ipq8064 SoC.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/pci/qcom,pcie.txt | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index 981b4de12807..becdbdc0fffa 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -90,6 +90,8 @@
Definition: Should contain the following entries
- "core" Clocks the pcie hw block
- "phy" Clocks the pcie PHY block
+ - "aux" Clocks the pcie AUX block
+ - "ref" Clocks the pcie ref block
- clock-names:
Usage: required for apq8084/ipq4019
Value type: <stringlist>
@@ -277,8 +279,10 @@
<0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc PCIE_A_CLK>,
<&gcc PCIE_H_CLK>,
- <&gcc PCIE_PHY_CLK>;
- clock-names = "core", "iface", "phy";
+ <&gcc PCIE_PHY_CLK>,
+ <&gcc PCIE_AUX_CLK>,
+ <&gcc PCIE_ALT_REF_CLK>;
+ clock-names = "core", "iface", "phy", "aux", "ref";
resets = <&gcc PCIE_ACLK_RESET>,
<&gcc PCIE_HCLK_RESET>,
<&gcc PCIE_POR_RESET>,
--
2.25.1
^ permalink raw reply related
* [PATCH v4 06/10] PCI: qcom: Use bulk clk api and assert on error
From: Ansuel Smith @ 2020-05-14 20:07 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Ansuel Smith, Andy Gross, Bjorn Helgaas, Rob Herring,
Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi, Andrew Murray,
Philipp Zabel, linux-arm-msm, linux-pci, devicetree, linux-kernel
In-Reply-To: <20200514200712.12232-1-ansuelsmth@gmail.com>
Rework 2.1.0 revision to use bulk clk api and fix missing assert on
reset_control_deassert error.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 131 +++++++++----------------
1 file changed, 46 insertions(+), 85 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 4dab5ef630cc..f2ea1ab6f584 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -84,12 +84,9 @@
#define DEVICE_TYPE_RC 0x4
#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
+#define QCOM_PCIE_2_1_0_MAX_CLOCKS 5
struct qcom_pcie_resources_2_1_0 {
- struct clk *iface_clk;
- struct clk *core_clk;
- struct clk *phy_clk;
- struct clk *aux_clk;
- struct clk *ref_clk;
+ struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS];
struct reset_control *pci_reset;
struct reset_control *axi_reset;
struct reset_control *ahb_reset;
@@ -237,25 +234,21 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
if (ret)
return ret;
- res->iface_clk = devm_clk_get(dev, "iface");
- if (IS_ERR(res->iface_clk))
- return PTR_ERR(res->iface_clk);
-
- res->core_clk = devm_clk_get(dev, "core");
- if (IS_ERR(res->core_clk))
- return PTR_ERR(res->core_clk);
-
- res->phy_clk = devm_clk_get(dev, "phy");
- if (IS_ERR(res->phy_clk))
- return PTR_ERR(res->phy_clk);
+ res->clks[0].id = "iface";
+ res->clks[1].id = "core";
+ res->clks[2].id = "phy";
+ res->clks[3].id = "aux";
+ res->clks[4].id = "ref";
- res->aux_clk = devm_clk_get_optional(dev, "aux");
- if (IS_ERR(res->aux_clk))
- return PTR_ERR(res->aux_clk);
+ /* iface, core, phy are required */
+ ret = devm_clk_bulk_get(dev, 3, res->clks);
+ if (ret < 0)
+ return ret;
- res->ref_clk = devm_clk_get_optional(dev, "ref");
- if (IS_ERR(res->ref_clk))
- return PTR_ERR(res->ref_clk);
+ /* aux, ref are optional */
+ ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3);
+ if (ret < 0)
+ return ret;
res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
if (IS_ERR(res->pci_reset))
@@ -285,17 +278,13 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
{
struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
- clk_disable_unprepare(res->phy_clk);
+ clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
reset_control_assert(res->pci_reset);
reset_control_assert(res->axi_reset);
reset_control_assert(res->ahb_reset);
reset_control_assert(res->por_reset);
reset_control_assert(res->ext_reset);
reset_control_assert(res->phy_reset);
- clk_disable_unprepare(res->iface_clk);
- clk_disable_unprepare(res->core_clk);
- clk_disable_unprepare(res->aux_clk);
- clk_disable_unprepare(res->ref_clk);
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
}
@@ -313,36 +302,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
return ret;
}
- ret = reset_control_assert(res->ahb_reset);
- if (ret) {
- dev_err(dev, "cannot assert ahb reset\n");
- goto err_assert_ahb;
- }
-
- ret = clk_prepare_enable(res->iface_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable iface clock\n");
- goto err_assert_ahb;
- }
-
- ret = clk_prepare_enable(res->core_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable core clock\n");
- goto err_clk_core;
- }
-
- ret = clk_prepare_enable(res->aux_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable aux clock\n");
- goto err_clk_aux;
- }
-
- ret = clk_prepare_enable(res->ref_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable ref clock\n");
- goto err_clk_ref;
- }
-
ret = reset_control_deassert(res->ahb_reset);
if (ret) {
dev_err(dev, "cannot deassert ahb reset\n");
@@ -352,48 +311,46 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
ret = reset_control_deassert(res->ext_reset);
if (ret) {
dev_err(dev, "cannot deassert ext reset\n");
- goto err_deassert_ahb;
+ goto err_deassert_ext;
}
- /* enable PCIe clocks and resets */
- val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
- val &= ~BIT(0);
- writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
-
- /* enable external reference clock */
- val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
- val |= BIT(16);
- writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
-
ret = reset_control_deassert(res->phy_reset);
if (ret) {
dev_err(dev, "cannot deassert phy reset\n");
- return ret;
+ goto err_deassert_phy;
}
ret = reset_control_deassert(res->pci_reset);
if (ret) {
dev_err(dev, "cannot deassert pci reset\n");
- return ret;
+ goto err_deassert_pci;
}
ret = reset_control_deassert(res->por_reset);
if (ret) {
dev_err(dev, "cannot deassert por reset\n");
- return ret;
+ goto err_deassert_por;
}
ret = reset_control_deassert(res->axi_reset);
if (ret) {
dev_err(dev, "cannot deassert axi reset\n");
- return ret;
+ goto err_deassert_axi;
}
- ret = clk_prepare_enable(res->phy_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable phy clock\n");
- goto err_deassert_ahb;
- }
+ ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
+ if (ret)
+ goto err_clks;
+
+ /* enable PCIe clocks and resets */
+ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
+ val &= ~BIT(0);
+ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+
+ /* enable external reference clock */
+ val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
+ val |= BIT(16);
+ writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
/* wait for clock acquisition */
usleep_range(1000, 1500);
@@ -407,15 +364,19 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
return 0;
+err_clks:
+ reset_control_assert(res->axi_reset);
+err_deassert_axi:
+ reset_control_assert(res->por_reset);
+err_deassert_por:
+ reset_control_assert(res->pci_reset);
+err_deassert_pci:
+ reset_control_assert(res->phy_reset);
+err_deassert_phy:
+ reset_control_assert(res->ext_reset);
+err_deassert_ext:
+ reset_control_assert(res->ahb_reset);
err_deassert_ahb:
- clk_disable_unprepare(res->ref_clk);
-err_clk_ref:
- clk_disable_unprepare(res->aux_clk);
-err_clk_aux:
- clk_disable_unprepare(res->core_clk);
-err_clk_core:
- clk_disable_unprepare(res->iface_clk);
-err_assert_ahb:
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
return ret;
--
2.25.1
^ permalink raw reply related
* [PATCH v4 04/10] PCI: qcom: Add missing reset for ipq806x
From: Ansuel Smith @ 2020-05-14 20:07 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Ansuel Smith, Sham Muthayyan, stable, Rob Herring, Philipp Zabel,
Andy Gross, Bjorn Helgaas, Rob Herring, Mark Rutland,
Stanimir Varbanov, Lorenzo Pieralisi, Andrew Murray,
linux-arm-msm, linux-pci, devicetree, linux-kernel
In-Reply-To: <20200514200712.12232-1-ansuelsmth@gmail.com>
Add missing ext reset used by ipq8064 SoC in PCIe qcom driver.
Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Cc: stable@vger.kernel.org # v4.5+
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
---
drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 4512c2c5f61c..4dab5ef630cc 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -95,6 +95,7 @@ struct qcom_pcie_resources_2_1_0 {
struct reset_control *ahb_reset;
struct reset_control *por_reset;
struct reset_control *phy_reset;
+ struct reset_control *ext_reset;
struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
};
@@ -272,6 +273,10 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
if (IS_ERR(res->por_reset))
return PTR_ERR(res->por_reset);
+ res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext");
+ if (IS_ERR(res->ext_reset))
+ return PTR_ERR(res->ext_reset);
+
res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
return PTR_ERR_OR_ZERO(res->phy_reset);
}
@@ -285,6 +290,7 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
reset_control_assert(res->axi_reset);
reset_control_assert(res->ahb_reset);
reset_control_assert(res->por_reset);
+ reset_control_assert(res->ext_reset);
reset_control_assert(res->phy_reset);
clk_disable_unprepare(res->iface_clk);
clk_disable_unprepare(res->core_clk);
@@ -343,6 +349,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
goto err_deassert_ahb;
}
+ ret = reset_control_deassert(res->ext_reset);
+ if (ret) {
+ dev_err(dev, "cannot deassert ext reset\n");
+ goto err_deassert_ahb;
+ }
+
/* enable PCIe clocks and resets */
val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
val &= ~BIT(0);
--
2.25.1
^ permalink raw reply related
* [PATCH v4 10/10] PCI: qcom: Add Force GEN1 support
From: Ansuel Smith @ 2020-05-14 20:07 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Sham Muthayyan, Ansuel Smith, Andy Gross, Bjorn Helgaas,
Rob Herring, Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi,
Andrew Murray, Philipp Zabel, linux-arm-msm, linux-pci,
devicetree, linux-kernel
In-Reply-To: <20200514200712.12232-1-ansuelsmth@gmail.com>
From: Sham Muthayyan <smuthayy@codeaurora.org>
Add Force GEN1 support needed in some ipq8064 board that needs to limit
some PCIe line to gen1 for some hardware limitation. This is set by the
max-link-speed binding and needed by some soc based on ipq8064. (for
example Netgear R7800 router)
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index ab6f1bdd24c3..f6190c954e92 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -27,6 +27,7 @@
#include <linux/slab.h>
#include <linux/types.h>
+#include "../../pci.h"
#include "pcie-designware.h"
#define PCIE20_PARF_SYS_CTRL 0x00
@@ -99,6 +100,8 @@
#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
#define SLV_ADDR_SPACE_SZ 0x10000000
+#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0
+
#define DEVICE_TYPE_RC 0x4
#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
@@ -195,6 +198,7 @@ struct qcom_pcie {
struct phy *phy;
struct gpio_desc *reset;
const struct qcom_pcie_ops *ops;
+ int gen;
};
#define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
@@ -395,6 +399,11 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
/* wait for clock acquisition */
usleep_range(1000, 1500);
+ if (pcie->gen == 1) {
+ val = readl(pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
+ val |= 1;
+ writel(val, pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2);
+ }
/* Set the Max TLP size to 2K, instead of using default of 4K */
writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
@@ -1397,6 +1406,10 @@ static int qcom_pcie_probe(struct platform_device *pdev)
goto err_pm_runtime_put;
}
+ pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node);
+ if (pcie->gen < 0)
+ pcie->gen = 2;
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
pcie->parf = devm_ioremap_resource(dev, res);
if (IS_ERR(pcie->parf)) {
--
2.25.1
^ permalink raw reply related
* [PATCH v4 08/10] PCI: qcom: Add ipq8064 rev2 variant and set tx term offset
From: Ansuel Smith @ 2020-05-14 20:07 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Ansuel Smith, Sham Muthayyan, Andy Gross, Bjorn Helgaas,
Rob Herring, Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi,
Andrew Murray, Philipp Zabel, linux-arm-msm, linux-pci,
devicetree, linux-kernel
In-Reply-To: <20200514200712.12232-1-ansuelsmth@gmail.com>
Add tx term offset support to pcie qcom driver need in some revision of
the ipq806x SoC. Ipq8064 have tx term offset set to 7. Ipq8064-v2 revision
and ipq8065 have the tx term offset set to 0.
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index f5398b0d270c..ab6f1bdd24c3 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -45,6 +45,9 @@
#define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
#define PCIE20_PARF_PHY_CTRL 0x40
+#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
+#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) ((x) << 16)
+
#define PCIE20_PARF_PHY_REFCLK 0x4C
#define PHY_REFCLK_SSP_EN BIT(16)
#define PHY_REFCLK_USE_PAD BIT(12)
@@ -363,7 +366,8 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
val &= ~BIT(0);
writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
- if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
+ if (of_device_is_compatible(node, "qcom,pcie-ipq8064") |
+ of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
@@ -374,9 +378,18 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
}
+ if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
+ /* set TX termination offset */
+ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
+ val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
+ val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7);
+ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+ }
+
/* enable external reference clock */
val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
- val |= BIT(16);
+ val &= ~PHY_REFCLK_USE_PAD;
+ val |= PHY_REFCLK_SSP_EN;
writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
/* wait for clock acquisition */
@@ -1452,6 +1465,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
static const struct of_device_id qcom_pcie_match[] = {
{ .compatible = "qcom,pcie-apq8084", .data = &ops_1_0_0 },
{ .compatible = "qcom,pcie-ipq8064", .data = &ops_2_1_0 },
+ { .compatible = "qcom,pcie-ipq8064-v2", .data = &ops_2_1_0 },
{ .compatible = "qcom,pcie-apq8064", .data = &ops_2_1_0 },
{ .compatible = "qcom,pcie-msm8996", .data = &ops_2_3_2 },
{ .compatible = "qcom,pcie-ipq8074", .data = &ops_2_3_3 },
--
2.25.1
^ permalink raw reply related
* [PATCH v4 09/10] dt-bindings: PCI: qcom: Add ipq8064 rev 2 variant
From: Ansuel Smith @ 2020-05-14 20:07 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Ansuel Smith, Rob Herring, Andy Gross, Bjorn Helgaas, Rob Herring,
Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi, Andrew Murray,
Philipp Zabel, linux-arm-msm, linux-pci, devicetree, linux-kernel
In-Reply-To: <20200514200712.12232-1-ansuelsmth@gmail.com>
Document qcom,pcie-ipq8064-v2 needed to use different phy_tx0_term_offset.
In ipq8064 phy_tx0_term_offset is 7. In ipq8064 v2 other SoC it's set to 0
by default.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/pci/qcom,pcie.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index 6efcef040741..02bc81bb8b2d 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -5,6 +5,7 @@
Value type: <stringlist>
Definition: Value should contain
- "qcom,pcie-ipq8064" for ipq8064
+ - "qcom,pcie-ipq8064-v2" for ipq8064 rev 2 or ipq8065
- "qcom,pcie-apq8064" for apq8064
- "qcom,pcie-apq8084" for apq8084
- "qcom,pcie-msm8996" for msm8996 or apq8096
--
2.25.1
^ permalink raw reply related
* [PATCH v4 07/10] PCI: qcom: Define some PARF params needed for ipq8064 SoC
From: Ansuel Smith @ 2020-05-14 20:07 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Ansuel Smith, stable, Andy Gross, Bjorn Helgaas, Rob Herring,
Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi, Andrew Murray,
Philipp Zabel, linux-arm-msm, linux-pci, devicetree, linux-kernel
In-Reply-To: <20200514200712.12232-1-ansuelsmth@gmail.com>
Set some specific value for Tx De-Emphasis, Tx Swing and Rx equalization
needed on some ipq8064 based device (Netgear R7800 for example). Without
this the system locks on kernel load.
Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Cc: stable@vger.kernel.org # v4.5+
---
drivers/pci/controller/dwc/pcie-qcom.c | 27 ++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index f2ea1ab6f584..f5398b0d270c 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -46,6 +46,9 @@
#define PCIE20_PARF_PHY_CTRL 0x40
#define PCIE20_PARF_PHY_REFCLK 0x4C
+#define PHY_REFCLK_SSP_EN BIT(16)
+#define PHY_REFCLK_USE_PAD BIT(12)
+
#define PCIE20_PARF_DBI_BASE_ADDR 0x168
#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
@@ -77,6 +80,18 @@
#define DBI_RO_WR_EN 1
#define PERST_DELAY_US 1000
+/* PARF registers */
+#define PCIE20_PARF_PCS_DEEMPH 0x34
+#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) ((x) << 16)
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) ((x) << 8)
+#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) ((x) << 0)
+
+#define PCIE20_PARF_PCS_SWING 0x38
+#define PCS_SWING_TX_SWING_FULL(x) ((x) << 8)
+#define PCS_SWING_TX_SWING_LOW(x) ((x) << 0)
+
+#define PCIE20_PARF_CONFIG_BITS 0x50
+#define PHY_RX0_EQ(x) ((x) << 24)
#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
#define SLV_ADDR_SPACE_SZ 0x10000000
@@ -293,6 +308,7 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
+ struct device_node *node = dev->of_node;
u32 val;
int ret;
@@ -347,6 +363,17 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
val &= ~BIT(0);
writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+ if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
+ writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
+ PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
+ PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
+ pcie->parf + PCIE20_PARF_PCS_DEEMPH);
+ writel(PCS_SWING_TX_SWING_FULL(120) |
+ PCS_SWING_TX_SWING_LOW(120),
+ pcie->parf + PCIE20_PARF_PCS_SWING);
+ writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
+ }
+
/* enable external reference clock */
val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
val |= BIT(16);
--
2.25.1
^ permalink raw reply related
* [PATCH v4 03/10] PCI: qcom: Change duplicate PCI reset to phy reset
From: Ansuel Smith @ 2020-05-14 20:07 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Abhishek Sahu, Ansuel Smith, Rob Herring, Andy Gross,
Bjorn Helgaas, Rob Herring, Mark Rutland, Stanimir Varbanov,
Lorenzo Pieralisi, Andrew Murray, Philipp Zabel, linux-arm-msm,
linux-pci, devicetree, linux-kernel
In-Reply-To: <20200514200712.12232-1-ansuelsmth@gmail.com>
From: Abhishek Sahu <absahu@codeaurora.org>
The deinit issues reset_control_assert for PCI twice and does not contain
phy reset.
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
drivers/pci/controller/dwc/pcie-qcom.c | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 4bf93ab8c7a7..4512c2c5f61c 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -280,14 +280,14 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
{
struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
+ clk_disable_unprepare(res->phy_clk);
reset_control_assert(res->pci_reset);
reset_control_assert(res->axi_reset);
reset_control_assert(res->ahb_reset);
reset_control_assert(res->por_reset);
- reset_control_assert(res->pci_reset);
+ reset_control_assert(res->phy_reset);
clk_disable_unprepare(res->iface_clk);
clk_disable_unprepare(res->core_clk);
- clk_disable_unprepare(res->phy_clk);
clk_disable_unprepare(res->aux_clk);
clk_disable_unprepare(res->ref_clk);
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
@@ -325,12 +325,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
goto err_clk_core;
}
- ret = clk_prepare_enable(res->phy_clk);
- if (ret) {
- dev_err(dev, "cannot prepare/enable phy clock\n");
- goto err_clk_phy;
- }
-
ret = clk_prepare_enable(res->aux_clk);
if (ret) {
dev_err(dev, "cannot prepare/enable aux clock\n");
@@ -383,6 +377,12 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
return ret;
}
+ ret = clk_prepare_enable(res->phy_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable phy clock\n");
+ goto err_deassert_ahb;
+ }
+
/* wait for clock acquisition */
usleep_range(1000, 1500);
@@ -400,8 +400,6 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
err_clk_ref:
clk_disable_unprepare(res->aux_clk);
err_clk_aux:
- clk_disable_unprepare(res->phy_clk);
-err_clk_phy:
clk_disable_unprepare(res->core_clk);
err_clk_core:
clk_disable_unprepare(res->iface_clk);
--
2.25.1
^ permalink raw reply related
* [PATCH v4 01/10] PCI: qcom: Add missing ipq806x clocks in PCIe driver
From: Ansuel Smith @ 2020-05-14 20:07 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Ansuel Smith, Sham Muthayyan, Andy Gross, Bjorn Helgaas,
Rob Herring, Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi,
Andrew Murray, Philipp Zabel, linux-arm-msm, linux-pci,
devicetree, linux-kernel
In-Reply-To: <20200514200712.12232-1-ansuelsmth@gmail.com>
Aux and Ref clk are missing in PCIe qcom driver. Add support for this
optional clks for ipq8064/apq8064 SoC.
Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/pci/controller/dwc/pcie-qcom.c | 38 ++++++++++++++++++++++----
1 file changed, 33 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 5ea527a6bd9f..4bf93ab8c7a7 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -88,6 +88,8 @@ struct qcom_pcie_resources_2_1_0 {
struct clk *iface_clk;
struct clk *core_clk;
struct clk *phy_clk;
+ struct clk *aux_clk;
+ struct clk *ref_clk;
struct reset_control *pci_reset;
struct reset_control *axi_reset;
struct reset_control *ahb_reset;
@@ -246,6 +248,14 @@ static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
if (IS_ERR(res->phy_clk))
return PTR_ERR(res->phy_clk);
+ res->aux_clk = devm_clk_get_optional(dev, "aux");
+ if (IS_ERR(res->aux_clk))
+ return PTR_ERR(res->aux_clk);
+
+ res->ref_clk = devm_clk_get_optional(dev, "ref");
+ if (IS_ERR(res->ref_clk))
+ return PTR_ERR(res->ref_clk);
+
res->pci_reset = devm_reset_control_get_exclusive(dev, "pci");
if (IS_ERR(res->pci_reset))
return PTR_ERR(res->pci_reset);
@@ -278,6 +288,8 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
clk_disable_unprepare(res->iface_clk);
clk_disable_unprepare(res->core_clk);
clk_disable_unprepare(res->phy_clk);
+ clk_disable_unprepare(res->aux_clk);
+ clk_disable_unprepare(res->ref_clk);
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
}
@@ -307,16 +319,28 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
goto err_assert_ahb;
}
+ ret = clk_prepare_enable(res->core_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable core clock\n");
+ goto err_clk_core;
+ }
+
ret = clk_prepare_enable(res->phy_clk);
if (ret) {
dev_err(dev, "cannot prepare/enable phy clock\n");
goto err_clk_phy;
}
- ret = clk_prepare_enable(res->core_clk);
+ ret = clk_prepare_enable(res->aux_clk);
if (ret) {
- dev_err(dev, "cannot prepare/enable core clock\n");
- goto err_clk_core;
+ dev_err(dev, "cannot prepare/enable aux clock\n");
+ goto err_clk_aux;
+ }
+
+ ret = clk_prepare_enable(res->ref_clk);
+ if (ret) {
+ dev_err(dev, "cannot prepare/enable ref clock\n");
+ goto err_clk_ref;
}
ret = reset_control_deassert(res->ahb_reset);
@@ -372,10 +396,14 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
return 0;
err_deassert_ahb:
- clk_disable_unprepare(res->core_clk);
-err_clk_core:
+ clk_disable_unprepare(res->ref_clk);
+err_clk_ref:
+ clk_disable_unprepare(res->aux_clk);
+err_clk_aux:
clk_disable_unprepare(res->phy_clk);
err_clk_phy:
+ clk_disable_unprepare(res->core_clk);
+err_clk_core:
clk_disable_unprepare(res->iface_clk);
err_assert_ahb:
regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
--
2.25.1
^ permalink raw reply related
* [PATCH v4 00/10] Multiple fixes in PCIe qcom driver
From: Ansuel Smith @ 2020-05-14 20:07 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Ansuel Smith, Andy Gross, Bjorn Helgaas, Rob Herring,
Mark Rutland, Stanimir Varbanov, Lorenzo Pieralisi, Andrew Murray,
Philipp Zabel, linux-arm-msm, linux-pci, devicetree, linux-kernel
This contains multiple fix for PCIe qcom driver.
Some optional reset and clocks were missing.
Fix a problem with no PARF programming that cause kernel lock on load.
Add support to force gen 1 speed if needed. (due to hardware limitation)
Add ipq8064 rev 2 support that use a different tx termination offset.
v4:
* Fix grammar error across all patch subject
* Use bulk api for clks
* Program PARF only in ipq8064 SoC
* Program tx term only in ipq8064 SoC
* Drop configurable tx-dempth rx-eq
* Make added clk optional
v3:
* Fix check reported by checkpatch --strict
* Rename force_gen1 to gen
v2:
* Drop iATU programming (already done in pcie init)
* Use max-link-speed instead of force-gen1 custom definition
* Drop MRRS to 256B (Can't find a realy reason why this was suggested)
* Introduce a new variant for different revision of ipq8064
Abhishek Sahu (1):
PCI: qcom: Change duplicate PCI reset to phy reset
Ansuel Smith (8):
PCI: qcom: Add missing ipq806x clocks in PCIe driver
dt-bindings: PCI: qcom: Add missing clks
PCI: qcom: Add missing reset for ipq806x
dt-bindings: PCI: qcom: Add ext reset
PCI: qcom: Use bulk clk api and assert on error
PCI: qcom: Define some PARF params needed for ipq8064 SoC
PCI: qcom: Add ipq8064 rev2 variant and set tx term offset
dt-bindings: PCI: qcom: Add ipq8064 rev 2 variant
Sham Muthayyan (1):
PCI: qcom: Add Force GEN1 support
.../devicetree/bindings/pci/qcom,pcie.txt | 15 +-
drivers/pci/controller/dwc/pcie-qcom.c | 171 ++++++++++++------
2 files changed, 123 insertions(+), 63 deletions(-)
--
2.25.1
^ permalink raw reply
* Re: [PATCH RFC] dt-bindings: pinctrl: sh-pfc: Convert to json-schema
From: Geert Uytterhoeven @ 2020-05-14 20:00 UTC (permalink / raw)
To: Rob Herring
Cc: Linus Walleij, Linux-Renesas, open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
In-Reply-To: <20200430023237.GA23316@bogus>
Hi Rob,
On Thu, Apr 30, 2020 at 4:32 AM Rob Herring <robh@kernel.org> wrote:
> On Fri, Apr 17, 2020 at 04:09:20PM +0200, Geert Uytterhoeven wrote:
> > Convert the Renesas Pin Function Controller (PFC) Device Tree binding
> > documentation to json-schema.
> >
> > Document missing properties.
> > Drop deprecated and obsolete #gpio-range-cells property.
> > Update the example to match reality.
> > Drop consumer examples, as they do not belong here.
> >
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > ---
> > How to describe that pin configuration nodes can have subnodes?
> > E.g.
> >
> > arch/arm/boot/dts/sh73a0-kzm9g.dt.yaml: pin-controller@e6050000: mmc: Additional properties are not allowed ('cfg', 'mux' were unexpected)
>
> I shouldn't tell you so no one does this again...
>
> I think you want something like this assuming you have either
> grandchildren or properties, but not both in the child nodes:
>
> patternProperties:
> ".*":
> if:
> type: object
> then:
> oneOf:
> - allOf:
> - $ref: pincfg-node.yaml#
> - $ref: pinmux-node.yaml#
> ...
> - patternProperties:
> ".*":
> type: object
> allOf:
> - $ref: pincfg-node.yaml#
> - $ref: pinmux-node.yaml#
Thanks, sounds sane!
As there are phandles pointing to the child node, I do need an explicit
phandle property in the child node...
> If you did have a mixture, then you'd need the same if/then construct.
... so I have a mixture, and do need the if/then construct.
However, that gives me "is valid under each of" errors for all child nodes
of sh-pfc nodes.
As both child and grandchild do not have any required properties, I
tried adding some, but that didn't help.
Do you have a clue? For reference, this is what I ended up with:
patternProperties:
"^.*$":
if:
type: object
then:
oneOf:
- allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
description:
Pinctrl node's client devices use subnodes for desired pin
configuration.
Client device subnodes use below standard properties.
properties:
phandle: true
pins: true
groups: true
function: true
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength:
enum: [ 3, 6, 9, 12, 15, 18, 21, 24 ] # Superset of
supported values
power-source:
enum: [ 1800, 3300 ]
gpio-hog: true
gpios: true
input: true
output-high: true
output-low: true
additionalProperties: false
- properties:
phandle: true
patternProperties:
"^.*$":
if:
type: object
then:
allOf:
- $ref: pincfg-node.yaml#
- $ref: pinmux-node.yaml#
description:
Pinctrl node's client devices use subnodes for desired pin
configuration.
Client device subnodes use below standard properties.
properties:
pins: true
groups: true
function: true
bias-disable: true
bias-pull-down: true
bias-pull-up: true
drive-strength:
enum: [ 3, 6, 9, 12, 15, 18, 21, 24 ] # Superset
of supported values
power-source:
enum: [ 1800, 3300 ]
gpio-hog: true
gpios: true
input: true
output-high: true
output-low: true
additionalProperties: false
additionalProperties: false
> Now it probably ends up that the 'allOf' and everything else with it are
> duplicated. If so you can do:
>
> definitions:
> pin-nodes:
> allOf:
> ...
>
> And use '$ref: #/definitions/pin-nodes' where you need it.
>
> That probably is not going to work with the fixups the tooling does, but
> we could fix that.
Obviously I haven't tried this part yet, but I'll keep it in mind.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCHv2 2/2] dt-bindings: arm: coresight: Add support to skip trace unit power up
From: Sai Prakash Ranjan @ 2020-05-14 19:57 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Mike Leach, devicetree,
Rob Herring
Cc: Stephen Boyd, Leo Yan, linux-arm-kernel, linux-kernel,
linux-arm-msm, Tingwei Zhang, coresight, Sai Prakash Ranjan
In-Reply-To: <cover.1589485594.git.saiprakash.ranjan@codeaurora.org>
From: Tingwei Zhang <tingwei@codeaurora.org>
Add "qcom,skip-power-up" property to identify systems which can
skip powering up of trace unit since they share the same power
domain as their CPU core. This is required to identify such
systems with hardware errata which stops the CPU watchdog counter
when the power up bit is set (TRCPDCR.PU).
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
Co-developed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
Documentation/devicetree/bindings/arm/coresight.txt | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
index 846f6daae71b..e4b2eda0b53b 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -108,6 +108,13 @@ its hardware characteristcs.
* arm,cp14: must be present if the system accesses ETM/PTM management
registers via co-processor 14.
+ * qcom,skip-power-up: boolean. Indicates that an implementation can
+ skip powering up the trace unit. TRCPDCR.PU does not have to be set
+ on Qualcomm Technologies Inc. systems since ETMs are in the same power
+ domain as their CPU cores. This property is required to identify such
+ systems with hardware errata where the CPU watchdog counter is stopped
+ when TRCPDCR.PU is set.
+
* Optional property for TMC:
* arm,buffer-size: size of contiguous buffer space for TMC ETR
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCHv2 1/2] coresight: etm4x: Add support to skip trace unit power up
From: Sai Prakash Ranjan @ 2020-05-14 19:57 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Mike Leach, devicetree,
Rob Herring
Cc: Stephen Boyd, Leo Yan, linux-arm-kernel, linux-kernel,
linux-arm-msm, Tingwei Zhang, coresight, Sai Prakash Ranjan
In-Reply-To: <cover.1589485594.git.saiprakash.ranjan@codeaurora.org>
From: Tingwei Zhang <tingwei@codeaurora.org>
On some Qualcomm Technologies Inc. SoCs like SC7180, there
exists a hardware errata where the APSS (Application Processor
SubSystem)/CPU watchdog counter is stopped when the trace unit
power up ETM register is set (TRCPDCR.PU = 1). Since the ETMs
share the same power domain as that of respective CPU cores,
they are powered on when the CPU core is powered on. So we can
skip powering up of trace unit after checking for this errata
via new property called "qcom,skip-power-up".
Signed-off-by: Tingwei Zhang <tingwei@codeaurora.org>
Co-developed-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
drivers/hwtracing/coresight/coresight-etm4x.c | 27 ++++++++++++-------
drivers/hwtracing/coresight/coresight-etm4x.h | 3 +++
2 files changed, 20 insertions(+), 10 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index fb0f5f4f3a91..b38214326fa4 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -196,12 +196,14 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0);
writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1);
- /*
- * Request to keep the trace unit powered and also
- * emulation of powerdown
- */
- writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU,
- drvdata->base + TRCPDCR);
+ if (!drvdata->skip_power_up) {
+ /*
+ * Request to keep the trace unit powered and also
+ * emulation of powerdown
+ */
+ writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU,
+ drvdata->base + TRCPDCR);
+ }
/* Enable the trace unit */
writel_relaxed(1, drvdata->base + TRCPRGCTLR);
@@ -476,10 +478,12 @@ static void etm4_disable_hw(void *info)
CS_UNLOCK(drvdata->base);
- /* power can be removed from the trace unit now */
- control = readl_relaxed(drvdata->base + TRCPDCR);
- control &= ~TRCPDCR_PU;
- writel_relaxed(control, drvdata->base + TRCPDCR);
+ if (!drvdata->skip_power_up) {
+ /* power can be removed from the trace unit now */
+ control = readl_relaxed(drvdata->base + TRCPDCR);
+ control &= ~TRCPDCR_PU;
+ writel_relaxed(control, drvdata->base + TRCPDCR);
+ }
control = readl_relaxed(drvdata->base + TRCPRGCTLR);
@@ -1429,6 +1433,9 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
return -ENOMEM;
}
+ if (fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up"))
+ drvdata->skip_power_up = true;
+
/* Validity for the resource is already checked by the AMBA core */
base = devm_ioremap_resource(dev, res);
if (IS_ERR(base))
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 4a695bf90582..72c9a55e67df 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -407,6 +407,8 @@ struct etmv4_save_state {
* @config: structure holding configuration parameters.
* @save_state: State to be preserved across power loss
* @state_needs_restore: True when there is context to restore after PM exit
+ * @skip_power_up: Indicates if an implementation can skip powering up
+ * the trace unit.
*/
struct etmv4_drvdata {
void __iomem *base;
@@ -454,6 +456,7 @@ struct etmv4_drvdata {
struct etmv4_config config;
struct etmv4_save_state *save_state;
bool state_needs_restore;
+ bool skip_power_up;
};
/* Address comparator access types */
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCHv2 0/2] coresight: etm4x: Add support to skip trace unit power up
From: Sai Prakash Ranjan @ 2020-05-14 19:57 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Mike Leach, devicetree,
Rob Herring
Cc: Stephen Boyd, Leo Yan, linux-arm-kernel, linux-kernel,
linux-arm-msm, Tingwei Zhang, coresight, Sai Prakash Ranjan
This series adds support to skip powering up of trace unit on systems
with an errata which stops CPU watchdog counter when power up bit is
set (TRCPDCR.PU = 1). Setting this bit is not required on Qualcomm
Technologies Inc. chipsets where this errata exists since the ETMs
are in the same power domain as their respective CPU cores.
Tingwei Zhang (2):
coresight: etm4x: Add support to skip trace unit power up
dt-bindings: arm: coresight: Add support to skip trace unit power up
.../devicetree/bindings/arm/coresight.txt | 7 +++++
drivers/hwtracing/coresight/coresight-etm4x.c | 27 ++++++++++++-------
drivers/hwtracing/coresight/coresight-etm4x.h | 3 +++
3 files changed, 27 insertions(+), 10 deletions(-)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply
* Re: [PATCH v3 00/15] mediatek: add support for MediaTek Ethernet MAC
From: David Miller @ 2020-05-14 19:56 UTC (permalink / raw)
To: brgl
Cc: corbet, robh+dt, matthias.bgg, john, sean.wang, Mark-MC.Lee, kuba,
arnd, fparent, hkallweit1, edwin.peer, devicetree, linux-kernel,
netdev, linux-arm-kernel, linux-mediatek, stephane.leprovost,
pedro.tsai, andrew.perepech, bgolaszewski
In-Reply-To: <20200514075942.10136-1-brgl@bgdev.pl>
From: Bartosz Golaszewski <brgl@bgdev.pl>
Date: Thu, 14 May 2020 09:59:27 +0200
> Next we do some cleanup of the mediatek ethernet drivers directory and update
> the devres documentation with existing networking devres helpers.
I don't agree with the new devres stuff.
You have to be very careful with the ordering of when you map/unmap
registers, free up anciliary resources, etc. in relationship to when
the netdev unregister happens.
Please submit this driver without these controversial devres changes,
and then you can submit and discuss those changes separately later.
Thanks.
^ permalink raw reply
* Re: [PATCH v2 1/4] dt-bindings: clk: Add Baikal-T1 CCU PLLs binding
From: Serge Semin @ 2020-05-14 19:54 UTC (permalink / raw)
To: Rob Herring
Cc: Serge Semin, Thomas Bogendoerfer, Stephen Boyd, Michael Turquette,
Alexey Malahov, Paul Burton, Ralf Baechle, Arnd Bergmann,
linux-mips, linux-clk, devicetree, linux-kernel
In-Reply-To: <20200514191318.GA10192@bogus>
On Thu, May 14, 2020 at 02:13:18PM -0500, Rob Herring wrote:
> On Thu, May 07, 2020 at 01:22:57AM +0300, Serge Semin wrote:
> > Baikal-T1 Clocks Control Unit is responsible for transformation of a
> > signal coming from an external oscillator into clocks of various
> > frequencies to propagate them then to the corresponding clocks
> > consumers (either individual IP-blocks or clock domains). In order
> > to create a set of high-frequency clocks the external signal is
> > firstly handled by the embedded into CCU PLLs. So the corresponding
> > dts-node is just a normal clock-provider node with standard set of
> > properties. Note as being part of the Baikal-T1 System Controller its
> > DT node is supposed to be a child the system controller node.
> >
> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > Cc: Paul Burton <paulburton@kernel.org>
> > Cc: Ralf Baechle <ralf@linux-mips.org>
> > Cc: Arnd Bergmann <arnd@arndb.de>
> > Cc: linux-mips@vger.kernel.org
> >
> > ---
> >
> > Changelog v2:
> > - Rearrange the SoBs.
> > - Discard comments in the bindings file header.
> > - Add dual GPL/BSD license.
> > - Add spaces around the ASCII-graphics in the binding description.
> > - Remove reference to Documentation/devicetree/bindings/clock/clock-bindings.txt
> > file.
> > - Discard redundant object check against "/schemas/clock/clock.yaml#" schema.
> > - Discard redundant descriptions of the "#clock-cells" property.
> > - Remove "reg" property since from now the clock DT node is supposed to be
> > a child of the syscon-compatible system controller node.
> > - Remove "clock-output-names" property support.
> > - Replace "additionalProperties: false" with "unevaluatedProperties: false".
> > - Lowercase the nodes name in the examples.
> > - Use "clock-controller" node name suffix in the examples.
> > - Remove unnecessary comments in the clocks dt-bindings header file.
> > ---
> > .../bindings/clock/baikal,bt1-ccu-pll.yaml | 127 ++++++++++++++++++
> > include/dt-bindings/clock/bt1-ccu.h | 16 +++
> > 2 files changed, 143 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml
> > create mode 100644 include/dt-bindings/clock/bt1-ccu.h
> >
> > diff --git a/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml b/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml
> > new file mode 100644
> > index 000000000000..571181758ef2
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml
> > @@ -0,0 +1,127 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Baikal-T1 Clock Control Unit PLL
> > +
> > +maintainers:
> > + - Serge Semin <fancer.lancer@gmail.com>
> > +
> > +description: |
> > + Clocks Control Unit is the core of Baikal-T1 SoC System Controller
> > + responsible for the chip subsystems clocking and resetting. The CCU is
> > + connected with an external fixed rate oscillator, which signal is transformed
> > + into clocks of various frequencies and then propagated to either individual
> > + IP-blocks or to groups of blocks (clock domains). The transformation is done
> > + by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
> > + It's logically divided into the next components:
> > + 1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
> > + in general can provide any frequency supported by the CCU PLLs).
> > + 2) PLLs clocks generators (PLLs) - described in this binding file.
> > + 3) AXI-bus clock dividers (AXI).
> > + 4) System devices reference clock dividers (SYS).
> > + which are connected with each other as shown on the next figure:
> > +
> > + +---------------+
> > + | Baikal-T1 CCU |
> > + | +----+------|- MIPS P5600 cores
> > + | +-|PLLs|------|- DDR controller
> > + | | +----+ |
> > + +----+ | | | | |
> > + |XTAL|--|-+ | | +---+-|
> > + +----+ | | | +-|AXI|-|- AXI-bus
> > + | | | +---+-|
> > + | | | |
> > + | | +----+---+-|- APB-bus
> > + | +-------|SYS|-|- Low-speed Devices
> > + | +---+-|- High-speed Devices
> > + +---------------+
>
> Are you going to just duplicate all this for each sub-block?
Apparently yes. Since the bindings are placed in different files it would be
good to have the CCU diagram in each of them so the user would see what part of
CCU this binding describes without need to open the other file. Additionally
they don't completely match. Here I signify that the binding file is about PLLs.
The text in another file says that its about the clock dividers.
>
> > +
> > + Each CCU sub-block is represented as a separate dts-node and has an
> > + individual driver to be bound with.
> > +
> > + In order to create signals of wide range frequencies the external oscillator
> > + output is primarily connected to a set of CCU PLLs. There are five PLLs
> > + to create a clock for the MIPS P5600 cores, the embedded DDR controller,
> > + SATA, Ethernet and PCIe domains. The last three domains though named by the
> > + biggest system interfaces in fact include nearly all of the rest SoC
> > + peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core
> > + with an interface wrapper (so called safe PLL' clocks switcher) to simplify
> > + the PLL configuration procedure. The PLLs work as depicted on the next
> > + diagram:
> > +
> > + +--------------------------+
> > + | |
> > + +-->+---+ +---+ +---+ | +---+ 0|\
> > + CLKF--->|/NF|--->|PFD|...|VCO|-+->|/OD|--->| |
> > + +---+ +->+---+ +---+ /->+---+ | |--->CLKOUT
> > + CLKOD---------C----------------+ 1| |
> > + +--------C--------------------------->|/
> > + | | ^
> > + Rclk-+->+---+ | |
> > + CLKR--->|/NR|-+ |
> > + +---+ |
> > + BYPASS--------------------------------------+
> > + BWADJ--->
> > +
> > + where Rclk is the reference clock coming from XTAL, NR - reference clock
> > + divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -
> > + output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment
> > + the binding supports the PLL dividers configuration in accordance with a
> > + requested rate, while bypassing and bandwidth adjustment settings can be
> > + added in future if it gets to be necessary.
> > +
> > + The PLLs CLKOUT is then either directly connected with the corresponding
> > + clocks consumer (like P5600 cores or DDR controller) or passed over a CCU
> > + divider to create a signal required for the clock domain.
> > +
> > + The CCU PLL dts-node uses the common clock bindings with no custom
> > + parameters. The list of exported clocks can be found in
> > + 'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the
> > + Baikal-T1 SoC System Controller its DT node is supposed to be a child of
> > + later one.
>
> The schema can and should express this. IOW, either move this into the
> system controller schema or reference this ($ref) from it.
Ok. I'll make use of $ref approach because otherwise the system controller DT
binding would be overwhelmed with various properties.
>
> > +
> > +properties:
> > + compatible:
> > + const: baikal,bt1-ccu-pll
> > +
> > + "#clock-cells":
> > + const: 1
> > +
> > + clocks:
> > + description: External reference clock
> > + maxItems: 1
> > +
> > + clock-names:
> > + const: ref_clk
> > +
> > +unevaluatedProperties: false
> > +
> > +required:
> > + - compatible
> > + - "#clock-cells"
> > + - clocks
> > + - clock-names
> > +
> > +examples:
> > + # Clock Control Unit PLL node:
> > + - |
> > + clock-controller-pll {
> > + compatible = "baikal,bt1-ccu-pll";
> > + #clock-cells = <1>;
> > +
> > + clocks = <&clk25m>;
> > + clock-names = "ref_clk";
>
> If there's a register range within the system controller for the pll,
> then add 'reg' even if Linux doesn't use it.
Yes, there is. Shall I add the optional reg property to the binding too and use
the reg value in the unit-name like clock-controller@1F04D000?
-Sergey
>
> > + };
> > + # Required external oscillator:
> > + - |
> > + clk25m: clock-oscillator-25m {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <25000000>;
> > + clock-output-names = "clk25m";
> > + };
> > +...
> > diff --git a/include/dt-bindings/clock/bt1-ccu.h b/include/dt-bindings/clock/bt1-ccu.h
> > new file mode 100644
> > index 000000000000..931a4bea67c0
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/bt1-ccu.h
> > @@ -0,0 +1,16 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
> > + *
> > + * Baikal-T1 CCU clock indices
> > + */
> > +#ifndef __DT_BINDINGS_CLOCK_BT1_CCU_H
> > +#define __DT_BINDINGS_CLOCK_BT1_CCU_H
> > +
> > +#define CCU_CPU_PLL 0
> > +#define CCU_SATA_PLL 1
> > +#define CCU_DDR_PLL 2
> > +#define CCU_PCIE_PLL 3
> > +#define CCU_ETH_PLL 4
> > +
> > +#endif /* __DT_BINDINGS_CLOCK_BT1_CCU_H */
> > --
> > 2.25.1
> >
^ permalink raw reply
* Re: [PATCH net-next 1/2] dt-bindings: net: dp83822: Add TI dp83822 phy
From: Dan Murphy @ 2020-05-14 19:38 UTC (permalink / raw)
To: Andrew Lunn
Cc: f.fainelli, hkallweit1, davem, robh, netdev, linux-kernel,
devicetree, Rob Herring
In-Reply-To: <20200514183912.GW499265@lunn.ch>
Andrew
On 5/14/20 1:39 PM, Andrew Lunn wrote:
> On Thu, May 14, 2020 at 12:30:54PM -0500, Dan Murphy wrote:
>> Add a dt binding for the TI dp83822 ethernet phy device.
>>
>> CC: Rob Herring <robh+dt@kernel.org>
>> Signed-off-by: Dan Murphy <dmurphy@ti.com>
>> ---
>> .../devicetree/bindings/net/ti,dp83822.yaml | 49 +++++++++++++++++++
>> 1 file changed, 49 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/net/ti,dp83822.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/net/ti,dp83822.yaml b/Documentation/devicetree/bindings/net/ti,dp83822.yaml
>> new file mode 100644
>> index 000000000000..60afd43ad3b6
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/net/ti,dp83822.yaml
>> @@ -0,0 +1,49 @@
>> +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
>> +# Copyright (C) 2020 Texas Instruments Incorporated
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/net/ti,dp83822.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>> +
>> +title: TI DP83822 ethernet PHY
>> +
>> +allOf:
>> + - $ref: "ethernet-controller.yaml#"
>> +
>> +maintainers:
>> + - Dan Murphy <dmurphy@ti.com>
>> +
>> +description: |
>> + The DP83822 is a low-power, single-port, 10/100 Mbps Ethernet PHY. It
>> + provides all of the physical layer functions needed to transmit and receive
>> + data over standard, twisted-pair cables or to connect to an external,
>> + fiber-optic transceiver. Additionally, the DP83822 provides flexibility to
>> + connect to a MAC through a standard MII, RMII, or RGMII interface
> Hi Dan
>
> You say 10/100 Mbps Ethernet PHY, but then list RGMII?
Copied from the data sheet.
>
>> +
>> + Specifications about the charger can be found at:
>> + http://www.ti.com/lit/ds/symlink/dp83822i.pdf
>> +
>> +properties:
>> + reg:
>> + maxItems: 1
>> +
>> + ti,signal-polarity-low:
>> + type: boolean
>> + description: |
>> + DP83822 PHY in Fiber mode only.
>> + Sets the DP83822 to detect a link drop condition when the signal goes
>> + high. If not set then link drop will occur when the signal goes low.
> Are we talking about the LOS line from the SFP cage? In the SFF/SFP
> binding we have:
>
> - los-gpios : GPIO phandle and a specifier of the Receiver Loss of Signal
> Indication input gpio signal, active (signal lost) high
>
> It would be nice to have a consistent naming.
> Is it required the LOS signal is connected to the PHY? Russell King
> has some patches which allows the Marvell PHY to be used as a media
> converter. In that setting, i think the SFP signals are connected to
> GPIOs not the PHY. The SFP core can then control the transmit disable,
> module insertion detection etc. So i'm wondering if you need a
> property to indicate the LOS is not connected to the PHY?
The LED_1 pin can be strapped to be an input to the chip for signal loss
detection. This is an optional feature of the PHY.
This property defines the polarity for the 822 LED_1/GPIO input pin.
The LOS is not required to be connected to the PHY. If the preferred
method is to use the SFP framework and Processor GPIOs then I can remove
this from the patch set.
And if a user would like to use the feature then they can add it.
Dan
>
> Andrew
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox