* Re: [PATCH v3 19/20] dt-bindings: mali-midgard: Allow dma-coherent
From: Rob Herring @ 2020-05-15 3:16 UTC (permalink / raw)
To: Andre Przywara
Cc: Sudeep Holla, Liviu Dudau, linux-arm-kernel, Lorenzo Pieralisi,
devicetree, dri-devel, David Airlie, Mark Rutland
In-Reply-To: <20200513103016.130417-20-andre.przywara@arm.com>
On Wed, 13 May 2020 11:30:15 +0100, Andre Przywara wrote:
> Add the boolean dma-coherent property to the list of allowed properties,
> since some boards (Arm Juno) integrate the GPU this way.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH v3 01/20] dt-bindings: arm: gic: Allow combining arm, gic-400 compatible strings
From: Rob Herring @ 2020-05-15 3:16 UTC (permalink / raw)
To: Andre Przywara
Cc: Lorenzo Pieralisi, linux-arm-kernel, devicetree, Marc Zyngier,
Liviu Dudau, Mark Rutland, Sudeep Holla
In-Reply-To: <20200513103016.130417-2-andre.przywara@arm.com>
On Wed, 13 May 2020 11:29:57 +0100, Andre Przywara wrote:
> The arm,gic-400 compatible is probably the best matching string for the
> GIC in most modern SoCs, but was only introduced later into the kernel.
> For historic reasons and to keep compatibility, some SoC DTs were thus
> using a combination of this name and one of the older strings, which
> currently the binding denies.
>
> Add a stanza to the DT binding to allow "arm,gic-400", followed by
> either "arm,cortex-a15-gic" or "arm,cortex-a7-gic". This fixes binding
> compliance for quite some SoC .dtsi files in the kernel tree.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> .../devicetree/bindings/interrupt-controller/arm,gic.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH v2 2/3] dt-bindings: power: reset: Unrequire regmap property in syscon-reboot node
From: Rob Herring @ 2020-05-15 3:14 UTC (permalink / raw)
To: Serge Semin
Cc: Ralf Baechle, linux-mips, Allison Randal, Kate Stewart,
Sebastian Reichel, Thomas Bogendoerfer, linux-kernel,
Krzysztof Kozlowski, Jonathan Cameron, Arnd Bergmann,
Alexandre Belloni, Paul Burton, linux-pm, devicetree,
Richard Fontana, Thomas Gleixner, Rob Herring, Serge Semin,
Alexey Malahov
In-Reply-To: <20200507233846.11548-3-Sergey.Semin@baikalelectronics.ru>
On Fri, 8 May 2020 02:38:45 +0300, Serge Semin wrote:
> Since normally syscon-reboot block is supposed to be a part of a system
> controller, lets mark the regmap property as deprecated and recommend the
> syscon-reboot node to be a sub-node of SYSCON.
>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Richard Fontana <rfontana@redhat.com>
> Cc: Kate Stewart <kstewart@linuxfoundation.org>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: linux-mips@vger.kernel.org
>
> ---
>
> Changelog v2:
> - This is a new patch created as a result of the discussion:
> https://lore.kernel.org/linux-pm/20200306130402.1F4F0803079F@mail.baikalelectronics.ru/
> ---
> .../bindings/power/reset/syscon-reboot.yaml | 15 ++++++++++-----
> 1 file changed, 10 insertions(+), 5 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 2/4] dt-bindings: bus: Add Baikal-T1 APB-bus binding
From: Rob Herring @ 2020-05-15 3:13 UTC (permalink / raw)
To: Serge Semin
Cc: Paul Burton, soc, Alexey Malahov, Linus Walleij, Ralf Baechle,
linux-kernel, Jeffrey Hugo, linux-mips, Serge Semin, Tero Kristo,
Arnd Bergmann, Greg Kroah-Hartman, Thomas Bogendoerfer,
Manivannan Sadhasivam, Olof Johansson, devicetree, Tony Lindgren,
Rob Herring
In-Reply-To: <20200507224116.1523-3-Sergey.Semin@baikalelectronics.ru>
On Fri, 8 May 2020 01:41:14 +0300, Serge Semin wrote:
> Baikal-T1 CPU or DMAC MMIO requests are handled by the AMBA 3 AXI
> Interconnect which routes them to the AXI-APB bridge, which in turn
> serializes accesses and routes them to the corresponding APB slave device.
> This binding describes the AXI-APB bridge considered as the APB-bus. It is
> supposed to be compatible with "be,bt1-apb" and "simple-bus" drivers,
> should be equipped with EHB MMIO region and a region with no slave device
> mapped, interrupts line number, APB reference clock and domain reset line.
>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Tero Kristo <t-kristo@ti.com>
> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Cc: Jeffrey Hugo <jhugo@codeaurora.org>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Olof Johansson <olof@lixom.net>
> Cc: linux-mips@vger.kernel.org
> Cc: soc@kernel.org
>
> ---
>
> Rob, I had to remove your Reviewed-by tag, since new changes had been
> introduced.
>
> Changelog v2:
> - Move driver to the bus subsystem.
> - Don't use a multi-arg clock phandle reference in the examples dt-bindings
> property. Thus redundant include statement can be removed.
> - Use dual GPL/BSD license.
> - Use single lined copyright header.
> - Lowercase the unit-address.
> - Convert a dedicated EHB block binding to the Baikal-T1 APB-bus one.
> - Add APB reference clock and reset support.
> - Replace "additionalProperties: false" property with
> "unevaluatedProperties: false".
> - Add reg-names property.
> ---
> .../bindings/bus/baikal,bt1-apb.yaml | 90 +++++++++++++++++++
> 1 file changed, 90 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/bus/baikal,bt1-apb.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 1/4] dt-bindings: bus: Add Baikal-T1 AXI-bus binding
From: Rob Herring @ 2020-05-15 3:13 UTC (permalink / raw)
To: Serge Semin
Cc: Manivannan Sadhasivam, Serge Semin, Olof Johansson, Ralf Baechle,
Alexey Malahov, devicetree, Tony Lindgren, Tero Kristo,
Arnd Bergmann, Jeffrey Hugo, Greg Kroah-Hartman, Paul Burton,
linux-kernel, Thomas Bogendoerfer, linux-mips, Rob Herring, soc,
Linus Walleij
In-Reply-To: <20200507224116.1523-2-Sergey.Semin@baikalelectronics.ru>
On Fri, 8 May 2020 01:41:13 +0300, Serge Semin wrote:
> AXI3-bus is the main communication bus connecting all high-speed
> peripheral IP-cores with RAM controller and with MIPS P5600 cores on
> Baikal-T1 SoC. This binding describes the DW AMBA 3 AXI Inteconnect
> and Errors Handler Block synthesized on top of it, which are
> responsible for the AXI-bus traffic arbitration and errors reporting
> upstream to CPU. Baikal-T1 AXI-bus DT node is supposed to be compatible
> with "be,bt1-axi" and "simple-bus" drivers, should have reg property with
> AXI-bus QOS registers space, syscon phandle reference to the Baikal-T1
> System Controller, IRQ line declared, AXI Interconnect reference clock and
> reset line.
>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Tero Kristo <t-kristo@ti.com>
> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> Cc: Jeffrey Hugo <jhugo@codeaurora.org>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Olof Johansson <olof@lixom.net>
> Cc: linux-mips@vger.kernel.org
> Cc: soc@kernel.org
>
> ---
>
> Rob, I had to remove your Reviewed-by tag, since new changes had been
> introduced.
>
> Changelog v2:
> - Move driver to the bus subsystem.
> - Use dual GPL/BSD license.
> - Use single lined copyright header.
> - Lowercase the unit-address.
> - Convert a simple EHB block binding to the Baikal-T1 AXI-bus one with
> interconnect capabilities support.
> - Replace "additionalProperties: false" property with
> "unevaluatedProperties: false".
> - Add AXI reference clock and reset support.
> - Add syscon phandle reference to the Baikal-T1 System Controller node.
> ---
> .../bindings/bus/baikal,bt1-axi.yaml | 95 +++++++++++++++++++
> 1 file changed, 95 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/bus/baikal,bt1-axi.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [RFC 3/3] dt-bindings: usb: dwc3: Add entry for tx-fifo-resize
From: Rob Herring @ 2020-05-15 3:10 UTC (permalink / raw)
To: Wesley Cheng
Cc: agross, bjorn.andersson, balbi, gregkh, linux-arm-msm, devicetree,
linux-kernel, linux-usb, jackp
In-Reply-To: <1588888768-25315-4-git-send-email-wcheng@codeaurora.org>
On Thu, May 07, 2020 at 02:59:28PM -0700, Wesley Cheng wrote:
> Re-introduce the comment for the tx-fifo-resize setting for the DWC3
> controller.
Why?
>
> Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
> ---
> Documentation/devicetree/bindings/usb/dwc3.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
> index 9946ff9..489f5da 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> @@ -105,7 +105,7 @@ Optional properties:
> 1-16 (DWC_usb31 programming guide section 1.2.3) to
> enable periodic ESS TX threshold.
>
> - - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated.
> + - tx-fifo-resize: determines if the FIFO *has* to be reallocated.
> - snps,incr-burst-type-adjustment: Value for INCR burst type of GSBUSCFG0
> register, undefined length INCR burst type enable and INCRx type.
> When just one value, which means INCRX burst mode enabled. When
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [PATCH v2 1/2] dt-bindings: usb: Add TI tps6598x device tree binding documentation
From: Rob Herring @ 2020-05-15 3:09 UTC (permalink / raw)
To: Bryan O'Donoghue
Cc: heikki.krogerus, linux-usb, devicetree, gregkh, linux-kernel,
nikolaus.voss, andriy.shevchenko, garsilva, keescook
In-Reply-To: <20200507214733.1982696-2-bryan.odonoghue@linaro.org>
On Thu, May 07, 2020 at 10:47:32PM +0100, Bryan O'Donoghue wrote:
> Add device tree binding documentation for the Texas Instruments tps6598x
> Type-C chip driver.
>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Heikki Krogerus <heikki.krogerus@linux.intel.com>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: linux-usb@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
> .../devicetree/bindings/usb/ti,tps6598x.yaml | 64 +++++++++++++++++++
> 1 file changed, 64 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/ti,tps6598x.yaml
>
> diff --git a/Documentation/devicetree/bindings/usb/ti,tps6598x.yaml b/Documentation/devicetree/bindings/usb/ti,tps6598x.yaml
> new file mode 100644
> index 000000000000..8eaf4b6c4735
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/ti,tps6598x.yaml
> @@ -0,0 +1,64 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/usb/ti,tps6598x.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Texas Instruments 6598x Type-C Port Switch and Power Delivery controller DT bindings
> +
> +maintainers:
> + - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> +
> +description: |
> + Texas Instruments 6598x Type-C Port Switch and Power Delivery controller
> +
> +properties:
> + compatible:
> + enum:
> + - ti,tps6598x
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + interrupt-names:
> + items:
> + - const: irq
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - interrupt-names
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + i2c0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + tps6598x: tps6598x@38 {
> + compatible = "ti,tps6598x";
> + reg = <0x38>;
> +
> + interrupt-parent = <&msmgpio>;
> + interrupts = <107 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-names = "irq";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&typec_pins>;
> +
> + typec_con: connector {
> + compatible = "usb-c-connector";
> + label = "USB-C";
> + port {
The connector binding has specific numbering of the ports defined for
HS, SS, alt mode.
So you should have 'ports' here.
> + typec_ep: endpoint {
> + remote-endpoint = <&otg_ep>;
> + };
> + };
> + };
> + };
> + };
> +...
> --
> 2.25.1
>
^ permalink raw reply
* Re: [PATCH V6 3/3] dt-bindings: serial: Add binding for UART pin swap
From: Rob Herring @ 2020-05-15 3:01 UTC (permalink / raw)
To: Akash Asthana
Cc: gregkh, linux-arm-msm, devicetree, linux-kernel, mgautam, rojay,
skakit, mka
In-Reply-To: <1588863647-17240-4-git-send-email-akashast@codeaurora.org>
On Thu, May 07, 2020 at 08:30:47PM +0530, Akash Asthana wrote:
> Add documentation to support RX-TX & CTS-RTS GPIO pin swap in HW.
>
> Signed-off-by: Akash Asthana <akashast@codeaurora.org>
> ---
> Documentation/devicetree/bindings/serial/serial.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/serial/serial.yaml b/Documentation/devicetree/bindings/serial/serial.yaml
> index 53204d9..e657dd6 100644
> --- a/Documentation/devicetree/bindings/serial/serial.yaml
> +++ b/Documentation/devicetree/bindings/serial/serial.yaml
> @@ -67,6 +67,12 @@ properties:
> (wired and enabled by pinmux configuration). This depends on both the
> UART hardware and the board wiring.
>
> + rx-tx-swap:
> + description: RX and TX pins are swapped.
> +
> + cts-rts-swap:
> + description: CTS and RTS pins are swapped.
Need 'type: boolean' on both of these.
> +
> if:
> required:
> - uart-has-rtscts
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [PATCH 11/12] dt-bindings: iio: imu: Add inv_icm42600 documentation
From: Rob Herring @ 2020-05-15 3:00 UTC (permalink / raw)
To: Jean-Baptiste Maneyrol
Cc: jic23, mchehab+huawei, davem, gregkh, linux-iio, devicetree,
linux-kernel
In-Reply-To: <20200507144222.20989-12-jmaneyrol@invensense.com>
On Thu, May 07, 2020 at 04:42:21PM +0200, Jean-Baptiste Maneyrol wrote:
> Document the ICM-426xxx devices devicetree bindings.
>
> Signed-off-by: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com>
> ---
> .../bindings/iio/imu/invensense,icm42600.yaml | 90 +++++++++++++++++++
> 1 file changed, 90 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
>
> diff --git a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
> new file mode 100644
> index 000000000000..a7175f6543fa
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
> @@ -0,0 +1,90 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/imu/invensense,icm42600.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: InvenSense ICM-426xx Inertial Measurement Unit
> +
> +maintainers:
> + - Jean-Baptiste Maneyrol <jmaneyrol@invensense.com>
> +
> +description: |
> + 6-axis MotionTracking device that combines a 3-axis gyroscope and a 3-axis accelerometer.
> +
> + It has a configurable host interface that supports I3C, I2C and SPI serial communication, features a 2kB FIFO and
> + 2 programmable interrupts with ultra-low-power wake-on-motion support to minimize system power consumption.
> +
> + Other industry-leading features include InvenSense on-chip APEX Motion Processing engine for gesture recognition,
> + activity classification, and pedometer, along with programmable digital filters, and an embedded temperature sensor.
> +
> + https://invensense.tdk.com/wp-content/uploads/2020/03/DS-000292-ICM-42605-v1.4.pdf
> +
> +properties:
> + compatible:
> + enum:
> + - invensense,icm42600
> + - invensense,icm42602
> + - invensense,icm42605
> + - invensense,icm42622
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + spi-cpha: true
> +
> + spi-cpol: true
It doesn't make much sense to specify these and not make them required.
I guess you could have a device with multiple modes, but generally
there's only one right combination of these properties. Also, this could
just be implied by the compatible.
> +
> + spi-max-frequency:
> + maxItems: 1
Not an array. Either give a frequency range (minimum/maximum) or just
'true'.
> +
> + vdd-supply:
> + description: Regulator that provides power to the sensor
> +
> + vddio-supply:
> + description: Regulator that provides power to the bus
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> +
> +examples:
> + - |
> + #include <dt-bindings/gpio/gpio.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + i2c0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + icm42605@68 {
> + compatible = "invensense,icm42605";
> + reg = <0x68>;
> + interrupt-parent = <&gpio2>;
> + interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
> + vdd-supply = <&vdd>;
> + vddio-supply = <&vddio>;
> + };
> + };
> + - |
> + #include <dt-bindings/gpio/gpio.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + spi0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + icm42602@0 {
> + compatible = "invensense,icm42602";
> + reg = <0>;
> + spi-max-frequency = <24000000>;
> + spi-cpha;
> + spi-cpol;
> + interrupt-parent = <&gpio1>;
> + interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
> + vdd-supply = <&vdd>;
> + vddio-supply = <&vddio>;
> + };
> + };
> --
> 2.17.1
>
^ permalink raw reply
* [PATCH v2 2/2] media: cec: i2c: ch7322: Add ch7322 CEC controller driver
From: Jeff Chase @ 2020-05-15 2:51 UTC (permalink / raw)
To: linux-media; +Cc: mchehab, hverkuil-cisco, robh+dt, devicetree, Jeff Chase
In-Reply-To: <20200515025159.101081-1-jnchase@google.com>
Add a CEC device driver for the Chrontel ch7322 CEC conroller.
This is an I2C device capable of sending and receiving CEC messages.
Signed-off-by: Jeff Chase <jnchase@google.com>
---
MAINTAINERS | 1 +
drivers/media/cec/Kconfig | 1 +
drivers/media/cec/Makefile | 2 +-
drivers/media/cec/i2c/Kconfig | 14 +
drivers/media/cec/i2c/Makefile | 5 +
drivers/media/cec/i2c/ch7322.c | 499 +++++++++++++++++++++++++++++++++
6 files changed, 521 insertions(+), 1 deletion(-)
create mode 100644 drivers/media/cec/i2c/Kconfig
create mode 100644 drivers/media/cec/i2c/Makefile
create mode 100644 drivers/media/cec/i2c/ch7322.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 34c6d30e61e5..43e876395686 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4053,6 +4053,7 @@ L: linux-media@vger.kernel.org
S: Maintained
T: git git://linuxtv.org/media_tree.git
F: Documentation/devicetree/bindings/media/i2c/chontel,ch7322.yaml
+F: drivers/media/cec/i2c/ch7322.c
CIRRUS LOGIC AUDIO CODEC DRIVERS
M: James Schulman <james.schulman@cirrus.com>
diff --git a/drivers/media/cec/Kconfig b/drivers/media/cec/Kconfig
index eea74b7cfa8c..3e934aa239ab 100644
--- a/drivers/media/cec/Kconfig
+++ b/drivers/media/cec/Kconfig
@@ -33,6 +33,7 @@ menuconfig MEDIA_CEC_SUPPORT
adapter that supports HDMI CEC.
if MEDIA_CEC_SUPPORT
+source "drivers/media/cec/i2c/Kconfig"
source "drivers/media/cec/platform/Kconfig"
source "drivers/media/cec/usb/Kconfig"
endif
diff --git a/drivers/media/cec/Makefile b/drivers/media/cec/Makefile
index 74e80e1b3571..23539339bc81 100644
--- a/drivers/media/cec/Makefile
+++ b/drivers/media/cec/Makefile
@@ -1,2 +1,2 @@
# SPDX-License-Identifier: GPL-2.0
-obj-y += core/ platform/ usb/
+obj-y += core/ i2c/ platform/ usb/
diff --git a/drivers/media/cec/i2c/Kconfig b/drivers/media/cec/i2c/Kconfig
new file mode 100644
index 000000000000..e445ca2110b3
--- /dev/null
+++ b/drivers/media/cec/i2c/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# I2C drivers
+
+config CEC_CH7322
+ tristate "Chrontel CH7322 CEC controller"
+ select I2C
+ select REGMAP_I2C
+ select CEC_CORE
+ help
+ This is a driver for the Chrontel CH7322 CEC controller. It uses the
+ generic CEC framework interface.
+ CEC bus is present in the HDMI connector and enables communication
+ between compatible devices.
diff --git a/drivers/media/cec/i2c/Makefile b/drivers/media/cec/i2c/Makefile
new file mode 100644
index 000000000000..d7496dfd0fa4
--- /dev/null
+++ b/drivers/media/cec/i2c/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the CEC I2C device drivers.
+#
+obj-$(CONFIG_CEC_CH7322) += ch7322.o
diff --git a/drivers/media/cec/i2c/ch7322.c b/drivers/media/cec/i2c/ch7322.c
new file mode 100644
index 000000000000..40bc87ae5282
--- /dev/null
+++ b/drivers/media/cec/i2c/ch7322.c
@@ -0,0 +1,499 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for the Chrontel CH7322 CEC Controller
+ *
+ * Copyright 2020 Google LLC.
+ */
+
+/*
+ * Notes
+ *
+ * - This device powers on in Auto Mode which has limited functionality. This
+ * driver disables Auto Mode when it attaches.
+ *
+ */
+
+#include <linux/cec.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/regmap.h>
+#include <media/cec.h>
+
+#define CH7322_WRITE 0x00
+#define CH7322_WRITE_MSENT 0x80
+#define CH7322_WRITE_BOK 0x40
+#define CH7322_WRITE_NMASK 0x0F
+
+/* Write buffer is 0x01-0x10 */
+#define CH7322_WRBUF 0x01
+#define CH7322_WRBUF_LEN 0x10
+
+#define CH7322_READ 0x40
+#define CH7322_READ_NRDT 0x80
+#define CH7322_READ_MSENT 0x20
+#define CH7322_READ_NMASK 0x0F
+
+/* Read buffer is 0x41-0x50 */
+#define CH7322_RDBUF 0x41
+#define CH7322_RDBUF_LEN 0x10
+
+#define CH7322_MODE 0x11
+#define CH7322_MODE_AUTO 0x78
+#define CH7322_MODE_SW 0xB5
+
+#define CH7322_RESET 0x12
+#define CH7322_POWER 0x13
+
+#define CH7322_CFG0 0x17
+#define CH7322_CFG0_EOBEN 0x40
+#define CH7322_CFG0_PEOB 0x20
+#define CH7322_CFG0_CLRSPP 0x10
+#define CH7322_CFG0_FLOW 0x08
+
+#define CH7322_CFG1 0x1A
+#define CH7322_CFG1_STDBYO 0x04
+#define CH7322_CFG1_HPBP 0x02
+#define CH7322_CFG1_PIO 0x01
+
+#define CH7322_INTCTL 0x1B
+#define CH7322_INTCTL_INTPB 0x80
+#define CH7322_INTCTL_STDBY 0x40
+#define CH7322_INTCTL_HPDFALL 0x20
+#define CH7322_INTCTL_HPDRISE 0x10
+#define CH7322_INTCTL_RXMSG 0x08
+#define CH7322_INTCTL_TXMSG 0x04
+#define CH7322_INTCTL_NEWPHA 0x02
+#define CH7322_INTCTL_ERROR 0x01
+
+#define CH7322_DVCLKFNH 0x1D
+#define CH7322_DVCLKFNL 0x1E
+
+#define CH7322_CTL 0x31
+#define CH7322_CTL_FSTDBY 0x80
+#define CH7322_CTL_PLSEN 0x40
+#define CH7322_CTL_PLSPB 0x20
+#define CH7322_CTL_SPADL 0x10
+#define CH7322_CTL_HINIT 0x08
+#define CH7322_CTL_WPHYA 0x04
+#define CH7322_CTL_H1T 0x02
+#define CH7322_CTL_S1T 0x01
+
+#define CH7322_PAWH 0x32
+#define CH7322_PAWL 0x33
+
+#define CH7322_ADDLW 0x34
+#define CH7322_ADDLW_MASK 0xF0
+
+#define CH7322_ADDLR 0x3D
+#define CH7322_ADDLR_HPD 0x80
+#define CH7322_ADDLR_MASK 0x0F
+
+#define CH7322_INTDATA 0x3E
+#define CH7322_INTDATA_MODE 0x80
+#define CH7322_INTDATA_STDBY 0x40
+#define CH7322_INTDATA_HPDFALL 0x20
+#define CH7322_INTDATA_HPDRISE 0x10
+#define CH7322_INTDATA_RXMSG 0x08
+#define CH7322_INTDATA_TXMSG 0x04
+#define CH7322_INTDATA_NEWPHA 0x02
+#define CH7322_INTDATA_ERROR 0x01
+
+#define CH7322_EVENT 0x3F
+#define CH7322_EVENT_TXERR 0x80
+#define CH7322_EVENT_HRST 0x40
+#define CH7322_EVENT_HFST 0x20
+#define CH7322_EVENT_PHACHG 0x10
+#define CH7322_EVENT_ACTST 0x08
+#define CH7322_EVENT_PHARDY 0x04
+#define CH7322_EVENT_BSOK 0x02
+#define CH7322_EVENT_ERRADCF 0x01
+
+#define CH7322_DID 0x51
+#define CH7322_DID_CH7322 0x5B
+#define CH7322_DID_CH7323 0x5F
+
+#define CH7322_REVISIONID 0x52
+
+#define CH7322_PARH 0x53
+#define CH7322_PARL 0x54
+
+#define CH7322_IOCFG2 0x75
+#define CH7322_IOCFG_CIO 0x80
+#define CH7322_IOCFG_IOCFGMASK 0x78
+#define CH7322_IOCFG_AUDIO 0x04
+#define CH7322_IOCFG_SPAMST 0x02
+#define CH7322_IOCFG_SPAMSP 0x01
+
+#define CH7322_CTL3 0x7B
+#define CH7322_CTL3_SWENA 0x80
+#define CH7322_CTL3_FC_INIT 0x40
+#define CH7322_CTL3_SML_FL 0x20
+#define CH7322_CTL3_SM_RDST 0x10
+#define CH7322_CTL3_SPP_CIAH 0x08
+#define CH7322_CTL3_SPP_CIAL 0x04
+#define CH7322_CTL3_SPP_ACTH 0x02
+#define CH7322_CTL3_SPP_ACTL 0x01
+
+/* BOK status means NACK */
+#define CH7322_TX_FLAG_NACK BIT(0)
+/* Device will retry automatically */
+#define CH7322_TX_FLAG_RETRY BIT(1)
+
+struct ch7322 {
+ struct i2c_client *i2c;
+ struct regmap *regmap;
+ struct cec_adapter *cec;
+ struct mutex mutex; /* device access mutex */
+ u8 tx_flags;
+};
+
+static const struct regmap_config ch7322_regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = 0x7F,
+ .disable_locking = true,
+};
+
+static int ch7322_send_message(struct ch7322 *ch7322, const struct cec_msg *msg)
+{
+ unsigned int val;
+ unsigned int len = msg->len;
+ int ret;
+ int i;
+
+ WARN_ON(!mutex_is_locked(&ch7322->mutex));
+
+ if (len > CH7322_WRBUF_LEN || len < 1)
+ return -EINVAL;
+
+ ret = regmap_read(ch7322->regmap, CH7322_WRITE, &val);
+ if (ret)
+ return ret;
+
+ /* Buffer not ready */
+ if (!(val & CH7322_WRITE_MSENT))
+ return -EBUSY;
+
+ if (cec_msg_opcode(msg) == -1 &&
+ cec_msg_initiator(msg) == cec_msg_destination(msg)) {
+ ch7322->tx_flags = CH7322_TX_FLAG_NACK | CH7322_TX_FLAG_RETRY;
+ } else if (cec_msg_is_broadcast(msg)) {
+ ch7322->tx_flags = CH7322_TX_FLAG_NACK;
+ } else {
+ ch7322->tx_flags = CH7322_TX_FLAG_RETRY;
+ }
+
+ ret = regmap_write(ch7322->regmap, CH7322_WRITE, len - 1);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < len; i++) {
+ ret = regmap_write(ch7322->regmap,
+ CH7322_WRBUF + i, msg->msg[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ch7322_receive_message(struct ch7322 *ch7322, struct cec_msg *msg)
+{
+ unsigned int val;
+ int ret = 0;
+ int i;
+
+ WARN_ON(!mutex_is_locked(&ch7322->mutex));
+
+ ret = regmap_read(ch7322->regmap, CH7322_READ, &val);
+ if (ret)
+ return ret;
+
+ /* Message not ready */
+ if (!(val & CH7322_READ_NRDT))
+ return -EIO;
+
+ msg->len = (val & CH7322_READ_NMASK) + 1;
+
+ /* Read entire RDBUF to clear state */
+ for (i = 0; i < CH7322_RDBUF_LEN; i++) {
+ ret = regmap_read(ch7322->regmap, CH7322_RDBUF + i, &val);
+ if (ret)
+ return ret;
+ msg->msg[i] = (u8)val;
+ }
+
+ return 0;
+}
+
+static void ch7322_tx_done(struct ch7322 *ch7322)
+{
+ int ret;
+ unsigned int val;
+ u8 status, flags;
+
+ mutex_lock(&ch7322->mutex);
+ ret = regmap_read(ch7322->regmap, CH7322_WRITE, &val);
+ flags = ch7322->tx_flags;
+ mutex_unlock(&ch7322->mutex);
+
+ /*
+ * The device returns a one-bit OK status which usually means ACK but
+ * actually means NACK when sending a logical address query or a
+ * broadcast.
+ */
+ if (ret)
+ status = CEC_TX_STATUS_ERROR;
+ else if ((val & CH7322_WRITE_BOK) && (flags & CH7322_TX_FLAG_NACK))
+ status = CEC_TX_STATUS_NACK;
+ else if (val & CH7322_WRITE_BOK)
+ status = CEC_TX_STATUS_OK;
+ else if (flags & CH7322_TX_FLAG_NACK)
+ status = CEC_TX_STATUS_OK;
+ else
+ status = CEC_TX_STATUS_NACK;
+
+ if (status == CEC_TX_STATUS_NACK && (flags & CH7322_TX_FLAG_RETRY))
+ status |= CEC_TX_STATUS_MAX_RETRIES;
+
+ cec_transmit_attempt_done(ch7322->cec, status);
+}
+
+static void ch7322_rx_done(struct ch7322 *ch7322)
+{
+ struct cec_msg msg;
+ int ret;
+
+ mutex_lock(&ch7322->mutex);
+ ret = ch7322_receive_message(ch7322, &msg);
+ mutex_unlock(&ch7322->mutex);
+
+ if (ret)
+ dev_err(&ch7322->i2c->dev, "cec receive error: %d\n", ret);
+ else
+ cec_received_msg(ch7322->cec, &msg);
+}
+
+/*
+ * This device can either monitor the DDC lines to obtain the physical address
+ * or it can allow the host to program it. This driver lets the device obtain
+ * it.
+ */
+static void ch7322_phys_addr(struct ch7322 *ch7322)
+{
+ unsigned int pah, pal;
+ int ret = 0;
+
+ mutex_lock(&ch7322->mutex);
+ ret |= regmap_read(ch7322->regmap, CH7322_PARH, &pah);
+ ret |= regmap_read(ch7322->regmap, CH7322_PARL, &pal);
+ mutex_unlock(&ch7322->mutex);
+
+ if (ret)
+ dev_err(&ch7322->i2c->dev, "phys addr error\n");
+ else
+ cec_s_phys_addr(ch7322->cec, pal | (pah << 8), false);
+}
+
+static void ch7322_handle_events(struct ch7322 *ch7322)
+{
+ unsigned int data = 0;
+
+ mutex_lock(&ch7322->mutex);
+ regmap_read(ch7322->regmap, CH7322_INTDATA, &data);
+ regmap_write(ch7322->regmap, CH7322_INTDATA, data);
+ mutex_unlock(&ch7322->mutex);
+
+ if (data & CH7322_INTDATA_HPDFALL)
+ cec_phys_addr_invalidate(ch7322->cec);
+
+ if (data & CH7322_INTDATA_TXMSG)
+ ch7322_tx_done(ch7322);
+
+ if (data & CH7322_INTDATA_RXMSG)
+ ch7322_rx_done(ch7322);
+
+ if (data & CH7322_INTDATA_NEWPHA)
+ ch7322_phys_addr(ch7322);
+
+ if (data & CH7322_INTDATA_ERROR)
+ dev_dbg(&ch7322->i2c->dev, "unknown error\n");
+}
+
+static irqreturn_t ch7322_irq(int irq, void *dev)
+{
+ struct ch7322 *ch7322 = dev;
+
+ ch7322_handle_events(ch7322);
+
+ return IRQ_HANDLED;
+}
+
+/* This device is always enabled */
+static int ch7322_cec_adap_enable(struct cec_adapter *adap, bool enable)
+{
+ return 0;
+}
+
+static int ch7322_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
+{
+ struct ch7322 *ch7322 = cec_get_drvdata(adap);
+ int ret;
+
+ mutex_lock(&ch7322->mutex);
+ ret = regmap_update_bits(ch7322->regmap, CH7322_ADDLW,
+ CH7322_ADDLW_MASK, log_addr << 4);
+ mutex_unlock(&ch7322->mutex);
+
+ return ret;
+}
+
+static int ch7322_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
+ u32 signal_free_time, struct cec_msg *msg)
+{
+ struct ch7322 *ch7322 = cec_get_drvdata(adap);
+ int ret;
+
+ mutex_lock(&ch7322->mutex);
+ ret = ch7322_send_message(ch7322, msg);
+ mutex_unlock(&ch7322->mutex);
+
+ return ret;
+}
+
+static const struct cec_adap_ops ch7322_cec_adap_ops = {
+ .adap_enable = ch7322_cec_adap_enable,
+ .adap_log_addr = ch7322_cec_adap_log_addr,
+ .adap_transmit = ch7322_cec_adap_transmit,
+};
+
+static int ch7322_probe(struct i2c_client *client)
+{
+ struct ch7322 *ch7322;
+ int ret;
+ unsigned int val;
+
+ ch7322 = devm_kzalloc(&client->dev, sizeof(*ch7322), GFP_KERNEL);
+ if (!ch7322)
+ return -ENOMEM;
+
+ ch7322->regmap = devm_regmap_init_i2c(client, &ch7322_regmap);
+ if (IS_ERR(ch7322->regmap))
+ return PTR_ERR(ch7322->regmap);
+
+ ret = regmap_read(ch7322->regmap, CH7322_DID, &val);
+ if (ret)
+ return ret;
+
+ if (val != CH7322_DID_CH7322)
+ return -ENOTSUPP;
+
+ mutex_init(&ch7322->mutex);
+ ch7322->i2c = client;
+ ch7322->tx_flags = 0;
+
+ i2c_set_clientdata(client, ch7322);
+
+ /* Disable auto mode */
+ ret = regmap_write(ch7322->regmap, CH7322_MODE, CH7322_MODE_SW);
+ if (ret)
+ goto err_mutex;
+
+ /* Enable logical address register */
+ ret = regmap_update_bits(ch7322->regmap, CH7322_CTL,
+ CH7322_CTL_SPADL, CH7322_CTL_SPADL);
+ if (ret)
+ goto err_mutex;
+
+ ch7322->cec = cec_allocate_adapter(&ch7322_cec_adap_ops, ch7322,
+ dev_name(&client->dev),
+ CEC_CAP_DEFAULTS, 1);
+
+ if (IS_ERR(ch7322->cec)) {
+ ret = PTR_ERR(ch7322->cec);
+ goto err_mutex;
+ }
+
+ ret = cec_register_adapter(ch7322->cec, &client->dev);
+ if (ret) {
+ cec_delete_adapter(ch7322->cec);
+ goto err_mutex;
+ }
+
+ /* Configure and mask interrupt */
+ ret = regmap_write(ch7322->regmap, CH7322_CFG1, 0);
+ if (ret)
+ goto err_cec;
+
+ ret = regmap_write(ch7322->regmap, CH7322_INTCTL, CH7322_INTCTL_INTPB);
+ if (ret)
+ goto err_cec;
+
+ ret = devm_request_threaded_irq(&client->dev, client->irq, NULL,
+ ch7322_irq,
+ IRQF_ONESHOT | IRQF_TRIGGER_RISING,
+ client->name, ch7322);
+ if (ret)
+ goto err_cec;
+
+ ch7322_handle_events(ch7322);
+
+ /* Unmask interrupt */
+ mutex_lock(&ch7322->mutex);
+ ret = regmap_write(ch7322->regmap, CH7322_INTCTL, 0xff);
+ mutex_unlock(&ch7322->mutex);
+
+ if (ret)
+ goto err_cec;
+
+ dev_info(&client->dev, "device registered\n");
+
+ return 0;
+
+err_cec:
+ cec_unregister_adapter(ch7322->cec);
+
+err_mutex:
+ mutex_destroy(&ch7322->mutex);
+ return ret;
+}
+
+static int ch7322_remove(struct i2c_client *client)
+{
+ struct ch7322 *ch7322 = i2c_get_clientdata(client);
+
+ /* Mask interrupt */
+ mutex_lock(&ch7322->mutex);
+ regmap_write(ch7322->regmap, CH7322_INTCTL, CH7322_INTCTL_INTPB);
+ mutex_unlock(&ch7322->mutex);
+
+ cec_unregister_adapter(ch7322->cec);
+ mutex_destroy(&ch7322->mutex);
+
+ dev_info(&client->dev, "device unregistered\n");
+
+ return 0;
+}
+
+static const struct of_device_id ch7322_of_match[] = {
+ { .compatible = "chrontel,ch7322", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ch7322_of_match);
+
+static struct i2c_driver ch7322_i2c_driver = {
+ .driver = {
+ .name = "ch7322",
+ .of_match_table = of_match_ptr(ch7322_of_match),
+ },
+ .probe_new = ch7322_probe,
+ .remove = ch7322_remove,
+};
+
+module_i2c_driver(ch7322_i2c_driver);
+
+MODULE_DESCRIPTION("Chrontel CH7322 CEC Controller Driver");
+MODULE_AUTHOR("Jeff Chase <jnchase@google.com>");
+MODULE_LICENSE("GPL");
--
2.26.2.761.g0e0b3e54be-goog
^ permalink raw reply related
* [PATCH v2 1/2] dt-bindings: Add ch7322 media i2c device
From: Jeff Chase @ 2020-05-15 2:51 UTC (permalink / raw)
To: linux-media; +Cc: mchehab, hverkuil-cisco, robh+dt, devicetree, Jeff Chase
In-Reply-To: <20200515025159.101081-1-jnchase@google.com>
The ch7322 is a Chrontel CEC controller.
Signed-off-by: Jeff Chase <jnchase@google.com>
---
.../bindings/media/i2c/chrontel,ch7322.yaml | 65 +++++++++++++++++++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 7 ++
3 files changed, 74 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/i2c/chrontel,ch7322.yaml
diff --git a/Documentation/devicetree/bindings/media/i2c/chrontel,ch7322.yaml b/Documentation/devicetree/bindings/media/i2c/chrontel,ch7322.yaml
new file mode 100644
index 000000000000..d78e355e411a
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/chrontel,ch7322.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/media/i2c/ch7322.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Chrontel HDMI-CEC Controller
+
+maintainers:
+ - Jeff Chase <jnchase@google.com>
+
+description: |-
+ The Chrontel CH7322 is a discrete HDMI-CEC controller. It is
+ programmable through I2C and drives a single CEC line.
+
+properties:
+ compatible:
+ const: chrontel,ch7322
+
+ reg:
+ description: I2C device address
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ reset-gpios:
+ description: |-
+ Reference to the GPIO connected to the RESET pin, if any. This
+ pin is active-low.
+
+ standby-gpios:
+ description: |-
+ Reference to the GPIO connected to the OE pin, if any. When low
+ the device will respond to power status requests with "standby"
+ if in auto mode.
+
+ # see ../cec.txt
+ hdmi-phandle:
+ description: phandle to the HDMI controller
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ch7322@75 {
+ compatible = "chrontel,ch7322";
+ reg = <0x75>;
+ interrupts = <47 IRQ_TYPE_EDGE_RISING>;
+ standby-gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+ hdmi-phandle = <&hdmi>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index d3891386d671..7794ffccd325 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -187,6 +187,8 @@ patternProperties:
description: ChipOne
"^chipspark,.*":
description: ChipSPARK
+ "^chrontel,.*":
+ description: Chrontel, Inc.
"^chrp,.*":
description: Common Hardware Reference Platform
"^chunghwa,.*":
diff --git a/MAINTAINERS b/MAINTAINERS
index d633a131dcd7..34c6d30e61e5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4047,6 +4047,13 @@ F: drivers/power/supply/cros_usbpd-charger.c
N: cros_ec
N: cros-ec
+CHRONTEL CH7322 CEC DRIVER
+M: Jeff Chase <jnchase@google.com>
+L: linux-media@vger.kernel.org
+S: Maintained
+T: git git://linuxtv.org/media_tree.git
+F: Documentation/devicetree/bindings/media/i2c/chontel,ch7322.yaml
+
CIRRUS LOGIC AUDIO CODEC DRIVERS
M: James Schulman <james.schulman@cirrus.com>
M: David Rhodes <david.rhodes@cirrus.com>
--
2.26.2.761.g0e0b3e54be-goog
^ permalink raw reply related
* [PATCH v2 0/2] CH7322 CEC controller driver
From: Jeff Chase @ 2020-05-15 2:51 UTC (permalink / raw)
To: linux-media; +Cc: mchehab, hverkuil-cisco, robh+dt, devicetree, Jeff Chase
Add device driver and device tree bindings for a Chrontel CEC
conroller. This is an I2C device that can send and receive CEC
messages.
Changes from v1:
- fix formatpatch.pl --strict errors
- additional comments
- enable and program logical address register
- add flags to aid interpreting transmit done status
- move ch7322 out of devicetree trivial devices
Jeff Chase (2):
dt-bindings: Add ch7322 media i2c device
media: cec: i2c: ch7322: Add ch7322 CEC controller driver
.../bindings/media/i2c/chrontel,ch7322.yaml | 65 +++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 8 +
drivers/media/cec/Kconfig | 1 +
drivers/media/cec/Makefile | 2 +-
drivers/media/cec/i2c/Kconfig | 14 +
drivers/media/cec/i2c/Makefile | 5 +
drivers/media/cec/i2c/ch7322.c | 501 ++++++++++++++++++
8 files changed, 597 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/media/i2c/chrontel,ch7322.yaml
create mode 100644 drivers/media/cec/i2c/Kconfig
create mode 100644 drivers/media/cec/i2c/Makefile
create mode 100644 drivers/media/cec/i2c/ch7322.c
--
2.26.2.761.g0e0b3e54be-goog
^ permalink raw reply
* Re: [PATCH V1 1/7] dt-bindings: mmc: Add information for DLL register properties
From: Rob Herring @ 2020-05-15 2:50 UTC (permalink / raw)
To: Sarthak Garg
Cc: adrian.hunter, ulf.hansson, vbadigan, stummala, linux-mmc,
linux-kernel, linux-arm-msm,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
In-Reply-To: <1588838535-6050-2-git-send-email-sartgarg@codeaurora.org>
On Thu, May 07, 2020 at 01:32:08PM +0530, Sarthak Garg wrote:
> Add information regarding DLL register properties for getting target
> specific configurations. These DLL register settings may vary from
> target to target.
>
> Also new compatible string value for sm8250 target.
>
> Signed-off-by: Sarthak Garg <sartgarg@codeaurora.org>
> ---
> Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
> index 5445931..b8e1d2b 100644
> --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
> +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
> @@ -17,6 +17,7 @@ Required properties:
> "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
> "qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
> "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"
> + "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"
> "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"
> "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"
> "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
> @@ -46,6 +47,13 @@ Required properties:
> "cal" - reference clock for RCLK delay calibration (optional)
> "sleep" - sleep clock for RCLK delay calibration (optional)
>
> +- qcom,ddr-config: Certain chipsets and platforms require particular settings
> + for the DDR_CONFIG register. Use this field to specify the register
> + value as per the Hardware Programming Guide.
> +
> +- qcom,dll-config: Chipset and Platform specific value. Use this field to
> + specify the DLL_CONFIG register value as per Hardware Programming Guide.
Board specific or SoC specific? If the latter, imply this from the
compatible string.
^ permalink raw reply
* Re: [PATCH v3] dt-bindings: irqchip: renesas-intc-irqpin: Convert to json-schema
From: Rob Herring @ 2020-05-15 2:46 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Thomas Gleixner, Yoshihiro Kaneko, linux-renesas-soc,
linux-kernel, Rob Herring, devicetree, Marc Zyngier, Jason Cooper
In-Reply-To: <20200507075503.32291-1-geert+renesas@glider.be>
On Thu, 7 May 2020 09:55:03 +0200, Geert Uytterhoeven wrote:
> From: Yoshihiro Kaneko <ykaneko0929@gmail.com>
>
> Convert the Renesas Interrupt Controller (INTC) for external pins Device
> Tree binding documentation to json-schema.
>
> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
> Co-developed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> v3:
> - Take over from Kaneko-san,
> - Update license,
> - Fix title,
> - Remove standard descriptions,
> - reg: fix minItems, add descriptions,
> - interrupts: fix {min,max}Items,
> - sense-bitfield-width: add enum and default, use description,
> - control-parent: use description,
> - Make clocks and power-domains required on SH/R-Mobile,
> - Group interrupts in example,
>
> v2:
> - Correct Geert-san's E-mail address,
> - Delete Guennadi-san from the maintainer of this binding,
> - Give 'sense-bitfield-width' the uint32 type,
> - Describe 'control-parent' property as a boolean.
> ---
> .../renesas,intc-irqpin.txt | 62 ----------
> .../renesas,intc-irqpin.yaml | 108 ++++++++++++++++++
> 2 files changed, 108 insertions(+), 62 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.txt
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH v3] dt-bindings: irqchip: renesas-intc-irqpin: Convert to json-schema
From: Rob Herring @ 2020-05-15 2:46 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Thomas Gleixner, Jason Cooper, Marc Zyngier, Yoshihiro Kaneko,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux-Renesas, Linux Kernel Mailing List, Geert Uytterhoeven
In-Reply-To: <CAMuHMdVyFW-oWsDsOAC+H4f3oQZpwH=dPQHy3djgHnEJ-81+ug@mail.gmail.com>
On Wed, May 13, 2020 at 03:42:35PM +0200, Geert Uytterhoeven wrote:
> On Thu, May 7, 2020 at 9:55 AM Geert Uytterhoeven
> <geert+renesas@glider.be> wrote:
> > From: Yoshihiro Kaneko <ykaneko0929@gmail.com>
> >
> > Convert the Renesas Interrupt Controller (INTC) for external pins Device
> > Tree binding documentation to json-schema.
> >
> > Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
> > Co-developed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,intc-irqpin.yaml
>
> > + sense-bitfield-width:
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - enum: [2, 4]
> > + default: 4
>
> The "allOf" is no longer needed. Will remove for v4.
I'll fix up and apply.
Rob
^ permalink raw reply
* Re: [PATCH] dt-bindings: clock: renesas: div6: Convert to json-schema
From: Rob Herring @ 2020-05-15 2:43 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Stephen Boyd, Rob Herring, linux-clk, linux-renesas-soc,
Michael Turquette, devicetree
In-Reply-To: <20200507075026.31941-1-geert+renesas@glider.be>
On Thu, 7 May 2020 09:50:26 +0200, Geert Uytterhoeven wrote:
> Convert the Renesas CPG DIV6 Clock Device Tree binding documentation to
> json-schema.
>
> Drop R-Car Gen2 compatible values, which were obsoleted by the unified
> "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT
> bindings.
> Update the example to match reality.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> To be queued in clk-renesas-for-v5.8.
>
> .../clock/renesas,cpg-div6-clock.yaml | 60 +++++++++++++++++++
> .../clock/renesas,cpg-div6-clocks.txt | 40 -------------
> 2 files changed, 60 insertions(+), 40 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml
> delete mode 100644 Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH] clk: clk-si5341: Add support for the Si5345 series
From: Rob Herring @ 2020-05-15 2:42 UTC (permalink / raw)
To: Mike Looijmans
Cc: robh+dt, devicetree, linux-kernel, linux-clk, sboyd, mturquette
In-Reply-To: <20200507061544.11388-1-mike.looijmans@topic.nl>
On Thu, 7 May 2020 08:15:44 +0200, Mike Looijmans wrote:
> Add support for the Si5342, Si5344 and Si5345 chips. These are equivalent
> to the Si5341 family, but with more clock input options (which are not
> supported yet by this driver).
>
> Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
> ---
> .../bindings/clock/silabs,si5341.txt | 11 ++-
> drivers/clk/clk-si5341.c | 69 +++++++++++++++++--
> 2 files changed, 74 insertions(+), 6 deletions(-)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v7 3/4] dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SC7180
From: Sandeep Maheswaram @ 2020-05-15 2:39 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, Matthias Kaehlcke
Cc: linux-arm-msm, linux-kernel, devicetree, Manu Gautam,
Sandeep Maheswaram
In-Reply-To: <1589510358-3865-1-git-send-email-sanm@codeaurora.org>
Add compatible for SC7180 in QMP USB3 DP PHY bindings.
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
---
Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
index 6055786..b770e63 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
@@ -12,8 +12,9 @@ maintainers:
properties:
compatible:
- const:
- qcom,sdm845-qmp-usb3-phy
+ enum:
+ - qcom,sc7180-qmp-usb3-phy
+ - qcom,sdm845-qmp-usb3-phy
reg:
items:
- description: Address and length of PHY's common serdes block.
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v7 4/4] phy: qcom-qmp: Add QMP V3 USB3 PHY support for SC7180
From: Sandeep Maheswaram @ 2020-05-15 2:39 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, Matthias Kaehlcke
Cc: linux-arm-msm, linux-kernel, devicetree, Manu Gautam,
Sandeep Maheswaram
In-Reply-To: <1589510358-3865-1-git-send-email-sanm@codeaurora.org>
Adding QMP v3 USB3 PHY support for SC7180.
Adding only usb phy reset in the list to avoid
reset of DP block.
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 38 +++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 5942167..3504931 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -1578,6 +1578,10 @@ static const char * const msm8996_usb3phy_reset_l[] = {
"phy", "common",
};
+static const char * const sc7180_usb3phy_reset_l[] = {
+ "phy",
+};
+
static const char * const sdm845_pciephy_reset_l[] = {
"phy",
};
@@ -1791,6 +1795,37 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
.is_dual_lane_phy = true,
};
+static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
+ .type = PHY_TYPE_USB3,
+ .nlanes = 1,
+
+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
+ .tx_tbl = qmp_v3_usb3_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
+ .rx_tbl = qmp_v3_usb3_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
+ .clk_list = qmp_v3_phy_clk_l,
+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
+ .reset_list = sc7180_usb3phy_reset_l,
+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = qmp_v3_usb3phy_regs_layout,
+
+ .start_ctrl = SERDES_START | PCS_START,
+ .pwrdn_ctrl = SW_PWRDN,
+
+ .has_pwrdn_delay = true,
+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+
+ .has_phy_dp_com_ctrl = true,
+ .is_dual_lane_phy = true,
+};
+
static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
.type = PHY_TYPE_USB3,
.nlanes = 1,
@@ -2680,6 +2715,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
.compatible = "qcom,ipq8074-qmp-pcie-phy",
.data = &ipq8074_pciephy_cfg,
}, {
+ .compatible = "qcom,sc7180-qmp-usb3-phy",
+ .data = &sc7180_usb3phy_cfg,
+ }, {
.compatible = "qcom,sdm845-qhp-pcie-phy",
.data = &sdm845_qhp_pciephy_cfg,
}, {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v7 1/4] dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml
From: Sandeep Maheswaram @ 2020-05-15 2:39 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, Matthias Kaehlcke
Cc: linux-arm-msm, linux-kernel, devicetree, Manu Gautam,
Sandeep Maheswaram
In-Reply-To: <1589510358-3865-1-git-send-email-sanm@codeaurora.org>
Convert QMP PHY bindings to DT schema format using json-schema.
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
---
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 334 +++++++++++++++++++++
.../devicetree/bindings/phy/qcom-qmp-phy.txt | 247 ---------------
2 files changed, 334 insertions(+), 247 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
new file mode 100644
index 0000000..dcdb014
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -0,0 +1,334 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm QMP PHY controller
+
+maintainers:
+ - Manu Gautam <mgautam@codeaurora.org>
+
+description:
+ QMP phy controller supports physical layer functionality for a number of
+ controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq8074-qmp-pcie-phy
+ - qcom,msm8996-qmp-pcie-phy
+ - qcom,msm8996-qmp-ufs-phy
+ - qcom,msm8996-qmp-usb3-phy
+ - qcom,msm8998-qmp-pcie-phy
+ - qcom,msm8998-qmp-ufs-phy
+ - qcom,msm8998-qmp-usb3-phy
+ - qcom,sdm845-qhp-pcie-phy
+ - qcom,sdm845-qmp-pcie-phy
+ - qcom,sdm845-qmp-ufs-phy
+ - qcom,sdm845-qmp-usb3-phy
+ - qcom,sdm845-qmp-usb3-uni-phy
+ - qcom,sm8150-qmp-ufs-phy
+ - qcom,sm8250-qmp-ufs-phy
+
+ reg:
+ minItems: 1
+ items:
+ - description: Address and length of PHY's common serdes block.
+ - description: Address and length of the DP_COM control block.
+
+ reg-names:
+ items:
+ - const: reg-base
+ - const: dp_com
+
+ "#clock-cells":
+ enum: [ 1, 2 ]
+
+ "#address-cells":
+ enum: [ 1, 2 ]
+
+ "#size-cells":
+ enum: [ 1, 2 ]
+
+ clocks:
+ minItems: 1
+ maxItems: 4
+
+ clock-names:
+ minItems: 1
+ maxItems: 4
+
+ resets:
+ minItems: 1
+ maxItems: 3
+
+ reset-names:
+ minItems: 1
+ maxItems: 3
+
+ vdda-phy-supply:
+ description:
+ Phandle to a regulator supply to PHY core block.
+
+ vdda-pll-supply:
+ description:
+ Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+ vddp-ref-clk-supply:
+ description:
+ Phandle to a regulator supply to any specific refclk
+ pll block.
+
+#Required nodes:
+patternProperties:
+ "^phy@[0-9a-f]+$":
+ type: object
+ description:
+ Each device node of QMP phy is required to have as many child nodes as
+ the number of lanes the PHY has.
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#address-cells"
+ - "#size-cells"
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - vdda-phy-supply
+ - vdda-pll-supply
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdm845-qmp-usb3-phy
+ - qcom,sdm845-qmp-usb3-uni-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Phy aux clock.
+ - description: Phy config clock.
+ - description: 19.2 MHz ref clk.
+ - description: Phy common block aux clock.
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ - const: com_aux
+ resets:
+ items:
+ - description: reset of phy block.
+ - description: phy common block reset.
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8996-qmp-pcie-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Phy aux clock.
+ - description: Phy config clock.
+ - description: 19.2 MHz ref clk.
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ resets:
+ items:
+ - description: reset of phy block.
+ - description: phy common block reset.
+ - description: phy's ahb cfg block reset.
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+ - const: cfg
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8996-qmp-usb3-phy
+ - qcom,msm8998-qmp-pcie-phy
+ - qcom,msm8998-qmp-usb3-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Phy aux clock.
+ - description: Phy config clock.
+ - description: 19.2 MHz ref clk.
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ resets:
+ items:
+ - description: reset of phy block.
+ - description: phy common block reset.
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8996-qmp-ufs-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: 19.2 MHz ref clk.
+ clock-names:
+ items:
+ - const: ref
+ resets:
+ items:
+ - description: PHY reset in the UFS controller.
+ reset-names:
+ items:
+ - const: ufsphy
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8998-qmp-ufs-phy
+ - qcom,sdm845-qmp-ufs-phy
+ - qcom,sm8150-qmp-ufs-phy
+ - qcom,sm8250-qmp-ufs-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: 19.2 MHz ref clk.
+ - description: Phy reference aux clock.
+ clock-names:
+ items:
+ - const: ref
+ - const: ref_aux
+ resets:
+ items:
+ - description: PHY reset in the UFS controller.
+ reset-names:
+ items:
+ - const: ufsphy
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq8074-qmp-pcie-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: pipe clk.
+ clock-names:
+ items:
+ - const: pipe_clk
+ resets:
+ items:
+ - description: reset of phy block.
+ - description: phy common block reset.
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdm845-qhp-pcie-phy
+ - qcom,sdm845-qmp-pcie-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Phy aux clock.
+ - description: Phy config clock.
+ - description: 19.2 MHz ref clk.
+ - description: Phy refgen clk.
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ - const: refgen
+ resets:
+ items:
+ - description: reset of phy block.
+ reset-names:
+ items:
+ - const: phy
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,sdm845-qmp-usb3-phy
+ then:
+ required:
+ - reg-names
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ usb_1_qmpphy: phy-wrapper@88e9000 {
+ compatible = "qcom,sdm845-qmp-usb3-phy";
+ reg = <0 0x088e9000 0 0x18c>,
+ <0 0x088e8000 0 0x10>;
+ reg-names = "reg-base", "dp_com";
+ #clock-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "com_aux";
+
+ resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
+ reset-names = "phy", "common";
+
+ vdda-phy-supply = <&vdda_usb2_ss_1p2>;
+ vdda-pll-supply = <&vdda_usb2_ss_core>;
+
+ usb_1_ssphy: phy@88e9200 {
+ reg = <0 0x088e9200 0 0x128>,
+ <0 0x088e9400 0 0x200>,
+ <0 0x088e9c00 0 0x218>,
+ <0 0x088e9600 0 0x128>,
+ <0 0x088e9800 0 0x200>,
+ <0 0x088e9a00 0 0x100>;
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
deleted file mode 100644
index 5ff9e7a..0000000
--- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
+++ /dev/null
@@ -1,247 +0,0 @@
-Qualcomm QMP PHY controller
-===========================
-
-QMP phy controller supports physical layer functionality for a number of
-controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
-
-Required properties:
- - compatible: compatible list, contains:
- "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
- "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
- "qcom,msm8996-qmp-ufs-phy" for 14nm UFS phy on msm8996,
- "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
- "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998,
- "qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998,
- "qcom,msm8998-qmp-pcie-phy" for PCIe QMP phy on msm8998,
- "qcom,sdm845-qhp-pcie-phy" for QHP PCIe phy on sdm845,
- "qcom,sdm845-qmp-pcie-phy" for QMP PCIe phy on sdm845,
- "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
- "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
- "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845,
- "qcom,sm8150-qmp-ufs-phy" for UFS QMP phy on sm8150.
- "qcom,sm8250-qmp-ufs-phy" for UFS QMP phy on sm8250.
-
-- reg:
- - index 0: address and length of register set for PHY's common
- serdes block.
- - index 1: address and length of the DP_COM control block (for
- "qcom,sdm845-qmp-usb3-phy" only).
-
-- reg-names:
- - For "qcom,sdm845-qmp-usb3-phy":
- - Should be: "reg-base", "dp_com"
- - For all others:
- - The reg-names property shouldn't be defined.
-
- - #address-cells: must be 1
- - #size-cells: must be 1
- - ranges: must be present
-
- - clocks: a list of phandles and clock-specifier pairs,
- one for each entry in clock-names.
- - clock-names: "cfg_ahb" for phy config clock,
- "aux" for phy aux clock,
- "ref" for 19.2 MHz ref clk,
- "com_aux" for phy common block aux clock,
- "ref_aux" for phy reference aux clock,
-
- For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed.
- For "qcom,msm8996-qmp-pcie-phy" must contain:
- "aux", "cfg_ahb", "ref".
- For "qcom,msm8996-qmp-ufs-phy" must contain:
- "ref".
- For "qcom,msm8996-qmp-usb3-phy" must contain:
- "aux", "cfg_ahb", "ref".
- For "qcom,msm8998-qmp-usb3-phy" must contain:
- "aux", "cfg_ahb", "ref".
- For "qcom,msm8998-qmp-ufs-phy" must contain:
- "ref", "ref_aux".
- For "qcom,msm8998-qmp-pcie-phy" must contain:
- "aux", "cfg_ahb", "ref".
- For "qcom,sdm845-qhp-pcie-phy" must contain:
- "aux", "cfg_ahb", "ref", "refgen".
- For "qcom,sdm845-qmp-pcie-phy" must contain:
- "aux", "cfg_ahb", "ref", "refgen".
- For "qcom,sdm845-qmp-usb3-phy" must contain:
- "aux", "cfg_ahb", "ref", "com_aux".
- For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
- "aux", "cfg_ahb", "ref", "com_aux".
- For "qcom,sdm845-qmp-ufs-phy" must contain:
- "ref", "ref_aux".
- For "qcom,sm8150-qmp-ufs-phy" must contain:
- "ref", "ref_aux".
- For "qcom,sm8250-qmp-ufs-phy" must contain:
- "ref", "ref_aux".
-
- - resets: a list of phandles and reset controller specifier pairs,
- one for each entry in reset-names.
- - reset-names: "phy" for reset of phy block,
- "common" for phy common block reset,
- "cfg" for phy's ahb cfg block reset,
- "ufsphy" for the PHY reset in the UFS controller.
-
- For "qcom,ipq8074-qmp-pcie-phy" must contain:
- "phy", "common".
- For "qcom,msm8996-qmp-pcie-phy" must contain:
- "phy", "common", "cfg".
- For "qcom,msm8996-qmp-ufs-phy": must contain:
- "ufsphy".
- For "qcom,msm8996-qmp-usb3-phy" must contain
- "phy", "common".
- For "qcom,msm8998-qmp-usb3-phy" must contain
- "phy", "common".
- For "qcom,msm8998-qmp-ufs-phy": must contain:
- "ufsphy".
- For "qcom,msm8998-qmp-pcie-phy" must contain:
- "phy", "common".
- For "qcom,sdm845-qhp-pcie-phy" must contain:
- "phy".
- For "qcom,sdm845-qmp-pcie-phy" must contain:
- "phy".
- For "qcom,sdm845-qmp-usb3-phy" must contain:
- "phy", "common".
- For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
- "phy", "common".
- For "qcom,sdm845-qmp-ufs-phy": must contain:
- "ufsphy".
- For "qcom,sm8150-qmp-ufs-phy": must contain:
- "ufsphy".
- For "qcom,sm8250-qmp-ufs-phy": must contain:
- "ufsphy".
-
- - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
- - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
-
-Optional properties:
- - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
- pll block.
-
-Required nodes:
- - Each device node of QMP phy is required to have as many child nodes as
- the number of lanes the PHY has.
-
-Required properties for child nodes of PCIe PHYs (one child per lane):
- - reg: list of offset and length pairs of register sets for PHY blocks -
- tx, rx, pcs, and pcs_misc (optional).
- - #phy-cells: must be 0
-
-Required properties for a single "lanes" child node of non-PCIe PHYs:
- - reg: list of offset and length pairs of register sets for PHY blocks
- For 1-lane devices:
- tx, rx, pcs, and (optionally) pcs_misc
- For 2-lane devices:
- tx0, rx0, pcs, tx1, rx1, and (optionally) pcs_misc
- - #phy-cells: must be 0
-
-Required properties for child node of PCIe and USB3 qmp phys:
- - clocks: a list of phandles and clock-specifier pairs,
- one for each entry in clock-names.
- - clock-names: Must contain following:
- "pipe<lane-number>" for pipe clock specific to each lane.
- - clock-output-names: Name of the PHY clock that will be the parent for
- the above pipe clock.
- For "qcom,ipq8074-qmp-pcie-phy":
- - "pcie20_phy0_pipe_clk" Pipe Clock parent
- (or)
- "pcie20_phy1_pipe_clk"
- - #clock-cells: must be 0
- - Phy pll outputs pipe clocks for pipe based PHYs. These clocks are then
- gate-controlled by the gcc.
-
-Required properties for child node of PHYs with lane reset, AKA:
- "qcom,msm8996-qmp-pcie-phy"
- - resets: a list of phandles and reset controller specifier pairs,
- one for each entry in reset-names.
- - reset-names: Must contain following:
- "lane<lane-number>" for reset specific to each lane.
-
-Example:
- phy@34000 {
- compatible = "qcom,msm8996-qmp-pcie-phy";
- reg = <0x34000 0x488>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
- <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
- <&gcc GCC_PCIE_CLKREF_CLK>;
- clock-names = "aux", "cfg_ahb", "ref";
-
- vdda-phy-supply = <&pm8994_l28>;
- vdda-pll-supply = <&pm8994_l12>;
-
- resets = <&gcc GCC_PCIE_PHY_BCR>,
- <&gcc GCC_PCIE_PHY_COM_BCR>,
- <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
- reset-names = "phy", "common", "cfg";
-
- pciephy_0: lane@35000 {
- reg = <0x35000 0x130>,
- <0x35200 0x200>,
- <0x35400 0x1dc>;
- #clock-cells = <0>;
- #phy-cells = <0>;
-
- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "pcie_0_pipe_clk_src";
- resets = <&gcc GCC_PCIE_0_PHY_BCR>;
- reset-names = "lane0";
- };
-
- pciephy_1: lane@36000 {
- ...
- ...
- };
-
- phy@88eb000 {
- compatible = "qcom,sdm845-qmp-usb3-uni-phy";
- reg = <0x88eb000 0x18c>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
- <&gcc GCC_USB3_SEC_CLKREF_CLK>,
- <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "com_aux";
-
- resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
- <&gcc GCC_USB3_PHY_SEC_BCR>;
- reset-names = "phy", "common";
-
- lane@88eb200 {
- reg = <0x88eb200 0x128>,
- <0x88eb400 0x1fc>,
- <0x88eb800 0x218>,
- <0x88eb600 0x70>;
- #clock-cells = <0>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_uni_phy_pipe_clk_src";
- };
- };
-
- phy@1d87000 {
- compatible = "qcom,sdm845-qmp-ufs-phy";
- reg = <0x1d87000 0x18c>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clock-names = "ref",
- "ref_aux";
- clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
-
- lanes@1d87400 {
- reg = <0x1d87400 0x108>,
- <0x1d87600 0x1e0>,
- <0x1d87c00 0x1dc>,
- <0x1d87800 0x108>,
- <0x1d87a00 0x1e0>;
- #phy-cells = <0>;
- };
- };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v7 2/4] dt-bindings: phy: qcom,qmp-usb3-dp: Add dt bindings for USB3 DP PHY
From: Sandeep Maheswaram @ 2020-05-15 2:39 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, Matthias Kaehlcke
Cc: linux-arm-msm, linux-kernel, devicetree, Manu Gautam,
Sandeep Maheswaram
In-Reply-To: <1589510358-3865-1-git-send-email-sanm@codeaurora.org>
Split out the dt bindings for USB3 DP PHY from qcom,qmp bindings
for modularity.
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
---
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 51 +++-----
.../bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 135 +++++++++++++++++++++
2 files changed, 150 insertions(+), 36 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index dcdb014..973b2d1 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -27,21 +27,13 @@ properties:
- qcom,sdm845-qhp-pcie-phy
- qcom,sdm845-qmp-pcie-phy
- qcom,sdm845-qmp-ufs-phy
- - qcom,sdm845-qmp-usb3-phy
- qcom,sdm845-qmp-usb3-uni-phy
- qcom,sm8150-qmp-ufs-phy
- qcom,sm8250-qmp-ufs-phy
reg:
- minItems: 1
items:
- description: Address and length of PHY's common serdes block.
- - description: Address and length of the DP_COM control block.
-
- reg-names:
- items:
- - const: reg-base
- - const: dp_com
"#clock-cells":
enum: [ 1, 2 ]
@@ -110,7 +102,6 @@ allOf:
compatible:
contains:
enum:
- - qcom,sdm845-qmp-usb3-phy
- qcom,sdm845-qmp-usb3-uni-phy
then:
properties:
@@ -284,51 +275,39 @@ allOf:
reset-names:
items:
- const: phy
- - if:
- properties:
- compatible:
- contains:
- const: qcom,sdm845-qmp-usb3-phy
- then:
- required:
- - reg-names
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
- usb_1_qmpphy: phy-wrapper@88e9000 {
- compatible = "qcom,sdm845-qmp-usb3-phy";
- reg = <0 0x088e9000 0 0x18c>,
- <0 0x088e8000 0 0x10>;
- reg-names = "reg-base", "dp_com";
+ usb_2_qmpphy: phy-wrapper@88eb000 {
+ compatible = "qcom,sdm845-qmp-usb3-uni-phy";
+ reg = <0 0x088eb000 0 0x18c>;
#clock-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
- clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
- <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+ <&gcc GCC_USB3_SEC_CLKREF_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "com_aux";
- resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
- <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
+ resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
+ <&gcc GCC_USB3_PHY_SEC_BCR>;
reset-names = "phy", "common";
vdda-phy-supply = <&vdda_usb2_ss_1p2>;
vdda-pll-supply = <&vdda_usb2_ss_core>;
- usb_1_ssphy: phy@88e9200 {
- reg = <0 0x088e9200 0 0x128>,
- <0 0x088e9400 0 0x200>,
- <0 0x088e9c00 0 0x218>,
- <0 0x088e9600 0 0x128>,
- <0 0x088e9800 0 0x200>,
- <0 0x088e9a00 0 0x100>;
+ usb_2_ssphy: phy@88eb200 {
+ reg = <0 0x088eb200 0 0x128>,
+ <0 0x088eb400 0 0x1fc>,
+ <0 0x088eb800 0 0x218>,
+ <0 0x088eb600 0 0x70>;
#clock-cells = <0>;
#phy-cells = <0>;
- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
clock-names = "pipe0";
- clock-output-names = "usb3_phy_pipe_clk_src";
+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
};
};
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
new file mode 100644
index 0000000..6055786
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm QMP USB3 DP PHY controller
+
+maintainers:
+ - Manu Gautam <mgautam@codeaurora.org>
+
+properties:
+ compatible:
+ const:
+ qcom,sdm845-qmp-usb3-phy
+ reg:
+ items:
+ - description: Address and length of PHY's common serdes block.
+ - description: Address and length of the DP_COM control block.
+
+ reg-names:
+ items:
+ - const: reg-base
+ - const: dp_com
+
+ "#clock-cells":
+ enum: [ 1, 2 ]
+
+ "#address-cells":
+ enum: [ 1, 2 ]
+
+ "#size-cells":
+ enum: [ 1, 2 ]
+
+ clocks:
+ items:
+ - description: Phy aux clock.
+ - description: Phy config clock.
+ - description: 19.2 MHz ref clk.
+ - description: Phy common block aux clock.
+
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ - const: com_aux
+
+ resets:
+ items:
+ - description: reset of phy block.
+ - description: phy common block reset.
+
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+
+ vdda-phy-supply:
+ description:
+ Phandle to a regulator supply to PHY core block.
+
+ vdda-pll-supply:
+ description:
+ Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+ vddp-ref-clk-supply:
+ description:
+ Phandle to a regulator supply to any specific refclk
+ pll block.
+
+#Required nodes:
+patternProperties:
+ "^phy@[0-9a-f]+$":
+ type: object
+ description:
+ Each device node of QMP phy is required to have as many child nodes as
+ the number of lanes the PHY has.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#clock-cells"
+ - "#address-cells"
+ - "#size-cells"
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - vdda-phy-supply
+ - vdda-pll-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ usb_1_qmpphy: phy-wrapper@88e9000 {
+ compatible = "qcom,sdm845-qmp-usb3-phy";
+ reg = <0 0x088e9000 0 0x18c>,
+ <0 0x088e8000 0 0x10>;
+ reg-names = "reg-base", "dp_com";
+ #clock-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "com_aux";
+
+ resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
+ reset-names = "phy", "common";
+
+ vdda-phy-supply = <&vdda_usb2_ss_1p2>;
+ vdda-pll-supply = <&vdda_usb2_ss_core>;
+
+ usb_1_ssphy: phy@88e9200 {
+ reg = <0 0x088e9200 0 0x128>,
+ <0 0x088e9400 0 0x200>,
+ <0 0x088e9c00 0 0x218>,
+ <0 0x088e9600 0 0x128>,
+ <0 0x088e9800 0 0x200>,
+ <0 0x088e9a00 0 0x100>;
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ };
+ };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v7 0/4] Add QMP V3 USB3 PHY support for SC7180
From: Sandeep Maheswaram @ 2020-05-15 2:39 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, Matthias Kaehlcke
Cc: linux-arm-msm, linux-kernel, devicetree, Manu Gautam,
Sandeep Maheswaram
Add QMP V3 USB3 PHY entries for SC7180 in phy driver and
device tree bindings.
changes in v7:
*As per Matthias comments conversion to yaml and splitting out DP PHY bindings
patches are separated.
*PATCH v7 1/4 is for coversion to yaml.
*PATCH v7 2/4 has splitting out DP PHY bindings and adding as separate yaml
for DP PHY bindings.
*No changes in PATCH v7 3/4 and 4/4.
changes in v6:
*Added separate yaml file for USB3 DP PHY bindings.
changes in v5:
*Addressed comments from Matthias in yaml file.
*Dropped PATCH 4/4 as it is landed in linux-next.
changes in v4:
*Addressed comments from Matthias and Rob in yaml file.
changes in v3:
*Addressed Rob's comments in yaml file.
*Sepearated the SC7180 support in yaml patch.
*corrected the phy reset entries in device tree.
changes in v2:
*Remove global phy reset in QMP PHY.
*Convert QMP PHY bindings to yaml.
Sandeep Maheswaram (4):
dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml
dt-bindings: phy: qcom,qmp-usb3-dp: Add dt bindings for USB3 DP PHY
dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SC7180
phy: qcom-qmp: Add QMP V3 USB3 PHY support for SC7180
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 313 +++++++++++++++++++++
.../bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 136 +++++++++
.../devicetree/bindings/phy/qcom-qmp-phy.txt | 247 ----------------
drivers/phy/qualcomm/phy-qcom-qmp.c | 38 +++
4 files changed, 487 insertions(+), 247 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply
* Re: [PATCH 01/19] dt-bindings: PCI: Endpoint: Add DT bindings for PCI EPF NTB Device
From: Rob Herring @ 2020-05-15 2:38 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: linux-pci, devicetree, linux-ntb, Arnd Bergmann,
Greg Kroah-Hartman, linux-doc, Rob Herring, Jonathan Corbet,
linux-kernel, Bjorn Helgaas, Allen Hubbe, Tom Joseph, Dave Jiang,
Jon Mason, Lorenzo Pieralisi
In-Reply-To: <20200514145927.17555-2-kishon@ti.com>
On Thu, 14 May 2020 20:29:09 +0530, Kishon Vijay Abraham I wrote:
> Add device tree schema for PCI endpoint function bus to which
> endpoint function devices should be attached. Then add device tree
> schema for PCI endpoint function device to include bindings thats
> generic to all endpoint functions. Finally add device tree schema
> for PCI endpoint NTB function device by including the generic
> device tree schema for PCIe endpoint function.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> .../bindings/pci/endpoint/pci-epf-bus.yaml | 42 +++++++++++
> .../bindings/pci/endpoint/pci-epf-device.yaml | 69 +++++++++++++++++++
> .../bindings/pci/endpoint/pci-epf-ntb.yaml | 68 ++++++++++++++++++
> 3 files changed, 179 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pci/endpoint/pci-epf-bus.yaml
> create mode 100644 Documentation/devicetree/bindings/pci/endpoint/pci-epf-device.yaml
> create mode 100644 Documentation/devicetree/bindings/pci/endpoint/pci-epf-ntb.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
Traceback (most recent call last):
File "/usr/local/bin/dt-doc-validate", line 64, in <module>
ret = check_doc(args.yamldt)
File "/usr/local/bin/dt-doc-validate", line 25, in check_doc
testtree = dtschema.load(filename, line_number=line_number, duplicate_keys=False)
File "/usr/local/lib/python3.6/dist-packages/dtschema/lib.py", line 592, in load
return yaml.load(f.read())
File "/usr/local/lib/python3.6/dist-packages/ruamel/yaml/main.py", line 343, in load
return constructor.get_single_data()
File "/usr/local/lib/python3.6/dist-packages/ruamel/yaml/constructor.py", line 113, in get_single_data
return self.construct_document(node)
File "/usr/local/lib/python3.6/dist-packages/ruamel/yaml/constructor.py", line 123, in construct_document
for _dummy in generator:
File "/usr/local/lib/python3.6/dist-packages/ruamel/yaml/constructor.py", line 723, in construct_yaml_map
value = self.construct_mapping(node)
File "/usr/local/lib/python3.6/dist-packages/ruamel/yaml/constructor.py", line 440, in construct_mapping
return BaseConstructor.construct_mapping(self, node, deep=deep)
File "/usr/local/lib/python3.6/dist-packages/ruamel/yaml/constructor.py", line 257, in construct_mapping
if self.check_mapping_key(node, key_node, mapping, key, value):
File "/usr/local/lib/python3.6/dist-packages/ruamel/yaml/constructor.py", line 295, in check_mapping_key
raise DuplicateKeyError(*args)
ruamel.yaml.constructor.DuplicateKeyError: while constructing a mapping
in "<unicode string>", line 5, column 1
found duplicate key "properties" with value "{}" (original value: "{}")
in "<unicode string>", line 17, column 1
To suppress this check see:
http://yaml.readthedocs.io/en/latest/api.html#duplicate-keys
Duplicate keys will become an error in future releases, and are errors
by default when using the new API.
Documentation/devicetree/bindings/Makefile:12: recipe for target 'Documentation/devicetree/bindings/pci/endpoint/pci-epf-device.example.dts' failed
make[1]: *** [Documentation/devicetree/bindings/pci/endpoint/pci-epf-device.example.dts] Error 1
make[1]: *** Waiting for unfinished jobs....
Documentation/devicetree/bindings/pci/endpoint/pci-epf-ntb.yaml: while constructing a mapping
in "<unicode string>", line 5, column 1
found duplicate key "properties" with value "{}" (original value: "{}")
in "<unicode string>", line 17, column 1
To suppress this check see:
http://yaml.readthedocs.io/en/latest/api.html#duplicate-keys
Duplicate keys will become an error in future releases, and are errors
by default when using the new API.
Traceback (most recent call last):
File "/usr/local/bin/dt-mk-schema", line 34, in <module>
schemas = dtschema.process_schemas(args.schemas, core_schema=(not args.useronly))
File "/usr/local/lib/python3.6/dist-packages/dtschema/lib.py", line 554, in process_schemas
sch = process_schema(os.path.abspath(filename))
File "/usr/local/lib/python3.6/dist-packages/dtschema/lib.py", line 507, in process_schema
schema = load_schema(filename)
File "/usr/local/lib/python3.6/dist-packages/dtschema/lib.py", line 123, in load_schema
return do_load(os.path.join(schema_basedir, schema))
File "/usr/local/lib/python3.6/dist-packages/dtschema/lib.py", line 108, in do_load
return yaml.load(tmp)
File "/usr/local/lib/python3.6/dist-packages/ruamel/yaml/main.py", line 343, in load
return constructor.get_single_data()
File "/usr/local/lib/python3.6/dist-packages/ruamel/yaml/constructor.py", line 113, in get_single_data
return self.construct_document(node)
File "/usr/local/lib/python3.6/dist-packages/ruamel/yaml/constructor.py", line 123, in construct_document
for _dummy in generator:
File "/usr/local/lib/python3.6/dist-packages/ruamel/yaml/constructor.py", line 723, in construct_yaml_map
value = self.construct_mapping(node)
File "/usr/local/lib/python3.6/dist-packages/ruamel/yaml/constructor.py", line 440, in construct_mapping
return BaseConstructor.construct_mapping(self, node, deep=deep)
File "/usr/local/lib/python3.6/dist-packages/ruamel/yaml/constructor.py", line 257, in construct_mapping
if self.check_mapping_key(node, key_node, mapping, key, value):
File "/usr/local/lib/python3.6/dist-packages/ruamel/yaml/constructor.py", line 295, in check_mapping_key
raise DuplicateKeyError(*args)
ruamel.yaml.constructor.DuplicateKeyError: while constructing a mapping
in "<unicode string>", line 5, column 1
found duplicate key "properties" with value "{}" (original value: "{}")
in "<unicode string>", line 17, column 1
To suppress this check see:
http://yaml.readthedocs.io/en/latest/api.html#duplicate-keys
Duplicate keys will become an error in future releases, and are errors
by default when using the new API.
Documentation/devicetree/bindings/Makefile:41: recipe for target 'Documentation/devicetree/bindings/processed-schema-examples.yaml' failed
make[1]: *** [Documentation/devicetree/bindings/processed-schema-examples.yaml] Error 123
make[1]: *** Deleting file 'Documentation/devicetree/bindings/processed-schema-examples.yaml'
Traceback (most recent call last):
File "/usr/local/bin/dt-mk-schema", line 34, in <module>
schemas = dtschema.process_schemas(args.schemas, core_schema=(not args.useronly))
File "/usr/local/lib/python3.6/dist-packages/dtschema/lib.py", line 554, in process_schemas
sch = process_schema(os.path.abspath(filename))
File "/usr/local/lib/python3.6/dist-packages/dtschema/lib.py", line 507, in process_schema
schema = load_schema(filename)
File "/usr/local/lib/python3.6/dist-packages/dtschema/lib.py", line 123, in load_schema
return do_load(os.path.join(schema_basedir, schema))
File "/usr/local/lib/python3.6/dist-packages/dtschema/lib.py", line 108, in do_load
return yaml.load(tmp)
File "/usr/local/lib/python3.6/dist-packages/ruamel/yaml/main.py", line 343, in load
return constructor.get_single_data()
File "/usr/local/lib/python3.6/dist-packages/ruamel/yaml/constructor.py", line 113, in get_single_data
return self.construct_document(node)
File "/usr/local/lib/python3.6/dist-packages/ruamel/yaml/constructor.py", line 123, in construct_document
for _dummy in generator:
File "/usr/local/lib/python3.6/dist-packages/ruamel/yaml/constructor.py", line 723, in construct_yaml_map
value = self.construct_mapping(node)
File "/usr/local/lib/python3.6/dist-packages/ruamel/yaml/constructor.py", line 440, in construct_mapping
return BaseConstructor.construct_mapping(self, node, deep=deep)
File "/usr/local/lib/python3.6/dist-packages/ruamel/yaml/constructor.py", line 257, in construct_mapping
if self.check_mapping_key(node, key_node, mapping, key, value):
File "/usr/local/lib/python3.6/dist-packages/ruamel/yaml/constructor.py", line 295, in check_mapping_key
raise DuplicateKeyError(*args)
ruamel.yaml.constructor.DuplicateKeyError: while constructing a mapping
in "<unicode string>", line 5, column 1
found duplicate key "properties" with value "{}" (original value: "{}")
in "<unicode string>", line 17, column 1
To suppress this check see:
http://yaml.readthedocs.io/en/latest/api.html#duplicate-keys
Duplicate keys will become an error in future releases, and are errors
by default when using the new API.
Documentation/devicetree/bindings/Makefile:45: recipe for target 'Documentation/devicetree/bindings/processed-schema.yaml' failed
make[1]: *** [Documentation/devicetree/bindings/processed-schema.yaml] Error 123
make[1]: *** Deleting file 'Documentation/devicetree/bindings/processed-schema.yaml'
Makefile:1300: recipe for target 'dt_binding_check' failed
make: *** [dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1290443
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:
pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
Please check and re-submit.
^ permalink raw reply
* Re: [PATCH v6 1/2] dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC
From: Ramuthevar, Vadivel MuruganX @ 2020-05-15 2:08 UTC (permalink / raw)
To: Rob Herring
Cc: masonccyang, linux-mtd, richard, boris.brezillon, brendanhiggins,
tglx, miquel.raynal, vigneshr, hauke.mehrtens, devicetree,
anders.roxell, arnd, robh+dt, andriy.shevchenko, linux-mips,
cheol.yong.kim, linux-kernel, qi-ming.wu
In-Reply-To: <20200514125709.GA8436@bogus>
Hi Rob,
On 14/5/2020 8:57 pm, Rob Herring wrote:
> On Wed, 13 May 2020 18:46:14 +0800, Ramuthevar,Vadivel MuruganX wrote:
>> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>>
>> Add YAML file for dt-bindings to support NAND Flash Controller
>> on Intel's Lightning Mountain SoC.
>>
>> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>> ---
>> .../devicetree/bindings/mtd/intel,lgm-nand.yaml | 83 ++++++++++++++++++++++
>> 1 file changed, 83 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
>>
>
>
> My bot found errors running 'make dt_binding_check' on your patch:
>
> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/mtd/intel,lgm-nand.example.dt.yaml: nand-controller@e0f00000: 'dmas' is a dependency of 'dma-names'
>
> See https://patchwork.ozlabs.org/patch/1289160
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure dt-schema is up to date:
>
> pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
>
> Please check and re-submit.
Thank you very much for review comments...
I didn't find build errors, successfully built.
Regards
Vadivel
>
^ permalink raw reply
* Re: [PATCH v6 1/2] dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC
From: Ramuthevar, Vadivel MuruganX @ 2020-05-15 2:06 UTC (permalink / raw)
To: Rob Herring
Cc: linux-kernel, linux-mtd, devicetree, miquel.raynal, richard,
vigneshr, arnd, brendanhiggins, tglx, boris.brezillon,
anders.roxell, masonccyang, linux-mips, hauke.mehrtens,
andriy.shevchenko, qi-ming.wu, cheol.yong.kim
In-Reply-To: <20200514130321.GB8436@bogus>
Hi Rob,
Thank you for the review comments...
On 14/5/2020 9:03 pm, Rob Herring wrote:
> On Wed, May 13, 2020 at 06:46:14PM +0800, Ramuthevar,Vadivel MuruganX wrote:
>> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>>
>> Add YAML file for dt-bindings to support NAND Flash Controller
>> on Intel's Lightning Mountain SoC.
>>
>> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>> ---
>> .../devicetree/bindings/mtd/intel,lgm-nand.yaml | 83 ++++++++++++++++++++++
>> 1 file changed, 83 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
>> new file mode 100644
>> index 000000000000..d9e0df8553fa
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
>> @@ -0,0 +1,83 @@
>> +# SPDX-License-Identifier: GPL-2.0
>
> Dual license new bindings please:
>
> (GPL-2.0-only OR BSD-2-Clause)
Noted.
>
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/mtd/intel,lgm-nand.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Intel LGM SoC NAND Controller Device Tree Bindings
>> +
>> +allOf:
>> + - $ref: "nand-controller.yaml"
>> +
>> +maintainers:
>> + - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>> +
>> +properties:
>> + compatible:
>> + const: intel,lgm-nand-controller
>> +
>> + reg:
>> + maxItems: 1
>
> Looks like you have 4 or 6 entries, not 1. Need to define what each one
> is.
Sure, will define it.
>
>> +
>> + clocks:
>> + maxItems: 1
>> +
>> + dmas:
>> + maxItems: 2
>> +
>> + dma-names:
>> + enum:
>> + - rx
>> + - tx
>
> This defines a single entry. I believe you want:
>
> items:
> - const: tx
> - const: rx
Yes, Thanks!
>
>> +
>> + pinctrl-names: true
>
> No need for this. Tools add pinctrl properties.
will drop it.
>
>> +
>> +patternProperties:
>> + "^nand@[a-f0-9]+$":
>> + type: object
>> + properties:
>> + reg:
>> + minimum: 0
>> + maximum: 7
>> +
>> + nand-ecc-mode: true
>> +
>> + nand-ecc-algo:
>> + const: hw
>> +
>> + additionalProperties: false
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - dmas
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + nand-controller@e0f00000 {
>> + compatible = "intel,nand-controller";
>
> Doesn't match the schema.
Noted, will update the schema name.
>
>> + reg = <0xe0f00000 0x100>,
>> + <0xe1000000 0x300>,
>> + <0xe1400000 0x8000>,
>> + <0xe1c00000 0x1000>;
>
> Is it 4 or 6 entries?
yes, will update.
>
>> + reg-names = "ebunand", "hsnand", "nand_cs0", "nand_cs1",
>> + "addr_sel0","addr_sel1";
>
> Not documented.
Noted, will document it.
>
>> + clocks = <&cgu0 125>;
>> + dma-names = "tx", "rx";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + #clock-cells = <1>;
>
> This is a clock provider too?
Yes, it is getting clock from CGU for nand-controller.
Regards
Vadivel
>
>> +
>> + nand@0 {
>> + reg = <0>;
>> + nand-on-flash-bbt;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + };
>> + };
>> +
>> +...
>> --
>> 2.11.0
>>
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox