* [PATCH 04/17] dt-bindings: mmc: renesas,sdhi: Document r8a7742 support
From: Lad Prabhakar @ 2020-05-15 15:08 UTC (permalink / raw)
To: Geert Uytterhoeven, Jens Axboe, Rob Herring, Wolfram Sang,
Ulf Hansson, Sergei Shtylyov, David S. Miller, Wim Van Sebroeck,
Guenter Roeck
Cc: linux-ide, devicetree, linux-kernel, linux-i2c, linux-mmc, netdev,
linux-renesas-soc, linux-watchdog, Prabhakar, Lad Prabhakar
In-Reply-To: <1589555337-5498-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
Document SDHI controller for RZ/G1H (R8A7742) SoC, which is compatible
with R-Car Gen2 SoC family.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
---
Documentation/devicetree/bindings/mmc/renesas,sdhi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.txt b/Documentation/devicetree/bindings/mmc/renesas,sdhi.txt
index e6cc478..0ca9a62 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.txt
+++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.txt
@@ -7,6 +7,7 @@ Required properties:
"renesas,sdhi-r7s9210" - SDHI IP on R7S9210 SoC
"renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC
"renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC
+ "renesas,sdhi-r8a7742" - SDHI IP on R8A7742 SoC
"renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC
"renesas,sdhi-r8a7744" - SDHI IP on R8A7744 SoC
"renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC
--
2.7.4
^ permalink raw reply related
* [PATCH 05/17] mmc: renesas_sdhi_sys_dmac: Add support for r8a7742 SoC
From: Lad Prabhakar @ 2020-05-15 15:08 UTC (permalink / raw)
To: Geert Uytterhoeven, Jens Axboe, Rob Herring, Wolfram Sang,
Ulf Hansson, Sergei Shtylyov, David S. Miller, Wim Van Sebroeck,
Guenter Roeck
Cc: linux-ide, devicetree, linux-kernel, linux-i2c, linux-mmc, netdev,
linux-renesas-soc, linux-watchdog, Prabhakar, Lad Prabhakar
In-Reply-To: <1589555337-5498-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
Add support for r8a7742 SoC. Renesas RZ/G1H (R8A7742) SDHI is identical to
the R-Car Gen2 family.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
---
drivers/mmc/host/renesas_sdhi_sys_dmac.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/host/renesas_sdhi_sys_dmac.c b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
index 13ff023..dbfcbc2 100644
--- a/drivers/mmc/host/renesas_sdhi_sys_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_sys_dmac.c
@@ -75,6 +75,7 @@ static const struct of_device_id renesas_sdhi_sys_dmac_of_match[] = {
{ .compatible = "renesas,sdhi-r7s72100", .data = &of_rz_compatible, },
{ .compatible = "renesas,sdhi-r8a7778", .data = &of_rcar_gen1_compatible, },
{ .compatible = "renesas,sdhi-r8a7779", .data = &of_rcar_gen1_compatible, },
+ { .compatible = "renesas,sdhi-r8a7742", .data = &of_rcar_gen2_compatible, },
{ .compatible = "renesas,sdhi-r8a7743", .data = &of_rcar_gen2_compatible, },
{ .compatible = "renesas,sdhi-r8a7745", .data = &of_rcar_gen2_compatible, },
{ .compatible = "renesas,sdhi-r8a7790", .data = &of_rcar_gen2_compatible, },
--
2.7.4
^ permalink raw reply related
* [PATCH 06/17] ARM: dts: r8a7742: Add SDHI nodes
From: Lad Prabhakar @ 2020-05-15 15:08 UTC (permalink / raw)
To: Geert Uytterhoeven, Jens Axboe, Rob Herring, Wolfram Sang,
Ulf Hansson, Sergei Shtylyov, David S. Miller, Wim Van Sebroeck,
Guenter Roeck
Cc: linux-ide, devicetree, linux-kernel, linux-i2c, linux-mmc, netdev,
linux-renesas-soc, linux-watchdog, Prabhakar, Lad Prabhakar
In-Reply-To: <1589555337-5498-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
Add the SDHI devices nodes to the R8A7742 device tree.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742.dtsi | 60 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index f28c32d..0565472 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -717,6 +717,66 @@
status = "disabled";
};
+ sdhi0: sd@ee100000 {
+ compatible = "renesas,sdhi-r8a7742",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee100000 0 0x328>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 314>;
+ dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+ <&dmac1 0xcd>, <&dmac1 0xce>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 314>;
+ status = "disabled";
+ };
+
+ sdhi1: sd@ee120000 {
+ compatible = "renesas,sdhi-r8a7742",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee120000 0 0x328>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 313>;
+ dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
+ <&dmac1 0xc9>, <&dmac1 0xca>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <195000000>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 313>;
+ status = "disabled";
+ };
+
+ sdhi2: sd@ee140000 {
+ compatible = "renesas,sdhi-r8a7742",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee140000 0 0x100>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 312>;
+ dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+ <&dmac1 0xc1>, <&dmac1 0xc2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 312>;
+ status = "disabled";
+ };
+
+ sdhi3: sd@ee160000 {
+ compatible = "renesas,sdhi-r8a7742",
+ "renesas,rcar-gen2-sdhi";
+ reg = <0 0xee160000 0 0x100>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 311>;
+ dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+ <&dmac1 0xd3>, <&dmac1 0xd4>;
+ dma-names = "tx", "rx", "tx", "rx";
+ max-frequency = <97500000>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 311>;
+ status = "disabled";
+ };
+
mmcif1: mmc@ee220000 {
compatible = "renesas,mmcif-r8a7742",
"renesas,sh-mmcif";
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v3 08/20] arm64: dts: arm: model: Fix GIC compatible names
From: André Przywara @ 2020-05-15 15:10 UTC (permalink / raw)
To: Sudeep Holla
Cc: Rob Herring, Liviu Dudau, Lorenzo Pieralisi, devicetree,
linux-arm-kernel, Mark Rutland, Marc Zyngier
In-Reply-To: <20200513182144.GD27686@bogus>
On 13/05/2020 19:21, Sudeep Holla wrote:
> On Wed, May 13, 2020 at 11:30:04AM +0100, Andre Przywara wrote:
>> The GIC DT binding only allows certain combinations of DT compatible
>> strings. The somewhat awkward "arm,cortex-a15-gic", "arm,cortex-a9-gic"
>> is not among those.
>>
>> Drop that combination of different "cortex" based strings used for the
>> models, and replace it with the more useful combination including
>> "arm,gic-400".
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>> ---
>> arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi | 2 +-
>> arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts | 2 +-
>> 2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi b/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi
>> index 15fe81738e94..f17e744163a5 100644
>> --- a/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi
>> +++ b/arch/arm64/boot/dts/arm/foundation-v8-gicv2.dtsi
>> @@ -6,7 +6,7 @@
>>
>> / {
>> gic: interrupt-controller@2c001000 {
>> - compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
>> + compatible = "arm,gic-400", "arm,cortex-a15-gic";
>
> Do we need to still retain "arm,cortex-a15-gic" ?
I'd rather would like to keep that. "arm,gic-400" was introduced only
later into Linux as a compatible string, so dropping this would break
older kernels. I don't see any difference between a9-gic and a15-gic in
term of kernel support, so a9-gic can surely go.
Cheers,
Andre
^ permalink raw reply
* [PATCH 07/17] ARM: dts: r8a7742: Add MMC0 node
From: Lad Prabhakar @ 2020-05-15 15:08 UTC (permalink / raw)
To: Geert Uytterhoeven, Jens Axboe, Rob Herring, Wolfram Sang,
Ulf Hansson, Sergei Shtylyov, David S. Miller, Wim Van Sebroeck,
Guenter Roeck
Cc: linux-ide, devicetree, linux-kernel, linux-i2c, linux-mmc, netdev,
linux-renesas-soc, linux-watchdog, Prabhakar, Lad Prabhakar
In-Reply-To: <1589555337-5498-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
Describe MMC0 device node in the R8A7742 device tree.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index 0565472..ca1a016 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -777,6 +777,22 @@
status = "disabled";
};
+ mmcif0: mmc@ee200000 {
+ compatible = "renesas,mmcif-r8a7742",
+ "renesas,sh-mmcif";
+ reg = <0 0xee200000 0 0x80>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 315>;
+ dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+ <&dmac1 0xd1>, <&dmac1 0xd2>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 315>;
+ reg-io-width = <4>;
+ status = "disabled";
+ max-frequency = <97500000>;
+ };
+
mmcif1: mmc@ee220000 {
compatible = "renesas,mmcif-r8a7742",
"renesas,sh-mmcif";
--
2.7.4
^ permalink raw reply related
* Re: [PATCH 06/14] arm64: dts: sparx5: Add basic cpu support
From: Lars Povlsen @ 2020-05-15 15:09 UTC (permalink / raw)
To: Marc Zyngier
Cc: Lars Povlsen, SoC Team, Arnd Bergmann, Stephen Boyd,
Linus Walleij, devicetree, Alexandre Belloni, Steen Hegelund,
linux-clk, linux-kernel, Microchip Linux Driver Support,
linux-gpio, linux-arm-kernel, Olof Johansson, Michael Turquette
In-Reply-To: <2d230dab95ee96727a42f9c242c93c18@misterjones.org>
Marc Zyngier writes:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 2020-05-13 13:55, Lars Povlsen wrote:
>> This adds the basic DT structure for the Microchip Sparx5 SoC, and the
>> reference boards, pcb125, pcb134 and pcb135. The two latter have a
>> NAND vs a eMMC centric variant (as a mount option),
>>
>> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
>> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
>> ---
>> MAINTAINERS | 1 +
>> arch/arm64/boot/dts/Makefile | 1 +
>> arch/arm64/boot/dts/microchip/Makefile | 4 +
>> arch/arm64/boot/dts/microchip/sparx5.dtsi | 135 ++++++++++++++++++
>> .../boot/dts/microchip/sparx5_pcb125.dts | 17 +++
>> .../boot/dts/microchip/sparx5_pcb134.dts | 17 +++
>> .../dts/microchip/sparx5_pcb134_board.dtsi | 15 ++
>> .../boot/dts/microchip/sparx5_pcb134_emmc.dts | 17 +++
>> .../boot/dts/microchip/sparx5_pcb135.dts | 17 +++
>> .../dts/microchip/sparx5_pcb135_board.dtsi | 15 ++
>> .../boot/dts/microchip/sparx5_pcb135_emmc.dts | 17 +++
>> .../boot/dts/microchip/sparx5_pcb_common.dtsi | 15 ++
>> 12 files changed, 271 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/microchip/Makefile
>> create mode 100644 arch/arm64/boot/dts/microchip/sparx5.dtsi
>> create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
>> create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb134.dts
>> create mode 100644
>> arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
>> create mode 100644
>> arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts
>> create mode 100644 arch/arm64/boot/dts/microchip/sparx5_pcb135.dts
>> create mode 100644
>> arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
>> create mode 100644
>> arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts
>> create mode 100644
>> arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 1b5a18d3dbb9f..5aa28d6e39d4f 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -2084,6 +2084,7 @@ M: Lars Povlsen <lars.povlsen@microchip.com>
>> M: Steen Hegelund <Steen.Hegelund@microchip.com>
>> M: Microchip Linux Driver Support <UNGLinuxDriver@microchip.com>
>> L: linux-arm-kernel@lists.infradead.org (moderated for
>> non-subscribers)
>> +F: arch/arm64/boot/dts/microchip/
>> N: sparx5
>> S: Supported
>>
>> diff --git a/arch/arm64/boot/dts/Makefile
>> b/arch/arm64/boot/dts/Makefile
>> index f19b762c008d8..9680a7f20c307 100644
>> --- a/arch/arm64/boot/dts/Makefile
>> +++ b/arch/arm64/boot/dts/Makefile
>> @@ -17,6 +17,7 @@ subdir-y += intel
>> subdir-y += lg
>> subdir-y += marvell
>> subdir-y += mediatek
>> +subdir-y += microchip
>> subdir-y += nvidia
>> subdir-y += qcom
>> subdir-y += realtek
>> diff --git a/arch/arm64/boot/dts/microchip/Makefile
>> b/arch/arm64/boot/dts/microchip/Makefile
>> new file mode 100644
>> index 0000000000000..c6e0313eea0f9
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/microchip/Makefile
>> @@ -0,0 +1,4 @@
>> +# SPDX-License-Identifier: GPL-2.0
>> +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb125.dtb
>> +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb134.dtb sparx5_pcb134_emmc.dtb
>> +dtb-$(CONFIG_ARCH_SPARX5) += sparx5_pcb135.dtb sparx5_pcb135_emmc.dtb
>> diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
>> b/arch/arm64/boot/dts/microchip/sparx5.dtsi
>> new file mode 100644
>> index 0000000000000..3136b4369f507
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
>> @@ -0,0 +1,135 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
>> + */
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +/ {
>> + compatible = "microchip,sparx5";
>> + interrupt-parent = <&gic>;
>> + #address-cells = <2>;
>> + #size-cells = <1>;
>> +
>> + aliases {
>> + serial0 = &uart0;
>> + serial1 = &uart1;
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + cpus {
>> + #address-cells = <2>;
>> + #size-cells = <0>;
>> + cpu-map {
>> + cluster0 {
>> + core0 {
>> + cpu = <&cpu0>;
>> + };
>> + core1 {
>> + cpu = <&cpu1>;
>> + };
>> + };
>> + };
>> + cpu0: cpu@0 {
>> + compatible = "arm,cortex-a53", "arm,armv8";
>> + device_type = "cpu";
>> + reg = <0x0 0x0>;
>> + enable-method = "spin-table";
>
> Really? This is 2020, not 2012 any more. Surely a new platform
> boots using PSCI, and not *this*.
>
We don't currently support PSCI. The platform does not have TrustZone,
hence we don't use ATF.
We use U-Boot as the (only) bootloader, providing the spintable. I looked
at adding PSCI (in U-Boot) initially, but as most other platforms were
using ATF the PSCI support was buggy and caused me to go for spintable.
Is spintable being deprecated?
>> + cpu-release-addr = <0x0 0x0000fff8>;
>> + next-level-cache = <&L2_0>;
>> + };
>> + cpu1: cpu@1 {
>> + compatible = "arm,cortex-a53", "arm,armv8";
>> + device_type = "cpu";
>> + reg = <0x0 0x1>;
>> + enable-method = "spin-table";
>> + cpu-release-addr = <0x0 0x0000fff8>;
>> + next-level-cache = <&L2_0>;
>> + };
>> + L2_0: l2-cache0 {
>> + compatible = "cache";
>> + };
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts =
>> + <GIC_PPI 13
>> + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 14
>> + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 11
>> + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 10
>> + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
>
> You have a GICv3. These interrupt specifiers are not the ones GICv3
> expects.
I'll go back and look at this.
>
>> + };
>> +
>> + clocks: clocks {
>> + #address-cells = <2>;
>> + #size-cells = <1>;
>> + ranges;
>> + ahb_clk: ahb-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <250000000>;
>> + };
>> + sys_clk: sys-clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <625000000>;
>> + };
>> + };
>> +
>> + axi: axi@600000000 {
>> + compatible = "simple-bus";
>> + #address-cells = <2>;
>> + #size-cells = <1>;
>> + ranges;
>> +
>> + gic: interrupt-controller@600300000 {
>> + compatible = "arm,gic-v3";
>> + #interrupt-cells = <3>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + interrupt-controller;
>> + reg = <0x6 0x00300000 0x20000>, /* GICD */
>> + <0x6 0x00340000 0x1000000>; /* GICR */
>
> You are missing the GICv3 compatibility interfaces (GICV/GICH), which
> are implemented by the CPUs.
I'll get these sorted out.
>
>> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + uart0: serial@600100000 {
>> + compatible = "ns16550a";
>> + reg = <0x6 0x00100000 0x20>;
>> + clocks = <&ahb_clk>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + status = "disabled";
>> + };
>> +
>> + uart1: serial@600102000 {
>> + compatible = "ns16550a";
>> + reg = <0x6 0x00102000 0x20>;
>> + clocks = <&ahb_clk>;
>> + reg-io-width = <4>;
>> + reg-shift = <2>;
>> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + status = "disabled";
>> + };
>> +
>> + timer1: timer@600105000 {
>> + compatible = "snps,dw-apb-timer";
>> + reg = <0x6 0x00105000 0x1000>;
>> + clocks = <&ahb_clk>;
>> + clock-names = "timer";
>> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> + };
>> +};
>
> Where is the PMU node?
>
I'll add the PMU node.
Thank you for your comments!
> Thanks,
>
> M.
--
Lars Povlsen,
Microchip
^ permalink raw reply
* [PATCH 08/17] dt-bindings: ata: renesas,rcar-sata: Add r8a7742 support
From: Lad Prabhakar @ 2020-05-15 15:08 UTC (permalink / raw)
To: Geert Uytterhoeven, Jens Axboe, Rob Herring, Wolfram Sang,
Ulf Hansson, Sergei Shtylyov, David S. Miller, Wim Van Sebroeck,
Guenter Roeck
Cc: linux-ide, devicetree, linux-kernel, linux-i2c, linux-mmc, netdev,
linux-renesas-soc, linux-watchdog, Prabhakar, Lad Prabhakar
In-Reply-To: <1589555337-5498-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
Document SATA support for the RZ/G1H, which is compatible with
R-Car Gen2 SoC family.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
---
Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml b/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml
index 7b69831..d06096a 100644
--- a/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml
+++ b/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml
@@ -17,6 +17,7 @@ properties:
- renesas,sata-r8a7779 # R-Car H1
- items:
- enum:
+ - renesas,sata-r8a7742 # RZ/G1H
- renesas,sata-r8a7790-es1 # R-Car H2 ES1
- renesas,sata-r8a7790 # R-Car H2 other than ES1
- renesas,sata-r8a7791 # R-Car M2-W
--
2.7.4
^ permalink raw reply related
* [PATCH 10/17] dt-bindings: net: renesas,ravb: Add support for r8a7742 SoC
From: Lad Prabhakar @ 2020-05-15 15:08 UTC (permalink / raw)
To: Geert Uytterhoeven, Jens Axboe, Rob Herring, Wolfram Sang,
Ulf Hansson, Sergei Shtylyov, David S. Miller, Wim Van Sebroeck,
Guenter Roeck
Cc: linux-ide, devicetree, linux-kernel, linux-i2c, linux-mmc, netdev,
linux-renesas-soc, linux-watchdog, Prabhakar, Lad Prabhakar
In-Reply-To: <1589555337-5498-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
Document RZ/G1H (R8A7742) SoC bindings.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
---
Documentation/devicetree/bindings/net/renesas,ravb.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/renesas,ravb.txt b/Documentation/devicetree/bindings/net/renesas,ravb.txt
index 87dad2d..032b76f 100644
--- a/Documentation/devicetree/bindings/net/renesas,ravb.txt
+++ b/Documentation/devicetree/bindings/net/renesas,ravb.txt
@@ -5,6 +5,7 @@ interface contains.
Required properties:
- compatible: Must contain one or more of the following:
+ - "renesas,etheravb-r8a7742" for the R8A7742 SoC.
- "renesas,etheravb-r8a7743" for the R8A7743 SoC.
- "renesas,etheravb-r8a7744" for the R8A7744 SoC.
- "renesas,etheravb-r8a7745" for the R8A7745 SoC.
--
2.7.4
^ permalink raw reply related
* [PATCH 09/17] ARM: dts: r8a7742: Add sata nodes
From: Lad Prabhakar @ 2020-05-15 15:08 UTC (permalink / raw)
To: Geert Uytterhoeven, Jens Axboe, Rob Herring, Wolfram Sang,
Ulf Hansson, Sergei Shtylyov, David S. Miller, Wim Van Sebroeck,
Guenter Roeck
Cc: linux-ide, devicetree, linux-kernel, linux-i2c, linux-mmc, netdev,
linux-renesas-soc, linux-watchdog, Prabhakar, Lad Prabhakar
In-Reply-To: <1589555337-5498-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
Add the sata devices nodes to the R8A7742 device tree.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index ca1a016..553b92f 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -809,6 +809,28 @@
max-frequency = <97500000>;
};
+ sata0: sata@ee300000 {
+ compatible = "renesas,sata-r8a7742",
+ "renesas,rcar-gen2-sata";
+ reg = <0 0xee300000 0 0x200000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 815>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 815>;
+ status = "disabled";
+ };
+
+ sata1: sata@ee500000 {
+ compatible = "renesas,sata-r8a7742",
+ "renesas,rcar-gen2-sata";
+ reg = <0 0xee500000 0 0x200000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 814>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 814>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.7.4
^ permalink raw reply related
* [PATCH 11/17] dt-bindings: net: renesas,ether: Document R8A7742 SoC
From: Lad Prabhakar @ 2020-05-15 15:08 UTC (permalink / raw)
To: Geert Uytterhoeven, Jens Axboe, Rob Herring, Wolfram Sang,
Ulf Hansson, Sergei Shtylyov, David S. Miller, Wim Van Sebroeck,
Guenter Roeck
Cc: linux-ide, devicetree, linux-kernel, linux-i2c, linux-mmc, netdev,
linux-renesas-soc, linux-watchdog, Prabhakar, Lad Prabhakar
In-Reply-To: <1589555337-5498-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
Document RZ/G1H (R8A7742) SoC bindings.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
---
Documentation/devicetree/bindings/net/renesas,ether.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/net/renesas,ether.yaml b/Documentation/devicetree/bindings/net/renesas,ether.yaml
index c11eeb6..ce307e8 100644
--- a/Documentation/devicetree/bindings/net/renesas,ether.yaml
+++ b/Documentation/devicetree/bindings/net/renesas,ether.yaml
@@ -29,6 +29,7 @@ properties:
- renesas,rcar-gen1-ether # a generic R-Car Gen1 device
- items:
- enum:
+ - renesas,ether-r8a7742 # device is a part of R8A7742 SoC
- renesas,ether-r8a7743 # device is a part of R8A7743 SoC
- renesas,ether-r8a7745 # device is a part of R8A7745 SoC
- renesas,ether-r8a7790 # device is a part of R8A7790 SoC
--
2.7.4
^ permalink raw reply related
* [PATCH 12/17] ARM: dts: r8a7742: Add Ethernet AVB support
From: Lad Prabhakar @ 2020-05-15 15:08 UTC (permalink / raw)
To: Geert Uytterhoeven, Jens Axboe, Rob Herring, Wolfram Sang,
Ulf Hansson, Sergei Shtylyov, David S. Miller, Wim Van Sebroeck,
Guenter Roeck
Cc: linux-ide, devicetree, linux-kernel, linux-i2c, linux-mmc, netdev,
linux-renesas-soc, linux-watchdog, Prabhakar, Lad Prabhakar
In-Reply-To: <1589555337-5498-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
Add Ethernet AVB support for R8A7742 SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index 553b92f..925bc8a 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -547,6 +547,19 @@
dma-channels = <15>;
};
+ avb: ethernet@e6800000 {
+ compatible = "renesas,etheravb-r8a7742",
+ "renesas,etheravb-rcar-gen2";
+ reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 812>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
scifa0: serial@e6c40000 {
compatible = "renesas,scifa-r8a7742",
"renesas,rcar-gen2-scifa", "renesas,scifa";
--
2.7.4
^ permalink raw reply related
* [PATCH 13/17] ARM: dts: r8a7742: Add Ether support
From: Lad Prabhakar @ 2020-05-15 15:08 UTC (permalink / raw)
To: Geert Uytterhoeven, Jens Axboe, Rob Herring, Wolfram Sang,
Ulf Hansson, Sergei Shtylyov, David S. Miller, Wim Van Sebroeck,
Guenter Roeck
Cc: linux-ide, devicetree, linux-kernel, linux-i2c, linux-mmc, netdev,
linux-renesas-soc, linux-watchdog, Prabhakar, Lad Prabhakar
In-Reply-To: <1589555337-5498-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
Define the generic R8A7742 part of the Ether device node.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index 925bc8a..1fe65f7 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -844,6 +844,20 @@
status = "disabled";
};
+ ether: ethernet@ee700000 {
+ compatible = "renesas,ether-r8a7742",
+ "renesas,rcar-gen2-ether";
+ reg = <0 0xee700000 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 813>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@f1001000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.7.4
^ permalink raw reply related
* [PATCH 14/17] dt-bindings: power: renesas,apmu: Document r8a7742 support
From: Lad Prabhakar @ 2020-05-15 15:08 UTC (permalink / raw)
To: Geert Uytterhoeven, Jens Axboe, Rob Herring, Wolfram Sang,
Ulf Hansson, Sergei Shtylyov, David S. Miller, Wim Van Sebroeck,
Guenter Roeck
Cc: linux-ide, devicetree, linux-kernel, linux-i2c, linux-mmc, netdev,
linux-renesas-soc, linux-watchdog, Prabhakar, Lad Prabhakar
In-Reply-To: <1589555337-5498-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
Document APMU and SMP enable method for RZ/G1H (also known as r8a7742)
SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
---
Documentation/devicetree/bindings/power/renesas,apmu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/power/renesas,apmu.yaml b/Documentation/devicetree/bindings/power/renesas,apmu.yaml
index 078b2cb..60a23b3 100644
--- a/Documentation/devicetree/bindings/power/renesas,apmu.yaml
+++ b/Documentation/devicetree/bindings/power/renesas,apmu.yaml
@@ -18,6 +18,7 @@ properties:
compatible:
items:
- enum:
+ - renesas,r8a7742-apmu # RZ/G1H
- renesas,r8a7743-apmu # RZ/G1M
- renesas,r8a7744-apmu # RZ/G1N
- renesas,r8a7745-apmu # RZ/G1E
--
2.7.4
^ permalink raw reply related
* [PATCH 16/17] dt-bindings: watchdog: renesas,wdt: Document r8a7742 support
From: Lad Prabhakar @ 2020-05-15 15:08 UTC (permalink / raw)
To: Geert Uytterhoeven, Jens Axboe, Rob Herring, Wolfram Sang,
Ulf Hansson, Sergei Shtylyov, David S. Miller, Wim Van Sebroeck,
Guenter Roeck
Cc: linux-ide, devicetree, linux-kernel, linux-i2c, linux-mmc, netdev,
linux-renesas-soc, linux-watchdog, Prabhakar, Lad Prabhakar
In-Reply-To: <1589555337-5498-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
RZ/G1H (R8A7742) watchdog implementation is compatible with R-Car Gen2,
therefore add relevant documentation.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
---
Documentation/devicetree/bindings/watchdog/renesas,wdt.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt b/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
index 79b3c62..e42fd30 100644
--- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
@@ -5,6 +5,7 @@ Required properties:
fallback compatible string when compatible with the generic
version.
Examples with soctypes are:
+ - "renesas,r8a7742-wdt" (RZ/G1H)
- "renesas,r8a7743-wdt" (RZ/G1M)
- "renesas,r8a7744-wdt" (RZ/G1N)
- "renesas,r8a7745-wdt" (RZ/G1E)
--
2.7.4
^ permalink raw reply related
* [PATCH 15/17] ARM: dts: r8a7742: Add APMU nodes
From: Lad Prabhakar @ 2020-05-15 15:08 UTC (permalink / raw)
To: Geert Uytterhoeven, Jens Axboe, Rob Herring, Wolfram Sang,
Ulf Hansson, Sergei Shtylyov, David S. Miller, Wim Van Sebroeck,
Guenter Roeck
Cc: linux-ide, devicetree, linux-kernel, linux-i2c, linux-mmc, netdev,
linux-renesas-soc, linux-watchdog, Prabhakar, Lad Prabhakar
In-Reply-To: <1589555337-5498-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
Add DT nodes for the Advanced Power Management Units (APMU), and use the
enable-method to point out that the APMU should be used for SMP support.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index 1fe65f7..da75767 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -18,6 +18,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -305,6 +306,18 @@
#reset-cells = <1>;
};
+ apmu@e6151000 {
+ compatible = "renesas,r8a7742-apmu", "renesas,apmu";
+ reg = <0 0xe6151000 0 0x188>;
+ cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ };
+
+ apmu@e6152000 {
+ compatible = "renesas,r8a7742-apmu", "renesas,apmu";
+ reg = <0 0xe6152000 0 0x188>;
+ cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ };
+
rst: reset-controller@e6160000 {
compatible = "renesas,r8a7742-rst";
reg = <0 0xe6160000 0 0x0100>;
--
2.7.4
^ permalink raw reply related
* [PATCH 17/17] ARM: dts: r8a7742: Add RWDT node
From: Lad Prabhakar @ 2020-05-15 15:08 UTC (permalink / raw)
To: Geert Uytterhoeven, Jens Axboe, Rob Herring, Wolfram Sang,
Ulf Hansson, Sergei Shtylyov, David S. Miller, Wim Van Sebroeck,
Guenter Roeck
Cc: linux-ide, devicetree, linux-kernel, linux-i2c, linux-mmc, netdev,
linux-renesas-soc, linux-watchdog, Prabhakar, Lad Prabhakar
In-Reply-To: <1589555337-5498-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com>
Add a device node for the Watchdog Timer (RWDT) controller on the Renesas
RZ/G1H (r8a7742) SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
---
arch/arm/boot/dts/r8a7742.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi
index da75767..ea39c20 100644
--- a/arch/arm/boot/dts/r8a7742.dtsi
+++ b/arch/arm/boot/dts/r8a7742.dtsi
@@ -201,6 +201,16 @@
#size-cells = <2>;
ranges;
+ rwdt: watchdog@e6020000 {
+ compatible = "renesas,r8a7742-wdt",
+ "renesas,rcar-gen2-wdt";
+ reg = <0 0xe6020000 0 0x0c>;
+ clocks = <&cpg CPG_MOD 402>;
+ power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
+ resets = <&cpg 402>;
+ status = "disabled";
+ };
+
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7742",
"renesas,rcar-gen2-gpio";
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v2 18/19] spi: dw: Use regset32 DebugFS method to create regdump file
From: Andy Shevchenko @ 2020-05-15 15:10 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, Wan Ahmad Zainie, Charles Keepax,
Clement Leger, wuxu.wu, Phil Edworthy, Thomas Gleixner,
Jarkko Nikula, linux-spi, linux-kernel
In-Reply-To: <20200515104758.6934-19-Sergey.Semin@baikalelectronics.ru>
On Fri, May 15, 2020 at 01:47:57PM +0300, Serge Semin wrote:
> DebugFS kernel interface provides a dedicated method to create the
> registers dump file. Use it instead of creating a generic DebugFS
> file with manually written read callback function.
With below nit addressed,
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> ---
> drivers/spi/spi-dw.c | 86 ++++++++++++++------------------------------
> drivers/spi/spi-dw.h | 2 ++
> 2 files changed, 28 insertions(+), 60 deletions(-)
>
> diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
> index 31607b40147d..bb470cff40d3 100644
> --- a/drivers/spi/spi-dw.c
> +++ b/drivers/spi/spi-dw.c
> @@ -29,66 +29,29 @@ struct chip_data {
> };
>
> #ifdef CONFIG_DEBUG_FS
> -#define SPI_REGS_BUFSIZE 1024
> -static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
> - size_t count, loff_t *ppos)
> -{
> - struct dw_spi *dws = file->private_data;
> - char *buf;
> - u32 len = 0;
> - ssize_t ret;
> -
> - buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
> - if (!buf)
> - return 0;
> -
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "%s registers:\n", dev_name(&dws->master->dev));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "=================================\n");
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "CTRLR0: \t0x%08x\n", dw_readl(dws, DW_SPI_CTRLR0));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "CTRLR1: \t0x%08x\n", dw_readl(dws, DW_SPI_CTRLR1));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFTLR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFTLR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
> - len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
> - "=================================\n");
> -
> - ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
> - kfree(buf);
> - return ret;
> +
> +#define DW_SPI_DBGFS_REG(_name, _off) \
> +{ \
> + .name = _name, \
> + .offset = _off \
As previously discussed (did I miss your answer?) the comma at the end leaves
better pattern for maintenance prospective.
> }
>
> -static const struct file_operations dw_spi_regs_ops = {
> - .owner = THIS_MODULE,
> - .open = simple_open,
> - .read = dw_spi_show_regs,
> - .llseek = default_llseek,
> +static const struct debugfs_reg32 dw_spi_dbgfs_regs[] = {
> + DW_SPI_DBGFS_REG("CTRLR0", DW_SPI_CTRLR0),
> + DW_SPI_DBGFS_REG("CTRLR1", DW_SPI_CTRLR1),
> + DW_SPI_DBGFS_REG("SSIENR", DW_SPI_SSIENR),
> + DW_SPI_DBGFS_REG("SER", DW_SPI_SER),
> + DW_SPI_DBGFS_REG("BAUDR", DW_SPI_BAUDR),
> + DW_SPI_DBGFS_REG("TXFTLR", DW_SPI_TXFTLR),
> + DW_SPI_DBGFS_REG("RXFTLR", DW_SPI_RXFTLR),
> + DW_SPI_DBGFS_REG("TXFLR", DW_SPI_TXFLR),
> + DW_SPI_DBGFS_REG("RXFLR", DW_SPI_RXFLR),
> + DW_SPI_DBGFS_REG("SR", DW_SPI_SR),
> + DW_SPI_DBGFS_REG("IMR", DW_SPI_IMR),
> + DW_SPI_DBGFS_REG("ISR", DW_SPI_ISR),
> + DW_SPI_DBGFS_REG("DMACR", DW_SPI_DMACR),
> + DW_SPI_DBGFS_REG("DMATDLR", DW_SPI_DMATDLR),
> + DW_SPI_DBGFS_REG("DMARDLR", DW_SPI_DMARDLR)
> };
>
> static int dw_spi_debugfs_init(struct dw_spi *dws)
> @@ -100,8 +63,11 @@ static int dw_spi_debugfs_init(struct dw_spi *dws)
> if (!dws->debugfs)
> return -ENOMEM;
>
> - debugfs_create_file("registers", S_IFREG | S_IRUGO,
> - dws->debugfs, (void *)dws, &dw_spi_regs_ops);
> + dws->regset.regs = dw_spi_dbgfs_regs;
> + dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs);
> + dws->regset.base = dws->regs;
> + debugfs_create_regset32("registers", 0400, dws->debugfs, &dws->regset);
> +
> return 0;
> }
>
> diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
> index 24462b0c65cb..4adce6da6013 100644
> --- a/drivers/spi/spi-dw.h
> +++ b/drivers/spi/spi-dw.h
> @@ -2,6 +2,7 @@
> #ifndef DW_SPI_HEADER_H
> #define DW_SPI_HEADER_H
>
> +#include <linux/debugfs.h>
> #include <linux/irqreturn.h>
> #include <linux/io.h>
> #include <linux/scatterlist.h>
> @@ -150,6 +151,7 @@ struct dw_spi {
>
> #ifdef CONFIG_DEBUG_FS
> struct dentry *debugfs;
> + struct debugfs_regset32 regset;
> #endif
> };
>
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* [PATCH 00/17] RZ/G1H describe I2C, IIC, MMC0, SATA, AVB, RWDT and APMU nodes
From: Lad Prabhakar @ 2020-05-15 15:08 UTC (permalink / raw)
To: Geert Uytterhoeven, Jens Axboe, Rob Herring, Wolfram Sang,
Ulf Hansson, Sergei Shtylyov, David S. Miller, Wim Van Sebroeck,
Guenter Roeck
Cc: linux-ide, devicetree, linux-kernel, linux-i2c, linux-mmc, netdev,
linux-renesas-soc, linux-watchdog, Prabhakar, Lad Prabhakar
Hi All,
This patch series describes i2c, iic, mmc0, sdhi, sata, AVB, apmu and
RWDT on R8A7742 SoC.
Cheers,
Prabhakar
Lad Prabhakar (17):
dt-bindings: i2c: renesas,i2c: Document r8a7742 support
dt-bindings: i2c: renesas,iic: Document r8a7742 support
ARM: dts: r8a7742: Add I2C and IIC support
dt-bindings: mmc: renesas,sdhi: Document r8a7742 support
mmc: renesas_sdhi_sys_dmac: Add support for r8a7742 SoC
ARM: dts: r8a7742: Add SDHI nodes
ARM: dts: r8a7742: Add MMC0 node
dt-bindings: ata: renesas,rcar-sata: Add r8a7742 support
ARM: dts: r8a7742: Add sata nodes
dt-bindings: net: renesas,ravb: Add support for r8a7742 SoC
dt-bindings: net: renesas,ether: Document R8A7742 SoC
ARM: dts: r8a7742: Add Ethernet AVB support
ARM: dts: r8a7742: Add Ether support
dt-bindings: power: renesas,apmu: Document r8a7742 support
ARM: dts: r8a7742: Add APMU nodes
dt-bindings: watchdog: renesas,wdt: Document r8a7742 support
ARM: dts: r8a7742: Add RWDT node
.../devicetree/bindings/ata/renesas,rcar-sata.yaml | 1 +
.../devicetree/bindings/i2c/renesas,i2c.txt | 1 +
.../devicetree/bindings/i2c/renesas,iic.txt | 1 +
.../devicetree/bindings/mmc/renesas,sdhi.txt | 1 +
.../devicetree/bindings/net/renesas,ether.yaml | 1 +
.../devicetree/bindings/net/renesas,ravb.txt | 1 +
.../devicetree/bindings/power/renesas,apmu.yaml | 1 +
.../devicetree/bindings/watchdog/renesas,wdt.txt | 1 +
arch/arm/boot/dts/r8a7742.dtsi | 270 +++++++++++++++++++++
drivers/mmc/host/renesas_sdhi_sys_dmac.c | 1 +
10 files changed, 279 insertions(+)
--
2.7.4
^ permalink raw reply
* Re: [PATCH v2 17/19] spi: dw: Add DMA support to the DW SPI MMIO driver
From: Andy Shevchenko @ 2020-05-15 15:08 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, Wan Ahmad Zainie, Jarkko Nikula, Jay Fang,
Thomas Gleixner, YueHaibing, Stephen Boyd, linux-spi,
linux-kernel
In-Reply-To: <20200515104758.6934-18-Sergey.Semin@baikalelectronics.ru>
On Fri, May 15, 2020 at 01:47:56PM +0300, Serge Semin wrote:
> Since the common code in the spi-dw-dma.c driver is ready to be used
> by the MMIO driver and now provides a method to generically (on any
> DT or ACPI-based platforms) retrieve the Tx/Rx DMA channel handlers,
> we can use it and a set of the common DW SPI DMA callbacks to enable
> DMA at least for generic "snps,dw-apb-ssi" and "snps,dwc-ssi-1.01a"
> devices.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>
> Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> ---
> drivers/spi/spi-dw-mmio.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
> index 0894b4c09496..e23d0c53a664 100644
> --- a/drivers/spi/spi-dw-mmio.c
> +++ b/drivers/spi/spi-dw-mmio.c
> @@ -149,6 +149,8 @@ static int dw_spi_dw_apb_init(struct platform_device *pdev,
> /* Register hook to configure CTRLR0 */
> dwsmmio->dws.update_cr0 = dw_spi_update_cr0;
>
> + dw_spi_dma_setup_generic(&dwsmmio->dws);
> +
> return 0;
> }
>
> @@ -158,6 +160,8 @@ static int dw_spi_dwc_ssi_init(struct platform_device *pdev,
> /* Register hook to configure CTRLR0 */
> dwsmmio->dws.update_cr0 = dw_spi_update_cr0_v1_01a;
>
> + dw_spi_dma_setup_generic(&dwsmmio->dws);
> +
> return 0;
> }
>
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v2 15/19] spi: dw: Add DW SPI DMA/PCI/MMIO dependency on the DW SPI core
From: Andy Shevchenko @ 2020-05-15 15:03 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Allison Randal, Gareth Williams, Rob Herring,
linux-mips, devicetree, John Garry, Chuanhong Guo,
Masahisa Kojima, Chris Packham, Tomer Maimon, Krzysztof Kozlowski,
linux-spi, linux-kernel
In-Reply-To: <20200515104758.6934-16-Sergey.Semin@baikalelectronics.ru>
On Fri, May 15, 2020 at 01:47:54PM +0300, Serge Semin wrote:
> Seeing all of the DW SPI driver components like DW SPI DMA/PCI/MMIO
> depend on the DW SPI core code it's better to use the if-endif
> conditional kernel config statement to signify that common dependency.
Makes sense!
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>
> Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> ---
> drivers/spi/Kconfig | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 6a84f3dad35c..3cdf8310d185 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -226,17 +226,20 @@ config SPI_DESIGNWARE
> help
> general driver for SPI controller core from DesignWare
>
> +if SPI_DESIGNWARE
> +
> config SPI_DW_DMA
> bool "DMA support for DW SPI controller"
> - depends on SPI_DESIGNWARE
>
> config SPI_DW_PCI
> tristate "PCI interface driver for DW SPI core"
> - depends on SPI_DESIGNWARE && PCI
> + depends on PCI
>
> config SPI_DW_MMIO
> tristate "Memory-mapped io interface driver for DW SPI core"
> - depends on SPI_DESIGNWARE
> + depends on HAS_IOMEM
> +
> +endif
>
> config SPI_DLN2
> tristate "Diolan DLN-2 USB SPI adapter"
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v2 14/19] spi: dw: Remove DW DMA code dependency from DW_DMAC_PCI
From: Andy Shevchenko @ 2020-05-15 15:02 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Rob Herring, Arnd Bergmann, Allison Randal, Gareth Williams,
linux-mips, devicetree, John Garry, Chuanhong Guo,
Gregory CLEMENT, Chris Packham, Masahisa Kojima, Tomer Maimon,
Krzysztof Kozlowski, linux-spi, linux-kernel
In-Reply-To: <20200515104758.6934-15-Sergey.Semin@baikalelectronics.ru>
On Fri, May 15, 2020 at 01:47:53PM +0300, Serge Semin wrote:
> Since there is a generic method available to initialize the DW SPI DMA
> interface on any DT and ACPI-based platforms, which in general can be
> designed with not only DW DMAC but with any DMA engine on board, we can
> freely remove the CONFIG_DW_DMAC_PCI config from dependency list of
> CONFIG_SPI_DW_DMA. Especially seeing that we don't use anything DW DMAC
> specific in the new driver.
Right, and used data structures are always available at compile time.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Allison Randal <allison@lohutok.net>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Gareth Williams <gareth.williams.jx@renesas.com>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> ---
> drivers/spi/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index 03b061975f70..6a84f3dad35c 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -228,7 +228,7 @@ config SPI_DESIGNWARE
>
> config SPI_DW_DMA
> bool "DMA support for DW SPI controller"
> - depends on SPI_DESIGNWARE && DW_DMAC_PCI
> + depends on SPI_DESIGNWARE
>
> config SPI_DW_PCI
> tristate "PCI interface driver for DW SPI core"
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v1 8/9] arm64: dts: actions: Add MMC controller support for S700
From: André Przywara @ 2020-05-15 15:01 UTC (permalink / raw)
To: Amit Singh Tomar, afaerber, manivannan.sadhasivam, robh+dt
Cc: cristian.ciocaltea, linux-arm-kernel, linux-actions, devicetree
In-Reply-To: <1589472657-3930-9-git-send-email-amittomer25@gmail.com>
On 14/05/2020 17:10, Amit Singh Tomar wrote:
Hi,
> This commits adds support for MMC controllers present on Actions S700 SoC,
> there are 3 MMC controllers in this SoC which can be used for accessing
> SD/EMMC/SDIO cards.
>
> Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
> ---
> Changes since RFC:
> * No change.
> ---
> arch/arm64/boot/dts/actions/s700.dtsi | 33 +++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi
> index 56f2f84812cb..3f1fc3e48415 100644
> --- a/arch/arm64/boot/dts/actions/s700.dtsi
> +++ b/arch/arm64/boot/dts/actions/s700.dtsi
> @@ -258,5 +258,38 @@
> dma-requests = <44>;
> clocks = <&cmu CLK_DMAC>;
> };
> +
> + mmc0: mmc@e0210000 {
> + compatible = "actions,owl-mmc";
I was wondering if we should add a SoC specific compatible here, to be
on the safe side. The BSP driver seems to differentiate between S900 and
S700, although it looks like only to cover some misplaced platform setup.
But if we later find a problem, the DTs stay the same, and the driver
can easily be fixed.
So, using "actions,s700-mmc", "actions,owl-mmc" here, adding this combo
to the binding, but leaving the driver alone for now.
Cheers,
Andre
> + reg = <0x0 0xe0210000 0x0 0x4000>;
> + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cmu CLK_SD0>;
> + resets = <&cmu RESET_SD0>;
> + dmas = <&dma 2>;
> + dma-names = "mmc";
> + status = "disabled";
> + };
> +
> + mmc1: mmc@e0214000 {
> + compatible = "actions,owl-mmc";
> + reg = <0x0 0xe0214000 0x0 0x4000>;
> + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cmu CLK_SD1>;
> + resets = <&cmu RESET_SD1>;
> + dmas = <&dma 3>;
> + dma-names = "mmc";
> + status = "disabled";
> + };
> +
> + mmc2: mmc@e0218000 {
> + compatible = "actions,owl-mmc";
> + reg = <0x0 0xe0218000 0x0 0x4000>;
> + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cmu CLK_SD2>;
> + resets = <&cmu RESET_SD2>;
> + dmas = <&dma 4>;
> + dma-names = "mmc";
> + status = "disabled";
> + };
> };
> };
>
^ permalink raw reply
* Re: [PATCH v2 0/7] usb: gadget: udc: atmel: add usb device support for SAM9x60 SoC
From: Alexandre Belloni @ 2020-05-15 15:02 UTC (permalink / raw)
To: cristian.birsan
Cc: balbi, gregkh, nicolas.ferre, ludovic.desroches, robh+dt,
mark.rutland, linux-arm-kernel, linux-usb, devicetree,
linux-kernel
In-Reply-To: <20200515111631.31210-1-cristian.birsan@microchip.com>
Hi,
On 15/05/2020 14:16:24+0300, cristian.birsan@microchip.com wrote:
> From: Cristian Birsan <cristian.birsan@microchip.com>
>
> This patch set adds usb device support for SAM9x60 SoC.
> The DPRAM memory for the USB High Speed Device Port (UDPHS) hardware
> block was increased and the allocation method is changed. This patch
> series simplifies the endpoint allocation scheme to acomodate this SoC
> and the old ones.
>
> Changes in v2:
> - drop the patch that adds reference to pmc for sam9x60
> - use dt-bindings: usb prefix
> - enable usb device in device tree
>
> Claudiu Beznea (1):
> usb: gadget: udc: atmel: use of_find_matching_node_and_match
>
> Cristian Birsan (6):
> dt-bindings: usb: atmel: Update DT bindings documentation for sam9x60
> usb: gadget: udc: atmel: simplify endpoint allocation
> usb: gadget: udc: atmel: use 1 bank endpoints for control transfers
> usb: gadget: udc: atmel: rename errata into caps
> usb: gadget: udc: atmel: update endpoint allocation for sam9x60
> ARM: dts: at91: sam9x60ek: enable usb device
This should probably be rebased on top of
https://lore.kernel.org/linux-arm-kernel/20200507155651.1094142-1-gregory.clement@bootlin.com/
so we avoid having to define the endpoints in the device tree in the
first place.
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCHv1 15/19] power: supply: sbs-battery: add ability to disable charger broadcasts
From: Emil Velikov @ 2020-05-15 14:57 UTC (permalink / raw)
To: Sebastian Reichel
Cc: Sebastian Reichel, Rob Herring, Greg Kroah-Hartman,
Rafael J . Wysocki, linux-pm, devicetree, linux-kernel, kernel,
Jean-Francois Dagenais
In-Reply-To: <20200513185615.508236-16-sebastian.reichel@collabora.com>
On 2020/05/13, Sebastian Reichel wrote:
> From: Jean-Francois Dagenais <jeff.dagenais@gmail.com>
>
> In certain designs, it is possible to add a battery on a populated i2c
> bus without an sbs compliant charger. In that case, the battery will
> un-necessarily and sometimes un-desirably master the bus trying to write
> info in the charger.
Nit: s/un-/un/
>
> It is observed in many occasion that these battery "broadcasts" are even
> corrupting other ongoing master to slave communication. I.e. the
> multi-master support in the battery is inadequate.
>
> Thankfully, the CHARGER_MODE bit allows designers to disable that SBS
> battery behaviour.
>
> This needs to be done once when the battery is first seen on the bus.
>
> Signed-off-by: Jean-Francois Dagenais <jeff.dagenais@gmail.com>
> [rebased code]
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> ---
> @@ -1017,6 +1043,9 @@ static int sbs_probe(struct i2c_client *client,
> }
> chip->i2c_retry_count = chip->i2c_retry_count + 1;
>
> + chip->charger_broadcasts = !of_property_read_bool(client->dev.of_node,
> + "sbs,disable-charger-broadcasts");
> +
This patch adds the of_property_read, only for it to be replaced in the next
patch. Consider flipping the patch order?
-Emil
^ permalink raw reply
* Re: [PATCH v2 08/19] spi: dw: Discard dma_width member of the dw_spi structure
From: Andy Shevchenko @ 2020-05-15 15:00 UTC (permalink / raw)
To: Serge Semin
Cc: Serge Semin, Mark Brown, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Allison Randal, Gareth Williams, Arnd Bergmann, Rob Herring,
linux-mips, devicetree, Jarkko Nikula, Wan Ahmad Zainie,
Thomas Gleixner, Clement Leger, Xinwei Kong, wuxu.wu,
Phil Edworthy, Linus Walleij, linux-spi, linux-kernel
In-Reply-To: <20200515141627.pqdaic6wksatusl6@mobilestation>
On Fri, May 15, 2020 at 05:16:27PM +0300, Serge Semin wrote:
> On Fri, May 15, 2020 at 04:49:56PM +0300, Andy Shevchenko wrote:
> > On Fri, May 15, 2020 at 04:05:59PM +0300, Serge Semin wrote:
> > > On Fri, May 15, 2020 at 04:03:05PM +0300, Andy Shevchenko wrote:
> > > > On Fri, May 15, 2020 at 01:47:47PM +0300, Serge Semin wrote:
> > > > > This member has exactly the same value as n_bytes of the DW SPI private
> > > > > data object, it's calculated at the same point of the transfer method,
> > > > > n_bytes isn't changed during the whole transfer, and they even serve for
> > > > > the same purpose - keep number of bytes per transfer word, though the
> > > > > dma_width is used only to calculate the DMA source/destination addresses
> > > > > width, which n_bytes could be also utilized for. Taking all of these
> > > > > into account let's replace the dma_width member usage with n_bytes one
> > > > > and remove the former.
> > > >
> > > > I've no strong opinion about this.
> > > > So, after addressing one issue below,
> > > > Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> >
> > ...
> >
> > > > > -static enum dma_slave_buswidth convert_dma_width(u32 dma_width) {
> > > > > - if (dma_width == 1)
> > > >
> > > > > +static enum dma_slave_buswidth convert_dma_width(u8 n_bytes) {
> > > >
> > > > It seems somebody (maybe even me) at some point messed up between enum
> > > > definition and function that returns an enum.
> > > >
> > > > For what said, { should be on the separate line.
> > >
> > > See the patch 16/19: "spi: dw: Cleanup generic DW DMA code namings"
> > > in this series.
> >
> > Since you are touching that line here, it makes sense to do it here rather than
> > ping-pong to other patch in very same series.
>
> You didn't open the patch I referred to, did you?
Patches in the series are going on purpose. I look at them in the sequence of
the appearance. But okay, I looked at it and I found what I expected. I think
that you may reorder patch 16 to be one right after renaming module.
> If you did, you would have
> seen that I touched that line there too in the framework of the naming cleanup
> procedure. So please, stop wasting my time with trivial stuff.
Haven't you missed my tag? It means I spent *my* time on *your* stuff. Please,
be respectful to reviewers.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
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