* Re: [PATCH v9 2/4] media: i2c: Add MAX9286 driver
From: Kieran Bingham @ 2020-05-19 8:55 UTC (permalink / raw)
To: Sakari Ailus, Niklas Söderlund
Cc: linux-renesas-soc, linux-media, devicetree, linux-kernel,
Mauro Carvalho Chehab, Kieran Bingham, Laurent Pinchart,
Jacopo Mondi, Niklas Söderlund, Hans Verkuil, Hyun Kwon,
Manivannan Sadhasivam, Rob Herring, Jacopo Mondi,
Laurent Pinchart
In-Reply-To: <20200519081019.GB3877@valkosipuli.retiisi.org.uk>
Hi Sakari,
On 19/05/2020 09:10, Sakari Ailus wrote:
> Hi Kieran,
>
> On Mon, May 18, 2020 at 12:45:18PM +0100, Kieran Bingham wrote:
>> Hi Sakari,
>>
>> There are only fairly minor comments here, fix ups will be included in a
>> v10.
>>
>> Is there anything major blocking integration?
>
> Not that I can see. But please see my comments below.
Thanks,
We might have some more work tidying up the DT validation anyway which
has come too late, and perhaps is going to bump this to v5.9 now anyway.
I can still try but ... ;-S
At least hopefully now we /can/ see a path to integration though.
I probably don't care if it's 5.8 or 5.9 as long as it's not 8.5 ;-)
>>
>> Regards
>>
>> Kieran
>>
>>
>>
>> On 16/05/2020 22:51, Sakari Ailus wrote:
>>> Hi Kieran,
>>>
>>> Thanks for the update.
>>>
>>> On Tue, May 12, 2020 at 04:51:03PM +0100, Kieran Bingham wrote:
>>>
>>> ...
>>>
>>>> +static int max9286_enum_mbus_code(struct v4l2_subdev *sd,
>>>> + struct v4l2_subdev_pad_config *cfg,
>>>> + struct v4l2_subdev_mbus_code_enum *code)
>>>> +{
>>>> + if (code->pad || code->index > 0)
>>>> + return -EINVAL;
>>>> +
>>>> + code->code = MEDIA_BUS_FMT_UYVY8_2X8;
>>>
>>> Why UYVY8_2X8 and not UYVY8_1X16? In general, the single sample / pixel
>>> variant of the format is generally used on the serial busses. This choice
>>> was made when serial busses were introduced.
>>
>> Ok - I presume this doesn't really have much effect anyway, they just
>> have to match for the transmitter/receiver?
>
> In this case, yes. But it's harder to change later, so let's indeed do that
> now.
Yes indeed, I have to change my test scripts for the new configuration
(or we should update the scripts to get the configuration from the
device ;D)
>> But it makes sense to me, so I'll update to the 1x16 variant.
>
> ...
done anyway ;-)
I see the ADV748x is using the 2x8 variants though ... (all the more
reason for our scripts to /get/ the correct version when propagating
formats).
Perhaps I should/could add the 1x16 formats to the ADV748x too. (later)
>>> And as you don't, you also won't know which frequencies are known to be
>>> safe to use. That said, perhaps where this device is used having a random
>>> frequency on that bus could not be an issue. Perhaps.
>>
>> Does this generate a range? or a list of static supported frequencies?
>>
>> We configure the pixel clock based upon the number of cameras connected,
>> and their pixel rates etc ...
>>
>> Are you saying that the frequency of this clock should be validated to
>> be a specific range? or are you talking about a different frequency?
>
> It depends on the system. In general, only frequencies known to be safe
> should be used. If this one has enough shielding to guarantee there won't
> be problems in using a random frequency in the entire range, is there a
> guarantee that will be the case for all systems with this chip?
I have no idea here... Maybe Niklas knows more having dealt more with
the RCar-VIN/CSI parts.
It seems like this is something we can add later if necessary, by
extending the descriptions in the DT?
--
Kieran
^ permalink raw reply
* Re: [PATCH v15 2/2] i2c: core: support bus regulator controlling in adapter
From: Wolfram Sang @ 2020-05-19 8:48 UTC (permalink / raw)
To: Bibby Hsieh
Cc: Bartosz Golaszewski, linux-i2c, tfiga, drinkcat, srv_heupstream,
robh+dt, mark.rutland, devicetree, Rafael J . Wysocki
In-Reply-To: <20200519072729.7268-3-bibby.hsieh@mediatek.com>
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On Tue, May 19, 2020 at 03:27:29PM +0800, Bibby Hsieh wrote:
> Although in the most platforms, the bus power of i2c
> are alway on, some platforms disable the i2c bus power
> in order to meet low power request.
>
> We get and enable bulk regulator in i2c adapter device.
>
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Applied to for-next, thanks! I added Tomasz Rev-by: for you.
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^ permalink raw reply
* Re: [PATCH v15 1/2] dt-binding: i2c: add bus-supply property
From: Wolfram Sang @ 2020-05-19 8:48 UTC (permalink / raw)
To: Bibby Hsieh
Cc: Bartosz Golaszewski, linux-i2c, tfiga, drinkcat, srv_heupstream,
robh+dt, mark.rutland, devicetree, Rafael J . Wysocki
In-Reply-To: <20200519072729.7268-2-bibby.hsieh@mediatek.com>
[-- Attachment #1: Type: text/plain, Size: 334 bytes --]
On Tue, May 19, 2020 at 03:27:28PM +0800, Bibby Hsieh wrote:
> In some platforms, they disable the power-supply of i2c due
> to power consumption reduction. This patch add bus-supply property.
>
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> Acked-by: Rob Herring <robh@kernel.org>
Applied to for-next, thanks!
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^ permalink raw reply
* [PATCH v5 5/5] counter: Add microchip TCB capture counter
From: Kamel Bouhara @ 2020-05-19 8:37 UTC (permalink / raw)
To: William Breathitt Gray, Rob Herring, Mark Rutland, Nicolas Ferre,
Alexandre Belloni, Ludovic Desroches, linux-arm-kernel
Cc: Thomas Petazzoni, linux-input, devicetree, linux-iio,
Kamel Bouhara
In-Reply-To: <20200519083716.938384-1-kamel.bouhara@bootlin.com>
This drivers allows to use the capture mode of the Timer Counter Block
hardware block available in Microchip SoCs through the counter subsystem.
Two functions of the counter are supported for the moment: period
capture and quadrature decoder. The latter is only supported by the
SAMA5 series of SoCs.
For the period capture mode a basic setup has been chosen that will
reset the counter each time the period is actually reached. Of course
the device offers much more possibilities.
For quadrature mode, both channel 0 and 1 must be configured even if we
only capture the position (no revolution/rotation).
Signed-off-by: Kamel Bouhara <kamel.bouhara@bootlin.com>
---
drivers/counter/Kconfig | 11 +
drivers/counter/Makefile | 1 +
drivers/counter/microchip-tcb-capture.c | 397 ++++++++++++++++++++++++
3 files changed, 409 insertions(+)
create mode 100644 drivers/counter/microchip-tcb-capture.c
diff --git a/drivers/counter/Kconfig b/drivers/counter/Kconfig
index c80fa76bb531..2de53ab0dd25 100644
--- a/drivers/counter/Kconfig
+++ b/drivers/counter/Kconfig
@@ -70,4 +70,15 @@ config FTM_QUADDEC
To compile this driver as a module, choose M here: the
module will be called ftm-quaddec.
+config MICROCHIP_TCB_CAPTURE
+ tristate "Microchip Timer Counter Capture driver"
+ depends on HAS_IOMEM && OF
+ select REGMAP_MMIO
+ help
+ Select this option to enable the Microchip Timer Counter Block
+ capture driver.
+
+ To compile this driver as a module, choose M here: the
+ module will be called microchip-tcb-capture.
+
endif # COUNTER
diff --git a/drivers/counter/Makefile b/drivers/counter/Makefile
index 55142d1f4c43..0a393f71e481 100644
--- a/drivers/counter/Makefile
+++ b/drivers/counter/Makefile
@@ -10,3 +10,4 @@ obj-$(CONFIG_STM32_TIMER_CNT) += stm32-timer-cnt.o
obj-$(CONFIG_STM32_LPTIMER_CNT) += stm32-lptimer-cnt.o
obj-$(CONFIG_TI_EQEP) += ti-eqep.o
obj-$(CONFIG_FTM_QUADDEC) += ftm-quaddec.o
+obj-$(CONFIG_MICROCHIP_TCB_CAPTURE) += microchip-tcb-capture.o
diff --git a/drivers/counter/microchip-tcb-capture.c b/drivers/counter/microchip-tcb-capture.c
new file mode 100644
index 000000000000..f7b7743ddb94
--- /dev/null
+++ b/drivers/counter/microchip-tcb-capture.c
@@ -0,0 +1,397 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/**
+ * Copyright (C) 2020 Microchip
+ *
+ * Author: Kamel Bouhara <kamel.bouhara@bootlin.com>
+ */
+#include <linux/clk.h>
+#include <linux/counter.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <soc/at91/atmel_tcb.h>
+
+#define ATMEL_TC_CMR_MASK (ATMEL_TC_LDRA_RISING | ATMEL_TC_LDRB_FALLING | \
+ ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_LDBDIS | \
+ ATMEL_TC_LDBSTOP)
+
+#define ATMEL_TC_QDEN BIT(8)
+#define ATMEL_TC_POSEN BIT(9)
+
+struct mchp_tc_data {
+ const struct atmel_tcb_config *tc_cfg;
+ struct counter_device counter;
+ struct regmap *regmap;
+ int qdec_mode;
+ int num_channels;
+ int channel[2];
+ bool trig_inverted;
+};
+
+enum mchp_tc_count_function {
+ MCHP_TC_FUNCTION_INCREASE,
+ MCHP_TC_FUNCTION_QUADRATURE,
+};
+
+static enum counter_count_function mchp_tc_count_functions[] = {
+ [MCHP_TC_FUNCTION_INCREASE] = COUNTER_COUNT_FUNCTION_INCREASE,
+ [MCHP_TC_FUNCTION_QUADRATURE] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4,
+};
+
+enum mchp_tc_synapse_action {
+ MCHP_TC_SYNAPSE_ACTION_NONE = 0,
+ MCHP_TC_SYNAPSE_ACTION_RISING_EDGE,
+ MCHP_TC_SYNAPSE_ACTION_FALLING_EDGE,
+ MCHP_TC_SYNAPSE_ACTION_BOTH_EDGE
+};
+
+static enum counter_synapse_action mchp_tc_synapse_actions[] = {
+ [MCHP_TC_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
+ [MCHP_TC_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE,
+ [MCHP_TC_SYNAPSE_ACTION_FALLING_EDGE] = COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
+ [MCHP_TC_SYNAPSE_ACTION_BOTH_EDGE] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
+};
+
+static struct counter_signal mchp_tc_count_signals[] = {
+ {
+ .id = 0,
+ .name = "Channel A",
+ },
+ {
+ .id = 1,
+ .name = "Channel B",
+ }
+};
+
+static struct counter_synapse mchp_tc_count_synapses[] = {
+ {
+ .actions_list = mchp_tc_synapse_actions,
+ .num_actions = ARRAY_SIZE(mchp_tc_synapse_actions),
+ .signal = &mchp_tc_count_signals[0]
+ },
+ {
+ .actions_list = mchp_tc_synapse_actions,
+ .num_actions = ARRAY_SIZE(mchp_tc_synapse_actions),
+ .signal = &mchp_tc_count_signals[1]
+ }
+};
+
+static int mchp_tc_count_function_get(struct counter_device *counter,
+ struct counter_count *count,
+ size_t *function)
+{
+ struct mchp_tc_data *const priv = counter->priv;
+
+ if (priv->qdec_mode)
+ *function = MCHP_TC_FUNCTION_QUADRATURE;
+ else
+ *function = MCHP_TC_FUNCTION_INCREASE;
+
+ return 0;
+}
+
+static int mchp_tc_count_function_set(struct counter_device *counter,
+ struct counter_count *count,
+ size_t function)
+{
+ struct mchp_tc_data *const priv = counter->priv;
+ u32 bmr, cmr;
+
+ regmap_read(priv->regmap, ATMEL_TC_BMR, &bmr);
+ regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr);
+
+ /* Set capture mode */
+ cmr &= ~ATMEL_TC_WAVE;
+
+ switch (function) {
+ case MCHP_TC_FUNCTION_INCREASE:
+ priv->qdec_mode = 0;
+ /* Set highest rate based on whether soc has gclk or not */
+ bmr &= ~(ATMEL_TC_QDEN | ATMEL_TC_POSEN);
+ if (priv->tc_cfg->has_gclk)
+ cmr |= ATMEL_TC_TIMER_CLOCK2;
+ else
+ cmr |= ATMEL_TC_TIMER_CLOCK1;
+ /* Setup the period capture mode */
+ cmr |= ATMEL_TC_CMR_MASK;
+ cmr &= ~(ATMEL_TC_ABETRG | ATMEL_TC_XC0);
+ break;
+ case MCHP_TC_FUNCTION_QUADRATURE:
+ if (!priv->tc_cfg->has_qdec)
+ return -EINVAL;
+ /* In QDEC mode settings both channels 0 and 1 are required */
+ if (priv->num_channels < 2 || priv->channel[0] != 0 ||
+ priv->channel[1] != 1) {
+ pr_err("Invalid channels number or id for quadrature mode\n");
+ return -EINVAL;
+ }
+ priv->qdec_mode = 1;
+ bmr |= ATMEL_TC_QDEN | ATMEL_TC_POSEN;
+ cmr |= ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_ABETRG | ATMEL_TC_XC0;
+ break;
+ }
+
+ regmap_write(priv->regmap, ATMEL_TC_BMR, bmr);
+ regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), cmr);
+
+ /* Enable clock and trigger counter */
+ regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CCR),
+ ATMEL_TC_CLKEN | ATMEL_TC_SWTRG);
+
+ if (priv->qdec_mode) {
+ regmap_write(priv->regmap,
+ ATMEL_TC_REG(priv->channel[1], CMR), cmr);
+ regmap_write(priv->regmap,
+ ATMEL_TC_REG(priv->channel[1], CCR),
+ ATMEL_TC_CLKEN | ATMEL_TC_SWTRG);
+ }
+
+ return 0;
+}
+
+static int mchp_tc_count_signal_read(struct counter_device *counter,
+ struct counter_signal *signal,
+ enum counter_signal_value *val)
+{
+ struct mchp_tc_data *const priv = counter->priv;
+ bool sigstatus;
+ u32 sr;
+
+ regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], SR), &sr);
+
+ if (priv->trig_inverted)
+ sigstatus = (sr & ATMEL_TC_MTIOB);
+ else
+ sigstatus = (sr & ATMEL_TC_MTIOA);
+
+ *val = sigstatus ? COUNTER_SIGNAL_HIGH : COUNTER_SIGNAL_LOW;
+
+ return 0;
+}
+
+static int mchp_tc_count_action_get(struct counter_device *counter,
+ struct counter_count *count,
+ struct counter_synapse *synapse,
+ size_t *action)
+{
+ struct mchp_tc_data *const priv = counter->priv;
+ u32 cmr;
+
+ regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr);
+
+ *action = MCHP_TC_SYNAPSE_ACTION_NONE;
+
+ if (cmr & ATMEL_TC_ETRGEDG_NONE)
+ *action = MCHP_TC_SYNAPSE_ACTION_NONE;
+ else if (cmr & ATMEL_TC_ETRGEDG_RISING)
+ *action = MCHP_TC_SYNAPSE_ACTION_RISING_EDGE;
+ else if (cmr & ATMEL_TC_ETRGEDG_FALLING)
+ *action = MCHP_TC_SYNAPSE_ACTION_FALLING_EDGE;
+ else if (cmr & ATMEL_TC_ETRGEDG_BOTH)
+ *action = MCHP_TC_SYNAPSE_ACTION_BOTH_EDGE;
+
+ return 0;
+}
+
+static int mchp_tc_count_action_set(struct counter_device *counter,
+ struct counter_count *count,
+ struct counter_synapse *synapse,
+ size_t action)
+{
+ struct mchp_tc_data *const priv = counter->priv;
+ u32 edge = ATMEL_TC_ETRGEDG_NONE;
+
+ /* QDEC mode is rising edge only */
+ if (priv->qdec_mode)
+ return -EINVAL;
+
+ switch (action) {
+ case MCHP_TC_SYNAPSE_ACTION_NONE:
+ edge = ATMEL_TC_ETRGEDG_NONE;
+ break;
+ case MCHP_TC_SYNAPSE_ACTION_RISING_EDGE:
+ edge = ATMEL_TC_ETRGEDG_RISING;
+ break;
+ case MCHP_TC_SYNAPSE_ACTION_FALLING_EDGE:
+ edge = ATMEL_TC_ETRGEDG_FALLING;
+ break;
+ case MCHP_TC_SYNAPSE_ACTION_BOTH_EDGE:
+ edge = ATMEL_TC_ETRGEDG_BOTH;
+ break;
+ }
+
+ return regmap_write_bits(priv->regmap,
+ ATMEL_TC_REG(priv->channel[0], CMR),
+ ATMEL_TC_ETRGEDG, edge);
+}
+
+static int mchp_tc_count_read(struct counter_device *counter,
+ struct counter_count *count,
+ unsigned long *val)
+{
+ struct mchp_tc_data *const priv = counter->priv;
+ u32 cnt;
+
+ regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CV), &cnt);
+ *val = cnt;
+
+ return 0;
+}
+
+static struct counter_count mchp_tc_counts[] = {
+ {
+ .id = 0,
+ .name = "Timer Counter",
+ .functions_list = mchp_tc_count_functions,
+ .num_functions = ARRAY_SIZE(mchp_tc_count_functions),
+ .synapses = mchp_tc_count_synapses,
+ .num_synapses = ARRAY_SIZE(mchp_tc_count_synapses),
+ },
+};
+
+static struct counter_ops mchp_tc_ops = {
+ .signal_read = mchp_tc_count_signal_read,
+ .count_read = mchp_tc_count_read,
+ .function_get = mchp_tc_count_function_get,
+ .function_set = mchp_tc_count_function_set,
+ .action_get = mchp_tc_count_action_get,
+ .action_set = mchp_tc_count_action_set
+};
+
+static const struct atmel_tcb_config tcb_rm9200_config = {
+ .counter_width = 16,
+};
+
+static const struct atmel_tcb_config tcb_sam9x5_config = {
+ .counter_width = 32,
+};
+
+static const struct atmel_tcb_config tcb_sama5d2_config = {
+ .counter_width = 32,
+ .has_gclk = true,
+ .has_qdec = true,
+};
+
+static const struct atmel_tcb_config tcb_sama5d3_config = {
+ .counter_width = 32,
+ .has_qdec = true,
+};
+
+static const struct of_device_id atmel_tc_of_match[] = {
+ { .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
+ { .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
+ { .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
+ { .compatible = "atmel,sama5d3-tcb", .data = &tcb_sama5d3_config, },
+ { /* sentinel */ }
+};
+
+static void mchp_tc_clk_remove(void *ptr)
+{
+ clk_disable_unprepare((struct clk *)ptr);
+}
+
+static int mchp_tc_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ const struct atmel_tcb_config *tcb_config;
+ const struct of_device_id *match;
+ struct mchp_tc_data *priv;
+ char clk_name[7];
+ struct regmap *regmap;
+ struct clk *clk[3];
+ int channel;
+ int ret, i;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, priv);
+
+ match = of_match_node(atmel_tc_of_match, np->parent);
+ tcb_config = match->data;
+ if (!tcb_config) {
+ dev_err(&pdev->dev, "No matching parent node found\n");
+ return -ENODEV;
+ }
+
+ regmap = syscon_node_to_regmap(np->parent);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ /* max. channels number is 2 when in QDEC mode */
+ priv->num_channels = of_property_count_u32_elems(np, "reg");
+ if (priv->num_channels < 0) {
+ dev_err(&pdev->dev, "Invalid or missing channel\n");
+ return -EINVAL;
+ }
+
+ /* Register channels and initialize clocks */
+ for (i = 0; i < priv->num_channels; i++) {
+ ret = of_property_read_u32_index(np, "reg", i, &channel);
+ if (ret < 0 || channel > 2)
+ return -ENODEV;
+
+ priv->channel[i] = channel;
+
+ snprintf(clk_name, sizeof(clk_name), "t%d_clk", channel);
+
+ clk[i] = of_clk_get_by_name(np->parent, clk_name);
+ if (IS_ERR(clk[i])) {
+ /* Fallback to t0_clk */
+ clk[i] = of_clk_get_by_name(np->parent, "t0_clk");
+ if (IS_ERR(clk[i]))
+ return PTR_ERR(clk[i]);
+ }
+
+ ret = clk_prepare_enable(clk[i]);
+ if (ret)
+ return ret;
+
+ ret = devm_add_action_or_reset(&pdev->dev,
+ mchp_tc_clk_remove,
+ clk[i]);
+ if (ret)
+ return ret;
+
+ dev_dbg(&pdev->dev,
+ "Initialized capture mode on channel %d\n",
+ channel);
+ }
+
+ priv->tc_cfg = tcb_config;
+ priv->regmap = regmap;
+ priv->counter.name = dev_name(&pdev->dev);
+ priv->counter.parent = &pdev->dev;
+ priv->counter.ops = &mchp_tc_ops;
+ priv->counter.num_counts = ARRAY_SIZE(mchp_tc_counts);
+ priv->counter.counts = mchp_tc_counts;
+ priv->counter.num_signals = ARRAY_SIZE(mchp_tc_count_signals);
+ priv->counter.signals = mchp_tc_count_signals;
+ priv->counter.priv = priv;
+
+ return devm_counter_register(&pdev->dev, &priv->counter);
+}
+
+static const struct of_device_id mchp_tc_dt_ids[] = {
+ { .compatible = "microchip,tcb-capture", },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, mchp_tc_dt_ids);
+
+static struct platform_driver mchp_tc_driver = {
+ .probe = mchp_tc_probe,
+ .driver = {
+ .name = "microchip-tcb-capture",
+ .of_match_table = mchp_tc_dt_ids,
+ },
+};
+module_platform_driver(mchp_tc_driver);
+
+MODULE_AUTHOR("Kamel Bouhara <kamel.bouhara@bootlin.com>");
+MODULE_DESCRIPTION("Microchip TCB Capture driver");
+MODULE_LICENSE("GPL v2");
--
2.25.0
^ permalink raw reply related
* [PATCH v5 4/5] dt-bindings: counter: microchip-tcb-capture counter
From: Kamel Bouhara @ 2020-05-19 8:37 UTC (permalink / raw)
To: William Breathitt Gray, Rob Herring, Mark Rutland, Nicolas Ferre,
Alexandre Belloni, Ludovic Desroches, linux-arm-kernel
Cc: Thomas Petazzoni, linux-input, devicetree, linux-iio,
Kamel Bouhara
In-Reply-To: <20200519083716.938384-1-kamel.bouhara@bootlin.com>
Describe the devicetree binding for the Microchip TCB module.
Each counter blocks exposes three independent counters.
However, when configured in quadrature decoder, both channel <0> and <1>
are required for speed/position and rotation capture (yet only the
position is captured).
Signed-off-by: Kamel Bouhara <kamel.bouhara@bootlin.com>
---
.../soc/microchip/atmel,at91rm9200-tcb.yaml | 32 +++++++++++++++++--
1 file changed, 29 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
index 38403760f64d..e3319c4501c1 100644
--- a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
+++ b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
@@ -52,14 +52,20 @@ properties:
patternProperties:
"^timer@[0-2]$":
- description: The timer block channels that are used as timers.
+ description: The timer block channels that are used as timers or counters.
type: object
properties:
compatible:
- const: atmel,tcb-timer
+ items:
+ - enum:
+ - atmel,tcb-timer
+ - microchip,tcb-capture
reg:
description:
- List of channels to use for this particular timer.
+ List of channels to use for this particular timer. In Microchip TCB capture
+ mode channels are registered as a counter devices, for the qdec mode TCB0's
+ channel <0> and <1> are required.
+
minItems: 1
maxItems: 3
@@ -148,3 +154,23 @@ examples:
reg = <1>;
};
};
+ /* TCB0 Capture with QDEC: */
+ timer@f800c000 {
+ compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfff7c000 0x100>;
+ interrupts = <18 4>;
+ clocks = <&tcb0_clk>, <&clk32k>;
+ clock-names = "t0_clk", "slow_clk";
+
+ timer@0 {
+ compatible = "microchip,tcb-capture";
+ reg = <0>, <1>;
+ };
+
+ timer@2 {
+ compatible = "atmel,tcb-timer";
+ reg = <2>;
+ };
+ };
--
2.25.0
^ permalink raw reply related
* [PATCH v5 3/5] dt-bindings: microchip: atmel,at91rm9200-tcb: add sama5d2 compatible
From: Kamel Bouhara @ 2020-05-19 8:37 UTC (permalink / raw)
To: William Breathitt Gray, Rob Herring, Mark Rutland, Nicolas Ferre,
Alexandre Belloni, Ludovic Desroches, linux-arm-kernel
Cc: Thomas Petazzoni, linux-input, devicetree, linux-iio
In-Reply-To: <20200519083716.938384-1-kamel.bouhara@bootlin.com>
From: Alexandre Belloni <alexandre.belloni@bootlin.com>
The sama5d2 TC block TIMER_CLOCK1 is different from the at91sam9x5 one.
Instead of being MCK / 2, it is the TCB GCLK.
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
.../soc/microchip/atmel,at91rm9200-tcb.yaml | 36 +++++++++++++++----
1 file changed, 30 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
index 4b683151265e..38403760f64d 100644
--- a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
+++ b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
@@ -19,6 +19,7 @@ properties:
- enum:
- atmel,at91rm9200-tcb
- atmel,at91sam9x5-tcb
+ - atmel,sama5d2-tcb
- const: simple-mfd
- const: syscon
@@ -38,12 +39,6 @@ properties:
t1_clk and t2_clk if a clock per channel is available.
minItems: 2
maxItems: 4
- items:
- enum:
- - t0_clk
- - t1_clk
- - t2_clk
- - slow_clk
clocks:
minItems: 2
@@ -72,6 +67,35 @@ patternProperties:
- compatible
- reg
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: atmel,sama5d2-tcb
+ then:
+ properties:
+ clocks:
+ minItems: 3
+ maxItems: 3
+ clock-names:
+ items:
+ - const: t0_clk
+ - const: gclk
+ - const: slow_clk
+ else:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 4
+ clock-names:
+ items:
+ enum:
+ - t0_clk
+ - t1_clk
+ - t2_clk
+ - slow_clk
+
required:
- compatible
- reg
--
2.25.0
^ permalink raw reply related
* [PATCH v5 2/5] dt-bindings: atmel-tcb: convert bindings to json-schema
From: Kamel Bouhara @ 2020-05-19 8:37 UTC (permalink / raw)
To: William Breathitt Gray, Rob Herring, Mark Rutland, Nicolas Ferre,
Alexandre Belloni, Ludovic Desroches, linux-arm-kernel
Cc: Thomas Petazzoni, linux-input, devicetree, linux-iio
In-Reply-To: <20200519083716.938384-1-kamel.bouhara@bootlin.com>
From: Alexandre Belloni <alexandre.belloni@bootlin.com>
Convert Atmel Timer Counter Blocks bindings to DT schema format using
json-schema.
Also move it out of mfd as it is not and has never been related to mfd.
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
.../devicetree/bindings/mfd/atmel-tcb.txt | 56 --------
.../soc/microchip/atmel,at91rm9200-tcb.yaml | 126 ++++++++++++++++++
2 files changed, 126 insertions(+), 56 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-tcb.txt
create mode 100644 Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
diff --git a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt b/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
deleted file mode 100644
index c4a83e364cb6..000000000000
--- a/Documentation/devicetree/bindings/mfd/atmel-tcb.txt
+++ /dev/null
@@ -1,56 +0,0 @@
-* Device tree bindings for Atmel Timer Counter Blocks
-- compatible: Should be "atmel,<chip>-tcb", "simple-mfd", "syscon".
- <chip> can be "at91rm9200" or "at91sam9x5"
-- reg: Should contain registers location and length
-- #address-cells: has to be 1
-- #size-cells: has to be 0
-- interrupts: Should contain all interrupts for the TC block
- Note that you can specify several interrupt cells if the TC
- block has one interrupt per channel.
-- clock-names: tuple listing input clock names.
- Required elements: "t0_clk", "slow_clk"
- Optional elements: "t1_clk", "t2_clk"
-- clocks: phandles to input clocks.
-
-The TCB can expose multiple subdevices:
- * a timer
- - compatible: Should be "atmel,tcb-timer"
- - reg: Should contain the TCB channels to be used. If the
- counter width is 16 bits (at91rm9200-tcb), two consecutive
- channels are needed. Else, only one channel will be used.
-
-Examples:
-
-One interrupt per TC block:
- tcb0: timer@fff7c000 {
- compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xfff7c000 0x100>;
- interrupts = <18 4>;
- clocks = <&tcb0_clk>, <&clk32k>;
- clock-names = "t0_clk", "slow_clk";
-
- timer@0 {
- compatible = "atmel,tcb-timer";
- reg = <0>, <1>;
- };
-
- timer@2 {
- compatible = "atmel,tcb-timer";
- reg = <2>;
- };
- };
-
-One interrupt per TC channel in a TC block:
- tcb1: timer@fffdc000 {
- compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xfffdc000 0x100>;
- interrupts = <26 4>, <27 4>, <28 4>;
- clocks = <&tcb1_clk>, <&clk32k>;
- clock-names = "t0_clk", "slow_clk";
- };
-
-
diff --git a/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
new file mode 100644
index 000000000000..4b683151265e
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Atmel Timer Counter Block
+
+maintainers:
+ - Alexandre Belloni <alexandre.belloni@bootlin.com>
+
+description: |
+ The Atmel (now Microchip) SoCs have timers named Timer Counter Block. Each
+ timer has three channels with two counters each.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - atmel,at91rm9200-tcb
+ - atmel,at91sam9x5-tcb
+ - const: simple-mfd
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ List of interrupts. One interrupt per TCB channel if available or one
+ interrupt for the TC block
+ minItems: 1
+ maxItems: 3
+
+ clock-names:
+ description:
+ List of clock names. Always includes t0_clk and slow clk. Also includes
+ t1_clk and t2_clk if a clock per channel is available.
+ minItems: 2
+ maxItems: 4
+ items:
+ enum:
+ - t0_clk
+ - t1_clk
+ - t2_clk
+ - slow_clk
+
+ clocks:
+ minItems: 2
+ maxItems: 4
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+patternProperties:
+ "^timer@[0-2]$":
+ description: The timer block channels that are used as timers.
+ type: object
+ properties:
+ compatible:
+ const: atmel,tcb-timer
+ reg:
+ description:
+ List of channels to use for this particular timer.
+ minItems: 1
+ maxItems: 3
+
+ required:
+ - compatible
+ - reg
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - '#address-cells'
+ - '#size-cells'
+
+examples:
+ - |
+ /* One interrupt per TC block: */
+ tcb0: timer@fff7c000 {
+ compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfff7c000 0x100>;
+ interrupts = <18 4>;
+ clocks = <&tcb0_clk>, <&clk32k>;
+ clock-names = "t0_clk", "slow_clk";
+
+ timer@0 {
+ compatible = "atmel,tcb-timer";
+ reg = <0>, <1>;
+ };
+
+ timer@2 {
+ compatible = "atmel,tcb-timer";
+ reg = <2>;
+ };
+ };
+
+ /* One interrupt per TC channel in a TC block: */
+ tcb1: timer@fffdc000 {
+ compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfffdc000 0x100>;
+ interrupts = <26 4>, <27 4>, <28 4>;
+ clocks = <&tcb1_clk>, <&clk32k>;
+ clock-names = "t0_clk", "slow_clk";
+
+ timer@0 {
+ compatible = "atmel,tcb-timer";
+ reg = <0>;
+ };
+
+ timer@1 {
+ compatible = "atmel,tcb-timer";
+ reg = <1>;
+ };
+ };
--
2.25.0
^ permalink raw reply related
* [PATCH v5 1/5] ARM: at91: add atmel tcb capabilities
From: Kamel Bouhara @ 2020-05-19 8:37 UTC (permalink / raw)
To: William Breathitt Gray, Rob Herring, Mark Rutland, Nicolas Ferre,
Alexandre Belloni, Ludovic Desroches, linux-arm-kernel
Cc: Thomas Petazzoni, linux-input, devicetree, linux-iio,
Kamel Bouhara
In-Reply-To: <20200519083716.938384-1-kamel.bouhara@bootlin.com>
Some atmel socs have extra tcb capabilities that allow using a generic
clock source or enabling a quadrature decoder.
Signed-off-by: Kamel Bouhara <kamel.bouhara@bootlin.com>
---
include/soc/at91/atmel_tcb.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/soc/at91/atmel_tcb.h b/include/soc/at91/atmel_tcb.h
index c3c7200ce151..1d7071dc0bca 100644
--- a/include/soc/at91/atmel_tcb.h
+++ b/include/soc/at91/atmel_tcb.h
@@ -36,9 +36,14 @@ struct clk;
/**
* struct atmel_tcb_config - SoC data for a Timer/Counter Block
* @counter_width: size in bits of a timer counter register
+ * @has_gclk: boolean indicating if a timer counter has a generic clock
+ * @has_qdec: boolean indicating if a timer counter has a quadrature
+ * decoder.
*/
struct atmel_tcb_config {
size_t counter_width;
+ bool has_gclk;
+ bool has_qdec;
};
/**
--
2.25.0
^ permalink raw reply related
* [PATCH v5 0/5] Microchip TCB Capture driver
From: Kamel Bouhara @ 2020-05-19 8:37 UTC (permalink / raw)
To: William Breathitt Gray, Rob Herring, Mark Rutland, Nicolas Ferre,
Alexandre Belloni, Ludovic Desroches, linux-arm-kernel
Cc: Thomas Petazzoni, linux-input, devicetree, linux-iio,
Kamel Bouhara
Hello,
Here is a new counter driver to support Microchip TCB capture devices.
Each SoC has two TCB blocks, each one including three independent
channels.The following series adds support for two counter modes:
increase and quadrature decoder.
As for the atmel clocksource and pwm, the counter driver needs to fill
some tcb capabilities in order to operate with the right configuration.
This is achieved in first patch of this series.
Please feel free to comment.
Cheers,
Changes in v5:
- Fix duplicate keys errors in yaml dt-schema
Changes in v4:
- Use existing binding to document capture mode of the Microchip TCBs.
Changes in v3:
- Updated the brand name: s/atmel/microchip/.
- Added missing kernel doc for new elements introduced in structure
atmel_tcb_config.
- Removed useless blank line
- Added an explicit clock removing path using devm_add_action_or_reset
Changes in v2:
- Fixed first patch not applying on mainline
- Updated return code to -EINVAL when user is requesting qdec mode on
a counter device not supporting it.
- Added an error case returning -EINVAL when action edge is performed
in
qdec mode.
- Removed no need to explicity setting ops to NULL from static struct
as
it is the default value.
- Changed confusing code by using snprintf for the sake of clarity.
- Changed code to use ARRAY_SIZE so that future reviewers will know
that num_counts matches what's in the atmel_tc_count array without
having to check so themselves.
- Fixed errors reported by dt_binding_check
Alexandre Belloni (2):
dt-bindings: atmel-tcb: convert bindings to json-schema
dt-bindings: microchip: atmel,at91rm9200-tcb: add sama5d2 compatible
Kamel Bouhara (3):
ARM: at91: add atmel tcb capabilities
dt-bindings: counter: microchip-tcb-capture counter
counter: Add microchip TCB capture counter
.../devicetree/bindings/mfd/atmel-tcb.txt | 56 ---
.../soc/microchip/atmel,at91rm9200-tcb.yaml | 176 ++++++++
drivers/counter/Kconfig | 11 +
drivers/counter/Makefile | 1 +
drivers/counter/microchip-tcb-capture.c | 397 ++++++++++++++++++
include/soc/at91/atmel_tcb.h | 5 +
6 files changed, 590 insertions(+), 56 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-tcb.txt
create mode 100644 Documentation/devicetree/bindings/soc/microchip/atmel,at91rm9200-tcb.yaml
create mode 100644 drivers/counter/microchip-tcb-capture.c
--
2.25.0
^ permalink raw reply
* Re: [PATCH v8 1/3] dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY
From: Kishon Vijay Abraham I @ 2020-05-19 8:29 UTC (permalink / raw)
To: Laurent Pinchart, linux-kernel
Cc: Anurag Kumar Vulisha, Michal Simek, Vinod Koul, Rob Herring,
devicetree
In-Reply-To: <20200513172239.26444-2-laurent.pinchart@ideasonboard.com>
On 5/13/2020 10:52 PM, Laurent Pinchart wrote:
> From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
>
> Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed
> Processing System Gigabit Transceiver which provides PHY capabilities to
> USB, SATA, PCIE, Display Port and Ehernet SGMII controllers.
>
> Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Need RobH Ack for this to be merged.
Thanks
Kishon
> ---
> Changes since v7:
>
> - Switch to GPL-2.0-only OR BSD-2-Clause
>
> Changes since v6:
>
> - Fixed specification of compatible-dependent xlnx,tx-termination-fix
> property
> - Dropped status property from example
> - Use 4 spaces to indent example
>
> Changes since v5:
>
> - Document clocks and clock-names properties
> - Document resets and reset-names properties
> - Replace subnodes with an additional entry in the PHY cells
> - Drop lane frequency PHY cell, replaced by reference clock phandle
> - Convert bindings to YAML
> - Reword the subject line
> - Drop Rob's R-b as the bindings have significantly changed
> - Drop resets and reset-names properties
> ---
> .../bindings/phy/xlnx,zynqmp-psgtr.yaml | 105 ++++++++++++++++++
> include/dt-bindings/phy/phy.h | 1 +
> 2 files changed, 106 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml b/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
> new file mode 100644
> index 000000000000..09e3cde7ebca
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
> @@ -0,0 +1,105 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx ZynqMP Gigabit Transceiver PHY Device Tree Bindings
> +
> +maintainers:
> + - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> +
> +description: |
> + This binding describes the Xilinx ZynqMP Gigabit Transceiver (GTR) PHY. The
> + GTR provides four lanes and is used by USB, SATA, PCIE, Display port and
> + Ethernet SGMII controllers.
> +
> +properties:
> + "#phy-cells":
> + const: 4
> + description: |
> + The cells contain the following arguments.
> +
> + - description: The GTR lane
> + minimum: 0
> + maximum: 3
> + - description: The PHY type
> + enum:
> + - PHY_TYPE_DP
> + - PHY_TYPE_PCIE
> + - PHY_TYPE_SATA
> + - PHY_TYPE_SGMII
> + - PHY_TYPE_USB
> + - description: The PHY instance
> + minimum: 0
> + maximum: 1 # for DP, SATA or USB
> + maximum: 3 # for PCIE or SGMII
> + - description: The reference clock number
> + minimum: 0
> + maximum: 3
> +
> + compatible:
> + enum:
> + - xlnx,zynqmp-psgtr-v1.1
> + - xlnx,zynqmp-psgtr
> +
> + clocks:
> + minItems: 1
> + maxItems: 4
> + description: |
> + Clock for each PS_MGTREFCLK[0-3] reference clock input. Unconnected
> + inputs shall not have an entry.
> +
> + clock-names:
> + minItems: 1
> + maxItems: 4
> + items:
> + pattern: "^ref[0-3]$"
> +
> + reg:
> + items:
> + - description: SERDES registers block
> + - description: SIOU registers block
> +
> + reg-names:
> + items:
> + - const: serdes
> + - const: siou
> +
> + xlnx,tx-termination-fix:
> + description: |
> + Include this for fixing functional issue with the TX termination
> + resistance in GT, which can be out of spec for the XCZU9EG silicon
> + version.
> + type: boolean
> +
> +required:
> + - "#phy-cells"
> + - compatible
> + - reg
> + - reg-names
> +
> +if:
> + properties:
> + compatible:
> + const: xlnx,zynqmp-psgtr-v1.1
> +
> +then:
> + properties:
> + xlnx,tx-termination-fix: false
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + phy: phy@fd400000 {
> + compatible = "xlnx,zynqmp-psgtr-v1.1";
> + reg = <0x0 0xfd400000 0x0 0x40000>,
> + <0x0 0xfd3d0000 0x0 0x1000>;
> + reg-names = "serdes", "siou";
> + clocks = <&refclks 3>, <&refclks 2>, <&refclks 0>;
> + clock-names = "ref1", "ref2", "ref3";
> + #phy-cells = <4>;
> + };
> +
> +...
> diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h
> index 1f3f866fae7b..f6bc83b66ae9 100644
> --- a/include/dt-bindings/phy/phy.h
> +++ b/include/dt-bindings/phy/phy.h
> @@ -17,5 +17,6 @@
> #define PHY_TYPE_USB3 4
> #define PHY_TYPE_UFS 5
> #define PHY_TYPE_DP 6
> +#define PHY_TYPE_SGMII 7
>
> #endif /* _DT_BINDINGS_PHY */
>
^ permalink raw reply
* Re: [PATCH v2] arm: dts: Move am33xx and am43xx mmc nodes to sdhci-omap driver
From: Faiz Abbas @ 2020-05-19 8:22 UTC (permalink / raw)
To: Tony Lindgren, Keerthy
Cc: linux-kernel, devicetree, linux-omap, robh+dt, bcousson,
Tomi Valkeinen
In-Reply-To: <94025425-95e2-e53d-cfac-a1e73e6c011a@ti.com>
Tony,
On 15/05/20 3:04 pm, Faiz Abbas wrote:
> Hi Tony,
>
> On 13/05/20 9:53 pm, Tony Lindgren wrote:
>> * Faiz Abbas <faiz_abbas@ti.com> [200512 13:39]:
>>> Move mmc nodes to be compatible with the sdhci-omap driver. The following
>>> modifications are required for omap_hsmmc specific properties:
>>>
>>> ti,non-removable: convert to the generic mmc non-removable
>>> ti,needs-special-reset: co-opted into the sdhci-omap driver
>>> ti,dual-volt: removed. Legacy property not used in am335x or am43xx
>>> ti,needs-special-hs-handling: removed. Legacy property not used in am335x
>>> or am43xx
>>>
>>> Also since the sdhci-omap driver does not support runtime PM, explicitly
>>> disable the mmc3 instance in the dtsi.
>>>
>>> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
>>> ---
>>>
>>> v2: Rebased to latest mainline where all kernel dependancies have been merged.
>>>
>>> Suspend/Resume is now supported in the sdhci-omap driver.
>>
>> Great, thanks for updating it.
>>
>> Keerthy, care to test for am3 and am4?
>>
>
> Suspend/resume on am43xx-gpevm is broken right now in mainline and the regression looks
> like it is caused by the display subsystem. I have reported this to Tomi and
> its being investigated.
>
> Meanwhile I have tested this patch with display configs disabled and Keerthy's
> suspend/resume tests pass on both am3 and am4.
>
Can this patch be picked up? I would really like this to be merged by v5.8
Thanks,
Faiz
^ permalink raw reply
* [PATCH v3] arm64: dts: ti: k3-am654-main: Update otap-del-sel values
From: Faiz Abbas @ 2020-05-19 8:20 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel
Cc: robh+dt, t-kristo, faiz_abbas, nm
According to the latest AM65x Data Manual[1], a different output tap
delay value is optimum for a given speed mode. Update these values.
[1] http://www.ti.com/lit/gpn/am6526
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
---
v3: Updated values to the latest data manual revision
v2: Updated to the latest mainline kernel
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 11887c72f23a..056130a126f9 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -244,7 +244,17 @@
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
- ti,otap-del-sel = <0x2>;
+ ti,otap-del-sel-legacy = <0x0>;
+ ti,otap-del-sel-mmc-hs = <0x0>;
+ ti,otap-del-sel-sd-hs = <0x0>;
+ ti,otap-del-sel-sdr12 = <0x0>;
+ ti,otap-del-sel-sdr25 = <0x0>;
+ ti,otap-del-sel-sdr50 = <0x8>;
+ ti,otap-del-sel-sdr104 = <0x7>;
+ ti,otap-del-sel-ddr50 = <0x5>;
+ ti,otap-del-sel-ddr52 = <0x5>;
+ ti,otap-del-sel-hs200 = <0x5>;
+ ti,otap-del-sel-hs400 = <0x0>;
ti,trm-icp = <0x8>;
dma-coherent;
};
--
2.17.1
^ permalink raw reply related
* [PATCH] dt-bindings: gpio: Add renesas,em-gio bindings
From: Geert Uytterhoeven @ 2020-05-19 8:11 UTC (permalink / raw)
To: Linus Walleij, Bartosz Golaszewski, Rob Herring, Magnus Damm
Cc: devicetree, linux-gpio, linux-renesas-soc, Geert Uytterhoeven
Document Device Tree bindings for the Renesas EMMA Mobile General
Purpose I/O Interface.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
.../bindings/gpio/renesas,em-gio.yaml | 70 +++++++++++++++++++
1 file changed, 70 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/renesas,em-gio.yaml
diff --git a/Documentation/devicetree/bindings/gpio/renesas,em-gio.yaml b/Documentation/devicetree/bindings/gpio/renesas,em-gio.yaml
new file mode 100644
index 0000000000000000..8bdef812c87c3771
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/renesas,em-gio.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/renesas,em-gio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas EMMA Mobile General Purpose I/O Interface
+
+maintainers:
+ - Magnus Damm <magnus.damm@gmail.com>
+
+properties:
+ compatible:
+ const: renesas,em-gio
+
+ reg:
+ items:
+ - description: First set of contiguous registers
+ - description: Second set of contiguous registers
+
+ interrupts:
+ items:
+ - description: Interrupt for the first set of 16 GPIO ports
+ - description: Interrupt for the second set of 16 GPIO ports
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ ngpios:
+ minimum: 1
+ maximum: 32
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - gpio-controller
+ - '#gpio-cells'
+ - gpio-ranges
+ - ngpios
+ - interrupt-controller
+ - '#interrupt-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ gpio0: gpio@e0050000 {
+ compatible = "renesas,em-gio";
+ reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pfc 0 0 32>;
+ ngpios = <32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
--
2.17.1
^ permalink raw reply related
* [PATCH] dt-bindings: timer: Add renesas,em-sti bindings
From: Geert Uytterhoeven @ 2020-05-19 8:11 UTC (permalink / raw)
To: Daniel Lezcano, Thomas Gleixner, Rob Herring, Magnus Damm
Cc: devicetree, linux-renesas-soc, linux-kernel, Geert Uytterhoeven
Document Device Tree bindings for the Renesas EMMA Mobile System Timer.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
.../bindings/timer/renesas,em-sti.yaml | 46 +++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/renesas,em-sti.yaml
diff --git a/Documentation/devicetree/bindings/timer/renesas,em-sti.yaml b/Documentation/devicetree/bindings/timer/renesas,em-sti.yaml
new file mode 100644
index 0000000000000000..233d74d5402cf734
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/renesas,em-sti.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/renesas,em-sti.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas EMMA Mobile System Timer
+
+maintainers:
+ - Magnus Damm <magnus.damm@gmail.com>
+
+properties:
+ compatible:
+ const: renesas,em-sti
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: sclk
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ timer@e0180000 {
+ compatible = "renesas,em-sti";
+ reg = <0xe0180000 0x54>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sti_sclk>;
+ clock-names = "sclk";
+ };
--
2.17.1
^ permalink raw reply related
* Re: [PATCH v9 2/4] media: i2c: Add MAX9286 driver
From: Sakari Ailus @ 2020-05-19 8:10 UTC (permalink / raw)
To: Kieran Bingham
Cc: linux-renesas-soc, linux-media, devicetree, linux-kernel,
Mauro Carvalho Chehab, Kieran Bingham, Laurent Pinchart,
Jacopo Mondi, Niklas Söderlund, Hans Verkuil, Hyun Kwon,
Manivannan Sadhasivam, Rob Herring, Jacopo Mondi,
Laurent Pinchart, Niklas Söderlund
In-Reply-To: <930009cd-d887-752a-4f1f-567c795101ee@ideasonboard.com>
Hi Kieran,
On Mon, May 18, 2020 at 12:45:18PM +0100, Kieran Bingham wrote:
> Hi Sakari,
>
> There are only fairly minor comments here, fix ups will be included in a
> v10.
>
> Is there anything major blocking integration?
Not that I can see. But please see my comments below.
>
> Regards
>
> Kieran
>
>
>
> On 16/05/2020 22:51, Sakari Ailus wrote:
> > Hi Kieran,
> >
> > Thanks for the update.
> >
> > On Tue, May 12, 2020 at 04:51:03PM +0100, Kieran Bingham wrote:
> >
> > ...
> >
> >> +static int max9286_enum_mbus_code(struct v4l2_subdev *sd,
> >> + struct v4l2_subdev_pad_config *cfg,
> >> + struct v4l2_subdev_mbus_code_enum *code)
> >> +{
> >> + if (code->pad || code->index > 0)
> >> + return -EINVAL;
> >> +
> >> + code->code = MEDIA_BUS_FMT_UYVY8_2X8;
> >
> > Why UYVY8_2X8 and not UYVY8_1X16? In general, the single sample / pixel
> > variant of the format is generally used on the serial busses. This choice
> > was made when serial busses were introduced.
>
> Ok - I presume this doesn't really have much effect anyway, they just
> have to match for the transmitter/receiver?
In this case, yes. But it's harder to change later, so let's indeed do that
now.
>
> But it makes sense to me, so I'll update to the 1x16 variant.
...
>
> > And as you don't, you also won't know which frequencies are known to be
> > safe to use. That said, perhaps where this device is used having a random
> > frequency on that bus could not be an issue. Perhaps.
>
> Does this generate a range? or a list of static supported frequencies?
>
> We configure the pixel clock based upon the number of cameras connected,
> and their pixel rates etc ...
>
> Are you saying that the frequency of this clock should be validated to
> be a specific range? or are you talking about a different frequency?
It depends on the system. In general, only frequencies known to be safe
should be used. If this one has enough shielding to guarantee there won't
be problems in using a random frequency in the entire range, is there a
guarantee that will be the case for all systems with this chip?
--
Kind regards,
Sakari Ailus
^ permalink raw reply
* [PATCH] dt-bindings: serial: Add renesas,em-uart bindings
From: Geert Uytterhoeven @ 2020-05-19 8:09 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Magnus Damm
Cc: linux-serial, devicetree, linux-renesas-soc, Geert Uytterhoeven
Document Device Tree bindings for the Renesas EMMA Mobile UART
Interface.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
.../bindings/serial/renesas,em-uart.yaml | 49 +++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
diff --git a/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
new file mode 100644
index 0000000000000000..82aefdb0d45e5f1a
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/renesas,em-uart.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/serial/renesas,em-uart.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas EMMA Mobile UART Interface
+
+maintainers:
+ - Magnus Damm <magnus.damm@gmail.com>
+
+allOf:
+ - $ref: serial.yaml#
+
+properties:
+ compatible:
+ const: renesas,em-uart
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: sclk
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ uart0: serial@e1020000 {
+ compatible = "renesas,em-uart";
+ reg = <0xe1020000 0x38>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&usia_u0_sclk>;
+ clock-names = "sclk";
+ };
--
2.17.1
^ permalink raw reply related
* [PATCH] dt-bindings: memory-controllers: renesas,dbsc: Convert to json-schema
From: Geert Uytterhoeven @ 2020-05-19 8:08 UTC (permalink / raw)
To: Rob Herring; +Cc: devicetree, linux-renesas-soc, Geert Uytterhoeven
Convert the Renesas DDR Bus Controller Device Tree binding documentation
to json-schema.
Drop referrals to driver behavior.
Make power-domains required, as it is present for all current users.
Update the example to match reality.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
.../memory-controllers/renesas,dbsc.txt | 44 ---------------
.../memory-controllers/renesas,dbsc.yaml | 56 +++++++++++++++++++
2 files changed, 56 insertions(+), 44 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.txt
create mode 100644 Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml
diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.txt b/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.txt
deleted file mode 100644
index 9f78e6c82740cc89..0000000000000000
--- a/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.txt
+++ /dev/null
@@ -1,44 +0,0 @@
-DT bindings for Renesas R-Mobile and SH-Mobile memory controllers
-=================================================================
-
-Renesas R-Mobile and SH-Mobile SoCs contain one or more memory controllers.
-These memory controllers differ from one SoC variant to another, and are called
-by different names ("DDR Bus Controller (DBSC)", "DDR3 Bus State Controller
-(DBSC3)", "SDRAM Bus State Controller (SBSC)").
-
-Currently memory controller device nodes are used only to reference PM
-domains, and prevent these PM domains from being powered down, which would
-crash the system.
-
-As there exist no actual drivers for these controllers yet, these bindings
-should be considered EXPERIMENTAL for now.
-
-Required properties:
- - compatible: Must be one of the following SoC-specific values:
- - "renesas,dbsc-r8a73a4" (R-Mobile APE6)
- - "renesas,dbsc3-r8a7740" (R-Mobile A1)
- - "renesas,sbsc-sh73a0" (SH-Mobile AG5)
- - reg: Must contain the base address and length of the memory controller's
- registers.
-
-Optional properties:
- - interrupts: Must contain a list of interrupt specifiers for memory
- controller interrupts, if available.
- - interrupt-names: Must contain a list of interrupt names corresponding to
- the interrupts in the interrupts property, if available.
- Valid interrupt names are:
- - "sec" (secure interrupt)
- - "temp" (normal (temperature) interrupt)
- - power-domains: Must contain a reference to the PM domain that the memory
- controller belongs to, if available.
-
-Example:
-
- sbsc1: memory-controller@fe400000 {
- compatible = "renesas,sbsc-sh73a0";
- reg = <0xfe400000 0x400>;
- interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
- <0 36 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "sec", "temp";
- power-domains = <&pd_a4bc0>;
- };
diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml
new file mode 100644
index 0000000000000000..7056ccb7eb304cce
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/memory-controllers/renesas,dbsc.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Renesas DDR Bus Controllers
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description: |
+ Renesas SoCs contain one or more memory controllers. These memory
+ controllers differ from one SoC variant to another, and are called by
+ different names, e.g. "DDR Bus Controller (DBSC)", "DDR3 Bus State Controller
+ (DBSC3)", or "SDRAM Bus State Controller (SBSC)").
+
+properties:
+ compatible:
+ enum:
+ - renesas,dbsc-r8a73a4 # R-Mobile APE6
+ - renesas,dbsc3-r8a7740 # R-Mobile A1
+ - renesas,sbsc-sh73a0 # SH-Mobile AG5
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 2
+
+ interrupt-names:
+ items:
+ - const: sec # secure interrupt
+ - const: temp # normal (temperature) interrupt
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - power-domains
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ sbsc1: memory-controller@fe400000 {
+ compatible = "renesas,sbsc-sh73a0";
+ reg = <0xfe400000 0x400>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "sec", "temp";
+ power-domains = <&pd_a4bc0>;
+ };
--
2.17.1
^ permalink raw reply related
* [PATCH] dt-bindings: interrupt-controller: arm,gic: Document resets property
From: Geert Uytterhoeven @ 2020-05-19 8:05 UTC (permalink / raw)
To: Thomas Gleixner, Jason Cooper, Marc Zyngier, Rob Herring,
Andre Przywara
Cc: devicetree, linux-arm-kernel, linux-renesas-soc, linux-kernel,
Geert Uytterhoeven
A generic GIC block embedded in an SoC may be connected to an on-SoC
reset controller. Hence allow the DTS writer to describe this relation,
by documenting the optional presence of a "reset" property.
This gets rid of "make dtbs_check" warnings like:
arch/arm/boot/dts/r8a7791-porter.dt.yaml: interrupt-controller@f1001000: 'resets' does not match any of the regexes: '^v2m@[0-9a-f]+$', 'pinctrl-[0-9]+'
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
.../devicetree/bindings/interrupt-controller/arm,gic.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
index 9a47820ef34649dd..caefcc50bcf92c92 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml
@@ -125,6 +125,9 @@ properties:
power-domains:
maxItems: 1
+ resets:
+ maxItems: 1
+
required:
- compatible
- reg
--
2.17.1
^ permalink raw reply related
* [PATCH] ASoC: fsi: Add missing properties to DT bindings
From: Geert Uytterhoeven @ 2020-05-19 7:58 UTC (permalink / raw)
To: Kuninori Morimoto, Liam Girdwood, Mark Brown, Rob Herring
Cc: alsa-devel, devicetree, linux-renesas-soc, Geert Uytterhoeven
make dtbs_check:
arch/arm/boot/dts/r8a7740-armadillo800eva.dt.yaml: sound@fe1f0000: '#sound-dai-cells', 'clocks', 'power-domains' do not match any of the regexes: 'pinctrl-[0-9]+'
Fix this by documenting the missing properties.
Update the example to match reality.
While at it, improve the document title, and comment the various
compatible values with the corresponding SoC names.
Fixes: 7f464532b05dadc8 ("dt-bindings: Add missing 'additionalProperties: false'")
Fixes: 2f52475bac7e1572 ("ASoC: fsi: switch to yaml base Documentation")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
For a clean "make dtbs_check", this depends on "ARM: dts: sh73a0: Add
missing clocks to sound node"
(http://lore.kernel.org/r/20200519075525.24742-1-geert+renesas@glider.be).
---
.../bindings/sound/renesas,fsi.yaml | 29 +++++++++++++++----
1 file changed, 23 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml b/Documentation/devicetree/bindings/sound/renesas,fsi.yaml
index 91cf4176abd5f78f..8a4406be387a6b61 100644
--- a/Documentation/devicetree/bindings/sound/renesas,fsi.yaml
+++ b/Documentation/devicetree/bindings/sound/renesas,fsi.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/sound/renesas,fsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Renesas FSI Sound Driver Device Tree Bindings
+title: Renesas FIFO-buffered Serial Interface (FSI)
maintainers:
- Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
@@ -18,8 +18,8 @@ properties:
# for FSI2 SoC
- items:
- enum:
- - renesas,fsi2-sh73a0
- - renesas,fsi2-r8a7740
+ - renesas,fsi2-sh73a0 # SH-Mobile AG5
+ - renesas,fsi2-r8a7740 # R-Mobile A1
- enum:
- renesas,sh_fsi2
# for Generic
@@ -34,6 +34,15 @@ properties:
interrupts:
maxItems: 1
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ '#sound-dai-cells':
+ const: 1
+
fsia,spdif-connection:
$ref: /schemas/types.yaml#/definitions/flag
description: FSI is connected by S/PDIF
@@ -62,16 +71,24 @@ required:
- compatible
- reg
- interrupts
+ - clocks
+ - power-domains
+ - '#sound-dai-cells'
additionalProperties: false
examples:
- |
- sh_fsi2: sound@ec230000 {
+ #include <dt-bindings/clock/r8a7740-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ sh_fsi2: sound@fe1f0000 {
compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
- reg = <0xec230000 0x400>;
- interrupts = <0 146 0x4>;
+ reg = <0xfe1f0000 0x400>;
+ interrupts = <GIC_SPI 9 0x4>;
+ clocks = <&mstp3_clks R8A7740_CLK_FSI>;
+ power-domains = <&pd_a4mp>;
+ #sound-dai-cells = <1>;
fsia,spdif-connection;
fsia,stream-mode-support;
fsia,use-internal-clock;
--
2.17.1
^ permalink raw reply related
* [PATCH] ARM: dts: sh73a0: Add missing clocks to sound node
From: Geert Uytterhoeven @ 2020-05-19 7:55 UTC (permalink / raw)
To: Kuninori Morimoto, Magnus Damm
Cc: linux-renesas-soc, linux-arm-kernel, devicetree,
Geert Uytterhoeven
The device node for the FIFO-buffered Serial Interface sound node lacks
the "clocks" property, as the DTS file didn't describe any clocks yet at
its introduction.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
To be queued in renesas-fixes for v5.7 or v5.8, to avoid the
corresponding DT binding update introducing a regression.
arch/arm/boot/dts/sh73a0.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 6688f058087704d3..d7339e511288a4ec 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -601,6 +601,7 @@
compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
reg = <0xec230000 0x400>;
interrupts = <GIC_SPI 146 0x4>;
+ clocks = <&mstp3_clks SH73A0_CLK_FSI>;
power-domains = <&pd_a4mp>;
status = "disabled";
};
--
2.17.1
^ permalink raw reply related
* [PATCH v2 4/4] iio: imu: bmi160: added mount-matrix support
From: Jonathan Albrieux @ 2020-05-19 7:51 UTC (permalink / raw)
To: linux-kernel
Cc: Jonathan Albrieux,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Hartmut Knaack, Lars-Peter Clausen,
open list:IIO SUBSYSTEM AND DRIVERS, Peter Meerwald-Stadler,
Jonathan Cameron
In-Reply-To: <20200519075111.6356-1-jonathan.albrieux@gmail.com>
Add mount-matrix binding support. As chip could have different orientations
a mount matrix support is needed to correctly translate these differences
Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com>
---
drivers/iio/imu/bmi160/bmi160.h | 1 +
drivers/iio/imu/bmi160/bmi160_core.c | 20 ++++++++++++++++++++
2 files changed, 21 insertions(+)
diff --git a/drivers/iio/imu/bmi160/bmi160.h b/drivers/iio/imu/bmi160/bmi160.h
index 923c3b274fde..a82e040bd109 100644
--- a/drivers/iio/imu/bmi160/bmi160.h
+++ b/drivers/iio/imu/bmi160/bmi160.h
@@ -9,6 +9,7 @@ struct bmi160_data {
struct regmap *regmap;
struct iio_trigger *trig;
struct regulator_bulk_data supplies[2];
+ struct iio_mount_matrix orientation;
};
extern const struct regmap_config bmi160_regmap_config;
diff --git a/drivers/iio/imu/bmi160/bmi160_core.c b/drivers/iio/imu/bmi160/bmi160_core.c
index 9bbe0d8e6720..78c8ca962359 100644
--- a/drivers/iio/imu/bmi160/bmi160_core.c
+++ b/drivers/iio/imu/bmi160/bmi160_core.c
@@ -110,6 +110,7 @@
.storagebits = 16, \
.endianness = IIO_LE, \
}, \
+ .ext_info = bmi160_ext_info, \
}
/* scan indexes follow DATA register order */
@@ -265,6 +266,20 @@ static const struct bmi160_odr_item bmi160_odr_table[] = {
},
};
+static const struct iio_mount_matrix *
+bmi160_get_mount_matrix(const struct iio_dev *indio_dev,
+ const struct iio_chan_spec *chan)
+{
+ struct bmi160_data *data = iio_priv(indio_dev);
+
+ return &data->orientation;
+}
+
+static const struct iio_chan_spec_ext_info bmi160_ext_info[] = {
+ IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmi160_get_mount_matrix),
+ { }
+};
+
static const struct iio_chan_spec bmi160_channels[] = {
BMI160_CHANNEL(IIO_ACCEL, X, BMI160_SCAN_ACCEL_X),
BMI160_CHANNEL(IIO_ACCEL, Y, BMI160_SCAN_ACCEL_Y),
@@ -840,6 +855,11 @@ int bmi160_core_probe(struct device *dev, struct regmap *regmap,
return ret;
}
+ ret = iio_read_mount_matrix(dev, "mount-matrix",
+ &data->orientation);
+ if (ret)
+ return ret;
+
ret = bmi160_chip_init(data, use_spi);
if (ret)
return ret;
--
2.17.1
^ permalink raw reply related
* [PATCH v2 3/4] iio: imu: bmi160: added regulator support
From: Jonathan Albrieux @ 2020-05-19 7:50 UTC (permalink / raw)
To: linux-kernel
Cc: Jonathan Albrieux,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Hartmut Knaack, Lars-Peter Clausen,
open list:IIO SUBSYSTEM AND DRIVERS, Peter Meerwald-Stadler,
Jonathan Cameron
In-Reply-To: <20200519075111.6356-1-jonathan.albrieux@gmail.com>
v2: fixed missing description
Add vdd-supply and vddio-supply support. Without this support vdd and vddio
should be set to always-on in device tree
Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com>
---
drivers/iio/imu/bmi160/bmi160.h | 2 ++
drivers/iio/imu/bmi160/bmi160_core.c | 27 ++++++++++++++++++++++++++-
2 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/iio/imu/bmi160/bmi160.h b/drivers/iio/imu/bmi160/bmi160.h
index 621f5309d735..923c3b274fde 100644
--- a/drivers/iio/imu/bmi160/bmi160.h
+++ b/drivers/iio/imu/bmi160/bmi160.h
@@ -3,10 +3,12 @@
#define BMI160_H_
#include <linux/iio/iio.h>
+#include <linux/regulator/consumer.h>
struct bmi160_data {
struct regmap *regmap;
struct iio_trigger *trig;
+ struct regulator_bulk_data supplies[2];
};
extern const struct regmap_config bmi160_regmap_config;
diff --git a/drivers/iio/imu/bmi160/bmi160_core.c b/drivers/iio/imu/bmi160/bmi160_core.c
index 6af65d6f1d28..9bbe0d8e6720 100644
--- a/drivers/iio/imu/bmi160/bmi160_core.c
+++ b/drivers/iio/imu/bmi160/bmi160_core.c
@@ -15,6 +15,7 @@
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/of_irq.h>
+#include <linux/regulator/consumer.h>
#include <linux/iio/iio.h>
#include <linux/iio/triggered_buffer.h>
@@ -709,6 +710,12 @@ static int bmi160_chip_init(struct bmi160_data *data, bool use_spi)
unsigned int val;
struct device *dev = regmap_get_device(data->regmap);
+ ret = regulator_bulk_enable(ARRAY_SIZE(data->supplies), data->supplies);
+ if (ret) {
+ dev_err(dev, "Failed to enable regulators: %d\n", ret);
+ return ret;
+ }
+
ret = regmap_write(data->regmap, BMI160_REG_CMD, BMI160_CMD_SOFTRESET);
if (ret)
return ret;
@@ -793,9 +800,17 @@ int bmi160_probe_trigger(struct iio_dev *indio_dev, int irq, u32 irq_type)
static void bmi160_chip_uninit(void *data)
{
struct bmi160_data *bmi_data = data;
+ struct device *dev = regmap_get_device(bmi_data->regmap);
+ int ret;
bmi160_set_mode(bmi_data, BMI160_GYRO, false);
bmi160_set_mode(bmi_data, BMI160_ACCEL, false);
+
+ ret = regulator_bulk_disable(ARRAY_SIZE(bmi_data->supplies),
+ bmi_data->supplies);
+ if (ret) {
+ dev_err(dev, "Failed to disable regulators: %d\n", ret);
+ }
}
int bmi160_core_probe(struct device *dev, struct regmap *regmap,
@@ -815,6 +830,16 @@ int bmi160_core_probe(struct device *dev, struct regmap *regmap,
dev_set_drvdata(dev, indio_dev);
data->regmap = regmap;
+ data->supplies[0].supply = "vdd";
+ data->supplies[1].supply = "vddio";
+ ret = devm_regulator_bulk_get(dev,
+ ARRAY_SIZE(data->supplies),
+ data->supplies);
+ if (ret) {
+ dev_err(dev, "Failed to get regulators: %d\n", ret);
+ return ret;
+ }
+
ret = bmi160_chip_init(data, use_spi);
if (ret)
return ret;
@@ -853,6 +878,6 @@ int bmi160_core_probe(struct device *dev, struct regmap *regmap,
}
EXPORT_SYMBOL_GPL(bmi160_core_probe);
-MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com");
+MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
MODULE_DESCRIPTION("Bosch BMI160 driver");
MODULE_LICENSE("GPL v2");
--
2.17.1
^ permalink raw reply related
* [PATCH v2 2/4] dt-bindings: iio: imu: bmi160: add regulators and mount-matrix
From: Jonathan Albrieux @ 2020-05-19 7:50 UTC (permalink / raw)
To: linux-kernel
Cc: Jonathan Albrieux,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Hartmut Knaack, Lars-Peter Clausen,
open list:IIO SUBSYSTEM AND DRIVERS, Peter Meerwald-Stadler,
Jonathan Cameron, Rob Herring
In-Reply-To: <20200519075111.6356-1-jonathan.albrieux@gmail.com>
Add vdd-supply and vddio-supply support.
Add mount-matrix support.
Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com>
---
.../devicetree/bindings/iio/imu/bmi160.yaml | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/Documentation/devicetree/bindings/iio/imu/bmi160.yaml b/Documentation/devicetree/bindings/iio/imu/bmi160.yaml
index 6b464ce5ed0b..5b13af7a209f 100644
--- a/Documentation/devicetree/bindings/iio/imu/bmi160.yaml
+++ b/Documentation/devicetree/bindings/iio/imu/bmi160.yaml
@@ -46,6 +46,21 @@ properties:
set if the specified interrupt pin should be configured as
open drain. If not set, defaults to push-pull.
+ vdd-supply:
+ maxItems: 1
+ description: |
+ an optional regulator that needs to be on to provide VDD power to
+ the sensor.
+
+ vddio-supply:
+ maxItems: 1
+ description: |
+ an optional regulator that needs to be on to provide the VDD IO power to
+ the sensor.
+
+ mount-matrix:
+ description: an optional 3x3 mounting rotation matrix
+
required:
- compatible
- reg
@@ -61,9 +76,15 @@ examples:
bmi160@68 {
compatible = "bosch,bmi160";
reg = <0x68>;
+ vdd-supply = <&pm8916_l17>;
+ vddio-supply = <&pm8916_l6>;
interrupt-parent = <&gpio4>;
interrupts = <12 1>;
interrupt-names = "INT1";
+ mount-matrix = "0", "1", "0",
+ "-1", "0", "0",
+ "0", "0", "1";
+ };
};
- |
// Example for SPI
--
2.17.1
^ permalink raw reply related
* [PATCH v2 1/4] dt-bindings: iio: imu: bmi160: convert txt format to yaml
From: Jonathan Albrieux @ 2020-05-19 7:50 UTC (permalink / raw)
To: linux-kernel
Cc: Jonathan Albrieux,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Hartmut Knaack, Lars-Peter Clausen,
open list:IIO SUBSYSTEM AND DRIVERS, Peter Meerwald-Stadler,
Jonathan Cameron, Rob Herring
In-Reply-To: <20200519075111.6356-1-jonathan.albrieux@gmail.com>
Converts documentation from txt format to yaml
Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com>
---
.../devicetree/bindings/iio/imu/bmi160.txt | 37 --------
.../devicetree/bindings/iio/imu/bmi160.yaml | 84 +++++++++++++++++++
2 files changed, 84 insertions(+), 37 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/iio/imu/bmi160.txt
create mode 100644 Documentation/devicetree/bindings/iio/imu/bmi160.yaml
diff --git a/Documentation/devicetree/bindings/iio/imu/bmi160.txt b/Documentation/devicetree/bindings/iio/imu/bmi160.txt
deleted file mode 100644
index 900c169de00f..000000000000
--- a/Documentation/devicetree/bindings/iio/imu/bmi160.txt
+++ /dev/null
@@ -1,37 +0,0 @@
-Bosch BMI160 - Inertial Measurement Unit with Accelerometer, Gyroscope
-and externally connectable Magnetometer
-
-https://www.bosch-sensortec.com/bst/products/all_products/bmi160
-
-Required properties:
- - compatible : should be "bosch,bmi160"
- - reg : the I2C address or SPI chip select number of the sensor
- - spi-max-frequency : set maximum clock frequency (only for SPI)
-
-Optional properties:
- - interrupts : interrupt mapping for IRQ
- - interrupt-names : set to "INT1" if INT1 pin should be used as interrupt
- input, set to "INT2" if INT2 pin should be used instead
- - drive-open-drain : set if the specified interrupt pin should be configured as
- open drain. If not set, defaults to push-pull.
-
-Examples:
-
-bmi160@68 {
- compatible = "bosch,bmi160";
- reg = <0x68>;
-
- interrupt-parent = <&gpio4>;
- interrupts = <12 IRQ_TYPE_EDGE_RISING>;
- interrupt-names = "INT1";
-};
-
-bmi160@0 {
- compatible = "bosch,bmi160";
- reg = <0>;
- spi-max-frequency = <10000000>;
-
- interrupt-parent = <&gpio2>;
- interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "INT2";
-};
diff --git a/Documentation/devicetree/bindings/iio/imu/bmi160.yaml b/Documentation/devicetree/bindings/iio/imu/bmi160.yaml
new file mode 100644
index 000000000000..6b464ce5ed0b
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/imu/bmi160.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/imu/bmi160.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Bosch BMI160
+
+maintainers:
+ - can't find a mantainer, author is Daniel Baluta <daniel.baluta@intel.com>
+
+description: |
+ Inertial Measurement Unit with Accelerometer, Gyroscope and externally
+ connectable Magnetometer
+ https://www.bosch-sensortec.com/bst/products/all_products/bmi160
+
+properties:
+ compatible:
+ const: bosch,bmi160
+
+ reg:
+ maxItems: 1
+ description: the I2C address or SPI chip select number of the sensor
+
+ spi-max-frequency:
+ maxItems: 1
+ description: set maximum clock frequency (required only for SPI)
+
+ interrupts:
+ maxItems: 1
+ description: interrupt mapping for IRQ
+
+ interrupt-names:
+ minItems: 1
+ maxItems: 1
+ items:
+ enum:
+ - INT1
+ - INT2
+ description: |
+ set to "INT1" if INT1 pin should be used as interrupt input, set
+ to "INT2" if INT2 pin should be used instead
+
+ drive-open-drain:
+ description: |
+ set if the specified interrupt pin should be configured as
+ open drain. If not set, defaults to push-pull.
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ // Example for I2C
+ i2c@78b7000 {
+ reg = <0x78b6000 0x600>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bmi160@68 {
+ compatible = "bosch,bmi160";
+ reg = <0x68>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <12 1>;
+ interrupt-names = "INT1";
+ };
+ - |
+ // Example for SPI
+ spi@78b7000 {
+ reg = <0x78b7000 0x600>,
+ <0x7884000 0x23000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bmi160@0 {
+ compatible = "bosch,bmi160";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <12 1>;
+ interrupt-names = "INT2";
+ };
+ };
--
2.17.1
^ permalink raw reply related
* [PATCH v2 0/4] iio: imu: bmi160: added regulator and mount-matrix support
From: Jonathan Albrieux @ 2020-05-19 7:50 UTC (permalink / raw)
To: linux-kernel
Cc: Jonathan Albrieux,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Hartmut Knaack, Lars-Peter Clausen,
open list:IIO SUBSYSTEM AND DRIVERS, Peter Meerwald-Stadler
v2: fixed missing description for iio: imu: bmi160: added regulator
support
Convert txt format documentation to yaml.
Add documentation about vdd-supply, vddio-supply and mount-matrix.
Add vdd-supply and vddio-supply support. Without this support, vdd and
vddio should be set to always-on in device tree.
Add mount-matrix binding support. As chip could have different
orientations a mount matrix support is needed to correctly translate
these differences
Jonathan Albrieux (4):
dt-bindings: iio: imu: bmi160: convert txt format to yaml
dt-bindings: iio: imu: bmi160: add regulators and mount-matrix
iio: imu: bmi160: added regulator support
iio: imu: bmi160: added mount-matrix support
.../devicetree/bindings/iio/imu/bmi160.txt | 37 ------
.../devicetree/bindings/iio/imu/bmi160.yaml | 105 ++++++++++++++++++
drivers/iio/imu/bmi160/bmi160.h | 3 +
drivers/iio/imu/bmi160/bmi160_core.c | 47 +++++++-
4 files changed, 154 insertions(+), 38 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/iio/imu/bmi160.txt
create mode 100644 Documentation/devicetree/bindings/iio/imu/bmi160.yaml
--
2.17.1
^ permalink raw reply
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