* Re: [PATCH v1 2/2] mfd: Introduce QTI I2C PMIC controller
From: Guru Das Srinagesh @ 2020-05-19 18:57 UTC (permalink / raw)
To: Lee Jones
Cc: devicetree, linux-arm-msm, Rob Herring, Subbaraman Narayanamurthy,
David Collins, linux-kernel
In-Reply-To: <20200515104520.GK271301@dell>
On Fri, May 15, 2020 at 11:45:20AM +0100, Lee Jones wrote:
> On Thu, 30 Apr 2020, Guru Das Srinagesh wrote:
>
> > On Wed, Apr 29, 2020 at 08:50:10AM +0100, Lee Jones wrote:
> > > On Tue, 28 Apr 2020, Guru Das Srinagesh wrote:
> > >
> > > > The Qualcomm Technologies, Inc. I2C PMIC Controller is used by
> > > > multi-function PMIC devices which communicate over the I2C bus. The
> > > > controller enumerates all child nodes as platform devices, and
> > > > instantiates a regmap interface for them to communicate over the I2C
> > > > bus.
> > > >
> > > > The controller also controls interrupts for all of the children platform
> > > > devices. The controller handles the summary interrupt by deciphering
> > > > which peripheral triggered the interrupt, and which of the peripheral
> > > > interrupts were triggered. Finally, it calls the interrupt handlers for
> > > > each of the virtual interrupts that were registered.
> > > >
> > > > Nicholas Troast is the original author of this driver.
> > > >
> > > > Signed-off-by: Guru Das Srinagesh <gurus@codeaurora.org>
> > > > ---
> > > > drivers/mfd/Kconfig | 11 +
> > > > drivers/mfd/Makefile | 1 +
> > > > drivers/mfd/qcom-i2c-pmic.c | 737 ++++++++++++++++++++++++++++++++++++++++++++
> > >
> > > The vast majority of this driver deals with IRQ handling. Why can't
> > > this be split out into its own IRQ Chip driver and moved to
> > > drivers/irqchip?
> >
> > There appear to be quite a few in-tree MFD drivers that register IRQ
> > controllers, like this driver does:
> >
> > $ grep --exclude-dir=.git -rnE "irq_domain_(add|create).+\(" drivers/mfd | wc -l
> > 23
> >
> > As a further example, drivers/mfd/stpmic1.c closely resembles this
> > driver in that it uses both devm_regmap_add_irq_chip() as well as
> > devm_of_platform_populate().
> >
> > As such, it seems like this driver is in line with some of the
> > architectural choices that have been accepted in already-merged drivers.
> > Could you please elaborate on your concerns?
>
> It is true that *basic* IRQ domain support has been added to these
> drivers in the past. However, IMHO the support added to this driver
> goes beyond those realms such that it would justify a driver of its
> own.
I am exploring an option to see if the regmap-irq APIs may be used in
this driver, similar to stpmic1.c. Just to let you know, it might be a
few days before I am able to post my next patchset as I'll have to make
the necessary changes and test them out first.
Thank you.
Guru Das.
^ permalink raw reply
* Re: [PATCH v4 1/2] dt-bindings: soc: ti: add binding for k3 platforms chipid module
From: Rob Herring @ 2020-05-19 18:54 UTC (permalink / raw)
To: Grygorii Strashko
Cc: Santosh Shilimkar, Nishanth Menon, Dave Gerlach, linux-arm-kernel,
Sekhar Nori, Arnd Bergmann, linux-kernel, devicetree, Rob Herring,
Lokesh Vutla, Tero Kristo
In-Reply-To: <20200512123449.16517-2-grygorii.strashko@ti.com>
On Tue, 12 May 2020 15:34:48 +0300, Grygorii Strashko wrote:
> Add DT binding for Texas Instruments K3 Multicore SoC platforms chipid
> module which is represented by CTRLMMR_xxx_JTAGID register and contains
> information about SoC id and revision.
>
> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
> Reviewed-by: Tero Kristo <t-kristo@ti.com>
> ---
> .../bindings/soc/ti/k3-socinfo.yaml | 40 +++++++++++++++++++
> 1 file changed, 40 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soc/ti/k3-socinfo.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v10] arm64: dts: qcom: sc7180: Add WCN3990 WLAN module device node
From: Rakesh Pillai @ 2020-05-19 18:53 UTC (permalink / raw)
To: devicetree; +Cc: linux-arm-kernel, linux-kernel, linux-arm-msm, Rakesh Pillai
Add device node for the ath10k SNOC platform driver probe
and add resources required for WCN3990 on sc7180 soc.
Signed-off-by: Rakesh Pillai <pillair@codeaurora.org>
---
Changes from v9:
- Place the wlan_fw_mem under reserved-memory node
---
arch/arm64/boot/dts/qcom/sc7180-idp.dts | 7 +++++++
arch/arm64/boot/dts/qcom/sc7180.dtsi | 27 +++++++++++++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
index 4e9149d..38b102e 100644
--- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
+++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
@@ -389,6 +389,13 @@
};
};
+&wifi {
+ status = "okay";
+ wifi-firmware {
+ iommus = <&apps_smmu 0xc2 0x1>;
+ };
+};
+
/* PINCTRL - additions to nodes defined in sc7180.dtsi */
&qspi_clk {
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index f1280e0..19bd7d0 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -106,6 +106,11 @@
no-map;
};
+ wlan_fw_mem: memory@94100000 {
+ reg = <0 0x94100000 0 0x200000>;
+ no-map;
+ };
+
rmtfs_mem: memory@84400000 {
compatible = "qcom,rmtfs-mem";
reg = <0x0 0x84400000 0x0 0x200000>;
@@ -944,6 +949,28 @@
};
};
+ wifi: wifi@18800000 {
+ compatible = "qcom,wcn3990-wifi";
+ reg = <0 0x18800000 0 0x800000>;
+ reg-names = "membase";
+ iommus = <&apps_smmu 0xc0 0x1>;
+ interrupts =
+ <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
+ <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
+ <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
+ <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
+ <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
+ <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
+ <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
+ <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
+ <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
+ memory-region = <&wlan_fw_mem>;
+ status = "disabled";
+ };
+
config_noc: interconnect@1500000 {
compatible = "qcom,sc7180-config-noc";
reg = <0 0x01500000 0 0x28000>;
--
2.7.4
^ permalink raw reply related
* Re: [PATCH] dt-bindings: eeprom: at24: Fix list of page sizes for writing
From: Rob Herring @ 2020-05-19 18:52 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rob Herring, linux-i2c, Bartosz Golaszewski, devicetree
In-Reply-To: <20200512122450.20205-1-geert+renesas@glider.be>
On Tue, 12 May 2020 14:24:47 +0200, Geert Uytterhoeven wrote:
> "258" is an odd power-of-two ;-)
> Obviously this is a typo, and the intended value is "256".
>
> Fixes: 7f3bf4203774013b ("dt-bindings: at24: convert the binding document to yaml")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> Documentation/devicetree/bindings/eeprom/at24.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH V1 RESEND 1/3] perf/imx_ddr: Add system PMU identifier for userspace
From: Rob Herring @ 2020-05-19 18:51 UTC (permalink / raw)
To: Joakim Zhang
Cc: john.garry, will, mark.rutland, shawnguo, linux-imx,
linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20200512073115.14177-2-qiangqing.zhang@nxp.com>
On Tue, May 12, 2020 at 03:31:13PM +0800, Joakim Zhang wrote:
> The DDR Perf for i.MX8 is a system PMU whose axi id would different from
> SoC to SoC. Need expose system PMU identifier for userspace which refer
> to /sys/bus/event_source/devices/<PMU DEVICE>/identifier.
Why not just expose the AXI ID if that's what's different?
>
> Reviewed-by: John Garry <john.garry@huawei.com>
> Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
> ---
> drivers/perf/fsl_imx8_ddr_perf.c | 45 +++++++++++++++++++++++++++++---
> 1 file changed, 42 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/perf/fsl_imx8_ddr_perf.c b/drivers/perf/fsl_imx8_ddr_perf.c
> index 95dca2cb5265..88addbffbbd0 100644
> --- a/drivers/perf/fsl_imx8_ddr_perf.c
> +++ b/drivers/perf/fsl_imx8_ddr_perf.c
> @@ -50,21 +50,38 @@ static DEFINE_IDA(ddr_ida);
>
> struct fsl_ddr_devtype_data {
> unsigned int quirks; /* quirks needed for different DDR Perf core */
> + const char *identifier; /* system PMU identifier for userspace */
> };
>
> -static const struct fsl_ddr_devtype_data imx8_devtype_data;
> +static const struct fsl_ddr_devtype_data imx8_devtype_data = {
> + .identifier = "i.MX8",
> +};
> +
> +static const struct fsl_ddr_devtype_data imx8mq_devtype_data = {
> + .quirks = DDR_CAP_AXI_ID_FILTER,
> + .identifier = "i.MX8MQ",
> +};
> +
> +static const struct fsl_ddr_devtype_data imx8mm_devtype_data = {
> + .quirks = DDR_CAP_AXI_ID_FILTER,
> + .identifier = "i.MX8MM",
> +};
>
> -static const struct fsl_ddr_devtype_data imx8m_devtype_data = {
> +static const struct fsl_ddr_devtype_data imx8mn_devtype_data = {
> .quirks = DDR_CAP_AXI_ID_FILTER,
> + .identifier = "i.MX8MN",
> };
>
> static const struct fsl_ddr_devtype_data imx8mp_devtype_data = {
> .quirks = DDR_CAP_AXI_ID_FILTER_ENHANCED,
> + .identifier = "i.MX8MP",
> };
>
> static const struct of_device_id imx_ddr_pmu_dt_ids[] = {
> { .compatible = "fsl,imx8-ddr-pmu", .data = &imx8_devtype_data},
> - { .compatible = "fsl,imx8m-ddr-pmu", .data = &imx8m_devtype_data},
You need to keep the old one for compatibility.
> + { .compatible = "fsl,imx8mq-ddr-pmu", .data = &imx8mq_devtype_data},
> + { .compatible = "fsl,imx8mm-ddr-pmu", .data = &imx8mm_devtype_data},
> + { .compatible = "fsl,imx8mn-ddr-pmu", .data = &imx8mn_devtype_data},
> { .compatible = "fsl,imx8mp-ddr-pmu", .data = &imx8mp_devtype_data},
> { /* sentinel */ }
> };
> @@ -84,6 +101,27 @@ struct ddr_pmu {
> int id;
> };
>
> +static ssize_t ddr_perf_identifier_show(struct device *dev,
> + struct device_attribute *attr,
> + char *page)
> +{
> + struct ddr_pmu *pmu = dev_get_drvdata(dev);
> +
> + return sprintf(page, "%s\n", pmu->devtype_data->identifier);
Why do we need yet another way to identify the SoC from userspace?
> +}
> +
> +static struct device_attribute ddr_perf_identifier_attr =
> + __ATTR(identifier, 0444, ddr_perf_identifier_show, NULL);
sysfs attributes are supposed to be documented.
> +
> +static struct attribute *ddr_perf_identifier_attrs[] = {
> + &ddr_perf_identifier_attr.attr,
> + NULL,
> +};
> +
> +static struct attribute_group ddr_perf_identifier_attr_group = {
> + .attrs = ddr_perf_identifier_attrs,
> +};
> +
> enum ddr_perf_filter_capabilities {
> PERF_CAP_AXI_ID_FILTER = 0,
> PERF_CAP_AXI_ID_FILTER_ENHANCED,
> @@ -237,6 +275,7 @@ static const struct attribute_group *attr_groups[] = {
> &ddr_perf_format_attr_group,
> &ddr_perf_cpumask_attr_group,
> &ddr_perf_filter_cap_attr_group,
> + &ddr_perf_identifier_attr_group,
> NULL,
> };
>
> --
> 2.17.1
>
^ permalink raw reply
* RE: [PATCH v9] arm64: dts: qcom: sc7180: Add WCN3990 WLAN module device node
From: pillair @ 2020-05-19 18:50 UTC (permalink / raw)
To: 'Evan Green'
Cc: 'open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS',
'linux-arm Mailing List', 'LKML',
'linux-arm-msm'
In-Reply-To: <CAE=gft577zxP5F6OdFXt6taLuLyye+tdRqZa63mPSRtPXO3Lcw@mail.gmail.com>
Hi Evan,
> -----Original Message-----
> From: Evan Green <evgreen@chromium.org>
> Sent: Tuesday, May 19, 2020 10:58 PM
> To: Rakesh Pillai <pillair@codeaurora.org>
> Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> <devicetree@vger.kernel.org>; linux-arm Mailing List <linux-arm-
> kernel@lists.infradead.org>; LKML <linux-kernel@vger.kernel.org>; linux-
> arm-msm <linux-arm-msm@vger.kernel.org>
> Subject: Re: [PATCH v9] arm64: dts: qcom: sc7180: Add WCN3990 WLAN
> module device node
>
> On Sun, May 17, 2020 at 3:47 AM Rakesh Pillai <pillair@codeaurora.org>
> wrote:
> >
> > Add device node for the ath10k SNOC platform driver probe
> > and add resources required for WCN3990 on sc7180 soc.
> >
> > Signed-off-by: Rakesh Pillai <pillair@codeaurora.org>
> > ---
> > Changes from v8:
> > - Removed the qcom,msa-fixed-perm
> > ---
> > arch/arm64/boot/dts/qcom/sc7180-idp.dts | 7 +++++++
> > arch/arm64/boot/dts/qcom/sc7180.dtsi | 27
> +++++++++++++++++++++++++++
> > 2 files changed, 34 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> > index 4e9149d..38b102e 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> > +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> > @@ -389,6 +389,13 @@
> > };
> > };
> >
> > +&wifi {
> > + status = "okay";
> > + wifi-firmware {
> > + iommus = <&apps_smmu 0xc2 0x1>;
> > + };
> > +};
> > +
> > /* PINCTRL - additions to nodes defined in sc7180.dtsi */
> >
> > &qspi_clk {
> > diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> > index f1280e0..dd4e095 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> > @@ -63,6 +63,11 @@
> > clock-frequency = <32764>;
> > #clock-cells = <0>;
> > };
> > +
> > + wlan_fw_mem: memory@94100000 {
> > + reg = <0 0x94100000 0 0x200000>;
> > + no-map;
> > + };
>
> This node is not in the right place. Up through v8, this lived inside
> reserved-memory. Here it seems to apply into the clocks {} node, which
> is not the right spot.
Thanks for spotting this. This was a rebase problem.
I will post the next patchset by fixing this.
>
>
> > };
> >
> > reserved_memory: reserved-memory {
> > @@ -944,6 +949,28 @@
> > };
> > };
> >
> > + wifi: wifi@18800000 {
> > + compatible = "qcom,wcn3990-wifi";
> > + reg = <0 0x18800000 0 0x800000>;
> > + reg-names = "membase";
> > + iommus = <&apps_smmu 0xc0 0x1>;
> > + interrupts =
> > + <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
> > + <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
> > + <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
> > + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
> > + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
> > + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
> > + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
> > + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
> > + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
> > + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
> > + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
> > + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
> > + memory-region = <&wlan_fw_mem>;
>
> Should any of the *-supply regulators be specified? Or are they all
> board specific? Or just not needed? The example has these:
> vdd-0.8-cx-mx-supply = <&pm8998_l5>;
> vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
> vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
> vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
These votes are optional and were required for older targets.
We do not need these proxy votes in host now.
>
>
>
> > + status = "disabled";
> > + };
> > +
> > config_noc: interconnect@1500000 {
> > compatible = "qcom,sc7180-config-noc";
> > reg = <0 0x01500000 0 0x28000>;
> > --
> > 2.7.4
^ permalink raw reply
* Re: [PATCH net-next 2/4] net: phy: dp83869: Set opmode from straps
From: Jakub Kicinski @ 2020-05-19 18:48 UTC (permalink / raw)
To: Dan Murphy
Cc: Andrew Lunn, f.fainelli, hkallweit1, davem, netdev, linux-kernel,
devicetree
In-Reply-To: <c45bae32-d26f-cbe5-626b-2afae4a557b3@ti.com>
On Tue, 19 May 2020 13:41:40 -0500 Dan Murphy wrote:
> > Is this now a standard GCC warning? Or have you turned on extra
> > checking?
> I still was not able to reproduce this warning with gcc-9.2. I would
> like to know the same
W=1 + gcc-10 here, also curious to know which one of the two makes
the difference :)
^ permalink raw reply
* Re: [PATCH V1 RESEND 2/3] bindings/perf/imx-ddr: update compatible string
From: Rob Herring @ 2020-05-19 18:47 UTC (permalink / raw)
To: Joakim Zhang
Cc: john.garry, will, mark.rutland, shawnguo, linux-imx,
linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <20200512073115.14177-3-qiangqing.zhang@nxp.com>
On Tue, May 12, 2020 at 03:31:14PM +0800, Joakim Zhang wrote:
> Update compatible string according to driver change.`
Why?
You are breaking compatibility.
>
> Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com>
> ---
> Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt
> index 7822a806ea0a..b27a1d4fec78 100644
> --- a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt
> +++ b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt
> @@ -4,7 +4,9 @@ Required properties:
>
> - compatible: should be one of:
> "fsl,imx8-ddr-pmu"
> - "fsl,imx8m-ddr-pmu"
> + "fsl,imx8mq-ddr-pmu"
> + "fsl,imx8mm-ddr-pmu"
> + "fsl,imx8mn-ddr-pmu"
> "fsl,imx8mp-ddr-pmu"
>
> - reg: physical address and size
> --
> 2.17.1
>
^ permalink raw reply
* Re: [PATCH v1] dt-bindings: spi: Add schema for Cadence QSPI Controller driver
From: Rob Herring @ 2020-05-19 18:44 UTC (permalink / raw)
To: Ramuthevar,Vadivel MuruganX
Cc: devicetree, linux-kernel, linux-mtd, linux-spi, vigneshr, broonie,
cheol.yong.kim, qi-ming.wu
In-Reply-To: <20200512004919.40685-1-vadivel.muruganx.ramuthevar@linux.intel.com>
On Tue, May 12, 2020 at 08:49:19AM +0800, Ramuthevar,Vadivel MuruganX wrote:
> From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
>
> Add dt-bindings documentation for Cadence-QSPI controller to support
> spi based flash memories.
>
> Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
> ---
> .../devicetree/bindings/mtd/cadence-quadspi.txt | 67 -----------
> .../devicetree/bindings/spi/cdns,qspi-nor.yaml | 127 +++++++++++++++++++++
> 2 files changed, 127 insertions(+), 67 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> create mode 100644 Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
>
> diff --git a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt b/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> deleted file mode 100644
> index 945be7d5b236..000000000000
> --- a/Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
> +++ /dev/null
> @@ -1,67 +0,0 @@
> -* Cadence Quad SPI controller
> -
> -Required properties:
> -- compatible : should be one of the following:
> - Generic default - "cdns,qspi-nor".
> - For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
> - For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
> -- reg : Contains two entries, each of which is a tuple consisting of a
> - physical address and length. The first entry is the address and
> - length of the controller register set. The second entry is the
> - address and length of the QSPI Controller data area.
> -- interrupts : Unit interrupt specifier for the controller interrupt.
> -- clocks : phandle to the Quad SPI clock.
> -- cdns,fifo-depth : Size of the data FIFO in words.
> -- cdns,fifo-width : Bus width of the data FIFO in bytes.
> -- cdns,trigger-address : 32-bit indirect AHB trigger address.
> -
> -Optional properties:
> -- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
> -- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
> - the read data rather than the QSPI clock. Make sure that QSPI return
> - clock is populated on the board before using this property.
> -
> -Optional subnodes:
> -Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
> -custom properties:
> -- cdns,read-delay : Delay for read capture logic, in clock cycles
> -- cdns,tshsl-ns : Delay in nanoseconds for the length that the master
> - mode chip select outputs are de-asserted between
> - transactions.
> -- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being
> - de-activated and the activation of another.
> -- cdns,tchsh-ns : Delay in nanoseconds between last bit of current
> - transaction and deasserting the device chip select
> - (qspi_n_ss_out).
> -- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low
> - and first bit transfer.
> -- resets : Must contain an entry for each entry in reset-names.
> - See ../reset/reset.txt for details.
> -- reset-names : Must include either "qspi" and/or "qspi-ocp".
> -
> -Example:
> -
> - qspi: spi@ff705000 {
> - compatible = "cdns,qspi-nor";
> - #address-cells = <1>;
> - #size-cells = <0>;
> - reg = <0xff705000 0x1000>,
> - <0xffa00000 0x1000>;
> - interrupts = <0 151 4>;
> - clocks = <&qspi_clk>;
> - cdns,is-decoded-cs;
> - cdns,fifo-depth = <128>;
> - cdns,fifo-width = <4>;
> - cdns,trigger-address = <0x00000000>;
> - resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
> - reset-names = "qspi", "qspi-ocp";
> -
> - flash0: n25q00@0 {
> - ...
> - cdns,read-delay = <4>;
> - cdns,tshsl-ns = <50>;
> - cdns,tsd2d-ns = <50>;
> - cdns,tchsh-ns = <4>;
> - cdns,tslch-ns = <4>;
> - };
> - };
> diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
> new file mode 100644
> index 000000000000..28112b38e6a9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
> @@ -0,0 +1,127 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Cadence QSPI Flash Controller support
> +
> +maintainers:
> + - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
> +
> +allOf:
> + - $ref: "spi-controller.yaml#"
> +
> +description: |
> + Binding Documentation for Cadence QSPI controller,This controller is
> + present in the Intel LGM, Altera SoCFPGA and TI SoCs and this driver
> + has been tested On Intel's LGM SoC.
> +
> +properties:
> + compatible:
> + enum:
> + - cdns,qspi-nor
> + - ti,k2g-qspi
> + - ti,am654-ospi
> + - intel,lgm-qspi
> +
> + reg:
> + maxItems: 2
Need to define what each entry is.
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + cdns,fifo-depth:
> + description:
> + Depth of hardware FIFOs.
...FIFO in words.
> + allOf:
> + - $ref: "/schemas/types.yaml#/definitions/uint32"
> + - enum: [ 128, 256 ]
> + - default: 128
> +
> + cdns,fifo-width:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + 4 byte bus width of the data FIFO in bytes.
Constraints? Perhaps:
multipleOf: 4
if an enum doesn't work here.
> +
> + cdns,trigger-address:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + 32-bit indirect AHB trigger address.
> +
> + cdns,rclk-en:
> + type: boolean
> + description: |
> + Flag to indicate that QSPI return clock is used to latch the read data
> + rather than the QSPI clock. Make sure that QSPI return clock is populated
> + on the board before using this property.
> +
> +# subnode's properties
> +patternProperties:
> + "^.*@[0-9a-fa-f]+$":
'a-f' is twice. What's the max number of chip selects? If less than 10,
then '@[0-9]$' is enough. '^.*' can be dropped too.
> + type: object
> + description:
> + flash device uses the subnodes below defined properties.
> +
> + cdns,read-delay:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Delay for read capture logic, in clock cycles.
> +
> + cdns,tshsl-ns:
> + description: |
> + Delay in nanoseconds for the length that the master mode chip select
> + outputs are de-asserted between transactions.
> +
> + cdns,tsd2d-ns:
> + description: |
> + Delay in nanoseconds between one chip select being de-activated
> + and the activation of another.
> +
> + cdns,tchsh-ns:
> + description: |
> + Delay in nanoseconds between last bit of current transaction and
> + deasserting the device chip select (qspi_n_ss_out).
> +
> + cdns,tslch-ns:
> + description: |
> + Delay in nanoseconds between setting qspi_n_ss_out low and
> + first bit transfer.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - cdns,fifo-depth
> + - cdns,fifo-width
> + - cdns,trigger-address
> +
> +examples:
> + - |
> + spi@ff705000 {
> + compatible = "cdns,qspi-nor";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0xff705000 0x1000>,
> + <0xffa00000 0x1000>;
Seems kind of small for a data area if this is like most SPI flash
controllers.
> + interrupts = <0 151 4>;
> + clocks = <&qspi_clk>;
> + cdns,fifo-depth = <128>;
> + cdns,fifo-width = <4>;
> + cdns,trigger-address = <0x00000000>;
> +
> + flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0x0>;
> + cdns,read-delay = <4>;
> + cdns,tshsl-ns = <50>;
> + cdns,tsd2d-ns = <50>;
> + cdns,tchsh-ns = <4>;
> + cdns,tslch-ns = <4>;
> + };
> + };
> +
> --
> 2.11.0
>
^ permalink raw reply
* Re: [PATCH net-next 2/4] net: phy: dp83869: Set opmode from straps
From: Dan Murphy @ 2020-05-19 18:41 UTC (permalink / raw)
To: Andrew Lunn, Jakub Kicinski
Cc: f.fainelli, hkallweit1, davem, netdev, linux-kernel, devicetree
In-Reply-To: <20200519182916.GM624248@lunn.ch>
Andrew
On 5/19/20 1:29 PM, Andrew Lunn wrote:
> On Tue, May 19, 2020 at 09:58:18AM -0700, Jakub Kicinski wrote:
>> On Tue, 19 May 2020 09:18:11 -0500 Dan Murphy wrote:
>>> If the op-mode for the device is not set in the device tree then set
>>> the strapped op-mode and store it for later configuration.
>>>
>>> Signed-off-by: Dan Murphy <dmurphy@ti.com>
>> ../drivers/net/phy/dp83869.c: In function0 dp83869_set_strapped_mode:
>> ../drivers/net/phy/dp83869.c:171:10: warning: comparison is always false due to limited range of data type [-Wtype-limits]
>> 171 | if (val < 0)
>> | ^
> Hi Jakub
>
> This happens a lot with PHY drivers. The register being read is a u16,
> so that is what people use.
Yes this is what happened but phy_read_mmd returns an int so the
declaration of val should be an int.
I will update that in v2
> Is this now a standard GCC warning? Or have you turned on extra
> checking?
I still was not able to reproduce this warning with gcc-9.2. I would
like to know the same
Dan
^ permalink raw reply
* Re: [PATCH 10/11] dt-bindings: sound: Add Marvell MMP SSPA binding
From: Rob Herring @ 2020-05-19 18:37 UTC (permalink / raw)
To: Lubomir Rintel
Cc: Liam Girdwood, Mark Brown, devicetree, Michael Turquette,
Rob Herring, linux-media, linux-clk, linux-kernel, Stephen Boyd
In-Reply-To: <20200511210134.1224532-11-lkundrak@v3.sk>
On Mon, 11 May 2020 23:01:33 +0200, Lubomir Rintel wrote:
> Add binding documentation for the audio serial port interface (I2S) on
> Marvell MMP SoCs.
>
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
> ---
> .../bindings/sound/marvell,mmp-sspa.yaml | 122 ++++++++++++++++++
> 1 file changed, 122 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/sound/marvell,mmp-sspa.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 07/10] dt-bindings: reset: s700: Add binding constants for mmc
From: Rob Herring @ 2020-05-19 18:33 UTC (permalink / raw)
To: Amit Singh Tomar
Cc: andre.przywara, afaerber, manivannan.sadhasivam,
cristian.ciocaltea, linux-kernel, linux-arm-kernel, linux-actions,
devicetree
In-Reply-To: <1589912368-480-8-git-send-email-amittomer25@gmail.com>
On Tue, May 19, 2020 at 11:49:25PM +0530, Amit Singh Tomar wrote:
> This commit adds device tree binding reset constants for mmc controller
> present on Actions S700 Soc.
>
> Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
> ---
> Changes since v1:
> * No change.
> Changes since RFC:
> * added Rob's acked-by tag
And dropped??
> ---
> include/dt-bindings/reset/actions,s700-reset.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/include/dt-bindings/reset/actions,s700-reset.h b/include/dt-bindings/reset/actions,s700-reset.h
> index 5e3b16b8ef53..a3118de6d7aa 100644
> --- a/include/dt-bindings/reset/actions,s700-reset.h
> +++ b/include/dt-bindings/reset/actions,s700-reset.h
> @@ -30,5 +30,8 @@
> #define RESET_UART4 20
> #define RESET_UART5 21
> #define RESET_UART6 22
> +#define RESET_SD0 23
> +#define RESET_SD1 24
> +#define RESET_SD2 25
>
> #endif /* __DT_BINDINGS_ACTIONS_S700_RESET_H */
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH net-next 2/4] net: phy: dp83869: Set opmode from straps
From: Andrew Lunn @ 2020-05-19 18:29 UTC (permalink / raw)
To: Jakub Kicinski
Cc: Dan Murphy, f.fainelli, hkallweit1, davem, netdev, linux-kernel,
devicetree
In-Reply-To: <20200519095818.425d227b@kicinski-fedora-pc1c0hjn.dhcp.thefacebook.com>
On Tue, May 19, 2020 at 09:58:18AM -0700, Jakub Kicinski wrote:
> On Tue, 19 May 2020 09:18:11 -0500 Dan Murphy wrote:
> > If the op-mode for the device is not set in the device tree then set
> > the strapped op-mode and store it for later configuration.
> >
> > Signed-off-by: Dan Murphy <dmurphy@ti.com>
>
> ../drivers/net/phy/dp83869.c: In function0 dp83869_set_strapped_mode:
> ../drivers/net/phy/dp83869.c:171:10: warning: comparison is always false due to limited range of data type [-Wtype-limits]
> 171 | if (val < 0)
> | ^
Hi Jakub
This happens a lot with PHY drivers. The register being read is a u16,
so that is what people use.
Is this now a standard GCC warning? Or have you turned on extra
checking?
Andrew
^ permalink raw reply
* Re: [PATCH v2 01/14] dt-bindings: arm: add a binding document for MediaTek PERICFG controller
From: Rob Herring @ 2020-05-19 18:28 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: David S . Miller, Matthias Brugger, John Crispin, Sean Wang,
Mark Lee, Jakub Kicinski, Arnd Bergmann, Fabien Parent,
Heiner Kallweit, Edwin Peer, devicetree, linux-kernel, netdev,
linux-arm-kernel, linux-mediatek, Stephane Le Provost, Pedro Tsai,
Andrew Perepech, Bartosz Golaszewski
In-Reply-To: <20200511150759.18766-2-brgl@bgdev.pl>
On Mon, May 11, 2020 at 05:07:46PM +0200, Bartosz Golaszewski wrote:
> From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>
> This adds a binding document for the PERICFG controller present on
> MediaTek SoCs. For now the only variant supported is 'mt8516-pericfg'.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> ---
> .../arm/mediatek/mediatek,pericfg.yaml | 34 +++++++++++++++++++
> 1 file changed, 34 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
> new file mode 100644
> index 000000000000..74b2a6173ffb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
> @@ -0,0 +1,34 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,pericfg.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: MediaTek Peripheral Configuration Controller
> +
> +maintainers:
> + - Bartosz Golaszewski <bgolaszewski@baylibre.com>
> +
> +properties:
> + compatible:
> + oneOf:
Don't need oneOf here.
> + - items:
> + - enum:
> + - mediatek,pericfg
Doesn't match the example (which is correct).
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + pericfg: pericfg@10003050 {
> + compatible = "mediatek,mt8516-pericfg", "syscon";
> + reg = <0 0x10003050 0 0x1000>;
> + };
> --
> 2.25.0
>
^ permalink raw reply
* Re: [PATCH v7 7/7] input: joystick: Add ADC attached joystick driver.
From: Jonathan Cameron @ 2020-05-19 18:25 UTC (permalink / raw)
To: Artur Rojek
Cc: Dmitry Torokhov, Rob Herring, Mark Rutland, Jonathan Cameron,
Paul Cercueil, Andy Shevchenko, Heiko Stuebner, Ezequiel Garcia,
linux-input, devicetree, linux-iio, linux-kernel
In-Reply-To: <20200517194904.34758-7-contact@artur-rojek.eu>
On Sun, 17 May 2020 21:49:04 +0200
Artur Rojek <contact@artur-rojek.eu> wrote:
> Add a driver for joystick devices connected to ADC controllers
> supporting the Industrial I/O subsystem.
>
> Signed-off-by: Artur Rojek <contact@artur-rojek.eu>
> Tested-by: Paul Cercueil <paul@crapouillou.net>
> Tested-by: Heiko Stuebner <heiko@sntech.de>
> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
For the rest of the patches I haven't commented on I'm
find with this but will be looking for a dt review tag from Rob.
+ you'll want to fix the > which should be a | that is annoying Rob's
bot (at least I guess that is what it is)
Thanks,
Jonathan
> ---
>
> Changes:
>
> v2: - sanity check supported channel format on probe,
> - rename adc_joystick_disable to a more sensible adc_joystick_cleanup,
> - enforce correct axis order by checking the `reg` property of
> child nodes
>
> v3-v5: no change
>
> v6: - remove redundant `<linux/of.h>`
> - set `val` for each endianness case in their respective branches
> - pass received error codes to return value of `adc_joystick_set_axes`
> - change `(bits >> 3) > 2` to `bits > 16` for readability
> - drop `of_match_ptr`
>
> v7: no change
>
> drivers/input/joystick/Kconfig | 10 +
> drivers/input/joystick/Makefile | 1 +
> drivers/input/joystick/adc-joystick.c | 253 ++++++++++++++++++++++++++
> 3 files changed, 264 insertions(+)
> create mode 100644 drivers/input/joystick/adc-joystick.c
>
> diff --git a/drivers/input/joystick/Kconfig b/drivers/input/joystick/Kconfig
> index 940b744639c7..efbc20ec5099 100644
> --- a/drivers/input/joystick/Kconfig
> +++ b/drivers/input/joystick/Kconfig
> @@ -42,6 +42,16 @@ config JOYSTICK_A3D
> To compile this driver as a module, choose M here: the
> module will be called a3d.
>
> +config JOYSTICK_ADC
> + tristate "Simple joystick connected over ADC"
> + depends on IIO
> + select IIO_BUFFER_CB
> + help
> + Say Y here if you have a simple joystick connected over ADC.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called adc-joystick.
> +
> config JOYSTICK_ADI
> tristate "Logitech ADI digital joysticks and gamepads"
> select GAMEPORT
> diff --git a/drivers/input/joystick/Makefile b/drivers/input/joystick/Makefile
> index 8656023f6ef5..58232b3057d3 100644
> --- a/drivers/input/joystick/Makefile
> +++ b/drivers/input/joystick/Makefile
> @@ -6,6 +6,7 @@
> # Each configuration option enables a list of files.
>
> obj-$(CONFIG_JOYSTICK_A3D) += a3d.o
> +obj-$(CONFIG_JOYSTICK_ADC) += adc-joystick.o
> obj-$(CONFIG_JOYSTICK_ADI) += adi.o
> obj-$(CONFIG_JOYSTICK_AMIGA) += amijoy.o
> obj-$(CONFIG_JOYSTICK_AS5011) += as5011.o
> diff --git a/drivers/input/joystick/adc-joystick.c b/drivers/input/joystick/adc-joystick.c
> new file mode 100644
> index 000000000000..a4ba8eac5a12
> --- /dev/null
> +++ b/drivers/input/joystick/adc-joystick.c
> @@ -0,0 +1,253 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Input driver for joysticks connected over ADC.
> + * Copyright (c) 2019-2020 Artur Rojek <contact@artur-rojek.eu>
> + */
> +#include <linux/ctype.h>
> +#include <linux/input.h>
> +#include <linux/iio/iio.h>
> +#include <linux/iio/consumer.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/property.h>
> +
> +struct adc_joystick_axis {
> + u32 code;
> + s32 range[2];
> + s32 fuzz;
> + s32 flat;
> +};
> +
> +struct adc_joystick {
> + struct input_dev *input;
> + struct iio_cb_buffer *buffer;
> + struct adc_joystick_axis *axes;
> + struct iio_channel *chans;
> + int num_chans;
> +};
> +
> +static int adc_joystick_handle(const void *data, void *private)
> +{
> + struct adc_joystick *joy = private;
> + enum iio_endian endianness;
> + int bytes, msb, val, i;
> + bool sign;
> +
> + bytes = joy->chans[0].channel->scan_type.storagebits >> 3;
> +
> + for (i = 0; i < joy->num_chans; ++i) {
> + endianness = joy->chans[i].channel->scan_type.endianness;
> + msb = joy->chans[i].channel->scan_type.realbits - 1;
> + sign = (tolower(joy->chans[i].channel->scan_type.sign) == 's');
> +
> + switch (bytes) {
> + case 1:
> + val = ((const u8 *)data)[i];
> + break;
> + case 2:
> + if (endianness == IIO_BE)
> + val = be16_to_cpu(((const u16 *)data)[i]);
> + else if (endianness == IIO_LE)
> + val = le16_to_cpu(((const u16 *)data)[i]);
> + else /* IIO_CPU */
> + val = ((const u16 *)data)[i];
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + val >>= joy->chans[i].channel->scan_type.shift;
> + if (sign)
> + val = sign_extend32(val, msb);
> + else
> + val &= GENMASK(msb, 0);
> + input_report_abs(joy->input, joy->axes[i].code, val);
> + }
> +
> + input_sync(joy->input);
> +
> + return 0;
> +}
> +
> +static int adc_joystick_open(struct input_dev *dev)
> +{
> + struct adc_joystick *joy = input_get_drvdata(dev);
> + int ret;
> +
> + ret = iio_channel_start_all_cb(joy->buffer);
> + if (ret)
> + dev_err(dev->dev.parent, "Unable to start callback buffer");
> +
> + return ret;
> +}
> +
> +static void adc_joystick_close(struct input_dev *dev)
> +{
> + struct adc_joystick *joy = input_get_drvdata(dev);
> +
> + iio_channel_stop_all_cb(joy->buffer);
> +}
> +
> +static void adc_joystick_cleanup(void *data)
> +{
> + iio_channel_release_all_cb(data);
> +}
> +
> +static int adc_joystick_set_axes(struct device *dev, struct adc_joystick *joy)
> +{
> + struct adc_joystick_axis *axes;
> + struct fwnode_handle *child;
> + int num_axes, ret, i;
> +
> + num_axes = device_get_child_node_count(dev);
> + if (!num_axes) {
> + dev_err(dev, "Unable to find child nodes");
> + return -EINVAL;
> + }
> +
> + if (num_axes != joy->num_chans) {
> + dev_err(dev, "Got %d child nodes for %d channels",
> + num_axes, joy->num_chans);
> + return -EINVAL;
> + }
> +
> + axes = devm_kmalloc_array(dev, num_axes, sizeof(*axes), GFP_KERNEL);
> + if (!axes)
> + return -ENOMEM;
> +
> + device_for_each_child_node(dev, child) {
> + ret = fwnode_property_read_u32(child, "reg", &i);
> + if (ret) {
> + dev_err(dev, "reg invalid or missing");
> + goto err;
> + }
> +
> + if (i >= num_axes) {
> + ret = -EINVAL;
> + dev_err(dev, "No matching axis for reg %d", i);
> + goto err;
> + }
> +
> + ret = fwnode_property_read_u32(child, "linux,code",
> + &axes[i].code);
> + if (ret) {
> + dev_err(dev, "linux,code invalid or missing");
> + goto err;
> + }
> +
> + ret = fwnode_property_read_u32_array(child, "abs-range",
> + axes[i].range, 2);
> + if (ret) {
> + dev_err(dev, "abs-range invalid or missing");
> + goto err;
> + }
> +
> + fwnode_property_read_u32(child, "abs-fuzz",
> + &axes[i].fuzz);
> + fwnode_property_read_u32(child, "abs-flat",
> + &axes[i].flat);
> +
> + input_set_abs_params(joy->input, axes[i].code,
> + axes[i].range[0], axes[i].range[1],
> + axes[i].fuzz,
> + axes[i].flat);
> + input_set_capability(joy->input, EV_ABS, axes[i].code);
> + }
> +
> + joy->axes = axes;
> +
> + return 0;
> +
> +err:
> + fwnode_handle_put(child);
> + return ret;
> +}
> +
> +static int adc_joystick_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct adc_joystick *joy;
> + struct input_dev *input;
> + int bits, ret, i;
> +
> + joy = devm_kzalloc(dev, sizeof(*joy), GFP_KERNEL);
> + if (!joy)
> + return -ENOMEM;
> +
> + joy->chans = devm_iio_channel_get_all(dev);
> + if (IS_ERR(joy->chans)) {
> + ret = PTR_ERR(joy->chans);
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev, "Unable to get IIO channels");
> + return ret;
> + }
> +
> + /* Count how many channels we got. NULL terminated. */
> + while (joy->chans[joy->num_chans].indio_dev)
> + joy->num_chans++;
> +
> + bits = joy->chans[0].channel->scan_type.storagebits;
> + if (!bits || (bits > 16)) {
> + dev_err(dev, "Unsupported channel storage size");
> + return -EINVAL;
> + }
> + for (i = 1; i < joy->num_chans; ++i)
> + if (joy->chans[i].channel->scan_type.storagebits != bits) {
> + dev_err(dev, "Channels must have equal storage size");
> + return -EINVAL;
> + }
> +
> + input = devm_input_allocate_device(dev);
> + if (!input) {
> + dev_err(dev, "Unable to allocate input device");
> + return -ENOMEM;
> + }
> +
> + joy->input = input;
> + input->name = pdev->name;
> + input->id.bustype = BUS_HOST;
> + input->open = adc_joystick_open;
> + input->close = adc_joystick_close;
> +
> + ret = adc_joystick_set_axes(dev, joy);
> + if (ret)
> + return ret;
> +
> + input_set_drvdata(input, joy);
> + ret = input_register_device(input);
> + if (ret) {
> + dev_err(dev, "Unable to register input device: %d", ret);
> + return ret;
> + }
> +
> + joy->buffer = iio_channel_get_all_cb(dev, adc_joystick_handle, joy);
> + if (IS_ERR(joy->buffer)) {
> + dev_err(dev, "Unable to allocate callback buffer");
> + return PTR_ERR(joy->buffer);
> + }
> +
> + ret = devm_add_action_or_reset(dev, adc_joystick_cleanup, joy->buffer);
> + if (ret)
> + dev_err(dev, "Unable to add action");
> +
> + return ret;
> +}
> +
> +static const struct of_device_id adc_joystick_of_match[] = {
> + { .compatible = "adc-joystick", },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, adc_joystick_of_match);
> +
> +static struct platform_driver adc_joystick_driver = {
> + .driver = {
> + .name = "adc-joystick",
> + .of_match_table = adc_joystick_of_match,
> + },
> + .probe = adc_joystick_probe,
> +};
> +module_platform_driver(adc_joystick_driver);
> +
> +MODULE_DESCRIPTION("Input driver for joysticks connected over ADC");
> +MODULE_AUTHOR("Artur Rojek <contact@artur-rojek.eu>");
> +MODULE_LICENSE("GPL");
^ permalink raw reply
* Re: [PATCH v8 1/6] MIPS: JZ4780: Introduce SMP support.
From: kbuild test robot @ 2020-05-19 18:21 UTC (permalink / raw)
To: 周琰杰 (Zhou Yanjie), linux-mips
Cc: kbuild-all, linux-kernel, devicetree, tsbogend, paulburton,
jiaxun.yang, chenhc, tglx, robh+dt, daniel.lezcano
In-Reply-To: <1589898923-60048-3-git-send-email-zhouyanjie@wanyeetech.com>
[-- Attachment #1: Type: text/plain, Size: 2668 bytes --]
Hi "周琰杰,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on tip/timers/core linus/master v5.7-rc6]
[cannot apply to linux/master next-20200518]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Zhou-Yanjie/Introduce-SMP-support-for-CI20-based-on-JZ4780/20200519-224008
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: mips-allyesconfig (attached as .config)
compiler: mips-linux-gcc (GCC) 9.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=mips
If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp@intel.com>
All warnings (new ones prefixed by >>, old ones prefixed by <<):
>> arch/mips/kernel/idle.c:97:6: warning: no previous prototype for 'jz4780_smp_wait_irqoff' [-Wmissing-prototypes]
97 | void jz4780_smp_wait_irqoff(void)
| ^~~~~~~~~~~~~~~~~~~~~~
arch/mips/kernel/idle.c:155:13: warning: no previous prototype for 'check_wait' [-Wmissing-prototypes]
155 | void __init check_wait(void)
| ^~~~~~~~~~
vim +/jz4780_smp_wait_irqoff +97 arch/mips/kernel/idle.c
90
91 /*
92 * The Ingenic jz4780 SMP variant has to write back dirty cache lines before
93 * executing wait. The CPU & cache clock will be gated until we return from
94 * the wait, and if another core attempts to access data from our data cache
95 * during this time then it will lock up.
96 */
> 97 void jz4780_smp_wait_irqoff(void)
98 {
99 unsigned long pending = read_c0_cause() & read_c0_status() & CAUSEF_IP;
100
101 /*
102 * Going to idle has a significant overhead due to the cache flush so
103 * try to avoid it if we'll immediately be woken again due to an IRQ.
104 */
105 if (!need_resched() && !pending) {
106 r4k_blast_dcache();
107
108 __asm__(
109 " .set push \n"
110 " .set mips3 \n"
111 " sync \n"
112 " wait \n"
113 " .set pop \n");
114 }
115
116 local_irq_enable();
117 }
118
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 65515 bytes --]
^ permalink raw reply
* Re: [PATCH] drivers/of: keep description of function consistent with function name
From: Rob Herring @ 2020-05-19 18:24 UTC (permalink / raw)
To: qiwuchen55; +Cc: devicetree, chenqiwu, robh+dt, frowand.list
In-Reply-To: <1589209497-13945-1-git-send-email-qiwuchen55@gmail.com>
On Mon, 11 May 2020 23:04:57 +0800, wrote:
> From: chenqiwu <chenqiwu@xiaomi.com>
>
> Currently, there are some descriptions of function not
> consistent with function name, fixing them will make
> the code more readable.
>
> Signed-off-by: chenqiwu <chenqiwu@xiaomi.com>
> ---
> drivers/of/fdt.c | 2 +-
> drivers/of/of_reserved_mem.c | 10 +++++-----
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
Applied, thanks!
^ permalink raw reply
* [PATCH v2 10/10] arm64: dts: actions: Add uSD support for Cubieboard7
From: Amit Singh Tomar @ 2020-05-19 18:19 UTC (permalink / raw)
To: andre.przywara, afaerber, manivannan.sadhasivam, robh+dt
Cc: cristian.ciocaltea, linux-kernel, linux-arm-kernel, linux-actions,
devicetree
In-Reply-To: <1589912368-480-1-git-send-email-amittomer25@gmail.com>
This commit adds uSD support for Cubieboard7 board based on Actions Semi
S700 SoC. SD0 is connected to uSD slot. Since there is no PMIC support
added yet, fixed regulator has been used as a regulator node.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
---
Changes since v1:
* No change.
Changes since RFC:
* No change.
---
arch/arm64/boot/dts/actions/s700-cubieboard7.dts | 41 ++++++++++++++++++++++++
arch/arm64/boot/dts/actions/s700.dtsi | 1 +
2 files changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
index 63e375cd9eb4..ec117eb12f3a 100644
--- a/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
+++ b/arch/arm64/boot/dts/actions/s700-cubieboard7.dts
@@ -13,6 +13,7 @@
aliases {
serial3 = &uart3;
+ mmc0 = &mmc0;
};
chosen {
@@ -28,6 +29,23 @@
device_type = "memory";
reg = <0x1 0xe0000000 0x0 0x0>;
};
+
+ /* Fixed regulator used in the absence of PMIC */
+ vcc_3v1: vcc-3v1 {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.1V";
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3100000>;
+ };
+
+ /* Fixed regulator used in the absence of PMIC */
+ sd_vcc: sd-vcc {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.1V";
+ regulator-min-microvolt = <3100000>;
+ regulator-max-microvolt = <3100000>;
+ regulator-always-on;
+ };
};
&i2c0 {
@@ -81,6 +99,14 @@
bias-pull-up;
};
};
+
+ mmc0_default: mmc0_default {
+ pinmux {
+ groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
+ "sd0_cmd_mfp", "sd0_clk_mfp";
+ function = "sd0";
+ };
+ };
};
&timer {
@@ -90,3 +116,18 @@
&uart3 {
status = "okay";
};
+
+/* uSD */
+&mmc0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_default>;
+ cd-gpios = <&pinctrl 120 GPIO_ACTIVE_LOW>;
+ no-sdio;
+ no-mmc;
+ no-1-8-v;
+ bus-width = <4>;
+ vmmc-supply = <&sd_vcc>;
+ vqmmc-supply = <&sd_vcc>;
+};
+
diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi
index 0d3ff315b00e..18700aeb8d2b 100644
--- a/arch/arm64/boot/dts/actions/s700.dtsi
+++ b/arch/arm64/boot/dts/actions/s700.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/clock/actions,s700-cmu.h>
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/actions,s700-reset.h>
--
2.7.4
^ permalink raw reply related
* [PATCH v2 09/10] arm64: dts: actions: Add MMC controller support for S700
From: Amit Singh Tomar @ 2020-05-19 18:19 UTC (permalink / raw)
To: andre.przywara, afaerber, manivannan.sadhasivam, robh+dt
Cc: cristian.ciocaltea, linux-kernel, linux-arm-kernel, linux-actions,
devicetree
In-Reply-To: <1589912368-480-1-git-send-email-amittomer25@gmail.com>
This commits adds support for MMC controllers present on Actions S700 SoC,
there are 3 MMC controllers in this SoC which can be used for accessing
SD/EMMC/SDIO cards.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
---
Changes since v1:
* Added SoC specific compatibe string.
Changes since RFC:
* No change.
---
arch/arm64/boot/dts/actions/s700.dtsi | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi
index 56f2f84812cb..0d3ff315b00e 100644
--- a/arch/arm64/boot/dts/actions/s700.dtsi
+++ b/arch/arm64/boot/dts/actions/s700.dtsi
@@ -258,5 +258,38 @@
dma-requests = <44>;
clocks = <&cmu CLK_DMAC>;
};
+
+ mmc0: mmc@e0210000 {
+ compatible = "actions,s700-mmc", "actions,owl-mmc";
+ reg = <0x0 0xe0210000 0x0 0x4000>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_SD0>;
+ resets = <&cmu RESET_SD0>;
+ dmas = <&dma 2>;
+ dma-names = "mmc";
+ status = "disabled";
+ };
+
+ mmc1: mmc@e0214000 {
+ compatible = "actions,s700-mmc", "actions,owl-mmc";
+ reg = <0x0 0xe0214000 0x0 0x4000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_SD1>;
+ resets = <&cmu RESET_SD1>;
+ dmas = <&dma 3>;
+ dma-names = "mmc";
+ status = "disabled";
+ };
+
+ mmc2: mmc@e0218000 {
+ compatible = "actions,s700-mmc", "actions,owl-mmc";
+ reg = <0x0 0xe0218000 0x0 0x4000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_SD2>;
+ resets = <&cmu RESET_SD2>;
+ dmas = <&dma 4>;
+ dma-names = "mmc";
+ status = "disabled";
+ };
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH v2 08/10] dt-bindings: mmc: owl: add compatible string actions,s700-mmc
From: Amit Singh Tomar @ 2020-05-19 18:19 UTC (permalink / raw)
To: andre.przywara, afaerber, manivannan.sadhasivam, robh+dt
Cc: cristian.ciocaltea, linux-kernel, linux-arm-kernel, linux-actions,
devicetree
In-Reply-To: <1589912368-480-1-git-send-email-amittomer25@gmail.com>
The commit adds a new SoC specific compatible string "actions,s700-mmc"
in combination with more generic string "actions,owl-mmc".
Placement order of these strings should abide by the principle of
"from most specific to most general".
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
---
* Newly added patch in v2.
---
Documentation/devicetree/bindings/mmc/owl-mmc.yaml | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mmc/owl-mmc.yaml b/Documentation/devicetree/bindings/mmc/owl-mmc.yaml
index 12b40213426d..9604ef695585 100644
--- a/Documentation/devicetree/bindings/mmc/owl-mmc.yaml
+++ b/Documentation/devicetree/bindings/mmc/owl-mmc.yaml
@@ -14,7 +14,11 @@ maintainers:
properties:
compatible:
- const: actions,owl-mmc
+ oneOf:
+ - const: actions,owl-mmc
+ - items:
+ - const: actions,s700-mmc
+ - const: actions,owl-mmc
reg:
maxItems: 1
--
2.7.4
^ permalink raw reply related
* [PATCH v2 07/10] dt-bindings: reset: s700: Add binding constants for mmc
From: Amit Singh Tomar @ 2020-05-19 18:19 UTC (permalink / raw)
To: andre.przywara, afaerber, manivannan.sadhasivam, robh+dt
Cc: cristian.ciocaltea, linux-kernel, linux-arm-kernel, linux-actions,
devicetree
In-Reply-To: <1589912368-480-1-git-send-email-amittomer25@gmail.com>
This commit adds device tree binding reset constants for mmc controller
present on Actions S700 Soc.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
---
Changes since v1:
* No change.
Changes since RFC:
* added Rob's acked-by tag
---
include/dt-bindings/reset/actions,s700-reset.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/dt-bindings/reset/actions,s700-reset.h b/include/dt-bindings/reset/actions,s700-reset.h
index 5e3b16b8ef53..a3118de6d7aa 100644
--- a/include/dt-bindings/reset/actions,s700-reset.h
+++ b/include/dt-bindings/reset/actions,s700-reset.h
@@ -30,5 +30,8 @@
#define RESET_UART4 20
#define RESET_UART5 21
#define RESET_UART6 22
+#define RESET_SD0 23
+#define RESET_SD1 24
+#define RESET_SD2 25
#endif /* __DT_BINDINGS_ACTIONS_S700_RESET_H */
--
2.7.4
^ permalink raw reply related
* [PATCH v2 06/10] arm64: dts: actions: Add DMA Controller for S700
From: Amit Singh Tomar @ 2020-05-19 18:19 UTC (permalink / raw)
To: andre.przywara, afaerber, vkoul, manivannan.sadhasivam, robh+dt
Cc: dan.j.williams, cristian.ciocaltea, linux-kernel,
linux-arm-kernel, linux-actions, devicetree
In-Reply-To: <1589912368-480-1-git-send-email-amittomer25@gmail.com>
This commit adds DAM controller present on Actions S700, it differs from
S900 in terms of number of dma channels and requests.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
---
Changes since v1:
* No Change.
Changes since RFC:
* No Change.
---
arch/arm64/boot/dts/actions/s700.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi
index 0397c5dd3dec..56f2f84812cb 100644
--- a/arch/arm64/boot/dts/actions/s700.dtsi
+++ b/arch/arm64/boot/dts/actions/s700.dtsi
@@ -245,5 +245,18 @@
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ dma: dma-controller@e0230000 {
+ compatible = "actions,s700-dma";
+ reg = <0x0 0xe0230000 0x0 0x1000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <10>;
+ dma-requests = <44>;
+ clocks = <&cmu CLK_DMAC>;
+ };
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH v2 05/10] dt-bindings: dmaengine: convert Actions Semi Owl SoCs bindings to yaml
From: Amit Singh Tomar @ 2020-05-19 18:19 UTC (permalink / raw)
To: andre.przywara, afaerber, vkoul, manivannan.sadhasivam, robh+dt
Cc: dan.j.williams, cristian.ciocaltea, linux-kernel,
linux-arm-kernel, linux-actions, devicetree
In-Reply-To: <1589912368-480-1-git-send-email-amittomer25@gmail.com>
Converts the device tree bindings for the Actions Semi Owl SoCs DMA
Controller over to YAML schemas.
It also adds new compatible string "actions,s700-dma".
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
---
Change since v1:
* Updated the description field to reflect
only the necessary information.
* replaced the maxItems field with description for each
controller attribute(except interrupts).
* Replaced the clock macro with number to keep the example
as independent as possible.
New patch, was not there in RFC.
---
Documentation/devicetree/bindings/dma/owl-dma.txt | 47 -------------
Documentation/devicetree/bindings/dma/owl-dma.yaml | 76 ++++++++++++++++++++++
2 files changed, 76 insertions(+), 47 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/dma/owl-dma.txt
create mode 100644 Documentation/devicetree/bindings/dma/owl-dma.yaml
diff --git a/Documentation/devicetree/bindings/dma/owl-dma.txt b/Documentation/devicetree/bindings/dma/owl-dma.txt
deleted file mode 100644
index 03e9bb12b75f..000000000000
--- a/Documentation/devicetree/bindings/dma/owl-dma.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-* Actions Semi Owl SoCs DMA controller
-
-This binding follows the generic DMA bindings defined in dma.txt.
-
-Required properties:
-- compatible: Should be "actions,s900-dma".
-- reg: Should contain DMA registers location and length.
-- interrupts: Should contain 4 interrupts shared by all channel.
-- #dma-cells: Must be <1>. Used to represent the number of integer
- cells in the dmas property of client device.
-- dma-channels: Physical channels supported.
-- dma-requests: Number of DMA request signals supported by the controller.
- Refer to Documentation/devicetree/bindings/dma/dma.txt
-- clocks: Phandle and Specifier of the clock feeding the DMA controller.
-
-Example:
-
-Controller:
- dma: dma-controller@e0260000 {
- compatible = "actions,s900-dma";
- reg = <0x0 0xe0260000 0x0 0x1000>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- dma-channels = <12>;
- dma-requests = <46>;
- clocks = <&clock CLK_DMAC>;
- };
-
-Client:
-
-DMA clients connected to the Actions Semi Owl SoCs DMA controller must
-use the format described in the dma.txt file, using a two-cell specifier
-for each channel.
-
-The two cells in order are:
-1. A phandle pointing to the DMA controller.
-2. The channel id.
-
-uart5: serial@e012a000 {
- ...
- dma-names = "tx", "rx";
- dmas = <&dma 26>, <&dma 27>;
- ...
-};
diff --git a/Documentation/devicetree/bindings/dma/owl-dma.yaml b/Documentation/devicetree/bindings/dma/owl-dma.yaml
new file mode 100644
index 000000000000..82e7d261e967
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/owl-dma.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/owl-dma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Actions Semi Owl SoCs DMA controller
+
+description: |
+ The OWL DMA is a general-purpose direct memory access controller capable of
+ supporting 10 and 12 independent DMA channels for S700 and S900 SoCs
+ respectively.
+
+maintainers:
+ - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+allOf:
+ - $ref: "dma-controller.yaml#"
+
+properties:
+ compatible:
+ enum:
+ - actions,s900-dma
+ - actions,s700-dma
+
+ reg:
+ description:
+ DMA registers location and length.
+
+ interrupts:
+ description:
+ controller supports 4 interrupts, which are freely assignable to the
+ DMA channels.
+ maxItems: 4
+
+ "#dma-cells":
+ const: 1
+
+ dma-channels:
+ description:
+ Physical channels supported.
+
+ dma-requests:
+ description:
+ Number of DMA request signals supported by the controller.
+
+ clocks:
+ description:
+ Phandle and Specifier of the clock feeding the DMA controller.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#dma-cells"
+ - dma-channels
+ - dma-requests
+ - clocks
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ dma: dma-controller@e0260000 {
+ compatible = "actions,s900-dma";
+ reg = <0x0 0xe0260000 0x0 0x1000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <12>;
+ dma-requests = <46>;
+ clocks = <&clock 22>;
+ };
+
+...
--
2.7.4
^ permalink raw reply related
* [PATCH v2 6/6] sc16is7xx: Read the LSR register for basic device presence check
From: Daniel Mack @ 2020-05-19 18:21 UTC (permalink / raw)
To: devicetree, linux-serial
Cc: gregkh, robh+dt, jslaby, jringle, m.brock, pascal.huerst,
Daniel Mack
In-Reply-To: <20200519182147.218713-1-daniel@zonque.org>
Currently, the driver probes just fine and binds all its resources even
if the physical device is not present.
As the device lacks an identification register, let's at least read the
LSR register to check whether a device at the configured address responds
to the request at all.
Signed-off-by: Daniel Mack <daniel@zonque.org>
---
drivers/tty/serial/sc16is7xx.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c
index 7e2360f8e393..5e84ed5938af 100644
--- a/drivers/tty/serial/sc16is7xx.c
+++ b/drivers/tty/serial/sc16is7xx.c
@@ -1181,6 +1181,7 @@ static int sc16is7xx_probe(struct device *dev,
{
struct sched_param sched_param = { .sched_priority = MAX_RT_PRIO / 2 };
unsigned long freq = 0, *pfreq = dev_get_platdata(dev);
+ unsigned int val;
u32 uartclk = 0;
int i, ret;
struct sc16is7xx_port *s;
@@ -1188,6 +1189,16 @@ static int sc16is7xx_probe(struct device *dev,
if (IS_ERR(regmap))
return PTR_ERR(regmap);
+ /*
+ * This device does not have an identification register that would
+ * tell us if we are really connected to the correct device.
+ * The best we can do is to check if communication is at all possible.
+ */
+ ret = regmap_read(regmap,
+ SC16IS7XX_LSR_REG << SC16IS7XX_REG_SHIFT, &val);
+ if (ret < 0)
+ return ret;
+
/* Alloc port structure */
s = devm_kzalloc(dev, struct_size(s, p, devtype->nr_uart), GFP_KERNEL);
if (!s) {
--
2.26.2
^ permalink raw reply related
* [PATCH v2 04/10] arm64: dts: actions: *do not merge* disable sps node from S700
From: Amit Singh Tomar @ 2020-05-19 18:19 UTC (permalink / raw)
To: andre.przywara, afaerber, manivannan.sadhasivam, robh+dt
Cc: cristian.ciocaltea, linux-kernel, linux-arm-kernel, linux-actions,
devicetree
In-Reply-To: <1589912368-480-1-git-send-email-amittomer25@gmail.com>
After commit 7cdf8446ed1d ("arm64: dts: actions: Add pinctrl node for
Actions Semi S700") following error has been observed while booting
Linux on Cubieboard7-lite(based on S700 SoC).
[ 0.257415] pinctrl-s700 e01b0000.pinctrl: can't request region for
resource [mem 0xe01b0000-0xe01b0fff]
[ 0.266902] pinctrl-s700: probe of e01b0000.pinctrl failed with error -16
This is due to the fact that memory range for "sps" power domain controller
clashes with pinctrl.
This commit disable "sps" to avoid this conflict and let us test DMA and MMC
related changes.
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
---
Changes since v1:
* No change.
Changes since RFC:
* kept as do not merge.
---
arch/arm64/boot/dts/actions/s700.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/actions/s700.dtsi b/arch/arm64/boot/dts/actions/s700.dtsi
index 2006ad5424fa..0397c5dd3dec 100644
--- a/arch/arm64/boot/dts/actions/s700.dtsi
+++ b/arch/arm64/boot/dts/actions/s700.dtsi
@@ -220,6 +220,7 @@
compatible = "actions,s700-sps";
reg = <0x0 0xe01b0100 0x0 0x100>;
#power-domain-cells = <1>;
+ status = "disabled";
};
timer: timer@e024c000 {
--
2.7.4
^ permalink raw reply related
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