* Re: [PATCH] arm64: dts: imx8mm: Add support for micfil
From: Shawn Guo @ 2020-05-20 1:03 UTC (permalink / raw)
To: Adam Ford
Cc: linux-arm-kernel, aford, Rob Herring, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Catalin Marinas, Will Deacon, devicetree, linux-kernel
In-Reply-To: <20200502125949.194032-2-aford173@gmail.com>
On Sat, May 02, 2020 at 07:59:48AM -0500, Adam Ford wrote:
> The i.MX8M Mini has supports the MICFIL digital interface.
> It's a 16-bit audio signal from a PDM microphone bitstream.
> The driver is already in the kernel, but the node is missing.
>
> This patch adds the micfil node.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index c63685ae80ee..d46e727fc362 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -339,6 +339,25 @@ sai6: sai@30060000 {
> status = "disabled";
> };
>
> + micfil: micfil@30080000 {
Find a generic node name, audio-controller maybe?
Shawn
> + compatible = "fsl,imx8mm-micfil";
> + reg = <0x30080000 0x10000>;
> + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MM_CLK_PDM_IPG>,
> + <&clk IMX8MM_CLK_PDM_ROOT>,
> + <&clk IMX8MM_AUDIO_PLL1_OUT>,
> + <&clk IMX8MM_AUDIO_PLL2_OUT>,
> + <&clk IMX8MM_CLK_EXT3>;
> + clock-names = "ipg_clk", "ipg_clk_app",
> + "pll8k", "pll11k", "clkext3";
> + dmas = <&sdma2 24 25 0x80000000>;
> + dma-names = "rx";
> + status = "disabled";
> + };
> +
> gpio1: gpio@30200000 {
> compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
> reg = <0x30200000 0x10000>;
> --
> 2.25.1
>
^ permalink raw reply
* Re: [PATCH] arm64: defconfig: Enable some audio drivers on i.MX8M Mini
From: Shawn Guo @ 2020-05-20 1:02 UTC (permalink / raw)
To: Adam Ford
Cc: linux-arm-kernel, aford, Rob Herring, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
Catalin Marinas, Will Deacon, devicetree, linux-kernel
In-Reply-To: <20200502125949.194032-1-aford173@gmail.com>
On Sat, May 02, 2020 at 07:59:47AM -0500, Adam Ford wrote:
> The i.MX8M Mini has SAI and micfil support but the drivers
> are not being loaded.
>
> This patch updates the defconfig to add support
> CONFIG_SND_SOC_FSL_SAI and CONFIG_SND_SOC_FSL_MICFIL to support
> these drivers.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 366857dfa9de..4e60e8a98b83 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -638,6 +638,8 @@ CONFIG_SND_HDA_TEGRA=m
> CONFIG_SND_HDA_CODEC_HDMI=m
> CONFIG_SND_SOC=y
> CONFIG_SND_BCM2835_SOC_I2S=m
> +CONFIG_SND_SOC_FSL_SAI=y
> +CONFIG_SND_SOC_FSL_MICFIL=y
Please enable them as 'm'.
Shawn
> CONFIG_SND_MESON_AXG_SOUND_CARD=m
> CONFIG_SND_SOC_SDM845=m
> CONFIG_SND_SOC_ROCKCHIP=m
> --
> 2.25.1
>
^ permalink raw reply
* Re: [PATCH v9 2/4] media: i2c: Add MAX9286 driver
From: Laurent Pinchart @ 2020-05-20 0:50 UTC (permalink / raw)
To: Sakari Ailus
Cc: Kieran Bingham, linux-renesas-soc, linux-media, devicetree,
linux-kernel, Mauro Carvalho Chehab, Kieran Bingham, Jacopo Mondi,
Niklas Söderlund, Hans Verkuil, Hyun Kwon,
Manivannan Sadhasivam, Rob Herring, Jacopo Mondi,
Laurent Pinchart, Niklas Söderlund
In-Reply-To: <930009cd-d887-752a-4f1f-567c795101ee@ideasonboard.com>
Hi Sakari,
On Mon, May 18, 2020 at 12:45:18PM +0100, Kieran Bingham wrote:
> Hi Sakari,
>
> There are only fairly minor comments here, fix ups will be included in a
> v10.
>
> Is there anything major blocking integration?
>
> On 16/05/2020 22:51, Sakari Ailus wrote:
> > On Tue, May 12, 2020 at 04:51:03PM +0100, Kieran Bingham wrote:
> >
> > ...
> >
> >> +static int max9286_enum_mbus_code(struct v4l2_subdev *sd,
> >> + struct v4l2_subdev_pad_config *cfg,
> >> + struct v4l2_subdev_mbus_code_enum *code)
> >> +{
> >> + if (code->pad || code->index > 0)
> >> + return -EINVAL;
> >> +
> >> + code->code = MEDIA_BUS_FMT_UYVY8_2X8;
> >
> > Why UYVY8_2X8 and not UYVY8_1X16? In general, the single sample / pixel
> > variant of the format is generally used on the serial busses. This choice
> > was made when serial busses were introduced.
This is a bit of a tricky one. On the camera size, for the RDACM20, the
O10635 sensor outputs UYVY8_2X8. This if fed to the MAX9271 serializer,
which doesn't care about the data type. The MAX9271 has a 16-bit input
bus, with 10 bits reserved for data, 2 bits dynamically configurable
to carry H/V sync or extra data, and 4 bits dynamically configurable to
carry GPIOs or extra data. The 16-bit words are then serialized (it's a
bit more complicated, when using the H/V sync signals they are
transmitted in a different way, and the MAX9271 also supports a DDR mode
that makes the "serial link word" carry up to 30 bits). Effectively, the
two samples of UYVY8_2X8 are serialized in a 16-bit word each.
Sakari, with this information in mind, what would you recommend ?
> Ok - I presume this doesn't really have much effect anyway, they just
> have to match for the transmitter/receiver?
>
> But it makes sense to me, so I'll update to the 1x16 variant.
>
> >> +
> >> + return 0;
> >> +}
> >> +
> >> +static struct v4l2_mbus_framefmt *
> >> +max9286_get_pad_format(struct max9286_priv *priv,
> >> + struct v4l2_subdev_pad_config *cfg,
> >> + unsigned int pad, u32 which)
> >> +{
> >> + switch (which) {
> >> + case V4L2_SUBDEV_FORMAT_TRY:
> >> + return v4l2_subdev_get_try_format(&priv->sd, cfg, pad);
> >> + case V4L2_SUBDEV_FORMAT_ACTIVE:
> >> + return &priv->fmt[pad];
> >> + default:
> >> + return NULL;
> >> + }
> >> +}
> >> +
> >> +static int max9286_set_fmt(struct v4l2_subdev *sd,
> >> + struct v4l2_subdev_pad_config *cfg,
> >> + struct v4l2_subdev_format *format)
> >> +{
> >> + struct max9286_priv *priv = sd_to_max9286(sd);
> >> + struct v4l2_mbus_framefmt *cfg_fmt;
> >> +
> >> + if (format->pad >= MAX9286_SRC_PAD)
> >> + return -EINVAL;
> >
> > You can remove these checks; it's been already done by the caller.
> >
>
> Ok.
>
>
> > ...
> >
> >> +static int max9286_parse_dt(struct max9286_priv *priv)
> >> +{
> >> + struct device *dev = &priv->client->dev;
> >> + struct device_node *i2c_mux;
> >> + struct device_node *node = NULL;
> >> + unsigned int i2c_mux_mask = 0;
> >> +
> >> + of_node_get(dev->of_node);
> >> + i2c_mux = of_find_node_by_name(dev->of_node, "i2c-mux");
> >> + if (!i2c_mux) {
> >> + dev_err(dev, "Failed to find i2c-mux node\n");
> >> + of_node_put(dev->of_node);
> >> + return -EINVAL;
> >> + }
> >> +
> >> + /* Identify which i2c-mux channels are enabled */
> >> + for_each_child_of_node(i2c_mux, node) {
> >> + u32 id = 0;
> >> +
> >> + of_property_read_u32(node, "reg", &id);
> >> + if (id >= MAX9286_NUM_GMSL)
> >> + continue;
> >> +
> >> + if (!of_device_is_available(node)) {
> >> + dev_dbg(dev, "Skipping disabled I2C bus port %u\n", id);
> >> + continue;
> >> + }
> >> +
> >> + i2c_mux_mask |= BIT(id);
> >> + }
> >> + of_node_put(node);
> >> + of_node_put(i2c_mux);
> >> +
> >> + /* Parse the endpoints */
> >> + for_each_endpoint_of_node(dev->of_node, node) {
> >> + struct max9286_source *source;
> >> + struct of_endpoint ep;
> >> +
> >> + of_graph_parse_endpoint(node, &ep);
> >> + dev_dbg(dev, "Endpoint %pOF on port %d",
> >> + ep.local_node, ep.port);
> >> +
> >> + if (ep.port > MAX9286_NUM_GMSL) {
> >> + dev_err(dev, "Invalid endpoint %s on port %d",
> >> + of_node_full_name(ep.local_node), ep.port);
> >> + continue;
> >> + }
> >> +
> >> + /* For the source endpoint just parse the bus configuration. */
> >> + if (ep.port == MAX9286_SRC_PAD) {
> >> + struct v4l2_fwnode_endpoint vep = {
> >> + .bus_type = V4L2_MBUS_CSI2_DPHY
> >> + };
> >> + int ret;
> >> +
> >> + ret = v4l2_fwnode_endpoint_parse(
> >> + of_fwnode_handle(node), &vep);
> >> + if (ret) {
> >> + of_node_put(node);
> >> + of_node_put(dev->of_node);
> >> + return ret;
> >> + }
> >> +
> >> + if (vep.bus_type != V4L2_MBUS_CSI2_DPHY) {
> >
> > This won't happen, the bus type will stay if you set it to a non-zero
> > value.
>
>
> Ok - I'll remove this check.
>
>
> >
> >> + dev_err(dev,
> >> + "Media bus %u type not supported\n",
> >> + vep.bus_type);
> >> + v4l2_fwnode_endpoint_free(&vep);
> >> + of_node_put(node);
> >> + of_node_put(dev->of_node);
> >> + return -EINVAL;
> >> + }
> >> +
> >> + priv->csi2_data_lanes =
> >> + vep.bus.mipi_csi2.num_data_lanes;
> >> + v4l2_fwnode_endpoint_free(&vep);
> >
> > No need to call this unless you use v4l2_fwnode_endpoint_alloc_parse().
> >
> > And as you don't, you also won't know which frequencies are known to be
> > safe to use. That said, perhaps where this device is used having a random
> > frequency on that bus could not be an issue. Perhaps.
>
> Does this generate a range? or a list of static supported frequencies?
>
> We configure the pixel clock based upon the number of cameras connected,
> and their pixel rates etc ...
>
> Are you saying that the frequency of this clock should be validated to
> be a specific range? or are you talking about a different frequency?
>
>
> For now I'll remove the v4l2_fwnode_endpoint_alloc_parse().
>
>
>
> >> +
> >> + continue;
> >> + }
> >> +
> >> + /* Skip if the corresponding GMSL link is unavailable. */
> >> + if (!(i2c_mux_mask & BIT(ep.port)))
> >> + continue;
> >> +
> >> + if (priv->sources[ep.port].fwnode) {
> >> + dev_err(dev,
> >> + "Multiple port endpoints are not supported: %d",
> >> + ep.port);
> >> +
> >> + continue;
> >> + }
> >> +
> >> + source = &priv->sources[ep.port];
> >> + source->fwnode = fwnode_graph_get_remote_endpoint(
> >> + of_fwnode_handle(node));
> >> + if (!source->fwnode) {
> >> + dev_err(dev,
> >> + "Endpoint %pOF has no remote endpoint connection\n",
> >> + ep.local_node);
> >> +
> >> + continue;
> >> + }
> >> +
> >> + priv->source_mask |= BIT(ep.port);
> >> + priv->nsources++;
> >> + }
> >> + of_node_put(node);
> >> + of_node_put(dev->of_node);
> >> +
> >> + priv->route_mask = priv->source_mask;
> >> +
> >> + return 0;
> >> +}
> >
>
--
Regards,
Laurent Pinchart
^ permalink raw reply
* Re: [PATCH v2 4/4] mtd: rawnand: ingenic: Convert the driver to exec_op()
From: Paul Cercueil @ 2020-05-20 0:37 UTC (permalink / raw)
To: Boris Brezillon
Cc: Harvey Hunt, Miquel Raynal, linux-mtd, Rob Herring, Mark Rutland,
devicetree, Richard Weinberger, Vignesh Raghavendra,
Tudor Ambarus
In-Reply-To: <20200519232454.374081-4-boris.brezillon@collabora.com>
Hi,
Le mer. 20 mai 2020 à 1:24, Boris Brezillon
<boris.brezillon@collabora.com> a écrit :
> Let's convert the driver to exec_op() to have one less driver relying
> on the legacy interface.
>
> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Paul Cercueil <paul@crapouillou.net>
Cheers,
-Paul
> ---
> Changes in v2:
> * Add a delay after instructions when needed
> * s/cmd_offset/addr_offset/
>
> Paul, I didn't add your T-b since this new version follows the path
> you proposed for the R/B polarity inversion issue. Feel free to add
> it back if it still works.
> ---
> .../mtd/nand/raw/ingenic/ingenic_nand_drv.c | 139
> +++++++++++-------
> 1 file changed, 83 insertions(+), 56 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c
> b/drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c
> index e939404e1383..3659e62829f9 100644
> --- a/drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c
> +++ b/drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c
> @@ -27,9 +27,6 @@
>
> #define DRV_NAME "ingenic-nand"
>
> -/* Command delay when there is no R/B pin. */
> -#define RB_DELAY_US 100
> -
> struct jz_soc_info {
> unsigned long data_offset;
> unsigned long addr_offset;
> @@ -49,7 +46,6 @@ struct ingenic_nfc {
> struct nand_controller controller;
> unsigned int num_banks;
> struct list_head chips;
> - int selected;
> struct ingenic_nand_cs cs[];
> };
>
> @@ -142,51 +138,6 @@ static const struct mtd_ooblayout_ops
> jz4725b_ooblayout_ops = {
> .free = jz4725b_ooblayout_free,
> };
>
> -static void ingenic_nand_select_chip(struct nand_chip *chip, int
> chipnr)
> -{
> - struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
> - struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
> - struct ingenic_nand_cs *cs;
> -
> - /* Ensure the currently selected chip is deasserted. */
> - if (chipnr == -1 && nfc->selected >= 0) {
> - cs = &nfc->cs[nfc->selected];
> - jz4780_nemc_assert(nfc->dev, cs->bank, false);
> - }
> -
> - nfc->selected = chipnr;
> -}
> -
> -static void ingenic_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
> - unsigned int ctrl)
> -{
> - struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
> - struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
> - struct ingenic_nand_cs *cs;
> -
> - if (WARN_ON(nfc->selected < 0))
> - return;
> -
> - cs = &nfc->cs[nfc->selected];
> -
> - jz4780_nemc_assert(nfc->dev, cs->bank, ctrl & NAND_NCE);
> -
> - if (cmd == NAND_CMD_NONE)
> - return;
> -
> - if (ctrl & NAND_ALE)
> - writeb(cmd, cs->base + nfc->soc_info->addr_offset);
> - else if (ctrl & NAND_CLE)
> - writeb(cmd, cs->base + nfc->soc_info->cmd_offset);
> -}
> -
> -static int ingenic_nand_dev_ready(struct nand_chip *chip)
> -{
> - struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
> -
> - return gpiod_get_value_cansleep(nand->busy_gpio);
> -}
> -
> static void ingenic_nand_ecc_hwctl(struct nand_chip *chip, int mode)
> {
> struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
> @@ -298,8 +249,91 @@ static int ingenic_nand_attach_chip(struct
> nand_chip *chip)
> return 0;
> }
>
> +static int ingenic_nand_exec_instr(struct nand_chip *chip,
> + struct ingenic_nand_cs *cs,
> + const struct nand_op_instr *instr)
> +{
> + struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
> + struct ingenic_nfc *nfc = to_ingenic_nfc(chip->controller);
> + unsigned int i;
> +
> + switch (instr->type) {
> + case NAND_OP_CMD_INSTR:
> + writeb(instr->ctx.cmd.opcode,
> + cs->base + nfc->soc_info->cmd_offset);
> + return 0;
> + case NAND_OP_ADDR_INSTR:
> + for (i = 0; i < instr->ctx.addr.naddrs; i++)
> + writeb(instr->ctx.addr.addrs[i],
> + cs->base + nfc->soc_info->addr_offset);
> + return 0;
> + case NAND_OP_DATA_IN_INSTR:
> + if (instr->ctx.data.force_8bit ||
> + !(chip->options & NAND_BUSWIDTH_16))
> + ioread8_rep(cs->base + nfc->soc_info->data_offset,
> + instr->ctx.data.buf.in,
> + instr->ctx.data.len);
> + else
> + ioread16_rep(cs->base + nfc->soc_info->data_offset,
> + instr->ctx.data.buf.in,
> + instr->ctx.data.len);
> + return 0;
> + case NAND_OP_DATA_OUT_INSTR:
> + if (instr->ctx.data.force_8bit ||
> + !(chip->options & NAND_BUSWIDTH_16))
> + iowrite8_rep(cs->base + nfc->soc_info->data_offset,
> + instr->ctx.data.buf.out,
> + instr->ctx.data.len);
> + else
> + iowrite16_rep(cs->base + nfc->soc_info->data_offset,
> + instr->ctx.data.buf.out,
> + instr->ctx.data.len);
> + return 0;
> + case NAND_OP_WAITRDY_INSTR:
> + if (!nand->busy_gpio)
> + return nand_soft_waitrdy(chip,
> + instr->ctx.waitrdy.timeout_ms);
> +
> + return nand_gpio_waitrdy(chip, nand->busy_gpio,
> + instr->ctx.waitrdy.timeout_ms);
> + default:
> + break;
> + }
> +
> + return -EINVAL;
> +}
> +
> +static int ingenic_nand_exec_op(struct nand_chip *chip,
> + const struct nand_operation *op,
> + bool check_only)
> +{
> + struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
> + struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
> + struct ingenic_nand_cs *cs;
> + unsigned int i;
> + int ret = 0;
> +
> + if (check_only)
> + return 0;
> +
> + cs = &nfc->cs[op->cs];
> + jz4780_nemc_assert(nfc->dev, cs->bank, true);
> + for (i = 0; i < op->ninstrs; i++) {
> + ret = ingenic_nand_exec_instr(chip, cs, &op->instrs[i]);
> + if (ret)
> + break;
> +
> + if (op->instrs[i].delay_ns)
> + ndelay(op->instrs[i].delay_ns);
> + }
> + jz4780_nemc_assert(nfc->dev, cs->bank, false);
> +
> + return ret;
> +}
> +
> static const struct nand_controller_ops ingenic_nand_controller_ops
> = {
> .attach_chip = ingenic_nand_attach_chip,
> + .exec_op = ingenic_nand_exec_op,
> };
>
> static int ingenic_nand_init_chip(struct platform_device *pdev,
> @@ -339,8 +373,6 @@ static int ingenic_nand_init_chip(struct
> platform_device *pdev,
> ret = PTR_ERR(nand->busy_gpio);
> dev_err(dev, "failed to request busy GPIO: %d\n", ret);
> return ret;
> - } else if (nand->busy_gpio) {
> - nand->chip.legacy.dev_ready = ingenic_nand_dev_ready;
> }
>
> /*
> @@ -371,12 +403,7 @@ static int ingenic_nand_init_chip(struct
> platform_device *pdev,
> return -ENOMEM;
> mtd->dev.parent = dev;
>
> - chip->legacy.IO_ADDR_R = cs->base + nfc->soc_info->data_offset;
> - chip->legacy.IO_ADDR_W = cs->base + nfc->soc_info->data_offset;
> - chip->legacy.chip_delay = RB_DELAY_US;
> chip->options = NAND_NO_SUBPAGE_WRITE;
> - chip->legacy.select_chip = ingenic_nand_select_chip;
> - chip->legacy.cmd_ctrl = ingenic_nand_cmd_ctrl;
> chip->ecc.mode = NAND_ECC_HW;
> chip->controller = &nfc->controller;
> nand_set_flash_node(chip, np);
> --
> 2.25.4
>
^ permalink raw reply
* [PATCH] dt-bindings: gpio: Convert mxs to json-schema
From: Anson Huang @ 2020-05-20 0:20 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, robh+dt, shawnguo, s.hauer, kernel,
festevam, linux-gpio, devicetree, linux-arm-kernel, linux-kernel
Cc: Linux-imx
Convert the MXS GPIO binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
.../devicetree/bindings/gpio/gpio-mxs.txt | 88 -------------
.../devicetree/bindings/gpio/gpio-mxs.yaml | 136 +++++++++++++++++++++
2 files changed, 136 insertions(+), 88 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/gpio/gpio-mxs.txt
create mode 100644 Documentation/devicetree/bindings/gpio/gpio-mxs.yaml
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mxs.txt b/Documentation/devicetree/bindings/gpio/gpio-mxs.txt
deleted file mode 100644
index 1e677a4..0000000
--- a/Documentation/devicetree/bindings/gpio/gpio-mxs.txt
+++ /dev/null
@@ -1,88 +0,0 @@
-* Freescale MXS GPIO controller
-
-The Freescale MXS GPIO controller is part of MXS PIN controller. The
-GPIOs are organized in port/bank. Each port consists of 32 GPIOs.
-
-As the GPIO controller is embedded in the PIN controller and all the
-GPIO ports share the same IO space with PIN controller, the GPIO node
-will be represented as sub-nodes of MXS pinctrl node.
-
-Required properties for GPIO node:
-- compatible : Should be "fsl,<soc>-gpio". The supported SoCs include
- imx23 and imx28.
-- interrupts : Should be the port interrupt shared by all 32 pins.
-- gpio-controller : Marks the device node as a gpio controller.
-- #gpio-cells : Should be two. The first cell is the pin number and
- the second cell is used to specify the gpio polarity:
- 0 = active high
- 1 = active low
-- interrupt-controller: Marks the device node as an interrupt controller.
-- #interrupt-cells : Should be 2. The first cell is the GPIO number.
- The second cell bits[3:0] is used to specify trigger type and level flags:
- 1 = low-to-high edge triggered.
- 2 = high-to-low edge triggered.
- 4 = active high level-sensitive.
- 8 = active low level-sensitive.
-
-Note: Each GPIO port should have an alias correctly numbered in "aliases"
-node.
-
-Examples:
-
-aliases {
- gpio0 = &gpio0;
- gpio1 = &gpio1;
- gpio2 = &gpio2;
- gpio3 = &gpio3;
- gpio4 = &gpio4;
-};
-
-pinctrl@80018000 {
- compatible = "fsl,imx28-pinctrl", "simple-bus";
- reg = <0x80018000 2000>;
-
- gpio0: gpio@0 {
- compatible = "fsl,imx28-gpio";
- interrupts = <127>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio1: gpio@1 {
- compatible = "fsl,imx28-gpio";
- interrupts = <126>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio2: gpio@2 {
- compatible = "fsl,imx28-gpio";
- interrupts = <125>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio3: gpio@3 {
- compatible = "fsl,imx28-gpio";
- interrupts = <124>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- gpio4: gpio@4 {
- compatible = "fsl,imx28-gpio";
- interrupts = <123>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml b/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml
new file mode 100644
index 0000000..ccf5b50
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml
@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/gpio-mxs.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale MXS GPIO controller
+
+maintainers:
+ - Shawn Guo <shawn.guo@linaro.org>
+ - Anson Huang <Anson.Huang@nxp.com>
+
+description: |
+ The Freescale MXS GPIO controller is part of MXS PIN controller.
+ The GPIOs are organized in port/bank, each port consists of 32 GPIOs.
+ As the GPIO controller is embedded in the PIN controller and all the
+ GPIO ports share the same IO space with PIN controller, the GPIO node
+ will be represented as sub-nodes of MXS pinctrl node.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx23-pinctrl
+ - fsl,imx28-pinctrl
+
+ '#address-cells':
+ const: 1
+ '#size-cells':
+ const: 0
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ "gpio@[0-9]+$":
+ type: object
+ properties:
+ compatible:
+ enum:
+ - fsl,imx23-gpio
+ - fsl,imx28-gpio
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: Should be the port interrupt shared by all 32 pins.
+ maxItems: 1
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-controller: true
+
+ required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-controller
+ - "#interrupt-cells"
+ - "#gpio-cells"
+ - gpio-controller
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ pinctrl@80018000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx28-pinctrl";
+ reg = <0x80018000 0x2000>;
+
+ gpio@0 {
+ compatible = "fsl,imx28-gpio";
+ reg = <0>;
+ interrupts = <127>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio@1 {
+ compatible = "fsl,imx28-gpio";
+ reg = <1>;
+ interrupts = <126>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio@2 {
+ compatible = "fsl,imx28-gpio";
+ reg = <2>;
+ interrupts = <125>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio@3 {
+ compatible = "fsl,imx28-gpio";
+ reg = <3>;
+ interrupts = <124>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio@4 {
+ compatible = "fsl,imx28-gpio";
+ reg = <4>;
+ interrupts = <123>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v2 1/4] dt-bindings: mtd: rawnand: ingenic: Clarify the active state of the RB pin
From: Paul Cercueil @ 2020-05-20 0:25 UTC (permalink / raw)
To: Boris Brezillon
Cc: Harvey Hunt, Miquel Raynal, linux-mtd, Rob Herring, Mark Rutland,
devicetree, Richard Weinberger, Vignesh Raghavendra,
Tudor Ambarus
In-Reply-To: <20200519232454.374081-1-boris.brezillon@collabora.com>
Hi Boris,
This .txt file is going away, so there's no need to apply this one
patch.
I Cc'd you on the V2 of the patchset that drops this file.
-Paul
Le mer. 20 mai 2020 à 1:24, Boris Brezillon
<boris.brezillon@collabora.com> a écrit :
> Let's make things consistent with other bindings and clarify the
> expected active state.
>
> Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
> ---
> Changes in v2:
> * New patch
> ---
> Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git
> a/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
> b/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
> index c02259353327..4cbe13f94564 100644
> --- a/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
> +++ b/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
> @@ -30,7 +30,8 @@ Optional children node properties:
> - nand-ecc-strength: ECC strength (max number of correctable bits).
> - nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw"
> by default
> - nand-on-flash-bbt: boolean to enable on flash bbt option, if not
> present false
> -- rb-gpios: GPIO specifier for the busy pin.
> +- rb-gpios: GPIO specifier for the ready/busy pin. The active state
> (ready)
> + should be high unless the signal is inverted.
> - wp-gpios: GPIO specifier for the write protect pin.
>
> Optional child node of NAND chip nodes:
> --
> 2.25.4
>
^ permalink raw reply
* [PATCH v2 3/3] dt-bindings: mtd: Convert ingenic,jz4780-nand.txt to YAML
From: Paul Cercueil @ 2020-05-20 0:22 UTC (permalink / raw)
To: Rob Herring
Cc: Boris Brezillon, od, devicetree, linux-kernel, linux-mtd,
linux-gpio, Paul Cercueil
In-Reply-To: <20200520002234.418025-1-paul@crapouillou.net>
Convert the ingenic,jz4780-nand.txt doc file to ingenic,nand.yaml.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
Notes:
v2: - Don't include ingenic,nemc-client.yaml which is gone
- Use 'partitions' property instead of '^partitions$' pattern
.../bindings/mtd/ingenic,jz4780-nand.txt | 92 ------------
.../devicetree/bindings/mtd/ingenic,nand.yaml | 132 ++++++++++++++++++
2 files changed, 132 insertions(+), 92 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
create mode 100644 Documentation/devicetree/bindings/mtd/ingenic,nand.yaml
diff --git a/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt b/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
deleted file mode 100644
index c02259353327..000000000000
--- a/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
+++ /dev/null
@@ -1,92 +0,0 @@
-* Ingenic JZ4780 NAND/ECC
-
-This file documents the device tree bindings for NAND flash devices on the
-JZ4780. NAND devices are connected to the NEMC controller (described in
-memory-controllers/ingenic,jz4780-nemc.txt), and thus NAND device nodes must
-be children of the NEMC node.
-
-Required NAND controller device properties:
-- compatible: Should be one of:
- * ingenic,jz4740-nand
- * ingenic,jz4725b-nand
- * ingenic,jz4780-nand
-- reg: For each bank with a NAND chip attached, should specify a bank number,
- an offset of 0 and a size of 0x1000000 (i.e. the whole NEMC bank).
-
-Optional NAND controller device properties:
-- ecc-engine: To make use of the hardware ECC controller, this
- property must contain a phandle for the ECC controller node. The required
- properties for this node are described below. If this is not specified,
- software ECC will be used instead.
-
-Optional children nodes:
-- Individual NAND chips are children of the NAND controller node.
-
-Required children node properties:
-- reg: An integer ranging from 1 to 6 representing the CS line to use.
-
-Optional children node properties:
-- nand-ecc-step-size: ECC block size in bytes.
-- nand-ecc-strength: ECC strength (max number of correctable bits).
-- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by default
-- nand-on-flash-bbt: boolean to enable on flash bbt option, if not present false
-- rb-gpios: GPIO specifier for the busy pin.
-- wp-gpios: GPIO specifier for the write protect pin.
-
-Optional child node of NAND chip nodes:
-- partitions: see Documentation/devicetree/bindings/mtd/partition.txt
-
-Example:
-
-nemc: nemc@13410000 {
- ...
-
- nandc: nand-controller@1 {
- compatible = "ingenic,jz4780-nand";
- reg = <1 0 0x1000000>; /* Bank 1 */
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- ecc-engine = <&bch>;
-
- nand@1 {
- reg = <1>;
-
- nand-ecc-step-size = <1024>;
- nand-ecc-strength = <24>;
- nand-ecc-mode = "hw";
- nand-on-flash-bbt;
-
- rb-gpios = <&gpa 20 GPIO_ACTIVE_LOW>;
- wp-gpios = <&gpf 22 GPIO_ACTIVE_LOW>;
-
- partitions {
- #address-cells = <2>;
- #size-cells = <2>;
- ...
- }
- };
- };
-};
-
-The ECC controller is a separate SoC component used for error correction on
-NAND devices. The following is a description of the device properties for a
-ECC controller.
-
-Required ECC properties:
-- compatible: Should be one of:
- * ingenic,jz4740-ecc
- * ingenic,jz4725b-bch
- * ingenic,jz4780-bch
-- reg: Should specify the ECC controller registers location and length.
-- clocks: Clock for the ECC controller.
-
-Example:
-
-bch: bch@134d0000 {
- compatible = "ingenic,jz4780-bch";
- reg = <0x134d0000 0x10000>;
-
- clocks = <&cgu JZ4780_CLK_BCH>;
-};
diff --git a/Documentation/devicetree/bindings/mtd/ingenic,nand.yaml b/Documentation/devicetree/bindings/mtd/ingenic,nand.yaml
new file mode 100644
index 000000000000..8abb6d463cb6
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/ingenic,nand.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/ingenic,nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ingenic SoCs NAND controller devicetree bindings
+
+maintainers:
+ - Paul Cercueil <paul@crapouillou.net>
+
+allOf:
+ - $ref: nand-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ingenic,jz4740-nand
+ - ingenic,jz4725b-nand
+ - ingenic,jz4780-nand
+
+ reg:
+ items:
+ - description: Bank number, offset and size of first attached NAND chip
+ - description: Bank number, offset and size of second attached NAND chip
+ - description: Bank number, offset and size of third attached NAND chip
+ - description: Bank number, offset and size of fourth attached NAND chip
+ minItems: 1
+
+ ecc-engine: true
+
+ partitions:
+ type: object
+ description:
+ Node containing description of fixed partitions.
+ See Documentation/devicetree/bindings/mtd/partition.txt
+
+patternProperties:
+ "^nand@[a-f0-9]$":
+ type: object
+ properties:
+ rb-gpios:
+ description: GPIO specifier for the busy pin.
+ maxItems: 1
+
+ wp-gpios:
+ description: GPIO specifier for the write-protect pin.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ #include <dt-bindings/clock/jz4780-cgu.h>
+ memory-controller@13410000 {
+ compatible = "ingenic,jz4780-nemc";
+ reg = <0x13410000 0x10000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0x1b000000 0x1000000>,
+ <2 0 0x1a000000 0x1000000>,
+ <3 0 0x19000000 0x1000000>,
+ <4 0 0x18000000 0x1000000>,
+ <5 0 0x17000000 0x1000000>,
+ <6 0 0x16000000 0x1000000>;
+
+ clocks = <&cgu JZ4780_CLK_NEMC>;
+
+ nand-controller@1 {
+ compatible = "ingenic,jz4780-nand";
+ reg = <1 0 0x1000000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ecc-engine = <&bch>;
+
+ ingenic,nemc-tAS = <10>;
+ ingenic,nemc-tAH = <5>;
+ ingenic,nemc-tBP = <10>;
+ ingenic,nemc-tAW = <15>;
+ ingenic,nemc-tSTRV = <100>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_nemc>;
+
+ nand@1 {
+ reg = <1>;
+
+ nand-ecc-step-size = <1024>;
+ nand-ecc-strength = <24>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_nemc_cs1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ partition@0 {
+ label = "u-boot-spl";
+ reg = <0x0 0x0 0x0 0x800000>;
+ };
+
+ partition@800000 {
+ label = "u-boot";
+ reg = <0x0 0x800000 0x0 0x200000>;
+ };
+
+ partition@a00000 {
+ label = "u-boot-env";
+ reg = <0x0 0xa00000 0x0 0x200000>;
+ };
+
+ partition@c00000 {
+ label = "boot";
+ reg = <0x0 0xc00000 0x0 0x4000000>;
+ };
+
+ partition@4c00000 {
+ label = "system";
+ reg = <0x0 0x4c00000 0x1 0xfb400000>;
+ };
+ };
+ };
+ };
+ };
--
2.26.2
^ permalink raw reply related
* [PATCH v2 2/3] dt-bindings: memory: Convert ingenic,jz4780-nemc.txt to YAML
From: Paul Cercueil @ 2020-05-20 0:22 UTC (permalink / raw)
To: Rob Herring
Cc: Boris Brezillon, od, devicetree, linux-kernel, linux-mtd,
linux-gpio, Paul Cercueil
In-Reply-To: <20200520002234.418025-1-paul@crapouillou.net>
Convert the ingenic,jz4780-nemc.txt doc file to ingenic,nemc.yaml.
The ingenic,jz4725b-nemc compatible string was added in the process,
with a fallback to ingenic,jz4740-nemc.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
Notes:
v2: - Inline content of ingenic,nemc-client.yaml inside ingenic,nemc.yaml
- Add missing 'reg' property to sub-nodes and mark it as required
- Use a more generic wildcard to match all sub-nodes.
.../ingenic,jz4780-nemc.txt | 76 -----------
.../memory-controllers/ingenic,nemc.yaml | 126 ++++++++++++++++++
2 files changed, 126 insertions(+), 76 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/memory-controllers/ingenic,jz4780-nemc.txt
create mode 100644 Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml
diff --git a/Documentation/devicetree/bindings/memory-controllers/ingenic,jz4780-nemc.txt b/Documentation/devicetree/bindings/memory-controllers/ingenic,jz4780-nemc.txt
deleted file mode 100644
index 59b8dcc118ee..000000000000
--- a/Documentation/devicetree/bindings/memory-controllers/ingenic,jz4780-nemc.txt
+++ /dev/null
@@ -1,76 +0,0 @@
-* Ingenic JZ4780 NAND/external memory controller (NEMC)
-
-This file documents the device tree bindings for the NEMC external memory
-controller in Ingenic JZ4780
-
-Required properties:
-- compatible: Should be set to one of:
- "ingenic,jz4740-nemc" (JZ4740)
- "ingenic,jz4780-nemc" (JZ4780)
-- reg: Should specify the NEMC controller registers location and length.
-- clocks: Clock for the NEMC controller.
-- #address-cells: Must be set to 2.
-- #size-cells: Must be set to 1.
-- ranges: A set of ranges for each bank describing the physical memory layout.
- Each should specify the following 4 integer values:
-
- <cs number> 0 <physical address of mapping> <size of mapping>
-
-Each child of the NEMC node describes a device connected to the NEMC.
-
-Required child node properties:
-- reg: Should contain at least one register specifier, given in the following
- format:
-
- <cs number> <offset> <size>
-
- Multiple registers can be specified across multiple banks. This is needed,
- for example, for packaged NAND devices with multiple dies. Such devices
- should be grouped into a single node.
-
-Optional child node properties:
-- ingenic,nemc-bus-width: Specifies the bus width in bits. Defaults to 8 bits.
-- ingenic,nemc-tAS: Address setup time in nanoseconds.
-- ingenic,nemc-tAH: Address hold time in nanoseconds.
-- ingenic,nemc-tBP: Burst pitch time in nanoseconds.
-- ingenic,nemc-tAW: Access wait time in nanoseconds.
-- ingenic,nemc-tSTRV: Static memory recovery time in nanoseconds.
-
-If a child node references multiple banks in its "reg" property, the same value
-for all optional parameters will be configured for all banks. If any optional
-parameters are omitted, they will be left unchanged from whatever they are
-configured to when the NEMC device is probed (which may be the reset value as
-given in the hardware reference manual, or a value configured by the boot
-loader).
-
-Example (NEMC node with a NAND child device attached at CS1):
-
-nemc: nemc@13410000 {
- compatible = "ingenic,jz4780-nemc";
- reg = <0x13410000 0x10000>;
-
- #address-cells = <2>;
- #size-cells = <1>;
-
- ranges = <1 0 0x1b000000 0x1000000
- 2 0 0x1a000000 0x1000000
- 3 0 0x19000000 0x1000000
- 4 0 0x18000000 0x1000000
- 5 0 0x17000000 0x1000000
- 6 0 0x16000000 0x1000000>;
-
- clocks = <&cgu JZ4780_CLK_NEMC>;
-
- nand: nand@1 {
- compatible = "ingenic,jz4780-nand";
- reg = <1 0 0x1000000>;
-
- ingenic,nemc-tAS = <10>;
- ingenic,nemc-tAH = <5>;
- ingenic,nemc-tBP = <10>;
- ingenic,nemc-tAW = <15>;
- ingenic,nemc-tSTRV = <100>;
-
- ...
- };
-};
diff --git a/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml b/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml
new file mode 100644
index 000000000000..9b478da0c479
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/ingenic,nemc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ingenic SoCs NAND / External Memory Controller (NEMC) devicetree bindings
+
+maintainers:
+ - Paul Cercueil <paul@crapouillou.net>
+
+properties:
+ $nodename:
+ pattern: "^memory-controller@[0-9a-f]+$"
+
+ compatible:
+ oneOf:
+ - enum:
+ - ingenic,jz4740-nemc
+ - ingenic,jz4780-nemc
+ - items:
+ - const: ingenic,jz4725b-nemc
+ - const: ingenic,jz4740-nemc
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 1
+
+ ranges: true
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+patternProperties:
+ ".*@[0-9]+$":
+ type: object
+ properties:
+ reg:
+ minItems: 1
+ maxItems: 255
+
+ ingenic,nemc-bus-width:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [8, 16]
+ description: Specifies the bus width in bits.
+
+ ingenic,nemc-tAS:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Address setup time in nanoseconds.
+
+ ingenic,nemc-tAH:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Address hold time in nanoseconds.
+
+ ingenic,nemc-tBP:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Burst pitch time in nanoseconds.
+
+ ingenic,nemc-tAW:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Address wait time in nanoseconds.
+
+ ingenic,nemc-tSTRV:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Static memory recovery time in nanoseconds.
+
+ required:
+ - reg
+
+required:
+ - compatible
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/jz4780-cgu.h>
+ #include <dt-bindings/gpio/gpio.h>
+ nemc: memory-controller@13410000 {
+ compatible = "ingenic,jz4780-nemc";
+ reg = <0x13410000 0x10000>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <1 0 0x1b000000 0x1000000>,
+ <2 0 0x1a000000 0x1000000>,
+ <3 0 0x19000000 0x1000000>,
+ <4 0 0x18000000 0x1000000>,
+ <5 0 0x17000000 0x1000000>,
+ <6 0 0x16000000 0x1000000>;
+
+ clocks = <&cgu JZ4780_CLK_NEMC>;
+
+ ethernet@6 {
+ compatible = "davicom,dm9000";
+ davicom,no-eeprom;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_nemc_cs6>;
+
+ reg = <6 0 1>, /* addr */
+ <6 2 1>; /* data */
+
+ ingenic,nemc-tAS = <15>;
+ ingenic,nemc-tAH = <10>;
+ ingenic,nemc-tBP = <20>;
+ ingenic,nemc-tAW = <50>;
+ ingenic,nemc-tSTRV = <100>;
+
+ reset-gpios = <&gpf 12 GPIO_ACTIVE_HIGH>;
+ vcc-supply = <ð0_power>;
+
+ interrupt-parent = <&gpe>;
+ interrupts = <19 4>;
+ };
+ };
--
2.26.2
^ permalink raw reply related
* [PATCH v2 1/3] dt-bindings: pinctrl: Convert ingenic,pinctrl.txt to YAML
From: Paul Cercueil @ 2020-05-20 0:22 UTC (permalink / raw)
To: Rob Herring
Cc: Boris Brezillon, od, devicetree, linux-kernel, linux-mtd,
linux-gpio, Paul Cercueil
Convert the ingenic,pinctrl.txt doc file to ingenic,pinctrl.yaml.
In the process, some compatible strings now require a fallback, as the
corresponding SoCs are pin-compatible with their fallback variant.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
Notes:
v2: - Use 'pinctrl' instead of 'pin-controller' as the node name
- remove 'additionalProperties: false' since we will have pin conf nodes
.../bindings/pinctrl/ingenic,pinctrl.txt | 81 -----------
.../bindings/pinctrl/ingenic,pinctrl.yaml | 136 ++++++++++++++++++
2 files changed, 136 insertions(+), 81 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
deleted file mode 100644
index d9b2100c98e8..000000000000
--- a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.txt
+++ /dev/null
@@ -1,81 +0,0 @@
-Ingenic XBurst pin controller
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-For the XBurst SoCs, pin control is tightly bound with GPIO ports. All pins may
-be used as GPIOs, multiplexed device functions are configured within the
-GPIO port configuration registers and it is typical to refer to pins using the
-naming scheme "PxN" where x is a character identifying the GPIO port with
-which the pin is associated and N is an integer from 0 to 31 identifying the
-pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
-PB31 is the last pin in GPIO port B. The jz4740, the x1000 and the x1830
-contains 4 GPIO ports, PA to PD, for a total of 128 pins. The jz4760, the
-jz4770 and the jz4780 contains 6 GPIO ports, PA to PF, for a total of 192 pins.
-
-
-Required properties:
---------------------
-
- - compatible: One of:
- - "ingenic,jz4740-pinctrl"
- - "ingenic,jz4725b-pinctrl"
- - "ingenic,jz4760-pinctrl"
- - "ingenic,jz4760b-pinctrl"
- - "ingenic,jz4770-pinctrl"
- - "ingenic,jz4780-pinctrl"
- - "ingenic,x1000-pinctrl"
- - "ingenic,x1000e-pinctrl"
- - "ingenic,x1500-pinctrl"
- - "ingenic,x1830-pinctrl"
- - reg: Address range of the pinctrl registers.
-
-
-Required properties for sub-nodes (GPIO chips):
------------------------------------------------
-
- - compatible: Must contain one of:
- - "ingenic,jz4740-gpio"
- - "ingenic,jz4760-gpio"
- - "ingenic,jz4770-gpio"
- - "ingenic,jz4780-gpio"
- - "ingenic,x1000-gpio"
- - "ingenic,x1830-gpio"
- - reg: The GPIO bank number.
- - interrupt-controller: Marks the device node as an interrupt controller.
- - interrupts: Interrupt specifier for the controllers interrupt.
- - #interrupt-cells: Should be 2. Refer to
- ../interrupt-controller/interrupts.txt for more details.
- - gpio-controller: Marks the device node as a GPIO controller.
- - #gpio-cells: Should be 2. The first cell is the GPIO number and the second
- cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. Only the
- GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported.
- - gpio-ranges: Range of pins managed by the GPIO controller. Refer to
- ../gpio/gpio.txt for more details.
-
-
-Example:
---------
-
-pinctrl: pin-controller@10010000 {
- compatible = "ingenic,jz4740-pinctrl";
- reg = <0x10010000 0x400>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- gpa: gpio@0 {
- compatible = "ingenic,jz4740-gpio";
- reg = <0>;
-
- gpio-controller;
- gpio-ranges = <&pinctrl 0 0 32>;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
-
- interrupt-parent = <&intc>;
- interrupts = <28>;
- };
-};
diff --git a/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
new file mode 100644
index 000000000000..5be2b1e95b36
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/ingenic,pinctrl.yaml
@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/ingenic,pinctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ingenic SoCs pin controller devicetree bindings
+
+description: >
+ Please refer to pinctrl-bindings.txt in this directory for details of the
+ common pinctrl bindings used by client devices, including the meaning of the
+ phrase "pin configuration node".
+
+ For the Ingenic SoCs, pin control is tightly bound with GPIO ports. All pins
+ may be used as GPIOs, multiplexed device functions are configured within the
+ GPIO port configuration registers and it is typical to refer to pins using the
+ naming scheme "PxN" where x is a character identifying the GPIO port with
+ which the pin is associated and N is an integer from 0 to 31 identifying the
+ pin within that GPIO port. For example PA0 is the first pin in GPIO port A,
+ and PB31 is the last pin in GPIO port B. The JZ4740, the X1000 and the X1830
+ contains 4 GPIO ports, PA to PD, for a total of 128 pins. The JZ4760, the
+ JZ4770 and the JZ4780 contains 6 GPIO ports, PA to PF, for a total of 192
+ pins.
+
+maintainers:
+ - Paul Cercueil <paul@crapouillou.net>
+
+properties:
+ nodename:
+ pattern: "^pinctrl@[0-9a-f]+$"
+
+ compatible:
+ oneOf:
+ - enum:
+ - ingenic,jz4740-pinctrl
+ - ingenic,jz4725b-pinctrl
+ - ingenic,jz4760-pinctrl
+ - ingenic,jz4770-pinctrl
+ - ingenic,jz4780-pinctrl
+ - ingenic,x1000-pinctrl
+ - ingenic,x1500-pinctrl
+ - ingenic,x1830-pinctrl
+ - items:
+ - const: ingenic,jz4760b-pinctrl
+ - const: ingenic,jz4760-pinctrl
+ - items:
+ - const: ingenic,x1000e-pinctrl
+ - const: ingenic,x1000-pinctrl
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+patternProperties:
+ "^gpio@[0-9]$":
+ type: object
+ properties:
+ compatible:
+ enum:
+ - ingenic,jz4740-gpio
+ - ingenic,jz4725b-gpio
+ - ingenic,jz4760-gpio
+ - ingenic,jz4770-gpio
+ - ingenic,jz4780-gpio
+ - ingenic,x1000-gpio
+ - ingenic,x1500-gpio
+ - ingenic,x1830-gpio
+
+ reg:
+ items:
+ - description: The GPIO bank number
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+ description:
+ Refer to ../interrupt-controller/interrupts.txt for more details.
+
+ interrupts:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+ - gpio-controller
+ - "#gpio-cells"
+ - interrupts
+ - interrupt-controller
+ - "#interrupt-cells"
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+
+examples:
+ - |
+ pin-controller@10010000 {
+ compatible = "ingenic,jz4770-pinctrl";
+ reg = <0x10010000 0x600>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@0 {
+ compatible = "ingenic,jz4770-gpio";
+ reg = <0>;
+
+ gpio-controller;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <17>;
+ };
+ };
--
2.26.2
^ permalink raw reply related
* [RESENDPATCH v8 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC
From: Ramuthevar,Vadivel MuruganX @ 2020-05-20 0:06 UTC (permalink / raw)
To: linux-kernel, linux-mtd, devicetree
Cc: miquel.raynal, richard, vigneshr, arnd, brendanhiggins, tglx,
boris.brezillon, anders.roxell, masonccyang, robh+dt, linux-mips,
hauke.mehrtens, andriy.shevchenko, qi-ming.wu, cheol.yong.kim,
Ramuthevar Vadivel Murugan
In-Reply-To: <20200520000621.49152-1-vadivel.muruganx.ramuthevar@linux.intel.com>
From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8 supported. Data register used to support the read/write
operation from/to device.
NAND controller driver implements ->exec_op() to replace legacy hooks,
these specific call-back method to execute NAND operations.
Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
---
drivers/mtd/nand/raw/Kconfig | 8 +
drivers/mtd/nand/raw/Makefile | 1 +
drivers/mtd/nand/raw/intel-nand-controller.c | 747 +++++++++++++++++++++++++++
3 files changed, 756 insertions(+)
create mode 100644 drivers/mtd/nand/raw/intel-nand-controller.c
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index a80a46bb5b8b..75ab2afb78cf 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -457,6 +457,14 @@ config MTD_NAND_CADENCE
Enable the driver for NAND flash on platforms using a Cadence NAND
controller.
+config MTD_NAND_INTEL_LGM
+ tristate "Support for NAND controller on Intel LGM SoC"
+ depends on OF || COMPILE_TEST
+ depends on HAS_IOMEM
+ help
+ Enables support for NAND Flash chips on Intel's LGM SoC.
+ NAND flash controller interfaced through the External Bus Unit.
+
comment "Misc"
config MTD_SM_COMMON
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index 2d136b158fb7..bfc8fe4d2cb0 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -58,6 +58,7 @@ obj-$(CONFIG_MTD_NAND_TEGRA) += tegra_nand.o
obj-$(CONFIG_MTD_NAND_STM32_FMC2) += stm32_fmc2_nand.o
obj-$(CONFIG_MTD_NAND_MESON) += meson_nand.o
obj-$(CONFIG_MTD_NAND_CADENCE) += cadence-nand-controller.o
+obj-$(CONFIG_MTD_NAND_INTEL_LGM) += intel-nand-controller.o
nand-objs := nand_base.o nand_legacy.o nand_bbt.o nand_timings.o nand_ids.o
nand-objs += nand_onfi.o
diff --git a/drivers/mtd/nand/raw/intel-nand-controller.c b/drivers/mtd/nand/raw/intel-nand-controller.c
new file mode 100644
index 000000000000..564d28978943
--- /dev/null
+++ b/drivers/mtd/nand/raw/intel-nand-controller.c
@@ -0,0 +1,747 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (c) 2020 Intel Corporation. */
+
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-direction.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/nand.h>
+#include <linux/resource.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+
+#define EBU_CLC 0x000
+#define EBU_CLC_RST 0x00000000u
+
+#define EBU_ADDR_SEL(n) (0x20 + (n) * 4)
+/* 5 bits 26:22 included for comparison in the ADDR_SELx */
+#define EBU_ADDR_MASK(x) ((x) << 4)
+#define EBU_ADDR_SEL_REGEN 0x1
+
+#define EBU_BUSCON(n) (0x60 + (n) * 4)
+#define EBU_BUSCON_CMULT_V4 0x1
+#define EBU_BUSCON_RECOVC(n) ((n) << 2)
+#define EBU_BUSCON_HOLDC(n) ((n) << 4)
+#define EBU_BUSCON_WAITRDC(n) ((n) << 6)
+#define EBU_BUSCON_WAITWRC(n) ((n) << 8)
+#define EBU_BUSCON_BCGEN_CS 0x0
+#define EBU_BUSCON_SETUP_EN BIT(22)
+#define EBU_BUSCON_ALEC 0xC000
+
+#define EBU_CON 0x0B0
+#define EBU_CON_NANDM_EN BIT(0)
+#define EBU_CON_NANDM_DIS 0x0
+#define EBU_CON_CSMUX_E_EN BIT(1)
+#define EBU_CON_ALE_P_LOW BIT(2)
+#define EBU_CON_CLE_P_LOW BIT(3)
+#define EBU_CON_CS_P_LOW BIT(4)
+#define EBU_CON_SE_P_LOW BIT(5)
+#define EBU_CON_WP_P_LOW BIT(6)
+#define EBU_CON_PRE_P_LOW BIT(7)
+#define EBU_CON_IN_CS_S(n) ((n) << 8)
+#define EBU_CON_OUT_CS_S(n) ((n) << 10)
+#define EBU_CON_LAT_EN_CS_P ((0x3D) << 18)
+
+#define EBU_WAIT 0x0B4
+#define EBU_WAIT_RDBY BIT(0)
+#define EBU_WAIT_WR_C BIT(3)
+
+#define HSNAND_CTL1 0x110
+#define HSNAND_CTL1_ADDR_SHIFT 24
+
+#define HSNAND_CTL2 0x114
+#define HSNAND_CTL2_ADDR_SHIFT 8
+#define HSNAND_CTL2_CYC_N_V5 (0x2 << 16)
+
+#define HSNAND_INT_MSK_CTL 0x124
+#define HSNAND_INT_MSK_CTL_WR_C BIT(4)
+
+#define HSNAND_INT_STA 0x128
+#define HSNAND_INT_STA_WR_C BIT(4)
+
+#define HSNAND_CTL 0x130
+#define HSNAND_CTL_ENABLE_ECC BIT(0)
+#define HSNAND_CTL_GO BIT(2)
+#define HSNAND_CTL_CE_SEL_CS(n) BIT(3 + (n))
+#define HSNAND_CTL_RW_READ 0x0
+#define HSNAND_CTL_RW_WRITE BIT(10)
+#define HSNAND_CTL_ECC_OFF_V8TH BIT(11)
+#define HSNAND_CTL_CKFF_EN 0x0
+#define HSNAND_CTL_MSG_EN BIT(17)
+
+#define HSNAND_PARA0 0x13c
+#define HSNAND_PARA0_PAGE_V8192 0x3
+#define HSNAND_PARA0_PIB_V256 (0x3 << 4)
+#define HSNAND_PARA0_BYP_EN_NP 0x0
+#define HSNAND_PARA0_BYP_DEC_NP 0x0
+#define HSNAND_PARA0_TYPE_ONFI BIT(18)
+#define HSNAND_PARA0_ADEP_EN BIT(21)
+
+#define HSNAND_CMSG_0 0x150
+#define HSNAND_CMSG_1 0x154
+
+#define HSNAND_ALE_OFFS BIT(2)
+#define HSNAND_CLE_OFFS BIT(3)
+#define HSNAND_CS_OFFS BIT(4)
+
+#define HSNAND_ECC_OFFSET 0x008
+
+#define NAND_DATA_IFACE_CHECK_ONLY -1
+
+#define MAX_CS 2
+
+struct ebu_nand_cs {
+ void __iomem *chipaddr;
+ dma_addr_t nand_pa;
+ u32 addr_sel;
+};
+
+struct ebu_nand_controller {
+ struct nand_controller controller;
+ struct nand_chip chip;
+ struct device *dev;
+ void __iomem *ebu;
+ void __iomem *hsnand;
+ struct dma_chan *dma_tx;
+ struct dma_chan *dma_rx;
+ struct completion dma_access_complete;
+ unsigned long clk_rate;
+ struct clk *clk;
+ u32 nd_para0;
+ u8 cs_num;
+ struct ebu_nand_cs cs[MAX_CS];
+};
+
+static inline struct ebu_nand_controller *nand_to_ebu(struct nand_chip *chip)
+{
+ return container_of(chip, struct ebu_nand_controller, chip);
+}
+
+static u8 ebu_nand_readb(struct nand_chip *chip)
+{
+ struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
+ void __iomem *nand_wait = ebu_host->ebu + EBU_WAIT;
+ u8 cs_num = ebu_host->cs_num;
+ u32 stat;
+ int ret;
+ u8 val;
+
+ val = readb(ebu_host->cs[cs_num].chipaddr + HSNAND_CS_OFFS);
+
+ ret = readl_poll_timeout(nand_wait, stat, stat & EBU_WAIT_WR_C,
+ 20, 1000);
+ if (ret)
+ dev_warn(ebu_host->dev,
+ "ebu nand write timeout. nand_wait(0x%p)=0x%x\n",
+ nand_wait, readl(nand_wait));
+
+ return val;
+}
+
+static void ebu_nand_writeb(struct nand_chip *chip, u32 offset, u8 value)
+{
+ struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
+ void __iomem *nand_wait = ebu_host->ebu + EBU_WAIT;
+ u8 cs_num = ebu_host->cs_num;
+ u32 stat;
+ int ret;
+
+ writeb(value, ebu_host->cs[cs_num].chipaddr + offset);
+
+ ret = readl_poll_timeout(nand_wait, stat, stat & EBU_WAIT_WR_C,
+ 20, 1000);
+ if (ret)
+ dev_warn(ebu_host->dev,
+ "ebu nand write timeout. nand_wait(0x%p)=0x%x\n",
+ nand_wait, readl(nand_wait));
+}
+
+static void ebu_read_buf(struct nand_chip *chip, u_char *buf, unsigned int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ buf[i] = ebu_nand_readb(chip);
+}
+
+static void ebu_write_buf(struct nand_chip *chip, const u_char *buf, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ ebu_nand_writeb(chip, HSNAND_CS_OFFS, buf[i]);
+}
+
+static void ebu_nand_disable(struct nand_chip *chip)
+{
+ struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
+
+ writel(0, ebu_host->ebu + EBU_CON);
+}
+
+static void ebu_select_chip(struct nand_chip *chip)
+{
+ struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
+ void __iomem *nand_con = ebu_host->ebu + EBU_CON;
+ u32 cs = ebu_host->cs_num;
+
+ writel(EBU_CON_NANDM_EN | EBU_CON_CSMUX_E_EN | EBU_CON_CS_P_LOW |
+ EBU_CON_SE_P_LOW | EBU_CON_WP_P_LOW | EBU_CON_PRE_P_LOW |
+ EBU_CON_IN_CS_S(cs) | EBU_CON_OUT_CS_S(cs) |
+ EBU_CON_LAT_EN_CS_P, nand_con);
+}
+
+static void ebu_nand_setup_timing(struct ebu_nand_controller *ctrl,
+ const struct nand_sdr_timings *timings)
+{
+ unsigned int rate = clk_get_rate(ctrl->clk) / 1000000;
+ unsigned int period = DIV_ROUND_UP(1000000, rate);
+ u32 trecov, thold, twrwait, trdwait;
+ u32 reg = 0;
+
+ trecov = DIV_ROUND_UP(max(timings->tREA_max, timings->tREH_min),
+ period);
+ reg |= EBU_BUSCON_RECOVC(trecov);
+
+ thold = DIV_ROUND_UP(max(timings->tDH_min, timings->tDS_min), period);
+ reg |= EBU_BUSCON_HOLDC(thold);
+
+ trdwait = DIV_ROUND_UP(max(timings->tRC_min, timings->tREH_min),
+ period);
+ reg |= EBU_BUSCON_WAITRDC(trdwait);
+
+ twrwait = DIV_ROUND_UP(max(timings->tWC_min, timings->tWH_min), period);
+ reg |= EBU_BUSCON_WAITWRC(twrwait);
+
+ reg |= EBU_BUSCON_CMULT_V4 | EBU_BUSCON_BCGEN_CS | EBU_BUSCON_ALEC |
+ EBU_BUSCON_SETUP_EN;
+
+ writel(reg, ctrl->ebu + EBU_BUSCON(ctrl->cs_num));
+}
+
+static int ebu_nand_setup_data_interface(struct nand_chip *chip, int csline,
+ const struct nand_data_interface *conf)
+{
+ struct ebu_nand_controller *ctrl = nand_to_ebu(chip);
+ const struct nand_sdr_timings *timings;
+
+ timings = nand_get_sdr_timings(conf);
+ if (IS_ERR(timings))
+ return PTR_ERR(timings);
+
+ if (csline == NAND_DATA_IFACE_CHECK_ONLY)
+ return 0;
+
+ ebu_nand_setup_timing(ctrl, timings);
+
+ return 0;
+}
+
+static int ebu_nand_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+
+ if (section)
+ return -ERANGE;
+
+ oobregion->offset = HSNAND_ECC_OFFSET;
+ oobregion->length = chip->ecc.total;
+
+ return 0;
+}
+
+static int ebu_nand_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *oobregion)
+{
+ struct nand_chip *chip = mtd_to_nand(mtd);
+
+ if (section)
+ return -ERANGE;
+
+ oobregion->offset = chip->ecc.total + HSNAND_ECC_OFFSET;
+ oobregion->length = mtd->oobsize - oobregion->offset;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops ebu_nand_ooblayout_ops = {
+ .ecc = ebu_nand_ooblayout_ecc,
+ .free = ebu_nand_ooblayout_free,
+};
+
+static void ebu_dma_rx_callback(void *cookie)
+{
+ struct ebu_nand_controller *ebu_host = cookie;
+
+ dmaengine_terminate_async(ebu_host->dma_rx);
+
+ complete(&ebu_host->dma_access_complete);
+}
+
+static void ebu_dma_tx_callback(void *cookie)
+{
+ struct ebu_nand_controller *ebu_host = cookie;
+
+ dmaengine_terminate_async(ebu_host->dma_tx);
+
+ complete(&ebu_host->dma_access_complete);
+}
+
+static int ebu_dma_start(struct ebu_nand_controller *ebu_host, u32 dir,
+ const u8 *buf, u32 len)
+{
+ struct dma_async_tx_descriptor *tx;
+ struct completion *dma_completion;
+ dma_async_tx_callback callback;
+ struct dma_chan *chan;
+ dma_cookie_t cookie;
+ unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
+ dma_addr_t buf_dma;
+ int ret;
+ u32 timeout;
+
+ if (dir == DMA_DEV_TO_MEM) {
+ chan = ebu_host->dma_rx;
+ dma_completion = &ebu_host->dma_access_complete;
+ callback = ebu_dma_rx_callback;
+ } else {
+ chan = ebu_host->dma_tx;
+ dma_completion = &ebu_host->dma_access_complete;
+ callback = ebu_dma_tx_callback;
+ }
+
+ buf_dma = dma_map_single(chan->device->dev, (void *)buf, len, dir);
+ if (dma_mapping_error(chan->device->dev, buf_dma)) {
+ dev_err(ebu_host->dev, "Failed to map DMA buffer\n");
+ ret = -EIO;
+ goto err_unmap;
+ }
+
+ tx = dmaengine_prep_slave_single(chan, buf_dma, len, dir, flags);
+ if (!tx)
+ return -ENXIO;
+
+ tx->callback = callback;
+ tx->callback_param = ebu_host;
+ cookie = tx->tx_submit(tx);
+
+ ret = dma_submit_error(cookie);
+ if (ret) {
+ dev_err(ebu_host->dev, "dma_submit_error %d\n", cookie);
+ ret = -EIO;
+ goto err_unmap;
+ }
+
+ init_completion(dma_completion);
+ dma_async_issue_pending(chan);
+
+ /* Wait DMA to finish the data transfer.*/
+ timeout =
+ wait_for_completion_timeout(dma_completion, msecs_to_jiffies(1000));
+ if (!timeout) {
+ dev_err(ebu_host->dev, "I/O Error in DMA RX (status %d)\n",
+ dmaengine_tx_status(chan, cookie, NULL));
+ dmaengine_terminate_sync(chan);
+ ret = -ETIMEDOUT;
+ goto err_unmap;
+ }
+
+ return 0;
+
+err_unmap:
+ dma_unmap_single(ebu_host->dev, buf_dma, len, dir);
+
+ return ret;
+}
+
+static void ebu_nand_trigger(struct ebu_nand_controller *ebu_host,
+ int page, u32 cmd)
+{
+ unsigned int val;
+
+ val = cmd | (page & 0xFF) << HSNAND_CTL1_ADDR_SHIFT;
+ writel(val, ebu_host->hsnand + HSNAND_CTL1);
+ val = (page & 0xFFFF00) >> 8 | HSNAND_CTL2_CYC_N_V5;
+ writel(val, ebu_host->hsnand + HSNAND_CTL2);
+
+ writel(ebu_host->nd_para0, ebu_host->hsnand + HSNAND_PARA0);
+
+ /* clear first, will update later */
+ writel(0xFFFFFFFF, ebu_host->hsnand + HSNAND_CMSG_0);
+ writel(0xFFFFFFFF, ebu_host->hsnand + HSNAND_CMSG_1);
+
+ writel(HSNAND_INT_MSK_CTL_WR_C,
+ ebu_host->hsnand + HSNAND_INT_MSK_CTL);
+
+ val = cmd == NAND_CMD_READ0 ? HSNAND_CTL_RW_READ : HSNAND_CTL_RW_WRITE;
+
+ writel(HSNAND_CTL_MSG_EN | HSNAND_CTL_CKFF_EN |
+ HSNAND_CTL_ECC_OFF_V8TH | HSNAND_CTL_CE_SEL_CS(ebu_host->cs_num) |
+ HSNAND_CTL_ENABLE_ECC | HSNAND_CTL_GO | val,
+ ebu_host->hsnand + HSNAND_CTL);
+}
+
+static int ebu_nand_read_page_hwecc(struct nand_chip *chip, u8 *buf,
+ int oob_required, int page)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
+ int ret, x;
+
+ ebu_nand_trigger(ebu_host, page, NAND_CMD_READ0);
+
+ ret = ebu_dma_start(ebu_host, DMA_DEV_TO_MEM, buf, mtd->writesize);
+ if (ret)
+ return ret;
+
+ if (oob_required)
+ chip->ecc.read_oob(chip, page);
+
+ x = readl(ebu_host->hsnand + HSNAND_CTL);
+ x &= ~HSNAND_CTL_GO;
+ writel(x, ebu_host->hsnand + HSNAND_CTL);
+
+ return 0;
+}
+
+static int ebu_nand_write_page_hwecc(struct nand_chip *chip, const u8 *buf,
+ int oob_required, int page)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
+ void __iomem *int_sta = ebu_host->hsnand + HSNAND_INT_STA;
+ int ret, val, x;
+ u32 reg;
+
+ ebu_nand_trigger(ebu_host, page, NAND_CMD_SEQIN);
+
+ ret = ebu_dma_start(ebu_host, DMA_MEM_TO_DEV, buf, mtd->writesize);
+ if (ret)
+ return ret;
+
+ if (oob_required) {
+ reg = (chip->oob_poi[3] << 24) | (chip->oob_poi[2] << 16) |
+ (chip->oob_poi[1] << 8) | chip->oob_poi[0];
+
+ writel(reg, ebu_host->hsnand + HSNAND_CMSG_0);
+
+ reg = (chip->oob_poi[7] << 24) | (chip->oob_poi[6] << 16) |
+ (chip->oob_poi[5] << 8) | chip->oob_poi[4];
+
+ writel(reg, ebu_host->hsnand + HSNAND_CMSG_1);
+ }
+
+ ret = readl_poll_timeout_atomic(int_sta, val,
+ !(val & HSNAND_INT_STA_WR_C), 10, 1000);
+ if (ret)
+ return -EIO;
+
+ x = readl(ebu_host->hsnand + HSNAND_CTL);
+ x &= ~HSNAND_CTL_GO;
+ writel(x, ebu_host->hsnand + HSNAND_CTL);
+
+ return 0;
+}
+
+static const u8 ecc_strength[] = { 1, 1, 4, 8, 24, 32, 40, 60, };
+
+static int ebu_nand_attach_chip(struct nand_chip *chip)
+{
+ struct mtd_info *mtd = nand_to_mtd(chip);
+ struct ebu_nand_controller *ebu_host = nand_get_controller_data(chip);
+ u32 eccsize, eccsteps, eccbytes, ecctotal, pagesize, pg_per_blk;
+ u32 eccstrength = chip->ecc.strength;
+ u32 writesize = mtd->writesize;
+ u32 blocksize = mtd->erasesize;
+ int start, val, i;
+
+ if (chip->ecc.mode != NAND_ECC_HW)
+ return 0;
+
+ /* Check whether eccsize is 0x0 or wrong. assign eccsize = 512 if YES */
+ if (!chip->ecc.size)
+ chip->ecc.size = 512;
+ eccsize = chip->ecc.size;
+
+ switch (eccsize) {
+ case 512:
+ start = 1;
+ if (!eccstrength)
+ eccstrength = 4;
+ break;
+ case 1024:
+ start = 4;
+ if (!eccstrength)
+ eccstrength = 32;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ i = round_up(start + 1, 4);
+ for (val = start; val < i; val++) {
+ if (eccstrength == ecc_strength[val])
+ break;
+ }
+ if (val == i)
+ return -EINVAL;
+
+ if (eccstrength == 8)
+ eccbytes = 14;
+ else
+ eccbytes = DIV_ROUND_UP(eccstrength * fls(8 * eccsize), 8);
+
+ eccsteps = writesize / eccsize;
+ ecctotal = eccsteps * eccbytes;
+ if ((ecctotal + 8) > mtd->oobsize)
+ return -ERANGE;
+
+ chip->ecc.total = ecctotal;
+ pagesize = fls(writesize >> 11);
+ if (pagesize > HSNAND_PARA0_PAGE_V8192)
+ return -ERANGE;
+
+ pg_per_blk = fls((blocksize / writesize) >> 6) << 4;
+ if (pg_per_blk > HSNAND_PARA0_PIB_V256)
+ return -ERANGE;
+
+ ebu_host->nd_para0 = pagesize | pg_per_blk | HSNAND_PARA0_BYP_EN_NP |
+ HSNAND_PARA0_BYP_DEC_NP | HSNAND_PARA0_ADEP_EN |
+ HSNAND_PARA0_TYPE_ONFI | (val << 29);
+
+ mtd_set_ooblayout(mtd, &ebu_nand_ooblayout_ops);
+ chip->ecc.read_page = ebu_nand_read_page_hwecc;
+ chip->ecc.write_page = ebu_nand_write_page_hwecc;
+
+ return 0;
+}
+
+static int ebu_nand_exec_op(struct nand_chip *chip,
+ const struct nand_operation *op, bool check_only)
+{
+ struct ebu_nand_controller *ctrl = nand_to_ebu(chip);
+ const struct nand_op_instr *instr = NULL;
+ unsigned int op_id;
+ int i, time_out, ret = 0;
+ u32 stat;
+
+ ebu_select_chip(chip);
+
+ for (op_id = 0; op_id < op->ninstrs; op_id++) {
+ instr = &op->instrs[op_id];
+
+ switch (instr->type) {
+ case NAND_OP_CMD_INSTR:
+ ebu_nand_writeb(chip, HSNAND_CLE_OFFS | HSNAND_CS_OFFS,
+ instr->ctx.cmd.opcode);
+ break;
+
+ case NAND_OP_ADDR_INSTR:
+ for (i = 0; i < instr->ctx.addr.naddrs; i++)
+ ebu_nand_writeb(chip,
+ HSNAND_ALE_OFFS | HSNAND_CS_OFFS,
+ instr->ctx.addr.addrs[i]);
+ break;
+
+ case NAND_OP_DATA_IN_INSTR:
+ ebu_read_buf(chip, instr->ctx.data.buf.in,
+ instr->ctx.data.len);
+ break;
+
+ case NAND_OP_DATA_OUT_INSTR:
+ ebu_write_buf(chip, instr->ctx.data.buf.out,
+ instr->ctx.data.len);
+ break;
+
+ case NAND_OP_WAITRDY_INSTR:
+ time_out = instr->ctx.waitrdy.timeout_ms * 1000;
+ ret = readl_poll_timeout(ctrl->ebu + EBU_WAIT,
+ stat, stat & EBU_WAIT_RDBY,
+ 20, time_out);
+ break;
+ }
+ }
+
+ return ret;
+}
+
+static const struct nand_controller_ops ebu_nand_controller_ops = {
+ .attach_chip = ebu_nand_attach_chip,
+ .exec_op = ebu_nand_exec_op,
+ .setup_data_interface = ebu_nand_setup_data_interface,
+};
+
+static void ebu_dma_cleanup(struct ebu_nand_controller *ebu_host)
+{
+ if (ebu_host->dma_rx)
+ dma_release_channel(ebu_host->dma_rx);
+
+ if (ebu_host->dma_tx)
+ dma_release_channel(ebu_host->dma_tx);
+}
+
+static int ebu_nand_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct ebu_nand_controller *ebu_host;
+ struct nand_chip *nand;
+ struct mtd_info *mtd;
+ struct resource *res;
+ char *resname;
+ int ret, i;
+ u32 reg;
+
+ ebu_host = devm_kzalloc(dev, sizeof(*ebu_host), GFP_KERNEL);
+ if (!ebu_host)
+ return -ENOMEM;
+
+ ebu_host->dev = dev;
+ nand_controller_init(&ebu_host->controller);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ebunand");
+ ebu_host->ebu = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(ebu_host->ebu))
+ return PTR_ERR(ebu_host->ebu);
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hsnand");
+ ebu_host->hsnand = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(ebu_host->hsnand))
+ return PTR_ERR(ebu_host->hsnand);
+
+ ret = device_property_read_u32(dev, "nand,cs", ®);
+ if (ret) {
+ dev_err(dev, "failed to get chip select: %d\n", ret);
+ return ret;
+ }
+ ebu_host->cs_num = reg;
+
+ for (i = 0; i < MAX_CS; i++) {
+ resname = devm_kasprintf(dev, GFP_KERNEL, "nand_cs%d", i);
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ resname);
+ if (!res)
+ return -EINVAL;
+ ebu_host->cs[i].chipaddr = devm_ioremap_resource(dev, res);
+ ebu_host->cs[i].nand_pa = res->start;
+ if (IS_ERR(ebu_host->cs[i].chipaddr))
+ return PTR_ERR(ebu_host->cs[i].chipaddr);
+ }
+
+ ebu_host->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(ebu_host->clk)) {
+ ret = PTR_ERR(ebu_host->clk);
+ dev_err(dev, "failed to get clock: %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(ebu_host->clk);
+ if (ret) {
+ dev_err(dev, "failed to enable clock: %d\n", ret);
+ return ret;
+ }
+ ebu_host->clk_rate = clk_get_rate(ebu_host->clk);
+
+ ebu_host->dma_tx = dma_request_chan(dev, "tx");
+ if (IS_ERR(ebu_host->dma_tx)) {
+ ret = PTR_ERR(ebu_host->dma_tx);
+ dev_err(dev, "DMA tx channel request fail!.\n");
+ goto err_cleanup_dma;
+ }
+
+ ebu_host->dma_rx = dma_request_chan(dev, "rx");
+ if (IS_ERR(ebu_host->dma_rx)) {
+ ret = PTR_ERR(ebu_host->dma_rx);
+ dev_err(dev, "DMA rx channel request fail!.\n");
+ goto err_cleanup_dma;
+ }
+
+ for (i = 0; i < MAX_CS; i++) {
+ resname = devm_kasprintf(dev, GFP_KERNEL, "addr_sel%d", i);
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ resname);
+ if (!res)
+ return -EINVAL;
+ ebu_host->cs[i].addr_sel = res->start;
+ writel(ebu_host->cs[i].addr_sel | EBU_ADDR_MASK(5) |
+ EBU_ADDR_SEL_REGEN, ebu_host->ebu + EBU_ADDR_SEL(i));
+ }
+
+ nand_set_flash_node(&ebu_host->chip, dev->of_node);
+ mtd = nand_to_mtd(&ebu_host->chip);
+ mtd->dev.parent = dev;
+ ebu_host->dev = dev;
+
+ platform_set_drvdata(pdev, ebu_host);
+ nand_set_controller_data(&ebu_host->chip, ebu_host);
+
+ nand = &ebu_host->chip;
+ nand->controller = &ebu_host->controller;
+ nand->controller->ops = &ebu_nand_controller_ops;
+
+ /* Scan to find existence of the device */
+ ret = nand_scan(&ebu_host->chip, 1);
+ if (ret)
+ goto err_cleanup_dma;
+
+ ret = mtd_device_register(mtd, NULL, 0);
+ if (ret)
+ goto err_clean_nand;
+
+ return 0;
+
+err_clean_nand:
+ nand_cleanup(&ebu_host->chip);
+err_cleanup_dma:
+ ebu_dma_cleanup(ebu_host);
+ clk_disable_unprepare(ebu_host->clk);
+
+ return ret;
+}
+
+static int ebu_nand_remove(struct platform_device *pdev)
+{
+ struct ebu_nand_controller *ebu_host = platform_get_drvdata(pdev);
+
+ mtd_device_unregister(nand_to_mtd(&ebu_host->chip));
+ nand_cleanup(&ebu_host->chip);
+ ebu_nand_disable(&ebu_host->chip);
+ ebu_dma_cleanup(ebu_host);
+ clk_disable_unprepare(ebu_host->clk);
+
+ return 0;
+}
+
+static const struct of_device_id ebu_nand_match[] = {
+ { .compatible = "intel,nand-controller", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, ebu_nand_match);
+
+static struct platform_driver ebu_nand_driver = {
+ .probe = ebu_nand_probe,
+ .remove = ebu_nand_remove,
+ .driver = {
+ .name = "intel-nand-controller",
+ .of_match_table = ebu_nand_match,
+ },
+
+};
+module_platform_driver(ebu_nand_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Vadivel Murugan R <vadivel.muruganx.ramuthevar@intel.com>");
+MODULE_DESCRIPTION("Intel's LGM External Bus NAND Controller driver");
--
2.11.0
^ permalink raw reply related
* Re: [PATCH] arm64: dts: meson: add ethernet interrupt to wetek dtsi
From: Kevin Hilman @ 2020-05-20 0:07 UTC (permalink / raw)
To: linux-amlogic, linux-kernel, Rob Herring, linux-arm-kernel,
Mark Rutland, devicetree, Christian Hewitt
In-Reply-To: <20200518025451.16401-1-christianshewitt@gmail.com>
On Mon, 18 May 2020 02:54:51 +0000, Christian Hewitt wrote:
> Add Ethernet interrupt details to the WeTek Hub/Play2 dtsi to resolve
> an issue with Ethernet probing in mainline u-boot.
Applied, thanks!
[1/1] arm64: dts: meson: add ethernet interrupt to wetek dtsi
commit: 647e1643d61312ce08172e466fa1c8d8a5c8fbc8
Best regards,
--
Kevin Hilman <khilman@baylibre.com>
^ permalink raw reply
* Re: [PATCH 0/7] arm64: dts: meson: add internal audio DAC support
From: Kevin Hilman @ 2020-05-20 0:07 UTC (permalink / raw)
To: Jerome Brunet; +Cc: devicetree, linux-kernel, linux-amlogic
In-Reply-To: <20200506221656.477379-1-jbrunet@baylibre.com>
On Thu, 7 May 2020 00:16:49 +0200, Jerome Brunet wrote:
> This patchset adds support for the internal audio DAC found on the gxl,
> g12 and sm1 SoC family.
>
> It was mainly tested on the gxl libretech-cc and g12a u200.
>
> /!\
> This series (patches 1 in particular) depends on this reset binding [0].
> Philipp has provided an immutable with it here [1]
>
> [...]
Applied, thanks!
[1/7] arm64: dts: meson: gxl: add acodec support
commit: a66d4ae3144a18476626dd8de8b8dff5f523daee
[2/7] arm64: dts: meson: p230-q200: add internal DAC support
commit: f3c35382259f67c2ae878de2142fb58b94df0525
[3/7] arm64: dts: meson: libretech-cc: add internal DAC support
commit: 249ce3777c25b383702e91a6547ffc676dc004a5
[4/7] arm64: dts: meson: libretech-ac: add internal DAC support
commit: 451323f8bc9e9b701b87b4598ec1cac8eff82d15
[5/7] arm64: dts: meson: libretech-pc: add internal DAC support
commit: 2989a2d6c7f36da2bddffdb293bdf123e735d5f7
[6/7] arm64: dts: meson: g12: add internal DAC
commit: 457fa78771a23ecedf3bcd9ce9946a5183472ff6
[7/7] arm64: dts: meson: g12: add internal DAC glue
commit: dbffd7f9bdb463437d3c3f7c3e1bd4379a785fe4
Best regards,
--
Kevin Hilman <khilman@baylibre.com>
^ permalink raw reply
* Re: [PATCH v8 0/3] arm64: dts: meson: add dts/bindings for SmartLabs SML-5442TW
From: Kevin Hilman @ 2020-05-20 0:07 UTC (permalink / raw)
To: linux-amlogic, linux-kernel, Rob Herring, linux-arm-kernel,
Mark Rutland, devicetree, Christian Hewitt
In-Reply-To: <20200510124129.31575-1-christianshewitt@gmail.com>
On Sun, 10 May 2020 12:41:26 +0000, Christian Hewitt wrote:
> This series adds new bindings and a device-tree file for the Smartlabs
> SML-5442TW set-top box which is based on the P231 reference design.
>
> As requested, I have reworked the device-tree on the p23x-q20x dtsi. I
> have also re-added the BT device with new bindings that have now been
> merged in bluetooth-next for inclusion in Linux 5.8. See [1].
>
> [...]
Applied, thanks!
[1/3] dt-bindings: add vendor prefix for Smartlabs LLC
commit: bc15895e142396fed5ebf1f60139d9ca9a56a4e4
[2/3] dt-bindings: arm: amlogic: add support for the Smartlabs SML-5442TW
commit: 341e85047bdbc0196c91ccb4612ffab87bae9cfe
[3/3] arm64: dts: meson: add support for the Smartlabs SML-5442TW
commit: 1d6ece87b750cf26fed4eb794ea0b2fc7ff2be10
Best regards,
--
Kevin Hilman <khilman@baylibre.com>
^ permalink raw reply
* [RESENDPATCH v8 1/2] dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC
From: Ramuthevar,Vadivel MuruganX @ 2020-05-20 0:06 UTC (permalink / raw)
To: linux-kernel, linux-mtd, devicetree
Cc: miquel.raynal, richard, vigneshr, arnd, brendanhiggins, tglx,
boris.brezillon, anders.roxell, masonccyang, robh+dt, linux-mips,
hauke.mehrtens, andriy.shevchenko, qi-ming.wu, cheol.yong.kim,
Ramuthevar Vadivel Murugan
In-Reply-To: <20200520000621.49152-1-vadivel.muruganx.ramuthevar@linux.intel.com>
From: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
Add YAML file for dt-bindings to support NAND Flash Controller
on Intel's Lightning Mountain SoC.
Signed-off-by: Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
---
.../devicetree/bindings/mtd/intel,lgm-nand.yaml | 91 ++++++++++++++++++++++
1 file changed, 91 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
diff --git a/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
new file mode 100644
index 000000000000..cd4e983a449e
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/intel,lgm-nand.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel LGM SoC NAND Controller Device Tree Bindings
+
+allOf:
+ - $ref: "nand-controller.yaml"
+
+maintainers:
+ - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
+
+properties:
+ compatible:
+ const: intel,lgm-nand-controller
+
+ reg:
+ items:
+ - description: ebunand registers
+ - description: hsnand registers
+ - description: nand_cs0 external flash access
+ - description: nand_cs1 external flash access
+ - description: addr_sel0 memory region enable and access
+ - description: addr_sel1 memory region enable and access
+
+ clocks:
+ maxItems: 1
+
+ dmas:
+ maxItems: 2
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+
+patternProperties:
+ "^nand@[a-f0-9]+$":
+ type: object
+ properties:
+ reg:
+ minimum: 0
+ maximum: 7
+
+ nand-ecc-mode: true
+
+ nand-ecc-algo:
+ const: hw
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - dmas
+ - dma-names
+
+additionalProperties: false
+
+examples:
+ - |
+ nand-controller@e0f00000 {
+ compatible = "intel,lgm-nand";
+ reg = <0xe0f00000 0x100>,
+ <0xe1000000 0x300>,
+ <0xe1400000 0x8000>,
+ <0xe1c00000 0x1000>,
+ <0x17400000 0x4>,
+ <0x17c00000 0x4>;
+ reg-names = "ebunand", "hsnand", "nand_cs0", "nand_cs1",
+ "addr_sel0","addr_sel1";
+ clocks = <&cgu0 125>;
+ dmas = <&dma0 8>, <&dma0 9>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ nand@0 {
+ reg = <0>;
+ nand-on-flash-bbt;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ };
+ };
+
+...
--
2.11.0
^ permalink raw reply related
* [RESENDPATCH v8 0/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC
From: Ramuthevar,Vadivel MuruganX @ 2020-05-20 0:06 UTC (permalink / raw)
To: linux-kernel, linux-mtd, devicetree
Cc: miquel.raynal, richard, vigneshr, arnd, brendanhiggins, tglx,
boris.brezillon, anders.roxell, masonccyang, robh+dt, linux-mips,
hauke.mehrtens, andriy.shevchenko, qi-ming.wu, cheol.yong.kim,
Ramuthevar,Vadivel MuruganX
This patch adds the new IP of Nand Flash Controller(NFC) support
on Intel's Lightning Mountain(LGM) SoC.
DMA is used for burst data transfer operation, also DMA HW supports
aligned 32bit memory address and aligned data access by default.
DMA burst of 8 supported. Data register used to support the read/write
operation from/to device.
NAND controller also supports in-built HW ECC engine.
NAND controller driver implements ->exec_op() to replace legacy hooks,
these specific call-back method to execute NAND operations.
Thanks Boris, Andy and Arnd for the review comments and suggestions.
---
v8:
- fix the kbuild bot warnings
- correct the typo's
v7:
- indentation issue is fixed
- add error check for retrieve the resource from dt
- Rob's review comments addressed
- dt-schema build issue fixed with upgraded dt-schema
v6:
- update EBU_ADDR_SELx register base value build it from DT
- Add tabs in in Kconfig
- Rob's review comments addressed in YAML file
- add addr_sel0 and addr_sel1 reg-names in YAML example
v5:
- replace by 'HSNAND_CLE_OFFS | HSNAND_CS_OFFS' to NAND_WRITE_CMD and NAND_WRITE_ADDR
- remove the unused macros
- update EBU_ADDR_MASK(x) macro
- update the EBU_ADDR_SELx register values to be written
- add the example in YAML file
v4:
- add ebu_nand_cs structure for multiple-CS support
- mask/offset encoding for 0x51 value
- update macro HSNAND_CTL_ENABLE_ECC
- drop the op argument and un-used macros.
- updated the datatype and macros
- add function disable nand module
- remove ebu_host->dma_rx = NULL;
- rename MMIO address range variables to ebu and hsnand
- implement ->setup_data_interface()
- update label err_cleanup_nand and err_cleanup_dma
- add return value check in the nand_remove function
- add/remove tabs and spaces as per coding standard
- encoded CS ids by reg property
v3:
- Add depends on MACRO in Kconfig
- file name update in Makefile
- file name update to intel-nand-controller
- modification of MACRO divided like EBU, HSNAND and NAND
- add NAND_ALE_OFFS, NAND_CLE_OFFS and NAND_CS_OFFS
- rename lgm_ to ebu_ and _va suffix is removed in the whole file
- rename structure and varaibles as per review comments.
- remove lgm_read_byte(), lgm_dev_ready() and cmd_ctrl() un-used function
- update in exec_op() as per review comments
- rename function lgm_dma_exit() by lgm_dma_cleanup()
- hardcoded magic value for base and offset replaced by MACRO defined
- mtd_device_unregister() + nand_cleanup() instead of nand_release()
v2:
- implement the ->exec_op() to replaces the legacy hook-up.
- update the commit message
- YAML compatible string update to intel, lgm-nand-controller
- add MIPS maintainers and xway_nand driver author in CC
v1:
- initial version
Ramuthevar Vadivel Murugan (2):
dt-bindings: mtd: Add Nand Flash Controller support for Intel LGM SoC
mtd: rawnand: Add NAND controller support on Intel LGM SoC
.../devicetree/bindings/mtd/intel,lgm-nand.yaml | 91 +++
drivers/mtd/nand/raw/Kconfig | 8 +
drivers/mtd/nand/raw/Makefile | 1 +
drivers/mtd/nand/raw/intel-nand-controller.c | 747 +++++++++++++++++++++
4 files changed, 847 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/intel,lgm-nand.yaml
create mode 100644 drivers/mtd/nand/raw/intel-nand-controller.c
--
2.11.0
^ permalink raw reply
* Re: [kbuild-all] Re: [PATCH net-next 2/4] net: phy: dp83869: Set opmode from straps
From: Philip Li @ 2020-05-19 23:54 UTC (permalink / raw)
To: Dan Murphy
Cc: kbuild test robot, andrew, f.fainelli, hkallweit1, davem,
kbuild-all, netdev, linux-kernel, devicetree
In-Reply-To: <ac286fd2-b77f-9103-d9f2-aa95ad792476@ti.com>
On Tue, May 19, 2020 at 12:40:37PM -0500, Dan Murphy wrote:
> kbuild
>
> On 5/19/20 12:19 PM, kbuild test robot wrote:
> > Hi Dan,
> >
> > I love your patch! Perhaps something to improve:
> >
> > [auto build test WARNING on net-next/master]
> > [also build test WARNING on robh/for-next sparc-next/master net/master linus/master v5.7-rc6 next-20200518]
> > [if your patch is applied to the wrong git tree, please drop us a note to help
> > improve the system. BTW, we also suggest to use '--base' option to specify the
> > base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
> >
> > url: https://github.com/0day-ci/linux/commits/Dan-Murphy/DP83869-Enhancements/20200519-222047
> > base: https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git 5cdfe8306631b2224e3f81fc5a1e2721c7a1948b
> > config: sh-allmodconfig (attached as .config)
> > compiler: sh4-linux-gcc (GCC) 9.3.0
> > reproduce:
> > wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> > chmod +x ~/bin/make.cross
> > # save the attached .config to linux build tree
> > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=sh
> >
> > If you fix the issue, kindly add following tag as appropriate
> > Reported-by: kbuild test robot <lkp@intel.com>
> >
> > All warnings (new ones prefixed by >>, old ones prefixed by <<):
> >
> > drivers/net/phy/dp83869.c: In function 'dp83869_set_strapped_mode':
> > > > drivers/net/phy/dp83869.c:171:10: warning: comparison is always false due to limited range of data type [-Wtype-limits]
> > 171 | if (val < 0)
>
> This looks to be a false positive.
>
> phy_read_mmd will return an errno or a value from 0->15
thanks, here because val is defined as "u16 val", the comparison
to < 0 can not work as expected. Any err returned from phy_read_mmd,
which is int, will be converted to u16.
>
> So if errno is returned then this will be true.
>
> Unless I have to do IS_ERR.
>
> Dan
> _______________________________________________
> kbuild-all mailing list -- kbuild-all@lists.01.org
> To unsubscribe send an email to kbuild-all-leave@lists.01.org
^ permalink raw reply
* Re: [PATCH 3/4] clk/soc: mediatek: mt6779: Bind clock driver from platform device
From: Chun-Kuang Hu @ 2020-05-19 23:52 UTC (permalink / raw)
To: Matthias Brugger
Cc: Chun-Kuang Hu, matthias.bgg, Rob Herring, Matthias Brugger,
Michael Turquette, Stephen Boyd, Kate Stewart, devicetree,
Greg Kroah-Hartman, linux-kernel,
moderated list:ARM/Mediatek SoC support, Linux ARM, mtk01761,
Thomas Gleixner, linux-clk, Allison Randal
In-Reply-To: <3a8b3846-c399-2193-a203-8707d693dad8@suse.com>
Matthias Brugger <mbrugger@suse.com> 於 2020年5月20日 週三 上午5:26寫道：
>
>
>
> On 19/05/2020 17:10, Chun-Kuang Hu wrote:
> > Hi, Matthias:
> >
> > <matthias.bgg@kernel.org> 於 2020年5月18日 週一 下午7:33寫道：
> >>
> >> From: Matthias Brugger <matthias.bgg@gmail.com>
> >>
> >> The mmsys driver is now the top level entry point for the multimedia
> >> system (mmsys), we bind the clock driver by creating a platform device.
> >> We also bind the MediaTek DRM driver which is not yet implement and
> >> therefor will errror out for now.
> >>
> >> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
> >> ---
> >>
> >> drivers/clk/mediatek/clk-mt6779-mm.c | 9 ++-------
> >> drivers/soc/mediatek/mtk-mmsys.c | 8 ++++++++
> >> 2 files changed, 10 insertions(+), 7 deletions(-)
> >>
> >> diff --git a/drivers/clk/mediatek/clk-mt6779-mm.c b/drivers/clk/mediatek/clk-mt6779-mm.c
> >> index fb5fbb8e3e41..059c1a41ac7a 100644
> >> --- a/drivers/clk/mediatek/clk-mt6779-mm.c
> >> +++ b/drivers/clk/mediatek/clk-mt6779-mm.c
> >> @@ -84,15 +84,11 @@ static const struct mtk_gate mm_clks[] = {
> >> GATE_MM1(CLK_MM_DISP_OVL_FBDC, "mm_disp_ovl_fbdc", "mm_sel", 16),
> >> };
> >>
> >> -static const struct of_device_id of_match_clk_mt6779_mm[] = {
> >> - { .compatible = "mediatek,mt6779-mmsys", },
> >> - {}
> >> -};
> >> -
> >> static int clk_mt6779_mm_probe(struct platform_device *pdev)
> >> {
> >> + struct device *dev = &pdev->dev;
> >> + struct device_node *node = dev->parent->of_node;
> >> struct clk_onecell_data *clk_data;
> >> - struct device_node *node = pdev->dev.of_node;
> >>
> >> clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
> >>
> >> @@ -106,7 +102,6 @@ static struct platform_driver clk_mt6779_mm_drv = {
> >> .probe = clk_mt6779_mm_probe,
> >> .driver = {
> >> .name = "clk-mt6779-mm",
> >> - .of_match_table = of_match_clk_mt6779_mm,
> >> },
> >> };
> >>
> >> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> >> index fee64c8d3020..dc15808cf3a3 100644
> >> --- a/drivers/soc/mediatek/mtk-mmsys.c
> >> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> >> @@ -88,6 +88,10 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
> >> .clk_driver = "clk-mt2712-mm",
> >> };
> >>
> >> +static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
> >> + .clk_driver = "clk-mt6779-mm",
> >
> > This patch looks good to me, but I've one question: why drm driver
> > just use single "mediatek-drm" for sub driver name, but clock driver
> > has different name for each SoC?
> > Could we just use single name for clock driver such as "mediatek-clk-mm"?
>
> Because the DRM for all SoCs are handled in the same driver, while we have a
> different clock drivers for each SoC. So we need to specify which clock driver
> we want to load.
>
> If we want to change that, we would need to refactor heavily the clock drivers
> for all MediaTek SoCs. I don't think it's worth the effort.
>
OK, so for this patch,
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
> Regards,
> Matthias
>
> >
> > Regards,
> > Chun-Kuang.
> >
> >> +};
> >> +
> >> static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
> >> .clk_driver = "clk-mt6797-mm",
> >> };
> >> @@ -343,6 +347,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
> >> .compatible = "mediatek,mt2712-mmsys",
> >> .data = &mt2712_mmsys_driver_data,
> >> },
> >> + {
> >> + .compatible = "mediatek,mt6779-mmsys",
> >> + .data = &mt6779_mmsys_driver_data,
> >> + },
> >> {
> >> .compatible = "mediatek,mt6797-mmsys",
> >> .data = &mt6797_mmsys_driver_data,
> >> --
> >> 2.26.2
> >>
> >>
> >> _______________________________________________
> >> Linux-mediatek mailing list
> >> Linux-mediatek@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply
* Re: [PATCH v3 0/5] arm64: dts: meson: add W400 dtsi and GT-King/Pro devices
From: Kevin Hilman @ 2020-05-19 23:42 UTC (permalink / raw)
To: Christian Hewitt, Rob Herring, Mark Rutland, devicetree,
linux-arm-kernel, linux-amlogic, linux-kernel
Cc: Christian Hewitt
In-Reply-To: <20200518023404.15166-1-christianshewitt@gmail.com>
Hi Christian,
Christian Hewitt <christianshewitt@gmail.com> writes:
> This series combines patch 2 from [1] which converts the existing Ugoos
> AM6 device-tree to a common W400 dtsi and dts, and then reworks the
> Beelink GT-King/GT-King Pro serries from [2] to use the dtsi, but this
> time without the offending common audio dtsi approach. I've carried
> forwards acks on bindings from Rob as these did not change.
This looks good to me, thank you very much for reworking into a
w400-based include.
Unfortunately, it no longer applies on top of all the other stuff I have
queued for v5.8.
Could you please do a rebase on top of my v5.8/dt64 branch[1], and I'll
queue for v5.8.
Thanks,
Kevin
> v3 - amend author full-name on bindings patch
>
> [1] https://patchwork.kernel.org/patch/11497105/
> [2] https://patchwork.kernel.org/project/linux-amlogic/list/?series=273483
>
> Christian Hewitt (5):
> arm64: dts: meson: convert ugoos-am6 to common w400 dtsi
> dt-bindings: arm: amlogic: add support for the Beelink GT-King
> arm64: dts: meson-g12b-gtking: add initial device-tree
> dt-bindings: arm: amlogic: add support for the Beelink GT-King Pro
> arm64: dts: meson-g12b-gtking-pro: add initial device-tree
>
> .../devicetree/bindings/arm/amlogic.yaml | 2 +
> arch/arm64/boot/dts/amlogic/Makefile | 2 +
> .../dts/amlogic/meson-g12b-gtking-pro.dts | 125 ++++++
> .../boot/dts/amlogic/meson-g12b-gtking.dts | 145 ++++++
> .../boot/dts/amlogic/meson-g12b-ugoos-am6.dts | 410 +----------------
> .../boot/dts/amlogic/meson-g12b-w400.dtsi | 423 ++++++++++++++++++
> 6 files changed, 698 insertions(+), 409 deletions(-)
> create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-gtking-pro.dts
> create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-gtking.dts
> create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12b-w400.dtsi
>
> --
> 2.17.1
^ permalink raw reply
* Re: [PATCH v3] arm64: dts: qcom: apq8016-sbc-d3: Add Qualcomm APQ8016 SBC + D3Camera mezzanine
From: Bjorn Andersson @ 2020-05-19 23:24 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: Robert Foss, Vinod Koul, Rob Herring, linux-arm-msm, devicetree,
linux-kernel, Nicolas Dechesne
In-Reply-To: <20200519102256.GB8114@Mani-XPS-13-9360>
On Tue 19 May 03:22 PDT 2020, Manivannan Sadhasivam wrote:
> Hi Robert,
>
> On Mon, May 18, 2020 at 10:21:29AM +0200, Robert Foss wrote:
> > Add device treee support for the Qualcomm APQ8016 SBC, otherwise known as
> > the Dragonboard 410c with the D3Camera mezzanine expansion board.
> >
> > The D3Camera mezzanine ships in a kit with a OmniVision 5640 sensor module,
> > which is what this DT targets.
> >
>
> What is the motivation behind adding this new dts? We have been using the
> userspace tool [1] for applying this as an overlay for some time. But if we
> start adding dts for mezzanines then for sure we'll end up with some good
> numbers which will flood arch/{..}/qcom directory.
>
> I could understand that one of the motivation is to provide nice user experience
> to users but that's also taken care by the dt-update tool IMO.
>
The motivation for posting this was to provoke a response like yours.
I knew about [1], but not that it included the overlays. I'm okay with
using overlays and the dt-update tool. But I would have preferred that
the dts files didn't live out of tree, given that this approach breaks
if I change the name of a node you depend on upstream.
Thanks,
Bjorn
> Thanks,
> Mani
>
> [1] https://github.com/96boards/dt-update
>
> > Signed-off-by: Robert Foss <robert.foss@linaro.org>
> > ---
> >
> > Changes since v2:
> > - Vinod: Change copyright assignment to Linaro
> >
> > Changes since v1:
> > - Vinod: Changed license to GPL+BSD
> > - Vinod: Changed copyright year to 2020
> > - Nico: Changed name of mezzanine to d3camera
> >
> > arch/arm64/boot/dts/qcom/Makefile | 1 +
> > .../boot/dts/qcom/apq8016-sbc-d3camera.dts | 45 +++++++++++++++++++
> > 2 files changed, 46 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/qcom/apq8016-sbc-d3camera.dts
> >
> > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> > index cc103f7020fd..3f95b522694e 100644
> > --- a/arch/arm64/boot/dts/qcom/Makefile
> > +++ b/arch/arm64/boot/dts/qcom/Makefile
> > @@ -1,5 +1,6 @@
> > # SPDX-License-Identifier: GPL-2.0
> > dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
> > +dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc-d3camera.dtb
> > dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
> > dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
> > dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
> > diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc-d3camera.dts b/arch/arm64/boot/dts/qcom/apq8016-sbc-d3camera.dts
> > new file mode 100644
> > index 000000000000..752e5ec47499
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc-d3camera.dts
> > @@ -0,0 +1,45 @@
> > +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
> > +/*
> > + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include "apq8016-sbc.dtsi"
> > +
> > +/ {
> > + model = "Qualcomm Technologies, Inc. APQ 8016 SBC w/ D3Camera Mezzanine";
> > + compatible = "qcom,apq8016-sbc", "qcom,apq8016", "qcom,sbc";
> > +};
> > +
> > +&cci_i2c0 {
> > + /delete-node/ camera_rear@3b;
> > +
> > + camera_rear@76 {
> > + compatible = "ovti,ov5640";
> > + reg = <0x76>;
> > +
> > + enable-gpios = <&msmgpio 34 GPIO_ACTIVE_HIGH>;
> > + reset-gpios = <&msmgpio 35 GPIO_ACTIVE_LOW>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&camera_rear_default>;
> > +
> > + clocks = <&gcc GCC_CAMSS_MCLK0_CLK>;
> > + clock-names = "xclk";
> > + clock-frequency = <23880000>;
> > +
> > + vdddo-supply = <&camera_vdddo_1v8>;
> > + vdda-supply = <&camera_vdda_2v8>;
> > + vddd-supply = <&camera_vddd_1v5>;
> > +
> > + status = "ok";
> > +
> > + port {
> > + ov5640_ep: endpoint {
> > + clock-lanes = <1>;
> > + data-lanes = <0 2>;
> > + remote-endpoint = <&csiphy0_ep>;
> > + };
> > + };
> > + };
> > +};
> > --
> > 2.25.1
> >
^ permalink raw reply
* [PATCH v2 4/4] mtd: rawnand: ingenic: Convert the driver to exec_op()
From: Boris Brezillon @ 2020-05-19 23:24 UTC (permalink / raw)
To: Paul Cercueil, Harvey Hunt, Miquel Raynal, linux-mtd
Cc: Rob Herring, Mark Rutland, devicetree, Richard Weinberger,
Vignesh Raghavendra, Tudor Ambarus, Boris Brezillon
In-Reply-To: <20200519232454.374081-1-boris.brezillon@collabora.com>
Let's convert the driver to exec_op() to have one less driver relying
on the legacy interface.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
---
Changes in v2:
* Add a delay after instructions when needed
* s/cmd_offset/addr_offset/
Paul, I didn't add your T-b since this new version follows the path
you proposed for the R/B polarity inversion issue. Feel free to add
it back if it still works.
---
.../mtd/nand/raw/ingenic/ingenic_nand_drv.c | 139 +++++++++++-------
1 file changed, 83 insertions(+), 56 deletions(-)
diff --git a/drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c b/drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c
index e939404e1383..3659e62829f9 100644
--- a/drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c
+++ b/drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c
@@ -27,9 +27,6 @@
#define DRV_NAME "ingenic-nand"
-/* Command delay when there is no R/B pin. */
-#define RB_DELAY_US 100
-
struct jz_soc_info {
unsigned long data_offset;
unsigned long addr_offset;
@@ -49,7 +46,6 @@ struct ingenic_nfc {
struct nand_controller controller;
unsigned int num_banks;
struct list_head chips;
- int selected;
struct ingenic_nand_cs cs[];
};
@@ -142,51 +138,6 @@ static const struct mtd_ooblayout_ops jz4725b_ooblayout_ops = {
.free = jz4725b_ooblayout_free,
};
-static void ingenic_nand_select_chip(struct nand_chip *chip, int chipnr)
-{
- struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
- struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
- struct ingenic_nand_cs *cs;
-
- /* Ensure the currently selected chip is deasserted. */
- if (chipnr == -1 && nfc->selected >= 0) {
- cs = &nfc->cs[nfc->selected];
- jz4780_nemc_assert(nfc->dev, cs->bank, false);
- }
-
- nfc->selected = chipnr;
-}
-
-static void ingenic_nand_cmd_ctrl(struct nand_chip *chip, int cmd,
- unsigned int ctrl)
-{
- struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
- struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
- struct ingenic_nand_cs *cs;
-
- if (WARN_ON(nfc->selected < 0))
- return;
-
- cs = &nfc->cs[nfc->selected];
-
- jz4780_nemc_assert(nfc->dev, cs->bank, ctrl & NAND_NCE);
-
- if (cmd == NAND_CMD_NONE)
- return;
-
- if (ctrl & NAND_ALE)
- writeb(cmd, cs->base + nfc->soc_info->addr_offset);
- else if (ctrl & NAND_CLE)
- writeb(cmd, cs->base + nfc->soc_info->cmd_offset);
-}
-
-static int ingenic_nand_dev_ready(struct nand_chip *chip)
-{
- struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
-
- return gpiod_get_value_cansleep(nand->busy_gpio);
-}
-
static void ingenic_nand_ecc_hwctl(struct nand_chip *chip, int mode)
{
struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
@@ -298,8 +249,91 @@ static int ingenic_nand_attach_chip(struct nand_chip *chip)
return 0;
}
+static int ingenic_nand_exec_instr(struct nand_chip *chip,
+ struct ingenic_nand_cs *cs,
+ const struct nand_op_instr *instr)
+{
+ struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
+ struct ingenic_nfc *nfc = to_ingenic_nfc(chip->controller);
+ unsigned int i;
+
+ switch (instr->type) {
+ case NAND_OP_CMD_INSTR:
+ writeb(instr->ctx.cmd.opcode,
+ cs->base + nfc->soc_info->cmd_offset);
+ return 0;
+ case NAND_OP_ADDR_INSTR:
+ for (i = 0; i < instr->ctx.addr.naddrs; i++)
+ writeb(instr->ctx.addr.addrs[i],
+ cs->base + nfc->soc_info->addr_offset);
+ return 0;
+ case NAND_OP_DATA_IN_INSTR:
+ if (instr->ctx.data.force_8bit ||
+ !(chip->options & NAND_BUSWIDTH_16))
+ ioread8_rep(cs->base + nfc->soc_info->data_offset,
+ instr->ctx.data.buf.in,
+ instr->ctx.data.len);
+ else
+ ioread16_rep(cs->base + nfc->soc_info->data_offset,
+ instr->ctx.data.buf.in,
+ instr->ctx.data.len);
+ return 0;
+ case NAND_OP_DATA_OUT_INSTR:
+ if (instr->ctx.data.force_8bit ||
+ !(chip->options & NAND_BUSWIDTH_16))
+ iowrite8_rep(cs->base + nfc->soc_info->data_offset,
+ instr->ctx.data.buf.out,
+ instr->ctx.data.len);
+ else
+ iowrite16_rep(cs->base + nfc->soc_info->data_offset,
+ instr->ctx.data.buf.out,
+ instr->ctx.data.len);
+ return 0;
+ case NAND_OP_WAITRDY_INSTR:
+ if (!nand->busy_gpio)
+ return nand_soft_waitrdy(chip,
+ instr->ctx.waitrdy.timeout_ms);
+
+ return nand_gpio_waitrdy(chip, nand->busy_gpio,
+ instr->ctx.waitrdy.timeout_ms);
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static int ingenic_nand_exec_op(struct nand_chip *chip,
+ const struct nand_operation *op,
+ bool check_only)
+{
+ struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
+ struct ingenic_nfc *nfc = to_ingenic_nfc(nand->chip.controller);
+ struct ingenic_nand_cs *cs;
+ unsigned int i;
+ int ret = 0;
+
+ if (check_only)
+ return 0;
+
+ cs = &nfc->cs[op->cs];
+ jz4780_nemc_assert(nfc->dev, cs->bank, true);
+ for (i = 0; i < op->ninstrs; i++) {
+ ret = ingenic_nand_exec_instr(chip, cs, &op->instrs[i]);
+ if (ret)
+ break;
+
+ if (op->instrs[i].delay_ns)
+ ndelay(op->instrs[i].delay_ns);
+ }
+ jz4780_nemc_assert(nfc->dev, cs->bank, false);
+
+ return ret;
+}
+
static const struct nand_controller_ops ingenic_nand_controller_ops = {
.attach_chip = ingenic_nand_attach_chip,
+ .exec_op = ingenic_nand_exec_op,
};
static int ingenic_nand_init_chip(struct platform_device *pdev,
@@ -339,8 +373,6 @@ static int ingenic_nand_init_chip(struct platform_device *pdev,
ret = PTR_ERR(nand->busy_gpio);
dev_err(dev, "failed to request busy GPIO: %d\n", ret);
return ret;
- } else if (nand->busy_gpio) {
- nand->chip.legacy.dev_ready = ingenic_nand_dev_ready;
}
/*
@@ -371,12 +403,7 @@ static int ingenic_nand_init_chip(struct platform_device *pdev,
return -ENOMEM;
mtd->dev.parent = dev;
- chip->legacy.IO_ADDR_R = cs->base + nfc->soc_info->data_offset;
- chip->legacy.IO_ADDR_W = cs->base + nfc->soc_info->data_offset;
- chip->legacy.chip_delay = RB_DELAY_US;
chip->options = NAND_NO_SUBPAGE_WRITE;
- chip->legacy.select_chip = ingenic_nand_select_chip;
- chip->legacy.cmd_ctrl = ingenic_nand_cmd_ctrl;
chip->ecc.mode = NAND_ECC_HW;
chip->controller = &nfc->controller;
nand_set_flash_node(chip, np);
--
2.25.4
^ permalink raw reply related
* [PATCH v2 1/4] dt-bindings: mtd: rawnand: ingenic: Clarify the active state of the RB pin
From: Boris Brezillon @ 2020-05-19 23:24 UTC (permalink / raw)
To: Paul Cercueil, Harvey Hunt, Miquel Raynal, linux-mtd
Cc: Rob Herring, Mark Rutland, devicetree, Richard Weinberger,
Vignesh Raghavendra, Tudor Ambarus, Boris Brezillon
Let's make things consistent with other bindings and clarify the
expected active state.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
---
Changes in v2:
* New patch
---
Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt b/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
index c02259353327..4cbe13f94564 100644
--- a/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
+++ b/Documentation/devicetree/bindings/mtd/ingenic,jz4780-nand.txt
@@ -30,7 +30,8 @@ Optional children node properties:
- nand-ecc-strength: ECC strength (max number of correctable bits).
- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by default
- nand-on-flash-bbt: boolean to enable on flash bbt option, if not present false
-- rb-gpios: GPIO specifier for the busy pin.
+- rb-gpios: GPIO specifier for the ready/busy pin. The active state (ready)
+ should be high unless the signal is inverted.
- wp-gpios: GPIO specifier for the write protect pin.
Optional child node of NAND chip nodes:
--
2.25.4
^ permalink raw reply related
* [PATCH v2 3/4] mtd: rawnand: ingenic: Fix the RB gpio active-high property on qi,lb60
From: Boris Brezillon @ 2020-05-19 23:24 UTC (permalink / raw)
To: Paul Cercueil, Harvey Hunt, Miquel Raynal, linux-mtd
Cc: Rob Herring, Mark Rutland, devicetree, Richard Weinberger,
Vignesh Raghavendra, Tudor Ambarus, Boris Brezillon
In-Reply-To: <20200519232454.374081-1-boris.brezillon@collabora.com>
The rb-gpios semantics was undocumented and qi,lb60 (along with the
ingenic driver) got it wrong. The active state encodes the NAND ready
state, which is high level. Since there's no signal inverter on this
board, it should be active-high. Let's fix that here for older DTs so
we can re-use the generic nand_gpio_waitrdy() helper, and be consistent
with what other drivers do.
Suggested-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
---
Changes in v2:
* New patch
---
drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c b/drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c
index e7bd845fdbf5..e939404e1383 100644
--- a/drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c
+++ b/drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c
@@ -184,7 +184,7 @@ static int ingenic_nand_dev_ready(struct nand_chip *chip)
{
struct ingenic_nand *nand = to_ingenic_nand(nand_to_mtd(chip));
- return !gpiod_get_value_cansleep(nand->busy_gpio);
+ return gpiod_get_value_cansleep(nand->busy_gpio);
}
static void ingenic_nand_ecc_hwctl(struct nand_chip *chip, int mode)
@@ -343,6 +343,18 @@ static int ingenic_nand_init_chip(struct platform_device *pdev,
nand->chip.legacy.dev_ready = ingenic_nand_dev_ready;
}
+ /*
+ * The rb-gpios semantics was undocumented and qi,lb60 (along with
+ * the ingenic driver) got it wrong. The active state encodes the
+ * NAND ready state, which is high level. Since there's no signal
+ * inverter on this board, it should be active-high. Let's fix that
+ * here for older DTs so we can re-use the generic nand_gpio_waitrdy()
+ * helper, and be consistent with what other drivers do.
+ */
+ if (of_machine_is_compatible("qi,lb60") &&
+ gpiod_is_active_low(nand->busy_gpio))
+ gpiod_toggle_active_low(nand->busy_gpio);
+
nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
if (IS_ERR(nand->wp_gpio)) {
--
2.25.4
^ permalink raw reply related
* [PATCH v2 2/4] dt-bindings: mtd: nand: Document the generic rb-gpios property
From: Boris Brezillon @ 2020-05-19 23:24 UTC (permalink / raw)
To: Paul Cercueil, Harvey Hunt, Miquel Raynal, linux-mtd
Cc: Rob Herring, Mark Rutland, devicetree, Richard Weinberger,
Vignesh Raghavendra, Tudor Ambarus, Boris Brezillon
In-Reply-To: <20200519232454.374081-1-boris.brezillon@collabora.com>
A few drivers use this property to describe GPIO pins used to sample
the NAND Ready/Busy state. Let's make it part of the generic binding
doc.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
---
Changes in v2:
* New patch
---
Documentation/devicetree/bindings/mtd/nand-controller.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
index d261b7096c69..17f4dc8f8cab 100644
--- a/Documentation/devicetree/bindings/mtd/nand-controller.yaml
+++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
@@ -119,6 +119,13 @@ patternProperties:
description:
Contains the native Ready/Busy IDs.
+ rb-gpios:
+ description:
+ Contains one or more GPIO descriptor (the numper of descriptor
+ depends on the number of R/B pins exposed by the flash) for the
+ Ready/Busy pins. Active state refers to the NAND ready state and
+ should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
+
required:
- reg
--
2.25.4
^ permalink raw reply related
* Re: [PATCH v5 3/5] remoteproc: qcom: Update PIL relocation info on load
From: Bjorn Andersson @ 2020-05-19 23:07 UTC (permalink / raw)
To: rishabhb
Cc: Andy Gross, Ohad Ben-Cohen, Rob Herring, linux-arm-msm,
linux-remoteproc, devicetree, linux-kernel,
linux-remoteproc-owner
In-Reply-To: <3ff29ccc94d3097fb39b7df377754af6@codeaurora.org>
On Tue 19 May 11:14 PDT 2020, rishabhb@codeaurora.org wrote:
> On 2020-05-12 22:56, Bjorn Andersson wrote:
> > Update the PIL relocation information in IMEM with information about
> > where the firmware for various remoteprocs are loaded.
> >
> > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> > ---
> >
> > Changes since v4:
> > - Dropped unnecessary comment about ignoring return value.
> >
> > drivers/remoteproc/Kconfig | 3 +++
> > drivers/remoteproc/qcom_q6v5_adsp.c | 16 +++++++++++++---
> > drivers/remoteproc/qcom_q6v5_mss.c | 3 +++
> > drivers/remoteproc/qcom_q6v5_pas.c | 15 ++++++++++++---
> > drivers/remoteproc/qcom_q6v5_wcss.c | 14 +++++++++++---
> > drivers/remoteproc/qcom_wcnss.c | 14 +++++++++++---
> > 6 files changed, 53 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
> > index 8088ca4dd6dc..6bd42a411ca8 100644
> > --- a/drivers/remoteproc/Kconfig
> > +++ b/drivers/remoteproc/Kconfig
> > @@ -126,6 +126,7 @@ config QCOM_Q6V5_ADSP
> > depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
> > depends on QCOM_SYSMON || QCOM_SYSMON=n
> > select MFD_SYSCON
> > + select QCOM_PIL_INFO
> > select QCOM_MDT_LOADER
> > select QCOM_Q6V5_COMMON
> > select QCOM_RPROC_COMMON
> > @@ -158,6 +159,7 @@ config QCOM_Q6V5_PAS
> > depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
> > depends on QCOM_SYSMON || QCOM_SYSMON=n
> > select MFD_SYSCON
> > + select QCOM_PIL_INFO
> > select QCOM_MDT_LOADER
> > select QCOM_Q6V5_COMMON
> > select QCOM_RPROC_COMMON
> > @@ -209,6 +211,7 @@ config QCOM_WCNSS_PIL
> > depends on QCOM_SMEM
> > depends on QCOM_SYSMON || QCOM_SYSMON=n
> > select QCOM_MDT_LOADER
> > + select QCOM_PIL_INFO
> > select QCOM_RPROC_COMMON
> > select QCOM_SCM
> > help
> > diff --git a/drivers/remoteproc/qcom_q6v5_adsp.c
> > b/drivers/remoteproc/qcom_q6v5_adsp.c
> > index d2a2574dcf35..c539e89664cb 100644
> > --- a/drivers/remoteproc/qcom_q6v5_adsp.c
> > +++ b/drivers/remoteproc/qcom_q6v5_adsp.c
> > @@ -26,6 +26,7 @@
> > #include <linux/soc/qcom/smem_state.h>
> >
> > #include "qcom_common.h"
> > +#include "qcom_pil_info.h"
> > #include "qcom_q6v5.h"
> > #include "remoteproc_internal.h"
> >
> > @@ -82,6 +83,7 @@ struct qcom_adsp {
> > unsigned int halt_lpass;
> >
> > int crash_reason_smem;
> > + const char *info_name;
> >
> > struct completion start_done;
> > struct completion stop_done;
> > @@ -164,10 +166,17 @@ static int qcom_adsp_shutdown(struct qcom_adsp
> > *adsp)
> > static int adsp_load(struct rproc *rproc, const struct firmware *fw)
> > {
> > struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
> > + int ret;
> > +
> > + ret = qcom_mdt_load_no_init(adsp->dev, fw, rproc->firmware, 0,
> > + adsp->mem_region, adsp->mem_phys,
> > + adsp->mem_size, &adsp->mem_reloc);
> > + if (ret)
> > + return ret;
> > +
> > + qcom_pil_info_store(adsp->info_name, adsp->mem_reloc, adsp->mem_size);
> >
> > - return qcom_mdt_load_no_init(adsp->dev, fw, rproc->firmware, 0,
> > - adsp->mem_region, adsp->mem_phys, adsp->mem_size,
> > - &adsp->mem_reloc);
> > + return 0;
> > }
> >
> > static int adsp_start(struct rproc *rproc)
> > @@ -436,6 +445,7 @@ static int adsp_probe(struct platform_device *pdev)
> > adsp = (struct qcom_adsp *)rproc->priv;
> > adsp->dev = &pdev->dev;
> > adsp->rproc = rproc;
> > + adsp->info_name = desc->sysmon_name;
> > platform_set_drvdata(pdev, adsp);
> >
> > ret = adsp_alloc_memory_region(adsp);
> > diff --git a/drivers/remoteproc/qcom_q6v5_mss.c
> > b/drivers/remoteproc/qcom_q6v5_mss.c
> > index c4936f4d1e80..fdbcae11ae64 100644
> > --- a/drivers/remoteproc/qcom_q6v5_mss.c
> > +++ b/drivers/remoteproc/qcom_q6v5_mss.c
> > @@ -29,6 +29,7 @@
> >
> > #include "remoteproc_internal.h"
> > #include "qcom_common.h"
> > +#include "qcom_pil_info.h"
> > #include "qcom_q6v5.h"
> >
> > #include <linux/qcom_scm.h>
> > @@ -1221,6 +1222,8 @@ static int q6v5_mpss_load(struct q6v5 *qproc)
> > else if (ret < 0)
> > dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
> >
> > + qcom_pil_info_store("modem", mpss_reloc, qproc->mpss_size);
> > +
> > release_firmware:
> > release_firmware(fw);
> > out:
> > diff --git a/drivers/remoteproc/qcom_q6v5_pas.c
> > b/drivers/remoteproc/qcom_q6v5_pas.c
> > index 3bb69f58e086..84cb19231c35 100644
> > --- a/drivers/remoteproc/qcom_q6v5_pas.c
> > +++ b/drivers/remoteproc/qcom_q6v5_pas.c
> > @@ -25,6 +25,7 @@
> > #include <linux/soc/qcom/smem_state.h>
> >
> > #include "qcom_common.h"
> > +#include "qcom_pil_info.h"
> > #include "qcom_q6v5.h"
> > #include "remoteproc_internal.h"
> >
> > @@ -64,6 +65,7 @@ struct qcom_adsp {
> > int pas_id;
> > int crash_reason_smem;
> > bool has_aggre2_clk;
> > + const char *info_name;
> >
> > struct completion start_done;
> > struct completion stop_done;
> > @@ -117,11 +119,17 @@ static void adsp_pds_disable(struct qcom_adsp
> > *adsp, struct device **pds,
> > static int adsp_load(struct rproc *rproc, const struct firmware *fw)
> > {
> > struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
> > + int ret;
> >
> > - return qcom_mdt_load(adsp->dev, fw, rproc->firmware, adsp->pas_id,
> > - adsp->mem_region, adsp->mem_phys, adsp->mem_size,
> > - &adsp->mem_reloc);
> > + ret = qcom_mdt_load(adsp->dev, fw, rproc->firmware, adsp->pas_id,
> > + adsp->mem_region, adsp->mem_phys, adsp->mem_size,
> > + &adsp->mem_reloc);
> > + if (ret)
> > + return ret;
> >
> > + qcom_pil_info_store(adsp->info_name, adsp->mem_reloc, adsp->mem_size);
> mem_reloc is used to calculate offset and then we again add that offset to
> the
> ioremapped region base. So we should pass adsp->mem_phys as start here?
You're correct, I will respin this.
Thanks,
Bjorn
^ permalink raw reply
* Re: [PATCH v4 0/4] meson-ee-pwrc: support for Meson8/8b/8m2 and GX
From: Kevin Hilman @ 2020-05-19 23:07 UTC (permalink / raw)
To: Martin Blumenstingl, linux-amlogic
Cc: robh+dt, narmstrong, devicetree, linux-arm-kernel, linux-kernel,
Martin Blumenstingl
In-Reply-To: <20200515204709.1505498-1-martin.blumenstingl@googlemail.com>
Martin Blumenstingl <martin.blumenstingl@googlemail.com> writes:
> This series adds support for all "older" SoCs to the meson-ee-pwrc
> driver. I wanted to compare as much as I could between my Meson8b EC-100
> (Endless Mini) and the Le Potato board so I added support for GXBB, GXL
> and GXM as well as for the SoCs that I'm actually working on. I will
> send the ARM64 dts patches once all of this is reviewed and merged.
>
> I successfully tested the Meson8b part on EC-100 where u-boot does not
> initialize the VPU controller. So this the board where I have been
> struggling most.
>
> Kevin, I'm not sure if this can still make it into v5.8. If the
> series as a whole can't make it for some reason then I'd appreciate if
> patches #1 and #2 could end in v5.8 so I can push the .dts patches for
> v5.9.
Queuing for v5.8,
Thanks Martin!
Kevin
^ permalink raw reply
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