* [PATCH v15 08/11] soc: mediatek: Add MT8183 scpsys support
From: Weiyi Lu @ 2020-05-21 9:06 UTC (permalink / raw)
To: Enric Balletbo Serra, Matthias Brugger, Nicolas Boichat,
Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel, devicetree,
linux-mediatek, srv_heupstream, Weiyi Lu
In-Reply-To: <1590051985-29149-1-git-send-email-weiyi.lu@mediatek.com>
Add scpsys driver for MT8183
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
---
drivers/soc/mediatek/mtk-scpsys.c | 249 ++++++++++++++++++++++++++++++++++++++
1 file changed, 249 insertions(+)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index ef46e31..ae03127 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -19,6 +19,7 @@
#include <dt-bindings/power/mt7622-power.h>
#include <dt-bindings/power/mt7623a-power.h>
#include <dt-bindings/power/mt8173-power.h>
+#include <dt-bindings/power/mt8183-power.h>
#define MTK_POLL_DELAY_US 10
#define MTK_POLL_TIMEOUT USEC_PER_SEC
@@ -99,6 +100,34 @@
#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
+#define MT8183_TOP_AXI_PROT_EN_DISP (BIT(10) | BIT(11))
+#define MT8183_TOP_AXI_PROT_EN_CONN (BIT(13) | BIT(14))
+#define MT8183_TOP_AXI_PROT_EN_MFG (BIT(21) | BIT(22))
+#define MT8183_TOP_AXI_PROT_EN_CAM BIT(28)
+#define MT8183_TOP_AXI_PROT_EN_VPU_TOP BIT(27)
+#define MT8183_TOP_AXI_PROT_EN_1_DISP (BIT(16) | BIT(17))
+#define MT8183_TOP_AXI_PROT_EN_1_MFG GENMASK(21, 19)
+#define MT8183_TOP_AXI_PROT_EN_MM_ISP (BIT(3) | BIT(8))
+#define MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND BIT(10)
+#define MT8183_TOP_AXI_PROT_EN_MM_CAM (BIT(4) | BIT(5) | \
+ BIT(9) | BIT(13))
+#define MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP (GENMASK(9, 6) | \
+ BIT(12))
+#define MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND (BIT(10) | BIT(11))
+#define MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND BIT(11)
+#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND (BIT(0) | BIT(2) | \
+ BIT(4))
+#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND (BIT(1) | BIT(3) | \
+ BIT(5))
+#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0 BIT(6)
+#define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1 BIT(7)
+#define MT8183_SMI_COMMON_SMI_CLAMP_DISP GENMASK(7, 0)
+#define MT8183_SMI_COMMON_SMI_CLAMP_VENC BIT(1)
+#define MT8183_SMI_COMMON_SMI_CLAMP_ISP BIT(2)
+#define MT8183_SMI_COMMON_SMI_CLAMP_CAM (BIT(3) | BIT(4))
+#define MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP (BIT(5) | BIT(6))
+#define MT8183_SMI_COMMON_SMI_CLAMP_VDEC BIT(7)
+
#define MAX_CLKS 3
#define MAX_SUBSYS_CLKS 10
@@ -1190,6 +1219,212 @@ static void mtk_register_power_domains(struct platform_device *pdev,
{MT8173_POWER_DOMAIN_MFG_2D, MT8173_POWER_DOMAIN_MFG},
};
+/*
+ * MT8183 power domain support
+ */
+
+static const struct scp_domain_data scp_domain_data_mt8183[] = {
+ [MT8183_POWER_DOMAIN_AUDIO] = {
+ .name = "audio",
+ .sta_mask = PWR_STATUS_AUDIO,
+ .ctl_offs = 0x0314,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .basic_clk_name = {"audio", "audio1", "audio2"},
+ },
+ [MT8183_POWER_DOMAIN_CONN] = {
+ .name = "conn",
+ .sta_mask = PWR_STATUS_CONN,
+ .ctl_offs = 0x032c,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ MT8183_TOP_AXI_PROT_EN_CONN),
+ },
+ },
+ [MT8183_POWER_DOMAIN_MFG_ASYNC] = {
+ .name = "mfg_async",
+ .sta_mask = PWR_STATUS_MFG_ASYNC,
+ .ctl_offs = 0x0334,
+ .sram_pdn_bits = 0,
+ .sram_pdn_ack_bits = 0,
+ .basic_clk_name = {"mfg"},
+ },
+ [MT8183_POWER_DOMAIN_MFG] = {
+ .name = "mfg",
+ .sta_mask = PWR_STATUS_MFG,
+ .ctl_offs = 0x0338,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8183_POWER_DOMAIN_MFG_CORE0] = {
+ .name = "mfg_core0",
+ .sta_mask = BIT(7),
+ .ctl_offs = 0x034c,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8183_POWER_DOMAIN_MFG_CORE1] = {
+ .name = "mfg_core1",
+ .sta_mask = BIT(20),
+ .ctl_offs = 0x0310,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ },
+ [MT8183_POWER_DOMAIN_MFG_2D] = {
+ .name = "mfg_2d",
+ .sta_mask = PWR_STATUS_MFG_2D,
+ .ctl_offs = 0x0348,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0, 0x258,
+ MT8183_TOP_AXI_PROT_EN_1_MFG),
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ MT8183_TOP_AXI_PROT_EN_MFG),
+ },
+ },
+ [MT8183_POWER_DOMAIN_DISP] = {
+ .name = "disp",
+ .sta_mask = PWR_STATUS_DISP,
+ .ctl_offs = 0x030c,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .basic_clk_name = {"mm"},
+ .subsys_clk_prefix = "mm",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2a8, 0x2ac, 0, 0x258,
+ MT8183_TOP_AXI_PROT_EN_1_DISP),
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ MT8183_TOP_AXI_PROT_EN_DISP),
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ MT8183_SMI_COMMON_SMI_CLAMP_DISP),
+ },
+ },
+ [MT8183_POWER_DOMAIN_CAM] = {
+ .name = "cam",
+ .sta_mask = BIT(25),
+ .ctl_offs = 0x0344,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .basic_clk_name = {"cam"},
+ .subsys_clk_prefix = "cam",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ MT8183_TOP_AXI_PROT_EN_MM_CAM),
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ MT8183_TOP_AXI_PROT_EN_CAM),
+ BUS_PROT_IGN(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND),
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ MT8183_SMI_COMMON_SMI_CLAMP_CAM),
+ },
+ },
+ [MT8183_POWER_DOMAIN_ISP] = {
+ .name = "isp",
+ .sta_mask = PWR_STATUS_ISP,
+ .ctl_offs = 0x0308,
+ .sram_pdn_bits = GENMASK(9, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .basic_clk_name = {"isp"},
+ .subsys_clk_prefix = "isp",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ MT8183_TOP_AXI_PROT_EN_MM_ISP),
+ BUS_PROT_IGN(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND),
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ MT8183_SMI_COMMON_SMI_CLAMP_ISP),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VDEC] = {
+ .name = "vdec",
+ .sta_mask = BIT(31),
+ .ctl_offs = 0x0300,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .bp_table = {
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ MT8183_SMI_COMMON_SMI_CLAMP_VDEC),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VENC] = {
+ .name = "venc",
+ .sta_mask = PWR_STATUS_VENC,
+ .ctl_offs = 0x0304,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(15, 12),
+ .bp_table = {
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ MT8183_SMI_COMMON_SMI_CLAMP_VENC),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VPU_TOP] = {
+ .name = "vpu_top",
+ .sta_mask = BIT(26),
+ .ctl_offs = 0x0324,
+ .sram_pdn_bits = GENMASK(8, 8),
+ .sram_pdn_ack_bits = GENMASK(12, 12),
+ .basic_clk_name = {"vpu", "vpu1"},
+ .subsys_clk_prefix = "vpu",
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP),
+ BUS_PROT(IFR_TYPE, 0x2a0, 0x2a4, 0, 0x228,
+ MT8183_TOP_AXI_PROT_EN_VPU_TOP),
+ BUS_PROT(IFR_TYPE, 0x2d4, 0x2d8, 0, 0x2ec,
+ MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND),
+ BUS_PROT(SMI_TYPE, 0x3c4, 0x3c8, 0, 0x3c0,
+ MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP),
+ },
+ },
+ [MT8183_POWER_DOMAIN_VPU_CORE0] = {
+ .name = "vpu_core0",
+ .sta_mask = BIT(27),
+ .ctl_offs = 0x33c,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .basic_clk_name = {"vpu2"},
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
+ MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0),
+ BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
+ MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND),
+ },
+ .caps = MTK_SCPD_SRAM_ISO,
+ },
+ [MT8183_POWER_DOMAIN_VPU_CORE1] = {
+ .name = "vpu_core1",
+ .sta_mask = BIT(28),
+ .ctl_offs = 0x0340,
+ .sram_pdn_bits = GENMASK(11, 8),
+ .sram_pdn_ack_bits = GENMASK(13, 12),
+ .basic_clk_name = {"vpu3"},
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
+ MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1),
+ BUS_PROT(IFR_TYPE, 0x2c4, 0x2c8, 0, 0x2e4,
+ MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND),
+ },
+ .caps = MTK_SCPD_SRAM_ISO,
+ },
+};
+
+static const struct scp_subdomain scp_subdomain_mt8183[] = {
+ {MT8183_POWER_DOMAIN_MFG_ASYNC, MT8183_POWER_DOMAIN_MFG},
+ {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_2D},
+ {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE0},
+ {MT8183_POWER_DOMAIN_MFG, MT8183_POWER_DOMAIN_MFG_CORE1},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_CAM},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_ISP},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VDEC},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VENC},
+ {MT8183_POWER_DOMAIN_DISP, MT8183_POWER_DOMAIN_VPU_TOP},
+ {MT8183_POWER_DOMAIN_VPU_TOP, MT8183_POWER_DOMAIN_VPU_CORE0},
+ {MT8183_POWER_DOMAIN_VPU_TOP, MT8183_POWER_DOMAIN_VPU_CORE1},
+};
+
static const struct scp_soc_data mt2701_data = {
.domains = scp_domain_data_mt2701,
.num_domains = ARRAY_SIZE(scp_domain_data_mt2701),
@@ -1250,6 +1485,17 @@ static void mtk_register_power_domains(struct platform_device *pdev,
},
};
+static const struct scp_soc_data mt8183_data = {
+ .domains = scp_domain_data_mt8183,
+ .num_domains = ARRAY_SIZE(scp_domain_data_mt8183),
+ .subdomains = scp_subdomain_mt8183,
+ .num_subdomains = ARRAY_SIZE(scp_subdomain_mt8183),
+ .regs = {
+ .pwr_sta_offs = 0x0180,
+ .pwr_sta2nd_offs = 0x0184
+ }
+};
+
/*
* scpsys driver init
*/
@@ -1274,6 +1520,9 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.compatible = "mediatek,mt8173-scpsys",
.data = &mt8173_data,
}, {
+ .compatible = "mediatek,mt8183-scpsys",
+ .data = &mt8183_data,
+ }, {
/* sentinel */
}
};
--
1.8.1.1.dirty
^ permalink raw reply related
* [PATCH v15 06/11] soc: mediatek: Add subsys clock control for bus protection
From: Weiyi Lu @ 2020-05-21 9:06 UTC (permalink / raw)
To: Enric Balletbo Serra, Matthias Brugger, Nicolas Boichat,
Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel, devicetree,
linux-mediatek, srv_heupstream, Weiyi Lu
In-Reply-To: <1590051985-29149-1-git-send-email-weiyi.lu@mediatek.com>
For the bus protection operations, some subsys clocks need to be enabled
before releasing the protection, and vice versa.
But those subsys clocks could only be controlled once its corresponding
power domain is turned on first.
In this patch, we add the subsys clock control into its relevant steps.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 62 +++++++++++++++++++++++++++++++++++++--
1 file changed, 60 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index 59a525a..ef2c668 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -97,6 +97,7 @@
#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
#define MAX_CLKS 3
+#define MAX_SUBSYS_CLKS 10
#define MAX_STEPS 4
@@ -145,6 +146,8 @@ struct bus_prot {
* @sram_pdn_bits: The mask for sram power control bits.
* @sram_pdn_ack_bits: The mask for sram power control acked bits.
* @basic_clk_name: The basic clocks required by this power domain.
+ * @subsys_clk_prefix: The prefix name of the clocks need to be enabled
+ * before releasing bus protection.
* @caps: The flag for active wake-up action.
* @bp_table: The mask table for multiple step bus protection.
*/
@@ -155,6 +158,7 @@ struct scp_domain_data {
u32 sram_pdn_bits;
u32 sram_pdn_ack_bits;
const char *basic_clk_name[MAX_CLKS];
+ const char *subsys_clk_prefix;
u8 caps;
struct bus_prot bp_table[MAX_STEPS];
};
@@ -165,6 +169,7 @@ struct scp_domain {
struct generic_pm_domain genpd;
struct scp *scp;
struct clk *clk[MAX_CLKS];
+ struct clk *subsys_clk[MAX_SUBSYS_CLKS];
const struct scp_domain_data *data;
struct regulator *supply;
};
@@ -425,16 +430,22 @@ static int scpsys_power_on(struct generic_pm_domain *genpd)
val |= PWR_RST_B_BIT;
writel(val, ctl_addr);
- ret = scpsys_sram_enable(scpd, ctl_addr);
+ ret = scpsys_clk_enable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
if (ret < 0)
goto err_pwr_ack;
+ ret = scpsys_sram_enable(scpd, ctl_addr);
+ if (ret < 0)
+ goto err_sram;
+
ret = scpsys_bus_protect_disable(scpd);
if (ret < 0)
- goto err_pwr_ack;
+ goto err_sram;
return 0;
+err_sram:
+ scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
err_pwr_ack:
scpsys_clk_disable(scpd->clk, MAX_CLKS);
err_clk:
@@ -461,6 +472,8 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
if (ret < 0)
goto out;
+ scpsys_clk_disable(scpd->subsys_clk, MAX_SUBSYS_CLKS);
+
/* subsys power off */
val = readl(ctl_addr);
val |= PWR_ISO_BIT;
@@ -498,6 +511,39 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
return ret;
}
+static int init_subsys_clks(struct platform_device *pdev,
+ const char *prefix, struct clk **clk)
+{
+ struct device_node *node = pdev->dev.of_node;
+ u32 prefix_len, sub_clk_cnt = 0;
+ struct property *prop;
+ const char *clk_name;
+
+ prefix_len = strlen(prefix);
+
+ of_property_for_each_string(node, "clock-names", prop, clk_name) {
+ if (!strncmp(clk_name, prefix, prefix_len) &&
+ (clk_name[prefix_len] == '-')) {
+ if (sub_clk_cnt >= MAX_SUBSYS_CLKS) {
+ dev_err(&pdev->dev,
+ "subsys clk out of range %d\n",
+ sub_clk_cnt);
+ return -EINVAL;
+ }
+
+ clk[sub_clk_cnt] = devm_clk_get(&pdev->dev,
+ clk_name);
+
+ if (IS_ERR(clk[sub_clk_cnt]))
+ return PTR_ERR(clk[sub_clk_cnt]);
+
+ sub_clk_cnt++;
+ }
+ }
+
+ return sub_clk_cnt;
+}
+
static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
const char * const *name)
{
@@ -596,6 +642,18 @@ static struct scp *init_scp(struct platform_device *pdev,
if (ret)
return ERR_PTR(ret);
+ if (data->subsys_clk_prefix) {
+ ret = init_subsys_clks(pdev,
+ data->subsys_clk_prefix,
+ scpd->subsys_clk);
+ if (ret < 0) {
+ dev_err(&pdev->dev,
+ "%s: subsys clk unavailable\n",
+ data->name);
+ return ERR_PTR(ret);
+ }
+ }
+
genpd->name = data->name;
genpd->power_off = scpsys_power_off;
genpd->power_on = scpsys_power_on;
--
1.8.1.1.dirty
^ permalink raw reply related
* [PATCH v15 05/11] soc: mediatek: Add multiple step bus protection control
From: Weiyi Lu @ 2020-05-21 9:06 UTC (permalink / raw)
To: Enric Balletbo Serra, Matthias Brugger, Nicolas Boichat,
Rob Herring, Sascha Hauer
Cc: James Liao, Fan Chen, linux-arm-kernel, linux-kernel, devicetree,
linux-mediatek, srv_heupstream, Weiyi Lu
In-Reply-To: <1590051985-29149-1-git-send-email-weiyi.lu@mediatek.com>
Both MT8183 & MT6765 have more control steps of bus protection
than previous project. And there add more bus protection registers
reside at infracfg & smi-common.
Extend function to support multiple step bus protection control
with more customized arguments.
And then use bp_table for bus protection of all compatibles,
instead of mixing bus_prot_mask and bus_prot_reg_update.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
drivers/soc/mediatek/mtk-scpsys.c | 235 +++++++++++++++++++++++++++-----------
1 file changed, 168 insertions(+), 67 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
index b603af7..59a525a 100644
--- a/drivers/soc/mediatek/mtk-scpsys.c
+++ b/drivers/soc/mediatek/mtk-scpsys.c
@@ -78,11 +78,6 @@
#define PWR_STATUS_HIF1 BIT(26) /* MT7622 */
#define PWR_STATUS_WB BIT(27) /* MT7622 */
-#define INFRA_TOPAXI_PROTECTEN 0x0220
-#define INFRA_TOPAXI_PROTECTSTA1 0x0228
-#define INFRA_TOPAXI_PROTECTEN_SET 0x0260
-#define INFRA_TOPAXI_PROTECTEN_CLR 0x0264
-
#define MT2701_TOP_AXI_PROT_EN_MM_M0 BIT(1)
#define MT2701_TOP_AXI_PROT_EN_CONN_M BIT(2)
#define MT2701_TOP_AXI_PROT_EN_CONN_S BIT(8)
@@ -103,6 +98,45 @@
#define MAX_CLKS 3
+#define MAX_STEPS 4
+
+#define _BUS_PROT(_type, _set_ofs, _clr_ofs, \
+ _en_ofs, _sta_ofs, _mask, _ignore_clr_ack) { \
+ .type = _type, \
+ .set_ofs = _set_ofs, \
+ .clr_ofs = _clr_ofs, \
+ .en_ofs = _en_ofs, \
+ .sta_ofs = _sta_ofs, \
+ .mask = _mask, \
+ .ignore_clr_ack = _ignore_clr_ack, \
+ }
+
+#define BUS_PROT(_type, _set_ofs, _clr_ofs, \
+ _en_ofs, _sta_ofs, _mask) \
+ _BUS_PROT(_type, _set_ofs, _clr_ofs, \
+ _en_ofs, _sta_ofs, _mask, false)
+
+#define BUS_PROT_IGN(_type, _set_ofs, _clr_ofs, \
+ _en_ofs, _sta_ofs, _mask) \
+ _BUS_PROT(_type, _set_ofs, _clr_ofs, \
+ _en_ofs, _sta_ofs, _mask, true)
+
+enum regmap_type {
+ INVALID_TYPE = 0,
+ IFR_TYPE,
+ SMI_TYPE,
+};
+
+struct bus_prot {
+ enum regmap_type type;
+ u32 set_ofs;
+ u32 clr_ofs;
+ u32 en_ofs;
+ u32 sta_ofs;
+ u32 mask;
+ bool ignore_clr_ack;
+};
+
/**
* struct scp_domain_data - scp domain data for power on/off flow
* @name: The domain name.
@@ -110,9 +144,9 @@
* @ctl_offs: The offset for main power control register.
* @sram_pdn_bits: The mask for sram power control bits.
* @sram_pdn_ack_bits: The mask for sram power control acked bits.
- * @bus_prot_mask: The mask for single step bus protection.
* @basic_clk_name: The basic clocks required by this power domain.
* @caps: The flag for active wake-up action.
+ * @bp_table: The mask table for multiple step bus protection.
*/
struct scp_domain_data {
const char *name;
@@ -120,9 +154,9 @@ struct scp_domain_data {
int ctl_offs;
u32 sram_pdn_bits;
u32 sram_pdn_ack_bits;
- u32 bus_prot_mask;
const char *basic_clk_name[MAX_CLKS];
u8 caps;
+ struct bus_prot bp_table[MAX_STEPS];
};
struct scp;
@@ -146,8 +180,8 @@ struct scp {
struct device *dev;
void __iomem *base;
struct regmap *infracfg;
+ struct regmap *smi_common;
struct scp_ctrl_reg ctrl_reg;
- bool bus_prot_reg_update;
};
struct scp_subdomain {
@@ -161,7 +195,6 @@ struct scp_soc_data {
const struct scp_subdomain *subdomains;
int num_subdomains;
const struct scp_ctrl_reg regs;
- bool bus_prot_reg_update;
};
static int scpsys_domain_is_on(struct scp_domain *scpd)
@@ -271,53 +304,87 @@ static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_addr)
MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
}
+static int set_bus_protection(struct regmap *map, const struct bus_prot *bp)
+{
+ u32 val;
+
+ if (bp->set_ofs)
+ regmap_write(map, bp->set_ofs, bp->mask);
+ else
+ regmap_update_bits(map, bp->en_ofs, bp->mask, bp->mask);
+
+ return regmap_read_poll_timeout(map, bp->sta_ofs,
+ val, (val & bp->mask) == bp->mask,
+ MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+}
+
+static int clear_bus_protection(struct regmap *map, const struct bus_prot *bp)
+{
+ u32 val;
+
+ if (bp->clr_ofs)
+ regmap_write(map, bp->clr_ofs, bp->mask);
+ else
+ regmap_update_bits(map, bp->en_ofs, bp->mask, 0);
+
+ if (bp->ignore_clr_ack)
+ return 0;
+
+ return regmap_read_poll_timeout(map, bp->sta_ofs,
+ val, !(val & bp->mask),
+ MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+}
+
static int scpsys_bus_protect_enable(struct scp_domain *scpd)
{
struct scp *scp = scpd->scp;
+ const struct bus_prot *bp_table = scpd->data->bp_table;
struct regmap *infracfg = scp->infracfg;
- u32 mask = scpd->data->bus_prot_mask;
- bool reg_update = scp->bus_prot_reg_update;
- u32 val;
- int ret;
+ struct regmap *smi_common = scp->smi_common;
+ struct regmap *map;
+ int i, ret;
- if (!mask)
- return 0;
+ for (i = 0; i < MAX_STEPS; i++) {
+ if (bp_table[i].type == IFR_TYPE)
+ map = infracfg;
+ else if (bp_table[i].type == SMI_TYPE)
+ map = smi_common;
+ else
+ break;
- if (reg_update)
- regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask,
- mask);
- else
- regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask);
+ ret = set_bus_protection(map, &bp_table[i]);
- ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1,
- val, (val & mask) == mask,
- MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+ if (ret)
+ return ret;
+ }
- return ret;
+ return 0;
}
static int scpsys_bus_protect_disable(struct scp_domain *scpd)
{
struct scp *scp = scpd->scp;
+ const struct bus_prot *bp_table = scpd->data->bp_table;
struct regmap *infracfg = scp->infracfg;
- u32 mask = scpd->data->bus_prot_mask;
- bool reg_update = scp->bus_prot_reg_update;
- u32 val;
- int ret;
+ struct regmap *smi_common = scp->smi_common;
+ struct regmap *map;
+ int i, ret;
- if (!mask)
- return 0;
+ for (i = MAX_STEPS - 1; i >= 0; i--) {
+ if (bp_table[i].type == IFR_TYPE)
+ map = infracfg;
+ else if (bp_table[i].type == SMI_TYPE)
+ map = smi_common;
+ else
+ continue;
- if (reg_update)
- regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0);
- else
- regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask);
+ ret = clear_bus_protection(map, &bp_table[i]);
- ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1,
- val, !(val & mask),
- MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
+ if (ret)
+ return ret;
+ }
- return ret;
+ return 0;
}
static int scpsys_power_on(struct generic_pm_domain *genpd)
@@ -448,8 +515,7 @@ static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
static struct scp *init_scp(struct platform_device *pdev,
const struct scp_domain_data *scp_domain_data, int num,
- const struct scp_ctrl_reg *scp_ctrl_reg,
- bool bus_prot_reg_update)
+ const struct scp_ctrl_reg *scp_ctrl_reg)
{
struct genpd_onecell_data *pd_data;
struct resource *res;
@@ -463,8 +529,6 @@ static struct scp *init_scp(struct platform_device *pdev,
scp->ctrl_reg.pwr_sta_offs = scp_ctrl_reg->pwr_sta_offs;
scp->ctrl_reg.pwr_sta2nd_offs = scp_ctrl_reg->pwr_sta2nd_offs;
- scp->bus_prot_reg_update = bus_prot_reg_update;
-
scp->dev = &pdev->dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -492,6 +556,17 @@ static struct scp *init_scp(struct platform_device *pdev,
return ERR_CAST(scp->infracfg);
}
+ scp->smi_common = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "mediatek,smi");
+
+ if (scp->smi_common == ERR_PTR(-ENODEV)) {
+ scp->smi_common = NULL;
+ } else if (IS_ERR(scp->smi_common)) {
+ dev_err(&pdev->dev, "Cannot find smi_common controller: %ld\n",
+ PTR_ERR(scp->smi_common));
+ return ERR_CAST(scp->smi_common);
+ }
+
for (i = 0; i < num; i++) {
struct scp_domain *scpd = &scp->domains[i];
const struct scp_domain_data *data = &scp_domain_data[i];
@@ -574,8 +649,11 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.name = "conn",
.sta_mask = PWR_STATUS_CONN,
.ctl_offs = SPM_CONN_PWR_CON,
- .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
- MT2701_TOP_AXI_PROT_EN_CONN_S,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ MT2701_TOP_AXI_PROT_EN_CONN_M |
+ MT2701_TOP_AXI_PROT_EN_CONN_S),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2701_POWER_DOMAIN_DISP] = {
@@ -584,7 +662,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_DIS_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.basic_clk_name = {"mm"},
- .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ MT2701_TOP_AXI_PROT_EN_MM_M0),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2701_POWER_DOMAIN_MFG] = {
@@ -719,7 +800,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(16, 16),
.basic_clk_name = {"mfg"},
- .bus_prot_mask = BIT(14) | BIT(21) | BIT(23),
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0x260, 0x264, 0x220, 0x228,
+ BIT(14) | BIT(21) | BIT(23)),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT2712_POWER_DOMAIN_MFG_SC1] = {
@@ -791,7 +875,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.sram_pdn_bits = GENMASK(8, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.basic_clk_name = {"mm"},
- .bus_prot_mask = (BIT(1) | BIT(2)),
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ BIT(1) | BIT(2)),
+ },
},
[MT6797_POWER_DOMAIN_AUDIO] = {
.name = "audio",
@@ -838,7 +925,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_ETHSYS_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
- .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_ETHSYS,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ MT7622_TOP_AXI_PROT_EN_ETHSYS),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT7622_POWER_DOMAIN_HIF0] = {
@@ -848,7 +938,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.basic_clk_name = {"hif_sel"},
- .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF0,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ MT7622_TOP_AXI_PROT_EN_HIF0),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT7622_POWER_DOMAIN_HIF1] = {
@@ -858,7 +951,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(15, 12),
.basic_clk_name = {"hif_sel"},
- .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_HIF1,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ MT7622_TOP_AXI_PROT_EN_HIF1),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT7622_POWER_DOMAIN_WB] = {
@@ -867,7 +963,10 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_WB_PWR_CON,
.sram_pdn_bits = 0,
.sram_pdn_ack_bits = 0,
- .bus_prot_mask = MT7622_TOP_AXI_PROT_EN_WB,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ MT7622_TOP_AXI_PROT_EN_WB),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_FWAIT_SRAM,
},
};
@@ -881,8 +980,11 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.name = "conn",
.sta_mask = PWR_STATUS_CONN,
.ctl_offs = SPM_CONN_PWR_CON,
- .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
- MT2701_TOP_AXI_PROT_EN_CONN_S,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ MT2701_TOP_AXI_PROT_EN_CONN_M |
+ MT2701_TOP_AXI_PROT_EN_CONN_S),
+ },
.caps = MTK_SCPD_ACTIVE_WAKEUP,
},
[MT7623A_POWER_DOMAIN_ETH] = {
@@ -947,8 +1049,11 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = GENMASK(12, 12),
.basic_clk_name = {"mm"},
- .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MM_M0 |
- MT8173_TOP_AXI_PROT_EN_MM_M1,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ MT8173_TOP_AXI_PROT_EN_MM_M0 |
+ MT8173_TOP_AXI_PROT_EN_MM_M1),
+ },
},
[MT8173_POWER_DOMAIN_VENC_LT] = {
.name = "venc_lt",
@@ -994,10 +1099,13 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.ctl_offs = SPM_MFG_PWR_CON,
.sram_pdn_bits = GENMASK(13, 8),
.sram_pdn_ack_bits = GENMASK(21, 16),
- .bus_prot_mask = MT8173_TOP_AXI_PROT_EN_MFG_S |
- MT8173_TOP_AXI_PROT_EN_MFG_M0 |
- MT8173_TOP_AXI_PROT_EN_MFG_M1 |
- MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT,
+ .bp_table = {
+ BUS_PROT(IFR_TYPE, 0, 0, 0x220, 0x228,
+ MT8173_TOP_AXI_PROT_EN_MFG_S |
+ MT8173_TOP_AXI_PROT_EN_MFG_M0 |
+ MT8173_TOP_AXI_PROT_EN_MFG_M1 |
+ MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
+ },
},
};
@@ -1013,7 +1121,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
},
- .bus_prot_reg_update = true,
};
static const struct scp_soc_data mt2712_data = {
@@ -1025,7 +1132,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
},
- .bus_prot_reg_update = false,
};
static const struct scp_soc_data mt6797_data = {
@@ -1037,7 +1143,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.pwr_sta_offs = SPM_PWR_STATUS_MT6797,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND_MT6797
},
- .bus_prot_reg_update = true,
};
static const struct scp_soc_data mt7622_data = {
@@ -1047,7 +1152,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
},
- .bus_prot_reg_update = true,
};
static const struct scp_soc_data mt7623a_data = {
@@ -1057,7 +1161,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
},
- .bus_prot_reg_update = true,
};
static const struct scp_soc_data mt8173_data = {
@@ -1069,7 +1172,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
.pwr_sta_offs = SPM_PWR_STATUS,
.pwr_sta2nd_offs = SPM_PWR_STATUS_2ND
},
- .bus_prot_reg_update = true,
};
/*
@@ -1110,8 +1212,7 @@ static int scpsys_probe(struct platform_device *pdev)
soc = of_device_get_match_data(&pdev->dev);
- scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs,
- soc->bus_prot_reg_update);
+ scp = init_scp(pdev, soc->domains, soc->num_domains, &soc->regs);
if (IS_ERR(scp))
return PTR_ERR(scp);
--
1.8.1.1.dirty
^ permalink raw reply related
* Re: [PATCH 09/12] devfreq: add mediatek cci devfreq
From: andrew-sh.cheng @ 2020-05-21 8:52 UTC (permalink / raw)
Cc: MyungJoo Ham, Kyungmin Park, Chanwoo Choi, Rob Herring,
Mark Rutland, Matthias Brugger, Rafael J . Wysocki, Viresh Kumar,
Nishanth Menon, Stephen Boyd, Liam Girdwood, linux-pm, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, srv_heupstream
In-Reply-To: <20200520123135.GD4823@sirena.org.uk>
On Wed, 2020-05-20 at 13:31 +0100, Mark Brown wrote:
> On Wed, May 20, 2020 at 11:43:04AM +0800, Andrew-sh.Cheng wrote:
>
> > + cci_df->proc_reg = devm_regulator_get_optional(cci_dev, "proc");
> > + ret = PTR_ERR_OR_ZERO(cci_df->proc_reg);
> > + if (ret) {
> > + if (ret != -EPROBE_DEFER)
> > + dev_err(cci_dev, "failed to get regulator for CCI: %d\n",
> > + ret);
> > + return ret;
> > + }
> > + ret = regulator_enable(cci_df->proc_reg);
>
> The code appears to require a regulator (and I'm guessing the device
> needs power) so why is this using regulator_get_optional()?
Hi Mark,
Do you mean, why not use regulator_get_exclusive() or regulator_get()?
Because cci and cpu litter core shared buck, it cannot use
regulator_get_exclusive().
Because both cci and cpu want to tune voltage, it cannot use
regulator_get(), otherwise it will get dummy regulator even this buck
doesn't register.as regulator.
BR,
Andrew-sh.Cheng
^ permalink raw reply
* Re: [PATCH v2 2/6] sc16is7xx: Add flag to activate IrDA mode
From: Greg KH @ 2020-05-21 8:43 UTC (permalink / raw)
To: Daniel Mack
Cc: devicetree, linux-serial, robh+dt, jslaby, jringle, m.brock,
pascal.huerst
In-Reply-To: <20200519182147.218713-3-daniel@zonque.org>
On Tue, May 19, 2020 at 08:21:43PM +0200, Daniel Mack wrote:
> From: Pascal Huerst <pascal.huerst@gmail.com>
>
> This series of uart controllers is able to work in IrDA mode.
> Add per-port flag to the device-tree to enable that feature if needed.
>
> Signed-off-by: Pascal Huerst <pascal.huerst@gmail.com>
> ---
If you send on a patch from someone else, you too need to sign-off on
it, so that I could take it. Please fix this up for all of the patches
that need it in this series and resend.
thanks,
greg k-h
^ permalink raw reply
* Re: [PATCH V6 5/7] tty: serial: qcom_geni_serial: Add interconnect support
From: Greg KH @ 2020-05-21 8:39 UTC (permalink / raw)
To: Akash Asthana
Cc: agross, bjorn.andersson, wsa, broonie, mark.rutland, robh+dt,
linux-i2c, linux-spi, devicetree, swboyd, mgautam, linux-arm-msm,
linux-serial, mka, dianders, msavaliy, evgreen
In-Reply-To: <1590049764-20912-6-git-send-email-akashast@codeaurora.org>
On Thu, May 21, 2020 at 01:59:22PM +0530, Akash Asthana wrote:
> Get the interconnect paths for Uart based Serial Engine device
> and vote according to the baud rate requirement of the driver.
>
> Signed-off-by: Akash Asthana <akashast@codeaurora.org>
> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
> ---
> Changes in V2:
> - As per Bjorn's comment, removed se == NULL check from geni_serial_icc_get
> - As per Bjorn's comment, removed code to set se->icc_path* to NULL in failure
> - As per Bjorn's comment, introduced and using devm_of_icc_get API for getting
> path handle
> - As per Matthias comment, added error handling for icc_set_bw call
>
> Changes in V3:
> - As per Matthias comment, use common library APIs defined in geni-se
> driver for ICC functionality.
>
> Changes in V4:
> - As per Mark's comment move peak_bw guess as twice of avg_bw if
> nothing mentioned explicitly to ICC core.
> - As per Matthias's comment select core clock BW based on baud rate.
> If it's less than 115200 go for GENI_DEFAULT_BW else CORE_2X_50_MHZ
>
> Changes in V5:
> - Add icc_enable/disable to power on/off call.
> - Save some non-zero avg/peak value to ICC core by calling geni_icc_set_bw
> from probe so that when resume/icc_enable is called NOC are running at
> some non-zero value. No need to call icc_disable after BW vote because
> console devices are expected to be in active state from the probe itself
> and qcom_geni_serial_pm(STATE_OFF) will be called for non-console ones.
>
> Changes in V6:
> - No change
>
> drivers/tty/serial/qcom_geni_serial.c | 31 ++++++++++++++++++++++++++++---
> 1 file changed, 28 insertions(+), 3 deletions(-)
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
^ permalink raw reply
* [PATCH v2 3/3] dt-bindings: usb: dwc3: Add entry for tx-fifo-resize
From: Wesley Cheng @ 2020-05-21 8:36 UTC (permalink / raw)
To: agross, bjorn.andersson, robh+dt, balbi, gregkh
Cc: linux-arm-msm, devicetree, linux-kernel, linux-usb, jackp,
Wesley Cheng
In-Reply-To: <1590050169-30747-1-git-send-email-wcheng@codeaurora.org>
Re-introduce the comment for the tx-fifo-resize setting for the DWC3
controller. This allows for vendors to control if they require the TX FIFO
resizing logic on their HW, as the default FIFO size configurations may
already be sufficient.
Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/usb/dwc3.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 9946ff9..489f5da 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -105,7 +105,7 @@ Optional properties:
1-16 (DWC_usb31 programming guide section 1.2.3) to
enable periodic ESS TX threshold.
- - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated.
+ - tx-fifo-resize: determines if the FIFO *has* to be reallocated.
- snps,incr-burst-type-adjustment: Value for INCR burst type of GSBUSCFG0
register, undefined length INCR burst type enable and INCRx type.
When just one value, which means INCRX burst mode enabled. When
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH v2 1/3] usb: dwc3: Resize TX FIFOs to meet EP bursting requirements
From: Wesley Cheng @ 2020-05-21 8:36 UTC (permalink / raw)
To: agross, bjorn.andersson, robh+dt, balbi, gregkh
Cc: linux-arm-msm, devicetree, linux-kernel, linux-usb, jackp,
Wesley Cheng
In-Reply-To: <1590050169-30747-1-git-send-email-wcheng@codeaurora.org>
Some devices have USB compositions which may require multiple endpoints
that support EP bursting. HW defined TX FIFO sizes may not always be
sufficient for these compositions. By utilizing flexible TX FIFO
allocation, this allows for endpoints to request the required FIFO depth to
achieve higher bandwidth. With some higher bMaxBurst configurations, using
a larger TX FIFO size results in better TX throughput.
Ensure that one TX FIFO is reserved for every IN endpoint. This allows for
the FIFO logic to prevent running out of FIFO space.
Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
Reviewed-by: Felipe Balbi <balbi@kernel.org>
---
drivers/usb/dwc3/core.c | 2 +
drivers/usb/dwc3/core.h | 8 ++++
drivers/usb/dwc3/ep0.c | 37 +++++++++++++++-
drivers/usb/dwc3/gadget.c | 111 ++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 157 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index edc1715..cca5554 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1304,6 +1304,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
&tx_thr_num_pkt_prd);
device_property_read_u8(dev, "snps,tx-max-burst-prd",
&tx_max_burst_prd);
+ dwc->needs_fifo_resize = device_property_read_bool(dev,
+ "tx-fifo-resize");
dwc->disable_scramble_quirk = device_property_read_bool(dev,
"snps,disable_scramble_quirk");
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 4c171a8..ce0bf28 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -675,6 +675,7 @@ struct dwc3_event_buffer {
* isochronous START TRANSFER command failure workaround
* @start_cmd_status: the status of testing START TRANSFER command with
* combo_num = 'b00
+ * @fifo_depth: allocated TXFIFO depth
*/
struct dwc3_ep {
struct usb_ep endpoint;
@@ -727,6 +728,7 @@ struct dwc3_ep {
/* For isochronous START TRANSFER workaround only */
u8 combo_num;
int start_cmd_status;
+ int fifo_depth;
};
enum dwc3_phy {
@@ -1004,6 +1006,7 @@ struct dwc3_scratchpad_array {
* 1 - utmi_l1_suspend_n
* @is_fpga: true when we are using the FPGA board
* @pending_events: true when we have pending IRQs to be handled
+ * @needs_fifo_resize: not all users might want fifo resizing, flag it
* @pullups_connected: true when Run/Stop bit is set
* @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
* @three_stage_setup: set if we perform a three phase setup
@@ -1044,6 +1047,8 @@ struct dwc3_scratchpad_array {
* @dis_metastability_quirk: set to disable metastability quirk.
* @imod_interval: set the interrupt moderation interval in 250ns
* increments or 0 to disable.
+ * @last_fifo_depth: total TXFIFO depth of all enabled USB IN/INT endpoints
+ * @num_ep_resized: the number of TX FIFOs that have already been resized
*/
struct dwc3 {
struct work_struct drd_work;
@@ -1204,6 +1209,7 @@ struct dwc3 {
unsigned is_utmi_l1_suspend:1;
unsigned is_fpga:1;
unsigned pending_events:1;
+ unsigned needs_fifo_resize:1;
unsigned pullups_connected:1;
unsigned setup_packet_pending:1;
unsigned three_stage_setup:1;
@@ -1236,6 +1242,8 @@ struct dwc3 {
unsigned dis_metastability_quirk:1;
u16 imod_interval;
+ int last_fifo_depth;
+ int num_ep_resized;
};
#define INCRX_BURST_MODE 0
diff --git a/drivers/usb/dwc3/ep0.c b/drivers/usb/dwc3/ep0.c
index 6dee4da..76db9b5 100644
--- a/drivers/usb/dwc3/ep0.c
+++ b/drivers/usb/dwc3/ep0.c
@@ -601,8 +601,9 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
{
enum usb_device_state state = dwc->gadget.state;
u32 cfg;
- int ret;
+ int ret, num, size;
u32 reg;
+ struct dwc3_ep *dep;
cfg = le16_to_cpu(ctrl->wValue);
@@ -611,6 +612,40 @@ static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
return -EINVAL;
case USB_STATE_ADDRESS:
+ /*
+ * If tx-fifo-resize flag is not set for the controller, then
+ * do not clear existing allocated TXFIFO since we do not
+ * allocate it again in dwc3_gadget_resize_tx_fifos
+ */
+ if (dwc->needs_fifo_resize) {
+ /* Read ep0IN related TXFIFO size */
+ dep = dwc->eps[1];
+ size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
+ if (dwc3_is_usb31(dwc))
+ dep->fifo_depth = DWC31_GTXFIFOSIZ_TXFDEP(size);
+ else
+ dep->fifo_depth = DWC3_GTXFIFOSIZ_TXFDEP(size);
+
+ dwc->last_fifo_depth = dep->fifo_depth;
+ /* Clear existing TXFIFO for all IN eps except ep0 */
+ for (num = 3; num < min_t(int, dwc->num_eps,
+ DWC3_ENDPOINTS_NUM); num += 2) {
+ dep = dwc->eps[num];
+ /* Don't change TXFRAMNUM on usb31 version */
+ size = dwc3_is_usb31(dwc) ?
+ dwc3_readl(dwc->regs,
+ DWC3_GTXFIFOSIZ(num >> 1)) &
+ DWC31_GTXFIFOSIZ_TXFRAMNUM :
+ 0;
+
+ dwc3_writel(dwc->regs,
+ DWC3_GTXFIFOSIZ(num >> 1),
+ size);
+ dep->fifo_depth = 0;
+ }
+ dwc->num_ep_resized = 0;
+ }
+
ret = dwc3_ep0_delegate_req(dwc, ctrl);
/* if the cfg matches and the cfg is non zero */
if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 00746c2..65bcc0f 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -540,6 +540,113 @@ static int dwc3_gadget_start_config(struct dwc3_ep *dep)
return 0;
}
+/*
+ * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
+ * @dwc: pointer to our context structure
+ *
+ * This function will a best effort FIFO allocation in order
+ * to improve FIFO usage and throughput, while still allowing
+ * us to enable as many endpoints as possible.
+ *
+ * Keep in mind that this operation will be highly dependent
+ * on the configured size for RAM1 - which contains TxFifo -,
+ * the amount of endpoints enabled on coreConsultant tool, and
+ * the width of the Master Bus.
+ *
+ * In general, FIFO depths are represented with the following equation:
+ *
+ * fifo_size = mult * ((max_packet + mdwidth)/mdwidth + 1) + 1
+ *
+ * Conversions can be done to the equation to derive the number of packets that
+ * will fit to a particular FIFO size value.
+ */
+static int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc, struct dwc3_ep *dep)
+{
+ int ram1_depth, mdwidth, fifo_0_start, tmp, num_in_ep;
+ int min_depth, remaining, fifo_size, mult = 1, fifo, max_packet = 1024;
+
+ if (!dwc->needs_fifo_resize)
+ return 0;
+
+ /* resize IN endpoints except ep0 */
+ if (!usb_endpoint_dir_in(dep->endpoint.desc) || dep->number <= 1)
+ return 0;
+
+ /* Don't resize already resized IN endpoint */
+ if (dep->fifo_depth)
+ return 0;
+
+ ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
+ mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
+ /* MDWIDTH is represented in bits, we need it in bytes */
+ mdwidth >>= 3;
+
+ if (((dep->endpoint.maxburst > 1) &&
+ usb_endpoint_xfer_bulk(dep->endpoint.desc))
+ || usb_endpoint_xfer_isoc(dep->endpoint.desc))
+ mult = 3;
+
+ if ((dep->endpoint.maxburst > 6) &&
+ usb_endpoint_xfer_bulk(dep->endpoint.desc)
+ && dwc3_is_usb31(dwc))
+ mult = 6;
+
+ /* FIFO size for a single buffer */
+ fifo = (max_packet + mdwidth)/mdwidth;
+ fifo++;
+
+ /* Calculate the number of remaining EPs w/o any FIFO */
+ num_in_ep = dwc->num_eps/2;
+ num_in_ep -= dwc->num_ep_resized;
+ /* Ignore EP0 IN */
+ num_in_ep--;
+
+ /* Reserve at least one FIFO for the number of IN EPs */
+ min_depth = num_in_ep * (fifo+1);
+ remaining = ram1_depth - min_depth - dwc->last_fifo_depth;
+
+ /* We've already reserved 1 FIFO per EP, so check what we can fit in
+ * addition to it. If there is not enough remaining space, allocate
+ * all the remaining space to the EP.
+ */
+ fifo_size = (mult-1) * fifo;
+ if (remaining < fifo_size && remaining > 0)
+ fifo_size = remaining;
+
+ fifo_size += fifo;
+ fifo_size++;
+ dep->fifo_depth = fifo_size;
+
+ /* Check if TXFIFOs start at non-zero addr */
+ tmp = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0));
+ fifo_0_start = DWC3_GTXFIFOSIZ_TXFSTADDR(tmp);
+
+ fifo_size |= (fifo_0_start + (dwc->last_fifo_depth << 16));
+ if (dwc3_is_usb31(dwc))
+ dwc->last_fifo_depth += DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
+ else
+ dwc->last_fifo_depth += DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
+
+ /* Check fifo size allocation doesn't exceed available RAM size. */
+ if (dwc->last_fifo_depth >= ram1_depth) {
+ dev_err(dwc->dev, "Fifosize(%d) > RAM size(%d) %s depth:%d\n",
+ (dwc->last_fifo_depth * mdwidth), ram1_depth,
+ dep->endpoint.name, fifo_size);
+ if (dwc3_is_usb31(dwc))
+ fifo_size = DWC31_GTXFIFOSIZ_TXFDEP(fifo_size);
+ else
+ fifo_size = DWC3_GTXFIFOSIZ_TXFDEP(fifo_size);
+ dwc->last_fifo_depth -= fifo_size;
+ dep->fifo_depth = 0;
+ WARN_ON(1);
+ return -ENOMEM;
+ }
+
+ dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(dep->number >> 1), fifo_size);
+ dwc->num_ep_resized++;
+ return 0;
+}
+
static int dwc3_gadget_set_ep_config(struct dwc3_ep *dep, unsigned int action)
{
const struct usb_ss_ep_comp_descriptor *comp_desc;
@@ -620,6 +727,10 @@ static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep, unsigned int action)
int ret;
if (!(dep->flags & DWC3_EP_ENABLED)) {
+ ret = dwc3_gadget_resize_tx_fifos(dwc, dep);
+ if (ret)
+ return ret;
+
ret = dwc3_gadget_start_config(dep);
if (ret)
return ret;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH v2 0/3] Re-introduce TX FIFO resize for larger EP bursting
From: Wesley Cheng @ 2020-05-21 8:36 UTC (permalink / raw)
To: agross, bjorn.andersson, robh+dt, balbi, gregkh
Cc: linux-arm-msm, devicetree, linux-kernel, linux-usb, jackp,
Wesley Cheng
Changes in V2:
- Modified TXFIFO resizing logic to ensure that each EP is reserved a
FIFO.
- Removed dev_dbg() prints and fixed typos from patches
- Added some more description on the dt-bindings commit message
Reviewed-by: Felipe Balbi <balbi@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Currently, there is no functionality to allow for resizing the TXFIFOs, and
relying on the HW default setting for the TXFIFO depth. In most cases, the
HW default is probably sufficient, but for USB compositions that contain
multiple functions that require EP bursting, the default settings
might not be enough. Also to note, the current SW will assign an EP to a
function driver w/o checking to see if the TXFIFO size for that particular
EP is large enough. (this is a problem if there are multiple HW defined
values for the TXFIFO size)
It is mentioned in the SNPS databook that a minimum of TX FIFO depth = 3
is required for an EP that supports bursting. Otherwise, there may be
frequent occurences of bursts ending. For high bandwidth functions,
such as data tethering (protocols that support data aggregation), mass
storage, and media transfer protocol (over FFS), the bMaxBurst value can be
large, and a bigger TXFIFO depth may prove to be beneficial in terms of USB
throughput. (which can be associated to system access latency, etc...) It
allows for a more consistent burst of traffic, w/o any interruptions, as
data is readily available in the FIFO.
With testing done using the mass storage function driver, the results show
that with a larger TXFIFO depth, the bandwidth increased significantly.
Test Parameters:
- Platform: Qualcomm SM8150
- bMaxBurst = 6
- USB req size = 256kB
- Num of USB reqs = 16
- USB Speed = Super-Speed
- Function Driver: Mass Storage (w/ ramdisk)
- Test Application: CrystalDiskMark
Results:
TXFIFO Depth = 3 max packets
Test Case | Data Size | AVG tput (in MB/s)
-------------------------------------------
Sequential|1 GB x |
Read |9 loops | 193.60
| | 195.86
| | 184.77
| | 193.60
-------------------------------------------
TXFIFO Depth = 6 max packets
Test Case | Data Size | AVG tput (in MB/s)
-------------------------------------------
Sequential|1 GB x |
Read |9 loops | 287.35
| | 304.94
| | 289.64
| | 293.61
-------------------------------------------
Wesley Cheng (3):
usb: dwc3: Resize TX FIFOs to meet EP bursting requirements
arm64: boot: dts: qcom: sm8150: Enable dynamic TX FIFO resize logic
dt-bindings: usb: dwc3: Add entry for tx-fifo-resize
Documentation/devicetree/bindings/usb/dwc3.txt | 2 +-
arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 +
drivers/usb/dwc3/core.c | 2 +
drivers/usb/dwc3/core.h | 8 ++
drivers/usb/dwc3/ep0.c | 37 ++++++++-
drivers/usb/dwc3/gadget.c | 111 +++++++++++++++++++++++++
6 files changed, 159 insertions(+), 2 deletions(-)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v2 2/3] arm64: boot: dts: qcom: sm8150: Enable dynamic TX FIFO resize logic
From: Wesley Cheng @ 2020-05-21 8:36 UTC (permalink / raw)
To: agross, bjorn.andersson, robh+dt, balbi, gregkh
Cc: linux-arm-msm, devicetree, linux-kernel, linux-usb, jackp,
Wesley Cheng
In-Reply-To: <1590050169-30747-1-git-send-email-wcheng@codeaurora.org>
Enable the flexible TX FIFO resize logic on SM8150. Using a larger TX FIFO
SZ can help account for situations when system latency is greater than the
USB bus transmission latency.
Signed-off-by: Wesley Cheng <wcheng@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index a36512d..c285233 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -708,6 +708,7 @@
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
+ tx-fifo-resize;
phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
phy-names = "usb2-phy", "usb3-phy";
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH V6 7/7] arm64: dts: sc7180: Add interconnect for QUP and QSPI
From: Akash Asthana @ 2020-05-21 8:29 UTC (permalink / raw)
To: gregkh, agross, bjorn.andersson, wsa, broonie, mark.rutland,
robh+dt
Cc: linux-i2c, linux-spi, devicetree, swboyd, mgautam, linux-arm-msm,
linux-serial, mka, dianders, msavaliy, evgreen, Akash Asthana
In-Reply-To: <1590049764-20912-1-git-send-email-akashast@codeaurora.org>
Add interconnect ports for GENI QUPs and QSPI to set bus capabilities.
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
---
Changes in V2:
- As per Bjorn's comment, ignoring 80 char limit in defining interconnects
paths.
Changes in V3:
- No change.
Change in V4:
- No change.
Changes in V5:
- No change.
Chnages in V6:
- No change.
arch/arm64/boot/dts/qcom/sc7180.dtsi | 127 +++++++++++++++++++++++++++++++++++
1 file changed, 127 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 6b12c60..e1fd3d4 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -547,6 +547,8 @@
#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x43 0x0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>;
+ interconnect-names = "qup-core";
status = "disabled";
i2c0: i2c@880000 {
@@ -559,6 +561,11 @@
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -572,6 +579,9 @@
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -583,6 +593,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -596,6 +609,11 @@
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -609,6 +627,9 @@
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -620,6 +641,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -633,6 +657,11 @@
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -644,6 +673,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart2_default>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -657,6 +689,11 @@
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -670,6 +707,9 @@
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -681,6 +721,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart3_default>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -694,6 +737,11 @@
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -705,6 +753,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart4_default>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -718,6 +769,11 @@
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>,
+ <&aggre1_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -731,6 +787,9 @@
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -742,6 +801,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 &qup_virt SLAVE_QUP_CORE_0>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
};
@@ -756,6 +818,8 @@
#size-cells = <2>;
ranges;
iommus = <&apps_smmu 0x4c3 0x0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>;
+ interconnect-names = "qup-core";
status = "disabled";
i2c6: i2c@a80000 {
@@ -768,6 +832,11 @@
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -781,6 +850,9 @@
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -792,6 +864,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart6_default>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -805,6 +880,11 @@
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -816,6 +896,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart7_default>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -829,6 +912,11 @@
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -842,6 +930,9 @@
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -853,6 +944,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart8_default>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -866,6 +960,11 @@
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -877,6 +976,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart9_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -890,6 +992,11 @@
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -903,6 +1010,9 @@
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -914,6 +1024,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart10_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -927,6 +1040,11 @@
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>,
+ <&aggre2_noc MASTER_QUP_1 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
status = "disabled";
};
@@ -940,6 +1058,9 @@
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -951,6 +1072,9 @@
pinctrl-names = "default";
pinctrl-0 = <&qup_uart11_default>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 &qup_virt SLAVE_QUP_CORE_1>,
+ <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_QUP_1>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
};
@@ -2132,6 +2256,9 @@
clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
<&gcc GCC_QSPI_CORE_CLK>;
clock-names = "iface", "core";
+ interconnects = <&gem_noc MASTER_APPSS_PROC
+ &config_noc SLAVE_QSPI_0>;
+ interconnect-names = "qspi-config";
status = "disabled";
};
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH V6 6/7] spi: spi-qcom-qspi: Add interconnect support
From: Akash Asthana @ 2020-05-21 8:29 UTC (permalink / raw)
To: gregkh, agross, bjorn.andersson, wsa, broonie, mark.rutland,
robh+dt
Cc: linux-i2c, linux-spi, devicetree, swboyd, mgautam, linux-arm-msm,
linux-serial, mka, dianders, msavaliy, evgreen, Akash Asthana
In-Reply-To: <1590049764-20912-1-git-send-email-akashast@codeaurora.org>
Get the interconnect paths for QSPI device and vote according to the
current bus speed of the driver.
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
Acked-by: Mark Brown <broonie@kernel.org>
---
Changes in V2:
- As per Bjorn's comment, introduced and using devm_of_icc_get API for getting
path handle
- As per Matthias comment, added error handling for icc_set_bw call
Changes in V3:
- No Change.
Changes in V4:
- As per Mark's comment move peak_bw guess as twice of avg_bw if
nothing mentioned explicitly to ICC core.
Changes in V5:
- Add icc_enable/disable to power on/off call.
- Save some non-zero avg/peak value to ICC core by calling geni_icc_set_bw
from probe so that when resume/icc_enable is called NOC are running at
some non-zero value.
Changes in V6:
- As per Matthias's comment made print statement consistent across driver
drivers/spi/spi-qcom-qspi.c | 59 ++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 58 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-qcom-qspi.c b/drivers/spi/spi-qcom-qspi.c
index 3c4f83b..d76001a 100644
--- a/drivers/spi/spi-qcom-qspi.c
+++ b/drivers/spi/spi-qcom-qspi.c
@@ -2,6 +2,7 @@
// Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
#include <linux/clk.h>
+#include <linux/interconnect.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
@@ -139,7 +140,10 @@ struct qcom_qspi {
struct device *dev;
struct clk_bulk_data *clks;
struct qspi_xfer xfer;
- /* Lock to protect xfer and IRQ accessed registers */
+ struct icc_path *icc_path_cpu_to_qspi;
+ unsigned int avg_bw_cpu;
+ unsigned int peak_bw_cpu;
+ /* Lock to protect data accessed by IRQs */
spinlock_t lock;
};
@@ -241,6 +245,20 @@ static int qcom_qspi_transfer_one(struct spi_master *master,
return ret;
}
+ /*
+ * Set BW quota for CPU as driver supports FIFO mode only.
+ * We don't have explicit peak requirement so keep it equal to avg_bw.
+ */
+ ctrl->avg_bw_cpu = Bps_to_icc(speed_hz);
+ ctrl->peak_bw_cpu = ctrl->avg_bw_cpu;
+ ret = icc_set_bw(ctrl->icc_path_cpu_to_qspi, ctrl->avg_bw_cpu,
+ ctrl->peak_bw_cpu);
+ if (ret) {
+ dev_err(ctrl->dev, "%s: ICC BW voting failed for cpu :%d\n",
+ __func__, ret);
+ return ret;
+ }
+
spin_lock_irqsave(&ctrl->lock, flags);
/* We are half duplex, so either rx or tx will be set */
@@ -458,6 +476,29 @@ static int qcom_qspi_probe(struct platform_device *pdev)
if (ret)
goto exit_probe_master_put;
+ ctrl->icc_path_cpu_to_qspi = devm_of_icc_get(dev, "qspi-config");
+ if (IS_ERR(ctrl->icc_path_cpu_to_qspi)) {
+ ret = PTR_ERR(ctrl->icc_path_cpu_to_qspi);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "Failed to get cpu path :%d\n", ret);
+ goto exit_probe_master_put;
+ }
+ /* Set BW vote for register access */
+ ret = icc_set_bw(ctrl->icc_path_cpu_to_qspi, Bps_to_icc(1000),
+ Bps_to_icc(1000));
+ if (ret) {
+ dev_err(ctrl->dev, "%s: ICC BW voting failed for cpu :%d\n",
+ __func__, ret);
+ goto exit_probe_master_put;
+ }
+
+ ret = icc_disable(ctrl->icc_path_cpu_to_qspi);
+ if (ret) {
+ dev_err(ctrl->dev, "%s: ICC disable failed for cpu :%d\n",
+ __func__, ret);
+ goto exit_probe_master_put;
+ }
+
ret = platform_get_irq(pdev, 0);
if (ret < 0)
goto exit_probe_master_put;
@@ -511,9 +552,17 @@ static int __maybe_unused qcom_qspi_runtime_suspend(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct qcom_qspi *ctrl = spi_master_get_devdata(master);
+ int ret;
clk_bulk_disable_unprepare(QSPI_NUM_CLKS, ctrl->clks);
+ ret = icc_disable(ctrl->icc_path_cpu_to_qspi);
+ if (ret) {
+ dev_err_ratelimited(ctrl->dev, "%s: ICC disable failed for cpu :%d\n",
+ __func__, ret);
+ return ret;
+ }
+
return 0;
}
@@ -521,6 +570,14 @@ static int __maybe_unused qcom_qspi_runtime_resume(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct qcom_qspi *ctrl = spi_master_get_devdata(master);
+ int ret;
+
+ ret = icc_enable(ctrl->icc_path_cpu_to_qspi);
+ if (ret) {
+ dev_err_ratelimited(ctrl->dev, "%s: ICC enable failed for cpu :%d\n",
+ __func__, ret);
+ return ret;
+ }
return clk_bulk_prepare_enable(QSPI_NUM_CLKS, ctrl->clks);
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH V6 4/7] spi: spi-geni-qcom: Add interconnect support
From: Akash Asthana @ 2020-05-21 8:29 UTC (permalink / raw)
To: gregkh, agross, bjorn.andersson, wsa, broonie, mark.rutland,
robh+dt
Cc: linux-i2c, linux-spi, devicetree, swboyd, mgautam, linux-arm-msm,
linux-serial, mka, dianders, msavaliy, evgreen, Akash Asthana
In-Reply-To: <1590049764-20912-1-git-send-email-akashast@codeaurora.org>
Get the interconnect paths for SPI based Serial Engine device
and vote according to the current bus speed of the driver.
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Acked-by: Mark Brown <broonie@kernel.org>
---
Changes in V2:
- As per Bjorn's comment, removed se == NULL check from geni_spi_icc_get
- As per Bjorn's comment, removed code to set se->icc_path* to NULL in failure
- As per Bjorn's comment, introduced and using devm_of_icc_get API for getting
path handle
- As per Matthias comment, added error handling for icc_set_bw call
Changes in V3:
- As per Matthias's comment, use helper ICC function from geni-se driver.
Changes in V4:
- Move peak_bw guess as twice of avg_bw if nothing mentioned explicitly
to ICC core.
Changes in V5:
- Use icc_enable/disable in power on/off call.
- Save some non-zero avg/peak value to ICC core by calling geni_icc_set_bw
from probe so that when resume/icc_enable is called NOC are running at
some non-zero value. No need to call icc_disable after BW vote because
device will resume and suspend before probe return and will leave ICC in
disabled state.
Changes in V6:
- No change
drivers/spi/spi-geni-qcom.c | 31 ++++++++++++++++++++++++++++++-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
index c397242..cc637d2 100644
--- a/drivers/spi/spi-geni-qcom.c
+++ b/drivers/spi/spi-geni-qcom.c
@@ -234,6 +234,13 @@ static int setup_fifo_params(struct spi_device *spi_slv,
return ret;
}
+ /* Set BW quota for CPU as driver supports FIFO mode only. */
+ geni_icc_bw_init(&se->icc_paths[CPU_TO_GENI],
+ Bps_to_icc(mas->cur_speed_hz), 0);
+ ret = geni_icc_set_bw(se);
+ if (ret)
+ return ret;
+
clk_sel = idx & CLK_SEL_MSK;
m_clk_cfg = (div << CLK_DIV_SHFT) | SER_CLK_EN;
spi_setup_word_len(mas, spi_slv->mode, spi_slv->bits_per_word);
@@ -578,6 +585,18 @@ static int spi_geni_probe(struct platform_device *pdev)
spin_lock_init(&mas->lock);
pm_runtime_enable(dev);
+ ret = geni_icc_get(&mas->se, NULL);
+ if (ret)
+ goto spi_geni_probe_runtime_disable;
+ /* Set the bus quota to a reasonable value for register access */
+ geni_icc_bw_init(&mas->se.icc_paths[GENI_TO_CORE],
+ Bps_to_icc(CORE_2X_50_MHZ), 0);
+ geni_icc_bw_init(&mas->se.icc_paths[CPU_TO_GENI], GENI_DEFAULT_BW, 0);
+
+ ret = geni_icc_set_bw(&mas->se);
+ if (ret)
+ goto spi_geni_probe_runtime_disable;
+
ret = spi_geni_init(mas);
if (ret)
goto spi_geni_probe_runtime_disable;
@@ -616,14 +635,24 @@ static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
{
struct spi_master *spi = dev_get_drvdata(dev);
struct spi_geni_master *mas = spi_master_get_devdata(spi);
+ int ret;
+
+ ret = geni_se_resources_off(&mas->se);
+ if (ret)
+ return ret;
- return geni_se_resources_off(&mas->se);
+ return geni_icc_disable(&mas->se);
}
static int __maybe_unused spi_geni_runtime_resume(struct device *dev)
{
struct spi_master *spi = dev_get_drvdata(dev);
struct spi_geni_master *mas = spi_master_get_devdata(spi);
+ int ret;
+
+ ret = geni_icc_enable(&mas->se);
+ if (ret)
+ return ret;
return geni_se_resources_on(&mas->se);
}
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH V6 3/7] i2c: i2c-qcom-geni: Add interconnect support
From: Akash Asthana @ 2020-05-21 8:29 UTC (permalink / raw)
To: gregkh, agross, bjorn.andersson, wsa, broonie, mark.rutland,
robh+dt
Cc: linux-i2c, linux-spi, devicetree, swboyd, mgautam, linux-arm-msm,
linux-serial, mka, dianders, msavaliy, evgreen, Akash Asthana
In-Reply-To: <1590049764-20912-1-git-send-email-akashast@codeaurora.org>
Get the interconnect paths for I2C based Serial Engine device
and vote according to the bus speed of the driver.
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Acked-by: Wolfram Sang <wsa@kernel.org>
---
Changes in V2:
- As per Bjorn's comment, removed se == NULL check from geni_i2c_icc_get
- As per Bjorn's comment, removed code to set se->icc_path* to NULL in failure
- As per Bjorn's comment, introduced and using devm_of_icc_get API for getting
path handle
- As per Matthias comment, added error handling for icc_set_bw call
Changes in V3:
- As per Matthias comment, use common library APIs defined in geni-se
driver for ICC functionality.
Changes in V4:
- Move peak_bw guess as twice of avg_bw if nothing mentioned explicitly
to ICC core.
Changes in V5:
- Use icc_enable/disable in power on/off call.
Changes in V6:
- No changes
drivers/i2c/busses/i2c-qcom-geni.c | 29 ++++++++++++++++++++++++++++-
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qcom-geni.c
index 18d1e4f..f2e786d 100644
--- a/drivers/i2c/busses/i2c-qcom-geni.c
+++ b/drivers/i2c/busses/i2c-qcom-geni.c
@@ -557,6 +557,25 @@ static int geni_i2c_probe(struct platform_device *pdev)
gi2c->adap.dev.of_node = dev->of_node;
strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
+ ret = geni_icc_get(&gi2c->se, "qup-memory");
+ if (ret)
+ return ret;
+ /*
+ * Set the bus quota for core and cpu to a reasonable value for
+ * register access.
+ * Set quota for DDR based on bus speed.
+ */
+ geni_icc_bw_init(&gi2c->se.icc_paths[GENI_TO_CORE], GENI_DEFAULT_BW,
+ 0);
+ geni_icc_bw_init(&gi2c->se.icc_paths[CPU_TO_GENI], GENI_DEFAULT_BW,
+ 0);
+ geni_icc_bw_init(&gi2c->se.icc_paths[GENI_TO_DDR],
+ Bps_to_icc(gi2c->clk_freq_out), 0);
+
+ ret = geni_icc_set_bw(&gi2c->se);
+ if (ret)
+ return ret;
+
ret = geni_se_resources_on(&gi2c->se);
if (ret) {
dev_err(dev, "Error turning on resources %d\n", ret);
@@ -579,6 +598,10 @@ static int geni_i2c_probe(struct platform_device *pdev)
return ret;
}
+ ret = geni_icc_disable(&gi2c->se);
+ if (ret)
+ return ret;
+
dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth);
gi2c->suspended = 1;
@@ -623,7 +646,7 @@ static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev)
gi2c->suspended = 1;
}
- return 0;
+ return geni_icc_disable(&gi2c->se);
}
static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
@@ -631,6 +654,10 @@ static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
int ret;
struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
+ ret = geni_icc_enable(&gi2c->se);
+ if (ret)
+ return ret;
+
ret = geni_se_resources_on(&gi2c->se);
if (ret)
return ret;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH V6 5/7] tty: serial: qcom_geni_serial: Add interconnect support
From: Akash Asthana @ 2020-05-21 8:29 UTC (permalink / raw)
To: gregkh, agross, bjorn.andersson, wsa, broonie, mark.rutland,
robh+dt
Cc: linux-i2c, linux-spi, devicetree, swboyd, mgautam, linux-arm-msm,
linux-serial, mka, dianders, msavaliy, evgreen, Akash Asthana
In-Reply-To: <1590049764-20912-1-git-send-email-akashast@codeaurora.org>
Get the interconnect paths for Uart based Serial Engine device
and vote according to the baud rate requirement of the driver.
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
---
Changes in V2:
- As per Bjorn's comment, removed se == NULL check from geni_serial_icc_get
- As per Bjorn's comment, removed code to set se->icc_path* to NULL in failure
- As per Bjorn's comment, introduced and using devm_of_icc_get API for getting
path handle
- As per Matthias comment, added error handling for icc_set_bw call
Changes in V3:
- As per Matthias comment, use common library APIs defined in geni-se
driver for ICC functionality.
Changes in V4:
- As per Mark's comment move peak_bw guess as twice of avg_bw if
nothing mentioned explicitly to ICC core.
- As per Matthias's comment select core clock BW based on baud rate.
If it's less than 115200 go for GENI_DEFAULT_BW else CORE_2X_50_MHZ
Changes in V5:
- Add icc_enable/disable to power on/off call.
- Save some non-zero avg/peak value to ICC core by calling geni_icc_set_bw
from probe so that when resume/icc_enable is called NOC are running at
some non-zero value. No need to call icc_disable after BW vote because
console devices are expected to be in active state from the probe itself
and qcom_geni_serial_pm(STATE_OFF) will be called for non-console ones.
Changes in V6:
- No change
drivers/tty/serial/qcom_geni_serial.c | 31 ++++++++++++++++++++++++++++---
1 file changed, 28 insertions(+), 3 deletions(-)
diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c
index 8c5d97c..2a1da36 100644
--- a/drivers/tty/serial/qcom_geni_serial.c
+++ b/drivers/tty/serial/qcom_geni_serial.c
@@ -944,6 +944,7 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
unsigned long clk_rate;
u32 ver, sampling_rate;
+ unsigned int avg_bw_core;
qcom_geni_serial_stop_rx(uport);
/* baud rate */
@@ -965,6 +966,16 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
ser_clk_cfg = SER_CLK_EN;
ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
+ /*
+ * Bump up BW vote on CPU and CORE path as driver supports FIFO mode
+ * only.
+ */
+ avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ)
+ : GENI_DEFAULT_BW;
+ geni_icc_bw_init(&port->se.icc_paths[GENI_TO_CORE], avg_bw_core, 0);
+ geni_icc_bw_init(&port->se.icc_paths[CPU_TO_GENI], Bps_to_icc(baud), 0);
+ geni_icc_set_bw(&port->se);
+
/* parity */
tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
@@ -1202,11 +1213,14 @@ static void qcom_geni_serial_pm(struct uart_port *uport,
if (old_state == UART_PM_STATE_UNDEFINED)
old_state = UART_PM_STATE_OFF;
- if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
+ if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
+ geni_icc_enable(&port->se);
geni_se_resources_on(&port->se);
- else if (new_state == UART_PM_STATE_OFF &&
- old_state == UART_PM_STATE_ON)
+ } else if (new_state == UART_PM_STATE_OFF &&
+ old_state == UART_PM_STATE_ON) {
geni_se_resources_off(&port->se);
+ geni_icc_disable(&port->se);
+ }
}
static const struct uart_ops qcom_geni_console_pops = {
@@ -1304,6 +1318,17 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
return -ENOMEM;
}
+ ret = geni_icc_get(&port->se, NULL);
+ if (ret)
+ return ret;
+ geni_icc_bw_init(&port->se.icc_paths[GENI_TO_CORE], GENI_DEFAULT_BW, 0);
+ geni_icc_bw_init(&port->se.icc_paths[CPU_TO_GENI], GENI_DEFAULT_BW, 0);
+
+ /* Set BW for register access */
+ ret = geni_icc_set_bw(&port->se);
+ if (ret)
+ return ret;
+
port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
"qcom_geni_serial_%s%d",
uart_console(uport) ? "console" : "uart", uport->line);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH V6 2/7] soc: qcom-geni-se: Add interconnect support to fix earlycon crash
From: Akash Asthana @ 2020-05-21 8:29 UTC (permalink / raw)
To: gregkh, agross, bjorn.andersson, wsa, broonie, mark.rutland,
robh+dt
Cc: linux-i2c, linux-spi, devicetree, swboyd, mgautam, linux-arm-msm,
linux-serial, mka, dianders, msavaliy, evgreen, Akash Asthana
In-Reply-To: <1590049764-20912-1-git-send-email-akashast@codeaurora.org>
QUP core clock is shared among all the SE drivers present on particular
QUP wrapper, the system will reset(unclocked access) if earlycon used after
QUP core clock is put to 0 from other SE drivers before real console comes
up.
As earlycon can't vote for it's QUP core need, to fix this add ICC
support to common/QUP wrapper driver and put vote for QUP core from
probe on behalf of earlycon and remove vote during earlycon exit call.
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
Reported-by: Matthias Kaehlcke <mka@chromium.org>
---
Change in V3:
- Add geni_remove_earlycon_icc_vote API that will be used by earlycon
exit function to remove ICC vote for earlyconsole.
- Remove suspend/resume hook for geni-se driver as we are no longer
removing earlyconsole ICC vote from system suspend, we are removing
from earlycon exit.
Change in V4:
- As per Matthias comment make 'earlycon_wrapper' as static structure.
Changes in V5:
- Vote for core path only after checking whether "qcom_geni" earlycon is
actually present or not by traversing over structure "console_drivers".
Changes in V6:
- As per Matthias's comment removed NULL check for console_drivers global
struct, added NULL check for earlycon_wrapper in _remove_earlycon_icc_vote
API
- Addressed nitpicks from Andy.
drivers/soc/qcom/qcom-geni-se.c | 68 +++++++++++++++++++++++++++++++++++
drivers/tty/serial/qcom_geni_serial.c | 7 ++++
include/linux/qcom-geni-se.h | 2 ++
3 files changed, 77 insertions(+)
diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c
index 0b2526d..ac16bb1 100644
--- a/drivers/soc/qcom/qcom-geni-se.c
+++ b/drivers/soc/qcom/qcom-geni-se.c
@@ -3,6 +3,7 @@
#include <linux/acpi.h>
#include <linux/clk.h>
+#include <linux/console.h>
#include <linux/slab.h>
#include <linux/dma-mapping.h>
#include <linux/io.h>
@@ -90,11 +91,14 @@ struct geni_wrapper {
struct device *dev;
void __iomem *base;
struct clk_bulk_data ahb_clks[NUM_AHB_CLKS];
+ struct geni_icc_path to_core;
};
static const char * const icc_path_names[] = {"qup-core", "qup-config",
"qup-memory"};
+static struct geni_wrapper *earlycon_wrapper;
+
#define QUP_HW_VER_REG 0x4
/* Common SE registers */
@@ -812,11 +816,38 @@ int geni_icc_disable(struct geni_se *se)
}
EXPORT_SYMBOL(geni_icc_disable);
+void geni_remove_earlycon_icc_vote(void)
+{
+ struct geni_wrapper *wrapper;
+ struct device_node *parent;
+ struct device_node *child;
+
+ if (!earlycon_wrapper)
+ return;
+
+ wrapper = earlycon_wrapper;
+ parent = of_get_next_parent(wrapper->dev->of_node);
+ for_each_child_of_node(parent, child) {
+ if (!of_device_is_compatible(child, "qcom,geni-se-qup"))
+ continue;
+ wrapper = platform_get_drvdata(of_find_device_by_node(child));
+ icc_put(wrapper->to_core.path);
+ wrapper->to_core.path = NULL;
+
+ }
+ of_node_put(parent);
+
+ earlycon_wrapper = NULL;
+}
+EXPORT_SYMBOL(geni_remove_earlycon_icc_vote);
+
static int geni_se_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct resource *res;
struct geni_wrapper *wrapper;
+ struct console __maybe_unused *bcon;
+ bool __maybe_unused has_earlycon = false;
int ret;
wrapper = devm_kzalloc(dev, sizeof(*wrapper), GFP_KERNEL);
@@ -839,6 +870,43 @@ static int geni_se_probe(struct platform_device *pdev)
}
}
+#ifdef CONFIG_SERIAL_EARLYCON
+ for_each_console(bcon) {
+ if (!strcmp(bcon->name, "qcom_geni")) {
+ has_earlycon = true;
+ break;
+ }
+ }
+ if (!has_earlycon)
+ goto exit;
+
+ wrapper->to_core.path = devm_of_icc_get(dev, "qup-core");
+ if (IS_ERR(wrapper->to_core.path))
+ return PTR_ERR(wrapper->to_core.path);
+ /*
+ * Put minmal BW request on core clocks on behalf of early console.
+ * The vote will be removed earlycon exit function.
+ *
+ * Note: We are putting vote on each QUP wrapper instead only to which
+ * earlycon is connected because QUP core clock of different wrapper
+ * share same voltage domain. If core1 is put to 0, then core2 will
+ * also run at 0, if not voted. Default ICC vote will be removed ASA
+ * we touch any of the core clock.
+ * core1 = core2 = max(core1, core2)
+ */
+ ret = icc_set_bw(wrapper->to_core.path, GENI_DEFAULT_BW,
+ GENI_DEFAULT_BW);
+ if (ret) {
+ dev_err(&pdev->dev, "%s: ICC BW voting failed for core :%d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ if (of_get_compatible_child(pdev->dev.of_node, "qcom,geni-debug-uart"))
+ earlycon_wrapper = wrapper;
+ of_node_put(pdev->dev.of_node);
+#endif
+exit:
dev_set_drvdata(dev, wrapper);
dev_dbg(dev, "GENI SE Driver probed\n");
return devm_of_platform_populate(dev);
diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qcom_geni_serial.c
index 6119090..8c5d97c 100644
--- a/drivers/tty/serial/qcom_geni_serial.c
+++ b/drivers/tty/serial/qcom_geni_serial.c
@@ -1090,6 +1090,12 @@ static void qcom_geni_serial_earlycon_write(struct console *con,
__qcom_geni_serial_console_write(&dev->port, s, n);
}
+static int qcom_geni_serial_earlycon_exit(struct console *con)
+{
+ geni_remove_earlycon_icc_vote();
+ return 0;
+}
+
static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
const char *opt)
{
@@ -1135,6 +1141,7 @@ static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
dev->con->write = qcom_geni_serial_earlycon_write;
+ dev->con->exit = qcom_geni_serial_earlycon_exit;
dev->con->setup = NULL;
return 0;
}
diff --git a/include/linux/qcom-geni-se.h b/include/linux/qcom-geni-se.h
index 7afa08d..51e9e9b 100644
--- a/include/linux/qcom-geni-se.h
+++ b/include/linux/qcom-geni-se.h
@@ -458,5 +458,7 @@ void geni_icc_bw_init(struct geni_icc_path *icc_paths, unsigned int avg_bw,
int geni_icc_enable(struct geni_se *se);
int geni_icc_disable(struct geni_se *se);
+
+void geni_remove_earlycon_icc_vote(void);
#endif
#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH V6 1/7] soc: qcom: geni: Support for ICC voting
From: Akash Asthana @ 2020-05-21 8:29 UTC (permalink / raw)
To: gregkh, agross, bjorn.andersson, wsa, broonie, mark.rutland,
robh+dt
Cc: linux-i2c, linux-spi, devicetree, swboyd, mgautam, linux-arm-msm,
linux-serial, mka, dianders, msavaliy, evgreen, Akash Asthana
In-Reply-To: <1590049764-20912-1-git-send-email-akashast@codeaurora.org>
Add necessary macros and structure variables to support ICC BW
voting from individual SE drivers.
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
---
Changes in V2:
- As per Bjorn's comment dropped enums for ICC paths, given the three
paths individual members
Changes in V3:
- Add geni_icc_get, geni_icc_vote_on and geni_icc_vote_off as helper API.
- Add geni_icc_path structure in common header
Changes in V4:
- As per Bjorn's comment print error message in geni_icc_get if return
value is not -EPROBE_DEFER.
- As per Bjorn's comment remove NULL on path before calling icc_set_bw
API.
- As per Bjorn's comment drop __func__ print.
- As per Matthias's comment, make ICC path a array instead of individual
member entry in geni_se struct.
Changes in V5:
- As per Matthias's comment defined enums for ICC paths.
- Integrate icc_enable/disable with power on/off call for driver.
- As per Matthias's comment added icc_path_names array to print icc path name
in failure case.
- As per Georgi's suggestion assume peak_bw = avg_bw if not mentioned.
Changes in V6:
- Addressed nitpicks from Matthias.
Note: I have ignored below check patch suggestion because it was throwing
compilation error as 'icc_ddr' is not compile time comstant.
WARNING: char * array declaration might be better as static const
- FILE: drivers/soc/qcom/qcom-geni-se.c:726:
- const char *icc_names[] = {"qup-core", "qup-config", icc_ddr};
drivers/soc/qcom/qcom-geni-se.c | 92 +++++++++++++++++++++++++++++++++++++++++
include/linux/qcom-geni-se.h | 42 +++++++++++++++++++
2 files changed, 134 insertions(+)
diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c
index 7d622ea..0b2526d 100644
--- a/drivers/soc/qcom/qcom-geni-se.c
+++ b/drivers/soc/qcom/qcom-geni-se.c
@@ -92,6 +92,9 @@ struct geni_wrapper {
struct clk_bulk_data ahb_clks[NUM_AHB_CLKS];
};
+static const char * const icc_path_names[] = {"qup-core", "qup-config",
+ "qup-memory"};
+
#define QUP_HW_VER_REG 0x4
/* Common SE registers */
@@ -720,6 +723,95 @@ void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
}
EXPORT_SYMBOL(geni_se_rx_dma_unprep);
+int geni_icc_get(struct geni_se *se, const char *icc_ddr)
+{
+ int i, err;
+ const char *icc_names[] = {"qup-core", "qup-config", icc_ddr};
+
+ for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
+ if (!icc_names[i])
+ continue;
+
+ se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]);
+ if (IS_ERR(se->icc_paths[i].path))
+ goto err;
+ }
+
+ return 0;
+
+err:
+ err = PTR_ERR(se->icc_paths[i].path);
+ if (err != -EPROBE_DEFER)
+ dev_err_ratelimited(se->dev, "Failed to get ICC path:%s :%d\n",
+ icc_names[i], err);
+ return err;
+
+}
+EXPORT_SYMBOL(geni_icc_get);
+
+void geni_icc_bw_init(struct geni_icc_path *icc_paths, unsigned int avg_bw,
+ unsigned int peak_bw)
+{
+ if (!peak_bw)
+ peak_bw = avg_bw;
+ icc_paths->avg_bw = avg_bw;
+ icc_paths->peak_bw = peak_bw;
+}
+EXPORT_SYMBOL(geni_icc_bw_init);
+
+int geni_icc_set_bw(struct geni_se *se)
+{
+ int i, ret;
+
+ for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
+ ret = icc_set_bw(se->icc_paths[i].path,
+ se->icc_paths[i].avg_bw, se->icc_paths[i].peak_bw);
+ if (ret) {
+ dev_err_ratelimited(se->dev, "ICC BW voting failed on path:%s :%d\n",
+ icc_path_names[i], ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(geni_icc_set_bw);
+
+/* To do: Replace this by icc_bulk_enable once it's implemented in ICC core */
+int geni_icc_enable(struct geni_se *se)
+{
+ int i, ret;
+
+ for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
+ ret = icc_enable(se->icc_paths[i].path);
+ if (ret) {
+ dev_err_ratelimited(se->dev, "ICC enable failed on path:%s :%d\n",
+ icc_path_names[i], ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(geni_icc_enable);
+
+int geni_icc_disable(struct geni_se *se)
+{
+ int i, ret;
+
+ for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
+ ret = icc_disable(se->icc_paths[i].path);
+ if (ret) {
+ dev_err_ratelimited(se->dev, "ICC disable failed on path:%s :%d\n",
+ icc_path_names[i], ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(geni_icc_disable);
+
static int geni_se_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
diff --git a/include/linux/qcom-geni-se.h b/include/linux/qcom-geni-se.h
index dd46494..7afa08d 100644
--- a/include/linux/qcom-geni-se.h
+++ b/include/linux/qcom-geni-se.h
@@ -6,6 +6,8 @@
#ifndef _LINUX_QCOM_GENI_SE
#define _LINUX_QCOM_GENI_SE
+#include <linux/interconnect.h>
+
/* Transfer mode supported by GENI Serial Engines */
enum geni_se_xfer_mode {
GENI_SE_INVALID,
@@ -25,6 +27,18 @@ enum geni_se_protocol_type {
struct geni_wrapper;
struct clk;
+enum geni_icc_path_index {
+ GENI_TO_CORE,
+ CPU_TO_GENI,
+ GENI_TO_DDR
+};
+
+struct geni_icc_path {
+ struct icc_path *path;
+ unsigned int avg_bw;
+ unsigned int peak_bw;
+};
+
/**
* struct geni_se - GENI Serial Engine
* @base: Base Address of the Serial Engine's register block
@@ -33,6 +47,7 @@ struct clk;
* @clk: Handle to the core serial engine clock
* @num_clk_levels: Number of valid clock levels in clk_perf_tbl
* @clk_perf_tbl: Table of clock frequency input to serial engine clock
+ * @icc_paths: Array of ICC paths for SE
*/
struct geni_se {
void __iomem *base;
@@ -41,6 +56,7 @@ struct geni_se {
struct clk *clk;
unsigned int num_clk_levels;
unsigned long *clk_perf_tbl;
+ struct geni_icc_path icc_paths[3];
};
/* Common SE registers */
@@ -229,6 +245,21 @@ struct geni_se {
#define GENI_SE_VERSION_MINOR(ver) ((ver & HW_VER_MINOR_MASK) >> HW_VER_MINOR_SHFT)
#define GENI_SE_VERSION_STEP(ver) (ver & HW_VER_STEP_MASK)
+/*
+ * Define bandwidth thresholds that cause the underlying Core 2X interconnect
+ * clock to run at the named frequency. These baseline values are recommended
+ * by the hardware team, and are not dynamically scaled with GENI bandwidth
+ * beyond basic on/off.
+ */
+#define CORE_2X_19_2_MHZ 960
+#define CORE_2X_50_MHZ 2500
+#define CORE_2X_100_MHZ 5000
+#define CORE_2X_150_MHZ 7500
+#define CORE_2X_200_MHZ 10000
+#define CORE_2X_236_MHZ 16383
+
+#define GENI_DEFAULT_BW Bps_to_icc(1000)
+
#if IS_ENABLED(CONFIG_QCOM_GENI_SE)
u32 geni_se_get_qup_hw_version(struct geni_se *se);
@@ -416,5 +447,16 @@ int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len);
+
+int geni_icc_get(struct geni_se *se, const char *icc_ddr);
+
+int geni_icc_set_bw(struct geni_se *se);
+
+void geni_icc_bw_init(struct geni_icc_path *icc_paths, unsigned int avg_bw,
+ unsigned int peak_bw);
+
+int geni_icc_enable(struct geni_se *se);
+
+int geni_icc_disable(struct geni_se *se);
#endif
#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH V6 0/7] [PATCH V5 0/7] Add interconnect support to QSPI and QUP drivers
From: Akash Asthana @ 2020-05-21 8:29 UTC (permalink / raw)
To: gregkh, agross, bjorn.andersson, wsa, broonie, mark.rutland,
robh+dt
Cc: linux-i2c, linux-spi, devicetree, swboyd, mgautam, linux-arm-msm,
linux-serial, mka, dianders, msavaliy, evgreen, Akash Asthana
V5 depend on below patches.
- https://lore.kernel.org/patchwork/patch/1237642/ [Add helpers
for enabling/disabling a path]
- https://patchwork.kernel.org/patch/11491027/ [Add devm_of_icc_get()
as exported API for users ]
dt-binding patch for QUP drivers.
- https://patchwork.kernel.org/patch/11534149/ [Convert QUP bindings
to YAML and add ICC, pin swap doc]
High level design:
- QUP wrapper/common driver.
Vote for QUP core on behalf of earlycon from probe.
Remove BW vote during earlycon exit call
- SERIAL driver.
Vote only for CPU/CORE path because driver is in FIFO mode only
Vote/unvote from qcom_geni_serial_pm func.
Bump up the CPU vote from set_termios call based on real time need
- I2C driver.
Vote for CORE/CPU/DDR path
Vote/unvote from runtime resume/suspend callback
As bus speed for I2C is fixed from probe itself no need for bump up.
- SPI QUP driver.
Vote only for CPU/CORE path because driver is in FIFO mode only
Vote/unvote from runtime resume/suspend callback
Bump up CPU vote based on real time need per transfer.
- QSPI driver.
Vote only for CPU path
Vote/unvote from runtime resume/suspend callback
Bump up CPU vote based on real time need per transfer.
Changes in V2:
- Add devm_of_icc_get() API interconnect core.
- Add ICC support to common driver to fix earlyconsole crash.
Changes in V3:
- Define common ICC APIs in geni-se driver and use it across geni based
I2C,SPI and UART driver.
Changes in V4:
- Add a patch to ICC core to scale peak requirement
as twice of average if it is not mentioned explicilty.
Changes in V5:
- As per Georgi's suggestion removed patch from ICC core for assuming
peak_bw as twice of average when it's not mentioned, instead assume it
equall to avg_bw and keep this assumption in ICC client itself.
- As per Matthias suggestion use enum for GENI QUP ICC paths.
Changes in V6:
- No Major change
Akash Asthana (7):
soc: qcom: geni: Support for ICC voting
soc: qcom-geni-se: Add interconnect support to fix earlycon crash
i2c: i2c-qcom-geni: Add interconnect support
spi: spi-geni-qcom: Add interconnect support
tty: serial: qcom_geni_serial: Add interconnect support
spi: spi-qcom-qspi: Add interconnect support
arm64: dts: sc7180: Add interconnect for QUP and QSPI
arch/arm64/boot/dts/qcom/sc7180.dtsi | 127 +++++++++++++++++++++++++++
drivers/i2c/busses/i2c-qcom-geni.c | 29 +++++-
drivers/soc/qcom/qcom-geni-se.c | 160 ++++++++++++++++++++++++++++++++++
drivers/spi/spi-geni-qcom.c | 31 ++++++-
drivers/spi/spi-qcom-qspi.c | 59 ++++++++++++-
drivers/tty/serial/qcom_geni_serial.c | 38 +++++++-
include/linux/qcom-geni-se.h | 44 ++++++++++
7 files changed, 482 insertions(+), 6 deletions(-)
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [PATCH 09/15] device core: Add ability to handle multiple dma offsets
From: Christoph Hellwig @ 2020-05-21 8:19 UTC (permalink / raw)
To: Dan Williams
Cc: Jim Quinlan, Christoph Hellwig, Nicolas Saenz Julienne,
Rob Herring, Frank Rowand, Marek Szyprowski, Robin Murphy,
Greg Kroah-Hartman, Suzuki K Poulose, Saravana Kannan,
Heikki Krogerus, Rafael J. Wysocki,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE, open list,
open list:DMA MAPPING HELPERS
In-Reply-To: <CAPcyv4jOGE0F4wCFM+cC8g=SofiXaNCBfAEPumUv=7nCM6KJ6Q@mail.gmail.com>
On Wed, May 20, 2020 at 03:36:16PM -0700, Dan Williams wrote:
> Certainly blindly cc'ing everyone recommended by
> scripts/get_maintainers.pl is overkill, but finding that subset is a
> bit of an art.
Yes. But I'd rather be not Cced and just find the complete thread on
a list. But all the lists I'm on and have managed to read through
yesterday didn't have the full series either.
^ permalink raw reply
* [GIT PULL] Immutable branch between MFD, Power and RTC due for the v5.8 merge window
From: Lee Jones @ 2020-05-21 8:16 UTC (permalink / raw)
To: Hsin-Hsiung Wang
Cc: Rob Herring, Matthias Brugger, Alexandre Belloni, drinkcat,
Sean Wang, Sebastian Reichel, Eddie Huang, Alessandro Zummo,
Frank Wunderlich, Josef Friedl, Richard Fontana, Thomas Gleixner,
Ran Bi, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, linux-pm, linux-rtc, srv_heupstream
In-Reply-To: <1587438012-24832-1-git-send-email-hsin-hsiung.wang@mediatek.com>
Enjoy!
The following changes since commit 8f3d9f354286745c751374f5f1fcafee6b3f3136:
Linux 5.7-rc1 (2020-04-12 12:35:55 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git ib-mfd-power-rtc-v5.8
for you to fetch changes up to 29ee40091e27615530c0ba7773a2879d8266381e:
rtc: mt6397: Add support for the MediaTek MT6358 RTC (2020-05-21 08:55:48 +0100)
----------------------------------------------------------------
Immutable branch between MFD, Power and RTC due for the v5.8 merge window
----------------------------------------------------------------
Hsin-Hsiung Wang (4):
mfd: mt6397: Modify suspend/resume behavior
mfd: mt6397: Trim probe function to support different chips more cleanly
dt-bindings: mfd: Add compatible for the MediaTek MT6358 PMIC
mfd: Add support for the MediaTek MT6358 PMIC
Ran Bi (1):
rtc: mt6397: Add support for the MediaTek MT6358 RTC
Documentation/devicetree/bindings/mfd/mt6397.txt | 14 +-
drivers/mfd/Makefile | 2 +-
drivers/mfd/mt6358-irq.c | 235 +++++++++++++++++++
drivers/mfd/mt6397-core.c | 101 ++++----
drivers/mfd/mt6397-irq.c | 35 ++-
drivers/power/reset/mt6323-poweroff.c | 2 +-
drivers/rtc/rtc-mt6397.c | 18 +-
include/linux/mfd/mt6358/core.h | 158 +++++++++++++
include/linux/mfd/mt6358/registers.h | 282 +++++++++++++++++++++++
include/linux/mfd/mt6397/core.h | 5 +
include/linux/mfd/mt6397/rtc.h | 9 +-
11 files changed, 799 insertions(+), 62 deletions(-)
create mode 100644 drivers/mfd/mt6358-irq.c
create mode 100644 include/linux/mfd/mt6358/core.h
create mode 100644 include/linux/mfd/mt6358/registers.h
--
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* RE: [PATCH v4 3/9] usb: dwc3: Increase timeout for CmdAct cleared by device controller
From: Jun Li @ 2020-05-21 7:47 UTC (permalink / raw)
To: Felipe Balbi, Thinh Nguyen, Jun Li
Cc: John Stultz, lkml, Yu Chen, Greg Kroah-Hartman, Rob Herring,
Mark Rutland, ShuFan Lee, Heikki Krogerus, Suzuki K Poulose,
Chunfeng Yun, Hans de Goede, Andy Shevchenko, Valentin Schneider,
Jack Pham, Linux USB List,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Peter Chen
In-Reply-To: <87r1vdx0w4.fsf@kernel.org>
Hi Felipe,
> -----Original Message-----
> From: Felipe Balbi <balbif@gmail.com> On Behalf Of Felipe Balbi
> Sent: 2020年5月21日 14:23
> To: Thinh Nguyen <Thinh.Nguyen@synopsys.com>; Jun Li <jun.li@nxp.com>; Jun Li
> <lijun.kernel@gmail.com>
> Cc: John Stultz <john.stultz@linaro.org>; lkml <linux-kernel@vger.kernel.org>; Yu
> Chen <chenyu56@huawei.com>; Greg Kroah-Hartman <gregkh@linuxfoundation.org>; Rob
> Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>; ShuFan Lee
> <shufan_lee@richtek.com>; Heikki Krogerus <heikki.krogerus@linux.intel.com>;
> Suzuki K Poulose <suzuki.poulose@arm.com>; Chunfeng Yun
> <chunfeng.yun@mediatek.com>; Hans de Goede <hdegoede@redhat.com>; Andy Shevchenko
> <andy.shevchenko@gmail.com>; Valentin Schneider <valentin.schneider@arm.com>;
> Jack Pham <jackp@codeaurora.org>; Linux USB List <linux-usb@vger.kernel.org>; open
> list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS <devicetree@vger.kernel.org>;
> Peter Chen <peter.chen@nxp.com>
> Subject: Re: [PATCH v4 3/9] usb: dwc3: Increase timeout for CmdAct cleared by device
> controller
>
>
> Hi Jun,
>
> Felipe Balbi <balbi@kernel.org> writes:
> >> In any case, increasing the timeout should be fine with me. It maybe
> >> difficult to determine the max timeout base on the slowest clock rate
> >> and number of cycles. Different controller and controller versions
> >> behave differently and may have different number of clock cycles to
> >> complete a command.
> >>
> >> The RTL engineer recommended timeout to be at least 1ms (which maybe
> >> more than the polling rate of this patch). I'm fine with either the
> >> rate provided by this tested patch or higher.
> >
> > A whole ms waiting for a command to complete? Wow, that's a lot of
> > time blocking the CPU. It looks like, perhaps, we should move to
> > command completion interrupts. The difficulty here is that we issue
> > commands from within the interrupt handler and, as such, can't
> > wait_for_completion().
> >
> > Meanwhile, we will take the timeout increase I guess, otherwise NXP
> > won't have a working setup.
>
> patch 1 in this series doesn't apply to testing/next. Care to rebase and resend?
Sure, I will rebase and resend this patch with timeout loop 5000.
Thanks
Li Jun
>
> Thank you
>
> --
> balbi
^ permalink raw reply
* Re: [PATCH v13 5/6] rtc: mt6397: Add support for the MediaTek MT6358 RTC
From: Lee Jones @ 2020-05-21 7:47 UTC (permalink / raw)
To: Matthias Brugger
Cc: Hsin-Hsiung Wang, Rob Herring, Alexandre Belloni, drinkcat,
Sean Wang, Sebastian Reichel, Eddie Huang, Alessandro Zummo,
Frank Wunderlich, Josef Friedl, Richard Fontana, Thomas Gleixner,
Ran Bi, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, linux-pm, linux-rtc, srv_heupstream
In-Reply-To: <27c107b3-6ea8-e6f9-697c-7c3c4479008c@gmail.com>
On Sat, 16 May 2020, Matthias Brugger wrote:
> Hi Lee,
>
> On 21/04/2020 05:00, Hsin-Hsiung Wang wrote:
> > From: Ran Bi <ran.bi@mediatek.com>
> >
> > This add support for the MediaTek MT6358 RTC. Driver using
> > compatible data to store different RTC_WRTGR address offset.
> > This replace RTC_WRTGR to RTC_WRTGR_MT6323 in mt6323-poweroff
> > driver which only needed by armv7 CPU without ATF.
> >
> > Signed-off-by: Ran Bi <ran.bi@mediatek.com>
> > Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
> > Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
> > Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> > Acked-by: Sebastian Reichel <sre@kernel.org>
> > Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
>
> We have Acked-by from rtc and reset drivers maintainers. Are you OK to take them
> through your mfd branch?
>
> Are you planning to queue them for v5.8?
>
> Just asking because if so I'd queue patch 6 through my tree.
Yes, please take patch 6.
--
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* RE: [PATCH v4 3/9] usb: dwc3: Increase timeout for CmdAct cleared by device controller
From: Jun Li @ 2020-05-21 7:33 UTC (permalink / raw)
To: Thinh Nguyen, Felipe Balbi, Jun Li
Cc: John Stultz, lkml, Yu Chen, Greg Kroah-Hartman, Rob Herring,
Mark Rutland, ShuFan Lee, Heikki Krogerus, Suzuki K Poulose,
Chunfeng Yun, Hans de Goede, Andy Shevchenko, Valentin Schneider,
Jack Pham, Linux USB List,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Peter Chen
In-Reply-To: <1c16bdb6-8d8d-1e1b-f08b-b3963f905eb0@synopsys.com>
Hi Thinh,
> -----Original Message-----
> From: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
> Sent: 2020年5月21日 9:56
> To: Jun Li <jun.li@nxp.com>; Felipe Balbi <balbi@kernel.org>; Jun Li
> <lijun.kernel@gmail.com>
> Cc: John Stultz <john.stultz@linaro.org>; lkml <linux-kernel@vger.kernel.org>; Yu
> Chen <chenyu56@huawei.com>; Greg Kroah-Hartman <gregkh@linuxfoundation.org>; Rob
> Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>; ShuFan Lee
> <shufan_lee@richtek.com>; Heikki Krogerus <heikki.krogerus@linux.intel.com>;
> Suzuki K Poulose <suzuki.poulose@arm.com>; Chunfeng Yun
> <chunfeng.yun@mediatek.com>; Hans de Goede <hdegoede@redhat.com>; Andy Shevchenko
> <andy.shevchenko@gmail.com>; Valentin Schneider <valentin.schneider@arm.com>;
> Jack Pham <jackp@codeaurora.org>; Linux USB List <linux-usb@vger.kernel.org>; open
> list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS <devicetree@vger.kernel.org>;
> Peter Chen <peter.chen@nxp.com>
> Subject: Re: [PATCH v4 3/9] usb: dwc3: Increase timeout for CmdAct cleared by device
> controller
>
> Thinh Nguyen wrote:
> > Jun Li wrote:
> >> Hi
> >>
> >>> -----Original Message-----
> >>> From: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
> >>> Sent: 2020年5月19日 14:46
> >>> To: Jun Li <jun.li@nxp.com>; Felipe Balbi <balbi@kernel.org>; Jun Li
> >>> <lijun.kernel@gmail.com>
> >>> Cc: John Stultz <john.stultz@linaro.org>; lkml
> >>> <linux-kernel@vger.kernel.org>; Yu Chen <chenyu56@huawei.com>; Greg
> >>> Kroah-Hartman <gregkh@linuxfoundation.org>; Rob Herring
> >>> <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>; ShuFan
> >>> Lee <shufan_lee@richtek.com>; Heikki Krogerus
> >>> <heikki.krogerus@linux.intel.com>;
> >>> Suzuki K Poulose <suzuki.poulose@arm.com>; Chunfeng Yun
> >>> <chunfeng.yun@mediatek.com>; Hans de Goede <hdegoede@redhat.com>;
> >>> Andy Shevchenko <andy.shevchenko@gmail.com>; Valentin Schneider
> >>> <valentin.schneider@arm.com>; Jack Pham <jackp@codeaurora.org>;
> >>> Linux USB List <linux-usb@vger.kernel.org>; open list:OPEN FIRMWARE
> >>> AND FLATTENED DEVICE TREE BINDINGS <devicetree@vger.kernel.org>;
> >>> Peter Chen <peter.chen@nxp.com>
> >>> Subject: Re: [PATCH v4 3/9] usb: dwc3: Increase timeout for CmdAct
> >>> cleared by device controller
> >>>
> >>> Thinh Nguyen wrote:
> >>>> Jun Li wrote:
> >>>>>> -----Original Message-----
> >>>>>> From: Felipe Balbi <balbif@gmail.com> On Behalf Of Felipe Balbi
> >>>>>> Sent: 2020年5月16日 19:57
> >>>>>> To: Jun Li <jun.li@nxp.com>; Thinh Nguyen
> >>>>>> <Thinh.Nguyen@synopsys.com>; Jun Li <lijun.kernel@gmail.com>
> >>>>>> Cc: John Stultz <john.stultz@linaro.org>; lkml
> >>>>>> <linux-kernel@vger.kernel.org>; Yu Chen <chenyu56@huawei.com>;
> >>>>>> Greg Kroah-Hartman <gregkh@linuxfoundation.org>; Rob Herring
> >>>>>> <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>; ShuFan
> >>>>>> Lee <shufan_lee@richtek.com>; Heikki Krogerus
> >>>>>> <heikki.krogerus@linux.intel.com>;
> >>>>>> Suzuki K Poulose <suzuki.poulose@arm.com>; Chunfeng Yun
> >>>>>> <chunfeng.yun@mediatek.com>; Hans de Goede <hdegoede@redhat.com>;
> >>>>>> Andy Shevchenko <andy.shevchenko@gmail.com>; Valentin Schneider
> >>>>>> <valentin.schneider@arm.com>; Jack Pham <jackp@codeaurora.org>;
> >>>>>> Linux USB List <linux-usb@vger.kernel.org>; open list:OPEN
> >>>>>> FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> >>>>>> <devicetree@vger.kernel.org>; Peter Chen <peter.chen@nxp.com>;
> >>>>>> Thinh Nguyen <Thinh.Nguyen@synopsys.com>
> >>>>>> Subject: RE: [PATCH v4 3/9] usb: dwc3: Increase timeout for
> >>>>>> CmdAct cleared by device controller
> >>>>>>
> >>>>>>
> >>>>>> Hi,
> >>>>>>
> >>>>>> Jun Li <jun.li@nxp.com> writes:
> >>>>>>>>>> Hi Thinh, could you comment this?
> >>>>>>>>> You only need to wake up the usb2 phy when issuing the command
> >>>>>>>>> while running in highspeed or below. If you're running in SS
> >>>>>>>>> or higher, internally the controller does it for you for usb3 phy.
> >>>>>>>>> In Jun's case, it seems like it takes longer for his phy to wake up.
> >>>>>>>>>
> >>>>>>>>> IMO, in this case, I think it's fine to increase the command timeout.
> >>>>>>>> Is there an upper limit to this? Is 32k clock the slowest that
> >>>>>>>> can be fed to the PHY as a suspend clock?
> >>>>>>> Yes, 32K clock is the slowest, Per DWC3 document on Power Down
> >>>>>>> Scale (bits 31:19 of GCTL):
> >>>>>>>
> >>>>>>> "Power Down Scale (PwrDnScale)
> >>>>>>> The USB3 suspend_clk input replaces pipe3_rx_pclk as a clock
> >>>>>>> source to a small part of the USB3 controller that operates when
> >>>>>>> the SS PHY is in its lowest power (P3) state, and therefore does not provide
> a clock.
> >>>>>>> The Power Down Scale field specifies how many suspend_clk
> >>>>>>> periods fit into a 16 kHz clock period. When performing the
> >>>>>>> division, round up the remainder.
> >>>>>>> For example, when using an 8-bit/16-bit/32-bit PHY and 25-MHz
> >>>>>>> Suspend clock, Power Down Scale = 25000 kHz/16 kHz = 13'd1563
> >>>>>>> (rounder up)
> >>>>>>> Note:
> >>>>>>> - Minimum Suspend clock frequency is 32 kHz
> >>>>>>> - Maximum Suspend clock frequency is 125 MHz"
> >>>>>> Cool, now do we have an upper bound for how many clock cycles it
> >>>>>> takes to wake up the PHY?
> >>>>> My understanding is this ep command does not wake up the SS PHY,
> >>>>> the SS PHY still stays at P3 when execute this ep command. The
> >>>>> time required here is to wait controller complete something for
> >>>>> this ep command with 32K clock.
> >>>> Sorry I made a mistake. You're right. Just checked with one of the
> >>>> RTL engineers, and it doesn't need to wake up the phy. However, if
> >>>> it is eSS speed, it may take longer time as the command may be
> >>>> completing with the suspend clock.
> >>>>
> >>> What's the value for GCTL[7:6]?
> >> 2'b00
> >>
> >> Thanks
> >> Li Jun
> > (Sorry for the delay reply)
> >
> > If it's 0, then the ram clock should be the same as the bus_clk, which
> > is odd since you mentioned that the suspend_clk is used instead while in P3.
>
> Just checked with the RTL engineer, even if GCTL[7:6] is set to 0, internally it
> can still run with suspend clock during P3.
Thanks for your check.
>
> > Anyway, I was looking for a way maybe to improve the speed during
> > issuing a command. One way is to set GUSB3PIPECTL[17]=0, and it should
> > wakeup the phy anytime. I think Felipe suggested it. It's odd that it
> > doesn't work for you. I don't have other ideas beside increasing the
> > command timeout.
> >
>
> In any case, increasing the timeout should be fine with me. It maybe difficult to
> determine the max timeout base on the slowest clock rate and number of cycles.
> Different controller and controller versions behave differently and may have
> different number of clock cycles to complete a command.
>
> The RTL engineer recommended timeout to be at least 1ms (which maybe more than the
> polling rate of this patch). I'm fine with either the rate provided by this tested
> patch or higher.
OK, I will change the timeout to be 1ms if no object from Felipe.
thanks
Li Jun
>
> BR,
> Thinh
^ permalink raw reply
* Re: [PATCH v3 00/14] mips: Prepare MIPS-arch code for Baikal-T1 SoC support
From: Arnd Bergmann @ 2020-05-21 7:30 UTC (permalink / raw)
To: Thomas Bogendoerfer
Cc: Serge Semin, Serge Semin, Alexey Malahov, Maxim Kaurkin,
Pavel Parkhomenko, Ramil Zaripov, Ekaterina Skachko, Vadim Vlasov,
Alexey Kolotnikov, Paul Burton, Ralf Baechle, Rob Herring,
Frank Rowand, Tony Lindgren, Olof Johansson, Greg Kroah-Hartman,
Jiri Slaby, open list:BROADCOM NVRAM DRIVER, DTML,
linux-kernel@vger.kernel.org
In-Reply-To: <20200521071457.GC7309@alpha.franken.de>
On Thu, May 21, 2020 at 9:18 AM Thomas Bogendoerfer
<tsbogend@alpha.franken.de> wrote:
> On Thu, May 21, 2020 at 03:42:17AM +0300, Serge Semin wrote:
> > On Thu, May 21, 2020 at 03:34:29AM +0300, Serge Semin wrote:
> > >
> > > This patchset is rebased and tested on the mainline Linux kernel 5.7-rc4:
> > > base-commit: 0e698dfa2822 ("Linux 5.7-rc4")
> > > tag: v5.7-rc4
> >
> > Thomas,
> > Please note that this patchset is based on the Linux 5.7-rc4 tree (it most likely
> > will get cleanly applied on rc6 as well), while mips-next is still at rc1. Due
> > to that the patchset fails to be applied on mips-next. I think it would be
> > better first to merge the last Linux tree into the mips-next, then try to merge
> > this patchset in. Should you have any problem after that, please let me know.
> > I'll resend the patchset being rebased on top of the new mips-next tree.
>
> no, that's not how it works. Please rebase your patches on top of
> mips-next. Thank you.
Right, backmerges should generally be avoided. However if something
between rc1 and rc4 is required to make Baikal-T1 work, rebasing it to
rc1 would make it non-bisectable, which is also bad.
Serge, are you aware of something in -rc4 that is needed as a dependency?
Arnd
^ permalink raw reply
* Re: [PATCH v3 2/2] mfd: ene-kb3930: Add driver for ENE KB3930 Embedded Controller
From: Lee Jones @ 2020-05-21 7:27 UTC (permalink / raw)
To: Lubomir Rintel; +Cc: Rob Herring, Mark Rutland, devicetree, linux-kernel
In-Reply-To: <20200520185955.2144252-3-lkundrak@v3.sk>
On Wed, 20 May 2020, Lubomir Rintel wrote:
> This driver provides access to the EC RAM of said embedded controller
> attached to the I2C bus as well as optionally supporting its slightly weird
> power-off/restart protocol.
>
> A particular implementation of the EC firmware can be identified by a
> model byte. If this driver identifies the Dell Ariel platform, it
> registers the appropriate cells.
>
> Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
>
> ---
> Changes since v2:
> - Sort the includes
> - s/EC_MODEL_ID/EC_MODEL/
> - Add a couple of clarifying comments
> - Use #defines for values used in poweroff routine
> - Remove priority from a restart notifier block
> - s/priv/ddata/
> - s/ec_ram/ram_regmap/ for the regmap name
> - Fix the error handling when getting off gpios was not successful
> - Remove a useless dev_info at the end of probe()
> - Use i2c probe_new() callback, drop i2c_device_id
> - Modify the logic in checking the model ID
>
> drivers/mfd/Kconfig | 10 ++
> drivers/mfd/Makefile | 1 +
> drivers/mfd/ene-kb3930.c | 215 +++++++++++++++++++++++++++++++++++++++
> 3 files changed, 226 insertions(+)
> create mode 100644 drivers/mfd/ene-kb3930.c
Really starting to take shape.
Just a couple of nits, then we're good to go.
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index 0a59249198d3..dae18a2beab5 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -398,6 +398,16 @@ config MFD_DLN2
> etc. must be enabled in order to use the functionality of
> the device.
>
> +config MFD_ENE_KB3930
> + tristate "ENE KB3930 Embedded Controller support"
> + depends on I2C
> + depends on MACH_MMP3_DT || COMPILE_TEST
> + select MFD_CORE
> + help
> + This adds support for accessing the registers on ENE KB3930, Embedded
> + Controller. Additional drivers such as LEDS_ARIEL must be enabled in
> + order to use the functionality of the device.
Can you mention/describe all of the sub-devices please?
[...]
> +struct kb3930 *global_kb3930;
Can we call this kb3930_power_off please.
[...]
> +static int kb3930_probe(struct i2c_client *client)
> +{
> + struct device *dev = &client->dev;
> + struct device_node *np = dev->of_node;
> + struct kb3930 *ddata;
> + unsigned int model;
> + int ret;
> +
> + if (global_kb3930)
> + return -EEXIST;
This should not happen. If .probe() is called twice, either
-EDEFER_PROBE was returned or a new device was registered.
[...]
> + /* These are the cells valid for model == 'J' only. */
> + ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO,
> + ariel_ec_cells,
> + ARRAY_SIZE(ariel_ec_cells),
> + NULL, 0, NULL);
> + if (ret < 0)
if (ret)
> + return ret;
[...]
> +static struct i2c_driver kb3930_driver = {
> + .probe_new = kb3930_probe,
> + .remove = kb3930_remove,
> + .driver = {
> + .name = "ene-kb3930",
> + .of_match_table = of_match_ptr(kb3930_dt_ids),
> + },
> +};
> +
Remove this line please.
> +module_i2c_driver(kb3930_driver);
> +
> +MODULE_AUTHOR("Lubomir Rintel <lkundrak@v3.sk>");
> +MODULE_DESCRIPTION("ENE KB3930 Embedded Controller Driver");
> +MODULE_LICENSE("Dual BSD/GPL");
--
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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