* Re: [PATCH v5, 32/32] drm/mediatek: add support for mediatek SOC MT8183
From: Matthias Brugger @ 2020-05-21 10:52 UTC (permalink / raw)
To: yongqiang.niu, CK Hu, Philipp Zabel, Rob Herring
Cc: David Airlie, Daniel Vetter, Mark Rutland, dri-devel, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <1567090254-15566-33-git-send-email-yongqiang.niu@mediatek.com>
On 29/08/2019 16:50, yongqiang.niu@mediatek.com wrote:
> From: Yongqiang Niu <yongqiang.niu@mediatek.com>
>
> This patch add support for mediatek SOC MT8183
> 1.ovl_2l share driver with ovl
> 2.rdma1 share drive with rdma0, but fifo size is different
> 3.add mt8183 mutex private data, and mmsys private data
> 4.add mt8183 main and external path module for crtc create
>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
After a long time the mmsys problem is fixed [1], so pelase rebase your series
on linux-next and resend.
Thanks a lot!
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=for-next&id=1f9adbc72824ff07bbffd776d8b51f91f5a82c18
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 18 +++++++++
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 27 ++++++++++++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 69 ++++++++++++++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_ddp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 47 ++++++++++++++++++++++
> 5 files changed, 161 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index 53f3883..94c80c2 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -373,11 +373,29 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev)
> .fmt_rgb565_is_0 = true,
> };
>
> +static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
> + .addr = DISP_REG_OVL_ADDR_MT8173,
> + .gmc_bits = 10,
> + .layer_nr = 4,
> + .fmt_rgb565_is_0 = true,
> +};
> +
> +static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
> + .addr = DISP_REG_OVL_ADDR_MT8173,
> + .gmc_bits = 10,
> + .layer_nr = 2,
> + .fmt_rgb565_is_0 = true,
> +};
> +
> static const struct of_device_id mtk_disp_ovl_driver_dt_match[] = {
> { .compatible = "mediatek,mt2701-disp-ovl",
> .data = &mt2701_ovl_driver_data},
> { .compatible = "mediatek,mt8173-disp-ovl",
> .data = &mt8173_ovl_driver_data},
> + { .compatible = "mediatek,mt8183-disp-ovl",
> + .data = &mt8183_ovl_driver_data},
> + { .compatible = "mediatek,mt8183-disp-ovl-2l",
> + .data = &mt8183_ovl_2l_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_ovl_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index 9a6f0a2..24945fe 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -62,6 +62,7 @@ struct mtk_disp_rdma {
> struct mtk_ddp_comp ddp_comp;
> struct drm_crtc *crtc;
> const struct mtk_disp_rdma_data *data;
> + u32 fifo_size;
> };
>
> static inline struct mtk_disp_rdma *comp_to_rdma(struct mtk_ddp_comp *comp)
> @@ -130,10 +131,16 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> unsigned int threshold;
> unsigned int reg;
> struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
> + u32 rdma_fifo_size;
>
> rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
> rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
>
> + if (rdma->fifo_size)
> + rdma_fifo_size = rdma->fifo_size;
> + else
> + rdma_fifo_size = RDMA_FIFO_SIZE(rdma);
> +
> /*
> * Enable FIFO underflow since DSI and DPI can't be blocked.
> * Keep the FIFO pseudo size reset default of 8 KiB. Set the
> @@ -142,7 +149,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
> */
> threshold = width * height * vrefresh * 4 * 7 / 1000000;
> reg = RDMA_FIFO_UNDERFLOW_EN |
> - RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) |
> + RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
> RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
> writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
> }
> @@ -284,6 +291,18 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev)
> return comp_id;
> }
>
> + if (of_find_property(dev->of_node, "mediatek,rdma_fifo_size", &ret)) {
> + ret = of_property_read_u32(dev->of_node,
> + "mediatek,rdma_fifo_size",
> + &priv->fifo_size);
> + if (ret) {
> + dev_err(dev, "Failed to get rdma fifo size\n");
> + return ret;
> + }
> +
> + priv->fifo_size *= SZ_1K;
> + }
> +
> ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
> &mtk_disp_rdma_funcs);
> if (ret) {
> @@ -328,11 +347,17 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev)
> .fifo_size = SZ_8K,
> };
>
> +static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
> + .fifo_size = 5 * SZ_1K,
> +};
> +
> static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
> { .compatible = "mediatek,mt2701-disp-rdma",
> .data = &mt2701_rdma_driver_data},
> { .compatible = "mediatek,mt8173-disp-rdma",
> .data = &mt8173_rdma_driver_data},
> + { .compatible = "mediatek,mt8183-disp-rdma",
> + .data = &mt8183_rdma_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index 6a7cb15..9be6eae 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -33,19 +33,31 @@
> #define DISP_REG_CONFIG_DSI_SEL 0x050
> #define DISP_REG_CONFIG_DPI_SEL 0x064
>
> +#define MT8183_DISP_OVL0_MOUT_EN 0xf00
> #define MT8183_DISP_OVL0_2L_MOUT_EN 0xf04
> #define MT8183_DISP_OVL1_2L_MOUT_EN 0xf08
> #define MT8183_DISP_DITHER0_MOUT_EN 0xf0c
> #define MT8183_DISP_PATH0_SEL_IN 0xf24
> +#define MT8183_DISP_DSI0_SEL_IN 0xf2c
> +#define MT8183_DISP_DPI0_SEL_IN 0xf30
> +#define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
> +#define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
>
> #define OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
> #define OVL1_2L_MOUT_EN_RDMA1 BIT(4)
> #define DITHER0_MOUT_IN_DSI0 BIT(0)
> #define DISP_PATH0_SEL_IN_OVL0_2L 0x1
> #define DSI0_SEL_IN_RDMA0 0x1
> +#define MT8183_DSI0_SEL_IN_RDMA1 0x3
> +#define MT8183_DPI0_SEL_IN_RDMA0 0x1
> +#define MT8183_DPI0_SEL_IN_RDMA1 0x2
> +#define MT8183_RDMA0_SOUT_COLOR0 0x1
> +#define MT8183_RDMA1_SOUT_DSI0 0x1
>
> #define MT2701_DISP_MUTEX0_MOD0 0x2c
> #define MT2701_DISP_MUTEX0_SOF0 0x30
> +#define MT8183_DISP_MUTEX0_MOD0 0x30
> +#define MT8183_DISP_MUTEX0_SOF0 0x2c
>
> #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
> #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
> @@ -56,6 +68,18 @@
>
> #define INT_MUTEX BIT(1)
>
> +#define MT8183_MUTEX_MOD_DISP_RDMA0 0
> +#define MT8183_MUTEX_MOD_DISP_RDMA1 1
> +#define MT8183_MUTEX_MOD_DISP_OVL0 9
> +#define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
> +#define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
> +#define MT8183_MUTEX_MOD_DISP_WDMA0 12
> +#define MT8183_MUTEX_MOD_DISP_COLOR0 13
> +#define MT8183_MUTEX_MOD_DISP_CCORR0 14
> +#define MT8183_MUTEX_MOD_DISP_AAL0 15
> +#define MT8183_MUTEX_MOD_DISP_GAMMA0 16
> +#define MT8183_MUTEX_MOD_DISP_DITHER0 17
> +
> #define MT8173_MUTEX_MOD_DISP_OVL0 11
> #define MT8173_MUTEX_MOD_DISP_OVL1 12
> #define MT8173_MUTEX_MOD_DISP_RDMA0 13
> @@ -105,6 +129,10 @@
> #define MUTEX_SOF_DSI2 5
> #define MUTEX_SOF_DSI3 6
>
> +#define MT8183_MUTEX_SOF_DPI0 2
> +#define MT8183_MUTEX_EOF_DSI0 (MUTEX_SOF_DSI0 << 6)
> +#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
> +
> #define OVL0_MOUT_EN_COLOR0 0x1
> #define OD_MOUT_EN_RDMA0 0x1
> #define OD1_MOUT_EN_RDMA1 BIT(16)
> @@ -240,6 +268,20 @@ struct mtk_mmsys_reg_data {
> [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
> };
>
> +static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
> + [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
> + [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
> + [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
> + [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
> + [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
> + [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
> +};
> +
> static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
> [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
> @@ -250,6 +292,12 @@ struct mtk_mmsys_reg_data {
> [DDP_MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
> };
>
> +static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_DSI3 + 1] = {
> + [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
> + [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
> + [DDP_MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
> +};
> +
> static const struct mtk_ddp_data mt2701_ddp_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -271,6 +319,13 @@ struct mtk_mmsys_reg_data {
> .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
> };
>
> +static const struct mtk_ddp_data mt8183_ddp_driver_data = {
> + .mutex_mod = mt8183_mutex_mod,
> + .mutex_sof = mt8183_mutex_sof,
> + .mutex_mod_reg = MT8183_DISP_MUTEX0_MOD0,
> + .mutex_sof_reg = MT8183_DISP_MUTEX0_SOF0,
> +};
> +
> const struct mtk_mmsys_reg_data mt2701_mmsys_reg_data = {
> .ovl0_mout_en = DISP_REG_CONFIG_DISP_OVL_MOUT_EN,
> .dsi0_sel_in = DISP_REG_CONFIG_DSI_SEL,
> @@ -287,6 +342,18 @@ struct mtk_mmsys_reg_data {
> .dsi0_sel_in_rdma1 = DSI0_SEL_IN_RDMA1,
> };
>
> +const struct mtk_mmsys_reg_data mt8183_mmsys_reg_data = {
> + .ovl0_mout_en = MT8183_DISP_OVL0_MOUT_EN,
> + .rdma0_sout_sel_in = MT8183_DISP_RDMA0_SOUT_SEL_IN,
> + .rdma0_sout_color0 = MT8183_RDMA0_SOUT_COLOR0,
> + .rdma1_sout_sel_in = MT8183_DISP_RDMA1_SOUT_SEL_IN,
> + .rdma1_sout_dsi0 = MT8183_RDMA1_SOUT_DSI0,
> + .dpi0_sel_in = MT8183_DISP_DPI0_SEL_IN,
> + .dpi0_sel_in_rdma1 = MT8183_DPI0_SEL_IN_RDMA1,
> + .dsi0_sel_in = MT8183_DISP_DSI0_SEL_IN,
> + .dsi0_sel_in_rdma1 = MT8183_DSI0_SEL_IN_RDMA1,
> +};
> +
> static unsigned int mtk_ddp_mout_en(const struct mtk_mmsys_reg_data *data,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next,
> @@ -734,6 +801,8 @@ static int mtk_ddp_remove(struct platform_device *pdev)
> .data = &mt2712_ddp_driver_data},
> { .compatible = "mediatek,mt8173-disp-mutex",
> .data = &mt8173_ddp_driver_data},
> + { .compatible = "mediatek,mt8183-disp-mutex",
> + .data = &mt8183_ddp_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, ddp_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
> index c55cc63..b74d8b9 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
> @@ -15,6 +15,7 @@
>
> extern const struct mtk_mmsys_reg_data mt2701_mmsys_reg_data;
> extern const struct mtk_mmsys_reg_data mt8173_mmsys_reg_data;
> +extern const struct mtk_mmsys_reg_data mt8183_mmsys_reg_data;
> void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
> const struct mtk_mmsys_reg_data *reg_data,
> enum mtk_ddp_comp_id cur,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 2471ce9..a4346fe 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -184,6 +184,24 @@ static int mtk_atomic_commit(struct drm_device *drm,
> DDP_COMPONENT_DPI0,
> };
>
> +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = {
> + DDP_COMPONENT_OVL0,
> + DDP_COMPONENT_OVL_2L0,
> + DDP_COMPONENT_RDMA0,
> + DDP_COMPONENT_COLOR0,
> + DDP_COMPONENT_CCORR,
> + DDP_COMPONENT_AAL0,
> + DDP_COMPONENT_GAMMA,
> + DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DSI0,
> +};
> +
> +static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
> + DDP_COMPONENT_OVL_2L1,
> + DDP_COMPONENT_RDMA1,
> + DDP_COMPONENT_DPI0,
> +};
> +
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .main_path = mt2701_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
> @@ -211,6 +229,14 @@ static int mtk_atomic_commit(struct drm_device *drm,
> .reg_data = &mt8173_mmsys_reg_data,
> };
>
> +static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> + .main_path = mt8183_mtk_ddp_main,
> + .main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
> + .ext_path = mt8183_mtk_ddp_ext,
> + .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
> + .reg_data = &mt8183_mmsys_reg_data,
> +};
> +
> static int mtk_drm_kms_init(struct drm_device *drm)
> {
> struct mtk_drm_private *private = drm->dev_private;
> @@ -409,12 +435,22 @@ static void mtk_drm_unbind(struct device *dev)
> .data = (void *)MTK_DISP_OVL },
> { .compatible = "mediatek,mt8173-disp-ovl",
> .data = (void *)MTK_DISP_OVL },
> + { .compatible = "mediatek,mt8183-disp-ovl",
> + .data = (void *)MTK_DISP_OVL },
> + { .compatible = "mediatek,mt8183-disp-ovl-2l",
> + .data = (void *)MTK_DISP_OVL_2L },
> { .compatible = "mediatek,mt2701-disp-rdma",
> .data = (void *)MTK_DISP_RDMA },
> { .compatible = "mediatek,mt8173-disp-rdma",
> .data = (void *)MTK_DISP_RDMA },
> + { .compatible = "mediatek,mt8183-disp-rdma",
> + .data = (void *)MTK_DISP_RDMA },
> + { .compatible = "mediatek,mt8183-disp-rdma1",
> + .data = (void *)MTK_DISP_RDMA },
> { .compatible = "mediatek,mt8173-disp-wdma",
> .data = (void *)MTK_DISP_WDMA },
> + { .compatible = "mediatek,mt8183-disp-ccorr",
> + .data = (void *)MTK_DISP_CCORR },
> { .compatible = "mediatek,mt2701-disp-color",
> .data = (void *)MTK_DISP_COLOR },
> { .compatible = "mediatek,mt8173-disp-color",
> @@ -423,22 +459,30 @@ static void mtk_drm_unbind(struct device *dev)
> .data = (void *)MTK_DISP_AAL},
> { .compatible = "mediatek,mt8173-disp-gamma",
> .data = (void *)MTK_DISP_GAMMA, },
> + { .compatible = "mediatek,mt8183-disp-dither",
> + .data = (void *)MTK_DISP_DITHER },
> { .compatible = "mediatek,mt8173-disp-ufoe",
> .data = (void *)MTK_DISP_UFOE },
> { .compatible = "mediatek,mt2701-dsi",
> .data = (void *)MTK_DSI },
> { .compatible = "mediatek,mt8173-dsi",
> .data = (void *)MTK_DSI },
> + { .compatible = "mediatek,mt8183-dsi",
> + .data = (void *)MTK_DSI },
> { .compatible = "mediatek,mt2701-dpi",
> .data = (void *)MTK_DPI },
> { .compatible = "mediatek,mt8173-dpi",
> .data = (void *)MTK_DPI },
> + { .compatible = "mediatek,mt8183-dpi",
> + .data = (void *)MTK_DPI },
> { .compatible = "mediatek,mt2701-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt2712-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt8173-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> + { .compatible = "mediatek,mt8183-disp-mutex",
> + .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt2701-disp-pwm",
> .data = (void *)MTK_DISP_BLS },
> { .compatible = "mediatek,mt8173-disp-pwm",
> @@ -514,6 +558,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
> */
> if (comp_type == MTK_DISP_COLOR ||
> comp_type == MTK_DISP_OVL ||
> + comp_type == MTK_DISP_OVL_2L ||
> comp_type == MTK_DISP_RDMA ||
> comp_type == MTK_DSI ||
> comp_type == MTK_DPI) {
> @@ -613,6 +658,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
> .data = &mt2712_mmsys_driver_data},
> { .compatible = "mediatek,mt8173-mmsys",
> .data = &mt8173_mmsys_driver_data},
> + { .compatible = "mediatek,mt8183-display",
> + .data = &mt8183_mmsys_driver_data},
> { }
> };
>
>
^ permalink raw reply
* RE: [PATCH v2 2/2] arm64: dts: imx8mn-ddr4-evk: correct ldo1/ldo2 voltage range
From: Aisheng Dong @ 2020-05-21 10:51 UTC (permalink / raw)
To: Robin Gong, robh+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, festevam@gmail.com, Anson Huang, Peng Fan
Cc: kernel@pengutronix.de, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dl-linux-imx
In-Reply-To: <1590070674-23027-2-git-send-email-yibin.gong@nxp.com>
> From: Robin Gong <yibin.gong@nxp.com>
> Sent: Thursday, May 21, 2020 10:18 PM
>
> Correct ldo1 voltage range from wrong high group(3.0v~3.3v) to low group
> (1.6v~1.9v) because the ldo1 should be 1.8v. Actually, two voltage groups have
> been supported at bd718x7-regulator driver, hence, just corrrect the voltage
> range to 1.6v~3.3v. For ldo2@0.8v, correct voltage range too.
> Otherwise, ldo1 would be kept @3.0v and ldo2@0.9v which violate i.mx8mn
> datasheet as the below warning log in kernel:
>
> [ 0.995524] LDO1: Bringing 1800000uV into 3000000-3000000uV
> [ 0.999196] LDO2: Bringing 800000uV into 900000-900000uV
>
> Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Regards
Aisheng
^ permalink raw reply
* RE: [PATCH v2 1/2] arm64: dts: imx8mm-evk: correct ldo1/ldo2 voltage range
From: Aisheng Dong @ 2020-05-21 10:51 UTC (permalink / raw)
To: Robin Gong, robh+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, festevam@gmail.com, Anson Huang, Peng Fan
Cc: kernel@pengutronix.de, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, dl-linux-imx
In-Reply-To: <1590070674-23027-1-git-send-email-yibin.gong@nxp.com>
> From: Robin Gong <yibin.gong@nxp.com>
> Sent: Thursday, May 21, 2020 10:18 PM
>
> Correct ldo1 voltage range from wrong high group(3.0v~3.3v) to low group
> (1.6v~1.9v) because the ldo1 should be 1.8v. Actually, two voltage groups have
> been supported at bd718x7-regulator driver, hence, just corrrect the voltage
> range to 1.6v~3.3v. For ldo2@0.8v, correct voltage range too.
> Otherwise, ldo1 would be kept @3.0v and ldo2@0.9v which violate i.mx8mm
> datasheet as the below warning log in kernel:
>
> [ 0.995524] LDO1: Bringing 1800000uV into 3000000-3000000uV
> [ 0.999196] LDO2: Bringing 800000uV into 900000-900000uV
>
> Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Regards
Aisheng
^ permalink raw reply
* Re: [PATCH v3 07/16] spi: dw: Use DMA max burst to set the request thresholds
From: Andy Shevchenko @ 2020-05-21 10:49 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Alexey Malahov, Thomas Bogendoerfer,
Paul Burton, Ralf Baechle, Arnd Bergmann, Rob Herring, linux-mips,
devicetree, Georgy Vlasov, Ramil Zaripov, Thomas Gleixner,
Wan Ahmad Zainie, Jarkko Nikula, Clement Leger, linux-spi,
linux-kernel
In-Reply-To: <20200521012206.14472-8-Sergey.Semin@baikalelectronics.ru>
On Thu, May 21, 2020 at 04:21:57AM +0300, Serge Semin wrote:
> Each channel of DMA controller may have a limited length of burst
> transaction (number of IO operations performed at ones in a single
> DMA client request). This parameter can be used to setup the most
> optimal DMA Tx/Rx data level values. In order to avoid the Tx buffer
> overrun we can set the DMA Tx level to be of FIFO depth minus the
> maximum burst transactions length. To prevent the Rx buffer underflow
> the DMA Rx level should be set to the maximum burst transactions length.
> This commit setups the DMA channels and the DW SPI DMA Tx/Rx levels
> in accordance with these rules.
Besides one bikeshedding point, looks good to me.
Feel free to add
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
>
> ---
>
> Changelog v3:
> - Use min() method to calculate the optimal burst values.
> ---
> drivers/spi/spi-dw-mid.c | 37 +++++++++++++++++++++++++++++++++----
> drivers/spi/spi-dw.h | 2 ++
> 2 files changed, 35 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
> index be02fedd87cb..0e95d8bc85c5 100644
> --- a/drivers/spi/spi-dw-mid.c
> +++ b/drivers/spi/spi-dw-mid.c
> @@ -34,6 +34,31 @@ static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
> return true;
> }
>
> +static void mid_spi_maxburst_init(struct dw_spi *dws)
> +{
> + struct dma_slave_caps caps;
> + u32 max_burst, def_burst;
> + int ret;
> +
> + def_burst = dws->fifo_len / 2;
> +
> + ret = dma_get_slave_caps(dws->rxchan, &caps);
> + if (!ret && caps.max_burst)
> + max_burst = caps.max_burst;
> + else
> + max_burst = RX_BURST_LEVEL;
> +
> + dws->rxburst = min(max_burst, def_burst);
> +
> + ret = dma_get_slave_caps(dws->txchan, &caps);
> + if (!ret && caps.max_burst)
> + max_burst = caps.max_burst;
> + else
> + max_burst = TX_BURST_LEVEL;
> +
> + dws->txburst = min(max_burst, def_burst);
> +}
> +
> static int mid_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws)
> {
> struct dw_dma_slave slave = {
> @@ -69,6 +94,8 @@ static int mid_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws)
> dws->master->dma_rx = dws->rxchan;
> dws->master->dma_tx = dws->txchan;
>
> + mid_spi_maxburst_init(dws);
> +
> return 0;
>
> free_rxchan:
> @@ -94,6 +121,8 @@ static int mid_spi_dma_init_generic(struct device *dev, struct dw_spi *dws)
> dws->master->dma_rx = dws->rxchan;
> dws->master->dma_tx = dws->txchan;
>
> + mid_spi_maxburst_init(dws);
> +
> return 0;
> }
>
> @@ -216,7 +245,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
> memset(&txconf, 0, sizeof(txconf));
> txconf.direction = DMA_MEM_TO_DEV;
> txconf.dst_addr = dws->dma_addr;
> - txconf.dst_maxburst = TX_BURST_LEVEL;
> + txconf.dst_maxburst = dws->txburst;
> txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> txconf.dst_addr_width = convert_dma_width(dws->n_bytes);
> txconf.device_fc = false;
> @@ -290,7 +319,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
> memset(&rxconf, 0, sizeof(rxconf));
> rxconf.direction = DMA_DEV_TO_MEM;
> rxconf.src_addr = dws->dma_addr;
> - rxconf.src_maxburst = RX_BURST_LEVEL;
> + rxconf.src_maxburst = dws->rxburst;
> rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> rxconf.src_addr_width = convert_dma_width(dws->n_bytes);
> rxconf.device_fc = false;
> @@ -315,8 +344,8 @@ static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
> {
> u16 imr = 0, dma_ctrl = 0;
>
> - dw_writel(dws, DW_SPI_DMARDLR, RX_BURST_LEVEL - 1);
> - dw_writel(dws, DW_SPI_DMATDLR, TX_BURST_LEVEL);
> + dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1);
> + dw_writel(dws, DW_SPI_DMATDLR, dws->fifo_len - dws->txburst);
>
> if (xfer->tx_buf) {
> dma_ctrl |= SPI_DMA_TDMAE;
> diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
> index 4902f937c3d7..d0c8b7d3a5d2 100644
> --- a/drivers/spi/spi-dw.h
> +++ b/drivers/spi/spi-dw.h
> @@ -141,7 +141,9 @@ struct dw_spi {
>
> /* DMA info */
> struct dma_chan *txchan;
> + u32 txburst;
> struct dma_chan *rxchan;
> + u32 rxburst;
> unsigned long dma_chan_busy;
> dma_addr_t dma_addr; /* phy address of the Data register */
> const struct dw_spi_dma_ops *dma_ops;
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v3 09/16] spi: dw: Add core suffix to the DW APB SSI core source file
From: Andy Shevchenko @ 2020-05-21 10:47 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Rob Herring, Arnd Bergmann, linux-mips, devicetree, Chuanhong Guo,
John Garry, Eddie James, Tomer Maimon, Masahisa Kojima,
Chris Packham, Wan Ahmad Zainie, Charles Keepax, Clement Leger,
Linus Walleij, Thomas Gleixner, wuxu.wu, Phil Edworthy, linux-spi,
linux-kernel
In-Reply-To: <20200521012206.14472-10-Sergey.Semin@baikalelectronics.ru>
On Thu, May 21, 2020 at 04:21:59AM +0300, Serge Semin wrote:
> Generic DMA support is going to be part of the DW APB SSI core object.
> In order to preserve the kernel loadable module name as spi-dw.ko, let's
> add the "-core" suffix to the object with generic DW APB SSI code and
> build it into the target spi-dw.ko driver.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
>
> ---
>
> Changelog v3:
> - This is a new patch added as a result of the discussion with Andy
> Shevchenko.
> ---
> drivers/spi/Makefile | 1 +
> drivers/spi/{spi-dw.c => spi-dw-core.c} | 0
> 2 files changed, 1 insertion(+)
> rename drivers/spi/{spi-dw.c => spi-dw-core.c} (100%)
>
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index 28f601327f8c..70ebc2a62e5f 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -36,6 +36,7 @@ obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o
> obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o
> obj-$(CONFIG_SPI_DLN2) += spi-dln2.o
> obj-$(CONFIG_SPI_DESIGNWARE) += spi-dw.o
> +spi-dw-y := spi-dw-core.o
> obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o
> obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o
> spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o
> diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw-core.c
> similarity index 100%
> rename from drivers/spi/spi-dw.c
> rename to drivers/spi/spi-dw-core.c
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v7 00/24] iommu: Shared Virtual Addressing for SMMUv3
From: Will Deacon @ 2020-05-21 10:35 UTC (permalink / raw)
To: Jean-Philippe Brucker
Cc: iommu, devicetree, linux-arm-kernel, linux-pci, linux-mm, joro,
catalin.marinas, robin.murphy, kevin.tian, baolu.lu,
Jonathan.Cameron, jacob.jun.pan, christian.koenig, felix.kuehling,
zhangfei.gao, jgg, xuzaibo, fenghua.yu, hch
In-Reply-To: <20200519175502.2504091-1-jean-philippe@linaro.org>
Hi Jean-Philippe,
On Tue, May 19, 2020 at 07:54:38PM +0200, Jean-Philippe Brucker wrote:
> Shared Virtual Addressing (SVA) allows to share process page tables with
> devices using the IOMMU, PASIDs and I/O page faults. Add SVA support to
> the Arm SMMUv3 driver.
>
> Since v6 [1]:
> * Rename ioasid_free() to ioasid_put() in patch 02, requiring changes to
> the Intel drivers.
> * Use mmu_notifier_register() in patch 16 to avoid copying the ops and
> simplify the invalidate() notifier in patch 17.
> * As a result, replace context spinlock with a mutex. Simplified locking in
> patch 11 (That patch still looks awful, but I think the series is more
> readable overall). And I've finally been able to remove the GFP_ATOMIC
> allocations.
> * Use a single patch (04) for io-pgfault.c, since the code was simplified
> in v6. Fixed partial list in patch 04.
There's an awful lot here and it stretches across quite a few subsystems,
with different git trees. What's the plan for merging it?
I'm happy to take some of the arm64 and smmu changes for 5.8, then perhaps
we can review what's left and target 5.9? It would also be helpful to split
that up into separate series where there aren't strong dependencies, I
think.
Will
^ permalink raw reply
* Re: [PATCH v3 11/14] bus: cdmm: Add MIPS R5 arch support
From: Sergei Shtylyov @ 2020-05-21 10:25 UTC (permalink / raw)
To: Serge Semin, Thomas Bogendoerfer
Cc: Serge Semin, Alexey Malahov, Paul Burton, Ralf Baechle,
Greg Kroah-Hartman, Arnd Bergmann, Olof Johansson, Rob Herring,
linux-mips, devicetree, Jonathan Cameron, David Lechner,
John Garry, Manivannan Sadhasivam, Jon Hunter, Marek Behún,
Sameer Pujar, linux-kernel
In-Reply-To: <20200521003443.11385-12-Sergey.Semin@baikalelectronics.ru>
Hello!
On 21.05.2020 3:34, Serge Semin wrote:
> CDMM may be available not only MIPS R2 architectures, but also in
^ on -re, it's singular
> newer MIPS R5 chips. For instance our P5600 chip has one. Lets mark
> the CDMM bus being supported for that MIPS arch too.
>
> Co-developed-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Signed-off-by: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Reviewed-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Olof Johansson <olof@lixom.net>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
[...]
MBR, Sergei
^ permalink raw reply
* Re: [PATCH V3] arm64: dts: mediatek: add cpufreq and cci devfreq nodes for mt8183
From: Matthias Brugger @ 2020-05-21 10:25 UTC (permalink / raw)
To: Andrew-sh.Cheng, Rob Herring, Mark Rutland, devicetree
Cc: linux-arm-kernel, linux-mediatek, linux-kernel, srv_heupstream
In-Reply-To: <1576826785-3867-1-git-send-email-andrew-sh.cheng@mediatek.com>
On 20/12/2019 08:26, Andrew-sh.Cheng wrote:
> From: "Andrew-sh.Cheng" <andrew-sh.cheng@mediatek.com>
>
> add cpufreq and cci devfreq nodes for mt8183
>
> Depend on regulator node patch:
> https://patchwork.kernel.org/patch/11284617/
>
> Signed-off-by: Andrew-sh.Cheng <andrew-sh.cheng@mediatek.com>
> ---
Now queued for v5.7-next/dts64
Thanks!
> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 36 ++++
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 245 ++++++++++++++++++++++++++++
> 2 files changed, 281 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> index 1fb195c..ca5c0b2 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> @@ -231,6 +231,42 @@
>
> };
>
> +&cci {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> +&cpu0 {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> +&cpu1 {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> +&cpu2 {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> +&cpu3 {
> + proc-supply = <&mt6358_vproc12_reg>;
> +};
> +
> +&cpu4 {
> + proc-supply = <&mt6358_vproc11_reg>;
> +};
> +
> +&cpu5 {
> + proc-supply = <&mt6358_vproc11_reg>;
> +};
> +
> +&cpu6 {
> + proc-supply = <&mt6358_vproc11_reg>;
> +};
> +
> +&cpu7 {
> + proc-supply = <&mt6358_vproc11_reg>;
> +};
> +
> &uart0 {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> index 10b3247..d260a5a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
> @@ -31,6 +31,219 @@
> i2c11 = &i2c11;
> };
>
> + cluster0_opp: opp_table0 {
> + compatible = "operating-points-v2";
> + opp-shared;
> + opp00 {
> + opp-hz = /bits/ 64 <793000000>;
> + opp-microvolt = <650000>;
> + };
> + opp01 {
> + opp-hz = /bits/ 64 <910000000>;
> + opp-microvolt = <687500>;
> + };
> + opp02 {
> + opp-hz = /bits/ 64 <1014000000>;
> + opp-microvolt = <718750>;
> + };
> + opp03 {
> + opp-hz = /bits/ 64 <1131000000>;
> + opp-microvolt = <756250>;
> + };
> + opp04 {
> + opp-hz = /bits/ 64 <1248000000>;
> + opp-microvolt = <800000>;
> + };
> + opp05 {
> + opp-hz = /bits/ 64 <1326000000>;
> + opp-microvolt = <818750>;
> + };
> + opp06 {
> + opp-hz = /bits/ 64 <1417000000>;
> + opp-microvolt = <850000>;
> + };
> + opp07 {
> + opp-hz = /bits/ 64 <1508000000>;
> + opp-microvolt = <868750>;
> + };
> + opp08 {
> + opp-hz = /bits/ 64 <1586000000>;
> + opp-microvolt = <893750>;
> + };
> + opp09 {
> + opp-hz = /bits/ 64 <1625000000>;
> + opp-microvolt = <906250>;
> + };
> + opp10 {
> + opp-hz = /bits/ 64 <1677000000>;
> + opp-microvolt = <931250>;
> + };
> + opp11 {
> + opp-hz = /bits/ 64 <1716000000>;
> + opp-microvolt = <943750>;
> + };
> + opp12 {
> + opp-hz = /bits/ 64 <1781000000>;
> + opp-microvolt = <975000>;
> + };
> + opp13 {
> + opp-hz = /bits/ 64 <1846000000>;
> + opp-microvolt = <1000000>;
> + };
> + opp14 {
> + opp-hz = /bits/ 64 <1924000000>;
> + opp-microvolt = <1025000>;
> + };
> + opp15 {
> + opp-hz = /bits/ 64 <1989000000>;
> + opp-microvolt = <1050000>;
> + }; };
> +
> + cluster1_opp: opp_table1 {
> + compatible = "operating-points-v2";
> + opp-shared;
> + opp00 {
> + opp-hz = /bits/ 64 <793000000>;
> + opp-microvolt = <700000>;
> + };
> + opp01 {
> + opp-hz = /bits/ 64 <910000000>;
> + opp-microvolt = <725000>;
> + };
> + opp02 {
> + opp-hz = /bits/ 64 <1014000000>;
> + opp-microvolt = <750000>;
> + };
> + opp03 {
> + opp-hz = /bits/ 64 <1131000000>;
> + opp-microvolt = <775000>;
> + };
> + opp04 {
> + opp-hz = /bits/ 64 <1248000000>;
> + opp-microvolt = <800000>;
> + };
> + opp05 {
> + opp-hz = /bits/ 64 <1326000000>;
> + opp-microvolt = <825000>;
> + };
> + opp06 {
> + opp-hz = /bits/ 64 <1417000000>;
> + opp-microvolt = <850000>;
> + };
> + opp07 {
> + opp-hz = /bits/ 64 <1508000000>;
> + opp-microvolt = <875000>;
> + };
> + opp08 {
> + opp-hz = /bits/ 64 <1586000000>;
> + opp-microvolt = <900000>;
> + };
> + opp09 {
> + opp-hz = /bits/ 64 <1625000000>;
> + opp-microvolt = <912500>;
> + };
> + opp10 {
> + opp-hz = /bits/ 64 <1677000000>;
> + opp-microvolt = <931250>;
> + };
> + opp11 {
> + opp-hz = /bits/ 64 <1716000000>;
> + opp-microvolt = <950000>;
> + };
> + opp12 {
> + opp-hz = /bits/ 64 <1781000000>;
> + opp-microvolt = <975000>;
> + };
> + opp13 {
> + opp-hz = /bits/ 64 <1846000000>;
> + opp-microvolt = <1000000>;
> + };
> + opp14 {
> + opp-hz = /bits/ 64 <1924000000>;
> + opp-microvolt = <1025000>;
> + };
> + opp15 {
> + opp-hz = /bits/ 64 <1989000000>;
> + opp-microvolt = <1050000>;
> + };
> + };
> +
> + cci_opp: opp_table2 {
> + compatible = "operating-points-v2";
> + opp-shared;
> + opp00 {
> + opp-hz = /bits/ 64 <273000000>;
> + opp-microvolt = <650000>;
> + };
> + opp01 {
> + opp-hz = /bits/ 64 <338000000>;
> + opp-microvolt = <687500>;
> + };
> + opp02 {
> + opp-hz = /bits/ 64 <403000000>;
> + opp-microvolt = <718750>;
> + };
> + opp03 {
> + opp-hz = /bits/ 64 <463000000>;
> + opp-microvolt = <756250>;
> + };
> + opp04 {
> + opp-hz = /bits/ 64 <546000000>;
> + opp-microvolt = <800000>;
> + };
> + opp05 {
> + opp-hz = /bits/ 64 <624000000>;
> + opp-microvolt = <818750>;
> + };
> + opp06 {
> + opp-hz = /bits/ 64 <689000000>;
> + opp-microvolt = <850000>;
> + };
> + opp07 {
> + opp-hz = /bits/ 64 <767000000>;
> + opp-microvolt = <868750>;
> + };
> + opp08 {
> + opp-hz = /bits/ 64 <845000000>;
> + opp-microvolt = <893750>;
> + };
> + opp09 {
> + opp-hz = /bits/ 64 <871000000>;
> + opp-microvolt = <906250>;
> + };
> + opp10 {
> + opp-hz = /bits/ 64 <923000000>;
> + opp-microvolt = <931250>;
> + };
> + opp11 {
> + opp-hz = /bits/ 64 <962000000>;
> + opp-microvolt = <943750>;
> + };
> + opp12 {
> + opp-hz = /bits/ 64 <1027000000>;
> + opp-microvolt = <975000>;
> + };
> + opp13 {
> + opp-hz = /bits/ 64 <1092000000>;
> + opp-microvolt = <1000000>;
> + };
> + opp14 {
> + opp-hz = /bits/ 64 <1144000000>;
> + opp-microvolt = <1025000>;
> + };
> + opp15 {
> + opp-hz = /bits/ 64 <1196000000>;
> + opp-microvolt = <1050000>;
> + };
> + };
> +
> + cci: cci {
> + compatible = "mediatek,mt8183-cci";
> + clocks = <&apmixedsys CLK_APMIXED_CCIPLL>;
> + clock-names = "cci_clock";
> + operating-points-v2 = <&cci_opp>;
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -73,6 +286,10 @@
> reg = <0x000>;
> enable-method = "psci";
> capacity-dmips-mhz = <741>;
> + clocks = <&mcucfg CLK_MCU_MP0_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster0_opp>;
> };
>
> cpu1: cpu@1 {
> @@ -81,6 +298,10 @@
> reg = <0x001>;
> enable-method = "psci";
> capacity-dmips-mhz = <741>;
> + clocks = <&mcucfg CLK_MCU_MP0_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster0_opp>;
> };
>
> cpu2: cpu@2 {
> @@ -89,6 +310,10 @@
> reg = <0x002>;
> enable-method = "psci";
> capacity-dmips-mhz = <741>;
> + clocks = <&mcucfg CLK_MCU_MP0_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster0_opp>;
> };
>
> cpu3: cpu@3 {
> @@ -97,6 +322,10 @@
> reg = <0x003>;
> enable-method = "psci";
> capacity-dmips-mhz = <741>;
> + clocks = <&mcucfg CLK_MCU_MP0_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster0_opp>;
> };
>
> cpu4: cpu@100 {
> @@ -105,6 +334,10 @@
> reg = <0x100>;
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> + clocks = <&mcucfg CLK_MCU_MP2_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster1_opp>;
> };
>
> cpu5: cpu@101 {
> @@ -113,6 +346,10 @@
> reg = <0x101>;
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> + clocks = <&mcucfg CLK_MCU_MP2_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster1_opp>;
> };
>
> cpu6: cpu@102 {
> @@ -121,6 +358,10 @@
> reg = <0x102>;
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> + clocks = <&mcucfg CLK_MCU_MP2_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster1_opp>;
> };
>
> cpu7: cpu@103 {
> @@ -129,6 +370,10 @@
> reg = <0x103>;
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> + clocks = <&mcucfg CLK_MCU_MP2_SEL>,
> + <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
> + clock-names = "cpu", "intermediate";
> + operating-points-v2 = <&cluster1_opp>;
> };
> };
>
>
^ permalink raw reply
* Re: [PATCH v3 06/16] spi: dw: Parameterize the DMA Rx/Tx burst length
From: Andy Shevchenko @ 2020-05-21 10:23 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Rob Herring, linux-mips, devicetree,
Thomas Gleixner, Wan Ahmad Zainie, Jarkko Nikula, linux-spi,
linux-kernel
In-Reply-To: <20200521012206.14472-7-Sergey.Semin@baikalelectronics.ru>
On Thu, May 21, 2020 at 04:21:56AM +0300, Serge Semin wrote:
> It isn't good to have numeric literals in the code especially if there
> are multiple of them and they are related. Let's replace the Tx and Rx
> burst level literals with the corresponding constants.
Thanks!
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>
> Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
>
> ---
>
> Changelog v3:
> - Discard the dws->fifo_len utilization in the Tx FIFO DMA threshold
> setting.
> ---
> drivers/spi/spi-dw-mid.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
> index 7bba774885cd..be02fedd87cb 100644
> --- a/drivers/spi/spi-dw-mid.c
> +++ b/drivers/spi/spi-dw-mid.c
> @@ -19,7 +19,9 @@
>
> #define WAIT_RETRIES 5
> #define RX_BUSY 0
> +#define RX_BURST_LEVEL 16
> #define TX_BUSY 1
> +#define TX_BURST_LEVEL 16
>
> static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
> {
> @@ -214,7 +216,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
> memset(&txconf, 0, sizeof(txconf));
> txconf.direction = DMA_MEM_TO_DEV;
> txconf.dst_addr = dws->dma_addr;
> - txconf.dst_maxburst = 16;
> + txconf.dst_maxburst = TX_BURST_LEVEL;
> txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> txconf.dst_addr_width = convert_dma_width(dws->n_bytes);
> txconf.device_fc = false;
> @@ -288,7 +290,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
> memset(&rxconf, 0, sizeof(rxconf));
> rxconf.direction = DMA_DEV_TO_MEM;
> rxconf.src_addr = dws->dma_addr;
> - rxconf.src_maxburst = 16;
> + rxconf.src_maxburst = RX_BURST_LEVEL;
> rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
> rxconf.src_addr_width = convert_dma_width(dws->n_bytes);
> rxconf.device_fc = false;
> @@ -313,8 +315,8 @@ static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
> {
> u16 imr = 0, dma_ctrl = 0;
>
> - dw_writel(dws, DW_SPI_DMARDLR, 0xf);
> - dw_writel(dws, DW_SPI_DMATDLR, 0x10);
> + dw_writel(dws, DW_SPI_DMARDLR, RX_BURST_LEVEL - 1);
> + dw_writel(dws, DW_SPI_DMATDLR, TX_BURST_LEVEL);
>
> if (xfer->tx_buf) {
> dma_ctrl |= SPI_DMA_TDMAE;
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH] dt-bindings: mfd: mediatek: Add MT6397 Pin Controller
From: Matthias Brugger @ 2020-05-21 10:16 UTC (permalink / raw)
To: matthias.bgg, Lee Jones
Cc: Rob Herring, Mark Rutland, devicetree, linux-arm-kernel,
linux-kernel, linux-mediatek
In-Reply-To: <20200115151938.GA8182@bogus>
Hi Lee,
On 15/01/2020 16:19, Rob Herring wrote:
> On Fri, 10 Jan 2020 15:59:51 +0100, matthias.bgg@kernel.org wrote:
>> From: Matthias Brugger <matthias.bgg@gmail.com>
>>
>> The MT6397 mfd includes a pin controller. Add binding
>> a description for it.
>>
>> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
>>
>> ---
>>
>> Documentation/devicetree/bindings/mfd/mt6397.txt | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>
> Acked-by: Rob Herring <robh@kernel.org>
>
It looks like this fall through the cracks.
Would you consider to queue it or do you have further comments?
Regards,
Matthias
^ permalink raw reply
* Re: [PATCH 00/14] Adding support for Microchip Sparx5 SoC
From: Arnd Bergmann @ 2020-05-21 10:16 UTC (permalink / raw)
To: Lars Povlsen
Cc: SoC Team, Stephen Boyd, Linus Walleij, Steen Hegelund,
Microchip Linux Driver Support, Olof Johansson, Michael Turquette,
DTML, linux-clk, open list:GPIO SUBSYSTEM, Linux ARM,
linux-kernel@vger.kernel.org
In-Reply-To: <20200513125532.24585-1-lars.povlsen@microchip.com>
On Wed, May 13, 2020 at 2:55 PM Lars Povlsen <lars.povlsen@microchip.com> wrote:
>
> This patch series adds support for Microchip Sparx5 SoC, the CPU
> system of a advanced, TSN capable gigabit switch. The CPU is an armv8
> x 2 CPU core (A53).
>
> Although this is an ARM core, it shares some peripherals with the
> Microsemi Ocelot SoC.
>
> This is the first official revision of the series.
I see you sent multiple series to soc@kernel.org for review. This is the
correct address for getting the initial soc support merged, but as the patches
are still being reviewed by subsystem maintainers, please leave it off
for now, until you are confident that they are ready to get merged for the
following merge window and have received the appropriate Acks.
For each subsystem, there is generally the choice between merging
code through the subsystem maintainer tree, or through the soc tree
on an initial submission, as going through multiple trees is particularly
hard to do for the devicetree files.
For the moment, I have marked all sparx5 patches as "Not Applicable"
in patchwork at https://patchwork.kernel.org/project/linux-soc/list/
as it is still unclear who is merging which parts, and they are under
active review, but please do send them again after the review is
complete.
If you have a lot of patches, sending pull requests is sometimes easier,
but it also takes a bit of practice to know how exactly to structure
those. Let me know if you have questions about them. You an also
contact me and most of the other maintainers on IRC using the
#armlinux channel on irc.freenode.net.
Sorry for not having been able to review the patches myself yet, I
hope to get to that soon.
Arnd
^ permalink raw reply
* Re: [PATCH v3 03/16] spi: dw: Discard static DW DMA slave structures
From: Andy Shevchenko @ 2020-05-21 9:57 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Andy Shevchenko, Arnd Bergmann, Rob Herring, linux-mips,
devicetree, Thomas Gleixner, Wan Ahmad Zainie, Jarkko Nikula,
Clement Leger, linux-spi, Linux Kernel Mailing List
In-Reply-To: <20200521012206.14472-4-Sergey.Semin@baikalelectronics.ru>
On Thu, May 21, 2020 at 4:23 AM Serge Semin
<Sergey.Semin@baikalelectronics.ru> wrote:
>
> Having them declared is redundant since each struct dw_dma_chan has
> the same structure embedded and the structure from the passed dma_chan
> private pointer will be copied there as a result of the next calls
> chain:
> dma_request_channel() -> find_candidate() -> dma_chan_get() ->
> device_alloc_chan_resources() = dwc_alloc_chan_resources() ->
> dw_dma_filter().
> So just remove the static dw_dma_chan structures and use a locally
> declared data instance with dst_id/src_id set to the same values as
> the static copies used to have.
...
> - Explicitly initialize the dw_dma_slave members on stack.
Thanks for an update, but that's not what I asked for...
> -static struct dw_dma_slave mid_dma_tx = { .dst_id = 1 };
> -static struct dw_dma_slave mid_dma_rx = { .src_id = 0 };
> static int mid_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws)
> {
> + struct dw_dma_slave slave = {
> + .src_id = 0,
> + .dst_id = 0
> + };
(It's member, and not memberS)
> - struct dw_dma_slave *tx = dws->dma_tx;
> - struct dw_dma_slave *rx = dws->dma_rx;
May we simple do
struct dw_dma_slave tx = { .dst_id = 1 };
struct dw_dma_slave rx = { .src_id = 0 };
please?
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v13 5/6] rtc: mt6397: Add support for the MediaTek MT6358 RTC
From: Matthias Brugger @ 2020-05-21 9:38 UTC (permalink / raw)
To: Lee Jones
Cc: Hsin-Hsiung Wang, Rob Herring, Alexandre Belloni, drinkcat,
Sean Wang, Sebastian Reichel, Eddie Huang, Alessandro Zummo,
Frank Wunderlich, Josef Friedl, Richard Fontana, Thomas Gleixner,
Ran Bi, devicetree, linux-arm-kernel, linux-mediatek,
linux-kernel, linux-pm, linux-rtc, srv_heupstream
In-Reply-To: <20200521074718.GN271301@dell>
On 21/05/2020 09:47, Lee Jones wrote:
> On Sat, 16 May 2020, Matthias Brugger wrote:
>
>> Hi Lee,
>>
>> On 21/04/2020 05:00, Hsin-Hsiung Wang wrote:
>>> From: Ran Bi <ran.bi@mediatek.com>
>>>
>>> This add support for the MediaTek MT6358 RTC. Driver using
>>> compatible data to store different RTC_WRTGR address offset.
>>> This replace RTC_WRTGR to RTC_WRTGR_MT6323 in mt6323-poweroff
>>> driver which only needed by armv7 CPU without ATF.
>>>
>>> Signed-off-by: Ran Bi <ran.bi@mediatek.com>
>>> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
>>> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
>>> Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
>>> Acked-by: Sebastian Reichel <sre@kernel.org>
>>> Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
>>
>> We have Acked-by from rtc and reset drivers maintainers. Are you OK to take them
>> through your mfd branch?
>>
>> Are you planning to queue them for v5.8?
>>
>> Just asking because if so I'd queue patch 6 through my tree.
>
> Yes, please take patch 6.
>
Thanks!
^ permalink raw reply
* Re: [PATCH v13 6/6] arm64: dts: mt6358: add PMIC MT6358 related nodes
From: Matthias Brugger @ 2020-05-21 9:38 UTC (permalink / raw)
To: Hsin-Hsiung Wang, Lee Jones, Rob Herring, Alexandre Belloni
Cc: drinkcat, Sean Wang, Sebastian Reichel, Eddie Huang,
Alessandro Zummo, Frank Wunderlich, Josef Friedl, Richard Fontana,
Thomas Gleixner, Ran Bi, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel, linux-pm, linux-rtc, srv_heupstream
In-Reply-To: <1587438012-24832-7-git-send-email-hsin-hsiung.wang@mediatek.com>
On 21/04/2020 05:00, Hsin-Hsiung Wang wrote:
> add PMIC MT6358 related nodes which is for MT8183 platform
>
> Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
> ---
Now queued for v5.7-next/dts64
Thanks!
> arch/arm64/boot/dts/mediatek/mt6358.dtsi | 358 ++++++++++++++++++++++++++++
> arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 1 +
> 2 files changed, 359 insertions(+)
> create mode 100644 arch/arm64/boot/dts/mediatek/mt6358.dtsi
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6358.dtsi b/arch/arm64/boot/dts/mediatek/mt6358.dtsi
> new file mode 100644
> index 0000000..9361ada
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt6358.dtsi
> @@ -0,0 +1,358 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (c) 2020 MediaTek Inc.
> + */
> +
> +&pwrap {
> + pmic: mt6358 {
> + compatible = "mediatek,mt6358";
> + interrupt-controller;
> + interrupt-parent = <&pio>;
> + interrupts = <182 IRQ_TYPE_LEVEL_HIGH>;
> + #interrupt-cells = <2>;
> +
> + mt6358codec: mt6358codec {
> + compatible = "mediatek,mt6358-sound";
> + };
> +
> + mt6358regulator: mt6358regulator {
> + mt6358_vdram1_reg: buck_vdram1 {
> + regulator-name = "vdram1";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <2087500>;
> + regulator-ramp-delay = <12500>;
> + regulator-enable-ramp-delay = <0>;
> + regulator-always-on;
> + regulator-allowed-modes = <0 1>;
> + };
> +
> + mt6358_vcore_reg: buck_vcore {
> + regulator-name = "vcore";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1293750>;
> + regulator-ramp-delay = <6250>;
> + regulator-enable-ramp-delay = <200>;
> + regulator-always-on;
> + regulator-allowed-modes = <0 1>;
> + };
> +
> + mt6358_vpa_reg: buck_vpa {
> + regulator-name = "vpa";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <3650000>;
> + regulator-ramp-delay = <50000>;
> + regulator-enable-ramp-delay = <250>;
> + regulator-allowed-modes = <0 1>;
> + };
> +
> + mt6358_vproc11_reg: buck_vproc11 {
> + regulator-name = "vproc11";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1293750>;
> + regulator-ramp-delay = <6250>;
> + regulator-enable-ramp-delay = <200>;
> + regulator-always-on;
> + regulator-allowed-modes = <0 1>;
> + };
> +
> + mt6358_vproc12_reg: buck_vproc12 {
> + regulator-name = "vproc12";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1293750>;
> + regulator-ramp-delay = <6250>;
> + regulator-enable-ramp-delay = <200>;
> + regulator-always-on;
> + regulator-allowed-modes = <0 1>;
> + };
> +
> + mt6358_vgpu_reg: buck_vgpu {
> + regulator-name = "vgpu";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1293750>;
> + regulator-ramp-delay = <6250>;
> + regulator-enable-ramp-delay = <200>;
> + regulator-allowed-modes = <0 1>;
> + };
> +
> + mt6358_vs2_reg: buck_vs2 {
> + regulator-name = "vs2";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <2087500>;
> + regulator-ramp-delay = <12500>;
> + regulator-enable-ramp-delay = <0>;
> + regulator-always-on;
> + };
> +
> + mt6358_vmodem_reg: buck_vmodem {
> + regulator-name = "vmodem";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1293750>;
> + regulator-ramp-delay = <6250>;
> + regulator-enable-ramp-delay = <900>;
> + regulator-always-on;
> + regulator-allowed-modes = <0 1>;
> + };
> +
> + mt6358_vs1_reg: buck_vs1 {
> + regulator-name = "vs1";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <2587500>;
> + regulator-ramp-delay = <12500>;
> + regulator-enable-ramp-delay = <0>;
> + regulator-always-on;
> + };
> +
> + mt6358_vdram2_reg: ldo_vdram2 {
> + regulator-name = "vdram2";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <3300>;
> + };
> +
> + mt6358_vsim1_reg: ldo_vsim1 {
> + regulator-name = "vsim1";
> + regulator-min-microvolt = <1700000>;
> + regulator-max-microvolt = <3100000>;
> + regulator-enable-ramp-delay = <540>;
> + };
> +
> + mt6358_vibr_reg: ldo_vibr {
> + regulator-name = "vibr";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-enable-ramp-delay = <60>;
> + };
> +
> + mt6358_vrf12_reg: ldo_vrf12 {
> + compatible = "regulator-fixed";
> + regulator-name = "vrf12";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-enable-ramp-delay = <120>;
> + };
> +
> + mt6358_vio18_reg: ldo_vio18 {
> + compatible = "regulator-fixed";
> + regulator-name = "vio18";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <2700>;
> + regulator-always-on;
> + };
> +
> + mt6358_vusb_reg: ldo_vusb {
> + regulator-name = "vusb";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3100000>;
> + regulator-enable-ramp-delay = <270>;
> + regulator-always-on;
> + };
> +
> + mt6358_vcamio_reg: ldo_vcamio {
> + compatible = "regulator-fixed";
> + regulator-name = "vcamio";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <325>;
> + };
> +
> + mt6358_vcamd_reg: ldo_vcamd {
> + regulator-name = "vcamd";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <325>;
> + };
> +
> + mt6358_vcn18_reg: ldo_vcn18 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcn18";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vfe28_reg: ldo_vfe28 {
> + compatible = "regulator-fixed";
> + regulator-name = "vfe28";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vsram_proc11_reg: ldo_vsram_proc11 {
> + regulator-name = "vsram_proc11";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1293750>;
> + regulator-ramp-delay = <6250>;
> + regulator-enable-ramp-delay = <240>;
> + regulator-always-on;
> + };
> +
> + mt6358_vcn28_reg: ldo_vcn28 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcn28";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vsram_others_reg: ldo_vsram_others {
> + regulator-name = "vsram_others";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1293750>;
> + regulator-ramp-delay = <6250>;
> + regulator-enable-ramp-delay = <240>;
> + regulator-always-on;
> + };
> +
> + mt6358_vsram_gpu_reg: ldo_vsram_gpu {
> + regulator-name = "vsram_gpu";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1293750>;
> + regulator-ramp-delay = <6250>;
> + regulator-enable-ramp-delay = <240>;
> + };
> +
> + mt6358_vxo22_reg: ldo_vxo22 {
> + compatible = "regulator-fixed";
> + regulator-name = "vxo22";
> + regulator-min-microvolt = <2200000>;
> + regulator-max-microvolt = <2200000>;
> + regulator-enable-ramp-delay = <120>;
> + regulator-always-on;
> + };
> +
> + mt6358_vefuse_reg: ldo_vefuse {
> + regulator-name = "vefuse";
> + regulator-min-microvolt = <1700000>;
> + regulator-max-microvolt = <1900000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vaux18_reg: ldo_vaux18 {
> + compatible = "regulator-fixed";
> + regulator-name = "vaux18";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vmch_reg: ldo_vmch {
> + regulator-name = "vmch";
> + regulator-min-microvolt = <2900000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-enable-ramp-delay = <60>;
> + };
> +
> + mt6358_vbif28_reg: ldo_vbif28 {
> + compatible = "regulator-fixed";
> + regulator-name = "vbif28";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vsram_proc12_reg: ldo_vsram_proc12 {
> + regulator-name = "vsram_proc12";
> + regulator-min-microvolt = <500000>;
> + regulator-max-microvolt = <1293750>;
> + regulator-ramp-delay = <6250>;
> + regulator-enable-ramp-delay = <240>;
> + regulator-always-on;
> + };
> +
> + mt6358_vcama1_reg: ldo_vcama1 {
> + regulator-name = "vcama1";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-enable-ramp-delay = <325>;
> + };
> +
> + mt6358_vemc_reg: ldo_vemc {
> + regulator-name = "vemc";
> + regulator-min-microvolt = <2900000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-enable-ramp-delay = <60>;
> + };
> +
> + mt6358_vio28_reg: ldo_vio28 {
> + compatible = "regulator-fixed";
> + regulator-name = "vio28";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_va12_reg: ldo_va12 {
> + compatible = "regulator-fixed";
> + regulator-name = "va12";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-enable-ramp-delay = <270>;
> + regulator-always-on;
> + };
> +
> + mt6358_vrf18_reg: ldo_vrf18 {
> + compatible = "regulator-fixed";
> + regulator-name = "vrf18";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-enable-ramp-delay = <120>;
> + };
> +
> + mt6358_vcn33_bt_reg: ldo_vcn33_bt {
> + regulator-name = "vcn33_bt";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3500000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vcn33_wifi_reg: ldo_vcn33_wifi {
> + regulator-name = "vcn33_wifi";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3500000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vcama2_reg: ldo_vcama2 {
> + regulator-name = "vcama2";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-enable-ramp-delay = <325>;
> + };
> +
> + mt6358_vmc_reg: ldo_vmc {
> + regulator-name = "vmc";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-enable-ramp-delay = <60>;
> + };
> +
> + mt6358_vldo28_reg: ldo_vldo28 {
> + regulator-name = "vldo28";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vaud28_reg: ldo_vaud28 {
> + compatible = "regulator-fixed";
> + regulator-name = "vaud28";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-enable-ramp-delay = <270>;
> + };
> +
> + mt6358_vsim2_reg: ldo_vsim2 {
> + regulator-name = "vsim2";
> + regulator-min-microvolt = <1700000>;
> + regulator-max-microvolt = <3100000>;
> + regulator-enable-ramp-delay = <540>;
> + };
> + };
> +
> + mt6358rtc: mt6358rtc {
> + compatible = "mediatek,mt6358-rtc";
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> index 1fb195c..9eb84d7 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
> @@ -7,6 +7,7 @@
>
> /dts-v1/;
> #include "mt8183.dtsi"
> +#include "mt6358.dtsi"
>
> / {
> model = "MediaTek MT8183 evaluation board";
>
^ permalink raw reply
* [PATCH v8 1/5] x86: kdump: move reserve_crashkernel_low() into crash_core.c
From: Chen Zhou @ 2020-05-21 9:38 UTC (permalink / raw)
To: tglx, mingo, catalin.marinas, will, dyoung, bhe, robh+dt
Cc: arnd, John.p.donnelly, pkushwaha, horms, guohanjun, chenzhou10,
linux-arm-kernel, devicetree, linux-doc, linux-kernel, kexec
In-Reply-To: <20200521093805.64398-1-chenzhou10@huawei.com>
In preparation for supporting reserve_crashkernel_low in arm64 as
x86_64 does, move reserve_crashkernel_low() into kernel/crash_core.c.
BTW, move x86 CRASH_ALIGN to 2M.
Note, in arm64, we reserve low memory if and only if crashkernel=X,low
is specified. Different with x86_64, don't set low memory automatically.
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Chen Zhou <chenzhou10@huawei.com>
Tested-by: John Donnelly <John.p.donnelly@oracle.com>
Tested-by: Prabhakar Kushwaha <pkushwaha@marvell.com>
---
arch/x86/kernel/setup.c | 66 ++++-------------------------
include/linux/crash_core.h | 3 ++
include/linux/kexec.h | 2 -
kernel/crash_core.c | 85 ++++++++++++++++++++++++++++++++++++++
kernel/kexec_core.c | 17 --------
5 files changed, 96 insertions(+), 77 deletions(-)
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index 4b3fa6cd3106..de75fec73d47 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -395,8 +395,8 @@ static void __init memblock_x86_reserve_range_setup_data(void)
#ifdef CONFIG_KEXEC_CORE
-/* 16M alignment for crash kernel regions */
-#define CRASH_ALIGN SZ_16M
+/* 2M alignment for crash kernel regions */
+#define CRASH_ALIGN SZ_2M
/*
* Keep the crash kernel below this limit.
@@ -419,59 +419,6 @@ static void __init memblock_x86_reserve_range_setup_data(void)
# define CRASH_ADDR_HIGH_MAX SZ_64T
#endif
-static int __init reserve_crashkernel_low(void)
-{
-#ifdef CONFIG_X86_64
- unsigned long long base, low_base = 0, low_size = 0;
- unsigned long total_low_mem;
- int ret;
-
- total_low_mem = memblock_mem_size(1UL << (32 - PAGE_SHIFT));
-
- /* crashkernel=Y,low */
- ret = parse_crashkernel_low(boot_command_line, total_low_mem, &low_size, &base);
- if (ret) {
- /*
- * two parts from kernel/dma/swiotlb.c:
- * -swiotlb size: user-specified with swiotlb= or default.
- *
- * -swiotlb overflow buffer: now hardcoded to 32k. We round it
- * to 8M for other buffers that may need to stay low too. Also
- * make sure we allocate enough extra low memory so that we
- * don't run out of DMA buffers for 32-bit devices.
- */
- low_size = max(swiotlb_size_or_default() + (8UL << 20), 256UL << 20);
- } else {
- /* passed with crashkernel=0,low ? */
- if (!low_size)
- return 0;
- }
-
- low_base = memblock_find_in_range(0, 1ULL << 32, low_size, CRASH_ALIGN);
- if (!low_base) {
- pr_err("Cannot reserve %ldMB crashkernel low memory, please try smaller size.\n",
- (unsigned long)(low_size >> 20));
- return -ENOMEM;
- }
-
- ret = memblock_reserve(low_base, low_size);
- if (ret) {
- pr_err("%s: Error reserving crashkernel low memblock.\n", __func__);
- return ret;
- }
-
- pr_info("Reserving %ldMB of low memory at %ldMB for crashkernel (System low RAM: %ldMB)\n",
- (unsigned long)(low_size >> 20),
- (unsigned long)(low_base >> 20),
- (unsigned long)(total_low_mem >> 20));
-
- crashk_low_res.start = low_base;
- crashk_low_res.end = low_base + low_size - 1;
- insert_resource(&iomem_resource, &crashk_low_res);
-#endif
- return 0;
-}
-
static void __init reserve_crashkernel(void)
{
unsigned long long crash_size, crash_base, total_mem;
@@ -535,9 +482,12 @@ static void __init reserve_crashkernel(void)
return;
}
- if (crash_base >= (1ULL << 32) && reserve_crashkernel_low()) {
- memblock_free(crash_base, crash_size);
- return;
+ if (crash_base >= (1ULL << 32)) {
+ if (reserve_crashkernel_low()) {
+ memblock_free(crash_base, crash_size);
+ return;
+ }
+ insert_resource(&iomem_resource, &crashk_low_res);
}
pr_info("Reserving %ldMB of memory at %ldMB for crashkernel (System RAM: %ldMB)\n",
diff --git a/include/linux/crash_core.h b/include/linux/crash_core.h
index 525510a9f965..4df8c0bff03e 100644
--- a/include/linux/crash_core.h
+++ b/include/linux/crash_core.h
@@ -63,6 +63,8 @@ phys_addr_t paddr_vmcoreinfo_note(void);
extern unsigned char *vmcoreinfo_data;
extern size_t vmcoreinfo_size;
extern u32 *vmcoreinfo_note;
+extern struct resource crashk_res;
+extern struct resource crashk_low_res;
Elf_Word *append_elf_note(Elf_Word *buf, char *name, unsigned int type,
void *data, size_t data_len);
@@ -74,5 +76,6 @@ int parse_crashkernel_high(char *cmdline, unsigned long long system_ram,
unsigned long long *crash_size, unsigned long long *crash_base);
int parse_crashkernel_low(char *cmdline, unsigned long long system_ram,
unsigned long long *crash_size, unsigned long long *crash_base);
+int __init reserve_crashkernel_low(void);
#endif /* LINUX_CRASH_CORE_H */
diff --git a/include/linux/kexec.h b/include/linux/kexec.h
index 1776eb2e43a4..5d5d9635b18d 100644
--- a/include/linux/kexec.h
+++ b/include/linux/kexec.h
@@ -330,8 +330,6 @@ extern int kexec_load_disabled;
/* Location of a reserved region to hold the crash kernel.
*/
-extern struct resource crashk_res;
-extern struct resource crashk_low_res;
extern note_buf_t __percpu *crash_notes;
/* flag to track if kexec reboot is in progress */
diff --git a/kernel/crash_core.c b/kernel/crash_core.c
index 9f1557b98468..a7580d291c37 100644
--- a/kernel/crash_core.c
+++ b/kernel/crash_core.c
@@ -7,6 +7,8 @@
#include <linux/crash_core.h>
#include <linux/utsname.h>
#include <linux/vmalloc.h>
+#include <linux/memblock.h>
+#include <linux/swiotlb.h>
#include <asm/page.h>
#include <asm/sections.h>
@@ -19,6 +21,22 @@ u32 *vmcoreinfo_note;
/* trusted vmcoreinfo, e.g. we can make a copy in the crash memory */
static unsigned char *vmcoreinfo_data_safecopy;
+/* Location of the reserved area for the crash kernel */
+struct resource crashk_res = {
+ .name = "Crash kernel",
+ .start = 0,
+ .end = 0,
+ .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM,
+ .desc = IORES_DESC_CRASH_KERNEL
+};
+struct resource crashk_low_res = {
+ .name = "Crash kernel",
+ .start = 0,
+ .end = 0,
+ .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM,
+ .desc = IORES_DESC_CRASH_KERNEL
+};
+
/*
* parsing the "crashkernel" commandline
*
@@ -292,6 +310,73 @@ int __init parse_crashkernel_low(char *cmdline,
"crashkernel=", suffix_tbl[SUFFIX_LOW]);
}
+#if defined(CONFIG_X86_64) || defined(CONFIG_ARM64)
+#define CRASH_ALIGN SZ_2M
+#endif
+
+int __init reserve_crashkernel_low(void)
+{
+#if defined(CONFIG_X86_64) || defined(CONFIG_ARM64)
+ unsigned long long base, low_base = 0, low_size = 0;
+ unsigned long total_low_mem;
+ int ret;
+
+ total_low_mem = memblock_mem_size(1UL << (32 - PAGE_SHIFT));
+
+ /* crashkernel=Y,low */
+ ret = parse_crashkernel_low(boot_command_line, total_low_mem, &low_size,
+ &base);
+ if (ret) {
+#ifdef CONFIG_X86_64
+ /*
+ * two parts from lib/swiotlb.c:
+ * -swiotlb size: user-specified with swiotlb= or default.
+ *
+ * -swiotlb overflow buffer: now hardcoded to 32k. We round it
+ * to 8M for other buffers that may need to stay low too. Also
+ * make sure we allocate enough extra low memory so that we
+ * don't run out of DMA buffers for 32-bit devices.
+ */
+ low_size = max(swiotlb_size_or_default() + (8UL << 20),
+ 256UL << 20);
+#else
+ /*
+ * in arm64, reserve low memory if and only if crashkernel=X,low
+ * specified.
+ */
+ return -EINVAL;
+#endif
+ } else {
+ /* passed with crashkernel=0,low ? */
+ if (!low_size)
+ return 0;
+ }
+
+ low_base = memblock_find_in_range(0, 1ULL << 32, low_size, CRASH_ALIGN);
+ if (!low_base) {
+ pr_err("Cannot reserve %ldMB crashkernel low memory, please try smaller size.\n",
+ (unsigned long)(low_size >> 20));
+ return -ENOMEM;
+ }
+
+ ret = memblock_reserve(low_base, low_size);
+ if (ret) {
+ pr_err("%s: Error reserving crashkernel low memblock.\n",
+ __func__);
+ return ret;
+ }
+
+ pr_info("Reserving %ldMB of low memory at %ldMB for crashkernel (System low RAM: %ldMB)\n",
+ (unsigned long)(low_size >> 20),
+ (unsigned long)(low_base >> 20),
+ (unsigned long)(total_low_mem >> 20));
+
+ crashk_low_res.start = low_base;
+ crashk_low_res.end = low_base + low_size - 1;
+#endif
+ return 0;
+}
+
Elf_Word *append_elf_note(Elf_Word *buf, char *name, unsigned int type,
void *data, size_t data_len)
{
diff --git a/kernel/kexec_core.c b/kernel/kexec_core.c
index c19c0dad1ebe..db66bbabfff3 100644
--- a/kernel/kexec_core.c
+++ b/kernel/kexec_core.c
@@ -53,23 +53,6 @@ note_buf_t __percpu *crash_notes;
/* Flag to indicate we are going to kexec a new kernel */
bool kexec_in_progress = false;
-
-/* Location of the reserved area for the crash kernel */
-struct resource crashk_res = {
- .name = "Crash kernel",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM,
- .desc = IORES_DESC_CRASH_KERNEL
-};
-struct resource crashk_low_res = {
- .name = "Crash kernel",
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM,
- .desc = IORES_DESC_CRASH_KERNEL
-};
-
int kexec_should_crash(struct task_struct *p)
{
/*
--
2.20.1
^ permalink raw reply related
* [PATCH v8 5/5] dt-bindings: chosen: Document linux,low-memory-range for arm64 kdump
From: Chen Zhou @ 2020-05-21 9:38 UTC (permalink / raw)
To: tglx, mingo, catalin.marinas, will, dyoung, bhe, robh+dt
Cc: arnd, John.p.donnelly, pkushwaha, horms, guohanjun, chenzhou10,
linux-arm-kernel, devicetree, linux-doc, linux-kernel, kexec
In-Reply-To: <20200521093805.64398-1-chenzhou10@huawei.com>
Add documentation for DT property used by arm64 kdump:
linux,low-memory-range.
"linux,low-memory-range" is an another memory region used for crash
dump kernel devices.
Signed-off-by: Chen Zhou <chenzhou10@huawei.com>
---
Documentation/devicetree/bindings/chosen.txt | 25 ++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/Documentation/devicetree/bindings/chosen.txt b/Documentation/devicetree/bindings/chosen.txt
index 45e79172a646..bfe6fb6976e6 100644
--- a/Documentation/devicetree/bindings/chosen.txt
+++ b/Documentation/devicetree/bindings/chosen.txt
@@ -103,6 +103,31 @@ While this property does not represent a real hardware, the address
and the size are expressed in #address-cells and #size-cells,
respectively, of the root node.
+linux,low-memory-range
+----------------------
+This property (arm64 only) holds a base address and size, describing a
+limited region below 4G. Similar to "linux,usable-memory-range", it is
+an another memory range which may be considered available for use by the
+kernel.
+
+e.g.
+
+/ {
+ chosen {
+ linux,low-memory-range = <0x0 0x70000000 0x0 0x10000000>;
+ linux,usable-memory-range = <0x202f 0xc0000000 0x0 0x40000000>;
+ };
+};
+
+The main usage is for crash dump kernel devices when reserving crashkernel
+above 4G. When reserving crashkernel above 4G, there may be two crash kernel
+regions, one is below 4G, the other is above 4G. In order to distinct from
+the high region, use this property to pass the low region.
+
+While this property does not represent a real hardware, the address
+and the size are expressed in #address-cells and #size-cells,
+respectively, of the root node.
+
linux,elfcorehdr
----------------
--
2.20.1
^ permalink raw reply related
* [PATCH v8 0/5] support reserving crashkernel above 4G on arm64 kdump
From: Chen Zhou @ 2020-05-21 9:38 UTC (permalink / raw)
To: tglx, mingo, catalin.marinas, will, dyoung, bhe, robh+dt
Cc: arnd, John.p.donnelly, pkushwaha, horms, guohanjun, chenzhou10,
linux-arm-kernel, devicetree, linux-doc, linux-kernel, kexec
This patch series enable reserving crashkernel above 4G in arm64.
There are following issues in arm64 kdump:
1. We use crashkernel=X to reserve crashkernel below 4G, which will fail
when there is no enough low memory.
2. Currently, crashkernel=Y@X can be used to reserve crashkernel above 4G,
in this case, if swiotlb or DMA buffers are required, crash dump kernel
will boot failure because there is no low memory available for allocation.
To solve these issues, introduce crashkernel=X,low to reserve specified
size low memory.
Crashkernel=X tries to reserve memory for the crash dump kernel under
4G. If crashkernel=Y,low is specified simultaneously, reserve spcified
size low memory for crash kdump kernel devices firstly and then reserve
memory above 4G.
When crashkernel is reserved above 4G in memory, that is, crashkernel=X,low
is specified simultaneously, kernel should reserve specified size low memory
for crash dump kernel devices. So there may be two crash kernel regions, one
is below 4G, the other is above 4G.
In order to distinct from the high region and make no effect to the use of
kexec-tools, rename the low region as "Crash kernel (low)", and add DT property
"linux,low-memory-range" to crash dump kernel's dtb to pass the low region.
Besides, we need to modify kexec-tools:
arm64: kdump: add another DT property to crash dump kernel's dtb(see [1])
The previous changes and discussions can be retrieved from:
Changes since [v7]
- Move x86 CRASH_ALIGN to 2M
Suggested by Dave and do some test, move x86 CRASH_ALIGN to 2M.
- Update Documentation/devicetree/bindings/chosen.txt
Add corresponding documentation to Documentation/devicetree/bindings/chosen.txt suggested by Arnd.
- Add Tested-by from Jhon and pk
Changes since [v6]
- Fix build errors reported by kbuild test robot.
Changes since [v5]
- Move reserve_crashkernel_low() into kernel/crash_core.c.
- Delete crashkernel=X,high.
- Modify crashkernel=X,low.
If crashkernel=X,low is specified simultaneously, reserve spcified size low
memory for crash kdump kernel devices firstly and then reserve memory above 4G.
In addition, rename crashk_low_res as "Crash kernel (low)" for arm64, and then
pass to crash dump kernel by DT property "linux,low-memory-range".
- Update Documentation/admin-guide/kdump/kdump.rst.
Changes since [v4]
- Reimplement memblock_cap_memory_ranges for multiple ranges by Mike.
Changes since [v3]
- Add memblock_cap_memory_ranges back for multiple ranges.
- Fix some compiling warnings.
Changes since [v2]
- Split patch "arm64: kdump: support reserving crashkernel above 4G" as
two. Put "move reserve_crashkernel_low() into kexec_core.c" in a separate
patch.
Changes since [v1]:
- Move common reserve_crashkernel_low() code into kernel/kexec_core.c.
- Remove memblock_cap_memory_ranges() i added in v1 and implement that
in fdt_enforce_memory_region().
There are at most two crash kernel regions, for two crash kernel regions
case, we cap the memory range [min(regs[*].start), max(regs[*].end)]
and then remove the memory range in the middle.
[1]: http://lists.infradead.org/pipermail/kexec/2020-May/025128.html
[v1]: https://lkml.org/lkml/2019/4/2/1174
[v2]: https://lkml.org/lkml/2019/4/9/86
[v3]: https://lkml.org/lkml/2019/4/9/306
[v4]: https://lkml.org/lkml/2019/4/15/273
[v5]: https://lkml.org/lkml/2019/5/6/1360
[v6]: https://lkml.org/lkml/2019/8/30/142
[v7]: https://lkml.org/lkml/2019/12/23/411
Chen Zhou (5):
x86: kdump: move reserve_crashkernel_low() into crash_core.c
arm64: kdump: reserve crashkenel above 4G for crash dump kernel
arm64: kdump: add memory for devices by DT property, low-memory-range
kdump: update Documentation about crashkernel on arm64
dt-bindings: chosen: Document linux,low-memory-range for arm64 kdump
Documentation/admin-guide/kdump/kdump.rst | 13 ++-
.../admin-guide/kernel-parameters.txt | 12 ++-
Documentation/devicetree/bindings/chosen.txt | 25 ++++++
arch/arm64/kernel/setup.c | 8 +-
arch/arm64/mm/init.c | 61 ++++++++++++-
arch/x86/kernel/setup.c | 66 ++------------
include/linux/crash_core.h | 3 +
include/linux/kexec.h | 2 -
kernel/crash_core.c | 85 +++++++++++++++++++
kernel/kexec_core.c | 17 ----
10 files changed, 208 insertions(+), 84 deletions(-)
--
2.20.1
^ permalink raw reply
* [PATCH v8 4/5] kdump: update Documentation about crashkernel on arm64
From: Chen Zhou @ 2020-05-21 9:38 UTC (permalink / raw)
To: tglx, mingo, catalin.marinas, will, dyoung, bhe, robh+dt
Cc: arnd, John.p.donnelly, pkushwaha, horms, guohanjun, chenzhou10,
linux-arm-kernel, devicetree, linux-doc, linux-kernel, kexec
In-Reply-To: <20200521093805.64398-1-chenzhou10@huawei.com>
Now we support crashkernel=X,[low] on arm64, update the Documentation.
Signed-off-by: Chen Zhou <chenzhou10@huawei.com>
Tested-by: John Donnelly <John.p.donnelly@oracle.com>
Tested-by: Prabhakar Kushwaha <pkushwaha@marvell.com>
---
Documentation/admin-guide/kdump/kdump.rst | 13 +++++++++++--
Documentation/admin-guide/kernel-parameters.txt | 12 +++++++++++-
2 files changed, 22 insertions(+), 3 deletions(-)
diff --git a/Documentation/admin-guide/kdump/kdump.rst b/Documentation/admin-guide/kdump/kdump.rst
index ac7e131d2935..e55173ec1666 100644
--- a/Documentation/admin-guide/kdump/kdump.rst
+++ b/Documentation/admin-guide/kdump/kdump.rst
@@ -299,7 +299,13 @@ Boot into System Kernel
"crashkernel=64M@16M" tells the system kernel to reserve 64 MB of memory
starting at physical address 0x01000000 (16MB) for the dump-capture kernel.
- On x86 and x86_64, use "crashkernel=64M@16M".
+ On x86 use "crashkernel=64M@16M".
+
+ On x86_64, use "crashkernel=Y[@X]" to select a region under 4G first, and
+ fall back to reserve region above 4G when '@offset' hasn't been specified.
+ We can also use "crashkernel=X,high" to select a region above 4G, which
+ also tries to allocate at least 256M below 4G automatically and
+ "crashkernel=Y,low" can be used to allocate specified size low memory.
On ppc64, use "crashkernel=128M@32M".
@@ -316,8 +322,11 @@ Boot into System Kernel
kernel will automatically locate the crash kernel image within the
first 512MB of RAM if X is not given.
- On arm64, use "crashkernel=Y[@X]". Note that the start address of
+ On arm64, use "crashkernel=Y[@X]". Note that the start address of
the kernel, X if explicitly specified, must be aligned to 2MiB (0x200000).
+ If crashkernel=Z,low is specified simultaneously, reserve spcified size
+ low memory for crash kdump kernel devices firstly and then reserve memory
+ above 4G.
Load the Dump-capture Kernel
============================
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 7bc83f3d9bdf..97695783b817 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -722,6 +722,9 @@
[KNL, x86_64] select a region under 4G first, and
fall back to reserve region above 4G when '@offset'
hasn't been specified.
+ [KNL, arm64] If crashkernel=X,low is specified, reserve
+ spcified size low memory for crash kdump kernel devices
+ firstly, and then reserve memory above 4G.
See Documentation/admin-guide/kdump/kdump.rst for further details.
crashkernel=range1:size1[,range2:size2,...][@offset]
@@ -746,12 +749,19 @@
requires at least 64M+32K low memory, also enough extra
low memory is needed to make sure DMA buffers for 32-bit
devices won't run out. Kernel would try to allocate at
- at least 256M below 4G automatically.
+ least 256M below 4G automatically.
This one let user to specify own low range under 4G
for second kernel instead.
0: to disable low allocation.
It will be ignored when crashkernel=X,high is not used
or memory reserved is below 4G.
+ [KNL, arm64] range under 4G.
+ This one let user to specify own low range under 4G
+ for crash dump kernel instead.
+ Different with x86_64, kernel allocates specified size
+ physical memory region only when this parameter is specified
+ instead of trying to allocate at least 256M below 4G
+ automatically.
cryptomgr.notests
[KNL] Disable crypto self-tests
--
2.20.1
^ permalink raw reply related
* [PATCH v8 3/5] arm64: kdump: add memory for devices by DT property, low-memory-range
From: Chen Zhou @ 2020-05-21 9:38 UTC (permalink / raw)
To: tglx, mingo, catalin.marinas, will, dyoung, bhe, robh+dt
Cc: arnd, John.p.donnelly, pkushwaha, horms, guohanjun, chenzhou10,
linux-arm-kernel, devicetree, linux-doc, linux-kernel, kexec
In-Reply-To: <20200521093805.64398-1-chenzhou10@huawei.com>
If we want to reserve crashkernel above 4G, we could use parameters
"crashkernel=X crashkernel=Y,low", in this case, specified size low
memory is reserved for crash dump kernel devices and never mapped by
the first kernel. This memory range is advertised to crash dump kernel
via DT property under /chosen,
linux,low-memory-range=<BASE SIZE>
Crash dump kernel reads this property at boot time and call
memblock_add() after memblock_cap_memory_range() has been called.
Signed-off-by: Chen Zhou <chenzhou10@huawei.com>
Tested-by: John Donnelly <John.p.donnelly@oracle.com>
Tested-by: Prabhakar Kushwaha <pkushwaha@marvell.com>
---
arch/arm64/mm/init.c | 30 +++++++++++++++++++++++++++++-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index 71498acf0cd8..fcc3abee7003 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -323,6 +323,26 @@ static int __init early_mem(char *p)
}
early_param("mem", early_mem);
+static int __init early_init_dt_scan_lowmem(unsigned long node,
+ const char *uname, int depth, void *data)
+{
+ struct memblock_region *lowmem = data;
+ const __be32 *reg;
+ int len;
+
+ if (depth != 1 || strcmp(uname, "chosen") != 0)
+ return 0;
+
+ reg = of_get_flat_dt_prop(node, "linux,low-memory-range", &len);
+ if (!reg || (len < (dt_root_addr_cells + dt_root_size_cells)))
+ return 1;
+
+ lowmem->base = dt_mem_next_cell(dt_root_addr_cells, ®);
+ lowmem->size = dt_mem_next_cell(dt_root_size_cells, ®);
+
+ return 1;
+}
+
static int __init early_init_dt_scan_usablemem(unsigned long node,
const char *uname, int depth, void *data)
{
@@ -353,13 +373,21 @@ static void __init fdt_enforce_memory_region(void)
if (reg.size)
memblock_cap_memory_range(reg.base, reg.size);
+
+ of_scan_flat_dt(early_init_dt_scan_lowmem, ®);
+
+ if (reg.size)
+ memblock_add(reg.base, reg.size);
}
void __init arm64_memblock_init(void)
{
const s64 linear_region_size = BIT(vabits_actual - 1);
- /* Handle linux,usable-memory-range property */
+ /*
+ * Handle linux,usable-memory-range and linux,low-memory-range
+ * properties.
+ */
fdt_enforce_memory_region();
/* Remove memory above our supported physical address size */
--
2.20.1
^ permalink raw reply related
* [PATCH v8 2/5] arm64: kdump: reserve crashkenel above 4G for crash dump kernel
From: Chen Zhou @ 2020-05-21 9:38 UTC (permalink / raw)
To: tglx, mingo, catalin.marinas, will, dyoung, bhe, robh+dt
Cc: arnd, John.p.donnelly, pkushwaha, horms, guohanjun, chenzhou10,
linux-arm-kernel, devicetree, linux-doc, linux-kernel, kexec
In-Reply-To: <20200521093805.64398-1-chenzhou10@huawei.com>
Crashkernel=X tries to reserve memory for the crash dump kernel under
4G. If crashkernel=X,low is specified simultaneously, reserve spcified
size low memory for crash kdump kernel devices firstly and then reserve
memory above 4G.
Signed-off-by: Chen Zhou <chenzhou10@huawei.com>
Tested-by: John Donnelly <John.p.donnelly@oracle.com>
Tested-by: Prabhakar Kushwaha <pkushwaha@marvell.com>
---
arch/arm64/kernel/setup.c | 8 +++++++-
arch/arm64/mm/init.c | 31 +++++++++++++++++++++++++++++--
2 files changed, 36 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
index 3fd2c11c09fc..a8487e4d3e5a 100644
--- a/arch/arm64/kernel/setup.c
+++ b/arch/arm64/kernel/setup.c
@@ -238,7 +238,13 @@ static void __init request_standard_resources(void)
kernel_data.end <= res->end)
request_resource(res, &kernel_data);
#ifdef CONFIG_KEXEC_CORE
- /* Userspace will find "Crash kernel" region in /proc/iomem. */
+ /*
+ * Userspace will find "Crash kernel" region in /proc/iomem.
+ * Note: the low region is renamed as Crash kernel (low).
+ */
+ if (crashk_low_res.end && crashk_low_res.start >= res->start &&
+ crashk_low_res.end <= res->end)
+ request_resource(res, &crashk_low_res);
if (crashk_res.end && crashk_res.start >= res->start &&
crashk_res.end <= res->end)
request_resource(res, &crashk_res);
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index e42727e3568e..71498acf0cd8 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -81,6 +81,7 @@ static void __init reserve_crashkernel(void)
{
unsigned long long crash_base, crash_size;
int ret;
+ phys_addr_t crash_max = arm64_dma32_phys_limit;
ret = parse_crashkernel(boot_command_line, memblock_phys_mem_size(),
&crash_size, &crash_base);
@@ -88,12 +89,38 @@ static void __init reserve_crashkernel(void)
if (ret || !crash_size)
return;
+ ret = reserve_crashkernel_low();
+ if (!ret && crashk_low_res.end) {
+ /*
+ * If crashkernel=X,low specified, there may be two regions,
+ * we need to make some changes as follows:
+ *
+ * 1. rename the low region as "Crash kernel (low)"
+ * In order to distinct from the high region and make no effect
+ * to the use of existing kexec-tools, rename the low region as
+ * "Crash kernel (low)".
+ *
+ * 2. change the upper bound for crash memory
+ * Set MEMBLOCK_ALLOC_ACCESSIBLE upper bound for crash memory.
+ *
+ * 3. mark the low region as "nomap"
+ * The low region is intended to be used for crash dump kernel
+ * devices, just mark the low region as "nomap" simply.
+ */
+ const char *rename = "Crash kernel (low)";
+
+ crashk_low_res.name = rename;
+ crash_max = MEMBLOCK_ALLOC_ACCESSIBLE;
+ memblock_mark_nomap(crashk_low_res.start,
+ resource_size(&crashk_low_res));
+ }
+
crash_size = PAGE_ALIGN(crash_size);
if (crash_base == 0) {
/* Current arm64 boot protocol requires 2MB alignment */
- crash_base = memblock_find_in_range(0, arm64_dma32_phys_limit,
- crash_size, SZ_2M);
+ crash_base = memblock_find_in_range(0, crash_max, crash_size,
+ SZ_2M);
if (crash_base == 0) {
pr_warn("cannot allocate crashkernel (size:0x%llx)\n",
crash_size);
--
2.20.1
^ permalink raw reply related
* [PATCH v2 5/9] dt-bindings: media: Convert marvell,mmp2-ccic to json-schema
From: Lubomir Rintel @ 2020-05-21 9:13 UTC (permalink / raw)
To: Rob Herring
Cc: Alessandro Zummo, Alexandre Belloni, Bartosz Golaszewski,
Daniel Lezcano, Jason Cooper, Linus Walleij, Marc Zyngier,
Thomas Gleixner, Ulf Hansson, devicetree, linux-kernel,
Lubomir Rintel
In-Reply-To: <20200521091356.2211020-1-lkundrak@v3.sk>
Convert the marvell,mmp2-ccic binding to DT schema format using
json-schema. While at that this drops the "func" and "phy" clocks.
The driver consumes clocks with those names, but it's not clear
what are they for and they are not used in DT systems. "phy" is
probably a clock for the sensor and it would belong in the sensor
node.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
Changes since v1:
- Fix indentation
- Drop clocks other than "axi"
- s/GPL-2.0-or-later/GPL-2.0-only/
.../bindings/media/marvell,mmp2-ccic.txt | 50 ----------
.../bindings/media/marvell,mmp2-ccic.yaml | 97 +++++++++++++++++++
2 files changed, 97 insertions(+), 50 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/media/marvell,mmp2-ccic.txt
create mode 100644 Documentation/devicetree/bindings/media/marvell,mmp2-ccic.yaml
diff --git a/Documentation/devicetree/bindings/media/marvell,mmp2-ccic.txt b/Documentation/devicetree/bindings/media/marvell,mmp2-ccic.txt
deleted file mode 100644
index 7ec2c8c8a3b9..000000000000
--- a/Documentation/devicetree/bindings/media/marvell,mmp2-ccic.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-Marvell MMP2 camera host interface
-
-Required properties:
- - compatible: Should be "marvell,mmp2-ccic".
- - reg: Register base and size.
- - interrupts: The interrupt number.
- - #clock-cells: Must be 0.
-
-Optional properties:
- - clocks: Reference to the input clock as specified by
- Documentation/devicetree/bindings/clock/clock-bindings.txt.
- - clock-names: Names of the clocks used; "axi" for the AXI bus interface,
- "func" for the peripheral clock and "phy" for the parallel
- video bus interface.
- - clock-output-names: Optional clock source for sensors. Shall be "mclk".
-
-Required subnodes:
- - port: The parallel bus interface port with a single endpoint linked to
- the sensor's endpoint as described in
- Documentation/devicetree/bindings/media/video-interfaces.txt.
-
-Required endpoint properties:
- - bus-type: data bus type, <5> or <6> for Parallel or Bt.656 respectively
- - pclk-sample: pixel clock polarity
- - hsync-active: horizontal synchronization polarity (only required for
- parallel bus)
- - vsync-active: vertical synchronization polarity (only required for
- parallel bus)
-
-Example:
-
- camera0: camera@d420a000 {
- compatible = "marvell,mmp2-ccic";
- reg = <0xd420a000 0x800>;
- interrupts = <42>;
- clocks = <&soc_clocks MMP2_CLK_CCIC0>;
- clock-names = "axi";
- #clock-cells = <0>;
- clock-output-names = "mclk";
-
- port {
- camera0_0: endpoint {
- remote-endpoint = <&ov7670_0>;
- bus-type = <5>; /* Parallel */
- hsync-active = <1>; /* Active high */
- vsync-active = <1>; /* Active high */
- pclk-sample = <0>; /* Falling */
- };
- };
- };
diff --git a/Documentation/devicetree/bindings/media/marvell,mmp2-ccic.yaml b/Documentation/devicetree/bindings/media/marvell,mmp2-ccic.yaml
new file mode 100644
index 000000000000..fb399de668bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/marvell,mmp2-ccic.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2019,2020 Lubomir Rintel <lkundrak@v3.sk>
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/marvell,mmp2-ccic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell MMP2 camera host interface bindings
+
+maintainers:
+ - Lubomir Rintel <lkundrak@v3.sk>
+
+properties:
+ $nodename:
+ pattern: '^camera@[a-f0-9]+$'
+
+ compatible:
+ const: marvell,mmp2-ccic
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ port:
+ type: object
+ additionalProperties: false
+
+ properties:
+ endpoint:
+ type: object
+ additionalProperties: false
+
+ # Properties described in
+ # Documentation/devicetree/bindings/media/video-interfaces.txt
+ properties:
+ remote-endpoint: true
+ hsync-active: true
+ vsync-active: true
+ pclk-sample: true
+ bus-type: true
+
+ required:
+ - remote-endpoint
+
+ required:
+ - endpoint
+
+ clocks:
+ minItems: 1
+ maxItems: 3
+ items:
+ - description: AXI bus interface clock
+ - description: Peripheral clock
+ - description: Parallel video bus interface clock
+
+ clock-names:
+ const: axi
+
+ '#clock-cells':
+ const: 0
+
+ clock-output-names:
+ const: mclk
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - port
+
+examples:
+ - |
+ #include <dt-bindings/clock/marvell,mmp2.h>
+
+ camera@d420a000 {
+ compatible = "marvell,mmp2-ccic";
+ reg = <0xd420a000 0x800>;
+ interrupts = <42>;
+ clocks = <&soc_clocks MMP2_CLK_CCIC0>;
+ clock-names = "axi";
+ #clock-cells = <0>;
+ clock-output-names = "mclk";
+
+ port {
+ camera0_0: endpoint {
+ remote-endpoint = <&ov7670_0>;
+ bus-type = <5>; /* Parallel */
+ hsync-active = <1>; /* Active high */
+ vsync-active = <1>; /* Active high */
+ pclk-sample = <0>; /* Falling */
+ };
+ };
+ };
+
+...
--
2.26.2
^ permalink raw reply related
* [PATCH v2 3/9] dt-bindings: i2c: Convert i2c-pxa to json-schema
From: Lubomir Rintel @ 2020-05-21 9:13 UTC (permalink / raw)
To: Rob Herring
Cc: Alessandro Zummo, Alexandre Belloni, Bartosz Golaszewski,
Daniel Lezcano, Jason Cooper, Linus Walleij, Marc Zyngier,
Thomas Gleixner, Ulf Hansson, devicetree, linux-kernel,
Lubomir Rintel
In-Reply-To: <20200521091356.2211020-1-lkundrak@v3.sk>
A conversion of the i2c-pxa binding to DT schema format using json-schema.
This also cleans ups some errors in the binding: The compatible string
description suggested that "mmp" in "mrvl,mmp-twsi" is to be substituted
with a processor model, which wouldn't be a right thing to do and indeed
nobody seems to have been doing that. There also was "Recommended
properties" section that included optional as well as mandatory
properties. Missing mandatory properties were added to the example.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
Changes since v1:
- Add default GPL-2.0-only license tag
- Fill in maintainers from MAINTAINERS file
.../devicetree/bindings/i2c/i2c-pxa.txt | 31 --------
.../devicetree/bindings/i2c/i2c-pxa.yaml | 72 +++++++++++++++++++
2 files changed, 72 insertions(+), 31 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-pxa.txt
create mode 100644 Documentation/devicetree/bindings/i2c/i2c-pxa.yaml
diff --git a/Documentation/devicetree/bindings/i2c/i2c-pxa.txt b/Documentation/devicetree/bindings/i2c/i2c-pxa.txt
deleted file mode 100644
index c30783c0eca0..000000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-pxa.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-* Marvell MMP I2C controller
-
-Required properties :
-
- - reg : Offset and length of the register set for the device
- - compatible : should be "mrvl,mmp-twsi" where mmp is the name of a
- compatible processor, e.g. pxa168, pxa910, mmp2, mmp3.
- For the pxa2xx/pxa3xx, an additional node "mrvl,pxa-i2c" is required
- as shown in the example below.
- For the Armada 3700, the compatible should be "marvell,armada-3700-i2c".
-
-Recommended properties :
-
- - interrupts : the interrupt number
- - mrvl,i2c-polling : Disable interrupt of i2c controller. Polling
- status register of i2c controller instead.
- - mrvl,i2c-fast-mode : Enable fast mode of i2c controller.
-
-Examples:
- twsi1: i2c@d4011000 {
- compatible = "mrvl,mmp-twsi";
- reg = <0xd4011000 0x1000>;
- interrupts = <7>;
- mrvl,i2c-fast-mode;
- };
-
- twsi2: i2c@d4025000 {
- compatible = "mrvl,mmp-twsi";
- reg = <0xd4025000 0x1000>;
- interrupts = <58>;
- };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-pxa.yaml b/Documentation/devicetree/bindings/i2c/i2c-pxa.yaml
new file mode 100644
index 000000000000..19c81972243d
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-pxa.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/i2c-pxa.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell MMP I2C controller bindings
+
+maintainers:
+ - Rob Herring <robh+dt@kernel.org>
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+ - if:
+ not:
+ required:
+ - mrvl,i2c-polling
+ then:
+ required:
+ - interrupts
+
+properties:
+ compatible:
+ enum:
+ - mrvl,mmp-twsi
+ - mrvl,pxa-i2c
+ - marvell,armada-3700-i2c
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+
+ resets:
+ minItems: 1
+
+ mrvl,i2c-polling:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: |
+ Disable interrupt of i2c controller. Polling status register of i2c
+ controller instead.
+
+ mrvl,i2c-fast-mode:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description: Enable fast mode of i2c controller.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - '#address-cells'
+ - '#size-cells'
+
+examples:
+ - |
+ #include <dt-bindings/clock/marvell,mmp2.h>
+ i2c@d4011000 {
+ compatible = "mrvl,mmp-twsi";
+ reg = <0xd4011000 0x1000>;
+ interrupts = <7>;
+ clocks = <&soc_clocks MMP2_CLK_TWSI1>;
+ mrvl,i2c-fast-mode;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+...
--
2.26.2
^ permalink raw reply related
* [PATCH v2 2/9] dt-bindings: gpio: Convert mrvl-gpio to json-schema
From: Lubomir Rintel @ 2020-05-21 9:13 UTC (permalink / raw)
To: Rob Herring
Cc: Alessandro Zummo, Alexandre Belloni, Bartosz Golaszewski,
Daniel Lezcano, Jason Cooper, Linus Walleij, Marc Zyngier,
Thomas Gleixner, Ulf Hansson, devicetree, linux-kernel,
Lubomir Rintel
In-Reply-To: <20200521091356.2211020-1-lkundrak@v3.sk>
This converts the mrvl-gpio binding to DT schema format using json-schema.
Various fixes were done during the conversion, such as adding more
properties that are in fact mandatory or extending the examples to
include child nodes with extra GPIO blocks.
The compatible strings are a mess. It is not clear why so many of them
are needed; the driver doesn't really seem to differentiate between the
models. Some of them, like marvell,pxa93x-gpio and marvell,pxa1928-gpio
are not used at all, so it's not known how many interrupts they utilize.
On the other hand, mrvl,pxa-gpio has been seen in the tree, but it
doesn't end up in any actual DTB file.
In any case -- the schema merely copies whatever was in the original
binding document, so it's hopefully no more wrong that the original.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
Changes since v1:
- Drop marvell,pxa1928-gpio
- Drop ranges from example with no gcb child nodes
- Add default GPL-2.0-only license tag
- Fill in maintainers from MAINTAINERS file
.../devicetree/bindings/gpio/mrvl-gpio.txt | 48 -----
.../devicetree/bindings/gpio/mrvl-gpio.yaml | 174 ++++++++++++++++++
2 files changed, 174 insertions(+), 48 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
create mode 100644 Documentation/devicetree/bindings/gpio/mrvl-gpio.yaml
diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
deleted file mode 100644
index 30fd2201b3d4..000000000000
--- a/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-* Marvell PXA GPIO controller
-
-Required properties:
-- compatible : Should be "intel,pxa25x-gpio", "intel,pxa26x-gpio",
- "intel,pxa27x-gpio", "intel,pxa3xx-gpio",
- "marvell,pxa93x-gpio", "marvell,mmp-gpio",
- "marvell,mmp2-gpio" or marvell,pxa1928-gpio.
-- reg : Address and length of the register set for the device
-- interrupts : Should be the port interrupt shared by all gpio pins.
- There're three gpio interrupts in arch-pxa, and they're gpio0,
- gpio1 and gpio_mux. There're only one gpio interrupt in arch-mmp,
- gpio_mux.
-- interrupt-names : Should be the names of irq resources. Each interrupt
- uses its own interrupt name, so there should be as many interrupt names
- as referenced interrupts.
-- interrupt-controller : Identifies the node as an interrupt controller.
-- #interrupt-cells: Specifies the number of cells needed to encode an
- interrupt source.
-- gpio-controller : Marks the device node as a gpio controller.
-- #gpio-cells : Should be two. The first cell is the pin number and
- the second cell is used to specify flags. See gpio.txt for possible
- values.
-
-Example for a MMP platform:
-
- gpio: gpio@d4019000 {
- compatible = "marvell,mmp-gpio";
- reg = <0xd4019000 0x1000>;
- interrupts = <49>;
- interrupt-names = "gpio_mux";
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <1>;
- };
-
-Example for a PXA3xx platform:
-
- gpio: gpio@40e00000 {
- compatible = "intel,pxa3xx-gpio";
- reg = <0x40e00000 0x10000>;
- interrupt-names = "gpio0", "gpio1", "gpio_mux";
- interrupts = <8 9 10>;
- gpio-controller;
- #gpio-cells = <0x2>;
- interrupt-controller;
- #interrupt-cells = <0x2>;
- };
diff --git a/Documentation/devicetree/bindings/gpio/mrvl-gpio.yaml b/Documentation/devicetree/bindings/gpio/mrvl-gpio.yaml
new file mode 100644
index 000000000000..575ccc75ae30
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/mrvl-gpio.yaml
@@ -0,0 +1,174 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/mrvl-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell PXA GPIO controller
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+ - Bartosz Golaszewski <bgolaszewski@baylibre.com>
+ - Rob Herring <robh+dt@kernel.org>
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - intel,pxa25x-gpio
+ - intel,pxa26x-gpio
+ - intel,pxa27x-gpio
+ - intel,pxa3xx-gpio
+ then:
+ properties:
+ interrupts:
+ minItems: 3
+ maxItems: 3
+ interrupt-names:
+ items:
+ - const: gpio0
+ - const: gpio1
+ - const: gpio_mux
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - marvell,mmp-gpio
+ - marvell,mmp2-gpio
+ then:
+ properties:
+ interrupts:
+ maxItems: 1
+ interrupt-names:
+ items:
+ - const: gpio_mux
+
+properties:
+ $nodename:
+ pattern: '^gpio@[0-9a-f]+$'
+
+ compatible:
+ enum:
+ - intel,pxa25x-gpio
+ - intel,pxa26x-gpio
+ - intel,pxa27x-gpio
+ - intel,pxa3xx-gpio
+ - marvell,mmp-gpio
+ - marvell,mmp2-gpio
+ - marvell,pxa93x-gpio
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ ranges: true
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ gpio-ranges:
+ maxItems: 1
+
+ interrupts: true
+
+ interrupt-names: true
+
+ interrupt-controller: true
+
+ '#interrupt-cells':
+ const: 2
+
+patternProperties:
+ '^gpio@[0-9a-f]*$':
+ type: object
+ properties:
+ reg:
+ maxItems: 1
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - '#address-cells'
+ - '#size-cells'
+ - reg
+ - gpio-controller
+ - '#gpio-cells'
+ - interrupts
+ - interrupt-names
+ - interrupt-controller
+ - '#interrupt-cells'
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/pxa-clock.h>
+ gpio@40e00000 {
+ compatible = "intel,pxa3xx-gpio";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x40e00000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <8>, <9>, <10>;
+ interrupt-names = "gpio0", "gpio1", "gpio_mux";
+ clocks = <&clks CLK_GPIO>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ - |
+ #include <dt-bindings/clock/marvell,pxa910.h>
+ gpio@d4019000 {
+ compatible = "marvell,mmp-gpio";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0xd4019000 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupts = <49>;
+ interrupt-names = "gpio_mux";
+ clocks = <&soc_clocks PXA910_CLK_GPIO>;
+ resets = <&soc_clocks PXA910_CLK_GPIO>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ ranges;
+
+ gpio@d4019000 {
+ reg = <0xd4019000 0x4>;
+ };
+
+ gpio@d4019004 {
+ reg = <0xd4019004 0x4>;
+ };
+
+ gpio@d4019008 {
+ reg = <0xd4019008 0x4>;
+ };
+
+ gpio@d4019100 {
+ reg = <0xd4019100 0x4>;
+ };
+ };
+
+...
--
2.26.2
^ permalink raw reply related
* [PATCH v2 1/9] dt-bindings: mmc: Convert sdhci-pxa to json-schema
From: Lubomir Rintel @ 2020-05-21 9:13 UTC (permalink / raw)
To: Rob Herring
Cc: Alessandro Zummo, Alexandre Belloni, Bartosz Golaszewski,
Daniel Lezcano, Jason Cooper, Linus Walleij, Marc Zyngier,
Thomas Gleixner, Ulf Hansson, devicetree, linux-kernel,
Lubomir Rintel
In-Reply-To: <20200521091356.2211020-1-lkundrak@v3.sk>
Convert the sdhci-pxa binding to DT schema format using json-schema.
At the same time, fix a couple of issues with the examples discovered by
the validation tool -- a semicolon instead of a comma and wrong node names.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
Changes since v1:
- move reg-names items: from the conditional to main properties:, only
specify maxItems and minItems in conditional branches
- Specify minItems and maxItems in properties/reg instad of on
conditional branchs
- Add default GPL-2.0-only license tag
- Fill in maintainers from MAINTAINERS file
.../devicetree/bindings/mmc/sdhci-pxa.txt | 50 ---------
.../devicetree/bindings/mmc/sdhci-pxa.yaml | 103 ++++++++++++++++++
2 files changed, 103 insertions(+), 50 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
create mode 100644 Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt b/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
deleted file mode 100644
index 3d1b449d6097..000000000000
--- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-* Marvell sdhci-pxa v2/v3 controller
-
-This file documents differences between the core properties in mmc.txt
-and the properties used by the sdhci-pxav2 and sdhci-pxav3 drivers.
-
-Required properties:
-- compatible: Should be "mrvl,pxav2-mmc", "mrvl,pxav3-mmc" or
- "marvell,armada-380-sdhci".
-- reg:
- * for "mrvl,pxav2-mmc" and "mrvl,pxav3-mmc", one register area for
- the SDHCI registers.
-
- * for "marvell,armada-380-sdhci", three register areas. The first
- one for the SDHCI registers themselves, the second one for the
- AXI/Mbus bridge registers of the SDHCI unit, the third one for the
- SDIO3 Configuration register
-- reg names: should be "sdhci", "mbus", "conf-sdio3". only mandatory
- for "marvell,armada-380-sdhci"
-- clocks: Array of clocks required for SDHCI; requires at least one for
- I/O clock.
-- clock-names: Array of names corresponding to clocks property; shall be
- "io" for I/O clock and "core" for optional core clock.
-
-Optional properties:
-- mrvl,clk-delay-cycles: Specify a number of cycles to delay for tuning.
-
-Example:
-
-sdhci@d4280800 {
- compatible = "mrvl,pxav3-mmc";
- reg = <0xd4280800 0x800>;
- bus-width = <8>;
- interrupts = <27>;
- clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>;
- clock-names = "io", "core";
- non-removable;
- mrvl,clk-delay-cycles = <31>;
-};
-
-sdhci@d8000 {
- compatible = "marvell,armada-380-sdhci";
- reg-names = "sdhci", "mbus", "conf-sdio3";
- reg = <0xd8000 0x1000>,
- <0xdc000 0x100>;
- <0x18454 0x4>;
- interrupts = <0 25 0x4>;
- clocks = <&gateclk 17>;
- clock-names = "io";
- mrvl,clk-delay-cycles = <0x1F>;
-};
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml b/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml
new file mode 100644
index 000000000000..27ea069aa5fc
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/sdhci-pxa.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell PXA SDHCI v2/v3 bindings
+
+maintainers:
+ - Ulf Hansson <ulf.hansson@linaro.org>
+ - Rob Herring <robh+dt@kernel.org>
+
+allOf:
+ - $ref: mmc-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: marvell,armada-380-sdhci
+ then:
+ properties:
+ regs:
+ minItems: 3
+ reg-names:
+ minItems: 3
+ required:
+ - reg-names
+ else:
+ properties:
+ regs:
+ maxItems: 1
+ reg-names:
+ maxItems: 1
+
+properties:
+ compatible:
+ enum:
+ - mrvl,pxav2-mmc
+ - mrvl,pxav3-mmc
+ - marvell,armada-380-sdhci
+
+ reg:
+ minItems: 1
+ maxItems: 3
+
+ reg-names:
+ items:
+ - const: sdhci
+ - const: mbus
+ - const: conf-sdio3
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: io
+ - const: core
+
+ mrvl,clk-delay-cycles:
+ description: Specify a number of cycles to delay for tuning.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+examples:
+ - |
+ #include <dt-bindings/clock/berlin2.h>
+ mmc@d4280800 {
+ compatible = "mrvl,pxav3-mmc";
+ reg = <0xd4280800 0x800>;
+ bus-width = <8>;
+ interrupts = <27>;
+ clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>;
+ clock-names = "io", "core";
+ non-removable;
+ mrvl,clk-delay-cycles = <31>;
+ };
+ - |
+ mmc@d8000 {
+ compatible = "marvell,armada-380-sdhci";
+ reg-names = "sdhci", "mbus", "conf-sdio3";
+ reg = <0xd8000 0x1000>,
+ <0xdc000 0x100>,
+ <0x18454 0x4>;
+ interrupts = <0 25 0x4>;
+ clocks = <&gateclk 17>;
+ clock-names = "io";
+ mrvl,clk-delay-cycles = <0x1F>;
+ };
+
+...
--
2.26.2
^ permalink raw reply related
* [PATCH v2 4/9] dt-bindings: interrupt-controller: Convert mrvl,intc to json-schema
From: Lubomir Rintel @ 2020-05-21 9:13 UTC (permalink / raw)
To: Rob Herring
Cc: Alessandro Zummo, Alexandre Belloni, Bartosz Golaszewski,
Daniel Lezcano, Jason Cooper, Linus Walleij, Marc Zyngier,
Thomas Gleixner, Ulf Hansson, devicetree, linux-kernel,
Lubomir Rintel
In-Reply-To: <20200521091356.2211020-1-lkundrak@v3.sk>
Convert the mrvl,intc binding to DT schema format using json-schema.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
---
Changes since v1:
- Move minItems/maxItems to main reg property definition from the
conditional one
- Drop the condition for marvell,orion-intc
- Add default GPL-2.0-only license tag
- Fill in maintainers from MAINTAINERS file
.../interrupt-controller/mrvl,intc.txt | 64 ---------
.../interrupt-controller/mrvl,intc.yaml | 134 ++++++++++++++++++
2 files changed, 134 insertions(+), 64 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt b/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt
deleted file mode 100644
index a0ed02725a9d..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.txt
+++ /dev/null
@@ -1,64 +0,0 @@
-* Marvell MMP Interrupt controller
-
-Required properties:
-- compatible : Should be
- "mrvl,mmp-intc" on Marvel MMP,
- "mrvl,mmp2-intc" along with "mrvl,mmp2-mux-intc" on MMP2 or
- "marvell,mmp3-intc" with "mrvl,mmp2-mux-intc" on MMP3
-- reg : Address and length of the register set of the interrupt controller.
- If the interrupt controller is intc, address and length means the range
- of the whole interrupt controller. The "marvell,mmp3-intc" controller
- also has a secondary range for the second CPU core. If the interrupt
- controller is mux-intc, address and length means one register. Since
- address of mux-intc is in the range of intc. mux-intc is secondary
- interrupt controller.
-- reg-names : Name of the register set of the interrupt controller. It's
- only required in mux-intc interrupt controller.
-- interrupts : Should be the port interrupt shared by mux interrupts. It's
- only required in mux-intc interrupt controller.
-- interrupt-controller : Identifies the node as an interrupt controller.
-- #interrupt-cells : Specifies the number of cells needed to encode an
- interrupt source.
-- mrvl,intc-nr-irqs : Specifies the number of interrupts in the interrupt
- controller.
-- mrvl,clr-mfp-irq : Specifies the interrupt that needs to clear MFP edge
- detection first.
-
-Example:
- intc: interrupt-controller@d4282000 {
- compatible = "mrvl,mmp2-intc";
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0xd4282000 0x1000>;
- mrvl,intc-nr-irqs = <64>;
- };
-
- intcmux4@d4282150 {
- compatible = "mrvl,mmp2-mux-intc";
- interrupts = <4>;
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x150 0x4>, <0x168 0x4>;
- reg-names = "mux status", "mux mask";
- mrvl,intc-nr-irqs = <2>;
- };
-
-* Marvell Orion Interrupt controller
-
-Required properties
-- compatible : Should be "marvell,orion-intc".
-- #interrupt-cells: Specifies the number of cells needed to encode an
- interrupt source. Supported value is <1>.
-- interrupt-controller : Declare this node to be an interrupt controller.
-- reg : Interrupt mask address. A list of 4 byte ranges, one per controller.
- One entry in the list represents 32 interrupts.
-
-Example:
-
- intc: interrupt-controller {
- compatible = "marvell,orion-intc", "marvell,intc";
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0xfed20204 0x04>,
- <0xfed20214 0x04>;
- };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.yaml
new file mode 100644
index 000000000000..372ccbfae771
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/mrvl,intc.yaml
@@ -0,0 +1,134 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/mrvl,intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell MMP/Orion Interrupt controller bindings
+
+maintainers:
+ - Thomas Gleixner <tglx@linutronix.de>
+ - Jason Cooper <jason@lakedaemon.net>
+ - Marc Zyngier <maz@kernel.org>
+ - Rob Herring <robh+dt@kernel.org>
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ not:
+ contains:
+ const: marvell,orion-intc
+ then:
+ required:
+ - mrvl,intc-nr-irqs
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mrvl,mmp-intc
+ - mrvl,mmp2-intc
+ then:
+ properties:
+ reg:
+ maxItems: 1
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - marvell,mmp3-intc
+ - mrvl,mmp2-mux-intc
+ then:
+ properties:
+ reg:
+ minItems: 2
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mrvl,mmp2-mux-intc
+ then:
+ properties:
+ interrupts:
+ maxItems: 1
+ reg-names:
+ items:
+ - const: 'mux status'
+ - const: 'mux mask'
+ required:
+ - interrupts
+ else:
+ properties:
+ interrupts: false
+
+properties:
+ '#interrupt-cells':
+ const: 1
+
+ compatible:
+ enum:
+ - mrvl,mmp-intc
+ - mrvl,mmp2-intc
+ - marvell,mmp3-intc
+ - marvell,orion-intc
+ - mrvl,mmp2-mux-intc
+
+ reg:
+ minItems: 1
+ maxItems: 2
+
+ reg-names: true
+
+ interrupts: true
+
+ interrupt-controller: true
+
+ mrvl,intc-nr-irqs:
+ description: |
+ Specifies the number of interrupts in the interrupt controller.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ mrvl,clr-mfp-irq:
+ description: |
+ Specifies the interrupt that needs to clear MFP edge detection first.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+required:
+ - '#interrupt-cells'
+ - compatible
+ - reg
+ - interrupt-controller
+
+additionalProperties: false
+
+examples:
+ - |
+ interrupt-controller@d4282000 {
+ compatible = "mrvl,mmp2-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0xd4282000 0x1000>;
+ mrvl,intc-nr-irqs = <64>;
+ };
+
+ interrupt-controller@d4282150 {
+ compatible = "mrvl,mmp2-mux-intc";
+ interrupts = <4>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x150 0x4>, <0x168 0x4>;
+ reg-names = "mux status", "mux mask";
+ mrvl,intc-nr-irqs = <2>;
+ };
+ - |
+ interrupt-controller@fed20204 {
+ compatible = "marvell,orion-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0xfed20204 0x04>,
+ <0xfed20214 0x04>;
+ };
+
+...
--
2.26.2
^ permalink raw reply related
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