* [PATCH v5 10/11] ARM64: dts: mediatek: add ethernet pins for pumpkin boards
From: Bartosz Golaszewski @ 2020-05-22 12:06 UTC (permalink / raw)
To: Rob Herring, David S . Miller, Matthias Brugger, John Crispin,
Sean Wang, Mark Lee, Jakub Kicinski, Arnd Bergmann, Fabien Parent,
Heiner Kallweit, Edwin Peer
Cc: devicetree, linux-kernel, netdev, linux-arm-kernel,
linux-mediatek, Stephane Le Provost, Pedro Tsai, Andrew Perepech,
Bartosz Golaszewski
In-Reply-To: <20200522120700.838-1-brgl@bgdev.pl>
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Setup the pin control for the Ethernet MAC.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
index 97d9b000c37e..4b1d5f69aba6 100644
--- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
+++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
@@ -219,4 +219,19 @@ gpio_mux_int_n_pin {
bias-pull-up;
};
};
+
+ ethernet_pins_default: ethernet {
+ pins_ethernet {
+ pinmux = <MT8516_PIN_0_EINT0__FUNC_EXT_TXD0>,
+ <MT8516_PIN_1_EINT1__FUNC_EXT_TXD1>,
+ <MT8516_PIN_5_EINT5__FUNC_EXT_RXER>,
+ <MT8516_PIN_6_EINT6__FUNC_EXT_RXC>,
+ <MT8516_PIN_7_EINT7__FUNC_EXT_RXDV>,
+ <MT8516_PIN_8_EINT8__FUNC_EXT_RXD0>,
+ <MT8516_PIN_9_EINT9__FUNC_EXT_RXD1>,
+ <MT8516_PIN_12_EINT12__FUNC_EXT_TXEN>,
+ <MT8516_PIN_38_MRG_DI__FUNC_EXT_MDIO>,
+ <MT8516_PIN_39_MRG_DO__FUNC_EXT_MDC>;
+ };
+ };
};
--
2.25.0
^ permalink raw reply related
* [PATCH v5 11/11] ARM64: dts: mediatek: enable ethernet on pumpkin boards
From: Bartosz Golaszewski @ 2020-05-22 12:07 UTC (permalink / raw)
To: Rob Herring, David S . Miller, Matthias Brugger, John Crispin,
Sean Wang, Mark Lee, Jakub Kicinski, Arnd Bergmann, Fabien Parent,
Heiner Kallweit, Edwin Peer
Cc: devicetree, linux-kernel, netdev, linux-arm-kernel,
linux-mediatek, Stephane Le Provost, Pedro Tsai, Andrew Perepech,
Bartosz Golaszewski
In-Reply-To: <20200522120700.838-1-brgl@bgdev.pl>
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Add remaining properties to the ethernet node and enable it.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
.../boot/dts/mediatek/pumpkin-common.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
index 4b1d5f69aba6..dfceffe6950a 100644
--- a/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
+++ b/arch/arm64/boot/dts/mediatek/pumpkin-common.dtsi
@@ -167,6 +167,24 @@ &uart0 {
status = "okay";
};
+ðernet {
+ pinctrl-names = "default";
+ pinctrl-0 = <ðernet_pins_default>;
+ phy-handle = <ð_phy>;
+ phy-mode = "rmii";
+ mac-address = [00 00 00 00 00 00];
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
&usb0 {
status = "okay";
dr_mode = "peripheral";
--
2.25.0
^ permalink raw reply related
* [PATCH v5 05/11] net: ethernet: mediatek: remove unnecessary spaces from Makefile
From: Bartosz Golaszewski @ 2020-05-22 12:06 UTC (permalink / raw)
To: Rob Herring, David S . Miller, Matthias Brugger, John Crispin,
Sean Wang, Mark Lee, Jakub Kicinski, Arnd Bergmann, Fabien Parent,
Heiner Kallweit, Edwin Peer
Cc: devicetree, linux-kernel, netdev, linux-arm-kernel,
linux-mediatek, Stephane Le Provost, Pedro Tsai, Andrew Perepech,
Bartosz Golaszewski
In-Reply-To: <20200522120700.838-1-brgl@bgdev.pl>
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
The Makefile formatting in the kernel tree usually doesn't use tabs,
so remove them before we add a second driver.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
drivers/net/ethernet/mediatek/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/mediatek/Makefile b/drivers/net/ethernet/mediatek/Makefile
index 2d8362f9341b..3362fb7ef859 100644
--- a/drivers/net/ethernet/mediatek/Makefile
+++ b/drivers/net/ethernet/mediatek/Makefile
@@ -3,5 +3,5 @@
# Makefile for the Mediatek SoCs built-in ethernet macs
#
-obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
+obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o
--
2.25.0
^ permalink raw reply related
* [PATCH v5 00/11] mediatek: add support for MediaTek Ethernet MAC
From: Bartosz Golaszewski @ 2020-05-22 12:06 UTC (permalink / raw)
To: Rob Herring, David S . Miller, Matthias Brugger, John Crispin,
Sean Wang, Mark Lee, Jakub Kicinski, Arnd Bergmann, Fabien Parent,
Heiner Kallweit, Edwin Peer
Cc: devicetree, linux-kernel, netdev, linux-arm-kernel,
linux-mediatek, Stephane Le Provost, Pedro Tsai, Andrew Perepech,
Bartosz Golaszewski
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
This series adds support for the STAR Ethernet Controller present on MediaTeK
SoCs from the MT8* family.
First we convert the existing DT bindings for the PERICFG controller to YAML
and add a new compatible string for mt8516 variant of it. Then we add the DT
bindings for the MAC.
Next we do some cleanup of the mediatek ethernet drivers directory.
The largest patch in the series adds the actual new driver.
The rest of the patches add DT fixups for the boards already supported
upstream.
v1 -> v2:
- add a generic helper for retrieving the net_device associated with given
private data
- fix several typos in commit messages
- remove MTK_MAC_VERSION and don't set the driver version
- use NET_IP_ALIGN instead of a magic number (2) but redefine it as it defaults
to 0 on arm64
- don't manually turn the carrier off in mtk_mac_enable()
- process TX cleanup in napi poll callback
- configure pause in the adjust_link callback
- use regmap_read_poll_timeout() instead of handcoding the polling
- use devres_find() to verify that struct net_device is managed by devres in
devm_register_netdev()
- add a patch moving all networking devres helpers into net/devres.c
- tweak the dma barriers: remove where unnecessary and add comments to the
remaining barriers
- don't reset internal counters when enabling the NIC
- set the net_device's mtu size instead of checking the framesize in
ndo_start_xmit() callback
- fix a race condition in waking up the netif queue
- don't emit log messages on OOM errors
- use dma_set_mask_and_coherent()
- use eth_hw_addr_random()
- rework the receive callback so that we reuse the previous skb if unmapping
fails, like we already do if skb allocation fails
- rework hash table operations: add proper timeout handling and clear bits when
appropriate
v2 -> v3:
- drop the patch adding priv_to_netdev() and store the netdev pointer in the
driver private data
- add an additional dma_wmb() after reseting the descriptor in
mtk_mac_ring_pop_tail()
- check the return value of dma_set_mask_and_coherent()
- improve the DT bindings for mtk-eth-mac: make the reg property in the example
use single-cell address and size, extend the description of the PERICFG
phandle and document the mdio sub-node
- add a patch converting the old .txt bindings for PERICFG to yaml
- limit reading the DMA memory by storing the mapped addresses in the driver
private structure
- add a patch documenting the existing networking devres helpers
v3 -> v4:
- drop the devres patches: they will be sent separately
- call netdev_sent_queue() & netdev_completed_queue() where appropriate
- don't redefine NET_IP_ALIGN: define a private constant in the driver
- fix a couple typos
- only disabe/enable the MAC in suspend/resume if netif is running
- drop the count field from the ring structure and instead calculate the number
of used descriptors from the tail and head indicies
- rework the locking used to protect the ring structures from concurrent
access: use cheaper spin_lock_bh() and completely disable the internal
spinlock used by regmap
- rework the interrupt handling to make it more fine-grained: onle re-enable
TX and RX interrupts while they're needed, process the stats updates in a
workqueue, not in napi context
- shrink the code responsible for unmapping and freeing skb memory
- rework the barriers as advised by Arnd
v4 -> v5:
- rename the driver to make it less confusing with the existing mtk_eth_soc
ethernet driver
- unregister the mdiobus at device's detachment
- open-code spin lock calls to avoid calling the _bh variants where unnecessary
- limit read-modify-write operations where possible when accessing descriptor
memory
- use READ_ONCE/WRITE_ONCE when modifying the status and data_ptr descriptor
fields
Bartosz Golaszewski (11):
dt-bindings: convert the binding document for mediatek PERICFG to yaml
dt-bindings: add new compatible to mediatek,pericfg
dt-bindings: net: add a binding document for MediaTek STAR Ethernet
MAC
net: ethernet: mediatek: rename Kconfig prompt
net: ethernet: mediatek: remove unnecessary spaces from Makefile
net: ethernet: mtk-star-emac: new driver
ARM64: dts: mediatek: add pericfg syscon to mt8516.dtsi
ARM64: dts: mediatek: add the ethernet node to mt8516.dtsi
ARM64: dts: mediatek: add an alias for ethernet0 for pumpkin boards
ARM64: dts: mediatek: add ethernet pins for pumpkin boards
ARM64: dts: mediatek: enable ethernet on pumpkin boards
.../arm/mediatek/mediatek,pericfg.txt | 36 -
.../arm/mediatek/mediatek,pericfg.yaml | 64 +
.../bindings/net/mediatek,eth-mac.yaml | 89 +
arch/arm64/boot/dts/mediatek/mt8516.dtsi | 17 +
.../boot/dts/mediatek/pumpkin-common.dtsi | 34 +
drivers/net/ethernet/mediatek/Kconfig | 9 +-
drivers/net/ethernet/mediatek/Makefile | 3 +-
drivers/net/ethernet/mediatek/mtk_star_emac.c | 1678 +++++++++++++++++
8 files changed, 1892 insertions(+), 38 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml
create mode 100644 Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml
create mode 100644 drivers/net/ethernet/mediatek/mtk_star_emac.c
--
2.25.0
^ permalink raw reply
* Re: [PATCH v3 01/16] spi: dw: Add Tx/Rx finish wait methods to the MID DMA
From: Feng Tang @ 2020-05-22 12:03 UTC (permalink / raw)
To: Serge Semin
Cc: Serge Semin, Mark Brown, Grant Likely, Vinod Koul, Alan Cox,
Linus Walleij, Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Thomas Bogendoerfer, Paul Burton, Ralf Baechle, Arnd Bergmann,
Andy Shevchenko, Rob Herring, linux-mips, devicetree,
Jarkko Nikula, Thomas Gleixner, Wan Ahmad Zainie, Linus Walleij,
Clement Leger, linux-spi, linux-kernel
In-Reply-To: <20200522113235.miz6m7u7gs7lsq6n@mobilestation>
On Fri, May 22, 2020 at 02:32:35PM +0300, Serge Semin wrote:
> On Fri, May 22, 2020 at 03:58:44PM +0800, Feng Tang wrote:
> > Hi Serge,
> >
> > On Thu, May 21, 2020 at 06:33:17PM +0300, Serge Semin wrote:
> > > > > > > + dw_spi_dma_wait_rx_done(dws);
> > > > > >
> > > > > > I can understand the problem about TX, but I don't see how RX
> > > > > > will get hurt, can you elaborate more? thanks
> > > > > >
> > > > > > - Feng
> > > > >
> > > > > Your question is correct. You are right with your hypothesis. Ideally upon the
> > > > > dw_spi_dma_rx_done() execution Rx FIFO must be already empty. That's why the
> > > > > commit log signifies the error being mostly related with Tx FIFO. But
> > > > > practically there are many reasons why Rx FIFO might be left with data:
> > > > > DMA engine failures, incorrect DMA configuration (if DW SPI or DW DMA driver
> > > > > messed something up), controller hanging up, and so on. It's better to catch
> > > > > an error at this stage while propagating it up to the SPI device drivers.
> > > > > Especially seeing the wait-check implementation doesn't gives us much of the
> > > > > execution overhead in normal conditions. So by calling dw_spi_dma_wait_rx_done()
> > > > > we make sure that all the data has been fetched and we may freely get the
> > > > > buffers back to the client driver.
> > > >
> > > > I see your point about checking RX. But I still don't think checking
> > > > RX FIFO level is the right way to detect error. Some data left in
> > > > RX FIFO doesn't always mean a error, say for some case if there is
> > > > 20 words in RX FIFO, and the driver starts a DMA request for 16
> > > > words, then after a sucessful DMA transaction, there are 4 words
> > > > left without any error.
> > >
> > > Neither Tx nor Rx FIFO should be left with any data after transaction is
> > > finished. If they are then something has been wrong.
> > >
> > > See, every SPI transfer starts with FIFO clearance since we disable/enable the
> > > SPI controller by means of the SSIENR (spi_enable_chip(dws, 0) and
> > > spi_enable_chip(dws, 1) called in the dw_spi_transfer_one() callback). Here is the
> > > SSIENR register description: "It enables and disables all SPI Controller operations.
> > > When disabled, all serial transfers are halted immediately. Transmit and receive
> > > FIFO buffers are cleared when the device is disabled. It is impossible to program
> > > some of the SPI Controller control registers when enabled"
> > >
> > > No mater whether we start DMA request or perform the normal IRQ-based PIO, we
> > > request as much data as we need and neither Tx nor Rx FIFO are supposed to
> > > be left with any data after the request is finished. If data is left, then
> > > either we didn't push all of the necessary data to the SPI bus, or we didn't
> > > pull all the data from the FIFO, and this could have happened only due to some
> > > component mulfunction (drivers, DMA engine, SPI device). In any case the SPI
> > > device driver should be notified about the problem.
> >
> > Data left in TX FIFO and Data left in RX FIFO are 2 different stories. The
> > former in dma case means the dma hw/driver has done its job, and spi hw/driver
> > hasn't done its job of pushing out the data to spi slave devices,
>
> Agreed.
>
> > while the
> > latter means the spi hw/driver has done its job, while the dma hw/driver hasn't.
>
> In this particular case agreed, that the data left in the Rx FIFO means DMA
> hw/driver hasn't done its work right. Though SPI hw could be also a reason of
> the data left in FIFO (though this only a theoretical consideration).
Right, that's why I was initially very curious about this RX FIFO thing,
and if possible, please give some details in commit log about the data
left in TX FIFO problem, which will help future developers when they
met simliar bugs.
And I'm fine with adding the rx check, no matter the problem is in
dma side or spi side.
> >
> > And the code is called inside the dma rx channel callback, which means the
> > dma driver is saying "hey, I've done my job", but apparently it hasn't if
> > there is data left.
>
> Right, either it hasn't, or the DMA engine claimed it has, but still is doing
> something (asynchronously or something, depending on the hardware implementation),
> or it think it has, but in fact it hasn't due to whatever problem happened
> (software/hardware/etc.). In anyway we have to at least check whether it's
> really done with fetching data and to be on a safe side give it some time to
> make sure that the Rx FIFO isn't going to be emptied. Whatever problem it is
> having a non empty Rx FIFO at the stage of calling spi_finalize_current_transfer()
> means a certain error.
>
> >
> > As for the wait time
> >
> > + nents = dw_readl(dws, DW_SPI_RXFLR);
> > + ns = (NSEC_PER_SEC / spi_get_clk(dws)) * nents * dws->n_bytes *
> > + BITS_PER_BYTE;
> >
> > Using this formula for checking TX makes sense, but it doesn't for RX.
> > Because the time of pushing data in TX FIFO to spi device depends on
> > the clk, but the time of transferring RX FIFO to memory is up to
> > the DMA controller and peripheral bus.
>
> On this I agree with you. That formulae doesn't describe exactly the time left
> before the Rx FIFO gets empty. But at least it provides an upper limit on the
> time needed for the peripheral bus to fetch the data from FIFO. If for some
> reason the internal APB bus is slower than the SPI bus, then the hardware
> engineers screwed, since the CPU/DMA won't keep up with pulling data from Rx
> FIFO on time so the FIFO may get overflown. Though in this case CPU/DMA won't
> be able to push data to the Tx FIFO fast enough to cause the Rx FIFO overflown,
> so the problem might be unnoticeable until we enable the EEPROM-read or Rx-only
> modes of the DW APB SSI controller. Anyway I am pretty much sure all the systems
> have the internal bus much faster than the external SPI bus.
>
> Getting back to the formulae. I was thinking of how to make it better and here
> is what we can do. We can't predict neither the DMA controller performance,
> nor the performance of its driver. In this case we have no choice but to add
> some assumption to clarify the task. Let's assume that the reason why Rx FIFO is
> non-empty is that even though we are at the DMA completion callback, but the
> DMA controller is still fetching data in background (any other reason might be
> related with a bug, so we'll detect it here anyway). In this case we need to
> give it a time to finish its work. As far as I can see the DW_apb_ssi interface
> doesn't use PREADY APB signal, which means the IO access cycle will take 4
> reference clock periods for each read and write accesses. Thus taking all of
> these into account we can create the next formulae to measure the time needed to
> read all the data from the Rx FIFO:
>
> - ns = (NSEC_PER_SEC / spi_get_clk(dws)) * nents * dws->n_bytes *
> - BITS_PER_BYTE;
> + ns = (NSEC_PER_SEC / dws->max_freq) * nents * 4;
>
> By doing several busy-wait loop iteration we'll cover the DMA controller and
> it's driver possible latency.
>
> Feng, does it now makes sense for you now? If so, I'll replace the delay
> calculation formulae in the patch.
Frankly I don't have a good idea, if it really happens which means
something is abnormal, explicitly waiting for some micro-seconds may
also be acceptable?
> >
> > Also for the
> >
> > + while (dw_spi_dma_rx_busy(dws) && retry--)
> > + ndelay(ns);
> > +
> >
> > the rx busy bit is cleared after this rx/tx checking, and it should
> > be always true at this point. Am I mis-reading the code?
>
> Sorry I don't get your logic here. I am not checking the Rx busy bit here,
> but the Rx FIFO non-empty bit. Also SR register bits aren't cleared on read,
> so the status bits are left pending until the reason is cleared. In our case
> until Rx FIFO gets empty, which will happen eventually either at the point of
> all data finally being extracted from it or when the controller is disabled
> by means of the SSIENR register.
I did misread the code, I thought it is checking the busy bits, sorry
for that. Though the dw_spi_dma_rx_busy() name is a little confusing,
as checking the emptiness of RX FIFO is not dma bound.
Thanks,
Feng
^ permalink raw reply
* Re: [PATCH V4 5/5] iio: adc: Clean up ADC code common to PMIC5 and PMIC7
From: Jishnu Prakash @ 2020-05-22 11:59 UTC (permalink / raw)
To: Andy Shevchenko
Cc: agross, Bjorn Andersson, devicetree, Linux Kernel Mailing List,
Matthias Kaehlcke, Linus Walleij, Jonathan Cameron, Amit Kucheria,
smohanad, kgunda, aghayal, Jonathan Cameron, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, linux-arm-msm,
linux-iio, linux-arm-msm-owner
In-Reply-To: <CAHp75Vf-bFfrZ7uCOnXuzT+p+itkcmkE61=ezZzN8yDFQHABdw@mail.gmail.com>
Hi Andy,
On 5/13/2020 3:21 PM, Andy Shevchenko wrote:
> On Wed, May 13, 2020 at 12:24 PM Jishnu Prakash <jprakash@codeaurora.org> wrote:
>> This commit includes the following changes:
>> Add a common function used for read_raw callback for
>> both PMIC5 and PMIC7 ADCs.
>> Add exit function for ADC.
>> Add info_property under adc_data to more efficiently
>> distinguish PMIC5 and PMIC7 ADCs.
> Something happened to the editor settings. We have lines up to 72
> (recommended) characters.
In this case, I just meant to put each change on a different line. I'll
fix it in the next post.
>
> ...
>
>> @@ -512,6 +518,7 @@ static int adc5_read_raw(struct iio_dev *indio_dev,
>> &adc5_prescale_ratios[prop->prescale],
>> adc->data,
>> adc_code_volt, val);
>> +
>> if (ret)
>> return ret;
>>
> Unrelated.
I'll remove it in the next post.
>
^ permalink raw reply
* Re: [PATCH V4 4/5] iio: adc: Update error checks and debug prints
From: Jishnu Prakash @ 2020-05-22 11:58 UTC (permalink / raw)
To: Andy Shevchenko
Cc: agross, Bjorn Andersson, devicetree, Linux Kernel Mailing List,
Matthias Kaehlcke, Linus Walleij, Jonathan Cameron, Amit Kucheria,
smohanad, kgunda, aghayal, Jonathan Cameron, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, linux-arm-msm,
linux-iio, linux-arm-msm-owner
In-Reply-To: <CAHp75Vex+hm2pVat_VVH5gAqPDbm-VQMes56wC=RUcQeM=z7vA@mail.gmail.com>
Hi Andy,
On 5/13/2020 3:19 PM, Andy Shevchenko wrote:
> On Wed, May 13, 2020 at 12:23 PM Jishnu Prakash <jprakash@codeaurora.org> wrote:
>> Change pr_err/pr_debug statements to dev_err/dev_dbg for
>> increased clarity. Also clean up some return value checks.
> 'Also' on the commit message == 'split this to two'.
I'll do the ret value changes in the third patch in my next post,
according to your comment there.
> But here is a ping pong style of patches (you introduce a problem in
> one patch and fix it in the following).
I'll try to avoid this in the next post
>
^ permalink raw reply
* Re: [PATCH V4 3/5] iio: adc: Add support for PMIC7 ADC
From: Jishnu Prakash @ 2020-05-22 11:58 UTC (permalink / raw)
To: Andy Shevchenko
Cc: agross, Bjorn Andersson, devicetree, Linux Kernel Mailing List,
Matthias Kaehlcke, Linus Walleij, Jonathan Cameron, Amit Kucheria,
smohanad, kgunda, aghayal, Jonathan Cameron, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, linux-arm-msm,
linux-iio, linux-arm-msm-owner
In-Reply-To: <CAHp75VedM+=+m8WF=zPpUcizgCGareYuBzUfjKwesozVSY_gKg@mail.gmail.com>
Hi Andy,
On 5/13/2020 3:18 PM, Andy Shevchenko wrote:
> On Wed, May 13, 2020 at 12:23 PM Jishnu Prakash <jprakash@codeaurora.org> wrote:
>> The ADC architecture on PMIC7 is changed as compared to PMIC5. The
>> major change from PMIC5 is that all SW communication to ADC goes through
>> PMK8350, which communicates with other PMICs through PBS when the ADC
>> on PMK8350 works in master mode. The SID register is used to identify the
>> PMICs with which the PBS needs to communicate. Add support for the same.
>> +#define ADC7_CONV_TIMEOUT msecs_to_jiffies(10)
> ...
>
>> + ret = adc5_read(adc, ADC5_USR_DIG_PARAM, buf, sizeof(buf));
>> + if (ret < 0)
> Is ' < 0' part necessary?
> Ditto for same cases in other places in the code.
I'll fix this at all required locations in this patch in the next post.
>
>> + return ret;
> ...
>
>> + switch (mask) {
>> + case IIO_CHAN_INFO_PROCESSED:
>> + ret = adc7_do_conversion(adc, prop, chan,
>> + &adc_code_volt, &adc_code_cur);
>> + if (ret)
>> + return ret;
>> +
>> + ret = qcom_adc5_hw_scale(prop->scale_fn_type,
>> + &adc5_prescale_ratios[prop->prescale],
>> + adc->data,
>> + adc_code_volt, val);
>> +
>> + if (ret)
>> + return ret;
>> +
>> + return IIO_VAL_INT;
>> + default:
>> + return -EINVAL;
>> + }
>> +
>> + return 0;
> Dead code?
Right, I'll remove it in the next post.
>
> ...
>
>> +static int qcom_vadc7_scale_hw_calib_die_temp(
>> + const struct vadc_prescale_ratio *prescale,
>> + const struct adc5_data *data,
>> + u16 adc_code, int *result_mdec)
>> +{
>> +
>> + int voltage, vtemp0, temp, i = ARRAY_SIZE(adcmap7_die_temp) - 1;
> How assignment to i is useful?
I'm using it in adcmap7_die_temp[i] below, to keep it within the
character limit per line. I think it's more readable that way.
>
>> + voltage = qcom_vadc_scale_code_voltage_factor(adc_code,
>> + prescale, data, 1);
>> +
>> + if (adcmap7_die_temp[0].x > voltage) {
>> + *result_mdec = DIE_TEMP_ADC7_SCALE_1;
>> + return 0;
>> + } else if (adcmap7_die_temp[i].x <= voltage) {
> Redundant 'else'.
The expression is different, it's adcmap7_die_temp[i] here, not
adcmap7_die_temp[0].
>
>> + *result_mdec = DIE_TEMP_ADC7_MAX;
>> + return 0;
>> + }
>> +
>> + for (i = 0; i < ARRAY_SIZE(adcmap7_die_temp); i++)
>> + if (adcmap7_die_temp[i].x > voltage)
>> + break;
>> +
>> + vtemp0 = adcmap7_die_temp[i - 1].x;
>> + voltage = voltage - vtemp0;
>> + temp = div64_s64(voltage * DIE_TEMP_ADC7_SCALE_FACTOR,
>> + adcmap7_die_temp[i - 1].y);
>> + temp += DIE_TEMP_ADC7_SCALE_1 + (DIE_TEMP_ADC7_SCALE_2 * (i - 1));
>> + *result_mdec = temp;
>> +
>> + return 0;
>> +}
> ...
>
>> +#define RATIO_MAX_ADC7 0x4000
> Hmm... Why the last is in hex? Is it related to amount of bits in the
> hardware? Then probably better to use BIT().
It is the upper limit reading for a ratiometric calibration measurement,
which is reported as a 14 bit reading. I'll change this in the next post.
>
^ permalink raw reply
* Re: [PATCH V2] pwm: tegra: dynamic clk freq configuration by PWM driver
From: Jon Hunter @ 2020-05-22 11:50 UTC (permalink / raw)
To: Sandipan Patra, Thierry Reding, robh+dt@kernel.org,
u.kleine-koenig@pengutronix.de
Cc: Bibek Basu, Laxman Dewangan, linux-pwm@vger.kernel.org,
devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <BYAPR12MB3014B051AD088B42001A8132ADB40@BYAPR12MB3014.namprd12.prod.outlook.com>
On 22/05/2020 12:01, Sandipan Patra wrote:
> Thanks Jonathan,
> Please help reviewing further with my replies inline.
>
>
> Thanks & Regards,
> Sandipan
>
>> -----Original Message-----
>> From: Jonathan Hunter <jonathanh@nvidia.com>
>> Sent: Friday, May 22, 2020 3:54 PM
>> To: Sandipan Patra <spatra@nvidia.com>; Thierry Reding
>> <treding@nvidia.com>; robh+dt@kernel.org; u.kleine-koenig@pengutronix.de
>> Cc: Bibek Basu <bbasu@nvidia.com>; Laxman Dewangan
>> <ldewangan@nvidia.com>; linux-pwm@vger.kernel.org;
>> devicetree@vger.kernel.org; linux-tegra@vger.kernel.org; linux-
>> kernel@vger.kernel.org
>> Subject: Re: [PATCH V2] pwm: tegra: dynamic clk freq configuration by PWM
>> driver
>>
>>
>> On 20/04/2020 16:54, Sandipan Patra wrote:
>>> Added support for dynamic clock freq configuration in pwm kernel driver.
>>> Earlier the pwm driver used to cache boot time clock rate by pwm clock
>>> parent during probe. Hence dynamically changing pwm frequency was not
>>> possible for all the possible ranges. With this change, dynamic
>>> calculation is enabled and it is able to set the requested period from
>>> sysfs knob provided the value is supported by clock source.
>>>
>>> Changes mainly have 2 parts:
>>> - T186 and later chips [1]
>>> - T210 and prior chips [2]
>>>
>>> For [1] - Changes implemented to set pwm period dynamically and
>>> also checks added to allow only if requested period(ns) is
>>> below or equals to higher range.
>>>
>>> For [2] - Only checks if the requested period(ns) is below or equals
>>> to higher range defined by max clock limit. The limitation
>>> in T210 or prior chips are due to the reason of having only
>>> one pwm-controller supporting multiple channels. But later
>>> chips have multiple pwm controller instances each having
>>> single channel support.
>>>
>>> Signed-off-by: Sandipan Patra <spatra@nvidia.com>
>>> ---
>>> V2:
>>> 1. Min period_ns calculation is moved to probe.
>>> 2. Added descriptioins for PWM register bits and regarding behaviour
>>> of the controller when new configuration is applied or pwm is disabled.
>>> 3. Setting period with possible value when supplied period is below limit.
>>> 4. Corrected the earlier code comment:
>>> plus 1 instead of minus 1 during pwm calculation
>>>
>>> drivers/pwm/pwm-tegra.c | 110
>>> +++++++++++++++++++++++++++++++++++++++++-------
>>> 1 file changed, 94 insertions(+), 16 deletions(-)
>>>
>>> diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index
>>> d26ed8f..7a36325 100644
>>> --- a/drivers/pwm/pwm-tegra.c
>>> +++ b/drivers/pwm/pwm-tegra.c
>>> @@ -4,8 +4,39 @@
>>> *
>>> * Tegra pulse-width-modulation controller driver
>>> *
>>> - * Copyright (c) 2010, NVIDIA Corporation.
>>> - * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer
>>> <s.hauer@pengutronix.de>
>>> + * Copyright (c) 2010-2020, NVIDIA Corporation.
>>> + *
>>> + * Overview of Tegra Pulse Width Modulator Register:
>>> + * 1. 13-bit: Frequency division (SCALE)
>>> + * 2. 8-bit : Puls division (DUTY)
>>> + * 3. 1-bit : Enable bit
>>> + *
>>> + * The PWM clock frequency is divided by 256 before subdividing it
>>> + based
>>> + * on the programmable frequency division value to generate the
>>> + required
>>> + * frequency for PWM output. The maximum output frequency that can be
>>> + * achieved is (max rate of source clock) / 256.
>>> + * i.e. if source clock rate is 408 MHz, maximum output frequency cab be:
>>> + * 408 MHz/256 = 1.6 MHz.
>>> + * This 1.6 MHz frequency can further be divided using SCALE value in PWM.
>>> + *
>>> + * PWM pulse width: 8 bits are usable [23:16] for varying pulse width.
>>> + * To achieve 100% duty cycle, program Bit [24] of this register to
>>> + * 1’b1. In which case the other bits [23:16] are set to don't care.
>>> + *
>>> + * Limitations and known facts:
>>> + * - When PWM is disabled, the output is driven to 0.
>>> + * - It does not allow the current PWM period to complete and
>>> + * stops abruptly.
>>> + *
>>> + * - If the register is reconfigured while pwm is running,
>>> + * It does not let the currently running period to complete.
>>> + *
>>> + * - Pulse width of the pwm can never be out of bound.
>>> + * It's taken care at HW and SW
>>> + * - If the user input duty is below limit, then driver sets it to
>>> + * minimum possible value.
>>> + * - If anything else goes wrong for setting duty or period,
>>> + * -EINVAL is returned.
>>> */
>>>
>>> #include <linux/clk.h>
>>> @@ -41,6 +72,7 @@ struct tegra_pwm_chip {
>>> struct reset_control*rst;
>>>
>>> unsigned long clk_rate;
>>> + unsigned long min_period_ns;
>>>
>>> void __iomem *regs;
>>>
>>> @@ -67,8 +99,9 @@ static int tegra_pwm_config(struct pwm_chip *chip,
>> struct pwm_device *pwm,
>>> int duty_ns, int period_ns)
>>> {
>>> struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
>>> - unsigned long long c = duty_ns, hz;
>>> - unsigned long rate;
>>> + unsigned long long p_width = duty_ns, period_hz;
>>> + unsigned long rate, required_clk_rate;
>>> + unsigned long pfm; /* Frequency divider */
>>
>> If it is not necessary to change the variable names, then I would prefer we keep
>> them as is as then changes would be less.
>
> The earlier name was misleading so thought to use a specific name for
> which it can be helpful to follow up with the TRM. Since its recommended
> to retain the variable names, I will change this in next patch.
I was just wondering if was necessary to change 'c' to 'p_width'. This
could reduce the diff a bit.
>>
>>> u32 val = 0;
>>> int err;
>>>
>>> @@ -77,37 +110,77 @@ static int tegra_pwm_config(struct pwm_chip *chip,
>> struct pwm_device *pwm,
>>> * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
>>> * nearest integer during division.
>>> */
>>> - c *= (1 << PWM_DUTY_WIDTH);
>>> - c = DIV_ROUND_CLOSEST_ULL(c, period_ns);
>>> + p_width *= (1 << PWM_DUTY_WIDTH);
>>> + p_width = DIV_ROUND_CLOSEST_ULL(p_width, period_ns);
>>>
>>> - val = (u32)c << PWM_DUTY_SHIFT;
>>> + val = (u32)p_width << PWM_DUTY_SHIFT;
>>> +
>>> + /*
>>> + * Period in nano second has to be <= highest allowed period
>>> + * based on max clock rate of the pwm controller.
>>> + *
>>> + * higher limit = max clock limit >> PWM_DUTY_WIDTH
>>> + * lower limit = min clock limit >> PWM_DUTY_WIDTH >>
>> PWM_SCALE_WIDTH
>>> + */
>>> + if (period_ns < pc->min_period_ns) {
>>> + period_ns = pc->min_period_ns;
>>> + pr_warn("Period is adjusted to allowed value (%d ns)\n",
>>> + period_ns);
>>
>> I see that other drivers (pwm-img.c) consider this to be an error and return an
>> error. I wonder if adjusting the period makes sense here?
>>
>> I wonder if the handling of the min_period, should be a separate change?
>
> I think I misunderstood one of the discussions in initial patch and added this change
> to apply the minimum possible value. Understood and will revert this change
> with returning error in such case.
>
>>
>>> + }
>>>
>>> /*
>>> * Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
>>> * cycles at the PWM clock rate will take period_ns nanoseconds.
>>> */
>>> - rate = pc->clk_rate >> PWM_DUTY_WIDTH;
>>> + if (pc->soc->num_channels == 1) {
>>
>> Are you using num_channels to determine if Tegra uses the BPMP? If so then the
>> above is not really correct, because num_channels is not really related to what is
>> being done here. So maybe you need a new SoC attribute in the soc data.
>
> Here, it tries to find if pwm controller uses multiple channels (like in Tegra210 or older)
> or single channel for every pwm instance (i.e. T186, T194). If found multiple channels on
> a single controller then it is not correct to configure separate clock rates to each of the
> channels. So to distinguish the controller and channel type, num_channels is referred.
OK, then that makes sense. Maybe add this detail to the comment about
why num_channels is used.
>>
>>> + /*
>>> + * Rate is multiplied with 2^PWM_DUTY_WIDTH so that it
>> matches
>>> + * with the hieghest applicable rate that the controller can
>>
>> s/hieghest/highest/
>
> Got it.
>
>>
>>> + * provide. Any further lower value can be derived by setting
>>> + * PFM bits[0:12].
>>> + * Higher mark is taken since BPMP has round-up mechanism
>>> + * implemented.
>>> + */
>>> + required_clk_rate =
>>> + (NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH;
>>> +
>>
>> Should be we checking the rate against the max rate supported?
>
> If the request rate is beyond max supported rate, then the clk_set_rate will be failing
> and can get caught with error check followed by. Otherwise it will fail through fitting in
> the register's frequency divider filed. So I think it is not required to check against max rate.
> Please advise if I am not able to follow with what you are suggesting.
I think that it would be better to update the cached value so that it is
not incorrectly used else where by any future change. Furthermore, this
simplifies matters a bit because you can do the following for all
devices, but only update the clk_rate for those you wish to ...
rate = pc->clk_rate >> PWM_DUTY_WIDTH;
>>
>>> + err = clk_set_rate(pc->clk, required_clk_rate);
>>> + if (err < 0)
>>> + return -EINVAL;
>>> +
>>> + rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH;
>>
>> Do we need to update the pwm->clk_rate here?
>
> This return rate is basically from the factor that requested clk_set_rate and the actual rate set
> mostly will have a little deviation based on the clock divider and other factors while setting
> a new rate. So capturing the actual rate for further calculation and conversion to Hz.
> Whenever it is required to use pwm->clk_rate we are no longer depending upon the cached value
> for num_channels == 1. So in my opinion it does not need to be cached. However it is kept
> stored for the SoCs having num_channels > 1.
> Please suggest if I am missing any case where we need to keep the value stored.
OK sounds fine.
>>
>>> + } else {
>>> + /*
>>> + * This is the case for SoCs who support multiple channels:
>>> + *
>>> + * clk_set_rate() can not be called again in config because
>>> + * T210 or any prior chip supports one pwm-controller and
>>> + * multiple channels. Hence in this case cached clock rate
>>> + * will be considered which was stored during probe.
>>> + */
>>> + rate = pc->clk_rate >> PWM_DUTY_WIDTH;
>>> + }
>>>
>>> /* Consider precision in PWM_SCALE_WIDTH rate calculation */
>>> - hz = DIV_ROUND_CLOSEST_ULL(100ULL * NSEC_PER_SEC, period_ns);
>>> - rate = DIV_ROUND_CLOSEST_ULL(100ULL * rate, hz);
>>> + period_hz = DIV_ROUND_CLOSEST_ULL(100ULL * NSEC_PER_SEC,
>> period_ns);
>>> + pfm = DIV_ROUND_CLOSEST_ULL(100ULL * rate, period_hz);
>>>
>>> /*
>>> * Since the actual PWM divider is the register's frequency divider
>>> - * field minus 1, we need to decrement to get the correct value to
>>> + * field plus 1, we need to decrement to get the correct value to
>>> * write to the register.
>>> */
>>> - if (rate > 0)
>>> - rate--;
>>> + if (pfm > 0)
>>> + pfm--;
>>>
>>> /*
>>> - * Make sure that the rate will fit in the register's frequency
>>> + * Make sure that pfm will fit in the register's frequency
>>> * divider field.
>>> */
>>> - if (rate >> PWM_SCALE_WIDTH)
>>> + if (pfm >> PWM_SCALE_WIDTH)
>>> return -EINVAL;
>>>
>>> - val |= rate << PWM_SCALE_SHIFT;
>>> + val |= pfm << PWM_SCALE_SHIFT;
>>>
>>> /*
>>> * If the PWM channel is disabled, make sure to turn on the clock @@
>>> -205,6 +278,10 @@ static int tegra_pwm_probe(struct platform_device
>> *pdev)
>>> */
>>> pwm->clk_rate = clk_get_rate(pwm->clk);
>>>
>>> + /* Set minimum limit of PWM period for the IP */
>>> + pwm->min_period_ns =
>>> + (NSEC_PER_SEC / (pwm->soc->max_frequency >>
>> PWM_DUTY_WIDTH)) +
>>> +1;
>>> +
>>> pwm->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
>>> if (IS_ERR(pwm->rst)) {
>>> ret = PTR_ERR(pwm->rst);
>>> @@ -313,4 +390,5 @@ module_platform_driver(tegra_pwm_driver);
>>>
>>> MODULE_LICENSE("GPL");
>>> MODULE_AUTHOR("NVIDIA Corporation");
>>> +MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>");
>>> MODULE_ALIAS("platform:tegra-pwm");
>>>
>>
>> --
>> nvpublic
--
nvpublic
^ permalink raw reply
* [PATCH v3 2/2] dt-bindings: thermal: tsens: Add cold interrupt support in yaml
From: Manaf Meethalavalappu Pallikunhi @ 2020-05-22 11:46 UTC (permalink / raw)
To: Amit Kucheria, Andy Gross, Bjorn Andersson, Zhang Rui,
Daniel Lezcano, Rob Herring
Cc: linux-pm, linux-arm-msm, devicetree, linux-kernel,
Manaf Meethalavalappu Pallikunhi
In-Reply-To: <20200522114626.28834-1-manafm@codeaurora.org>
Add cold interrupt support for tsens in yaml.
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
---
.../bindings/thermal/qcom-tsens.yaml | 42 +++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
index 2ddd39d96766..3592322fe172 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
@@ -52,12 +52,14 @@ properties:
items:
- description: Combined interrupt if upper or lower threshold crossed
- description: Interrupt if critical threshold crossed
+ - description: Interrupt if cold threshold is crossed
interrupt-names:
minItems: 1
items:
- const: uplow
- const: critical
+ - const: cold
nvmem-cells:
minItems: 1
@@ -109,8 +111,10 @@ allOf:
properties:
interrupts:
minItems: 2
+ maxItems: 3
interrupt-names:
minItems: 2
+ maxItems: 3
required:
- compatible
@@ -174,4 +178,42 @@ examples:
#qcom,sensors = <13>;
#thermal-sensor-cells = <1>;
};
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ // Example 4 (for any platform containing v2.6+ of the TSENS IP)
+ // (with thermal-zone):
+ tsens4: thermal-sensor@c265000 {
+ compatible = "qcom,sc7180-tsens", "qcom,tsens-v2";
+ reg = <0xc265000 0x1ff>,
+ <0xc223000 0x1ff>;
+
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 501 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "uplow", "critical", "cold";
+
+ #qcom,sensors = <15>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cold_thermal: cold-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens4 128>;
+
+ trips {
+ cold-trip {
+ temperature = <1>;
+ hysteresis = <1>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ };
+ };
+ };
...
--
2.26.2
^ permalink raw reply related
* [PATCH v3 1/2] drivers: thermal: tsens: Add cold interrupt support
From: Manaf Meethalavalappu Pallikunhi @ 2020-05-22 11:46 UTC (permalink / raw)
To: Amit Kucheria, Andy Gross, Bjorn Andersson, Zhang Rui,
Daniel Lezcano, Rob Herring
Cc: linux-pm, linux-arm-msm, devicetree, linux-kernel,
Manaf Meethalavalappu Pallikunhi
In-Reply-To: <20200522114626.28834-1-manafm@codeaurora.org>
TSENS IP v2.6+ adds cold interrupt support. It triggers set
interrupt when aggregated minimum temperature of all TSENS falls
below cold preset threshold, 5 degree Celsius and triggers
reset interrupt when aggregated minimum temperature of all TSENS
crosses above reset threshold, 10 degree Celsius. These threshold
values could change in boot firmware code. Add support for this
interrupt in the driver.
It adds another virtual sensor to the of-thermal along with all
individual TSENS. This cold sensor only gives cold state value of
1 or 0 for successful temperature read. A state value of 1 indicates
minimum one TSENS is in cold temperature condition and state value
of 0 indicates all TSENS are out of cold temperature condition.
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
---
drivers/thermal/qcom/tsens-v2.c | 5 ++
drivers/thermal/qcom/tsens.c | 112 +++++++++++++++++++++++++++++++-
drivers/thermal/qcom/tsens.h | 11 ++++
3 files changed, 127 insertions(+), 1 deletion(-)
diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c
index b293ed32174b..1692e636d3bd 100644
--- a/drivers/thermal/qcom/tsens-v2.c
+++ b/drivers/thermal/qcom/tsens-v2.c
@@ -23,6 +23,7 @@
#define TM_Sn_UPPER_LOWER_THRESHOLD_OFF 0x0020
#define TM_Sn_CRITICAL_THRESHOLD_OFF 0x0060
#define TM_Sn_STATUS_OFF 0x00a0
+#define TM_COLD_INT_STATUS_OFF 0x00e0
#define TM_TRDY_OFF 0x00e4
#define TM_WDOG_LOG_OFF 0x013c
@@ -86,6 +87,9 @@ static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
REG_FIELD_FOR_EACH_SENSOR16(CRITICAL_STATUS, TM_Sn_STATUS_OFF, 19, 19),
REG_FIELD_FOR_EACH_SENSOR16(MAX_STATUS, TM_Sn_STATUS_OFF, 20, 20),
+ /* COLD INTERRUPT STATUS */
+ [COLD_STATUS] = REG_FIELD(TM_COLD_INT_STATUS_OFF, 0, 0),
+
/* TRDY: 1=ready, 0=in progress */
[TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0),
};
@@ -93,6 +97,7 @@ static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
static const struct tsens_ops ops_generic_v2 = {
.init = init_common,
.get_temp = get_temp_tsens_valid,
+ .get_cold_status = get_cold_int_status,
};
struct tsens_plat_data data_tsens_v2 = {
diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c
index 8d3e94d2a9ed..ee93e9d07678 100644
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -205,7 +205,8 @@ static void tsens_set_interrupt_v1(struct tsens_priv *priv, u32 hw_id,
index = LOW_INT_CLEAR_0 + hw_id;
break;
case CRITICAL:
- /* No critical interrupts before v2 */
+ case COLD:
+ /* No critical and cold interrupts before v2 */
return;
}
regmap_field_write(priv->rf[index], enable ? 0 : 1);
@@ -236,6 +237,9 @@ static void tsens_set_interrupt_v2(struct tsens_priv *priv, u32 hw_id,
index_mask = CRIT_INT_MASK_0 + hw_id;
index_clear = CRIT_INT_CLEAR_0 + hw_id;
break;
+ case COLD:
+ /* Nothing to handle for cold interrupt */
+ return;
}
if (enable) {
@@ -367,6 +371,35 @@ static inline u32 masked_irq(u32 hw_id, u32 mask, enum tsens_ver ver)
return 0;
}
+/**
+ * tsens_cold_irq_thread - Threaded interrupt handler for cold interrupt
+ * @irq: irq number
+ * @data: tsens controller private data
+ *
+ * Whenever interrupt triggers notify thermal framework using
+ * thermal_zone_device_update().
+ *
+ * Return: IRQ_HANDLED
+ */
+
+irqreturn_t tsens_cold_irq_thread(int irq, void *data)
+{
+ struct tsens_priv *priv = data;
+ struct tsens_sensor *s = priv->cold_sensor;
+ int cold_status, ret;
+
+ ret = regmap_field_read(priv->rf[COLD_STATUS], &cold_status);
+ if (ret)
+ return ret;
+
+ dev_dbg(priv->dev, "[%u] %s: cold interrupt is %s\n",
+ s->hw_id, __func__, cold_status ? "triggered" : "cleared");
+
+ thermal_zone_device_update(s->tzd, THERMAL_EVENT_UNSPECIFIED);
+
+ return IRQ_HANDLED;
+}
+
/**
* tsens_critical_irq_thread() - Threaded handler for critical interrupts
* @irq: irq number
@@ -575,6 +608,20 @@ void tsens_disable_irq(struct tsens_priv *priv)
regmap_field_write(priv->rf[INT_EN], 0);
}
+int get_cold_int_status(const struct tsens_sensor *s, bool *cold_status)
+{
+ struct tsens_priv *priv = s->priv;
+ int prev_cold = 0, ret;
+
+ ret = regmap_field_read(priv->rf[COLD_STATUS], &prev_cold);
+ if (ret)
+ return ret;
+
+ *cold_status = (bool)prev_cold;
+
+ return 0;
+}
+
int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp)
{
struct tsens_priv *priv = s->priv;
@@ -843,6 +890,19 @@ int __init init_common(struct tsens_priv *priv)
regmap_field_write(priv->rf[CC_MON_MASK], 1);
}
+ if (tsens_version(priv) > VER_1_X && ver_minor > 5) {
+ /* COLD interrupt is present only on v2.6+ */
+ priv->feat->cold_int = 1;
+ priv->rf[COLD_STATUS] = devm_regmap_field_alloc(
+ dev,
+ priv->tm_map,
+ priv->fields[COLD_STATUS]);
+ if (IS_ERR(priv->rf[COLD_STATUS])) {
+ ret = PTR_ERR(priv->rf[COLD_STATUS]);
+ goto err_put_device;
+ }
+ }
+
spin_lock_init(&priv->ul_lock);
tsens_enable_irq(priv);
tsens_debug_init(op);
@@ -852,6 +912,30 @@ int __init init_common(struct tsens_priv *priv)
return ret;
}
+/**
+ * tsens_get_cold_status - It gets cold temperature status of TSENS
+ * @data: tsens cold sensor private data
+ * @cold_status: pointer to store last cold interrupt status
+ *
+ * It gives cold state value of 0 or 1 on success. A state
+ * value of 1 indicates minimum one TSENS is in cold temperature
+ * condition and a state value of 0 indicates all TSENS are out of
+ * cold temperature condition.
+ *
+ * Return: 0 on success, a negative errno will be returned in
+ * error cases.
+ */
+static int tsens_get_cold_status(void *data, int *cold_status)
+{
+ struct tsens_sensor *s = data;
+ struct tsens_priv *priv = s->priv;
+
+ if (priv->ops->get_cold_status)
+ return priv->ops->get_cold_status(s, (bool *)cold_status);
+
+ return -ENOTSUPP;
+}
+
static int tsens_get_temp(void *data, int *temp)
{
struct tsens_sensor *s = data;
@@ -923,6 +1007,10 @@ static const struct thermal_zone_of_device_ops tsens_of_ops = {
.set_trips = tsens_set_trips,
};
+static const struct thermal_zone_of_device_ops tsens_cold_of_ops = {
+ .get_temp = tsens_get_cold_status,
+};
+
static int tsens_register_irq(struct tsens_priv *priv, char *irqname,
irq_handler_t thread_fn)
{
@@ -980,6 +1068,28 @@ static int tsens_register(struct tsens_priv *priv)
ret = tsens_register_irq(priv, "critical",
tsens_critical_irq_thread);
+ if (priv->feat->cold_int) {
+ priv->cold_sensor = devm_kzalloc(priv->dev,
+ sizeof(struct tsens_sensor),
+ GFP_KERNEL);
+ if (!priv->cold_sensor)
+ return -ENOMEM;
+
+ priv->cold_sensor->hw_id = COLD_SENSOR_HW_ID;
+ priv->cold_sensor->priv = priv;
+ tzd = devm_thermal_zone_of_sensor_register(priv->dev,
+ priv->cold_sensor->hw_id,
+ priv->cold_sensor,
+ &tsens_cold_of_ops);
+ if (IS_ERR(tzd)) {
+ ret = 0;
+ return ret;
+ }
+
+ priv->cold_sensor->tzd = tzd;
+ ret = tsens_register_irq(priv, "cold", tsens_cold_irq_thread);
+ }
+
return ret;
}
diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h
index 59d01162c66a..be532fabef30 100644
--- a/drivers/thermal/qcom/tsens.h
+++ b/drivers/thermal/qcom/tsens.h
@@ -15,6 +15,7 @@
#define SLOPE_DEFAULT 3200
#define THRESHOLD_MAX_ADC_CODE 0x3ff
#define THRESHOLD_MIN_ADC_CODE 0x0
+#define COLD_SENSOR_HW_ID 128
#include <linux/interrupt.h>
#include <linux/thermal.h>
@@ -34,6 +35,7 @@ enum tsens_irq_type {
LOWER,
UPPER,
CRITICAL,
+ COLD,
};
/**
@@ -64,6 +66,7 @@ struct tsens_sensor {
* @suspend: Function to suspend the tsens device
* @resume: Function to resume the tsens device
* @get_trend: Function to get the thermal/temp trend
+ * @get_cold_status: Function to get the cold interrupt status
*/
struct tsens_ops {
/* mandatory callbacks */
@@ -76,6 +79,7 @@ struct tsens_ops {
int (*suspend)(struct tsens_priv *priv);
int (*resume)(struct tsens_priv *priv);
int (*get_trend)(struct tsens_sensor *s, enum thermal_trend *trend);
+ int (*get_cold_status)(const struct tsens_sensor *s, bool *cold_status);
};
#define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \
@@ -485,6 +489,8 @@ enum regfield_ids {
MAX_STATUS_14,
MAX_STATUS_15,
+ COLD_STATUS, /* COLD interrupt status */
+
/* Keep last */
MAX_REGFIELDS
};
@@ -497,6 +503,7 @@ enum regfield_ids {
* @srot_split: does the IP neatly splits the register space into SROT and TM,
* with SROT only being available to secure boot firmware?
* @has_watchdog: does this IP support watchdog functionality?
+ * @cold_int: does this IP support COLD interrupt ?
* @max_sensors: maximum sensors supported by this version of the IP
*/
struct tsens_features {
@@ -505,6 +512,7 @@ struct tsens_features {
unsigned int adc:1;
unsigned int srot_split:1;
unsigned int has_watchdog:1;
+ unsigned int cold_int:1;
unsigned int max_sensors;
};
@@ -551,6 +559,7 @@ struct tsens_context {
* @ops: pointer to list of callbacks supported by this device
* @debug_root: pointer to debugfs dentry for all tsens
* @debug: pointer to debugfs dentry for tsens controller
+ * @cold_sensor: pointer to cold sensor attached to this device
* @sensor: list of sensors attached to this device
*/
struct tsens_priv {
@@ -571,6 +580,7 @@ struct tsens_priv {
struct dentry *debug_root;
struct dentry *debug;
+ struct tsens_sensor *cold_sensor;
struct tsens_sensor sensor[];
};
@@ -580,6 +590,7 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mo
int init_common(struct tsens_priv *priv);
int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp);
int get_temp_common(const struct tsens_sensor *s, int *temp);
+int get_cold_int_status(const struct tsens_sensor *s, bool *cold_status);
/* TSENS target */
extern struct tsens_plat_data data_8960;
--
2.26.2
^ permalink raw reply related
* [PATCH v3 0/2] Add cold interrupt support to tsens driver
From: Manaf Meethalavalappu Pallikunhi @ 2020-05-22 11:46 UTC (permalink / raw)
To: Amit Kucheria, Andy Gross, Bjorn Andersson, Zhang Rui,
Daniel Lezcano, Rob Herring
Cc: linux-pm, linux-arm-msm, devicetree, linux-kernel,
Manaf Meethalavalappu Pallikunhi
The changes have dependency on merging tsens-common.c into tsens.c [1]
to merge first.
Dependencies:
[1] https://lkml.org/lkml/2020/4/29/1028
Changes in v3:
* Add cold interrupt support to tsens driver
* Update cold interrupt support in yaml
Manaf Meethalavalappu Pallikunhi (2):
drivers: thermal: tsens: Add cold interrupt support
dt-bindings: thermal: tsens: Add cold interrupt support in yaml
.../bindings/thermal/qcom-tsens.yaml | 42 +++++++
drivers/thermal/qcom/tsens-v2.c | 5 +
drivers/thermal/qcom/tsens.c | 112 +++++++++++++++++-
drivers/thermal/qcom/tsens.h | 11 ++
4 files changed, 169 insertions(+), 1 deletion(-)
--
2.26.2
^ permalink raw reply
* [PATCH v3 2/2] dt-bindings: thermal: tsens: Add cold interrupt support in yaml
From: Manaf Meethalavalappu Pallikunhi @ 2020-05-22 11:44 UTC (permalink / raw)
To: Amit Kucheria, Andy Gross, Bjorn Andersson, Zhang Rui,
Daniel Lezcano, Rob Herring
Cc: linux-pm, linux-arm-msm, devicetree, linux-kernel,
Manaf Meethalavalappu Pallikunhi
In-Reply-To: <20200522114452.28647-1-manafm@codeaurora.org>
Add cold interrupt support for tsens in yaml.
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
---
.../bindings/thermal/qcom-tsens.yaml | 42 +++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
index 2ddd39d96766..3592322fe172 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
@@ -52,12 +52,14 @@ properties:
items:
- description: Combined interrupt if upper or lower threshold crossed
- description: Interrupt if critical threshold crossed
+ - description: Interrupt if cold threshold is crossed
interrupt-names:
minItems: 1
items:
- const: uplow
- const: critical
+ - const: cold
nvmem-cells:
minItems: 1
@@ -109,8 +111,10 @@ allOf:
properties:
interrupts:
minItems: 2
+ maxItems: 3
interrupt-names:
minItems: 2
+ maxItems: 3
required:
- compatible
@@ -174,4 +178,42 @@ examples:
#qcom,sensors = <13>;
#thermal-sensor-cells = <1>;
};
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ // Example 4 (for any platform containing v2.6+ of the TSENS IP)
+ // (with thermal-zone):
+ tsens4: thermal-sensor@c265000 {
+ compatible = "qcom,sc7180-tsens", "qcom,tsens-v2";
+ reg = <0xc265000 0x1ff>,
+ <0xc223000 0x1ff>;
+
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 501 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "uplow", "critical", "cold";
+
+ #qcom,sensors = <15>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cold_thermal: cold-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&tsens4 128>;
+
+ trips {
+ cold-trip {
+ temperature = <1>;
+ hysteresis = <1>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ };
+ };
+ };
...
--
2.26.2
^ permalink raw reply related
* [PATCH v3 1/2] drivers: thermal: tsens: Add cold interrupt support
From: Manaf Meethalavalappu Pallikunhi @ 2020-05-22 11:44 UTC (permalink / raw)
To: Amit Kucheria, Andy Gross, Bjorn Andersson, Zhang Rui,
Daniel Lezcano, Rob Herring
Cc: linux-pm, linux-arm-msm, devicetree, linux-kernel,
Manaf Meethalavalappu Pallikunhi
In-Reply-To: <20200522114452.28647-1-manafm@codeaurora.org>
TSENS IP v2.6+ adds cold interrupt support. It triggers set
interrupt when aggregated minimum temperature of all TSENS falls
below cold preset threshold, 5 degree Celsius and triggers
reset interrupt when aggregated minimum temperature of all TSENS
crosses above reset threshold, 10 degree Celsius. These threshold
values could change in boot firmware code. Add support for this
interrupt in the driver.
It adds another virtual sensor to the of-thermal along with all
individual TSENS. This cold sensor only gives cold state value of
1 or 0 for successful temperature read. A state value of 1 indicates
minimum one TSENS is in cold temperature condition and state value
of 0 indicates all TSENS are out of cold temperature condition.
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
---
drivers/thermal/qcom/tsens-v2.c | 5 ++
drivers/thermal/qcom/tsens.c | 112 +++++++++++++++++++++++++++++++-
drivers/thermal/qcom/tsens.h | 11 ++++
3 files changed, 127 insertions(+), 1 deletion(-)
diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c
index b293ed32174b..1692e636d3bd 100644
--- a/drivers/thermal/qcom/tsens-v2.c
+++ b/drivers/thermal/qcom/tsens-v2.c
@@ -23,6 +23,7 @@
#define TM_Sn_UPPER_LOWER_THRESHOLD_OFF 0x0020
#define TM_Sn_CRITICAL_THRESHOLD_OFF 0x0060
#define TM_Sn_STATUS_OFF 0x00a0
+#define TM_COLD_INT_STATUS_OFF 0x00e0
#define TM_TRDY_OFF 0x00e4
#define TM_WDOG_LOG_OFF 0x013c
@@ -86,6 +87,9 @@ static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
REG_FIELD_FOR_EACH_SENSOR16(CRITICAL_STATUS, TM_Sn_STATUS_OFF, 19, 19),
REG_FIELD_FOR_EACH_SENSOR16(MAX_STATUS, TM_Sn_STATUS_OFF, 20, 20),
+ /* COLD INTERRUPT STATUS */
+ [COLD_STATUS] = REG_FIELD(TM_COLD_INT_STATUS_OFF, 0, 0),
+
/* TRDY: 1=ready, 0=in progress */
[TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0),
};
@@ -93,6 +97,7 @@ static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
static const struct tsens_ops ops_generic_v2 = {
.init = init_common,
.get_temp = get_temp_tsens_valid,
+ .get_cold_status = get_cold_int_status,
};
struct tsens_plat_data data_tsens_v2 = {
diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c
index 8d3e94d2a9ed..ee93e9d07678 100644
--- a/drivers/thermal/qcom/tsens.c
+++ b/drivers/thermal/qcom/tsens.c
@@ -205,7 +205,8 @@ static void tsens_set_interrupt_v1(struct tsens_priv *priv, u32 hw_id,
index = LOW_INT_CLEAR_0 + hw_id;
break;
case CRITICAL:
- /* No critical interrupts before v2 */
+ case COLD:
+ /* No critical and cold interrupts before v2 */
return;
}
regmap_field_write(priv->rf[index], enable ? 0 : 1);
@@ -236,6 +237,9 @@ static void tsens_set_interrupt_v2(struct tsens_priv *priv, u32 hw_id,
index_mask = CRIT_INT_MASK_0 + hw_id;
index_clear = CRIT_INT_CLEAR_0 + hw_id;
break;
+ case COLD:
+ /* Nothing to handle for cold interrupt */
+ return;
}
if (enable) {
@@ -367,6 +371,35 @@ static inline u32 masked_irq(u32 hw_id, u32 mask, enum tsens_ver ver)
return 0;
}
+/**
+ * tsens_cold_irq_thread - Threaded interrupt handler for cold interrupt
+ * @irq: irq number
+ * @data: tsens controller private data
+ *
+ * Whenever interrupt triggers notify thermal framework using
+ * thermal_zone_device_update().
+ *
+ * Return: IRQ_HANDLED
+ */
+
+irqreturn_t tsens_cold_irq_thread(int irq, void *data)
+{
+ struct tsens_priv *priv = data;
+ struct tsens_sensor *s = priv->cold_sensor;
+ int cold_status, ret;
+
+ ret = regmap_field_read(priv->rf[COLD_STATUS], &cold_status);
+ if (ret)
+ return ret;
+
+ dev_dbg(priv->dev, "[%u] %s: cold interrupt is %s\n",
+ s->hw_id, __func__, cold_status ? "triggered" : "cleared");
+
+ thermal_zone_device_update(s->tzd, THERMAL_EVENT_UNSPECIFIED);
+
+ return IRQ_HANDLED;
+}
+
/**
* tsens_critical_irq_thread() - Threaded handler for critical interrupts
* @irq: irq number
@@ -575,6 +608,20 @@ void tsens_disable_irq(struct tsens_priv *priv)
regmap_field_write(priv->rf[INT_EN], 0);
}
+int get_cold_int_status(const struct tsens_sensor *s, bool *cold_status)
+{
+ struct tsens_priv *priv = s->priv;
+ int prev_cold = 0, ret;
+
+ ret = regmap_field_read(priv->rf[COLD_STATUS], &prev_cold);
+ if (ret)
+ return ret;
+
+ *cold_status = (bool)prev_cold;
+
+ return 0;
+}
+
int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp)
{
struct tsens_priv *priv = s->priv;
@@ -843,6 +890,19 @@ int __init init_common(struct tsens_priv *priv)
regmap_field_write(priv->rf[CC_MON_MASK], 1);
}
+ if (tsens_version(priv) > VER_1_X && ver_minor > 5) {
+ /* COLD interrupt is present only on v2.6+ */
+ priv->feat->cold_int = 1;
+ priv->rf[COLD_STATUS] = devm_regmap_field_alloc(
+ dev,
+ priv->tm_map,
+ priv->fields[COLD_STATUS]);
+ if (IS_ERR(priv->rf[COLD_STATUS])) {
+ ret = PTR_ERR(priv->rf[COLD_STATUS]);
+ goto err_put_device;
+ }
+ }
+
spin_lock_init(&priv->ul_lock);
tsens_enable_irq(priv);
tsens_debug_init(op);
@@ -852,6 +912,30 @@ int __init init_common(struct tsens_priv *priv)
return ret;
}
+/**
+ * tsens_get_cold_status - It gets cold temperature status of TSENS
+ * @data: tsens cold sensor private data
+ * @cold_status: pointer to store last cold interrupt status
+ *
+ * It gives cold state value of 0 or 1 on success. A state
+ * value of 1 indicates minimum one TSENS is in cold temperature
+ * condition and a state value of 0 indicates all TSENS are out of
+ * cold temperature condition.
+ *
+ * Return: 0 on success, a negative errno will be returned in
+ * error cases.
+ */
+static int tsens_get_cold_status(void *data, int *cold_status)
+{
+ struct tsens_sensor *s = data;
+ struct tsens_priv *priv = s->priv;
+
+ if (priv->ops->get_cold_status)
+ return priv->ops->get_cold_status(s, (bool *)cold_status);
+
+ return -ENOTSUPP;
+}
+
static int tsens_get_temp(void *data, int *temp)
{
struct tsens_sensor *s = data;
@@ -923,6 +1007,10 @@ static const struct thermal_zone_of_device_ops tsens_of_ops = {
.set_trips = tsens_set_trips,
};
+static const struct thermal_zone_of_device_ops tsens_cold_of_ops = {
+ .get_temp = tsens_get_cold_status,
+};
+
static int tsens_register_irq(struct tsens_priv *priv, char *irqname,
irq_handler_t thread_fn)
{
@@ -980,6 +1068,28 @@ static int tsens_register(struct tsens_priv *priv)
ret = tsens_register_irq(priv, "critical",
tsens_critical_irq_thread);
+ if (priv->feat->cold_int) {
+ priv->cold_sensor = devm_kzalloc(priv->dev,
+ sizeof(struct tsens_sensor),
+ GFP_KERNEL);
+ if (!priv->cold_sensor)
+ return -ENOMEM;
+
+ priv->cold_sensor->hw_id = COLD_SENSOR_HW_ID;
+ priv->cold_sensor->priv = priv;
+ tzd = devm_thermal_zone_of_sensor_register(priv->dev,
+ priv->cold_sensor->hw_id,
+ priv->cold_sensor,
+ &tsens_cold_of_ops);
+ if (IS_ERR(tzd)) {
+ ret = 0;
+ return ret;
+ }
+
+ priv->cold_sensor->tzd = tzd;
+ ret = tsens_register_irq(priv, "cold", tsens_cold_irq_thread);
+ }
+
return ret;
}
diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h
index 59d01162c66a..be532fabef30 100644
--- a/drivers/thermal/qcom/tsens.h
+++ b/drivers/thermal/qcom/tsens.h
@@ -15,6 +15,7 @@
#define SLOPE_DEFAULT 3200
#define THRESHOLD_MAX_ADC_CODE 0x3ff
#define THRESHOLD_MIN_ADC_CODE 0x0
+#define COLD_SENSOR_HW_ID 128
#include <linux/interrupt.h>
#include <linux/thermal.h>
@@ -34,6 +35,7 @@ enum tsens_irq_type {
LOWER,
UPPER,
CRITICAL,
+ COLD,
};
/**
@@ -64,6 +66,7 @@ struct tsens_sensor {
* @suspend: Function to suspend the tsens device
* @resume: Function to resume the tsens device
* @get_trend: Function to get the thermal/temp trend
+ * @get_cold_status: Function to get the cold interrupt status
*/
struct tsens_ops {
/* mandatory callbacks */
@@ -76,6 +79,7 @@ struct tsens_ops {
int (*suspend)(struct tsens_priv *priv);
int (*resume)(struct tsens_priv *priv);
int (*get_trend)(struct tsens_sensor *s, enum thermal_trend *trend);
+ int (*get_cold_status)(const struct tsens_sensor *s, bool *cold_status);
};
#define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \
@@ -485,6 +489,8 @@ enum regfield_ids {
MAX_STATUS_14,
MAX_STATUS_15,
+ COLD_STATUS, /* COLD interrupt status */
+
/* Keep last */
MAX_REGFIELDS
};
@@ -497,6 +503,7 @@ enum regfield_ids {
* @srot_split: does the IP neatly splits the register space into SROT and TM,
* with SROT only being available to secure boot firmware?
* @has_watchdog: does this IP support watchdog functionality?
+ * @cold_int: does this IP support COLD interrupt ?
* @max_sensors: maximum sensors supported by this version of the IP
*/
struct tsens_features {
@@ -505,6 +512,7 @@ struct tsens_features {
unsigned int adc:1;
unsigned int srot_split:1;
unsigned int has_watchdog:1;
+ unsigned int cold_int:1;
unsigned int max_sensors;
};
@@ -551,6 +559,7 @@ struct tsens_context {
* @ops: pointer to list of callbacks supported by this device
* @debug_root: pointer to debugfs dentry for all tsens
* @debug: pointer to debugfs dentry for tsens controller
+ * @cold_sensor: pointer to cold sensor attached to this device
* @sensor: list of sensors attached to this device
*/
struct tsens_priv {
@@ -571,6 +580,7 @@ struct tsens_priv {
struct dentry *debug_root;
struct dentry *debug;
+ struct tsens_sensor *cold_sensor;
struct tsens_sensor sensor[];
};
@@ -580,6 +590,7 @@ void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mo
int init_common(struct tsens_priv *priv);
int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp);
int get_temp_common(const struct tsens_sensor *s, int *temp);
+int get_cold_int_status(const struct tsens_sensor *s, bool *cold_status);
/* TSENS target */
extern struct tsens_plat_data data_8960;
--
2.26.2
^ permalink raw reply related
* [PATCH v3 0/2] Add cold interrupt support to tsens driver
From: Manaf Meethalavalappu Pallikunhi @ 2020-05-22 11:44 UTC (permalink / raw)
To: Amit Kucheria, Andy Gross, Bjorn Andersson, Zhang Rui,
Daniel Lezcano, Rob Herring
Cc: linux-pm, linux-arm-msm, devicetree, linux-kernel,
Manaf Meethalavalappu Pallikunhi
The changes have dependency on merging tsens-common.c into tsens.c [1]
to merge first.
Dependencies:
[1] https://lkml.org/lkml/2020/4/29/1028
Changes in v3:
* Add cold interrupt support to tsens driver
* Update cold interrupt support in yaml
*** BLURB HERE ***
Manaf Meethalavalappu Pallikunhi (2):
drivers: thermal: tsens: Add cold interrupt support
dt-bindings: thermal: tsens: Add cold interrupt support in yaml
.../bindings/thermal/qcom-tsens.yaml | 42 +++++++
drivers/thermal/qcom/tsens-v2.c | 5 +
drivers/thermal/qcom/tsens.c | 112 +++++++++++++++++-
drivers/thermal/qcom/tsens.h | 11 ++
4 files changed, 169 insertions(+), 1 deletion(-)
--
2.26.2
^ permalink raw reply
* [PATCH v13 0/3] i2c: npcm7xx: add NPCM i2c controller driver
From: Tali Perry @ 2020-05-22 11:33 UTC (permalink / raw)
To: ofery, brendanhiggins, avifishman70, tmaimon77, kfting, venture,
yuenn, benjaminfair, robh+dt, wsa, andriy.shevchenko
Cc: linux-arm-kernel, linux-i2c, openbmc, devicetree, linux-kernel,
Tali Perry
This patch set adds i2c controller support
for the Nuvoton NPCM Baseboard Management Controller (BMC).
NPCM7xx includes 16 I2C controllers. This driver operates the controller.
This module also includes a slave mode.
---
v13 -> v12:
- Fix yaml example. Issue found by an updated dt_binding_check.
- remove double spacing. indentation issues.
- remove ifdef DEBUG_FS around __init and __exit.
- debugfs and counters are always present in bus struct.
- Fix npcm_i2c_write_fifo_slave flow.
- Remove version number.
v12 -> v11:
- Fix according to maintainer comments.
- debugfs simplified (usedebugfs_create_u64).
- slave read fifo split from master read fifo.
v11 -> v10:
- Fix according to maintainer comments.
- Init clk simplified.
- Comments in c99
- Split master irq function.
- debugfs not mandatory.
- yaml file fix.
v10 -> v9:
- Fix according to maintainer comments.
- binding file changed to yaml format.
- Shorten recovery flow.
- Add support for health monitoring counters.
v9 -> v8:
- Fix according to maintainer comments.
- Split lines of iowrite..(ioread..) to separate lines.
- Use readx_poll_timeout_atomic
- resolve various style issues.
v8 -> v7:
- Split to two commits, one for master, one for slave.
- Rename smb to i2c.
- Remove global vars.
v7 -> v6:
- Rebased on Linux 5.4-rc8 (was Linux 5.4-rc7).
- Fix issue found by kbuild test robot (redundant include).
- Note: left a warning related to fall through. This fall through is
intentional.
v6 -> v5:
- Update documentation
v5 -> v4:
- support recovery
- master-slave switch support needed for IPMB
v4 -> v3:
- typo on cover letter.
v3 -> v2:
- fix dt binding: compatible name: omit "bus"
v2 -> v1:
- run check patch in strict mode.
- use linux crc.
- define regs in constant offset without base.
- remove debug prints.
- no declarations for local functions.
v1: initial version
Signed-off-by: Tali Perry <tali.perry1@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
Tali Perry (3):
dt-bindings: i2c: npcm7xx: add NPCM I2C controller documentation
i2c: npcm7xx: Add Nuvoton NPCM I2C controller driver
i2c: npcm7xx: Add support for slave mode for Nuvoton NPCM BMC I2C
controller driver.
.../bindings/i2c/nuvoton,npcm7xx-i2c.yaml | 60 +
drivers/i2c/busses/Kconfig | 9 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-npcm7xx.c | 2411 +++++++++++++++++
4 files changed, 2481 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml
create mode 100644 drivers/i2c/busses/i2c-npcm7xx.c
base-commit: b9bbe6ed63b2b9f2c9ee5cbd0f2c946a2723f4ce
--
2.22.0
^ permalink raw reply
* Re: [PATCH v4 3/8] spi: stm32: Add 'SPI_SIMPLEX_RX', 'SPI_3WIRE_RX' support for stm32f4
From: Mark Brown @ 2020-05-22 11:36 UTC (permalink / raw)
To: dillon.minfei
Cc: robh+dt, p.zabel, mcoquelin.stm32, devicetree, alexandre.torgue,
thierry.reding, sam, airlied, daniel, mturquette, sboyd,
linux-arm-kernel, linux-kernel, linux-spi, linux-stm32, dri-devel,
linux-clk
In-Reply-To: <1589800165-3271-4-git-send-email-dillon.minfei@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 423 bytes --]
On Mon, May 18, 2020 at 07:09:20PM +0800, dillon.minfei@gmail.com wrote:
> 2, use stm32 spi's "In full-duplex (BIDIMODE=0 and RXONLY=0)", as tx_buf is
> null, we must add dummy data sent out before read data.
> so, add stm32f4_spi_tx_dummy() to handle this situation.
There are flags SPI_CONTROLLER_MUST_TX and SPI_CONTROLLER_MUST_RX flags
that the driver can set if it needs to, no need to open code this in the
driver.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* [PATCH v13 1/3] dt-bindings: i2c: npcm7xx: add NPCM I2C controller
From: Tali Perry @ 2020-05-22 11:33 UTC (permalink / raw)
To: ofery, brendanhiggins, avifishman70, tmaimon77, kfting, venture,
yuenn, benjaminfair, robh+dt, wsa, andriy.shevchenko
Cc: linux-arm-kernel, linux-i2c, openbmc, devicetree, linux-kernel,
Tali Perry
In-Reply-To: <20200522113312.181413-1-tali.perry1@gmail.com>
Added device tree binding documentation for Nuvoton BMC
NPCM I2C controller.
Signed-off-by: Tali Perry <tali.perry1@gmail.com>
---
.../bindings/i2c/nuvoton,npcm7xx-i2c.yaml | 60 +++++++++++++++++++
1 file changed, 60 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml
diff --git a/Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml b/Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml
new file mode 100644
index 000000000000..1c9d9a2d4bcd
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/nuvoton,npcm7xx-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: nuvoton NPCM7XX I2C Controller Device Tree Bindings
+
+description: |
+ The NPCM750x includes sixteen I2C bus controllers. All Controllers support
+ both master and slave mode. Each controller can switch between master and slave
+ at run time (i.e. IPMB mode). Each controller has two 16 byte HW FIFO for TX and
+ RX.
+
+maintainers:
+ - Tali Perry <tali.perry1@gmail.com>
+
+properties:
+ compatible:
+ enum:
+ - nuvoton,npcm7xx-i2c
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description: Reference clock for the I2C bus
+
+ bus-frequency:
+ description: Desired I2C bus clock frequency in Hz. If not specified,
+ the default 100 kHz frequency will be used.
+ possible values are 100000, 400000 and 1000000.
+ default: 100000
+ enum: [100000, 400000, 1000000]
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ i2c0: i2c@80000 {
+ compatible = "nuvoton,npcm750-i2c";
+ reg = <0x80000 0x1000>;
+ clocks = <&clk NPCM7XX_CLK_APB2>;
+ bus-frequency = <100000>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+...
--
2.22.0
^ permalink raw reply related
* [PATCH v13 2/3] i2c: npcm7xx: Add Nuvoton NPCM I2C controller driver
From: Tali Perry @ 2020-05-22 11:33 UTC (permalink / raw)
To: ofery, brendanhiggins, avifishman70, tmaimon77, kfting, venture,
yuenn, benjaminfair, robh+dt, wsa, andriy.shevchenko
Cc: linux-arm-kernel, linux-i2c, openbmc, devicetree, linux-kernel,
Tali Perry
In-Reply-To: <20200522113312.181413-1-tali.perry1@gmail.com>
Add Nuvoton NPCM BMC I2C controller driver.
Signed-off-by: Tali Perry <tali.perry1@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/i2c/busses/Kconfig | 9 +
drivers/i2c/busses/Makefile | 1 +
drivers/i2c/busses/i2c-npcm7xx.c | 1804 ++++++++++++++++++++++++++++++
3 files changed, 1814 insertions(+)
create mode 100644 drivers/i2c/busses/i2c-npcm7xx.c
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 2ddca08f8a76..a2cfc555c284 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -791,6 +791,15 @@ config I2C_NOMADIK
I2C interface from ST-Ericsson's Nomadik and Ux500 architectures,
as well as the STA2X11 PCIe I/O HUB.
+config I2C_NPCM7XX
+ tristate "Nuvoton I2C Controller"
+ depends on ARCH_NPCM7XX || COMPILE_TEST
+ help
+ If you say yes to this option, support will be included for the
+ Nuvoton I2C controller, which is available on the NPCM7xx BMC
+ controller.
+ Driver can also support slave mode (select I2C_SLAVE).
+
config I2C_OCORES
tristate "OpenCores I2C Controller"
help
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 25d60889713c..8f3dfd376bec 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -81,6 +81,7 @@ obj-$(CONFIG_I2C_MT7621) += i2c-mt7621.o
obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o
obj-$(CONFIG_I2C_MXS) += i2c-mxs.o
obj-$(CONFIG_I2C_NOMADIK) += i2c-nomadik.o
+obj-$(CONFIG_I2C_NPCM7XX) += i2c-npcm7xx.o
obj-$(CONFIG_I2C_OCORES) += i2c-ocores.o
obj-$(CONFIG_I2C_OMAP) += i2c-omap.o
obj-$(CONFIG_I2C_OWL) += i2c-owl.o
diff --git a/drivers/i2c/busses/i2c-npcm7xx.c b/drivers/i2c/busses/i2c-npcm7xx.c
new file mode 100644
index 000000000000..c6e512908fa2
--- /dev/null
+++ b/drivers/i2c/busses/i2c-npcm7xx.c
@@ -0,0 +1,1804 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Nuvoton NPCM7xx I2C Controller driver
+ *
+ * Copyright (C) 2020 Nuvoton Technologies tali.perry@nuvoton.com
+ */
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/debugfs.h>
+#include <linux/errno.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/iopoll.h>
+#include <linux/irq.h>
+#include <linux/jiffies.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+enum i2c_mode {
+ I2C_MASTER,
+ I2C_SLAVE,
+};
+
+/*
+ * External I2C Interface driver xfer indication values, which indicate status
+ * of the bus.
+ */
+enum i2c_state_ind {
+ I2C_NO_STATUS_IND = 0,
+ I2C_SLAVE_RCV_IND,
+ I2C_SLAVE_XMIT_IND,
+ I2C_SLAVE_XMIT_MISSING_DATA_IND,
+ I2C_SLAVE_RESTART_IND,
+ I2C_SLAVE_DONE_IND,
+ I2C_MASTER_DONE_IND,
+ I2C_NACK_IND,
+ I2C_BUS_ERR_IND,
+ I2C_WAKE_UP_IND,
+ I2C_BLOCK_BYTES_ERR_IND,
+ I2C_SLAVE_RCV_MISSING_DATA_IND,
+};
+
+/*
+ * Operation type values (used to define the operation currently running)
+ * module is interrupt driven, on each interrupt the current operation is
+ * checked to see if the module is currently reading or writing.
+ */
+enum i2c_oper {
+ I2C_NO_OPER = 0,
+ I2C_WRITE_OPER,
+ I2C_READ_OPER,
+};
+
+/* I2C Bank (module had 2 banks of registers) */
+enum i2c_bank {
+ I2C_BANK_0 = 0,
+ I2C_BANK_1,
+};
+
+/* Internal I2C states values (for the I2C module state machine). */
+enum i2c_state {
+ I2C_DISABLE = 0,
+ I2C_IDLE,
+ I2C_MASTER_START,
+ I2C_SLAVE_MATCH,
+ I2C_OPER_STARTED,
+ I2C_STOP_PENDING,
+};
+
+/* init register and default value required to enable module */
+#define NPCM_I2CSEGCTL 0xE4
+#define NPCM_I2CSEGCTL_INIT_VAL 0x0333F000
+
+/* Common regs */
+#define NPCM_I2CSDA 0x00
+#define NPCM_I2CST 0x02
+#define NPCM_I2CCST 0x04
+#define NPCM_I2CCTL1 0x06
+#define NPCM_I2CADDR1 0x08
+#define NPCM_I2CCTL2 0x0A
+#define NPCM_I2CADDR2 0x0C
+#define NPCM_I2CCTL3 0x0E
+#define NPCM_I2CCST2 0x18
+#define NPCM_I2CCST3 0x19
+#define I2C_VER 0x1F
+
+/*BANK0 regs*/
+#define NPCM_I2CADDR3 0x10
+#define NPCM_I2CADDR7 0x11
+#define NPCM_I2CADDR4 0x12
+#define NPCM_I2CADDR8 0x13
+#define NPCM_I2CADDR5 0x14
+#define NPCM_I2CADDR9 0x15
+#define NPCM_I2CADDR6 0x16
+#define NPCM_I2CADDR10 0x17
+
+#define NPCM_I2CCTL4 0x1A
+#define NPCM_I2CCTL5 0x1B
+#define NPCM_I2CSCLLT 0x1C /* SCL Low Time */
+#define NPCM_I2CFIF_CTL 0x1D /* FIFO Control */
+#define NPCM_I2CSCLHT 0x1E /* SCL High Time */
+
+/* BANK 1 regs */
+#define NPCM_I2CFIF_CTS 0x10 /* Both FIFOs Control and Status */
+#define NPCM_I2CTXF_CTL 0x12 /* Tx-FIFO Control */
+#define NPCM_I2CT_OUT 0x14 /* Bus T.O. */
+#define NPCM_I2CPEC 0x16 /* PEC Data */
+#define NPCM_I2CTXF_STS 0x1A /* Tx-FIFO Status */
+#define NPCM_I2CRXF_STS 0x1C /* Rx-FIFO Status */
+#define NPCM_I2CRXF_CTL 0x1E /* Rx-FIFO Control */
+
+/* NPCM_I2CST reg fields */
+#define NPCM_I2CST_XMIT BIT(0)
+#define NPCM_I2CST_MASTER BIT(1)
+#define NPCM_I2CST_NMATCH BIT(2)
+#define NPCM_I2CST_STASTR BIT(3)
+#define NPCM_I2CST_NEGACK BIT(4)
+#define NPCM_I2CST_BER BIT(5)
+#define NPCM_I2CST_SDAST BIT(6)
+#define NPCM_I2CST_SLVSTP BIT(7)
+
+/* NPCM_I2CCST reg fields */
+#define NPCM_I2CCST_BUSY BIT(0)
+#define NPCM_I2CCST_BB BIT(1)
+#define NPCM_I2CCST_MATCH BIT(2)
+#define NPCM_I2CCST_GCMATCH BIT(3)
+#define NPCM_I2CCST_TSDA BIT(4)
+#define NPCM_I2CCST_TGSCL BIT(5)
+#define NPCM_I2CCST_MATCHAF BIT(6)
+#define NPCM_I2CCST_ARPMATCH BIT(7)
+
+/* NPCM_I2CCTL1 reg fields */
+#define NPCM_I2CCTL1_START BIT(0)
+#define NPCM_I2CCTL1_STOP BIT(1)
+#define NPCM_I2CCTL1_INTEN BIT(2)
+#define NPCM_I2CCTL1_EOBINTE BIT(3)
+#define NPCM_I2CCTL1_ACK BIT(4)
+#define NPCM_I2CCTL1_GCMEN BIT(5)
+#define NPCM_I2CCTL1_NMINTE BIT(6)
+#define NPCM_I2CCTL1_STASTRE BIT(7)
+
+/* RW1S fields (inside a RW reg): */
+#define NPCM_I2CCTL1_RWS \
+ (NPCM_I2CCTL1_START | NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK)
+
+/* npcm_i2caddr reg fields */
+#define NPCM_I2CADDR_A GENMASK(6, 0)
+#define NPCM_I2CADDR_SAEN BIT(7)
+
+/* NPCM_I2CCTL2 reg fields */
+#define I2CCTL2_ENABLE BIT(0)
+#define I2CCTL2_SCLFRQ6_0 GENMASK(7, 1)
+
+/* NPCM_I2CCTL3 reg fields */
+#define I2CCTL3_SCLFRQ8_7 GENMASK(1, 0)
+#define I2CCTL3_ARPMEN BIT(2)
+#define I2CCTL3_IDL_START BIT(3)
+#define I2CCTL3_400K_MODE BIT(4)
+#define I2CCTL3_BNK_SEL BIT(5)
+#define I2CCTL3_SDA_LVL BIT(6)
+#define I2CCTL3_SCL_LVL BIT(7)
+
+/* NPCM_I2CCST2 reg fields */
+#define NPCM_I2CCST2_MATCHA1F BIT(0)
+#define NPCM_I2CCST2_MATCHA2F BIT(1)
+#define NPCM_I2CCST2_MATCHA3F BIT(2)
+#define NPCM_I2CCST2_MATCHA4F BIT(3)
+#define NPCM_I2CCST2_MATCHA5F BIT(4)
+#define NPCM_I2CCST2_MATCHA6F BIT(5)
+#define NPCM_I2CCST2_MATCHA7F BIT(5)
+#define NPCM_I2CCST2_INTSTS BIT(7)
+
+/* NPCM_I2CCST3 reg fields */
+#define NPCM_I2CCST3_MATCHA8F BIT(0)
+#define NPCM_I2CCST3_MATCHA9F BIT(1)
+#define NPCM_I2CCST3_MATCHA10F BIT(2)
+#define NPCM_I2CCST3_EO_BUSY BIT(7)
+
+/* NPCM_I2CCTL4 reg fields */
+#define I2CCTL4_HLDT GENMASK(5, 0)
+#define I2CCTL4_LVL_WE BIT(7)
+
+/* NPCM_I2CCTL5 reg fields */
+#define I2CCTL5_DBNCT GENMASK(3, 0)
+
+/* NPCM_I2CFIF_CTS reg fields */
+#define NPCM_I2CFIF_CTS_RXF_TXE BIT(1)
+#define NPCM_I2CFIF_CTS_RFTE_IE BIT(3)
+#define NPCM_I2CFIF_CTS_CLR_FIFO BIT(6)
+#define NPCM_I2CFIF_CTS_SLVRSTR BIT(7)
+
+/* NPCM_I2CTXF_CTL reg fields */
+#define NPCM_I2CTXF_CTL_TX_THR GENMASK(4, 0)
+#define NPCM_I2CTXF_CTL_THR_TXIE BIT(6)
+
+/* NPCM_I2CT_OUT reg fields */
+#define NPCM_I2CT_OUT_TO_CKDIV GENMASK(5, 0)
+#define NPCM_I2CT_OUT_T_OUTIE BIT(6)
+#define NPCM_I2CT_OUT_T_OUTST BIT(7)
+
+/* NPCM_I2CTXF_STS reg fields */
+#define NPCM_I2CTXF_STS_TX_BYTES GENMASK(4, 0)
+#define NPCM_I2CTXF_STS_TX_THST BIT(6)
+
+/* NPCM_I2CRXF_STS reg fields */
+#define NPCM_I2CRXF_STS_RX_BYTES GENMASK(4, 0)
+#define NPCM_I2CRXF_STS_RX_THST BIT(6)
+
+/* NPCM_I2CFIF_CTL reg fields */
+#define NPCM_I2CFIF_CTL_FIFO_EN BIT(4)
+
+/* NPCM_I2CRXF_CTL reg fields */
+#define NPCM_I2CRXF_CTL_RX_THR GENMASK(4, 0)
+#define NPCM_I2CRXF_CTL_LAST_PEC BIT(5)
+#define NPCM_I2CRXF_CTL_THR_RXIE BIT(6)
+
+#define I2C_HW_FIFO_SIZE 16
+
+/* I2C_VER reg fields */
+#define I2C_VER_VERSION GENMASK(6, 0)
+#define I2C_VER_FIFO_EN BIT(7)
+
+/* stall/stuck timeout in us */
+#define DEFAULT_STALL_COUNT 25
+
+/* SCLFRQ field position */
+#define SCLFRQ_0_TO_6 GENMASK(6, 0)
+#define SCLFRQ_7_TO_8 GENMASK(8, 7)
+
+/* supported clk settings. values in Hz. */
+#define I2C_FREQ_MIN_HZ 10000
+#define I2C_FREQ_MAX_HZ I2C_MAX_FAST_MODE_PLUS_FREQ
+
+/* Status of one I2C module */
+struct npcm_i2c {
+ struct i2c_adapter adap;
+ struct device *dev;
+ unsigned char __iomem *reg;
+ spinlock_t lock; /* IRQ synchronization */
+ struct completion cmd_complete;
+ int irq;
+ int cmd_err;
+ struct i2c_msg *msgs;
+ int msgs_num;
+ int num;
+ u32 apb_clk;
+ struct i2c_bus_recovery_info rinfo;
+ enum i2c_state state;
+ enum i2c_oper operation;
+ enum i2c_mode master_or_slave;
+ enum i2c_state_ind stop_ind;
+ u8 dest_addr;
+ u8 *rd_buf;
+ u16 rd_size;
+ u16 rd_ind;
+ u8 *wr_buf;
+ u16 wr_size;
+ u16 wr_ind;
+ bool fifo_use;
+ u16 PEC_mask; /* PEC bit mask per slave address */
+ bool PEC_use;
+ bool read_block_use;
+ u8 int_cnt;
+ u32 clk_period_us;
+ unsigned long int_time_stamp;
+ unsigned long bus_freq; /* in kHz */
+ u32 xmits;
+ struct dentry *debugfs; /* debugfs device directory */
+ u64 ber_cnt;
+ u64 rec_succ_cnt;
+ u64 rec_fail_cnt;
+ u64 nack_cnt;
+ u64 timeout_cnt;
+};
+
+static inline void npcm_i2c_select_bank(struct npcm_i2c *bus,
+ enum i2c_bank bank)
+{
+ u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
+
+ if (bank == I2C_BANK_0)
+ i2cctl3 = i2cctl3 & ~I2CCTL3_BNK_SEL;
+ else
+ i2cctl3 = i2cctl3 | I2CCTL3_BNK_SEL;
+ iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
+}
+
+static void npcm_i2c_init_params(struct npcm_i2c *bus)
+{
+ bus->stop_ind = I2C_NO_STATUS_IND;
+ bus->rd_size = 0;
+ bus->wr_size = 0;
+ bus->rd_ind = 0;
+ bus->wr_ind = 0;
+ bus->int_cnt = 0;
+ bus->read_block_use = false;
+ bus->int_time_stamp = 0;
+ bus->PEC_use = false;
+ bus->PEC_mask = 0;
+}
+
+static inline void npcm_i2c_wr_byte(struct npcm_i2c *bus, u8 data)
+{
+ iowrite8(data, bus->reg + NPCM_I2CSDA);
+}
+
+static inline u8 npcm_i2c_rd_byte(struct npcm_i2c *bus)
+{
+ return ioread8(bus->reg + NPCM_I2CSDA);
+}
+
+static int npcm_i2c_get_SCL(struct i2c_adapter *_adap)
+{
+ struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
+
+ return !!(I2CCTL3_SCL_LVL & ioread32(bus->reg + NPCM_I2CCTL3));
+}
+
+static int npcm_i2c_get_SDA(struct i2c_adapter *_adap)
+{
+ struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
+
+ return !!(I2CCTL3_SDA_LVL & ioread32(bus->reg + NPCM_I2CCTL3));
+}
+
+static inline u16 npcm_i2c_get_index(struct npcm_i2c *bus)
+{
+ if (bus->operation == I2C_READ_OPER)
+ return bus->rd_ind;
+ if (bus->operation == I2C_WRITE_OPER)
+ return bus->wr_ind;
+ return 0;
+}
+
+/* quick protocol (just address) */
+static inline bool npcm_i2c_is_quick(struct npcm_i2c *bus)
+{
+ return bus->wr_size == 0 && bus->rd_size == 0;
+}
+
+static void npcm_i2c_disable(struct npcm_i2c *bus)
+{
+ u8 i2cctl2;
+
+ /* Disable module */
+ i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
+ i2cctl2 = i2cctl2 & ~I2CCTL2_ENABLE;
+ iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
+
+ bus->state = I2C_DISABLE;
+}
+
+static void npcm_i2c_enable(struct npcm_i2c *bus)
+{
+ u8 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
+
+ i2cctl2 = i2cctl2 | I2CCTL2_ENABLE;
+ iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
+ bus->state = I2C_IDLE;
+}
+
+/* enable\disable end of busy (EOB) interrupts */
+static inline void npcm_i2c_eob_int(struct npcm_i2c *bus, bool enable)
+{
+ u8 val;
+
+ /* Clear EO_BUSY pending bit: */
+ val = ioread8(bus->reg + NPCM_I2CCST3);
+ val = val | NPCM_I2CCST3_EO_BUSY;
+ iowrite8(val, bus->reg + NPCM_I2CCST3);
+
+ val = ioread8(bus->reg + NPCM_I2CCTL1);
+ val &= ~NPCM_I2CCTL1_RWS;
+ if (enable)
+ val |= NPCM_I2CCTL1_EOBINTE;
+ else
+ val &= ~NPCM_I2CCTL1_EOBINTE;
+ iowrite8(val, bus->reg + NPCM_I2CCTL1);
+}
+
+static inline bool npcm_i2c_tx_fifo_empty(struct npcm_i2c *bus)
+{
+ u8 tx_fifo_sts;
+
+ tx_fifo_sts = ioread8(bus->reg + NPCM_I2CTXF_STS);
+ /* check if TX FIFO is not empty */
+ if ((tx_fifo_sts & NPCM_I2CTXF_STS_TX_BYTES) == 0)
+ return false;
+
+ /* check if TX FIFO status bit is set: */
+ return !!FIELD_GET(NPCM_I2CTXF_STS_TX_THST, tx_fifo_sts);
+}
+
+static inline bool npcm_i2c_rx_fifo_full(struct npcm_i2c *bus)
+{
+ u8 rx_fifo_sts;
+
+ rx_fifo_sts = ioread8(bus->reg + NPCM_I2CRXF_STS);
+ /* check if RX FIFO is not empty: */
+ if ((rx_fifo_sts & NPCM_I2CRXF_STS_RX_BYTES) == 0)
+ return false;
+
+ /* check if rx fifo full status is set: */
+ return !!FIELD_GET(NPCM_I2CRXF_STS_RX_THST, rx_fifo_sts);
+}
+
+static inline void npcm_i2c_clear_fifo_int(struct npcm_i2c *bus)
+{
+ u8 val;
+
+ val = ioread8(bus->reg + NPCM_I2CFIF_CTS);
+ val = (val & NPCM_I2CFIF_CTS_SLVRSTR) | NPCM_I2CFIF_CTS_RXF_TXE;
+ iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
+}
+
+static inline void npcm_i2c_clear_tx_fifo(struct npcm_i2c *bus)
+{
+ u8 val;
+
+ val = ioread8(bus->reg + NPCM_I2CTXF_STS);
+ val = val | NPCM_I2CTXF_STS_TX_THST;
+ iowrite8(val, bus->reg + NPCM_I2CTXF_STS);
+}
+
+static inline void npcm_i2c_clear_rx_fifo(struct npcm_i2c *bus)
+{
+ u8 val;
+
+ val = ioread8(bus->reg + NPCM_I2CRXF_STS);
+ val = val | NPCM_I2CRXF_STS_RX_THST;
+ iowrite8(val, bus->reg + NPCM_I2CRXF_STS);
+}
+
+static void npcm_i2c_int_enable(struct npcm_i2c *bus, bool enable)
+{
+ u8 val;
+
+ val = ioread8(bus->reg + NPCM_I2CCTL1);
+ val &= ~NPCM_I2CCTL1_RWS;
+ if (enable)
+ val |= NPCM_I2CCTL1_INTEN;
+ else
+ val &= ~NPCM_I2CCTL1_INTEN;
+ iowrite8(val, bus->reg + NPCM_I2CCTL1);
+}
+
+static inline void npcm_i2c_master_start(struct npcm_i2c *bus)
+{
+ u8 val;
+
+ val = ioread8(bus->reg + NPCM_I2CCTL1);
+ val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK);
+ val |= NPCM_I2CCTL1_START;
+ iowrite8(val, bus->reg + NPCM_I2CCTL1);
+}
+
+static inline void npcm_i2c_master_stop(struct npcm_i2c *bus)
+{
+ u8 val;
+
+ /*
+ * override HW issue: I2C may fail to supply stop condition in Master
+ * Write operation.
+ * Need to delay at least 5 us from the last int, before issueing a stop
+ */
+ udelay(10);
+ val = ioread8(bus->reg + NPCM_I2CCTL1);
+ val &= ~(NPCM_I2CCTL1_START | NPCM_I2CCTL1_ACK);
+ val |= NPCM_I2CCTL1_STOP;
+ iowrite8(val, bus->reg + NPCM_I2CCTL1);
+
+ if (!bus->fifo_use)
+ return;
+
+ npcm_i2c_select_bank(bus, I2C_BANK_1);
+
+ if (bus->operation == I2C_READ_OPER)
+ npcm_i2c_clear_rx_fifo(bus);
+ else
+ npcm_i2c_clear_tx_fifo(bus);
+ npcm_i2c_clear_fifo_int(bus);
+ iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
+}
+
+static inline void npcm_i2c_stall_after_start(struct npcm_i2c *bus, bool stall)
+{
+ u8 val;
+
+ val = ioread8(bus->reg + NPCM_I2CCTL1);
+ val &= ~NPCM_I2CCTL1_RWS;
+ if (stall)
+ val |= NPCM_I2CCTL1_STASTRE;
+ else
+ val &= ~NPCM_I2CCTL1_STASTRE;
+ iowrite8(val, bus->reg + NPCM_I2CCTL1);
+}
+
+static inline void npcm_i2c_nack(struct npcm_i2c *bus)
+{
+ u8 val;
+
+ val = ioread8(bus->reg + NPCM_I2CCTL1);
+ val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_START);
+ val |= NPCM_I2CCTL1_ACK;
+ iowrite8(val, bus->reg + NPCM_I2CCTL1);
+}
+
+static void npcm_i2c_reset(struct npcm_i2c *bus)
+{
+ /*
+ * Save I2CCTL1 relevant bits. It is being cleared when the module
+ * is disabled.
+ */
+ u8 i2cctl1;
+ u8 i2cctl2;
+
+ i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
+ i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
+
+ npcm_i2c_disable(bus);
+ npcm_i2c_enable(bus);
+
+ /* Restore NPCM_I2CCTL1 Status */
+ i2cctl1 &= ~NPCM_I2CCTL1_RWS;
+ iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
+
+ /* Clear BB (BUS BUSY) bit */
+ iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
+ iowrite8(0xFF, bus->reg + NPCM_I2CST);
+
+ /* Clear EOB bit */
+ iowrite8(NPCM_I2CCST3_EO_BUSY, bus->reg + NPCM_I2CCST3);
+
+ /* Clear all fifo bits: */
+ iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
+
+ bus->state = I2C_IDLE;
+}
+
+static inline bool npcm_i2c_is_master(struct npcm_i2c *bus)
+{
+ return !!FIELD_GET(NPCM_I2CST_MASTER, ioread8(bus->reg + NPCM_I2CST));
+}
+
+static void npcm_i2c_callback(struct npcm_i2c *bus,
+ enum i2c_state_ind op_status, u16 info)
+{
+ struct i2c_msg *msgs;
+ int msgs_num;
+
+ msgs = bus->msgs;
+ msgs_num = bus->msgs_num;
+ /*
+ * check that transaction was not timed-out, and msgs still
+ * holds a valid value.
+ */
+ if (!msgs)
+ return;
+
+ if (completion_done(&bus->cmd_complete))
+ return;
+
+ switch (op_status) {
+ case I2C_MASTER_DONE_IND:
+ bus->cmd_err = bus->msgs_num;
+ fallthrough;
+ case I2C_BLOCK_BYTES_ERR_IND:
+ /* Master tx finished and all transmit bytes were sent */
+ if (bus->msgs) {
+ if (msgs[0].flags & I2C_M_RD)
+ msgs[0].len = info;
+ else if (msgs_num == 2 &&
+ msgs[1].flags & I2C_M_RD)
+ msgs[1].len = info;
+ }
+ if (completion_done(&bus->cmd_complete) == false)
+ complete(&bus->cmd_complete);
+ break;
+
+ case I2C_NACK_IND:
+ /* MASTER transmit got a NACK before tx all bytes */
+ bus->cmd_err = -ENXIO;
+ if (bus->master_or_slave == I2C_MASTER)
+ complete(&bus->cmd_complete);
+
+ break;
+ case I2C_BUS_ERR_IND:
+ /* Bus error */
+ bus->cmd_err = -EAGAIN;
+ if (bus->master_or_slave == I2C_MASTER)
+ complete(&bus->cmd_complete);
+
+ break;
+ case I2C_WAKE_UP_IND:
+ /* I2C wake up */
+ break;
+ default:
+ break;
+ }
+
+ bus->operation = I2C_NO_OPER;
+}
+
+static u8 npcm_i2c_fifo_usage(struct npcm_i2c *bus)
+{
+ if (bus->operation == I2C_WRITE_OPER)
+ return FIELD_GET(NPCM_I2CTXF_STS_TX_BYTES,
+ ioread8(bus->reg + NPCM_I2CTXF_STS));
+ if (bus->operation == I2C_READ_OPER)
+ return FIELD_GET(NPCM_I2CRXF_STS_RX_BYTES,
+ ioread8(bus->reg + NPCM_I2CRXF_STS));
+ return 0;
+}
+
+static void npcm_i2c_write_to_fifo_master(struct npcm_i2c *bus, u16 max_bytes)
+{
+ u8 size_free_fifo;
+
+ /*
+ * Fill the FIFO, while the FIFO is not full and there are more bytes
+ * to write
+ */
+ size_free_fifo = I2C_HW_FIFO_SIZE - npcm_i2c_fifo_usage(bus);
+ while (max_bytes-- && size_free_fifo) {
+ if (bus->wr_ind < bus->wr_size)
+ npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
+ else
+ npcm_i2c_wr_byte(bus, 0xFF);
+ size_free_fifo = I2C_HW_FIFO_SIZE - npcm_i2c_fifo_usage(bus);
+ }
+}
+
+/*
+ * npcm_i2c_set_fifo:
+ * configure the FIFO before using it. If nread is -1 RX FIFO will not be
+ * configured. same for nwrite
+ */
+static void npcm_i2c_set_fifo(struct npcm_i2c *bus, int nread, int nwrite)
+{
+ u8 rxf_ctl = 0;
+
+ if (!bus->fifo_use)
+ return;
+ npcm_i2c_select_bank(bus, I2C_BANK_1);
+ npcm_i2c_clear_tx_fifo(bus);
+ npcm_i2c_clear_rx_fifo(bus);
+
+ /* configure RX FIFO */
+ if (nread > 0) {
+ rxf_ctl = min_t(int, nread, I2C_HW_FIFO_SIZE);
+
+ /* set LAST bit. if LAST is set next FIFO packet is nacked */
+ if (nread <= I2C_HW_FIFO_SIZE)
+ rxf_ctl |= NPCM_I2CRXF_CTL_LAST_PEC;
+
+ /*
+ * if we are about to read the first byte in blk rd mode,
+ * don't NACK it. If slave returns zero size HW can't NACK
+ * it immidiattly, it will read extra byte and then NACK.
+ */
+ if (bus->rd_ind == 0 && bus->read_block_use) {
+ /* set fifo to read one byte, no last: */
+ rxf_ctl = 1;
+ }
+
+ /* set fifo size: */
+ iowrite8(rxf_ctl, bus->reg + NPCM_I2CRXF_CTL);
+ }
+
+ /* configure TX FIFO */
+ if (nwrite > 0) {
+ if (nwrite > I2C_HW_FIFO_SIZE)
+ /* data to send is more then FIFO size. */
+ iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CTXF_CTL);
+ else
+ iowrite8(nwrite, bus->reg + NPCM_I2CTXF_CTL);
+
+ npcm_i2c_clear_tx_fifo(bus);
+ }
+}
+
+static void npcm_i2c_read_fifo(struct npcm_i2c *bus, u8 bytes_in_fifo)
+{
+ u8 data;
+
+ while (bytes_in_fifo--) {
+ data = npcm_i2c_rd_byte(bus);
+ if (bus->rd_ind < bus->rd_size)
+ bus->rd_buf[bus->rd_ind++] = data;
+ }
+}
+
+static inline void npcm_i2c_clear_master_status(struct npcm_i2c *bus)
+{
+ u8 val;
+
+ /* Clear NEGACK, STASTR and BER bits */
+ val = NPCM_I2CST_BER | NPCM_I2CST_NEGACK | NPCM_I2CST_STASTR;
+ iowrite8(val, bus->reg + NPCM_I2CST);
+}
+
+static void npcm_i2c_master_abort(struct npcm_i2c *bus)
+{
+ /* Only current master is allowed to issue a stop condition */
+ if (!npcm_i2c_is_master(bus))
+ return;
+
+ npcm_i2c_eob_int(bus, true);
+ npcm_i2c_master_stop(bus);
+ npcm_i2c_clear_master_status(bus);
+}
+
+static void npcm_i2c_master_fifo_read(struct npcm_i2c *bus)
+{
+ int rcount;
+ int fifo_bytes;
+ enum i2c_state_ind ind = I2C_MASTER_DONE_IND;
+
+ fifo_bytes = npcm_i2c_fifo_usage(bus);
+ rcount = bus->rd_size - bus->rd_ind;
+
+ /*
+ * In order not to change the RX_TRH during transaction (we found that
+ * this might be problematic if it takes too much time to read the FIFO)
+ * we read the data in the following way. If the number of bytes to
+ * read == FIFO Size + C (where C < FIFO Size)then first read C bytes
+ * and in the next int we read rest of the data.
+ */
+ if (rcount < (2 * I2C_HW_FIFO_SIZE) && rcount > I2C_HW_FIFO_SIZE)
+ fifo_bytes = rcount - I2C_HW_FIFO_SIZE;
+
+ if (rcount <= fifo_bytes) {
+ /* last bytes are about to be read - end of tx */
+ bus->state = I2C_STOP_PENDING;
+ bus->stop_ind = ind;
+ npcm_i2c_eob_int(bus, true);
+ /* Stop should be set before reading last byte. */
+ npcm_i2c_master_stop(bus);
+ npcm_i2c_read_fifo(bus, fifo_bytes);
+ } else {
+ npcm_i2c_read_fifo(bus, fifo_bytes);
+ rcount = bus->rd_size - bus->rd_ind;
+ npcm_i2c_set_fifo(bus, rcount, -1);
+ }
+}
+
+static void npcm_i2c_irq_master_handler_write(struct npcm_i2c *bus)
+{
+ u16 wcount;
+
+ if (bus->fifo_use)
+ npcm_i2c_clear_tx_fifo(bus); /* clear the TX fifo status bit */
+
+ /* Master write operation - last byte handling */
+ if (bus->wr_ind == bus->wr_size) {
+ if (bus->fifo_use && npcm_i2c_fifo_usage(bus) > 0)
+ /*
+ * No more bytes to send (to add to the FIFO),
+ * however the FIFO is not empty yet. It is
+ * still in the middle of tx. Currently there's nothing
+ * to do except for waiting to the end of the tx
+ * We will get an int when the FIFO will get empty.
+ */
+ return;
+
+ if (bus->rd_size == 0) {
+ /* all bytes have been written, in wr only operation */
+ npcm_i2c_eob_int(bus, true);
+ bus->state = I2C_STOP_PENDING;
+ bus->stop_ind = I2C_MASTER_DONE_IND;
+ npcm_i2c_master_stop(bus);
+ /* Clear SDA Status bit (by writing dummy byte) */
+ npcm_i2c_wr_byte(bus, 0xFF);
+
+ } else {
+ /* last write-byte written on previous int - restart */
+ npcm_i2c_set_fifo(bus, bus->rd_size, -1);
+ /* Generate repeated start upon next write to SDA */
+ npcm_i2c_master_start(bus);
+
+ /*
+ * Receiving one byte only - stall after successful
+ * completion of send address byte. If we NACK here, and
+ * slave doesn't ACK the address, we might
+ * unintentionally NACK the next multi-byte read.
+ */
+ if (bus->rd_size == 1)
+ npcm_i2c_stall_after_start(bus, true);
+
+ /* Next int will occur on read */
+ bus->operation = I2C_READ_OPER;
+ /* send the slave address in read direction */
+ npcm_i2c_wr_byte(bus, bus->dest_addr | 0x1);
+ }
+ } else {
+ /* write next byte not last byte and not slave address */
+ if (!bus->fifo_use || bus->wr_size == 1) {
+ npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
+ } else {
+ wcount = bus->wr_size - bus->wr_ind;
+ npcm_i2c_set_fifo(bus, -1, wcount);
+ if (wcount)
+ npcm_i2c_write_to_fifo_master(bus, wcount);
+ }
+ }
+}
+
+static void npcm_i2c_irq_master_handler_read(struct npcm_i2c *bus)
+{
+ u16 block_extra_bytes_size;
+ u8 data;
+
+ /* added bytes to the packet: */
+ block_extra_bytes_size = bus->read_block_use + bus->PEC_use;
+
+ /*
+ * Perform master read, distinguishing between last byte and the rest of
+ * the bytes. The last byte should be read when the clock is stopped
+ */
+ if (bus->rd_ind == 0) { /* first byte handling: */
+ if (bus->read_block_use) {
+ /* first byte in block protocol is the size: */
+ data = npcm_i2c_rd_byte(bus);
+ data = clamp_val(data, 1, I2C_SMBUS_BLOCK_MAX);
+ bus->rd_size = data + block_extra_bytes_size;
+ bus->rd_buf[bus->rd_ind++] = data;
+
+ /* clear RX FIFO interrupt status: */
+ if (bus->fifo_use) {
+ data = ioread8(bus->reg + NPCM_I2CFIF_CTS);
+ data = data | NPCM_I2CFIF_CTS_RXF_TXE;
+ iowrite8(data, bus->reg + NPCM_I2CFIF_CTS);
+ }
+
+ npcm_i2c_set_fifo(bus, bus->rd_size - 1, -1);
+ npcm_i2c_stall_after_start(bus, false);
+ } else {
+ npcm_i2c_clear_tx_fifo(bus);
+ npcm_i2c_master_fifo_read(bus);
+ }
+ } else {
+ if (bus->rd_size == block_extra_bytes_size &&
+ bus->read_block_use) {
+ bus->state = I2C_STOP_PENDING;
+ bus->stop_ind = I2C_BLOCK_BYTES_ERR_IND;
+ bus->cmd_err = -EIO;
+ npcm_i2c_eob_int(bus, true);
+ npcm_i2c_master_stop(bus);
+ npcm_i2c_read_fifo(bus, npcm_i2c_fifo_usage(bus));
+ } else {
+ npcm_i2c_master_fifo_read(bus);
+ }
+ }
+}
+
+static void npcm_i2c_irq_handle_nmatch(struct npcm_i2c *bus)
+{
+ iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
+ npcm_i2c_nack(bus);
+ bus->stop_ind = I2C_BUS_ERR_IND;
+ npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
+}
+
+/* A NACK has occurred */
+static void npcm_i2c_irq_handle_nack(struct npcm_i2c *bus)
+{
+ u8 val;
+#ifdef CONFIG_DEBUG_FS
+ if (bus->nack_cnt == ULLONG_MAX) {
+ dev_dbg(bus->dev, "nack_cnt reach max, reset to 0");
+ bus->nack_cnt = 0;
+ }
+ bus->nack_cnt++;
+#endif
+ if (bus->fifo_use) {
+ /*
+ * if there are still untransmitted bytes in TX FIFO
+ * reduce them from wr_ind
+ */
+ if (bus->operation == I2C_WRITE_OPER)
+ bus->wr_ind -= npcm_i2c_fifo_usage(bus);
+
+ /* clear the FIFO */
+ iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
+ }
+
+ /* In master write operation, got unexpected NACK */
+ bus->stop_ind = I2C_NACK_IND;
+ /* Only current master is allowed to issue Stop Condition */
+ if (npcm_i2c_is_master(bus)) {
+ /* stopping in the middle */
+ npcm_i2c_eob_int(bus, false);
+ npcm_i2c_master_stop(bus);
+
+ /*
+ * The bus is released from stall only after the SW clears
+ * NEGACK bit. Then a Stop condition is sent.
+ */
+ npcm_i2c_clear_master_status(bus);
+ readx_poll_timeout_atomic(ioread8, bus->reg + NPCM_I2CCST, val,
+ !(val & NPCM_I2CCST_BUSY), 10, 200);
+ }
+ bus->state = I2C_IDLE;
+
+ /*
+ * In Master mode, NACK should be cleared only after STOP.
+ * In such case, the bus is released from stall only after the
+ * software clears NACK bit. Then a Stop condition is sent.
+ */
+ npcm_i2c_callback(bus, bus->stop_ind, bus->wr_ind);
+}
+
+ /* Master mode: a Bus Error has been identified */
+static void npcm_i2c_irq_handle_ber(struct npcm_i2c *bus)
+{
+#ifdef CONFIG_DEBUG_FS
+ if (bus->ber_cnt == ULLONG_MAX) {
+ dev_dbg(bus->dev, "ber_cnt reach max, reset");
+ bus->ber_cnt = 0;
+ }
+ bus->ber_cnt++;
+#endif
+ bus->stop_ind = I2C_BUS_ERR_IND;
+ if (npcm_i2c_is_master(bus)) {
+ npcm_i2c_master_abort(bus);
+ } else {
+ npcm_i2c_clear_master_status(bus);
+
+ /* Clear BB (BUS BUSY) bit */
+ iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
+
+ bus->cmd_err = -EAGAIN;
+ npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
+ }
+ bus->state = I2C_IDLE;
+}
+
+ /* EOB: a master End Of Busy (meaning STOP completed) */
+static void npcm_i2c_irq_handle_eob(struct npcm_i2c *bus)
+{
+ npcm_i2c_eob_int(bus, false);
+ bus->state = I2C_IDLE;
+ npcm_i2c_callback(bus, bus->stop_ind, bus->rd_ind);
+}
+
+/* Address sent and requested stall occurred (Master mode) */
+static void npcm_i2c_irq_handle_stall_after_start(struct npcm_i2c *bus)
+{
+ if (npcm_i2c_is_quick(bus)) {
+ bus->state = I2C_STOP_PENDING;
+ bus->stop_ind = I2C_MASTER_DONE_IND;
+ npcm_i2c_eob_int(bus, true);
+ npcm_i2c_master_stop(bus);
+ } else if ((bus->rd_size == 1) && !bus->read_block_use) {
+ /*
+ * Receiving one byte only - set NACK after ensuring
+ * slave ACKed the address byte.
+ */
+ npcm_i2c_nack(bus);
+ }
+
+ /* Reset stall-after-address-byte */
+ npcm_i2c_stall_after_start(bus, false);
+
+ /* Clear stall only after setting STOP */
+ iowrite8(NPCM_I2CST_STASTR, bus->reg + NPCM_I2CST);
+}
+
+/* SDA status is set - TX or RX, master */
+static void npcm_i2c_irq_handle_sda(struct npcm_i2c *bus, u8 i2cst)
+{
+ u8 fif_cts;
+
+ if (!npcm_i2c_is_master(bus))
+ return;
+
+ if (bus->state == I2C_IDLE) {
+ bus->stop_ind = I2C_WAKE_UP_IND;
+
+ if (npcm_i2c_is_quick(bus) || bus->read_block_use)
+ /*
+ * Need to stall after successful
+ * completion of sending address byte
+ */
+ npcm_i2c_stall_after_start(bus, true);
+ else
+ npcm_i2c_stall_after_start(bus, false);
+
+ /*
+ * Receiving one byte only - stall after successful completion
+ * of sending address byte If we NACK here, and slave doesn't
+ * ACK the address, we might unintentionally NACK the next
+ * multi-byte read
+ */
+ if (bus->wr_size == 0 && bus->rd_size == 1)
+ npcm_i2c_stall_after_start(bus, true);
+
+ /* Initiate I2C master tx */
+
+ /* select bank 1 for FIFO regs */
+ npcm_i2c_select_bank(bus, I2C_BANK_1);
+
+ fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
+ fif_cts = fif_cts & ~NPCM_I2CFIF_CTS_SLVRSTR;
+
+ /* clear FIFO and relevant status bits. */
+ fif_cts = fif_cts | NPCM_I2CFIF_CTS_CLR_FIFO;
+ iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
+
+ /* re-enable */
+ fif_cts = fif_cts | NPCM_I2CFIF_CTS_RXF_TXE;
+ iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
+
+ /*
+ * Configure the FIFO threshold:
+ * according to the needed # of bytes to read.
+ * Note: due to HW limitation can't config the rx fifo before it
+ * got and ACK on the restart. LAST bit will not be reset unless
+ * RX completed. It will stay set on the next tx.
+ */
+ if (bus->wr_size)
+ npcm_i2c_set_fifo(bus, -1, bus->wr_size);
+ else
+ npcm_i2c_set_fifo(bus, bus->rd_size, -1);
+
+ bus->state = I2C_OPER_STARTED;
+
+ if (npcm_i2c_is_quick(bus) || bus->wr_size)
+ npcm_i2c_wr_byte(bus, bus->dest_addr);
+ else
+ npcm_i2c_wr_byte(bus, bus->dest_addr | BIT(0));
+ /* SDA interrupt, after start\restart */
+ } else {
+ if (NPCM_I2CST_XMIT & i2cst) {
+ bus->operation = I2C_WRITE_OPER;
+ npcm_i2c_irq_master_handler_write(bus);
+ } else {
+ bus->operation = I2C_READ_OPER;
+ npcm_i2c_irq_master_handler_read(bus);
+ }
+ }
+}
+
+static int npcm_i2c_int_master_handler(struct npcm_i2c *bus)
+{
+ u8 i2cst;
+ int ret = -EIO;
+
+ i2cst = ioread8(bus->reg + NPCM_I2CST);
+
+ if (FIELD_GET(NPCM_I2CST_NMATCH, i2cst)) {
+ npcm_i2c_irq_handle_nmatch(bus);
+ return 0;
+ }
+ /* A NACK has occurred */
+ if (FIELD_GET(NPCM_I2CST_NEGACK, i2cst)) {
+ npcm_i2c_irq_handle_nack(bus);
+ return 0;
+ }
+
+ /* Master mode: a Bus Error has been identified */
+ if (FIELD_GET(NPCM_I2CST_BER, i2cst)) {
+ npcm_i2c_irq_handle_ber(bus);
+ return 0;
+ }
+
+ /* EOB: a master End Of Busy (meaning STOP completed) */
+ if ((FIELD_GET(NPCM_I2CCTL1_EOBINTE,
+ ioread8(bus->reg + NPCM_I2CCTL1)) == 1) &&
+ (FIELD_GET(NPCM_I2CCST3_EO_BUSY,
+ ioread8(bus->reg + NPCM_I2CCST3)))) {
+ npcm_i2c_irq_handle_eob(bus);
+ return 0;
+ }
+
+ /* Address sent and requested stall occurred (Master mode) */
+ if (FIELD_GET(NPCM_I2CST_STASTR, i2cst)) {
+ npcm_i2c_irq_handle_stall_after_start(bus);
+ ret = 0;
+ }
+
+ /* SDA status is set - TX or RX, master */
+ if (FIELD_GET(NPCM_I2CST_SDAST, i2cst) ||
+ (bus->fifo_use &&
+ (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
+ npcm_i2c_irq_handle_sda(bus, i2cst);
+ ret = 0;
+ }
+
+ return ret;
+}
+
+/* recovery using TGCLK functionality of the module */
+static int npcm_i2c_recovery_tgclk(struct i2c_adapter *_adap)
+{
+ u8 val;
+ u8 fif_cts;
+ bool done = false;
+ int status = -ENOTRECOVERABLE;
+ struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
+ /* Allow 3 bytes (27 toggles) to be read from the slave: */
+ int iter = 27;
+
+ if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1)) {
+ dev_dbg(bus->dev, "bus%d recovery skipped, bus not stuck",
+ bus->num);
+ npcm_i2c_reset(bus);
+ return status;
+ }
+
+ npcm_i2c_int_enable(bus, false);
+ npcm_i2c_disable(bus);
+ npcm_i2c_enable(bus);
+ iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
+ npcm_i2c_clear_tx_fifo(bus);
+ npcm_i2c_clear_rx_fifo(bus);
+ iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
+ iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
+ npcm_i2c_stall_after_start(bus, false);
+
+ /* select bank 1 for FIFO regs */
+ npcm_i2c_select_bank(bus, I2C_BANK_1);
+
+ /* clear FIFO and relevant status bits. */
+ fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
+ fif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;
+ fif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;
+ iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
+ npcm_i2c_set_fifo(bus, -1, 0);
+
+ /* Repeat the following sequence until SDA is released */
+ do {
+ /* Issue a single SCL toggle */
+ iowrite8(NPCM_I2CCST_TGSCL, bus->reg + NPCM_I2CCST);
+ udelay(20);
+ /* If SDA line is inactive (high), stop */
+ if (npcm_i2c_get_SDA(_adap)) {
+ done = true;
+ status = 0;
+ }
+ } while (!done && iter--);
+
+ /* If SDA line is released: send start-addr-stop, to re-sync. */
+ if (npcm_i2c_get_SDA(_adap)) {
+ /* Send an address byte in write direction: */
+ npcm_i2c_wr_byte(bus, bus->dest_addr);
+ npcm_i2c_master_start(bus);
+ /* Wait until START condition is sent */
+ status = readx_poll_timeout(npcm_i2c_get_SCL, _adap, val, !val,
+ 20, 200);
+ /* If START condition was sent */
+ if (npcm_i2c_is_master(bus) > 0) {
+ udelay(20);
+ npcm_i2c_master_stop(bus);
+ udelay(200);
+ }
+ }
+ npcm_i2c_reset(bus);
+ npcm_i2c_int_enable(bus, true);
+
+ if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1))
+ status = 0;
+ else
+ status = -ENOTRECOVERABLE;
+#ifdef CONFIG_DEBUG_FS
+ if (status) {
+ if (bus->rec_fail_cnt == ULLONG_MAX) {
+ dev_dbg(bus->dev, "rec_fail_cnt reach max, reset to 0");
+ bus->rec_fail_cnt = 0;
+ }
+ bus->rec_fail_cnt++;
+ } else {
+ if (bus->rec_succ_cnt == ULLONG_MAX) {
+ dev_dbg(bus->dev, "rec_succ_cnt reach max, reset to 0");
+ bus->rec_succ_cnt = 0;
+ }
+ bus->rec_succ_cnt++;
+ }
+#endif
+ return status;
+}
+
+/* recovery using bit banging functionality of the module */
+static int npcm_i2c_recovery_init(struct i2c_adapter *_adap)
+{
+ struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
+ struct i2c_bus_recovery_info *rinfo = &bus->rinfo;
+
+ rinfo->recover_bus = npcm_i2c_recovery_tgclk;
+ rinfo->prepare_recovery = NULL;
+ rinfo->unprepare_recovery = NULL;
+ rinfo->set_scl = NULL;
+ rinfo->set_sda = NULL;
+
+ dev_dbg(bus->dev, "init i2c recovery using TGCLK\n");
+
+ rinfo->get_scl = npcm_i2c_get_SCL;
+ rinfo->get_sda = npcm_i2c_get_SDA;
+
+ _adap->bus_recovery_info = rinfo;
+
+ return 0;
+}
+
+/* SCLFRQ min/max field values */
+#define SCLFRQ_MIN 10
+#define SCLFRQ_MAX 511
+#define clk_coef(freq, mul) DIV_ROUND_UP((freq) * (mul), 1000000)
+
+/*
+ * npcm_i2c_init_clk: init HW timing parameters.
+ * NPCM7XX i2c module timing parameters are depenent on module core clk (APB)
+ * and bus frequency.
+ * 100kHz bus requires tSCL = 4 * SCLFRQ * tCLK. LT and HT are simetric.
+ * 400kHz bus requires assymetric HT and LT. A different equation is recomended
+ * by the HW designer, given core clock range (equations in comments below).
+ *
+ */
+static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz)
+{
+ u32 k1 = 0;
+ u32 k2 = 0;
+ u8 dbnct = 0;
+ u32 sclfrq = 0;
+ u8 hldt = 7;
+ u8 fast_mode = 0;
+ u32 src_clk_khz;
+ u32 bus_freq_khz;
+
+ src_clk_khz = bus->apb_clk / 1000;
+ bus_freq_khz = bus_freq_hz / 1000;
+ bus->bus_freq = bus_freq_hz;
+
+ /* 100KHz and below: */
+ if (bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) {
+ sclfrq = src_clk_khz / (bus_freq_khz * 4);
+
+ if (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX)
+ return -EDOM;
+
+ if (src_clk_khz >= 40000)
+ hldt = 17;
+ else if (src_clk_khz >= 12500)
+ hldt = 15;
+ else
+ hldt = 7;
+ }
+
+ /* 400KHz: */
+ else if (bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ) {
+ sclfrq = 0;
+ fast_mode = I2CCTL3_400K_MODE;
+
+ if (src_clk_khz < 7500)
+ /* 400KHZ cannot be supported for core clock < 7.5MHz */
+ return -EDOM;
+
+ else if (src_clk_khz >= 50000) {
+ k1 = 80;
+ k2 = 48;
+ hldt = 12;
+ dbnct = 7;
+ }
+
+ /* Master or Slave with frequency > 25MHz */
+ else if (src_clk_khz > 25000) {
+ hldt = clk_coef(src_clk_khz, 300) + 7;
+ k1 = clk_coef(src_clk_khz, 1600);
+ k2 = clk_coef(src_clk_khz, 900);
+ }
+ }
+
+ /* 1MHz: */
+ else if (bus_freq_hz <= I2C_MAX_FAST_MODE_PLUS_FREQ) {
+ sclfrq = 0;
+ fast_mode = I2CCTL3_400K_MODE;
+
+ /* 1MHZ cannot be supported for core clock < 24 MHz */
+ if (src_clk_khz < 24000)
+ return -EDOM;
+
+ k1 = clk_coef(src_clk_khz, 620);
+ k2 = clk_coef(src_clk_khz, 380);
+
+ /* Core clk > 40 MHz */
+ if (src_clk_khz > 40000) {
+ /*
+ * Set HLDT:
+ * SDA hold time: (HLDT-7) * T(CLK) >= 120
+ * HLDT = 120/T(CLK) + 7 = 120 * FREQ(CLK) + 7
+ */
+ hldt = clk_coef(src_clk_khz, 120) + 7;
+ } else {
+ hldt = 7;
+ dbnct = 2;
+ }
+ }
+
+ /* Frequency larger than 1 MHz is not supported */
+ else
+ return -EINVAL;
+
+ if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {
+ k1 = round_up(k1, 2);
+ k2 = round_up(k2 + 1, 2);
+ if (k1 < SCLFRQ_MIN || k1 > SCLFRQ_MAX ||
+ k2 < SCLFRQ_MIN || k2 > SCLFRQ_MAX)
+ return -EDOM;
+ }
+
+ /* write sclfrq value. bits [6:0] are in I2CCTL2 reg */
+ iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, sclfrq & 0x7F),
+ bus->reg + NPCM_I2CCTL2);
+
+ /* bits [8:7] are in I2CCTL3 reg */
+ iowrite8(fast_mode | FIELD_PREP(I2CCTL3_SCLFRQ8_7, (sclfrq >> 7) & 0x3),
+ bus->reg + NPCM_I2CCTL3);
+
+ /* Select Bank 0 to access NPCM_I2CCTL4/NPCM_I2CCTL5 */
+ npcm_i2c_select_bank(bus, I2C_BANK_0);
+
+ if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {
+ /*
+ * Set SCL Low/High Time:
+ * k1 = 2 * SCLLT7-0 -> Low Time = k1 / 2
+ * k2 = 2 * SCLLT7-0 -> High Time = k2 / 2
+ */
+ iowrite8(k1 / 2, bus->reg + NPCM_I2CSCLLT);
+ iowrite8(k2 / 2, bus->reg + NPCM_I2CSCLHT);
+
+ iowrite8(dbnct, bus->reg + NPCM_I2CCTL5);
+ }
+
+ iowrite8(hldt, bus->reg + NPCM_I2CCTL4);
+
+ /* Return to Bank 1, and stay there by default: */
+ npcm_i2c_select_bank(bus, I2C_BANK_1);
+
+ return 0;
+}
+
+static int npcm_i2c_init_module(struct npcm_i2c *bus, enum i2c_mode mode,
+ u32 bus_freq_hz)
+{
+ u8 val;
+ int ret;
+
+ /* Check whether module already enabled or frequency is out of bounds */
+ if ((bus->state != I2C_DISABLE && bus->state != I2C_IDLE) ||
+ bus_freq_hz < I2C_FREQ_MIN_HZ || bus_freq_hz > I2C_FREQ_MAX_HZ)
+ return -EINVAL;
+
+ npcm_i2c_disable(bus);
+
+ /* Configure FIFO mode : */
+ if (FIELD_GET(I2C_VER_FIFO_EN, ioread8(bus->reg + I2C_VER))) {
+ bus->fifo_use = true;
+ npcm_i2c_select_bank(bus, I2C_BANK_0);
+ val = ioread8(bus->reg + NPCM_I2CFIF_CTL);
+ val |= NPCM_I2CFIF_CTL_FIFO_EN;
+ iowrite8(val, bus->reg + NPCM_I2CFIF_CTL);
+ npcm_i2c_select_bank(bus, I2C_BANK_1);
+ } else {
+ bus->fifo_use = false;
+ }
+
+ /* Configure I2C module clock frequency */
+ ret = npcm_i2c_init_clk(bus, bus_freq_hz);
+ if (ret) {
+ dev_err(bus->dev, "npcm_i2c_init_clk failed\n");
+ return ret;
+ }
+
+ /* Enable module (before configuring CTL1) */
+ npcm_i2c_enable(bus);
+ bus->state = I2C_IDLE;
+ val = ioread8(bus->reg + NPCM_I2CCTL1);
+ val = (val | NPCM_I2CCTL1_NMINTE) & ~NPCM_I2CCTL1_RWS;
+ iowrite8(val, bus->reg + NPCM_I2CCTL1);
+
+ npcm_i2c_int_enable(bus, true);
+
+ npcm_i2c_reset(bus);
+
+ return 0;
+}
+
+static int __npcm_i2c_init(struct npcm_i2c *bus, struct platform_device *pdev)
+{
+ u32 clk_freq_hz;
+ int ret;
+
+ /* Initialize the internal data structures */
+ bus->state = I2C_DISABLE;
+ bus->master_or_slave = I2C_SLAVE;
+ bus->int_time_stamp = 0;
+ bus->xmits = 0;
+
+ ret = device_property_read_u32(&pdev->dev, "bus-frequency",
+ &clk_freq_hz);
+ if (ret) {
+ dev_info(&pdev->dev, "Could not read bus-frequency property\n");
+ clk_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
+ }
+
+ ret = npcm_i2c_init_module(bus, I2C_MASTER, clk_freq_hz);
+ if (ret) {
+ dev_err(&pdev->dev, "npcm_i2c_init_module failed\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static irqreturn_t npcm_i2c_bus_irq(int irq, void *dev_id)
+{
+ struct npcm_i2c *bus = dev_id;
+
+ bus->int_cnt++;
+ if (npcm_i2c_is_master(bus))
+ bus->master_or_slave = I2C_MASTER;
+
+ if (bus->master_or_slave == I2C_MASTER) {
+ bus->int_time_stamp = jiffies;
+ if (!npcm_i2c_int_master_handler(bus))
+ return IRQ_HANDLED;
+ }
+ return IRQ_NONE;
+}
+
+static bool npcm_i2c_master_start_xmit(struct npcm_i2c *bus,
+ u8 slave_addr, u16 nwrite, u16 nread,
+ u8 *write_data, u8 *read_data,
+ bool use_PEC, bool use_read_block)
+{
+ if (bus->state != I2C_IDLE) {
+ bus->cmd_err = -EBUSY;
+ return false;
+ }
+ bus->xmits++;
+ bus->dest_addr = slave_addr << 1;
+ bus->wr_buf = write_data;
+ bus->wr_size = nwrite;
+ bus->wr_ind = 0;
+ bus->rd_buf = read_data;
+ bus->rd_size = nread;
+ bus->rd_ind = 0;
+ bus->PEC_use = 0;
+
+ /* for tx PEC is appended to buffer from i2c IF. PEC flag is ignored */
+ if (nread)
+ bus->PEC_use = use_PEC;
+
+ bus->read_block_use = use_read_block;
+ if (nread && !nwrite)
+ bus->operation = I2C_READ_OPER;
+ else
+ bus->operation = I2C_WRITE_OPER;
+ bus->int_cnt = 0;
+ if (bus->fifo_use) {
+ u8 i2cfif_cts;
+
+ npcm_i2c_select_bank(bus, I2C_BANK_1);
+ /* clear FIFO and relevant status bits. */
+ i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
+ i2cfif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;
+ i2cfif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;
+ iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS);
+ }
+
+ bus->state = I2C_IDLE;
+ npcm_i2c_stall_after_start(bus, true);
+ npcm_i2c_master_start(bus);
+ return true;
+}
+
+static int npcm_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
+ int num)
+{
+ struct npcm_i2c *bus = container_of(adap, struct npcm_i2c, adap);
+ struct i2c_msg *msg0, *msg1;
+ unsigned long time_left, flags;
+ u16 nwrite, nread;
+ u8 *write_data, *read_data;
+ u8 slave_addr;
+ int timeout;
+ int ret = 0;
+ bool read_block = false;
+ bool read_PEC = false;
+ u8 bus_busy;
+ unsigned long timeout_usec;
+
+ if (bus->state == I2C_DISABLE) {
+ dev_err(bus->dev, "I2C%d module is disabled", bus->num);
+ return -EINVAL;
+ }
+
+ if (num > 2 || num < 1) {
+ dev_err(bus->dev, "I2C cmd not supported num of msgs=%d", num);
+ return -EINVAL;
+ }
+
+ msg0 = &msgs[0];
+ slave_addr = msg0->addr;
+ if (msg0->flags & I2C_M_RD) { /* read */
+ if (num == 2) {
+ dev_err(bus->dev, "num=2 but 1st msg rd instead of wr");
+ return -EINVAL;
+ }
+ nwrite = 0;
+ write_data = NULL;
+ read_data = msg0->buf;
+ if (msg0->flags & I2C_M_RECV_LEN) {
+ nread = 1;
+ read_block = true;
+ if (msg0->flags & I2C_CLIENT_PEC)
+ read_PEC = true;
+ } else {
+ nread = msg0->len;
+ }
+ } else { /* write */
+ nwrite = msg0->len;
+ write_data = msg0->buf;
+ nread = 0;
+ read_data = NULL;
+ if (num == 2) {
+ msg1 = &msgs[1];
+ read_data = msg1->buf;
+ if (slave_addr != msg1->addr) {
+ dev_err(bus->dev,
+ "SA==%02x but msg1->addr==%02x\n",
+ slave_addr, msg1->addr);
+ return -EINVAL;
+ }
+ if ((msg1->flags & I2C_M_RD) == 0) {
+ dev_err(bus->dev,
+ "num = 2 but both msg are write.\n");
+ return -EINVAL;
+ }
+ if (msg1->flags & I2C_M_RECV_LEN) {
+ nread = 1;
+ read_block = true;
+ if (msg1->flags & I2C_CLIENT_PEC)
+ read_PEC = true;
+ } else {
+ nread = msg1->len;
+ read_block = false;
+ }
+ }
+ }
+
+ /* Adaptive TimeOut: astimated time in usec + 100% margin */
+ timeout_usec = (2 * 10000 / bus->bus_freq) * (2 + nread + nwrite);
+ timeout = max(msecs_to_jiffies(35), usecs_to_jiffies(timeout_usec));
+ if (nwrite >= 32 * 1024 || nread >= 32 * 1024) {
+ dev_err(bus->dev, "i2c%d buffer too big\n", bus->num);
+ return -EINVAL;
+ }
+
+ time_left = jiffies + msecs_to_jiffies(DEFAULT_STALL_COUNT) + 1;
+ do {
+ /*
+ * we must clear slave address immediately when the bus is not
+ * busy, so we spinlock it, but we don't keep the lock for the
+ * entire while since it is too long.
+ */
+ spin_lock_irqsave(&bus->lock, flags);
+ bus_busy = ioread8(bus->reg + NPCM_I2CCST) & NPCM_I2CCST_BB;
+ spin_unlock_irqrestore(&bus->lock, flags);
+
+ } while (time_is_after_jiffies(time_left) && bus_busy);
+
+ if (bus_busy) {
+ iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
+ npcm_i2c_reset(bus);
+ i2c_recover_bus(adap);
+ return -EAGAIN;
+ }
+
+ npcm_i2c_init_params(bus);
+ bus->dest_addr = slave_addr;
+ bus->msgs = msgs;
+ bus->msgs_num = num;
+ bus->cmd_err = 0;
+ bus->read_block_use = read_block;
+
+ reinit_completion(&bus->cmd_complete);
+ if (!npcm_i2c_master_start_xmit(bus, slave_addr, nwrite, nread,
+ write_data, read_data, read_PEC,
+ read_block))
+ ret = -EBUSY;
+
+ if (ret != -EBUSY) {
+ time_left = wait_for_completion_timeout(&bus->cmd_complete,
+ timeout);
+
+ if (time_left == 0) {
+#ifdef CONFIG_DEBUG_FS
+ if (bus->timeout_cnt == ULLONG_MAX) {
+ dev_dbg(bus->dev,
+ "timeout_cnt reach max, reset to 0");
+ bus->timeout_cnt = 0;
+ }
+ bus->timeout_cnt++;
+#endif
+ if (bus->master_or_slave == I2C_MASTER) {
+ i2c_recover_bus(adap);
+ bus->cmd_err = -EIO;
+ bus->state = I2C_IDLE;
+ }
+ }
+ }
+ ret = bus->cmd_err;
+
+ /* if there was BER, check if need to recover the bus: */
+ if (bus->cmd_err == -EAGAIN)
+ ret = i2c_recover_bus(adap);
+
+ return bus->cmd_err;
+}
+
+static u32 npcm_i2c_functionality(struct i2c_adapter *adap)
+{
+ return I2C_FUNC_I2C |
+ I2C_FUNC_SMBUS_EMUL |
+ I2C_FUNC_SMBUS_BLOCK_DATA |
+ I2C_FUNC_SMBUS_PEC;
+}
+
+static const struct i2c_adapter_quirks npcm_i2c_quirks = {
+ .max_read_len = 32768,
+ .max_write_len = 32768,
+ .max_num_msgs = 2,
+ .flags = I2C_AQ_COMB_WRITE_THEN_READ,
+};
+
+static const struct i2c_algorithm npcm_i2c_algo = {
+ .master_xfer = npcm_i2c_master_xfer,
+ .functionality = npcm_i2c_functionality,
+};
+
+/* i2c debugfs directory: used to keep health monitor of i2c devices */
+static struct dentry *npcm_i2c_debugfs_dir;
+
+static void i2c_init_debugfs(struct platform_device *pdev, struct npcm_i2c *bus)
+{
+ struct dentry *d;
+
+ if (!npcm_i2c_debugfs_dir)
+ return;
+
+ d = debugfs_create_dir(dev_name(&pdev->dev), npcm_i2c_debugfs_dir);
+ if (IS_ERR_OR_NULL(d))
+ return;
+
+ debugfs_create_u64("ber_cnt", 0444, d, &bus->ber_cnt);
+ debugfs_create_u64("nack_cnt", 0444, d, &bus->nack_cnt);
+ debugfs_create_u64("rec_succ_cnt", 0444, d, &bus->rec_succ_cnt);
+ debugfs_create_u64("rec_fail_cnt", 0444, d, &bus->rec_fail_cnt);
+ debugfs_create_u64("timeout_cnt", 0444, d, &bus->timeout_cnt);
+ bus->debugfs = d;
+}
+
+static int npcm_i2c_probe_bus(struct platform_device *pdev)
+{
+ struct npcm_i2c *bus;
+ struct i2c_adapter *adap;
+ struct clk *i2c_clk;
+ static struct regmap *gcr_regmap;
+ static struct regmap *clk_regmap;
+ int ret;
+ int num;
+
+ bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
+ if (!bus)
+ return -ENOMEM;
+
+ bus->dev = &pdev->dev;
+
+ num = of_alias_get_id(pdev->dev.of_node, "i2c");
+ bus->num = num;
+ /* core clk must be acquired to calculate module timing settings */
+ i2c_clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(i2c_clk))
+ return PTR_ERR(i2c_clk);
+ bus->apb_clk = clk_get_rate(i2c_clk);
+
+ gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
+ if (IS_ERR(gcr_regmap))
+ return IS_ERR(gcr_regmap);
+ regmap_write(gcr_regmap, NPCM_I2CSEGCTL, NPCM_I2CSEGCTL_INIT_VAL);
+
+ clk_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-clk");
+ if (IS_ERR(clk_regmap))
+ return IS_ERR(clk_regmap);
+
+ bus->reg = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(bus->reg))
+ return PTR_ERR((bus)->reg);
+
+ spin_lock_init(&bus->lock);
+ init_completion(&bus->cmd_complete);
+
+ adap = &bus->adap;
+ adap->owner = THIS_MODULE;
+ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD | I2C_CLIENT_SLAVE;
+ adap->retries = 3;
+ adap->timeout = HZ;
+ adap->algo = &npcm_i2c_algo;
+ adap->quirks = &npcm_i2c_quirks;
+ adap->algo_data = bus;
+ adap->dev.parent = &pdev->dev;
+ adap->dev.of_node = pdev->dev.of_node;
+ adap->nr = pdev->id;
+
+ bus->irq = platform_get_irq(pdev, 0);
+ if (bus->irq < 0)
+ return bus->irq;
+
+ ret = devm_request_irq(bus->dev, bus->irq, npcm_i2c_bus_irq, 0,
+ dev_name(bus->dev), bus);
+ if (ret)
+ return ret;
+
+ ret = __npcm_i2c_init(bus, pdev);
+ if (ret)
+ return ret;
+
+ ret = npcm_i2c_recovery_init(adap);
+ if (ret)
+ return ret;
+
+ i2c_set_adapdata(adap, bus);
+
+ snprintf(bus->adap.name, sizeof(bus->adap.name), "Nuvoton i2c");
+ ret = i2c_add_numbered_adapter(&bus->adap);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to add numbered adapter %d\n", ret);
+ return ret;
+ }
+ platform_set_drvdata(pdev, bus);
+
+ i2c_init_debugfs(pdev, bus);
+ return 0;
+}
+
+static int npcm_i2c_remove_bus(struct platform_device *pdev)
+{
+ unsigned long lock_flags;
+ struct npcm_i2c *bus = platform_get_drvdata(pdev);
+
+ spin_lock_irqsave(&bus->lock, lock_flags);
+ npcm_i2c_disable(bus);
+ spin_unlock_irqrestore(&bus->lock, lock_flags);
+ i2c_del_adapter(&bus->adap);
+ debugfs_remove_recursive(bus->debugfs);
+ return 0;
+}
+
+static const struct of_device_id npcm_i2c_bus_of_table[] = {
+ { .compatible = "nuvoton,npcm750-i2c", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, npcm_i2c_bus_of_table);
+
+static struct platform_driver npcm_i2c_bus_driver = {
+ .probe = npcm_i2c_probe_bus,
+ .remove = npcm_i2c_remove_bus,
+ .driver = {
+ .name = "nuvoton-i2c",
+ .of_match_table = npcm_i2c_bus_of_table,
+ }
+};
+module_platform_driver(npcm_i2c_bus_driver);
+
+static int __init npcm_i2c_init(void)
+{
+ struct dentry *dir;
+
+ dir = debugfs_create_dir("i2c", NULL);
+ if (IS_ERR_OR_NULL(dir))
+ return 0;
+
+ npcm_i2c_debugfs_dir = dir;
+ return 0;
+}
+
+static void __exit npcm_i2c_exit(void)
+{
+ debugfs_remove_recursive(npcm_i2c_debugfs_dir);
+}
+
+module_init(npcm_i2c_init);
+module_exit(npcm_i2c_exit);
+
+MODULE_AUTHOR("Avi Fishman <avi.fishman@gmail.com>");
+MODULE_AUTHOR("Tali Perry <tali.perry@nuvoton.com>");
+MODULE_AUTHOR("Tyrone Ting <kfting@nuvoton.com>");
+MODULE_DESCRIPTION("Nuvoton I2C Bus Driver");
+MODULE_LICENSE("GPL v2");
--
2.22.0
^ permalink raw reply related
* [PATCH v13 3/3] i2c: npcm7xx: Add support for slave mode for Nuvoton
From: Tali Perry @ 2020-05-22 11:33 UTC (permalink / raw)
To: ofery, brendanhiggins, avifishman70, tmaimon77, kfting, venture,
yuenn, benjaminfair, robh+dt, wsa, andriy.shevchenko
Cc: linux-arm-kernel, linux-i2c, openbmc, devicetree, linux-kernel,
Tali Perry
In-Reply-To: <20200522113312.181413-1-tali.perry1@gmail.com>
Add support for slave mode for Nuvoton
NPCM BMC I2C controller driver.
Signed-off-by: Tali Perry <tali.perry1@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/i2c/busses/i2c-npcm7xx.c | 609 ++++++++++++++++++++++++++++++-
1 file changed, 608 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-npcm7xx.c b/drivers/i2c/busses/i2c-npcm7xx.c
index c6e512908fa2..579985f0a6f2 100644
--- a/drivers/i2c/busses/i2c-npcm7xx.c
+++ b/drivers/i2c/busses/i2c-npcm7xx.c
@@ -71,6 +71,24 @@ enum i2c_state {
I2C_STOP_PENDING,
};
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+/* Module supports setting multiple own slave addresses */
+enum i2c_addr {
+ I2C_SLAVE_ADDR1 = 0,
+ I2C_SLAVE_ADDR2,
+ I2C_SLAVE_ADDR3,
+ I2C_SLAVE_ADDR4,
+ I2C_SLAVE_ADDR5,
+ I2C_SLAVE_ADDR6,
+ I2C_SLAVE_ADDR7,
+ I2C_SLAVE_ADDR8,
+ I2C_SLAVE_ADDR9,
+ I2C_SLAVE_ADDR10,
+ I2C_GC_ADDR,
+ I2C_ARP_ADDR,
+};
+#endif
+
/* init register and default value required to enable module */
#define NPCM_I2CSEGCTL 0xE4
#define NPCM_I2CSEGCTL_INIT_VAL 0x0333F000
@@ -98,6 +116,23 @@ enum i2c_state {
#define NPCM_I2CADDR6 0x16
#define NPCM_I2CADDR10 0x17
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+/*
+ * npcm_i2caddr array:
+ * The module supports having multiple own slave addresses.
+ * Since the addr regs are sprinkled all over the address space,
+ * use this array to get the address or each register.
+ */
+#define I2C_NUM_OWN_ADDR 10
+const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = {
+ NPCM_I2CADDR1, NPCM_I2CADDR2,
+ NPCM_I2CADDR3, NPCM_I2CADDR4,
+ NPCM_I2CADDR5, NPCM_I2CADDR6,
+ NPCM_I2CADDR7, NPCM_I2CADDR8,
+ NPCM_I2CADDR9, NPCM_I2CADDR10,
+ };
+#endif
+
#define NPCM_I2CCTL4 0x1A
#define NPCM_I2CCTL5 0x1B
#define NPCM_I2CSCLLT 0x1C /* SCL Low Time */
@@ -269,6 +304,16 @@ struct npcm_i2c {
unsigned long int_time_stamp;
unsigned long bus_freq; /* in kHz */
u32 xmits;
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+ u8 own_slave_addr;
+ struct i2c_client *slave;
+ int slv_rd_size;
+ int slv_rd_ind;
+ int slv_wr_size;
+ int slv_wr_ind;
+ u8 slv_rd_buf[I2C_HW_FIFO_SIZE];
+ u8 slv_wr_buf[I2C_HW_FIFO_SIZE];
+#endif
struct dentry *debugfs; /* debugfs device directory */
u64 ber_cnt;
u64 rec_succ_cnt;
@@ -301,6 +346,10 @@ static void npcm_i2c_init_params(struct npcm_i2c *bus)
bus->int_time_stamp = 0;
bus->PEC_use = false;
bus->PEC_mask = 0;
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+ if (bus->slave)
+ bus->master_or_slave = I2C_SLAVE;
+#endif
}
static inline void npcm_i2c_wr_byte(struct npcm_i2c *bus, u8 data)
@@ -346,6 +395,18 @@ static void npcm_i2c_disable(struct npcm_i2c *bus)
{
u8 i2cctl2;
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+ int i;
+
+ /* select bank 0 for I2C addresses */
+ npcm_i2c_select_bank(bus, I2C_BANK_0);
+
+ /* Slave addresses removal */
+ for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR; i++)
+ iowrite8(0, bus->reg + npcm_i2caddr[i]);
+
+ npcm_i2c_select_bank(bus, I2C_BANK_1);
+#endif
/* Disable module */
i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
i2cctl2 = i2cctl2 & ~I2CCTL2_ENABLE;
@@ -509,6 +570,61 @@ static inline void npcm_i2c_nack(struct npcm_i2c *bus)
iowrite8(val, bus->reg + NPCM_I2CCTL1);
}
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+static void npcm_i2c_slave_int_enable(struct npcm_i2c *bus, bool enable)
+{
+ u8 i2cctl1;
+
+ /* enable interrupt on slave match: */
+ i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
+ i2cctl1 &= ~NPCM_I2CCTL1_RWS;
+ if (enable)
+ i2cctl1 |= NPCM_I2CCTL1_NMINTE;
+ else
+ i2cctl1 &= ~NPCM_I2CCTL1_NMINTE;
+ iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
+}
+
+static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type,
+ u8 addr, bool enable)
+{
+ u8 i2cctl1;
+ u8 i2cctl3;
+ u8 sa_reg;
+
+ sa_reg = (addr & 0x7F) | FIELD_PREP(NPCM_I2CADDR_SAEN, enable);
+ if (addr_type == I2C_GC_ADDR) {
+ i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
+ if (enable)
+ i2cctl1 |= NPCM_I2CCTL1_GCMEN;
+ else
+ i2cctl1 &= ~NPCM_I2CCTL1_GCMEN;
+ iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
+ return 0;
+ }
+ if (addr_type == I2C_ARP_ADDR) {
+ i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
+ if (enable)
+ i2cctl3 |= I2CCTL3_ARPMEN;
+ else
+ i2cctl3 &= ~I2CCTL3_ARPMEN;
+ iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
+ return 0;
+ }
+ if (addr_type >= I2C_ARP_ADDR)
+ return -EFAULT;
+ /* select bank 0 for address 3 to 10 */
+ if (addr_type > I2C_SLAVE_ADDR2)
+ npcm_i2c_select_bank(bus, I2C_BANK_0);
+ /* Set and enable the address */
+ iowrite8(sa_reg, bus->reg + npcm_i2caddr[(int)addr_type]);
+ npcm_i2c_slave_int_enable(bus, enable);
+ if (addr_type > I2C_SLAVE_ADDR2)
+ npcm_i2c_select_bank(bus, I2C_BANK_1);
+ return 0;
+}
+#endif
+
static void npcm_i2c_reset(struct npcm_i2c *bus)
{
/*
@@ -517,6 +633,7 @@ static void npcm_i2c_reset(struct npcm_i2c *bus)
*/
u8 i2cctl1;
u8 i2cctl2;
+ u8 addr;
i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
@@ -538,6 +655,13 @@ static void npcm_i2c_reset(struct npcm_i2c *bus)
/* Clear all fifo bits: */
iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+ if (bus->slave) {
+ addr = bus->slave->addr;
+ npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, addr, true);
+ }
+#endif
+
bus->state = I2C_IDLE;
}
@@ -603,6 +727,10 @@ static void npcm_i2c_callback(struct npcm_i2c *bus,
}
bus->operation = I2C_NO_OPER;
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+ if (bus->slave)
+ bus->master_or_slave = I2C_SLAVE;
+#endif
}
static u8 npcm_i2c_fifo_usage(struct npcm_i2c *bus)
@@ -714,6 +842,460 @@ static void npcm_i2c_master_abort(struct npcm_i2c *bus)
npcm_i2c_clear_master_status(bus);
}
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+static u8 npcm_i2c_get_slave_addr(struct npcm_i2c *bus, enum i2c_addr addr_type)
+{
+ u8 slave_add;
+
+ /* select bank 0 for address 3 to 10 */
+ if (addr_type > I2C_SLAVE_ADDR2)
+ npcm_i2c_select_bank(bus, I2C_BANK_0);
+
+ slave_add = ioread8(bus->reg + npcm_i2caddr[(int)addr_type]);
+
+ if (addr_type > I2C_SLAVE_ADDR2)
+ npcm_i2c_select_bank(bus, I2C_BANK_1);
+
+ return slave_add;
+}
+
+static int npcm_i2c_remove_slave_addr(struct npcm_i2c *bus, u8 slave_add)
+{
+ int i;
+
+ /* Set the enable bit */
+ slave_add |= 0x80;
+ npcm_i2c_select_bank(bus, I2C_BANK_0);
+ for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR; i++) {
+ if (ioread8(bus->reg + npcm_i2caddr[i]) == slave_add)
+ iowrite8(0, bus->reg + npcm_i2caddr[i]);
+ }
+ npcm_i2c_select_bank(bus, I2C_BANK_1);
+ return 0;
+}
+
+static void npcm_i2c_write_fifo_slave(struct npcm_i2c *bus, u16 max_bytes)
+{
+ /*
+ * Fill the FIFO, while the FIFO is not full and there are more bytes
+ * to write
+ */
+ npcm_i2c_clear_fifo_int(bus);
+ npcm_i2c_clear_tx_fifo(bus);
+ iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
+ while (max_bytes-- && I2C_HW_FIFO_SIZE != npcm_i2c_fifo_usage(bus)) {
+ if (bus->slv_wr_size <= 0)
+ break;
+ bus->slv_wr_ind = bus->slv_wr_ind % I2C_HW_FIFO_SIZE;
+ npcm_i2c_wr_byte(bus, bus->slv_wr_buf[bus->slv_wr_ind]);
+ bus->slv_wr_ind++;
+ bus->slv_wr_ind = bus->slv_wr_ind % I2C_HW_FIFO_SIZE;
+ bus->slv_wr_size--;
+ }
+}
+
+static void npcm_i2c_read_fifo_slave(struct npcm_i2c *bus, u8 bytes_in_fifo)
+{
+ u8 data;
+
+ if (!bus->slave)
+ return;
+
+ while (bytes_in_fifo--) {
+ data = npcm_i2c_rd_byte(bus);
+
+ bus->slv_rd_ind = bus->slv_rd_ind % I2C_HW_FIFO_SIZE;
+ bus->slv_rd_buf[bus->slv_rd_ind] = data;
+ bus->slv_rd_ind++;
+
+ /* 1st byte is length in block protocol: */
+ if (bus->slv_rd_ind == 1 && bus->read_block_use)
+ bus->slv_rd_size = data + bus->PEC_use + 1;
+ }
+}
+
+static int npcm_i2c_slave_get_wr_buf(struct npcm_i2c *bus)
+{
+ int i;
+ u8 value;
+ int ind;
+ int ret = bus->slv_wr_ind;
+
+ /* fill a cyclic buffer */
+ for (i = 0; i < I2C_HW_FIFO_SIZE; i++) {
+ if (bus->slv_wr_size >= I2C_HW_FIFO_SIZE)
+ break;
+ i2c_slave_event(bus->slave, I2C_SLAVE_READ_REQUESTED, &value);
+ ind = (bus->slv_wr_ind + bus->slv_wr_size) % I2C_HW_FIFO_SIZE;
+ bus->slv_wr_buf[ind] = value;
+ bus->slv_wr_size++;
+ i2c_slave_event(bus->slave, I2C_SLAVE_READ_PROCESSED, &value);
+ }
+ return I2C_HW_FIFO_SIZE - ret;
+}
+
+static void npcm_i2c_slave_send_rd_buf(struct npcm_i2c *bus)
+{
+ int i;
+
+ for (i = 0; i < bus->slv_rd_ind; i++)
+ i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_RECEIVED,
+ &bus->slv_rd_buf[i]);
+ /*
+ * once we send bytes up, need to reset the counter of the wr buf
+ * got data from master (new offset in device), ignore wr fifo:
+ */
+ if (bus->slv_rd_ind) {
+ bus->slv_wr_size = 0;
+ bus->slv_wr_ind = 0;
+ }
+
+ bus->slv_rd_ind = 0;
+ bus->slv_rd_size = bus->adap.quirks->max_read_len;
+
+ npcm_i2c_clear_fifo_int(bus);
+ npcm_i2c_clear_rx_fifo(bus);
+}
+
+static void npcm_i2c_slave_receive(struct npcm_i2c *bus, u16 nread,
+ u8 *read_data)
+{
+ bus->state = I2C_OPER_STARTED;
+ bus->operation = I2C_READ_OPER;
+ bus->slv_rd_size = nread;
+ bus->slv_rd_ind = 0;
+
+ iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
+ iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CRXF_CTL);
+ npcm_i2c_clear_tx_fifo(bus);
+ npcm_i2c_clear_rx_fifo(bus);
+}
+
+static void npcm_i2c_slave_xmit(struct npcm_i2c *bus, u16 nwrite,
+ u8 *write_data)
+{
+ if (nwrite == 0)
+ return;
+
+ bus->state = I2C_OPER_STARTED;
+ bus->operation = I2C_WRITE_OPER;
+
+ /* get the next buffer */
+ npcm_i2c_slave_get_wr_buf(bus);
+ npcm_i2c_write_fifo_slave(bus, nwrite);
+}
+
+/*
+ * npcm_i2c_slave_wr_buf_sync:
+ * currently slave IF only supports single byte operations.
+ * in order to utilyze the npcm HW FIFO, the driver will ask for 16 bytes
+ * at a time, pack them in buffer, and then transmit them all together
+ * to the FIFO and onward to the bus.
+ * NACK on read will be once reached to bus->adap->quirks->max_read_len.
+ * sending a NACK wherever the backend requests for it is not supported.
+ * the next two functions allow reading to local buffer before writing it all
+ * to the HW FIFO.
+ */
+static void npcm_i2c_slave_wr_buf_sync(struct npcm_i2c *bus)
+{
+ int left_in_fifo;
+
+ left_in_fifo = FIELD_GET(NPCM_I2CTXF_STS_TX_BYTES,
+ ioread8(bus->reg + NPCM_I2CTXF_STS));
+
+ /* fifo already full: */
+ if (left_in_fifo >= I2C_HW_FIFO_SIZE ||
+ bus->slv_wr_size >= I2C_HW_FIFO_SIZE)
+ return;
+
+ /* update the wr fifo index back to the untransmitted bytes: */
+ bus->slv_wr_ind = bus->slv_wr_ind - left_in_fifo;
+ bus->slv_wr_size = bus->slv_wr_size + left_in_fifo;
+
+ if (bus->slv_wr_ind < 0)
+ bus->slv_wr_ind += I2C_HW_FIFO_SIZE;
+}
+
+static void npcm_i2c_slave_rd_wr(struct npcm_i2c *bus)
+{
+ if (NPCM_I2CST_XMIT & ioread8(bus->reg + NPCM_I2CST)) {
+ /*
+ * Slave got an address match with direction bit 1 so it should
+ * transmit data. Write till the master will NACK
+ */
+ bus->operation = I2C_WRITE_OPER;
+ npcm_i2c_slave_xmit(bus, bus->adap.quirks->max_write_len,
+ bus->slv_wr_buf);
+ } else {
+ /*
+ * Slave got an address match with direction bit 0 so it should
+ * receive data.
+ * this module does not support saying no to bytes.
+ * it will always ACK.
+ */
+ bus->operation = I2C_READ_OPER;
+ npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
+ bus->stop_ind = I2C_SLAVE_RCV_IND;
+ npcm_i2c_slave_send_rd_buf(bus);
+ npcm_i2c_slave_receive(bus, bus->adap.quirks->max_read_len,
+ bus->slv_rd_buf);
+ }
+}
+
+static irqreturn_t npcm_i2c_int_slave_handler(struct npcm_i2c *bus)
+{
+ u8 val;
+ irqreturn_t ret = IRQ_NONE;
+ u8 i2cst = ioread8(bus->reg + NPCM_I2CST);
+
+ /* Slave: A NACK has occurred */
+ if (NPCM_I2CST_NEGACK & i2cst) {
+ bus->stop_ind = I2C_NACK_IND;
+ npcm_i2c_slave_wr_buf_sync(bus);
+ if (bus->fifo_use)
+ /* clear the FIFO */
+ iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO,
+ bus->reg + NPCM_I2CFIF_CTS);
+
+ /* In slave write, NACK is OK, otherwise it is a problem */
+ bus->stop_ind = I2C_NO_STATUS_IND;
+ bus->operation = I2C_NO_OPER;
+ bus->own_slave_addr = 0xFF;
+
+ /*
+ * Slave has to wait for STOP to decide this is the end
+ * of the transaction. tx is not yet considered as done
+ */
+ iowrite8(NPCM_I2CST_NEGACK, bus->reg + NPCM_I2CST);
+
+ ret = IRQ_HANDLED;
+ }
+
+ /* Slave mode: a Bus Error (BER) has been identified */
+ if (NPCM_I2CST_BER & i2cst) {
+ /*
+ * Check whether bus arbitration or Start or Stop during data
+ * xfer bus arbitration problem should not result in recovery
+ */
+ bus->stop_ind = I2C_BUS_ERR_IND;
+
+ /* wait for bus busy before clear fifo */
+ iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
+
+ bus->state = I2C_IDLE;
+
+ /*
+ * in BER case we might get 2 interrupts: one for slave one for
+ * master ( for a channel which is master\slave switching)
+ */
+ if (completion_done(&bus->cmd_complete) == false) {
+ bus->cmd_err = -EIO;
+ complete(&bus->cmd_complete);
+ }
+ bus->own_slave_addr = 0xFF;
+ iowrite8(NPCM_I2CST_BER, bus->reg + NPCM_I2CST);
+ ret = IRQ_HANDLED;
+ }
+
+ /* A Slave Stop Condition has been identified */
+ if (NPCM_I2CST_SLVSTP & i2cst) {
+ u8 bytes_in_fifo = npcm_i2c_fifo_usage(bus);
+
+ bus->stop_ind = I2C_SLAVE_DONE_IND;
+
+ if (bus->operation == I2C_READ_OPER)
+ npcm_i2c_read_fifo_slave(bus, bytes_in_fifo);
+
+ /* if the buffer is empty nothing will be sent */
+ npcm_i2c_slave_send_rd_buf(bus);
+
+ /* Slave done transmitting or receiving */
+ bus->stop_ind = I2C_NO_STATUS_IND;
+
+ /*
+ * Note, just because we got here, it doesn't mean we through
+ * away the wr buffer.
+ * we keep it until the next received offset.
+ */
+ bus->operation = I2C_NO_OPER;
+ bus->int_cnt = 0;
+ bus->own_slave_addr = 0xFF;
+ i2c_slave_event(bus->slave, I2C_SLAVE_STOP, 0);
+ iowrite8(NPCM_I2CST_SLVSTP, bus->reg + NPCM_I2CST);
+ if (bus->fifo_use) {
+ npcm_i2c_clear_fifo_int(bus);
+ npcm_i2c_clear_rx_fifo(bus);
+ npcm_i2c_clear_tx_fifo(bus);
+
+ iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO,
+ bus->reg + NPCM_I2CFIF_CTS);
+ }
+ bus->state = I2C_IDLE;
+ ret = IRQ_HANDLED;
+ }
+
+ /* restart condition occurred and Rx-FIFO was not empty */
+ if (bus->fifo_use && FIELD_GET(NPCM_I2CFIF_CTS_SLVRSTR,
+ ioread8(bus->reg + NPCM_I2CFIF_CTS))) {
+ bus->stop_ind = I2C_SLAVE_RESTART_IND;
+ bus->master_or_slave = I2C_SLAVE;
+ if (bus->operation == I2C_READ_OPER)
+ npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
+ bus->operation = I2C_WRITE_OPER;
+ iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
+ val = NPCM_I2CFIF_CTS_CLR_FIFO | NPCM_I2CFIF_CTS_SLVRSTR |
+ NPCM_I2CFIF_CTS_RXF_TXE;
+ iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
+ npcm_i2c_slave_rd_wr(bus);
+ ret = IRQ_HANDLED;
+ }
+
+ /* A Slave Address Match has been identified */
+ if (NPCM_I2CST_NMATCH & i2cst) {
+ u8 info = 0;
+
+ /* Address match automatically implies slave mode */
+ bus->master_or_slave = I2C_SLAVE;
+ npcm_i2c_clear_fifo_int(bus);
+ npcm_i2c_clear_rx_fifo(bus);
+ npcm_i2c_clear_tx_fifo(bus);
+ iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
+ iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CRXF_CTL);
+ if (NPCM_I2CST_XMIT & i2cst) {
+ bus->operation = I2C_WRITE_OPER;
+ } else {
+ i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_REQUESTED,
+ &info);
+ bus->operation = I2C_READ_OPER;
+ }
+ if (bus->own_slave_addr == 0xFF) {
+ /* Check which type of address match */
+ val = ioread8(bus->reg + NPCM_I2CCST);
+ if (NPCM_I2CCST_MATCH & val) {
+ u16 addr;
+ enum i2c_addr eaddr;
+ u8 i2ccst2;
+ u8 i2ccst3;
+
+ i2ccst3 = ioread8(bus->reg + NPCM_I2CCST3);
+ i2ccst2 = ioread8(bus->reg + NPCM_I2CCST2);
+
+ /*
+ * the i2c module can response to 10 own SA.
+ * check which one was addressed by the master.
+ * repond to the first one.
+ */
+ addr = ((i2ccst3 & 0x07) << 7) |
+ (i2ccst2 & 0x7F);
+ info = ffs(addr);
+ eaddr = (enum i2c_addr)info;
+ addr = npcm_i2c_get_slave_addr(bus, eaddr);
+ addr &= 0x7F;
+ bus->own_slave_addr = addr;
+ if (bus->PEC_mask & BIT(info))
+ bus->PEC_use = true;
+ else
+ bus->PEC_use = false;
+ } else {
+ if (NPCM_I2CCST_GCMATCH & val)
+ bus->own_slave_addr = 0;
+ if (NPCM_I2CCST_ARPMATCH & val)
+ bus->own_slave_addr = 0x61;
+ }
+ } else {
+ /*
+ * Slave match can happen in two options:
+ * 1. Start, SA, read (slave read without further ado)
+ * 2. Start, SA, read, data, restart, SA, read, ...
+ * (slave read in fragmented mode)
+ * 3. Start, SA, write, data, restart, SA, read, ..
+ * (regular write-read mode)
+ */
+ if ((bus->state == I2C_OPER_STARTED &&
+ bus->operation == I2C_READ_OPER &&
+ bus->stop_ind == I2C_SLAVE_XMIT_IND) ||
+ bus->stop_ind == I2C_SLAVE_RCV_IND) {
+ /* slave tx after slave rx w/o STOP */
+ bus->stop_ind = I2C_SLAVE_RESTART_IND;
+ }
+ }
+
+ if (NPCM_I2CST_XMIT & i2cst)
+ bus->stop_ind = I2C_SLAVE_XMIT_IND;
+ else
+ bus->stop_ind = I2C_SLAVE_RCV_IND;
+ bus->state = I2C_SLAVE_MATCH;
+ npcm_i2c_slave_rd_wr(bus);
+ iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
+ ret = IRQ_HANDLED;
+ }
+
+ /* Slave SDA status is set - tx or rx */
+ if ((NPCM_I2CST_SDAST & i2cst) ||
+ (bus->fifo_use &&
+ (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
+ npcm_i2c_slave_rd_wr(bus);
+ iowrite8(NPCM_I2CST_SDAST, bus->reg + NPCM_I2CST);
+ ret = IRQ_HANDLED;
+ } /* SDAST */
+
+ return ret;
+}
+
+static int npcm_i2c_reg_slave(struct i2c_client *client)
+{
+ unsigned long lock_flags;
+ struct npcm_i2c *bus = i2c_get_adapdata(client->adapter);
+
+ bus->slave = client;
+
+ if (!bus->slave)
+ return -EINVAL;
+
+ if (client->flags & I2C_CLIENT_TEN)
+ return -EAFNOSUPPORT;
+
+ spin_lock_irqsave(&bus->lock, lock_flags);
+
+ npcm_i2c_init_params(bus);
+ bus->slv_rd_size = 0;
+ bus->slv_wr_size = 0;
+ bus->slv_rd_ind = 0;
+ bus->slv_wr_ind = 0;
+ if (client->flags & I2C_CLIENT_PEC)
+ bus->PEC_use = true;
+
+ dev_info(bus->dev, "i2c%d register slave SA=0x%x, PEC=%d\n", bus->num,
+ client->addr, bus->PEC_use);
+
+ npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, client->addr, true);
+ npcm_i2c_clear_fifo_int(bus);
+ npcm_i2c_clear_rx_fifo(bus);
+ npcm_i2c_clear_tx_fifo(bus);
+ npcm_i2c_slave_int_enable(bus, true);
+
+ spin_unlock_irqrestore(&bus->lock, lock_flags);
+ return 0;
+}
+
+static int npcm_i2c_unreg_slave(struct i2c_client *client)
+{
+ struct npcm_i2c *bus = client->adapter->algo_data;
+ unsigned long lock_flags;
+
+ spin_lock_irqsave(&bus->lock, lock_flags);
+ if (!bus->slave) {
+ spin_unlock_irqrestore(&bus->lock, lock_flags);
+ return -EINVAL;
+ }
+ npcm_i2c_slave_int_enable(bus, false);
+ npcm_i2c_remove_slave_addr(bus, client->addr);
+ bus->slave = NULL;
+ spin_unlock_irqrestore(&bus->lock, lock_flags);
+ return 0;
+}
+#endif /* CONFIG_I2C_SLAVE */
+
static void npcm_i2c_master_fifo_read(struct npcm_i2c *bus)
{
int rcount;
@@ -1399,6 +1981,9 @@ static int __npcm_i2c_init(struct npcm_i2c *bus, struct platform_device *pdev)
bus->master_or_slave = I2C_SLAVE;
bus->int_time_stamp = 0;
bus->xmits = 0;
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+ bus->slave = NULL;
+#endif
ret = device_property_read_u32(&pdev->dev, "bus-frequency",
&clk_freq_hz);
@@ -1429,6 +2014,12 @@ static irqreturn_t npcm_i2c_bus_irq(int irq, void *dev_id)
if (!npcm_i2c_int_master_handler(bus))
return IRQ_HANDLED;
}
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+ if (bus->slave) {
+ bus->master_or_slave = I2C_SLAVE;
+ return npcm_i2c_int_slave_handler(bus);
+ }
+#endif
return IRQ_NONE;
}
@@ -1570,6 +2161,11 @@ static int npcm_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
*/
spin_lock_irqsave(&bus->lock, flags);
bus_busy = ioread8(bus->reg + NPCM_I2CCST) & NPCM_I2CCST_BB;
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+ if (!bus_busy && bus->slave)
+ iowrite8((bus->slave->addr & 0x7F),
+ bus->reg + NPCM_I2CADDR1);
+#endif
spin_unlock_irqrestore(&bus->lock, flags);
} while (time_is_after_jiffies(time_left) && bus_busy);
@@ -1620,6 +2216,12 @@ static int npcm_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
if (bus->cmd_err == -EAGAIN)
ret = i2c_recover_bus(adap);
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+ /* reenable slave if it was enabled */
+ if (bus->slave)
+ iowrite8((bus->slave->addr & 0x7F) | NPCM_I2CADDR_SAEN,
+ bus->reg + NPCM_I2CADDR1);
+#endif
return bus->cmd_err;
}
@@ -1628,7 +2230,8 @@ static u32 npcm_i2c_functionality(struct i2c_adapter *adap)
return I2C_FUNC_I2C |
I2C_FUNC_SMBUS_EMUL |
I2C_FUNC_SMBUS_BLOCK_DATA |
- I2C_FUNC_SMBUS_PEC;
+ I2C_FUNC_SMBUS_PEC |
+ I2C_FUNC_SLAVE;
}
static const struct i2c_adapter_quirks npcm_i2c_quirks = {
@@ -1641,6 +2244,10 @@ static const struct i2c_adapter_quirks npcm_i2c_quirks = {
static const struct i2c_algorithm npcm_i2c_algo = {
.master_xfer = npcm_i2c_master_xfer,
.functionality = npcm_i2c_functionality,
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+ .reg_slave = npcm_i2c_reg_slave,
+ .unreg_slave = npcm_i2c_unreg_slave,
+#endif
};
/* i2c debugfs directory: used to keep health monitor of i2c devices */
--
2.22.0
^ permalink raw reply related
* Re: [PATCH v3 01/16] spi: dw: Add Tx/Rx finish wait methods to the MID DMA
From: Serge Semin @ 2020-05-22 11:32 UTC (permalink / raw)
To: Feng Tang
Cc: Serge Semin, Mark Brown, Grant Likely, Vinod Koul, Alan Cox,
Linus Walleij, Georgy Vlasov, Ramil Zaripov, Alexey Malahov,
Thomas Bogendoerfer, Paul Burton, Ralf Baechle, Arnd Bergmann,
Andy Shevchenko, Rob Herring, linux-mips, devicetree,
Jarkko Nikula, Thomas Gleixner, Wan Ahmad Zainie, Linus Walleij,
Clement Leger, linux-spi, linux-kernel
In-Reply-To: <20200522075844.GC12568@shbuild999.sh.intel.com>
On Fri, May 22, 2020 at 03:58:44PM +0800, Feng Tang wrote:
> Hi Serge,
>
> On Thu, May 21, 2020 at 06:33:17PM +0300, Serge Semin wrote:
> > > > > > + dw_spi_dma_wait_rx_done(dws);
> > > > >
> > > > > I can understand the problem about TX, but I don't see how RX
> > > > > will get hurt, can you elaborate more? thanks
> > > > >
> > > > > - Feng
> > > >
> > > > Your question is correct. You are right with your hypothesis. Ideally upon the
> > > > dw_spi_dma_rx_done() execution Rx FIFO must be already empty. That's why the
> > > > commit log signifies the error being mostly related with Tx FIFO. But
> > > > practically there are many reasons why Rx FIFO might be left with data:
> > > > DMA engine failures, incorrect DMA configuration (if DW SPI or DW DMA driver
> > > > messed something up), controller hanging up, and so on. It's better to catch
> > > > an error at this stage while propagating it up to the SPI device drivers.
> > > > Especially seeing the wait-check implementation doesn't gives us much of the
> > > > execution overhead in normal conditions. So by calling dw_spi_dma_wait_rx_done()
> > > > we make sure that all the data has been fetched and we may freely get the
> > > > buffers back to the client driver.
> > >
> > > I see your point about checking RX. But I still don't think checking
> > > RX FIFO level is the right way to detect error. Some data left in
> > > RX FIFO doesn't always mean a error, say for some case if there is
> > > 20 words in RX FIFO, and the driver starts a DMA request for 16
> > > words, then after a sucessful DMA transaction, there are 4 words
> > > left without any error.
> >
> > Neither Tx nor Rx FIFO should be left with any data after transaction is
> > finished. If they are then something has been wrong.
> >
> > See, every SPI transfer starts with FIFO clearance since we disable/enable the
> > SPI controller by means of the SSIENR (spi_enable_chip(dws, 0) and
> > spi_enable_chip(dws, 1) called in the dw_spi_transfer_one() callback). Here is the
> > SSIENR register description: "It enables and disables all SPI Controller operations.
> > When disabled, all serial transfers are halted immediately. Transmit and receive
> > FIFO buffers are cleared when the device is disabled. It is impossible to program
> > some of the SPI Controller control registers when enabled"
> >
> > No mater whether we start DMA request or perform the normal IRQ-based PIO, we
> > request as much data as we need and neither Tx nor Rx FIFO are supposed to
> > be left with any data after the request is finished. If data is left, then
> > either we didn't push all of the necessary data to the SPI bus, or we didn't
> > pull all the data from the FIFO, and this could have happened only due to some
> > component mulfunction (drivers, DMA engine, SPI device). In any case the SPI
> > device driver should be notified about the problem.
>
> Data left in TX FIFO and Data left in RX FIFO are 2 different stories. The
> former in dma case means the dma hw/driver has done its job, and spi hw/driver
> hasn't done its job of pushing out the data to spi slave devices,
Agreed.
> while the
> latter means the spi hw/driver has done its job, while the dma hw/driver hasn't.
In this particular case agreed, that the data left in the Rx FIFO means DMA
hw/driver hasn't done its work right. Though SPI hw could be also a reason of
the data left in FIFO (though this only a theoretical consideration).
>
> And the code is called inside the dma rx channel callback, which means the
> dma driver is saying "hey, I've done my job", but apparently it hasn't if
> there is data left.
Right, either it hasn't, or the DMA engine claimed it has, but still is doing
something (asynchronously or something, depending on the hardware implementation),
or it think it has, but in fact it hasn't due to whatever problem happened
(software/hardware/etc.). In anyway we have to at least check whether it's
really done with fetching data and to be on a safe side give it some time to
make sure that the Rx FIFO isn't going to be emptied. Whatever problem it is
having a non empty Rx FIFO at the stage of calling spi_finalize_current_transfer()
means a certain error.
>
> As for the wait time
>
> + nents = dw_readl(dws, DW_SPI_RXFLR);
> + ns = (NSEC_PER_SEC / spi_get_clk(dws)) * nents * dws->n_bytes *
> + BITS_PER_BYTE;
>
> Using this formula for checking TX makes sense, but it doesn't for RX.
> Because the time of pushing data in TX FIFO to spi device depends on
> the clk, but the time of transferring RX FIFO to memory is up to
> the DMA controller and peripheral bus.
On this I agree with you. That formulae doesn't describe exactly the time left
before the Rx FIFO gets empty. But at least it provides an upper limit on the
time needed for the peripheral bus to fetch the data from FIFO. If for some
reason the internal APB bus is slower than the SPI bus, then the hardware
engineers screwed, since the CPU/DMA won't keep up with pulling data from Rx
FIFO on time so the FIFO may get overflown. Though in this case CPU/DMA won't
be able to push data to the Tx FIFO fast enough to cause the Rx FIFO overflown,
so the problem might be unnoticeable until we enable the EEPROM-read or Rx-only
modes of the DW APB SSI controller. Anyway I am pretty much sure all the systems
have the internal bus much faster than the external SPI bus.
Getting back to the formulae. I was thinking of how to make it better and here
is what we can do. We can't predict neither the DMA controller performance,
nor the performance of its driver. In this case we have no choice but to add
some assumption to clarify the task. Let's assume that the reason why Rx FIFO is
non-empty is that even though we are at the DMA completion callback, but the
DMA controller is still fetching data in background (any other reason might be
related with a bug, so we'll detect it here anyway). In this case we need to
give it a time to finish its work. As far as I can see the DW_apb_ssi interface
doesn't use PREADY APB signal, which means the IO access cycle will take 4
reference clock periods for each read and write accesses. Thus taking all of
these into account we can create the next formulae to measure the time needed to
read all the data from the Rx FIFO:
- ns = (NSEC_PER_SEC / spi_get_clk(dws)) * nents * dws->n_bytes *
- BITS_PER_BYTE;
+ ns = (NSEC_PER_SEC / dws->max_freq) * nents * 4;
By doing several busy-wait loop iteration we'll cover the DMA controller and
it's driver possible latency.
Feng, does it now makes sense for you now? If so, I'll replace the delay
calculation formulae in the patch.
>
> Also for the
>
> + while (dw_spi_dma_rx_busy(dws) && retry--)
> + ndelay(ns);
> +
>
> the rx busy bit is cleared after this rx/tx checking, and it should
> be always true at this point. Am I mis-reading the code?
Sorry I don't get your logic here. I am not checking the Rx busy bit here,
but the Rx FIFO non-empty bit. Also SR register bits aren't cleared on read,
so the status bits are left pending until the reason is cleared. In our case
until Rx FIFO gets empty, which will happen eventually either at the point of
all data finally being extracted from it or when the controller is disabled
by means of the SSIENR register.
-Sergey
>
> Thanks,
> Feng
>
> >
> > -Sergey
> >
^ permalink raw reply
* Re: [RFC v1 2/3] drivers: nvmem: Add driver for QTI qfprom-efuse support
From: Srinivas Kandagatla @ 2020-05-22 11:18 UTC (permalink / raw)
To: Doug Anderson
Cc: Ravi Kumar Bokka (Temp), Rob Herring, LKML,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Rajendra Nayak, Sai Prakash Ranjan, dhavalp, mturney, sparate,
c_rbokka, mkurumel
In-Reply-To: <CAD=FV=XbbUkeSwvcverBS8t6BCHuw3UT0_KYfx9LFGqmZyY2hA@mail.gmail.com>
On 21/05/2020 22:28, Doug Anderson wrote:
> Hi,
>
> On Thu, May 21, 2020 at 8:56 AM Srinivas Kandagatla
> <srinivas.kandagatla@linaro.org> wrote:
>>
>> On 21/05/2020 16:10, Doug Anderson wrote:
>>>> On 20/05/2020 23:48, Doug Anderson wrote:
>>>>>> Is this only applicable for corrected address space?
>>>>> I guess I was proposing a two dts-node / two drive approach here.
>>>>>
>>>>> dts node #1:just covers the memory range for accessing the FEC-corrected data
>>>>> driver #1: read-only and reads the FEC-corrected data
>>>>>
>>>>> dts node #2: covers the memory range that's_not_ the FEC-corrected
>>>>> memory range.
>>>>> driver #2: read-write. reading reads uncorrected data
>>>>>
>>>>> Does that seem sane?
>>>> I see your point but it does not make sense to have two node for same thing.
>>> OK, so that sounds as if we want to go with the proposal where we
>>> "deprecate the old driver and/or bindings and say that there really
>>> should just be one node and one driver".
>>>
>>> Would this be acceptable to you?
>>>
>>> 1. Officially mark the old bindings as deprecated.
>>
>> Possibly Yes for some reasons below!
>>
>>>
>>> 2. Leave the old driver there to support the old deprecated bindings,
>>> at least until everyone can be transferred over. There seem to be
>>> quite a few existing users of "qcom,qfprom" and we're supposed to make
>>> an attempt at keeping the old device trees working, at least for a
>>> little while. Once everyone is transferred over we could decide to
>>> delete the old driver.
>> we could consider "qcom,qfrom" to be only passing corrected address
>> space. Till we transition users to new bindings!
>>
>>>
>> Yes.
>>
>>> 3. We will have a totally new driver here.
>> No, we should still be using the same driver. But the exiting driver
>> seems to incorrect and is need of fixing.
>>
>> Having a look at the memory map for old SoCs like msm8996 and msm8916
>> shows that memory map that was passed to qfprom driver is corrected
>> address space. Writes will not obviously work!
>>
>> This should also be true with sdm845 or sc7180
>>
>> That needs to be fixed first!
>
> OK, so to summarize:
>
> 1. We will have one driver: "drivers/nvmem/qfprom.c"
Yes, we should one driver for this because we are dealing with exactly
same IP.
>
> 2. If the driver detects that its reg is pointing to the corrected
> address space then it should operate in read-only mode. Maybe it can
> do this based on the compatible string being just "qcom,qfprom" or
> maybe it can do this based on the size of the "reg".
I found out that there is a version register at offset of 0x6000 which
can give MAJOR, MINOR and STEP numbers.
So we could still potentially continue using "qcom,qfprom"
The address space can be split into 3 resources, which is inline with
Specs as well
1. Raw address space ("raw")
2. Configuration address space ("conf" or "core")
3. Corrected address space ("corrected")
Exiting qfprom entries or read-only qfprom will have "corrected"
address space which can be the only resource provided by device tree
entries.
Other two entries("raw" and "conf") are optional.
qfprom: qfprom@780000 {
compatible = "qcom,qfprom";
reg = <0 0x00780000 0 0x8ff>,
<0 0x00782000 0 0x100>,
<0 0x00784000 0 0x8ff>;
reg-names = "raw", "conf", "corrected";
vcc-supply = <&vreg_xyz>;
clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
clock-names = "secclk";
assigned-clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
assigned-clock-rates = <19200000>;
qcom,fuse-blow-frequency = <4800000>
#address-cells = <1>;
#size-cells = <1>;
qusb2p_hstx_trim: hstx-trim-primary@25b {
reg = <0x25b 0x1>;
bits = <1 3>;
};
};
Regarding clk rate setting, the default rate can be set using
assigned-clock-rates property, however the blow frequency can go as new
binding.
regarding voltage range for regulator, it should come as part of board
specific voltage regulator node. In worst case we can discuss on adding
new bindings for allowing specific range.
for Older SoCs: we still continue to use old style with just one
resource corresponding to corrected by default.
qfprom: qfprom@784000 {
compatible = "qcom,qfprom";
reg = <0 0x00784000 0 0x8ff>;
#address-cells = <1>;
#size-cells = <1>;
qusb2p_hstx_trim: hstx-trim-primary@1eb {
reg = <0x1eb 0x1>;
bits = <1 4>;
};
qusb2s_hstx_trim: hstx-trim-secondary@1eb {
reg = <0x1eb 0x2>;
bits = <6 4>;
};
};
I see the patch as adding write support to qfprom, rather than adding
new driver or new SoC support.
This in summary should give us good direction for this patch!
Correct me if I miss understood something here!
Thanks,
srini
>
> 3. If that driver sees a newer compatible string (one that includes
> the SoC name in it) it will assume that its "reg" points to the start
> of qfprom space.
>
> 4. We should post patches to transition all old dts files away from
> the deprecated bindings.
>
>
>>> 4. A given device tree will_not_ be allowed to have both
>>> "qcom,qfprom" specified and "qcom,SOC-qfprom" specified. ...and by
>>> "qcom,SOC-qfprom" I mean that SOC should be replaced by the SoC name,
>>> so "qcom,sc7180-qfprom" or "qcom,sdm845-qfprom". So once you switch
>>> to the new node it replaces the old node.
>>
>> Secondly, this IP is clearly an integral part of Secure Control Block,
>> which clearly has versioning information.
>>
>> Versioning information should be part of compatible string in msm8996 it
>> should be "qcom,qfprom-5.1.0"
>> for msm8916 it should be "qcom,qfprom-4.0.0" this translates to
>> "qcom,qfprom-<MAJOR-NUMBER>-<MINOR-NUMBER>-<STEP>"
>
> I don't know much about this versioning info, but I'm curious: can we
> read it from the chip? If so then it actually _doesn't_ need to be in
> the compatible string, I think. Device tree shouldn't include things
> that can be probed. So if this can be probed then maybe we could have
> the compatible as:
>
> compatible = "qcom,msm8996-qfprom", "qcom,qfprom"
>
> ...where the SoC is there just in case we need it but we'd expect to
> just match on "qcom,qfprom" and then probe.
>
>
> If this can't be probed then having the version info is nice, so then
> I guess you'd have the compatible string:
>
> compatible = "qcom,msm8996-qfprom", "qcom,qfprom-5.1.0"
>
> ...where (again) you'd have the SoC specific string there just in case
> but you'd expect that you could just use the generic string.
>
>
> Does that sound right?
>
>
>> Thirdly we should be able to have common read for all these as they tend
>> to just read from corrected address space.
>>
>> Offsets to corrected address space seems to always constant across SoCs too.
>>
>> platform specific device tree nodes should also be able to specify
>> "read-only" property to not allow writes on to this raw area.
>
> Yeah, I was thinking we probably wanted a read-only property. That
> sounds sane to me.
>
>
> -Doug
>
^ permalink raw reply
* Re: [PATCH v4 01/16] spi: dw: Add Tx/Rx finish wait methods to the MID DMA
From: Andy Shevchenko @ 2020-05-22 11:13 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Linus Walleij, Vinod Koul, Feng Tang, Grant Likely,
Alan Cox, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Rob Herring, linux-mips, devicetree,
Wan Ahmad Zainie, Thomas Gleixner, Jarkko Nikula, wuxu.wu,
Clement Leger, Linus Walleij, linux-spi, linux-kernel
In-Reply-To: <20200522000806.7381-2-Sergey.Semin@baikalelectronics.ru>
On Fri, May 22, 2020 at 03:07:50AM +0300, Serge Semin wrote:
> Since DMA transfers are performed asynchronously with actual SPI
> transaction, then even if DMA transfers are finished it doesn't mean
> all data is actually pushed to the SPI bus. Some data might still be
> in the controller FIFO. This is specifically true for Tx-only
> transfers. In this case if the next SPI transfer is recharged while
> a tail of the previous one is still in FIFO, we'll loose that tail
> data. In order to fix this lets add the wait procedure of the Tx/Rx
> SPI transfers completion after the corresponding DMA transactions
> are finished.
...
> Fixes: 7063c0d942a1 ("spi/dw_spi: add DMA support")
Usually we put this before any other tags.
> Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Rob Herring <robh+dt@kernel.org>
Are you sure Rob needs this to see?
You really need to shrink Cc lists of the patches to send them on common sense basis.
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
Ditto.
...
> Changelog v4:
> - Get back ndelay() method to wait for an SPI transfer completion.
> spi_delay_exec() isn't suitable for the atomic context.
OTOH we may teach spi_delay_exec() to perform atomic sleeps.
...
> + while (dw_spi_dma_tx_busy(dws) && retry--)
> + ndelay(ns);
I might be mistaken, but I think I told that this one misses to keep power
management in mind.
Have you read Documentation/process/volatile-considered-harmful.rst ?
...
> + while (dw_spi_dma_rx_busy(dws) && retry--)
> + ndelay(ns);
Ditto.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v4 12/16] spi: dw: Add DW SPI DMA/PCI/MMIO dependency on the DW SPI core
From: Andy Shevchenko @ 2020-05-22 11:08 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Rob Herring, linux-mips, devicetree, John Garry,
Chuanhong Guo, Joe Perches, Chris Packham, Tomer Maimon,
Masahisa Kojima, Krzysztof Kozlowski, linux-spi, linux-kernel
In-Reply-To: <20200522110738.GV1634618@smile.fi.intel.com>
On Fri, May 22, 2020 at 02:07:38PM +0300, Andy Shevchenko wrote:
> On Fri, May 22, 2020 at 03:08:01AM +0300, Serge Semin wrote:
> > Seeing all of the DW SPI driver components like DW SPI DMA/PCI/MMIO
> > depend on the DW SPI core code it's better to use the if-endif
> > conditional kernel config statement to signify that common dependency.
> >
> > Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> > Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> > Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> > Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> > Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> > Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> > Cc: Paul Burton <paulburton@kernel.org>
> > Cc: Ralf Baechle <ralf@linux-mips.org>
> > Cc: Arnd Bergmann <arnd@arndb.de>
>
> > Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>
> Here and for the future, when you add somebody's tag, drop their appearance in
> Cc. git-send-email automatically converts known tags to Cc.
*) here == in this entire series.
> > Cc: Rob Herring <robh+dt@kernel.org>
> > Cc: linux-mips@vger.kernel.org
> > Cc: devicetree@vger.kernel.org
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v4 12/16] spi: dw: Add DW SPI DMA/PCI/MMIO dependency on the DW SPI core
From: Andy Shevchenko @ 2020-05-22 11:07 UTC (permalink / raw)
To: Serge Semin
Cc: Mark Brown, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Rob Herring, linux-mips, devicetree, John Garry,
Chuanhong Guo, Joe Perches, Chris Packham, Tomer Maimon,
Masahisa Kojima, Krzysztof Kozlowski, linux-spi, linux-kernel
In-Reply-To: <20200522000806.7381-13-Sergey.Semin@baikalelectronics.ru>
On Fri, May 22, 2020 at 03:08:01AM +0300, Serge Semin wrote:
> Seeing all of the DW SPI driver components like DW SPI DMA/PCI/MMIO
> depend on the DW SPI core code it's better to use the if-endif
> conditional kernel config statement to signify that common dependency.
>
> Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
> Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Paul Burton <paulburton@kernel.org>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Here and for the future, when you add somebody's tag, drop their appearance in
Cc. git-send-email automatically converts known tags to Cc.
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox