* Re: [PATCH v5 00/11] mediatek: add support for MediaTek Ethernet MAC
From: David Miller @ 2020-05-22 21:36 UTC (permalink / raw)
To: matthias.bgg
Cc: brgl, robh+dt, john, sean.wang, Mark-MC.Lee, kuba, arnd, fparent,
hkallweit1, edwin.peer, devicetree, linux-kernel, netdev,
linux-arm-kernel, linux-mediatek, stephane.leprovost, pedro.tsai,
andrew.perepech, bgolaszewski
In-Reply-To: <1f941213-7ca2-c138-3530-85c34ebf0d53@gmail.com>
From: Matthias Brugger <matthias.bgg@gmail.com>
Date: Fri, 22 May 2020 23:31:50 +0200
>
>
> On 22/05/2020 23:20, David Miller wrote:
>> From: Bartosz Golaszewski <brgl@bgdev.pl>
>> Date: Fri, 22 May 2020 14:06:49 +0200
>>
>>> This series adds support for the STAR Ethernet Controller present on MediaTeK
>>> SoCs from the MT8* family.
>>
>> Series applied to net-next, thank you.
>>
>
> If you say "series applied" do you mean you also applied the device tree parts?
> These should go through my branch, because there could be conflicts if there are
> other device tree patches from other series, not related with network, touching
> the same files.
It's starting to get rediculous and tedious to manage the DT changes
when they are tied to new networking drivers and such.
And in any event, it is the patch series submitter's responsibility to
sort these issues out, separate the patches based upon target tree, and
clearly indicate this in the introductory posting and Subject lines.
^ permalink raw reply
* Re: [PATCH 0/5] net: provide a devres variant of register_netdev()
From: David Miller @ 2020-05-22 22:36 UTC (permalink / raw)
To: brgl
Cc: corbet, matthias.bgg, john, sean.wang, Mark-MC.Lee, kuba, arnd,
fparent, hkallweit1, edwin.peer, devicetree, linux-kernel, netdev,
linux-arm-kernel, linux-mediatek, stephane.leprovost, pedro.tsai,
andrew.perepech, bgolaszewski
In-Reply-To: <20200520114415.13041-1-brgl@bgdev.pl>
From: Bartosz Golaszewski <brgl@bgdev.pl>
Date: Wed, 20 May 2020 13:44:10 +0200
> net: ethernet: mtk_eth_mac: use devm_register_netdev()
This patch doesn't apply to net-next.
Neither the source file drivers/net/ethernet/mediatek/mtk_eth_mac.c,
nor the function mtk_mac_probe() even exist in the net-next GIT
tree.
^ permalink raw reply
* Re: [PATCH v10 5/5] MIPS: Loongson64: Switch to generic PCI driver
From: Thomas Bogendoerfer @ 2020-05-22 22:36 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Jiaxun Yang, linux-pci, Bjorn Helgaas, Rob Herring, Huacai Chen,
Paul Burton, devicetree, linux-kernel, linux-mips
In-Reply-To: <20200522152210.GA15567@e121166-lin.cambridge.arm.com>
On Fri, May 22, 2020 at 04:22:11PM +0100, Lorenzo Pieralisi wrote:
> On Fri, May 22, 2020 at 04:25:50PM +0200, Thomas Bogendoerfer wrote:
> > On Thu, May 14, 2020 at 09:16:41PM +0800, Jiaxun Yang wrote:
> > > We can now enable generic PCI driver in Kconfig, and remove legacy
> > > PCI driver code.
> > >
> > > Radeon vbios quirk is moved to the platform folder to fit the
> > > new structure.
> > >
> > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> > > --
> > > v9: Fix licenses tag
> > > ---
> > > arch/mips/Kconfig | 1 +
> > > arch/mips/loongson64/Makefile | 2 +-
> > > arch/mips/loongson64/vbios_quirk.c | 29 ++++++++
> > > arch/mips/pci/Makefile | 1 -
> > > arch/mips/pci/fixup-loongson3.c | 71 ------------------
> > > arch/mips/pci/ops-loongson3.c | 116 -----------------------------
> > > 6 files changed, 31 insertions(+), 189 deletions(-)
> > > create mode 100644 arch/mips/loongson64/vbios_quirk.c
> > > delete mode 100644 arch/mips/pci/fixup-loongson3.c
> > > delete mode 100644 arch/mips/pci/ops-loongson3.c
> >
> > Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
>
> This patch (so the series) does not apply to v5.7-rc1 which is our
> baseline. I reiterate the point, isn't it better to take the whole
> series through the MIPS tree ?
sounds better then
> Failing that, the series has to
> be rebased (or split differently so that it can be taken through
> different trees), just let me know.
so let's take via mips-next. So can I add your Acked-by to the
first three patches ?
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply
* Re: [PATCH v13 1/3] dt-bindings: i2c: npcm7xx: add NPCM I2C controller
From: Rob Herring @ 2020-05-22 22:42 UTC (permalink / raw)
To: Tali Perry
Cc: linux-kernel, devicetree, kfting, benjaminfair, avifishman70,
yuenn, andriy.shevchenko, openbmc, tmaimon77, linux-i2c,
linux-arm-kernel, wsa, brendanhiggins, robh+dt, venture, ofery
In-Reply-To: <20200522113312.181413-2-tali.perry1@gmail.com>
On Fri, 22 May 2020 14:33:10 +0300, Tali Perry wrote:
> Added device tree binding documentation for Nuvoton BMC
> NPCM I2C controller.
>
> Signed-off-by: Tali Perry <tali.perry1@gmail.com>
> ---
> .../bindings/i2c/nuvoton,npcm7xx-i2c.yaml | 60 +++++++++++++++++++
> 1 file changed, 60 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
Error: Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.example.dts:22.28-29 syntax error
FATAL ERROR: Unable to parse input tree
scripts/Makefile.lib:312: recipe for target 'Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.example.dt.yaml' failed
make[1]: *** [Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
Makefile:1300: recipe for target 'dt_binding_check' failed
make: *** [dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1296162
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:
pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
Please check and re-submit.
^ permalink raw reply
* Re: [PATCH v13 1/3] dt-bindings: i2c: npcm7xx: add NPCM I2C controller
From: Rob Herring @ 2020-05-22 22:47 UTC (permalink / raw)
To: Tali Perry
Cc: linux-kernel@vger.kernel.org, devicetree, kfting, Benjamin Fair,
Avi Fishman, Nancy Yuen, Andy Shevchenko, OpenBMC Maillist,
Tomer Maimon, Linux I2C,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Wolfram Sang, Brendan Higgins, Patrick Venture, Ofer Yehielli
In-Reply-To: <20200522224217.GA847856@bogus>
On Fri, May 22, 2020 at 4:42 PM Rob Herring <robh@kernel.org> wrote:
>
> On Fri, 22 May 2020 14:33:10 +0300, Tali Perry wrote:
> > Added device tree binding documentation for Nuvoton BMC
> > NPCM I2C controller.
> >
> > Signed-off-by: Tali Perry <tali.perry1@gmail.com>
> > ---
> > .../bindings/i2c/nuvoton,npcm7xx-i2c.yaml | 60 +++++++++++++++++++
> > 1 file changed, 60 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml
> >
>
>
> My bot found errors running 'make dt_binding_check' on your patch:
>
> Error: Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.example.dts:22.28-29 syntax error
> FATAL ERROR: Unable to parse input tree
> scripts/Makefile.lib:312: recipe for target 'Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.example.dt.yaml' failed
> make[1]: *** [Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.example.dt.yaml] Error 1
> make[1]: *** Waiting for unfinished jobs....
> Makefile:1300: recipe for target 'dt_binding_check' failed
> make: *** [dt_binding_check] Error 2
>
> See https://patchwork.ozlabs.org/patch/1296162
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure dt-schema is up to date:
>
> pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
>
> Please check and re-submit.
Why do you keep sending new versions with the same problem? It won't
get reviewed until this is fixed. This isn't a free automated service
to throw things at to see if they work. I have to review the failures.
Rob
^ permalink raw reply
* [Patch 1/2] dt-binbings: media: ti-vpe: Document the VIP driver
From: Benoit Parrot @ 2020-05-22 22:54 UTC (permalink / raw)
To: Hans Verkuil, Rob Herring
Cc: linux-media, devicetree, linux-kernel, Benoit Parrot
In-Reply-To: <20200522225412.29440-1-bparrot@ti.com>
Device Tree bindings for the Video Input Port (VIP) driver.
Signed-off-by: Benoit Parrot <bparrot@ti.com>
---
.../devicetree/bindings/media/ti,vip.yaml | 394 ++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 395 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/ti,vip.yaml
diff --git a/Documentation/devicetree/bindings/media/ti,vip.yaml b/Documentation/devicetree/bindings/media/ti,vip.yaml
new file mode 100644
index 000000000000..8a9084e42329
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/ti,vip.yaml
@@ -0,0 +1,394 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/ti,vip.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Texas Instruments DRA7x VIDEO INPUT PORT (VIP) Device Tree Bindings
+
+maintainers:
+ - Benoit Parrot <bparrot@ti.com>
+
+description: |-
+ The Video Input Port (VIP) is a key component for image capture
+ applications. The capture module provides the system interface and the
+ processing capability to connect parallel image-sensor as well as
+ BT.656/1120 capable encoder chip to DRA7x device.
+
+ Each VIP instance supports 2 independently configurable external video
+ input capture slices (Slice 0 and Slice 1) each providing up to two video
+ input ports (Port A and Port B) where Port A can be configured as
+ 24/16/8-bit port and Port B is fixed as 8-bit port.
+ Here these ports a represented as follows
+ port@0 -> Slice 0 Port A
+ port@1 -> Slice 0 Port B
+ port@2 -> Slice 1 Port A
+ port@3 -> Slice 1 Port B
+
+ Each camera port nodes should contain a 'port' child node with child
+ 'endpoint' node. Please refer to the bindings defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+properties:
+ compatible:
+ const: ti,dra7-vip
+
+ label:
+ description: Instance name
+
+ reg:
+ items:
+ - description: The VIP main register region
+ - description: Video Data Parser (PARSER) register region for Slice0
+ - description: Color Space Conversion (CSC) register region for Slice0
+ - description: Scaler (SC) register region for Slice0
+ - description: Video Data Parser (PARSER) register region for Slice1
+ - description: Color Space Conversion (CSC) register region for Slice1
+ - description: Scaler (SC) register region for Slice1
+ - description: Video Port Direct Memory Access (VPDMA) register region
+
+ reg-names:
+ items:
+ - const: vip
+ - const: parser0
+ - const: csc0
+ - const: sc0
+ - const: parser1
+ - const: csc1
+ - const: sc1
+ - const: vpdma
+
+ interrupts:
+ minItems: 2
+ description:
+ IRQ index 0 is used for Slice0 interrupts
+ IRQ index 1 is used for Slice1 interrupts
+
+ ti,vip-clk-polarity:
+ $ref: "/schemas/types.yaml#/definitions/phandle-array"
+ description:
+ phandle to the device control module. The 1st argument should
+ contain the register offset to the CTRL_CORE_SMA_SW_1 register.
+ 2nd argument contains the bit field to slice 0 port A,
+ 3rd argument contains the bit field to slice 0 port B,
+ 4th argument contains the bit field to slice 1 port A,
+ 5th argument contains the bit field to slice 1 port B.
+
+ # See ./video-interfaces.txt for details
+ ports:
+ type: object
+ additionalProperties: false
+
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ port@0:
+ type: object
+ additionalProperties: false
+
+ properties:
+ reg:
+ const: 0
+ description: Slice 0 Port A
+
+ label:
+ description: Port name. Usually the pin group name
+
+ patternProperties:
+ endpoint:
+ type: object
+ additionalProperties: false
+
+ properties:
+ hsync-active:
+ maxItems: 1
+
+ vsync-active:
+ maxItems: 1
+
+ pclk-sample:
+ maxItems: 1
+
+ bus-width:
+ maxItems: 1
+
+ ti,vip-pixel-mux:
+ type: boolean
+ description:
+ In BT656/1120 mode, this enable pixel-muxing if
+ the number of channels is either 1, 2 or 4. If this
+ property is present then pixel-muxing is enabled
+ otherwise it will use line-muxing.
+
+ ti,vip-channels:
+ $ref: "/schemas/types.yaml#definitions/uint8-array"
+ minItems: 1
+ maxItems: 16
+ description: |-
+ In BT656/1120 mode, list of channel ids to be captured.
+ If the property is not present then 1 channel is assumed.
+
+ remote-endpoint: true
+
+ required:
+ - reg
+ - label
+
+ port@1:
+ type: object
+ additionalProperties: false
+
+ properties:
+ reg:
+ const: 1
+ description: Slice 0 Port B
+
+ label:
+ description: Port name. Usually the pin group name
+
+ patternProperties:
+ endpoint:
+ type: object
+ additionalProperties: false
+
+ properties:
+ hsync-active:
+ maxItems: 1
+
+ vsync-active:
+ maxItems: 1
+
+ pclk-sample:
+ maxItems: 1
+
+ bus-width:
+ maxItems: 1
+
+ ti,vip-pixel-mux:
+ type: boolean
+ description:
+ In BT656/1120 mode, this enable pixel-muxing if
+ the number of channels is either 1, 2 or 4. If this
+ property is present then pixel-muxing is enabled
+ otherwise it will use line-muxing.
+
+ ti,vip-channels:
+ $ref: "/schemas/types.yaml#definitions/uint8-array"
+ minItems: 1
+ maxItems: 16
+ description:
+ In BT656/1120 mode, list of channel ids to be captured.
+ If the property is not present then 1 channel is assumed.
+
+ remote-endpoint: true
+
+ required:
+ - reg
+ - label
+
+ port@2:
+ type: object
+ additionalProperties: false
+
+ properties:
+ reg:
+ const: 2
+ description: Slice 1 Port A
+
+ label:
+ description: Port name. Usually the pin group name
+
+ patternProperties:
+ endpoint:
+ type: object
+ additionalProperties: false
+
+ properties:
+ hsync-active:
+ maxItems: 1
+
+ vsync-active:
+ maxItems: 1
+
+ pclk-sample:
+ maxItems: 1
+
+ bus-width:
+ maxItems: 1
+
+ ti,vip-pixel-mux:
+ type: boolean
+ description:
+ In BT656/1120 mode, this enable pixel-muxing if
+ the number of channels is either 1, 2 or 4. If this
+ property is present then pixel-muxing is enabled
+ otherwise it will use line-muxing.
+
+ ti,vip-channels:
+ $ref: "/schemas/types.yaml#definitions/uint8-array"
+ minItems: 1
+ maxItems: 16
+ description:
+ In BT656/1120 mode, list of channel ids to be captured.
+ If the property is not present then 1 channel is assumed.
+
+ remote-endpoint: true
+
+ required:
+ - reg
+ - label
+
+ port@3:
+ type: object
+ additionalProperties: false
+
+ properties:
+ reg:
+ const: 3
+ description: Slice 1 Port B
+
+ label:
+ description: Port name. Usually the pin group name
+
+ patternProperties:
+ endpoint:
+ type: object
+ additionalProperties: false
+
+ properties:
+ hsync-active:
+ maxItems: 1
+
+ vsync-active:
+ maxItems: 1
+
+ pclk-sample:
+ maxItems: 1
+
+ bus-width:
+ maxItems: 1
+
+ ti,vip-pixel-mux:
+ type: boolean
+ description:
+ In BT656/1120 mode, this enable pixel-muxing if
+ the number of channels is either 1, 2 or 4. If this
+ property is present then pixel-muxing is enabled
+ otherwise it will use line-muxing.
+
+ ti,vip-channels:
+ $ref: "/schemas/types.yaml#definitions/uint8-array"
+ minItems: 1
+ maxItems: 16
+ description:
+ In BT656/1120 mode, list of channel ids to be captured.
+ If the property is not present then 1 channel is assumed.
+
+ remote-endpoint: true
+
+ required:
+ - reg
+ - label
+
+ required:
+ - "#address-cells"
+ - "#size-cells"
+ - port@0
+
+required:
+ - compatible
+ - label
+ - reg
+ - reg-names
+ - interrupts
+ - ti,vip-clk-polarity
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ vip1: vip@48970000 {
+ compatible = "ti,dra7-vip";
+ label = "vip1";
+ reg = <0x48970000 0x114>,
+ <0x48975500 0xD8>,
+ <0x48975700 0x18>,
+ <0x48975800 0x80>,
+ <0x48975a00 0xD8>,
+ <0x48975c00 0x18>,
+ <0x48975d00 0x80>,
+ <0x4897d000 0x400>;
+ reg-names = "vip",
+ "parser0",
+ "csc0",
+ "sc0",
+ "parser1",
+ "csc1",
+ "sc1",
+ "vpdma";
+ interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
+ ti,vip-clk-polarity = <&scm_conf 0x534 0x1 0x4 0x2 0x8>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vin1a: port@0 {
+ reg = <0>;
+ label = "vin1a";
+
+ vin1a_ep: endpoint {
+ remote-endpoint = <&camera1>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ pclk-sample = <0>;
+ bus-width = <8>;
+ };
+ };
+ vin1b: port@1 {
+ reg = <1>;
+ label = "vin1b";
+ };
+ vin2a: port@2 {
+ reg = <2>;
+ label = "vin2a";
+ };
+ vin2b: port@3 {
+ reg = <3>;
+ label = "vin2b";
+ };
+ };
+ };
+
+ i2c {
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ camera@37 {
+ compatible = "ovti,ov10633";
+ reg = <0x37>;
+
+ clocks = <&fixed_clock>;
+ clocks-names = "xvclk";
+
+ port {
+ camera1: endpoint {
+ remote-endpoint = <&vin1a_ep>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ pclk-sample = <0>;
+ bus-width = <8>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 2e9a5f6e4ff7..06856d05b53b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16947,6 +16947,7 @@ S: Maintained
W: http://linuxtv.org/
Q: http://patchwork.linuxtv.org/project/linux-media/list/
F: Documentation/devicetree/bindings/media/ti,cal.yaml
+F: Documentation/devicetree/bindings/media/ti,vip.yaml
F: Documentation/devicetree/bindings/media/ti,vpe.yaml
F: drivers/media/platform/ti-vpe/
--
2.17.1
^ permalink raw reply related
* [Patch 2/2] media: ti-vpe: Add the VIP driver
From: Benoit Parrot @ 2020-05-22 22:54 UTC (permalink / raw)
To: Hans Verkuil, Rob Herring
Cc: linux-media, devicetree, linux-kernel, Benoit Parrot,
Nikhil Devshatwar
In-Reply-To: <20200522225412.29440-1-bparrot@ti.com>
VIP stands for Video Input Port, it can be found on devices such as
DRA7xx and provides a parallel interface to a video source such as
a sensor or TV decoder. Each VIP can support two inputs (slices) and
a SoC can be configured with a variable number of VIP's.
Each slice can supports two ports each connected to its own
sub-device.
Signed-off-by: Benoit Parrot <bparrot@ti.com>
Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
---
drivers/media/platform/Kconfig | 13 +
drivers/media/platform/ti-vpe/Makefile | 2 +
drivers/media/platform/ti-vpe/vip.c | 4158 ++++++++++++++++++++++++
drivers/media/platform/ti-vpe/vip.h | 724 +++++
4 files changed, 4897 insertions(+)
create mode 100644 drivers/media/platform/ti-vpe/vip.c
create mode 100644 drivers/media/platform/ti-vpe/vip.h
diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index c57ee78fa99d..f4100a1aad58 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -168,6 +168,19 @@ config VIDEO_TI_CAL
In TI Technical Reference Manual this module is referred as
Camera Interface Subsystem (CAMSS).
+config VIDEO_TI_VIP
+ tristate "TI Video Input Port"
+ default n
+ depends on VIDEO_DEV && VIDEO_V4L2 && SOC_DRA7XX
+ depends on HAS_DMA
+ select VIDEOBUF2_DMA_CONTIG
+ select VIDEO_TI_VPDMA
+ select VIDEO_TI_SC
+ select VIDEO_TI_CSC
+ help
+ Driver support for VIP module on certain TI SoC's
+ VIP = Video Input Port.
+
endif # V4L_PLATFORM_DRIVERS
menuconfig V4L_MEM2MEM_DRIVERS
diff --git a/drivers/media/platform/ti-vpe/Makefile b/drivers/media/platform/ti-vpe/Makefile
index 886ac5ec073f..cdbecadf7191 100644
--- a/drivers/media/platform/ti-vpe/Makefile
+++ b/drivers/media/platform/ti-vpe/Makefile
@@ -3,11 +3,13 @@ obj-$(CONFIG_VIDEO_TI_VPE) += ti-vpe.o
obj-$(CONFIG_VIDEO_TI_VPDMA) += ti-vpdma.o
obj-$(CONFIG_VIDEO_TI_SC) += ti-sc.o
obj-$(CONFIG_VIDEO_TI_CSC) += ti-csc.o
+obj-$(CONFIG_VIDEO_TI_VIP) += ti-vip.o
ti-vpe-y := vpe.o
ti-vpdma-y := vpdma.o
ti-sc-y := sc.o
ti-csc-y := csc.o
+ti-vip-y := vip.o
ccflags-$(CONFIG_VIDEO_TI_VPE_DEBUG) += -DDEBUG
diff --git a/drivers/media/platform/ti-vpe/vip.c b/drivers/media/platform/ti-vpe/vip.c
new file mode 100644
index 000000000000..307b01851a14
--- /dev/null
+++ b/drivers/media/platform/ti-vpe/vip.c
@@ -0,0 +1,4158 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TI VIP capture driver
+ *
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ * David Griego, <dagriego@biglakesoftware.com>
+ * Dale Farnsworth, <dale@farnsworth.org>
+ * Nikhil Devshatwar, <nikhil.nd@ti.com>
+ * Benoit Parrot, <bparrot@ti.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/workqueue.h>
+#include <linux/pm_runtime.h>
+#include <linux/sched.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+
+#include <linux/pinctrl/consumer.h>
+#include <linux/of_device.h>
+#include <linux/of_graph.h>
+
+#include "vip.h"
+
+#define VIP_MODULE_NAME "vip"
+
+static int debug;
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "debug level (0-8)");
+
+/*
+ * Minimum and maximum frame sizes
+ */
+#define MIN_W 128
+#define MIN_H 128
+#define MAX_W 2048
+#define MAX_H 1536
+
+/*
+ * Required alignments
+ */
+#define S_ALIGN 0 /* multiple of 1 */
+#define H_ALIGN 1 /* multiple of 2 */
+#define W_ALIGN 1 /* multiple of 2 */
+#define L_ALIGN 7 /* multiple of 128, line stride, 16 bytes */
+
+/*
+ * Need a descriptor entry for each of up to 15 outputs,
+ * and up to 2 control transfers.
+ */
+#define VIP_DESC_LIST_SIZE (17 * sizeof(struct vpdma_dtd))
+
+#define vip_dbg(level, dev, fmt, arg...) \
+ v4l2_dbg(level, debug, dev, fmt, ##arg)
+#define vip_err(dev, fmt, arg...) \
+ v4l2_err(dev, fmt, ##arg)
+#define vip_warn(dev, fmt, arg...) \
+ v4l2_err(dev, fmt, ##arg)
+#define vip_info(dev, fmt, arg...) \
+ v4l2_info(dev, fmt, ##arg)
+
+#define CTRL_CORE_SMA_SW_1 0x534
+/*
+ * The srce_info structure contains per-srce data.
+ */
+struct vip_srce_info {
+ u8 base_channel; /* the VPDMA channel nummber */
+ u8 vb_index; /* input frame f, f-1, f-2 index */
+ u8 vb_part; /* identifies section of co-planar formats */
+};
+
+#define VIP_VPDMA_FIFO_SIZE 2
+#define VIP_DROPQ_SIZE 3
+
+/*
+ * Define indices into the srce_info tables
+ */
+
+#define VIP_SRCE_MULT_PORT 0
+#define VIP_SRCE_MULT_ANC 1
+#define VIP_SRCE_LUMA 2
+#define VIP_SRCE_CHROMA 3
+#define VIP_SRCE_RGB 4
+
+static struct vip_srce_info srce_info[5] = {
+ [VIP_SRCE_MULT_PORT] = {
+ .base_channel = VIP1_CHAN_NUM_MULT_PORT_A_SRC0,
+ .vb_index = 0,
+ .vb_part = VIP_CHROMA,
+ },
+ [VIP_SRCE_MULT_ANC] = {
+ .base_channel = VIP1_CHAN_NUM_MULT_ANC_A_SRC0,
+ .vb_index = 0,
+ .vb_part = VIP_LUMA,
+ },
+ [VIP_SRCE_LUMA] = {
+ .base_channel = VIP1_CHAN_NUM_PORT_A_LUMA,
+ .vb_index = 1,
+ .vb_part = VIP_LUMA,
+ },
+ [VIP_SRCE_CHROMA] = {
+ .base_channel = VIP1_CHAN_NUM_PORT_A_CHROMA,
+ .vb_index = 1,
+ .vb_part = VIP_CHROMA,
+ },
+ [VIP_SRCE_RGB] = {
+ .base_channel = VIP1_CHAN_NUM_PORT_A_RGB,
+ .vb_part = VIP_LUMA,
+ },
+};
+
+static struct vip_fmt vip_formats[VIP_MAX_ACTIVE_FMT] = {
+ {
+ .fourcc = V4L2_PIX_FMT_NV12,
+ .code = MEDIA_BUS_FMT_UYVY8_2X8,
+ .colorspace = V4L2_COLORSPACE_SMPTE170M,
+ .coplanar = 1,
+ .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y420],
+ &vpdma_yuv_fmts[VPDMA_DATA_FMT_C420],
+ },
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_UYVY,
+ .code = MEDIA_BUS_FMT_UYVY8_2X8,
+ .colorspace = V4L2_COLORSPACE_SMPTE170M,
+ .coplanar = 0,
+ .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_CBY422],
+ },
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_YUYV,
+ .code = MEDIA_BUS_FMT_UYVY8_2X8,
+ .colorspace = V4L2_COLORSPACE_SMPTE170M,
+ .coplanar = 0,
+ .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_YCB422],
+ },
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_VYUY,
+ .code = MEDIA_BUS_FMT_UYVY8_2X8,
+ .colorspace = V4L2_COLORSPACE_SMPTE170M,
+ .coplanar = 0,
+ .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_CRY422],
+ },
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_YVYU,
+ .code = MEDIA_BUS_FMT_UYVY8_2X8,
+ .colorspace = V4L2_COLORSPACE_SMPTE170M,
+ .coplanar = 0,
+ .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_YCR422],
+ },
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_RGB24,
+ .code = MEDIA_BUS_FMT_UYVY8_2X8,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ .coplanar = 0,
+ .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB24],
+ },
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_RGB32,
+ .code = MEDIA_BUS_FMT_UYVY8_2X8,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ .coplanar = 0,
+ .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ARGB32],
+ },
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_BGR24,
+ .code = MEDIA_BUS_FMT_UYVY8_2X8,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ .coplanar = 0,
+ .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_BGR24],
+ },
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_BGR32,
+ .code = MEDIA_BUS_FMT_UYVY8_2X8,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ .coplanar = 0,
+ .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ABGR32],
+ },
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_RGB24,
+ .code = MEDIA_BUS_FMT_RGB888_1X24,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ .coplanar = 0,
+ .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB24],
+ },
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_RGB32,
+ .code = MEDIA_BUS_FMT_ARGB8888_1X32,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ .coplanar = 0,
+ .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ARGB32],
+ },
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_SBGGR8,
+ .code = MEDIA_BUS_FMT_SBGGR8_1X8,
+ .colorspace = V4L2_COLORSPACE_SMPTE170M,
+ .coplanar = 0,
+ .vpdma_fmt = { &vpdma_raw_fmts[VPDMA_DATA_FMT_RAW8],
+ },
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_SGBRG8,
+ .code = MEDIA_BUS_FMT_SGBRG8_1X8,
+ .colorspace = V4L2_COLORSPACE_SMPTE170M,
+ .coplanar = 0,
+ .vpdma_fmt = { &vpdma_raw_fmts[VPDMA_DATA_FMT_RAW8],
+ },
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_SGRBG8,
+ .code = MEDIA_BUS_FMT_SGRBG8_1X8,
+ .colorspace = V4L2_COLORSPACE_SMPTE170M,
+ .coplanar = 0,
+ .vpdma_fmt = { &vpdma_raw_fmts[VPDMA_DATA_FMT_RAW8],
+ },
+ },
+ {
+ .fourcc = V4L2_PIX_FMT_SRGGB8,
+ .code = MEDIA_BUS_FMT_SRGGB8_1X8,
+ .colorspace = V4L2_COLORSPACE_SMPTE170M,
+ .coplanar = 0,
+ .vpdma_fmt = { &vpdma_raw_fmts[VPDMA_DATA_FMT_RAW8],
+ },
+ },
+ {
+ /* V4L2 currently only defines one 16 bit variant */
+ .fourcc = V4L2_PIX_FMT_SBGGR16,
+ .code = MEDIA_BUS_FMT_SBGGR16_1X16,
+ .colorspace = V4L2_COLORSPACE_SMPTE170M,
+ .coplanar = 0,
+ .vpdma_fmt = { &vpdma_raw_fmts[VPDMA_DATA_FMT_RAW16],
+ },
+ },
+};
+
+/* initialize v4l2_format_info member in vip_formats array */
+static void vip_init_format_info(struct device *dev)
+{
+ struct vip_fmt *fmt;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(vip_formats); i++) {
+ fmt = &vip_formats[i];
+ fmt->finfo = v4l2_format_info(fmt->fourcc);
+ }
+}
+
+/* Print Four-character-code (FOURCC) */
+static char *fourcc_to_str(u32 fmt)
+{
+ static char code[5];
+
+ code[0] = (unsigned char)(fmt & 0xff);
+ code[1] = (unsigned char)((fmt >> 8) & 0xff);
+ code[2] = (unsigned char)((fmt >> 16) & 0xff);
+ code[3] = (unsigned char)((fmt >> 24) & 0xff);
+ code[4] = '\0';
+
+ return code;
+}
+
+/*
+ * Find our format description corresponding to the passed v4l2_format
+ */
+
+static struct vip_fmt *find_port_format_by_pix(struct vip_port *port,
+ u32 pixelformat)
+{
+ struct vip_fmt *fmt;
+ unsigned int k;
+
+ for (k = 0; k < port->num_active_fmt; k++) {
+ fmt = port->active_fmt[k];
+ if (fmt->fourcc == pixelformat)
+ return fmt;
+ }
+
+ return NULL;
+}
+
+static struct vip_fmt *find_port_format_by_code(struct vip_port *port,
+ u32 code)
+{
+ struct vip_fmt *fmt;
+ unsigned int k;
+
+ for (k = 0; k < port->num_active_fmt; k++) {
+ fmt = port->active_fmt[k];
+ if (fmt->code == code)
+ return fmt;
+ }
+
+ return NULL;
+}
+
+static int vip_find_pad(struct v4l2_subdev *sd, int direction)
+{
+ unsigned int pad;
+
+ if (sd->entity.num_pads <= 1)
+ return 0;
+
+ for (pad = 0; pad < sd->entity.num_pads; pad++)
+ if (sd->entity.pads[pad].flags & direction)
+ return pad;
+
+ return -EINVAL;
+}
+
+inline struct vip_port *notifier_to_vip_port(struct v4l2_async_notifier *n)
+{
+ return container_of(n, struct vip_port, notifier);
+}
+
+static bool vip_is_mbuscode_yuv(u32 code)
+{
+ return ((code & 0xFF00) == 0x2000);
+}
+
+static bool vip_is_mbuscode_rgb(u32 code)
+{
+ return ((code & 0xFF00) == 0x1000);
+}
+
+static bool vip_is_mbuscode_raw(u32 code)
+{
+ return ((code & 0xFF00) == 0x3000);
+}
+
+/*
+ * This is not an accurate conversion but it is only used to
+ * assess if color conversion is needed.
+ */
+static u32 vip_mbus_code_to_fourcc(u32 code)
+{
+ if (vip_is_mbuscode_rgb(code))
+ return V4L2_PIX_FMT_RGB24;
+
+ if (vip_is_mbuscode_yuv(code))
+ return V4L2_PIX_FMT_UYVY;
+
+ return V4L2_PIX_FMT_SBGGR8;
+}
+
+static enum vip_csc_state
+vip_csc_direction(u32 src_code, const struct v4l2_format_info *dfinfo)
+{
+ if (vip_is_mbuscode_yuv(src_code) && v4l2_is_format_rgb(dfinfo))
+ return VIP_CSC_Y2R;
+ else if (vip_is_mbuscode_rgb(src_code) && v4l2_is_format_yuv(dfinfo))
+ return VIP_CSC_R2Y;
+ else
+ return VIP_CSC_NA;
+}
+
+/*
+ * port flag bits
+ */
+#define FLAG_FRAME_1D BIT(0)
+#define FLAG_EVEN_LINE_SKIP BIT(1)
+#define FLAG_ODD_LINE_SKIP BIT(2)
+#define FLAG_MODE_TILED BIT(3)
+#define FLAG_INTERLACED BIT(4)
+#define FLAG_MULTIPLEXED BIT(5)
+#define FLAG_MULT_PORT BIT(6)
+#define FLAG_MULT_ANC BIT(7)
+
+/*
+ * Function prototype declarations
+ */
+static int alloc_port(struct vip_dev *, int, const char *);
+static void free_port(struct vip_port *);
+static int vip_setup_parser(struct vip_port *port);
+static int vip_setup_scaler(struct vip_stream *stream);
+static void vip_enable_parser(struct vip_port *port, bool on);
+static void vip_reset_parser(struct vip_port *port, bool on);
+static void vip_parser_stop_imm(struct vip_port *port, bool on);
+static void stop_dma(struct vip_stream *stream, bool clear_list);
+static int vip_load_vpdma_list_fifo(struct vip_stream *stream);
+static inline bool is_scaler_available(struct vip_port *port);
+static inline bool allocate_scaler(struct vip_port *port);
+static inline void free_scaler(struct vip_port *port);
+static bool is_csc_available(struct vip_port *port);
+static bool allocate_csc(struct vip_port *port,
+ enum vip_csc_state csc_direction);
+static void free_csc(struct vip_port *port);
+
+#define reg_read(dev, offset) ioread32(dev->base + offset)
+#define reg_write(dev, offset, val) iowrite32(val, dev->base + offset)
+
+/*
+ * Insert a masked field into a 32-bit field
+ */
+static void insert_field(u32 *valp, u32 field, u32 mask, int shift)
+{
+ u32 val = *valp;
+
+ val &= ~(mask << shift);
+ val |= (field & mask) << shift;
+ *valp = val;
+}
+
+/*
+ * DMA address/data block for the shadow registers
+ */
+struct vip_mmr_adb {
+ struct vpdma_adb_hdr sc_hdr0;
+ u32 sc_regs0[7];
+ u32 sc_pad0[1];
+ struct vpdma_adb_hdr sc_hdr8;
+ u32 sc_regs8[6];
+ u32 sc_pad8[2];
+ struct vpdma_adb_hdr sc_hdr17;
+ u32 sc_regs17[9];
+ u32 sc_pad17[3];
+ struct vpdma_adb_hdr csc_hdr;
+ u32 csc_regs[6];
+ u32 csc_pad[2];
+};
+
+#define GET_OFFSET_TOP(port, obj, reg) \
+ ((obj)->res->start - port->dev->res->start + reg)
+
+#define VIP_SET_MMR_ADB_HDR(port, hdr, regs, offset_a) \
+ VPDMA_SET_MMR_ADB_HDR(port->mmr_adb, vip_mmr_adb, hdr, regs, offset_a)
+
+/*
+ * Set the headers for all of the address/data block structures.
+ */
+static void init_adb_hdrs(struct vip_port *port)
+{
+ VIP_SET_MMR_ADB_HDR(port, sc_hdr0, sc_regs0,
+ GET_OFFSET_TOP(port, port->dev->sc, CFG_SC0));
+ VIP_SET_MMR_ADB_HDR(port, sc_hdr8, sc_regs8,
+ GET_OFFSET_TOP(port, port->dev->sc, CFG_SC8));
+ VIP_SET_MMR_ADB_HDR(port, sc_hdr17, sc_regs17,
+ GET_OFFSET_TOP(port, port->dev->sc, CFG_SC17));
+ VIP_SET_MMR_ADB_HDR(port, csc_hdr, csc_regs,
+ GET_OFFSET_TOP(port, port->dev->csc, CSC_CSC00));
+
+};
+
+/*
+ * These represent the module resets bit for slice 1
+ * Upon detecting slice2 we simply left shift by 1
+ */
+#define VIP_DP_RST BIT(16)
+#define VIP_PARSER_RST BIT(18)
+#define VIP_CSC_RST BIT(20)
+#define VIP_SC_RST BIT(22)
+#define VIP_DS0_RST BIT(25)
+#define VIP_DS1_RST BIT(27)
+
+static void vip_module_reset(struct vip_dev *dev, uint32_t module, bool on)
+{
+ u32 val = 0;
+
+ val = reg_read(dev, VIP_CLK_RESET);
+
+ if (dev->slice_id == VIP_SLICE2)
+ module <<= 1;
+
+ if (on)
+ val |= module;
+ else
+ val &= ~module;
+
+ reg_write(dev, VIP_CLK_RESET, val);
+}
+
+/*
+ * Enable or disable the VIP clocks
+ */
+static void vip_set_clock_enable(struct vip_dev *dev, bool on)
+{
+ u32 val = 0;
+
+ val = reg_read(dev, VIP_CLK_ENABLE);
+ if (on) {
+ val |= VIP_VPDMA_CLK_ENABLE;
+ if (dev->slice_id == VIP_SLICE1)
+ val |= VIP_VIP1_DATA_PATH_CLK_ENABLE;
+ else
+ val |= VIP_VIP2_DATA_PATH_CLK_ENABLE;
+ } else {
+ if (dev->slice_id == VIP_SLICE1)
+ val &= ~VIP_VIP1_DATA_PATH_CLK_ENABLE;
+ else
+ val &= ~VIP_VIP2_DATA_PATH_CLK_ENABLE;
+
+ /* Both VIP are disabled then shutdown VPDMA also */
+ if (!(val & (VIP_VIP1_DATA_PATH_CLK_ENABLE |
+ VIP_VIP2_DATA_PATH_CLK_ENABLE)))
+ val = 0;
+ }
+
+ reg_write(dev, VIP_CLK_ENABLE, val);
+}
+
+/* This helper function is used to enable the clock early on to
+ * enable vpdma firmware loading before the slice device are created
+ */
+static void vip_shared_set_clock_enable(struct vip_shared *shared, bool on)
+{
+ u32 val = 0;
+
+ if (on)
+ val = VIP_VIP1_DATA_PATH_CLK_ENABLE | VIP_VPDMA_CLK_ENABLE;
+
+ reg_write(shared, VIP_CLK_ENABLE, val);
+}
+
+static void vip_top_reset(struct vip_dev *dev)
+{
+ u32 val = 0;
+
+ val = reg_read(dev, VIP_CLK_RESET);
+
+ if (dev->slice_id == VIP_SLICE1)
+ insert_field(&val, 1, VIP_DATA_PATH_CLK_RESET_MASK,
+ VIP_VIP1_DATA_PATH_RESET_SHIFT);
+ else
+ insert_field(&val, 1, VIP_DATA_PATH_CLK_RESET_MASK,
+ VIP_VIP2_DATA_PATH_RESET_SHIFT);
+
+ reg_write(dev, VIP_CLK_RESET, val);
+
+ usleep_range(200, 250);
+
+ val = reg_read(dev, VIP_CLK_RESET);
+
+ if (dev->slice_id == VIP_SLICE1)
+ insert_field(&val, 0, VIP_DATA_PATH_CLK_RESET_MASK,
+ VIP_VIP1_DATA_PATH_RESET_SHIFT);
+ else
+ insert_field(&val, 0, VIP_DATA_PATH_CLK_RESET_MASK,
+ VIP_VIP2_DATA_PATH_RESET_SHIFT);
+ reg_write(dev, VIP_CLK_RESET, val);
+}
+
+static void vip_top_vpdma_reset(struct vip_shared *shared)
+{
+ u32 val;
+
+ val = reg_read(shared, VIP_CLK_RESET);
+ insert_field(&val, 1, VIP_VPDMA_CLK_RESET_MASK,
+ VIP_VPDMA_CLK_RESET_SHIFT);
+ reg_write(shared, VIP_CLK_RESET, val);
+
+ usleep_range(200, 250);
+
+ val = reg_read(shared, VIP_CLK_RESET);
+ insert_field(&val, 0, VIP_VPDMA_CLK_RESET_MASK,
+ VIP_VPDMA_CLK_RESET_SHIFT);
+ reg_write(shared, VIP_CLK_RESET, val);
+}
+
+static void vip_set_pclk_invert(struct vip_port *port)
+{
+ struct vip_clk_polarity *pclk = port->dev->pclk_pol;
+ u32 index;
+
+ /*
+ * When the VIP parser is configured to so that the pixel clock
+ * is to be sampled at falling edge, the pixel clock needs to be
+ * inverted before it is given to the VIP module. This is done
+ * by setting a bit in the CTRL_CORE_SMA_SW1 register.
+ */
+
+ index = 2 * port->dev->slice_id + port->port_id;
+ vip_dbg(3, port, "%s: slice%d:port%d -> index: %d\n", __func__,
+ port->dev->slice_id, port->port_id, index);
+
+ if (pclk->rm_pol)
+ regmap_update_bits(pclk->rm_pol,
+ pclk->rm_offset,
+ pclk->rm_bit_field[index],
+ pclk->rm_bit_field[index]);
+}
+
+static void vip_clr_pclk_invert(struct vip_port *port)
+{
+ struct vip_clk_polarity *pclk = port->dev->pclk_pol;
+ u32 index;
+
+ index = 2 * port->dev->slice_id + port->port_id;
+ vip_dbg(3, port, "%s: slice%d:port%d -> index: %d\n", __func__,
+ port->dev->slice_id, port->port_id, index);
+
+ if (pclk->rm_pol)
+ regmap_update_bits(pclk->rm_pol, pclk->rm_offset,
+ pclk->rm_bit_field[index], 0);
+}
+
+#define VIP_PARSER_PORT(p) (VIP_PARSER_PORTA_0 + (p * 0x8U))
+#define VIP_PARSER_EXTRA_PORT(p) (VIP_PARSER_PORTA_1 + (p * 0x8U))
+#define VIP_PARSER_CROP_H_PORT(p) (VIP_PARSER_PORTA_EXTRA4 + (p * 0x10U))
+#define VIP_PARSER_CROP_V_PORT(p) (VIP_PARSER_PORTA_EXTRA5 + (p * 0x10U))
+#define VIP_PARSER_STOP_IMM_PORT(p) (VIP_PARSER_PORTA_EXTRA6 + (p * 0x4U))
+
+static void vip_set_data_interface(struct vip_port *port,
+ enum data_interface_modes mode)
+{
+ u32 val = 0;
+
+ insert_field(&val, mode, VIP_DATA_INTERFACE_MODE_MASK,
+ VIP_DATA_INTERFACE_MODE_SHFT);
+
+ reg_write(port->dev->parser, VIP_PARSER_MAIN_CFG, val);
+}
+
+static void vip_set_slice_path(struct vip_dev *dev,
+ enum data_path_select data_path, u32 path_val)
+{
+ u32 val = 0;
+ int data_path_reg;
+
+ vip_dbg(3, dev, "%s:\n", __func__);
+
+ data_path_reg = VIP_VIP1_DATA_PATH_SELECT + 4 * dev->slice_id;
+
+ switch (data_path) {
+ case ALL_FIELDS_DATA_SELECT:
+ val |= path_val;
+ break;
+ case VIP_CSC_SRC_DATA_SELECT:
+ insert_field(&val, path_val, VIP_CSC_SRC_SELECT_MASK,
+ VIP_CSC_SRC_SELECT_SHFT);
+ break;
+ case VIP_SC_SRC_DATA_SELECT:
+ insert_field(&val, path_val, VIP_SC_SRC_SELECT_MASK,
+ VIP_SC_SRC_SELECT_SHFT);
+ break;
+ case VIP_RGB_SRC_DATA_SELECT:
+ val |= (path_val) ? VIP_RGB_SRC_SELECT : 0;
+ break;
+ case VIP_RGB_OUT_LO_DATA_SELECT:
+ val |= (path_val) ? VIP_RGB_OUT_LO_SRC_SELECT : 0;
+ break;
+ case VIP_RGB_OUT_HI_DATA_SELECT:
+ val |= (path_val) ? VIP_RGB_OUT_HI_SRC_SELECT : 0;
+ break;
+ case VIP_CHR_DS_1_SRC_DATA_SELECT:
+ insert_field(&val, path_val, VIP_DS1_SRC_SELECT_MASK,
+ VIP_DS1_SRC_SELECT_SHFT);
+ break;
+ case VIP_CHR_DS_2_SRC_DATA_SELECT:
+ insert_field(&val, path_val, VIP_DS2_SRC_SELECT_MASK,
+ VIP_DS2_SRC_SELECT_SHFT);
+ break;
+ case VIP_MULTI_CHANNEL_DATA_SELECT:
+ val |= (path_val) ? VIP_MULTI_CHANNEL_SELECT : 0;
+ break;
+ case VIP_CHR_DS_1_DATA_BYPASS:
+ val |= (path_val) ? VIP_DS1_BYPASS : 0;
+ break;
+ case VIP_CHR_DS_2_DATA_BYPASS:
+ val |= (path_val) ? VIP_DS2_BYPASS : 0;
+ break;
+ default:
+ vip_err(dev, "%s: data_path 0x%x is not valid\n",
+ __func__, data_path);
+ return;
+ }
+ insert_field(&val, data_path, VIP_DATAPATH_SELECT_MASK,
+ VIP_DATAPATH_SELECT_SHFT);
+ reg_write(dev, data_path_reg, val);
+ vip_dbg(3, dev, "%s: DATA_PATH_SELECT(%08X): %08X\n", __func__,
+ data_path_reg, reg_read(dev, data_path_reg));
+}
+
+/*
+ * Return the vip_stream structure for a given struct file
+ */
+static inline struct vip_stream *file2stream(struct file *file)
+{
+ return video_drvdata(file);
+}
+
+/*
+ * Append a destination descriptor to the current descriptor list,
+ * setting up dma to the given srce.
+ */
+static int add_out_dtd(struct vip_stream *stream, int srce_type)
+{
+ struct vip_port *port = stream->port;
+ struct vip_dev *dev = port->dev;
+ struct vip_srce_info *sinfo = &srce_info[srce_type];
+ struct v4l2_rect *c_rect = &port->c_rect;
+ struct vip_fmt *fmt = port->fmt;
+ int channel, plane = 0;
+ int max_width, max_height;
+ dma_addr_t dma_addr;
+ u32 flags;
+ u32 width = stream->width;
+
+ channel = sinfo->base_channel;
+
+ switch (srce_type) {
+ case VIP_SRCE_MULT_PORT:
+ case VIP_SRCE_MULT_ANC:
+ if (port->port_id == VIP_PORTB)
+ channel += VIP_CHAN_MULT_PORTB_OFFSET;
+ channel += stream->stream_id;
+ flags = 0;
+ break;
+ case VIP_SRCE_CHROMA:
+ plane = 1;
+ /* fallthrough */
+ case VIP_SRCE_LUMA:
+ if (port->port_id == VIP_PORTB) {
+ if (port->scaler && !port->fmt->coplanar)
+ /*
+ * In this case Port A Chroma channel
+ * is used to carry Port B scaled YUV422
+ */
+ channel += 1;
+ else
+ channel += VIP_CHAN_YUV_PORTB_OFFSET;
+ }
+ flags = port->flags;
+ break;
+ case VIP_SRCE_RGB:
+ if ((port->port_id == VIP_PORTB) ||
+ ((port->port_id == VIP_PORTA) &&
+ (port->csc == VIP_CSC_NA) &&
+ v4l2_is_format_rgb(port->fmt->finfo)))
+ /*
+ * RGB sensor only connect to Y_LO
+ * channel i.e. port B channel.
+ */
+ channel += VIP_CHAN_RGB_PORTB_OFFSET;
+ flags = port->flags;
+ break;
+ default:
+ vip_err(stream, "%s: srce_type 0x%x is not valid\n",
+ __func__, srce_type);
+ return -1;
+ }
+
+ if (dev->slice_id == VIP_SLICE2)
+ channel += VIP_CHAN_VIP2_OFFSET;
+
+ /* This is just for initialization purposes.
+ * The actual dma_addr will be configured in vpdma_update_dma_addr
+ */
+ dma_addr = 0;
+
+ if (port->fmt->vpdma_fmt[0] == &vpdma_raw_fmts[VPDMA_DATA_FMT_RAW8]) {
+ /*
+ * Special case since we are faking a YUV422 16bit format
+ * to have the vpdma perform the needed byte swap
+ * we need to adjust the pixel width accordingly
+ * otherwise the parser will attempt to collect more pixels
+ * then available and the vpdma transfer will exceed the
+ * allocated frame buffer.
+ */
+ width >>= 1;
+ vip_dbg(1, stream, "%s: 8 bit raw detected, adjusting width to %d\n",
+ __func__, width);
+ }
+
+ /*
+ * Use VPDMA_MAX_SIZE1 or VPDMA_MAX_SIZE2 register for slice0/1
+ */
+
+ if (dev->slice_id == VIP_SLICE1) {
+ vpdma_set_max_size(dev->shared->vpdma, VPDMA_MAX_SIZE1,
+ width, stream->height);
+
+ max_width = MAX_OUT_WIDTH_REG1;
+ max_height = MAX_OUT_HEIGHT_REG1;
+ } else {
+ vpdma_set_max_size(dev->shared->vpdma, VPDMA_MAX_SIZE2,
+ width, stream->height);
+
+ max_width = MAX_OUT_WIDTH_REG2;
+ max_height = MAX_OUT_HEIGHT_REG2;
+ }
+
+ /*
+ * Mark this channel to be cleared while cleaning up resources
+ * This will make sure that an abort descriptor for this channel
+ * would be submitted to VPDMA causing any ongoing transaction to be
+ * aborted and cleanup the VPDMA FSM for this channel
+ */
+ stream->vpdma_channels[channel] = 1;
+
+ vpdma_rawchan_add_out_dtd(&stream->desc_list, c_rect->width,
+ stream->bytesperline, c_rect,
+ fmt->vpdma_fmt[plane], dma_addr,
+ max_width, max_height, channel, flags);
+
+ return 0;
+}
+
+/*
+ * add_stream_dtds - prepares and starts DMA for pending transfers
+ */
+static void add_stream_dtds(struct vip_stream *stream)
+{
+ struct vip_port *port = stream->port;
+ int srce_type;
+
+ if (port->flags & FLAG_MULT_PORT)
+ srce_type = VIP_SRCE_MULT_PORT;
+ else if (port->flags & FLAG_MULT_ANC)
+ srce_type = VIP_SRCE_MULT_ANC;
+ else if (v4l2_is_format_rgb(port->fmt->finfo))
+ srce_type = VIP_SRCE_RGB;
+ else
+ srce_type = VIP_SRCE_LUMA;
+
+ add_out_dtd(stream, srce_type);
+
+ if (srce_type == VIP_SRCE_LUMA && port->fmt->coplanar)
+ add_out_dtd(stream, VIP_SRCE_CHROMA);
+}
+
+#define PARSER_IRQ_MASK (VIP_PORTA_OUTPUT_FIFO_YUV | \
+ VIP_PORTB_OUTPUT_FIFO_YUV)
+
+static void enable_irqs(struct vip_dev *dev, int irq_num, int list_num)
+{
+ struct vip_parser_data *parser = dev->parser;
+ u32 reg_addr = VIP_INT0_ENABLE0_SET +
+ VIP_INTC_INTX_OFFSET * irq_num;
+ u32 irq_val = (1 << (list_num * 2)) |
+ (VIP_VIP1_PARSER_INT << (irq_num * 1));
+
+ /* Enable Parser Interrupt */
+ reg_write(parser, VIP_PARSER_FIQ_MASK, ~PARSER_IRQ_MASK);
+
+ reg_write(dev->shared, reg_addr, irq_val);
+
+ vpdma_enable_list_complete_irq(dev->shared->vpdma,
+ irq_num, list_num, true);
+}
+
+static void disable_irqs(struct vip_dev *dev, int irq_num, int list_num)
+{
+ struct vip_parser_data *parser = dev->parser;
+ u32 reg_addr = VIP_INT0_ENABLE0_CLR +
+ VIP_INTC_INTX_OFFSET * irq_num;
+ u32 irq_val = (1 << (list_num * 2)) |
+ (VIP_VIP1_PARSER_INT << (irq_num * 1));
+
+ /* Disable all Parser Interrupt */
+ reg_write(parser, VIP_PARSER_FIQ_MASK, 0xffffffff);
+
+ reg_write(dev->shared, reg_addr, irq_val);
+
+ vpdma_enable_list_complete_irq(dev->shared->vpdma,
+ irq_num, list_num, false);
+}
+
+static void clear_irqs(struct vip_dev *dev, int irq_num, int list_num)
+{
+ struct vip_parser_data *parser = dev->parser;
+ u32 reg_addr = VIP_INT0_STATUS0_CLR +
+ VIP_INTC_INTX_OFFSET * irq_num;
+ u32 irq_val = (1 << (list_num * 2)) |
+ (VIP_VIP1_PARSER_INT << (irq_num * 1));
+
+ /* Clear all Parser Interrupt */
+ reg_write(parser, VIP_PARSER_FIQ_CLR, 0xffffffff);
+ reg_write(parser, VIP_PARSER_FIQ_CLR, 0x0);
+
+ reg_write(dev->shared, reg_addr, irq_val);
+
+ vpdma_clear_list_stat(dev->shared->vpdma, irq_num, dev->slice_id);
+}
+
+static void populate_desc_list(struct vip_stream *stream)
+{
+ struct vip_port *port = stream->port;
+ struct vip_dev *dev = port->dev;
+ unsigned int list_length;
+
+ stream->desc_next = stream->desc_list.buf.addr;
+ add_stream_dtds(stream);
+
+ list_length = stream->desc_next - stream->desc_list.buf.addr;
+ vpdma_map_desc_buf(dev->shared->vpdma, &stream->desc_list.buf);
+}
+
+/*
+ * start_dma - adds descriptors to the dma list and submits them.
+ * Should be called after a new vb is queued and on a vpdma list
+ * completion interrupt.
+ */
+static void start_dma(struct vip_stream *stream, struct vip_buffer *buf)
+{
+ struct vip_dev *dev = stream->port->dev;
+ struct vpdma_data *vpdma = dev->shared->vpdma;
+ int list_num = stream->list_num;
+ dma_addr_t dma_addr;
+ int drop_data;
+
+ if (vpdma_list_busy(vpdma, list_num)) {
+ vip_err(stream, "vpdma list busy, cannot post\n");
+ return; /* nothing to do */
+ }
+
+ if (buf) {
+ dma_addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
+ drop_data = 0;
+ vip_dbg(4, stream, "%s: vb2 buf idx:%d, dma_addr:%pad\n",
+ __func__, buf->vb.vb2_buf.index, &dma_addr);
+ } else {
+ dma_addr = 0;
+ drop_data = 1;
+ vip_dbg(4, stream, "%s: dropped\n", __func__);
+ }
+
+ vpdma_update_dma_addr(dev->shared->vpdma, &stream->desc_list,
+ dma_addr, stream->write_desc, drop_data, 0);
+
+ if (stream->port->fmt->coplanar) {
+ dma_addr += stream->bytesperline * stream->height;
+ vpdma_update_dma_addr(dev->shared->vpdma, &stream->desc_list,
+ dma_addr, stream->write_desc + 1,
+ drop_data, 1);
+ }
+
+ vpdma_submit_descs(dev->shared->vpdma,
+ &stream->desc_list, stream->list_num);
+}
+
+static void vip_schedule_next_buffer(struct vip_stream *stream)
+{
+ struct vip_dev *dev = stream->port->dev;
+ struct vip_buffer *buf;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dev->slock, flags);
+ if (list_empty(&stream->vidq)) {
+ vip_dbg(4, stream, "Dropping frame\n");
+ if (list_empty(&stream->dropq)) {
+ vip_err(stream, "No dropq buffer left!");
+ spin_unlock_irqrestore(&dev->slock, flags);
+ return;
+ }
+ buf = list_entry(stream->dropq.next,
+ struct vip_buffer, list);
+
+ buf->drop = true;
+ list_move_tail(&buf->list, &stream->post_bufs);
+ buf = NULL;
+ } else {
+ buf = list_entry(stream->vidq.next,
+ struct vip_buffer, list);
+ buf->drop = false;
+ list_move_tail(&buf->list, &stream->post_bufs);
+ vip_dbg(4, stream, "added next buffer\n");
+ }
+
+ spin_unlock_irqrestore(&dev->slock, flags);
+ start_dma(stream, buf);
+}
+
+static void vip_process_buffer_complete(struct vip_stream *stream)
+{
+ struct vip_dev *dev = stream->port->dev;
+ struct vip_buffer *buf;
+ struct vb2_v4l2_buffer *vb = NULL;
+ unsigned long flags, fld;
+
+ buf = list_first_entry(&stream->post_bufs, struct vip_buffer, list);
+
+ if (stream->port->flags & FLAG_INTERLACED) {
+ vpdma_unmap_desc_buf(dev->shared->vpdma,
+ &stream->desc_list.buf);
+
+ fld = dtd_get_field(stream->write_desc);
+ stream->field = fld ? V4L2_FIELD_BOTTOM : V4L2_FIELD_TOP;
+
+ vpdma_map_desc_buf(dev->shared->vpdma, &stream->desc_list.buf);
+ }
+
+ if (buf) {
+ vip_dbg(4, stream, "vip buffer complete 0x%x, 0x%x\n",
+ (unsigned int)buf, buf->drop);
+
+ vb = &buf->vb;
+ vb->field = stream->field;
+ vb->sequence = stream->sequence;
+ vb->vb2_buf.timestamp = ktime_get_ns();
+
+ if (buf->drop) {
+ spin_lock_irqsave(&dev->slock, flags);
+ list_move_tail(&buf->list, &stream->dropq);
+ spin_unlock_irqrestore(&dev->slock, flags);
+ } else {
+ spin_lock_irqsave(&dev->slock, flags);
+ list_del(&buf->list);
+ spin_unlock_irqrestore(&dev->slock, flags);
+ vb2_buffer_done(&vb->vb2_buf, VB2_BUF_STATE_DONE);
+ }
+ } else {
+ vip_err(stream, "%s: buf is null!!!\n", __func__);
+ return;
+ }
+
+ stream->sequence++;
+}
+
+static int vip_reset_vpdma(struct vip_stream *stream)
+{
+ struct vip_port *port = stream->port;
+ struct vip_dev *dev = port->dev;
+ struct vip_buffer *buf;
+ unsigned long flags;
+
+ stop_dma(stream, false);
+
+ spin_lock_irqsave(&dev->slock, flags);
+ /* requeue all active buffers in the opposite order */
+ while (!list_empty(&stream->post_bufs)) {
+ buf = list_last_entry(&stream->post_bufs,
+ struct vip_buffer, list);
+ list_del(&buf->list);
+ if (buf->drop == 1) {
+ list_add_tail(&buf->list, &stream->dropq);
+ vip_dbg(4, stream, "requeueing drop buffer on dropq\n");
+ } else {
+ list_add(&buf->list, &stream->vidq);
+ vip_dbg(4, stream, "requeueing vb2 buf idx:%d on vidq\n",
+ buf->vb.vb2_buf.index);
+ }
+ }
+ spin_unlock_irqrestore(&dev->slock, flags);
+
+ /* Make sure the desc_list is unmapped */
+ vpdma_unmap_desc_buf(dev->shared->vpdma, &stream->desc_list.buf);
+
+ return 0;
+}
+
+static void vip_overflow_recovery_work(struct work_struct *work)
+{
+ struct vip_stream *stream = container_of(work, struct vip_stream,
+ recovery_work);
+ struct vip_port *port = stream->port;
+ struct vip_dev *dev = port->dev;
+
+ vip_err(stream, "%s: Port %c\n", __func__,
+ port->port_id == VIP_PORTA ? 'A' : 'B');
+
+ disable_irqs(dev, dev->slice_id, stream->list_num);
+ clear_irqs(dev, dev->slice_id, stream->list_num);
+
+ /* 1. Set VIP_XTRA6_PORT_A[31:16] YUV_SRCNUM_STOP_IMMEDIATELY */
+ /* 2. Set VIP_XTRA6_PORT_A[15:0] ANC_SRCNUM_STOP_IMMEDIATELY */
+ vip_parser_stop_imm(port, 1);
+
+ /* 3. Clear VIP_PORT_A[8] ENABLE */
+ /*
+ * 4. Set VIP_PORT_A[7] CLR_ASYNC_FIFO_RD
+ * Set VIP_PORT_A[6] CLR_ASYNC_FIFO_WR
+ */
+ vip_enable_parser(port, false);
+
+ /* 5. Set VIP_PORT_A[23] SW_RESET */
+ vip_reset_parser(port, 1);
+
+ /*
+ * 6. Reset other VIP modules
+ * For each module used downstream of VIP_PARSER, write 1 to the
+ * bit location of the VIP_CLKC_RST register which is connected
+ * to VIP_PARSER
+ */
+ vip_module_reset(dev, VIP_DP_RST, true);
+
+ usleep_range(200, 250);
+
+ /*
+ * 7. Abort VPDMA channels
+ * Write to list attribute to stop list 0
+ * Write to list address register location of abort list
+ * Write to list attribute register list 0 and size of abort list
+ */
+ vip_reset_vpdma(stream);
+
+ /* 8. Clear VIP_PORT_A[23] SW_RESET */
+ vip_reset_parser(port, 0);
+
+ /*
+ * 9. Un-reset other VIP modules
+ * For each module used downstream of VIP_PARSER, write 0 to
+ * the bit location of the VIP_CLKC_RST register which is
+ * connected to VIP_PARSER
+ */
+ vip_module_reset(dev, VIP_DP_RST, false);
+
+ /* 10. (Delay) */
+ /* 11. SC coeff downloaded (if VIP_SCALER is being used) */
+ vip_setup_scaler(stream);
+
+ /* 12. (Delay) */
+ /* the above are not needed here yet */
+
+ populate_desc_list(stream);
+ stream->num_recovery++;
+ if (stream->num_recovery < 5) {
+ /* Reload the vpdma */
+ vip_load_vpdma_list_fifo(stream);
+
+ enable_irqs(dev, dev->slice_id, stream->list_num);
+ vip_schedule_next_buffer(stream);
+
+ /* 13. Clear VIP_XTRA6_PORT_A[31:16] YUV_SRCNUM_STOP_IMM */
+ /* 14. Clear VIP_XTRA6_PORT_A[15:0] ANC_SRCNUM_STOP_IMM */
+
+ vip_parser_stop_imm(port, 0);
+
+ /* 15. Set VIP_PORT_A[8] ENABLE */
+ /*
+ * 16. Clear VIP_PORT_A[7] CLR_ASYNC_FIFO_RD
+ * Clear VIP_PORT_A[6] CLR_ASYNC_FIFO_WR
+ */
+ vip_enable_parser(port, true);
+ } else {
+ vip_err(stream, "%s: num_recovery limit exceeded leaving disabled\n",
+ __func__);
+ }
+}
+
+static void handle_parser_irqs(struct vip_dev *dev)
+{
+ struct vip_parser_data *parser = dev->parser;
+ struct vip_port *porta = dev->ports[VIP_PORTA];
+ struct vip_port *portb = dev->ports[VIP_PORTB];
+ struct vip_stream *stream = NULL;
+ u32 irq_stat = reg_read(parser, VIP_PARSER_FIQ_STATUS);
+ int i;
+
+ vip_dbg(3, dev, "%s: FIQ_STATUS: 0x%08x\n", __func__, irq_stat);
+
+ /* Clear all Parser Interrupt */
+ reg_write(parser, VIP_PARSER_FIQ_CLR, irq_stat);
+ reg_write(parser, VIP_PARSER_FIQ_CLR, 0x0);
+
+ if (irq_stat & VIP_PORTA_VDET)
+ vip_dbg(3, dev, "VIP_PORTA_VDET\n");
+ if (irq_stat & VIP_PORTB_VDET)
+ vip_dbg(3, dev, "VIP_PORTB_VDET\n");
+ if (irq_stat & VIP_PORTA_ASYNC_FIFO_OF)
+ vip_err(dev, "VIP_PORTA_ASYNC_FIFO_OF\n");
+ if (irq_stat & VIP_PORTB_ASYNC_FIFO_OF)
+ vip_err(dev, "VIP_PORTB_ASYNC_FIFO_OF\n");
+ if (irq_stat & VIP_PORTA_OUTPUT_FIFO_YUV)
+ vip_err(dev, "VIP_PORTA_OUTPUT_FIFO_YUV\n");
+ if (irq_stat & VIP_PORTA_OUTPUT_FIFO_ANC)
+ vip_err(dev, "VIP_PORTA_OUTPUT_FIFO_ANC\n");
+ if (irq_stat & VIP_PORTB_OUTPUT_FIFO_YUV)
+ vip_err(dev, "VIP_PORTB_OUTPUT_FIFO_YUV\n");
+ if (irq_stat & VIP_PORTB_OUTPUT_FIFO_ANC)
+ vip_err(dev, "VIP_PORTB_OUTPUT_FIFO_ANC\n");
+ if (irq_stat & VIP_PORTA_CONN)
+ vip_dbg(3, dev, "VIP_PORTA_CONN\n");
+ if (irq_stat & VIP_PORTA_DISCONN)
+ vip_dbg(3, dev, "VIP_PORTA_DISCONN\n");
+ if (irq_stat & VIP_PORTB_CONN)
+ vip_dbg(3, dev, "VIP_PORTB_CONN\n");
+ if (irq_stat & VIP_PORTB_DISCONN)
+ vip_dbg(3, dev, "VIP_PORTB_DISCONN\n");
+ if (irq_stat & VIP_PORTA_SRC0_SIZE)
+ vip_dbg(3, dev, "VIP_PORTA_SRC0_SIZE\n");
+ if (irq_stat & VIP_PORTB_SRC0_SIZE)
+ vip_dbg(3, dev, "VIP_PORTB_SRC0_SIZE\n");
+ if (irq_stat & VIP_PORTA_YUV_PROTO_VIOLATION)
+ vip_dbg(3, dev, "VIP_PORTA_YUV_PROTO_VIOLATION\n");
+ if (irq_stat & VIP_PORTA_ANC_PROTO_VIOLATION)
+ vip_dbg(3, dev, "VIP_PORTA_ANC_PROTO_VIOLATION\n");
+ if (irq_stat & VIP_PORTB_YUV_PROTO_VIOLATION)
+ vip_dbg(3, dev, "VIP_PORTB_YUV_PROTO_VIOLATION\n");
+ if (irq_stat & VIP_PORTB_ANC_PROTO_VIOLATION)
+ vip_dbg(3, dev, "VIP_PORTB_ANC_PROTO_VIOLATION\n");
+ if (irq_stat & VIP_PORTA_CFG_DISABLE_COMPLETE)
+ vip_dbg(3, dev, "VIP_PORTA_CFG_DISABLE_COMPLETE\n");
+ if (irq_stat & VIP_PORTB_CFG_DISABLE_COMPLETE)
+ vip_dbg(3, dev, "VIP_PORTB_CFG_DISABLE_COMPLETE\n");
+
+ if (irq_stat & (VIP_PORTA_ASYNC_FIFO_OF |
+ VIP_PORTA_OUTPUT_FIFO_YUV |
+ VIP_PORTA_OUTPUT_FIFO_ANC)) {
+ for (i = 0; i < VIP_CAP_STREAMS_PER_PORT; i++) {
+ if (porta->cap_streams[i] &&
+ porta->cap_streams[i]->port->port_id ==
+ porta->port_id) {
+ stream = porta->cap_streams[i];
+ break;
+ }
+ }
+ if (stream) {
+ disable_irqs(dev, dev->slice_id,
+ stream->list_num);
+ schedule_work(&stream->recovery_work);
+ return;
+ }
+ }
+ if (irq_stat & (VIP_PORTB_ASYNC_FIFO_OF |
+ VIP_PORTB_OUTPUT_FIFO_YUV |
+ VIP_PORTB_OUTPUT_FIFO_ANC)) {
+ for (i = 0; i < VIP_CAP_STREAMS_PER_PORT; i++) {
+ if (portb->cap_streams[i] &&
+ portb->cap_streams[i]->port->port_id ==
+ portb->port_id) {
+ stream = portb->cap_streams[i];
+ break;
+ }
+ }
+ if (stream) {
+ disable_irqs(dev, dev->slice_id,
+ stream->list_num);
+ schedule_work(&stream->recovery_work);
+ return;
+ }
+ }
+}
+
+static irqreturn_t vip_irq(int irq_vip, void *data)
+{
+ struct vip_dev *dev = (struct vip_dev *)data;
+ struct vpdma_data *vpdma;
+ struct vip_stream *stream;
+ int list_num;
+ int irq_num = dev->slice_id;
+ u32 irqst, irqst_saved, reg_addr;
+
+ if (!dev->shared)
+ return IRQ_HANDLED;
+
+ vpdma = dev->shared->vpdma;
+ reg_addr = VIP_INT0_STATUS0 +
+ VIP_INTC_INTX_OFFSET * irq_num;
+ irqst_saved = reg_read(dev->shared, reg_addr);
+ irqst = irqst_saved;
+
+ vip_dbg(8, dev, "IRQ %d VIP_INT%d_STATUS0 0x%x\n",
+ irq_vip, irq_num, irqst);
+ if (irqst) {
+ if (irqst & (VIP_VIP1_PARSER_INT << (irq_num * 1))) {
+ irqst &= ~(VIP_VIP1_PARSER_INT << (irq_num * 1));
+ handle_parser_irqs(dev);
+ }
+
+ for (list_num = 0; irqst && (list_num < 8); list_num++) {
+ /* Check for LIST_COMPLETE IRQ */
+ if (!(irqst & (1 << list_num * 2)))
+ continue;
+
+ vip_dbg(8, dev, "IRQ %d: handling LIST%d_COMPLETE\n",
+ irq_num, list_num);
+
+ stream = vpdma_hwlist_get_priv(vpdma, list_num);
+ if (!stream || stream->list_num != list_num) {
+ vip_err(dev, "IRQ occurred for unused list");
+ continue;
+ }
+
+ vpdma_clear_list_stat(vpdma, irq_num, list_num);
+
+ vip_process_buffer_complete(stream);
+
+ vip_schedule_next_buffer(stream);
+
+ irqst &= ~((1 << list_num * 2));
+ }
+ }
+
+ /* Acknowledge that we are done with all interrupts */
+ reg_write(dev->shared, VIP_INTC_E0I, 1 << irq_num);
+
+ /* Clear handled events from status register */
+ reg_addr = VIP_INT0_STATUS0_CLR +
+ VIP_INTC_INTX_OFFSET * irq_num;
+ reg_write(dev->shared, reg_addr, irqst_saved);
+
+ return IRQ_HANDLED;
+}
+
+/*
+ * video ioctls
+ */
+static int vip_querycap(struct file *file, void *priv,
+ struct v4l2_capability *cap)
+{
+ struct vip_stream *stream = file2stream(file);
+ struct vip_port *port = stream->port;
+ struct vip_dev *dev = port->dev;
+
+ strscpy(cap->driver, VIP_MODULE_NAME, sizeof(cap->driver));
+ strscpy(cap->card, VIP_MODULE_NAME, sizeof(cap->card));
+
+ snprintf(cap->bus_info, sizeof(cap->bus_info),
+ "platform:%s:%s:stream%1d", dev->shared->name, port->name,
+ stream->stream_id);
+ return 0;
+}
+
+static int vip_enuminput(struct file *file, void *priv,
+ struct v4l2_input *inp)
+{
+ struct vip_stream *stream = file2stream(file);
+
+ if (inp->index)
+ return -EINVAL;
+
+ inp->type = V4L2_INPUT_TYPE_CAMERA;
+ inp->std = stream->vfd->tvnorms;
+ snprintf(inp->name, sizeof(inp->name), "camera %u", stream->vfd->num);
+
+ return 0;
+}
+
+static int vip_g_input(struct file *file, void *priv, unsigned int *i)
+{
+ *i = 0;
+ return 0;
+}
+
+static int vip_s_input(struct file *file, void *priv, unsigned int i)
+{
+ if (i != 0)
+ return -EINVAL;
+ return 0;
+}
+
+static int vip_querystd(struct file *file, void *fh, v4l2_std_id *std)
+{
+ struct vip_stream *stream = file2stream(file);
+ struct vip_port *port = stream->port;
+
+ *std = stream->vfd->tvnorms;
+ v4l2_subdev_call(port->subdev, video, querystd, std);
+ vip_dbg(1, stream, "querystd: 0x%lx\n", (unsigned long)*std);
+ return 0;
+}
+
+static int vip_g_std(struct file *file, void *fh, v4l2_std_id *std)
+{
+ struct vip_stream *stream = file2stream(file);
+ struct vip_port *port = stream->port;
+
+ *std = stream->vfd->tvnorms;
+ v4l2_subdev_call(port->subdev, video, g_std_output, std);
+ vip_dbg(1, stream, "g_std: 0x%lx\n", (unsigned long)*std);
+
+ return 0;
+}
+
+static int vip_s_std(struct file *file, void *fh, v4l2_std_id std)
+{
+ struct vip_stream *stream = file2stream(file);
+ struct vip_port *port = stream->port;
+
+ vip_dbg(1, stream, "s_std: 0x%lx\n", (unsigned long)std);
+
+ if (!(std & stream->vfd->tvnorms)) {
+ vip_dbg(1, stream, "s_std after check: 0x%lx\n",
+ (unsigned long)std);
+ return -EINVAL;
+ }
+
+ v4l2_subdev_call(port->subdev, video, s_std_output, std);
+ return 0;
+}
+
+static int vip_enum_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_fmtdesc *f)
+{
+ struct vip_stream *stream = file2stream(file);
+ struct vip_port *port = stream->port;
+ struct vip_fmt *fmt;
+
+ vip_dbg(3, stream, "enum_fmt index:%d\n", f->index);
+ if (f->index >= port->num_active_fmt)
+ return -EINVAL;
+
+ fmt = port->active_fmt[f->index];
+
+ f->pixelformat = fmt->fourcc;
+ f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ vip_dbg(3, stream, "enum_fmt fourcc:%s\n",
+ fourcc_to_str(f->pixelformat));
+
+ return 0;
+}
+
+static int vip_enum_framesizes(struct file *file, void *priv,
+ struct v4l2_frmsizeenum *f)
+{
+ struct vip_stream *stream = file2stream(file);
+ struct vip_port *port = stream->port;
+ struct vip_fmt *fmt;
+ struct v4l2_subdev_frame_size_enum fse;
+ int ret;
+
+ fmt = find_port_format_by_pix(port, f->pixel_format);
+ if (!fmt)
+ return -EINVAL;
+
+ fse.index = f->index;
+ fse.pad = port->source_pad;
+ fse.code = fmt->code;
+ fse.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+ ret = v4l2_subdev_call(port->subdev, pad, enum_frame_size, NULL, &fse);
+ if (ret == -ENOIOCTLCMD && !f->index) {
+ /*
+ * if subdev does not support enum_frame_size
+ * then use get_fmt
+ */
+ struct v4l2_subdev_format format = {
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ .pad = port->source_pad,
+ };
+ ret = v4l2_subdev_call(port->subdev, pad, get_fmt, NULL,
+ &format);
+ if (ret)
+ return ret;
+
+ fse.max_width = format.format.width;
+ fse.max_height = format.format.height;
+ } else if (ret) {
+ return -EINVAL;
+ }
+
+ vip_dbg(1, stream, "%s: index: %d code: %x W:[%d,%d] H:[%d,%d]\n",
+ __func__, fse.index, fse.code, fse.min_width, fse.max_width,
+ fse.min_height, fse.max_height);
+
+ f->type = V4L2_FRMSIZE_TYPE_DISCRETE;
+ f->discrete.width = fse.max_width;
+ f->discrete.height = fse.max_height;
+
+ return 0;
+}
+
+static int vip_enum_frameintervals(struct file *file, void *priv,
+ struct v4l2_frmivalenum *f)
+{
+ struct vip_stream *stream = file2stream(file);
+ struct vip_port *port = stream->port;
+ struct vip_fmt *fmt;
+ struct v4l2_subdev_frame_interval_enum fie = {
+ .index = f->index,
+ .width = f->width,
+ .height = f->height,
+ .which = V4L2_SUBDEV_FORMAT_ACTIVE,
+ };
+ int ret;
+
+ fmt = find_port_format_by_pix(port, f->pixel_format);
+ if (!fmt)
+ return -EINVAL;
+
+ fie.code = fmt->code;
+ ret = v4l2_subdev_call(port->subdev, pad, enum_frame_interval,
+ NULL, &fie);
+ if (ret)
+ return ret;
+ f->type = V4L2_FRMIVAL_TYPE_DISCRETE;
+ f->discrete = fie.interval;
+
+ return 0;
+}
+
+static int vip_g_parm(struct file *file, void *priv,
+ struct v4l2_streamparm *parm)
+{
+ struct vip_stream *stream = file2stream(file);
+ struct vip_port *port = stream->port;
+
+ return v4l2_g_parm_cap(stream->vfd, port->subdev, parm);
+}
+
+static int vip_s_parm(struct file *file, void *priv,
+ struct v4l2_streamparm *parm)
+{
+ struct vip_stream *stream = file2stream(file);
+ struct vip_port *port = stream->port;
+
+ return v4l2_s_parm_cap(stream->vfd, port->subdev, parm);
+}
+
+static int vip_calc_format_size(struct vip_port *port,
+ struct vip_fmt *fmt,
+ struct v4l2_format *f)
+{
+ enum v4l2_field *field;
+ unsigned int stride;
+
+ if (!fmt) {
+ vip_dbg(2, port,
+ "no vip_fmt format provided!\n");
+ return -EINVAL;
+ }
+
+ field = &f->fmt.pix.field;
+ if (*field == V4L2_FIELD_ANY)
+ *field = V4L2_FIELD_NONE;
+ else if (V4L2_FIELD_NONE != *field && V4L2_FIELD_ALTERNATE != *field)
+ return -EINVAL;
+
+ v4l_bound_align_image(&f->fmt.pix.width, MIN_W, MAX_W, W_ALIGN,
+ &f->fmt.pix.height, MIN_H, MAX_H, H_ALIGN,
+ S_ALIGN);
+
+ stride = f->fmt.pix.width * (fmt->vpdma_fmt[0]->depth >> 3);
+ if (stride > f->fmt.pix.bytesperline)
+ f->fmt.pix.bytesperline = stride;
+
+ f->fmt.pix.bytesperline = clamp_t(u32, f->fmt.pix.bytesperline,
+ stride, VPDMA_MAX_STRIDE);
+ f->fmt.pix.bytesperline = ALIGN(f->fmt.pix.bytesperline,
+ VPDMA_STRIDE_ALIGN);
+
+ f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;
+ if (fmt->coplanar) {
+ f->fmt.pix.sizeimage += f->fmt.pix.height *
+ f->fmt.pix.bytesperline *
+ fmt->vpdma_fmt[VIP_CHROMA]->depth >> 3;
+ }
+
+ f->fmt.pix.colorspace = fmt->colorspace;
+ f->fmt.pix.priv = 0;
+
+ vip_dbg(3, port, "calc_format_size: fourcc:%s size: %dx%d bpl:%d img_size:%d\n",
+ fourcc_to_str(f->fmt.pix.pixelformat),
+ f->fmt.pix.width, f->fmt.pix.height,
+ f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);
+
+ return 0;
+}
+
+static inline bool vip_is_size_dma_aligned(u32 bpp, u32 width)
+{
+ return ((width * bpp) == ALIGN(width * bpp, VPDMA_STRIDE_ALIGN));
+}
+
+static int vip_try_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct vip_stream *stream = file2stream(file);
+ struct vip_port *port = stream->port;
+ struct v4l2_subdev_frame_size_enum fse;
+ struct vip_fmt *fmt;
+ u32 best_width, best_height, largest_width, largest_height;
+ int ret, found;
+ enum vip_csc_state csc_direction;
+
+ vip_dbg(3, stream, "try_fmt fourcc:%s size: %dx%d\n",
+ fourcc_to_str(f->fmt.pix.pixelformat),
+ f->fmt.pix.width, f->fmt.pix.height);
+
+ fmt = find_port_format_by_pix(port, f->fmt.pix.pixelformat);
+ if (!fmt) {
+ vip_dbg(2, stream,
+ "Fourcc format (0x%08x) not found.\n",
+ f->fmt.pix.pixelformat);
+
+ /* Just get the first one enumerated */
+ fmt = port->active_fmt[0];
+ f->fmt.pix.pixelformat = fmt->fourcc;
+ }
+
+ csc_direction = vip_csc_direction(fmt->code, fmt->finfo);
+ if (csc_direction != VIP_CSC_NA) {
+ if (!is_csc_available(port)) {
+ vip_dbg(2, stream,
+ "CSC not available for Fourcc format (0x%08x).\n",
+ f->fmt.pix.pixelformat);
+
+ /* Just get the first one enumerated */
+ fmt = port->active_fmt[0];
+ f->fmt.pix.pixelformat = fmt->fourcc;
+ /* re-evaluate the csc_direction here */
+ csc_direction = vip_csc_direction(fmt->code,
+ fmt->finfo);
+ } else {
+ vip_dbg(3, stream, "CSC active on Port %c: going %s\n",
+ port->port_id == VIP_PORTA ? 'A' : 'B',
+ (csc_direction == VIP_CSC_Y2R) ? "Y2R" : "R2Y");
+ }
+ }
+
+ /*
+ * Given that sensors might support multiple mbus code we need
+ * to use the one that matches the requested pixel format
+ */
+ port->try_mbus_framefmt = port->mbus_framefmt;
+ port->try_mbus_framefmt.code = fmt->code;
+
+ /* check for/find a valid width/height */
+ ret = 0;
+ found = false;
+ best_width = 0;
+ best_height = 0;
+ largest_width = 0;
+ largest_height = 0;
+ fse.pad = port->source_pad;
+ fse.code = fmt->code;
+ fse.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+ for (fse.index = 0; ; fse.index++) {
+ u32 bpp = fmt->vpdma_fmt[0]->depth >> 3;
+
+ ret = v4l2_subdev_call(port->subdev, pad,
+ enum_frame_size, NULL, &fse);
+ if (ret == -ENOIOCTLCMD) {
+ /*
+ * if subdev does not support enum_frame_size
+ * then just try to set_fmt directly
+ */
+ struct v4l2_subdev_format format = {
+ .which = V4L2_SUBDEV_FORMAT_TRY,
+ };
+ struct v4l2_subdev_pad_config *pad_cfg;
+
+ pad_cfg = v4l2_subdev_alloc_pad_config(port->subdev);
+ if (!pad_cfg)
+ return -ENOMEM;
+
+ v4l2_fill_mbus_format(&format.format, &f->fmt.pix,
+ fmt->code);
+ ret = v4l2_subdev_call(port->subdev, pad, set_fmt,
+ pad_cfg, &format);
+ if (ret)
+ /* here regardless of the reason we give up */
+ break;
+
+ if (f->fmt.pix.width == format.format.width &&
+ f->fmt.pix.height == format.format.height) {
+ found = true;
+ vip_dbg(3, stream, "try_fmt loop:%d found direct match: %dx%d\n",
+ fse.index, format.format.width,
+ format.format.height);
+ }
+ largest_width = format.format.width;
+ largest_height = format.format.height;
+ best_width = format.format.width;
+ best_height = format.format.height;
+
+ v4l2_subdev_free_pad_config(pad_cfg);
+ break;
+
+ } else if (ret) {
+ break;
+ }
+
+ vip_dbg(3, stream, "try_fmt loop:%d fourcc:%s size: %dx%d\n",
+ fse.index, fourcc_to_str(f->fmt.pix.pixelformat),
+ fse.max_width, fse.max_height);
+
+ if (!vip_is_size_dma_aligned(bpp, fse.max_width))
+ continue;
+
+ if ((fse.max_width >= largest_width) &&
+ (fse.max_height >= largest_height)) {
+ vip_dbg(3, stream, "try_fmt loop:%d found new larger: %dx%d\n",
+ fse.index, fse.max_width, fse.max_height);
+ largest_width = fse.max_width;
+ largest_height = fse.max_height;
+ }
+
+ if ((fse.max_width >= f->fmt.pix.width) &&
+ (fse.max_height >= f->fmt.pix.height)) {
+ vip_dbg(3, stream, "try_fmt loop:%d found at least larger: %dx%d\n",
+ fse.index, fse.max_width, fse.max_height);
+
+ if (!best_width ||
+ ((abs(best_width - f->fmt.pix.width) >=
+ abs(fse.max_width - f->fmt.pix.width)) &&
+ (abs(best_height - f->fmt.pix.height) >=
+ abs(fse.max_height - f->fmt.pix.height)))) {
+ best_width = fse.max_width;
+ best_height = fse.max_height;
+ vip_dbg(3, stream, "try_fmt loop:%d found new best: %dx%d\n",
+ fse.index, fse.max_width,
+ fse.max_height);
+ }
+ }
+
+ if ((f->fmt.pix.width == fse.max_width) &&
+ (f->fmt.pix.height == fse.max_height)) {
+ found = true;
+ vip_dbg(3, stream, "try_fmt loop:%d found direct match: %dx%d\n",
+ fse.index, fse.max_width,
+ fse.max_height);
+ break;
+ }
+
+ if ((f->fmt.pix.width >= fse.min_width) &&
+ (f->fmt.pix.width <= fse.max_width) &&
+ (f->fmt.pix.height >= fse.min_height) &&
+ (f->fmt.pix.height <= fse.max_height)) {
+ found = true;
+ vip_dbg(3, stream, "try_fmt loop:%d found direct range match: %dx%d\n",
+ fse.index, fse.max_width,
+ fse.max_height);
+ break;
+ }
+ }
+
+ if (found) {
+ port->try_mbus_framefmt.width = f->fmt.pix.width;
+ port->try_mbus_framefmt.height = f->fmt.pix.height;
+ /* No need to check for scaling */
+ goto calc_size;
+ } else if (largest_width && f->fmt.pix.width > largest_width) {
+ port->try_mbus_framefmt.width = largest_width;
+ port->try_mbus_framefmt.height = largest_height;
+ } else if (best_width) {
+ port->try_mbus_framefmt.width = best_width;
+ port->try_mbus_framefmt.height = best_height;
+ } else {
+ /* use existing values as default */
+ }
+
+ vip_dbg(3, stream, "try_fmt best subdev size: %dx%d\n",
+ port->try_mbus_framefmt.width,
+ port->try_mbus_framefmt.height);
+
+ if (is_scaler_available(port) &&
+ csc_direction != VIP_CSC_Y2R &&
+ !vip_is_mbuscode_raw(fmt->code) &&
+ f->fmt.pix.height <= port->try_mbus_framefmt.height &&
+ port->try_mbus_framefmt.height <= SC_MAX_PIXEL_HEIGHT &&
+ port->try_mbus_framefmt.width <= SC_MAX_PIXEL_WIDTH) {
+ /*
+ * Scaler is only accessible if the dst colorspace is YUV.
+ * As the input to the scaler must be in YUV mode only.
+ *
+ * Scaling up is allowed only horizontally.
+ */
+ unsigned int hratio, vratio, width_align, height_align;
+ u32 bpp = fmt->vpdma_fmt[0]->depth >> 3;
+
+ vip_dbg(3, stream, "Scaler active on Port %c: requesting %dx%d\n",
+ port->port_id == VIP_PORTA ? 'A' : 'B',
+ f->fmt.pix.width, f->fmt.pix.height);
+
+ /* Just make sure everything is properly aligned */
+ width_align = ALIGN(f->fmt.pix.width * bpp, VPDMA_STRIDE_ALIGN);
+ width_align /= bpp;
+ height_align = ALIGN(f->fmt.pix.height, 2);
+
+ f->fmt.pix.width = width_align;
+ f->fmt.pix.height = height_align;
+
+ hratio = f->fmt.pix.width * 1000 /
+ port->try_mbus_framefmt.width;
+ vratio = f->fmt.pix.height * 1000 /
+ port->try_mbus_framefmt.height;
+ if (hratio < 125) {
+ f->fmt.pix.width = port->try_mbus_framefmt.width / 8;
+ vip_dbg(3, stream, "Horizontal scaling ratio out of range adjusting -> %d\n",
+ f->fmt.pix.width);
+ }
+
+ if (vratio < 188) {
+ f->fmt.pix.height = port->try_mbus_framefmt.height / 4;
+ vip_dbg(3, stream, "Vertical scaling ratio out of range adjusting -> %d\n",
+ f->fmt.pix.height);
+ }
+ vip_dbg(3, stream, "Scaler: got %dx%d\n",
+ f->fmt.pix.width, f->fmt.pix.height);
+ } else {
+ /* use existing values as default */
+ f->fmt.pix.width = port->try_mbus_framefmt.width;
+ f->fmt.pix.height = port->try_mbus_framefmt.height;
+ }
+
+calc_size:
+ /* That we have a fmt calculate imagesize and bytesperline */
+ return vip_calc_format_size(port, fmt, f);
+}
+
+static int vip_g_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct vip_stream *stream = file2stream(file);
+ struct vip_port *port = stream->port;
+ struct vip_fmt *fmt = port->fmt;
+
+ /* Use last known values or defaults */
+ f->fmt.pix.width = stream->width;
+ f->fmt.pix.height = stream->height;
+ f->fmt.pix.pixelformat = port->fmt->fourcc;
+ f->fmt.pix.field = stream->sup_field;
+ f->fmt.pix.colorspace = port->fmt->colorspace;
+ f->fmt.pix.bytesperline = stream->bytesperline;
+ f->fmt.pix.sizeimage = stream->sizeimage;
+
+ vip_dbg(3, stream,
+ "g_fmt fourcc:%s code: %04x size: %dx%d bpl:%d img_size:%d\n",
+ fourcc_to_str(f->fmt.pix.pixelformat),
+ fmt->code,
+ f->fmt.pix.width, f->fmt.pix.height,
+ f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);
+ vip_dbg(3, stream, "g_fmt vpdma data type: 0x%02X\n",
+ port->fmt->vpdma_fmt[0]->data_type);
+
+ return 0;
+}
+
+static int vip_s_fmt_vid_cap(struct file *file, void *priv,
+ struct v4l2_format *f)
+{
+ struct vip_stream *stream = file2stream(file);
+ struct vip_port *port = stream->port;
+ struct v4l2_subdev_format sfmt;
+ struct v4l2_mbus_framefmt *mf;
+ enum vip_csc_state csc_direction;
+ int ret;
+
+ vip_dbg(3, stream, "s_fmt input fourcc:%s size: %dx%d bpl:%d img_size:%d\n",
+ fourcc_to_str(f->fmt.pix.pixelformat),
+ f->fmt.pix.width, f->fmt.pix.height,
+ f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);
+
+ ret = vip_try_fmt_vid_cap(file, priv, f);
+ if (ret)
+ return ret;
+
+ vip_dbg(3, stream, "s_fmt try_fmt fourcc:%s size: %dx%d bpl:%d img_size:%d\n",
+ fourcc_to_str(f->fmt.pix.pixelformat),
+ f->fmt.pix.width, f->fmt.pix.height,
+ f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);
+
+ if (vb2_is_busy(&stream->vb_vidq)) {
+ vip_err(stream, "%s queue busy\n", __func__);
+ return -EBUSY;
+ }
+
+ /*
+ * Check if we need the scaler or not
+ *
+ * Since on previous S_FMT call the scaler might have been
+ * allocated if it is not needed in this instance we will
+ * attempt to free it just in case.
+ *
+ * free_scaler() is harmless unless the current port
+ * allocated it.
+ */
+ if (f->fmt.pix.width == port->try_mbus_framefmt.width &&
+ f->fmt.pix.height == port->try_mbus_framefmt.height)
+ free_scaler(port);
+ else
+ allocate_scaler(port);
+
+ port->fmt = find_port_format_by_pix(port,
+ f->fmt.pix.pixelformat);
+ stream->width = f->fmt.pix.width;
+ stream->height = f->fmt.pix.height;
+ stream->bytesperline = f->fmt.pix.bytesperline;
+ stream->sizeimage = f->fmt.pix.sizeimage;
+ stream->sup_field = f->fmt.pix.field;
+ stream->field = f->fmt.pix.field;
+
+ port->c_rect.left = 0;
+ port->c_rect.top = 0;
+ port->c_rect.width = stream->width;
+ port->c_rect.height = stream->height;
+
+ /*
+ * Check if we need the csc unit or not
+ *
+ * Since on previous S_FMT call, the csc might have been
+ * allocated if it is not needed in this instance we will
+ * attempt to free it just in case.
+ *
+ * free_csc() is harmless unless the current port
+ * allocated it.
+ */
+ csc_direction = vip_csc_direction(port->fmt->code, port->fmt->finfo);
+ if (csc_direction == VIP_CSC_NA)
+ free_csc(port);
+ else
+ allocate_csc(port, csc_direction);
+
+ if (stream->sup_field == V4L2_FIELD_ALTERNATE)
+ port->flags |= FLAG_INTERLACED;
+ else
+ port->flags &= ~FLAG_INTERLACED;
+
+ vip_dbg(3, stream, "s_fmt fourcc:%s size: %dx%d bpl:%d img_size:%d\n",
+ fourcc_to_str(f->fmt.pix.pixelformat),
+ f->fmt.pix.width, f->fmt.pix.height,
+ f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);
+
+ mf = &sfmt.format;
+ v4l2_fill_mbus_format(mf, &f->fmt.pix, port->fmt->code);
+ /* Make sure to use the subdev size found in the try_fmt */
+ mf->width = port->try_mbus_framefmt.width;
+ mf->height = port->try_mbus_framefmt.height;
+
+ vip_dbg(3, stream, "s_fmt pix_to_mbus mbus_code: %04X size: %dx%d\n",
+ mf->code,
+ mf->width, mf->height);
+
+ sfmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+ sfmt.pad = port->source_pad;
+ ret = v4l2_subdev_call(port->subdev, pad, set_fmt, NULL, &sfmt);
+ if (ret) {
+ vip_dbg(1, stream, "set_fmt failed in subdev\n");
+ return ret;
+ }
+
+ /* Save it */
+ port->mbus_framefmt = *mf;
+
+ vip_dbg(3, stream, "s_fmt subdev fmt mbus_code: %04X size: %dx%d\n",
+ port->mbus_framefmt.code,
+ port->mbus_framefmt.width, port->mbus_framefmt.height);
+ vip_dbg(3, stream, "s_fmt vpdma data type: 0x%02X\n",
+ port->fmt->vpdma_fmt[0]->data_type);
+
+ return 0;
+}
+
+/*
+ * Does the exact opposite of set_fmt_params
+ * It makes sure the DataPath register is sane after tear down
+ */
+static void unset_fmt_params(struct vip_stream *stream)
+{
+ struct vip_dev *dev = stream->port->dev;
+ struct vip_port *port = stream->port;
+
+ stream->sequence = 0;
+ if (stream->port->flags & FLAG_INTERLACED)
+ stream->field = V4L2_FIELD_TOP;
+
+ if (port->csc == VIP_CSC_Y2R) {
+ if (port->port_id == VIP_PORTA) {
+ vip_set_slice_path(dev, VIP_CSC_SRC_DATA_SELECT, 0);
+ vip_set_slice_path(dev,
+ VIP_MULTI_CHANNEL_DATA_SELECT, 0);
+ vip_set_slice_path(dev, VIP_RGB_OUT_HI_DATA_SELECT, 0);
+ vip_set_slice_path(dev, VIP_RGB_SRC_DATA_SELECT, 0);
+ } else {
+ vip_set_slice_path(dev, VIP_CSC_SRC_DATA_SELECT, 0);
+ vip_set_slice_path(dev,
+ VIP_MULTI_CHANNEL_DATA_SELECT, 0);
+ vip_set_slice_path(dev, VIP_RGB_OUT_LO_DATA_SELECT, 0);
+ }
+ /* We are done */
+ return;
+ } else if (port->csc == VIP_CSC_R2Y) {
+ if (port->scaler && port->fmt->coplanar) {
+ if (port->port_id == VIP_PORTA) {
+ vip_set_slice_path(dev,
+ VIP_CSC_SRC_DATA_SELECT, 0);
+ vip_set_slice_path(dev,
+ VIP_SC_SRC_DATA_SELECT, 0);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_1_SRC_DATA_SELECT,
+ 0);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_1_DATA_BYPASS, 0);
+ vip_set_slice_path(dev,
+ VIP_RGB_OUT_HI_DATA_SELECT,
+ 0);
+ }
+ } else if (port->scaler) {
+ if (port->port_id == VIP_PORTA) {
+ vip_set_slice_path(dev,
+ VIP_CSC_SRC_DATA_SELECT, 0);
+ vip_set_slice_path(dev,
+ VIP_SC_SRC_DATA_SELECT, 0);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_1_SRC_DATA_SELECT,
+ 0);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_1_DATA_BYPASS, 0);
+ vip_set_slice_path(dev,
+ VIP_RGB_OUT_HI_DATA_SELECT,
+ 0);
+ }
+ } else if (port->fmt->coplanar) {
+ if (port->port_id == VIP_PORTA) {
+ vip_set_slice_path(dev,
+ VIP_CSC_SRC_DATA_SELECT, 0);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_1_SRC_DATA_SELECT,
+ 0);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_1_DATA_BYPASS, 0);
+ vip_set_slice_path(dev,
+ VIP_RGB_OUT_HI_DATA_SELECT,
+ 0);
+ }
+ } else {
+ if (port->port_id == VIP_PORTA) {
+ vip_set_slice_path(dev,
+ VIP_CSC_SRC_DATA_SELECT, 0);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_1_SRC_DATA_SELECT,
+ 0);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_1_DATA_BYPASS, 0);
+ vip_set_slice_path(dev,
+ VIP_RGB_OUT_HI_DATA_SELECT,
+ 0);
+ }
+ }
+ /* We are done */
+ return;
+ } else if (v4l2_is_format_rgb(port->fmt->finfo)) {
+ if (port->port_id == VIP_PORTA) {
+ vip_set_slice_path(dev,
+ VIP_MULTI_CHANNEL_DATA_SELECT, 0);
+ vip_set_slice_path(dev, VIP_RGB_OUT_LO_DATA_SELECT, 0);
+ }
+ /* We are done */
+ return;
+ }
+
+ if (port->scaler && port->fmt->coplanar) {
+ if (port->port_id == VIP_PORTA) {
+ vip_set_slice_path(dev, VIP_SC_SRC_DATA_SELECT, 0);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_1_SRC_DATA_SELECT, 0);
+ vip_set_slice_path(dev, VIP_CHR_DS_1_DATA_BYPASS, 0);
+ vip_set_slice_path(dev, VIP_RGB_OUT_HI_DATA_SELECT, 0);
+ } else {
+ vip_set_slice_path(dev, VIP_SC_SRC_DATA_SELECT, 0);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_2_SRC_DATA_SELECT, 0);
+ vip_set_slice_path(dev, VIP_CHR_DS_1_DATA_BYPASS, 0);
+ vip_set_slice_path(dev, VIP_RGB_OUT_LO_DATA_SELECT, 0);
+ vip_set_slice_path(dev,
+ VIP_MULTI_CHANNEL_DATA_SELECT, 0);
+ }
+ } else if (port->scaler) {
+ if (port->port_id == VIP_PORTA) {
+ vip_set_slice_path(dev, VIP_SC_SRC_DATA_SELECT, 0);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_1_SRC_DATA_SELECT, 0);
+ vip_set_slice_path(dev, VIP_CHR_DS_1_DATA_BYPASS, 0);
+ vip_set_slice_path(dev, VIP_RGB_OUT_HI_DATA_SELECT, 0);
+ } else {
+ vip_set_slice_path(dev, VIP_SC_SRC_DATA_SELECT, 0);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_2_SRC_DATA_SELECT, 0);
+ vip_set_slice_path(dev, VIP_CHR_DS_1_DATA_BYPASS, 0);
+ vip_set_slice_path(dev, VIP_CHR_DS_2_DATA_BYPASS, 0);
+ vip_set_slice_path(dev, VIP_RGB_OUT_HI_DATA_SELECT, 0);
+ }
+ } else if (port->fmt->coplanar) {
+ if (port->port_id == VIP_PORTA) {
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_1_SRC_DATA_SELECT, 0);
+ vip_set_slice_path(dev, VIP_CHR_DS_1_DATA_BYPASS, 0);
+ vip_set_slice_path(dev, VIP_RGB_OUT_HI_DATA_SELECT, 0);
+ } else {
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_2_SRC_DATA_SELECT, 0);
+ vip_set_slice_path(dev, VIP_CHR_DS_2_DATA_BYPASS, 0);
+ vip_set_slice_path(dev,
+ VIP_MULTI_CHANNEL_DATA_SELECT, 0);
+ vip_set_slice_path(dev, VIP_RGB_OUT_LO_DATA_SELECT, 0);
+ }
+ } else {
+ /*
+ * We undo all data path setting except for the multi
+ * stream case.
+ * Because we cannot disrupt other on-going capture if only
+ * one stream is terminated the other might still be going
+ */
+ vip_set_slice_path(dev, VIP_MULTI_CHANNEL_DATA_SELECT, 1);
+ vip_set_slice_path(dev, VIP_RGB_OUT_LO_DATA_SELECT, 0);
+ }
+}
+
+/*
+ * Set the registers that are modified when the video format changes.
+ */
+static void set_fmt_params(struct vip_stream *stream)
+{
+ struct vip_dev *dev = stream->port->dev;
+ struct vip_port *port = stream->port;
+
+ stream->sequence = 0;
+ if (stream->port->flags & FLAG_INTERLACED)
+ stream->field = V4L2_FIELD_TOP;
+
+ if (port->csc == VIP_CSC_Y2R) {
+ port->flags &= ~FLAG_MULT_PORT;
+ /* Set alpha component in background color */
+ vpdma_set_bg_color(dev->shared->vpdma,
+ (struct vpdma_data_format *)
+ port->fmt->vpdma_fmt[0],
+ 0xff);
+ if (port->port_id == VIP_PORTA) {
+ /*
+ * Input A: YUV422
+ * Output: Y_UP/UV_UP: RGB
+ * CSC_SRC_SELECT = 1
+ * RGB_OUT_HI_SELECT = 1
+ * RGB_SRC_SELECT = 1
+ * MULTI_CHANNEL_SELECT = 0
+ */
+ vip_set_slice_path(dev, VIP_CSC_SRC_DATA_SELECT, 1);
+ vip_set_slice_path(dev,
+ VIP_MULTI_CHANNEL_DATA_SELECT, 0);
+ vip_set_slice_path(dev, VIP_RGB_OUT_HI_DATA_SELECT, 1);
+ vip_set_slice_path(dev, VIP_RGB_SRC_DATA_SELECT, 1);
+ } else {
+ /*
+ * Input B: YUV422
+ * Output: Y_UP/UV_UP: RGB
+ * CSC_SRC_SELECT = 2
+ * RGB_OUT_LO_SELECT = 1
+ * MULTI_CHANNEL_SELECT = 0
+ */
+ vip_set_slice_path(dev, VIP_CSC_SRC_DATA_SELECT, 2);
+ vip_set_slice_path(dev,
+ VIP_MULTI_CHANNEL_DATA_SELECT, 0);
+ vip_set_slice_path(dev, VIP_RGB_OUT_LO_DATA_SELECT, 1);
+ }
+ /* We are done */
+ return;
+ } else if (port->csc == VIP_CSC_R2Y) {
+ port->flags &= ~FLAG_MULT_PORT;
+ if (port->scaler && port->fmt->coplanar) {
+ if (port->port_id == VIP_PORTA) {
+ /*
+ * Input A: RGB
+ * Output: Y_UP/UV_UP: Scaled YUV420
+ * CSC_SRC_SELECT = 4
+ * SC_SRC_SELECT = 1
+ * CHR_DS_1_SRC_SELECT = 1
+ * CHR_DS_1_BYPASS = 0
+ * RGB_OUT_HI_SELECT = 0
+ */
+ vip_set_slice_path(dev,
+ VIP_CSC_SRC_DATA_SELECT, 4);
+ vip_set_slice_path(dev,
+ VIP_SC_SRC_DATA_SELECT, 1);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_1_SRC_DATA_SELECT,
+ 1);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_1_DATA_BYPASS, 0);
+ vip_set_slice_path(dev,
+ VIP_RGB_OUT_HI_DATA_SELECT,
+ 0);
+ } else {
+ vip_err(stream, "RGB sensor can only be on Port A\n");
+ }
+ } else if (port->scaler) {
+ if (port->port_id == VIP_PORTA) {
+ /*
+ * Input A: RGB
+ * Output: Y_UP: Scaled YUV422
+ * CSC_SRC_SELECT = 4
+ * SC_SRC_SELECT = 1
+ * CHR_DS_1_SRC_SELECT = 1
+ * CHR_DS_1_BYPASS = 1
+ * RGB_OUT_HI_SELECT = 0
+ */
+ vip_set_slice_path(dev,
+ VIP_CSC_SRC_DATA_SELECT, 4);
+ vip_set_slice_path(dev,
+ VIP_SC_SRC_DATA_SELECT, 1);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_1_SRC_DATA_SELECT,
+ 1);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_1_DATA_BYPASS, 1);
+ vip_set_slice_path(dev,
+ VIP_RGB_OUT_HI_DATA_SELECT,
+ 0);
+ } else {
+ vip_err(stream, "RGB sensor can only be on Port A\n");
+ }
+ } else if (port->fmt->coplanar) {
+ if (port->port_id == VIP_PORTA) {
+ /*
+ * Input A: RGB
+ * Output: Y_UP/UV_UP: YUV420
+ * CSC_SRC_SELECT = 4
+ * CHR_DS_1_SRC_SELECT = 2
+ * CHR_DS_1_BYPASS = 0
+ * RGB_OUT_HI_SELECT = 0
+ */
+ vip_set_slice_path(dev,
+ VIP_CSC_SRC_DATA_SELECT, 4);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_1_SRC_DATA_SELECT,
+ 2);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_1_DATA_BYPASS, 0);
+ vip_set_slice_path(dev,
+ VIP_RGB_OUT_HI_DATA_SELECT,
+ 0);
+ } else {
+ vip_err(stream, "RGB sensor can only be on Port A\n");
+ }
+ } else {
+ if (port->port_id == VIP_PORTA) {
+ /*
+ * Input A: RGB
+ * Output: Y_UP/UV_UP: YUV420
+ * CSC_SRC_SELECT = 4
+ * CHR_DS_1_SRC_SELECT = 2
+ * CHR_DS_1_BYPASS = 1
+ * RGB_OUT_HI_SELECT = 0
+ */
+ vip_set_slice_path(dev,
+ VIP_CSC_SRC_DATA_SELECT, 4);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_1_SRC_DATA_SELECT,
+ 2);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_1_DATA_BYPASS, 1);
+ vip_set_slice_path(dev,
+ VIP_RGB_OUT_HI_DATA_SELECT,
+ 0);
+ } else {
+ vip_err(stream, "RGB sensor can only be on Port A\n");
+ }
+ }
+ /* We are done */
+ return;
+ } else if (v4l2_is_format_rgb(port->fmt->finfo)) {
+ port->flags &= ~FLAG_MULT_PORT;
+ /* Set alpha component in background color */
+ vpdma_set_bg_color(dev->shared->vpdma,
+ (struct vpdma_data_format *)
+ port->fmt->vpdma_fmt[0],
+ 0xff);
+ if (port->port_id == VIP_PORTA) {
+ /*
+ * Input A: RGB
+ * Output: Y_LO/UV_LO: RGB
+ * RGB_OUT_LO_SELECT = 1
+ * MULTI_CHANNEL_SELECT = 1
+ */
+ vip_set_slice_path(dev,
+ VIP_MULTI_CHANNEL_DATA_SELECT, 1);
+ vip_set_slice_path(dev, VIP_RGB_OUT_LO_DATA_SELECT, 1);
+ } else {
+ vip_err(stream, "RGB sensor can only be on Port A\n");
+ }
+ /* We are done */
+ return;
+ }
+
+ if (port->scaler && port->fmt->coplanar) {
+ port->flags &= ~FLAG_MULT_PORT;
+ if (port->port_id == VIP_PORTA) {
+ /*
+ * Input A: YUV422
+ * Output: Y_UP/UV_UP: Scaled YUV420
+ * SC_SRC_SELECT = 2
+ * CHR_DS_1_SRC_SELECT = 1
+ * CHR_DS_1_BYPASS = 0
+ * RGB_OUT_HI_SELECT = 0
+ */
+ vip_set_slice_path(dev, VIP_SC_SRC_DATA_SELECT, 2);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_1_SRC_DATA_SELECT, 1);
+ vip_set_slice_path(dev, VIP_CHR_DS_1_DATA_BYPASS, 0);
+ vip_set_slice_path(dev, VIP_RGB_OUT_HI_DATA_SELECT, 0);
+ } else {
+ /*
+ * Input B: YUV422
+ * Output: Y_LO/UV_LO: Scaled YUV420
+ * SC_SRC_SELECT = 3
+ * CHR_DS_2_SRC_SELECT = 1
+ * RGB_OUT_LO_SELECT = 0
+ * MULTI_CHANNEL_SELECT = 0
+ */
+ vip_set_slice_path(dev, VIP_SC_SRC_DATA_SELECT, 3);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_2_SRC_DATA_SELECT, 1);
+ vip_set_slice_path(dev, VIP_CHR_DS_1_DATA_BYPASS, 0);
+ vip_set_slice_path(dev, VIP_RGB_OUT_LO_DATA_SELECT, 0);
+ vip_set_slice_path(dev,
+ VIP_MULTI_CHANNEL_DATA_SELECT, 0);
+ }
+ } else if (port->scaler) {
+ port->flags &= ~FLAG_MULT_PORT;
+ if (port->port_id == VIP_PORTA) {
+ /*
+ * Input A: YUV422
+ * Output: Y_UP: Scaled YUV422
+ * SC_SRC_SELECT = 2
+ * CHR_DS_1_SRC_SELECT = 1
+ * CHR_DS_1_BYPASS = 1
+ * RGB_OUT_HI_SELECT = 0
+ */
+ vip_set_slice_path(dev, VIP_SC_SRC_DATA_SELECT, 2);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_1_SRC_DATA_SELECT, 1);
+ vip_set_slice_path(dev, VIP_CHR_DS_1_DATA_BYPASS, 1);
+ vip_set_slice_path(dev, VIP_RGB_OUT_HI_DATA_SELECT, 0);
+ } else {
+ /*
+ * Input B: YUV422
+ * Output: UV_UP: Scaled YUV422
+ * SC_SRC_SELECT = 3
+ * CHR_DS_2_SRC_SELECT = 1
+ * CHR_DS_1_BYPASS = 1
+ * CHR_DS_2_BYPASS = 1
+ * RGB_OUT_HI_SELECT = 0
+ */
+ vip_set_slice_path(dev, VIP_SC_SRC_DATA_SELECT, 3);
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_2_SRC_DATA_SELECT, 1);
+ vip_set_slice_path(dev, VIP_CHR_DS_1_DATA_BYPASS, 1);
+ vip_set_slice_path(dev, VIP_CHR_DS_2_DATA_BYPASS, 1);
+ vip_set_slice_path(dev, VIP_RGB_OUT_HI_DATA_SELECT, 0);
+ }
+ } else if (port->fmt->coplanar) {
+ port->flags &= ~FLAG_MULT_PORT;
+ if (port->port_id == VIP_PORTA) {
+ /*
+ * Input A: YUV422
+ * Output: Y_UP/UV_UP: YUV420
+ * CHR_DS_1_SRC_SELECT = 3
+ * CHR_DS_1_BYPASS = 0
+ * RGB_OUT_HI_SELECT = 0
+ */
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_1_SRC_DATA_SELECT, 3);
+ vip_set_slice_path(dev, VIP_CHR_DS_1_DATA_BYPASS, 0);
+ vip_set_slice_path(dev, VIP_RGB_OUT_HI_DATA_SELECT, 0);
+ } else {
+ /*
+ * Input B: YUV422
+ * Output: Y_LO/UV_LO: YUV420
+ * CHR_DS_2_SRC_SELECT = 4
+ * CHR_DS_2_BYPASS = 0
+ * RGB_OUT_LO_SELECT = 0
+ * MULTI_CHANNEL_SELECT = 0
+ */
+ vip_set_slice_path(dev,
+ VIP_CHR_DS_2_SRC_DATA_SELECT, 4);
+ vip_set_slice_path(dev, VIP_CHR_DS_2_DATA_BYPASS, 0);
+ vip_set_slice_path(dev,
+ VIP_MULTI_CHANNEL_DATA_SELECT, 0);
+ vip_set_slice_path(dev, VIP_RGB_OUT_LO_DATA_SELECT, 0);
+ }
+ } else {
+ port->flags |= FLAG_MULT_PORT;
+ /*
+ * Input A/B: YUV422
+ * Output: Y_LO: YUV422 - UV_LO: YUV422
+ * MULTI_CHANNEL_SELECT = 1
+ * RGB_OUT_LO_SELECT = 0
+ */
+ vip_set_slice_path(dev, VIP_MULTI_CHANNEL_DATA_SELECT, 1);
+ vip_set_slice_path(dev, VIP_RGB_OUT_LO_DATA_SELECT, 0);
+ }
+}
+
+static int vip_g_selection(struct file *file, void *fh,
+ struct v4l2_selection *s)
+{
+ struct vip_stream *stream = file2stream(file);
+
+ if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ return -EINVAL;
+
+ switch (s->target) {
+ case V4L2_SEL_TGT_COMPOSE_DEFAULT:
+ case V4L2_SEL_TGT_COMPOSE_BOUNDS:
+ case V4L2_SEL_TGT_CROP_BOUNDS:
+ case V4L2_SEL_TGT_CROP_DEFAULT:
+ s->r.left = 0;
+ s->r.top = 0;
+ s->r.width = stream->width;
+ s->r.height = stream->height;
+ return 0;
+
+ case V4L2_SEL_TGT_COMPOSE:
+ case V4L2_SEL_TGT_CROP:
+ s->r = stream->port->c_rect;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int enclosed_rectangle(struct v4l2_rect *a, struct v4l2_rect *b)
+{
+ if (a->left < b->left || a->top < b->top)
+ return 0;
+ if (a->left + a->width > b->left + b->width)
+ return 0;
+ if (a->top + a->height > b->top + b->height)
+ return 0;
+
+ return 1;
+}
+
+static int vip_s_selection(struct file *file, void *fh,
+ struct v4l2_selection *s)
+{
+ struct vip_stream *stream = file2stream(file);
+ struct v4l2_rect r = s->r;
+
+ if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ return -EINVAL;
+
+ switch (s->target) {
+ case V4L2_SEL_TGT_COMPOSE:
+ case V4L2_SEL_TGT_CROP:
+ v4l_bound_align_image(&r.width, 0, stream->width, 0,
+ &r.height, 0, stream->height, 0, 0);
+
+ r.left = clamp_t(unsigned int, r.left, 0,
+ stream->width - r.width);
+ r.top = clamp_t(unsigned int, r.top, 0,
+ stream->height - r.height);
+
+ if (s->flags & V4L2_SEL_FLAG_LE &&
+ !enclosed_rectangle(&r, &s->r))
+ return -ERANGE;
+
+ if (s->flags & V4L2_SEL_FLAG_GE &&
+ !enclosed_rectangle(&s->r, &r))
+ return -ERANGE;
+
+ s->r = r;
+ stream->port->c_rect = r;
+
+ vip_dbg(1, stream, "cropped (%d,%d)/%dx%d of %dx%d\n",
+ r.left, r.top, r.width, r.height,
+ stream->width, stream->height);
+
+ s->r = stream->port->c_rect;
+ return 0;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static long vip_ioctl_default(struct file *file, void *fh, bool valid_prio,
+ unsigned int cmd, void *arg)
+{
+ struct vip_stream *stream = file2stream(file);
+
+ if (!valid_prio) {
+ vip_err(stream, "%s device busy\n", __func__);
+ return -EBUSY;
+ }
+
+ switch (cmd) {
+ default:
+ return -ENOTTY;
+ }
+}
+
+static const struct v4l2_ioctl_ops vip_ioctl_ops = {
+ .vidioc_querycap = vip_querycap,
+ .vidioc_enum_input = vip_enuminput,
+ .vidioc_g_input = vip_g_input,
+ .vidioc_s_input = vip_s_input,
+
+ .vidioc_querystd = vip_querystd,
+ .vidioc_g_std = vip_g_std,
+ .vidioc_s_std = vip_s_std,
+
+ .vidioc_enum_fmt_vid_cap = vip_enum_fmt_vid_cap,
+ .vidioc_g_fmt_vid_cap = vip_g_fmt_vid_cap,
+ .vidioc_try_fmt_vid_cap = vip_try_fmt_vid_cap,
+ .vidioc_s_fmt_vid_cap = vip_s_fmt_vid_cap,
+
+ .vidioc_enum_frameintervals = vip_enum_frameintervals,
+ .vidioc_enum_framesizes = vip_enum_framesizes,
+ .vidioc_s_parm = vip_s_parm,
+ .vidioc_g_parm = vip_g_parm,
+ .vidioc_g_selection = vip_g_selection,
+ .vidioc_s_selection = vip_s_selection,
+ .vidioc_reqbufs = vb2_ioctl_reqbufs,
+ .vidioc_create_bufs = vb2_ioctl_create_bufs,
+ .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
+ .vidioc_querybuf = vb2_ioctl_querybuf,
+ .vidioc_qbuf = vb2_ioctl_qbuf,
+ .vidioc_dqbuf = vb2_ioctl_dqbuf,
+ .vidioc_expbuf = vb2_ioctl_expbuf,
+
+ .vidioc_streamon = vb2_ioctl_streamon,
+ .vidioc_streamoff = vb2_ioctl_streamoff,
+ .vidioc_log_status = v4l2_ctrl_log_status,
+ .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
+ .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
+ .vidioc_default = vip_ioctl_default,
+};
+
+/*
+ * Videobuf operations
+ */
+static int vip_queue_setup(struct vb2_queue *vq,
+ unsigned int *nbuffers, unsigned int *nplanes,
+ unsigned int sizes[], struct device *alloc_devs[])
+{
+ struct vip_stream *stream = vb2_get_drv_priv(vq);
+ unsigned int size = stream->sizeimage;
+
+ if (vq->num_buffers + *nbuffers < 3)
+ *nbuffers = 3 - vq->num_buffers;
+
+ if (*nplanes) {
+ if (sizes[0] < size)
+ return -EINVAL;
+ size = sizes[0];
+ }
+
+ *nplanes = 1;
+ sizes[0] = size;
+
+ vip_dbg(1, stream, "get %d buffer(s) of size %d each.\n",
+ *nbuffers, sizes[0]);
+
+ return 0;
+}
+
+static int vip_buf_prepare(struct vb2_buffer *vb)
+{
+ struct vip_stream *stream = vb2_get_drv_priv(vb->vb2_queue);
+
+ if (vb2_plane_size(vb, 0) < stream->sizeimage) {
+ vip_dbg(1, stream,
+ "%s data will not fit into plane (%lu < %lu)\n",
+ __func__, vb2_plane_size(vb, 0),
+ (long)stream->sizeimage);
+ return -EINVAL;
+ }
+
+ vb2_set_plane_payload(vb, 0, stream->sizeimage);
+
+ return 0;
+}
+
+static void vip_buf_queue(struct vb2_buffer *vb)
+{
+ struct vip_stream *stream = vb2_get_drv_priv(vb->vb2_queue);
+ struct vip_dev *dev = stream->port->dev;
+ struct vip_buffer *buf = container_of(vb, struct vip_buffer,
+ vb.vb2_buf);
+ unsigned long flags;
+
+ spin_lock_irqsave(&dev->slock, flags);
+ list_add_tail(&buf->list, &stream->vidq);
+ spin_unlock_irqrestore(&dev->slock, flags);
+}
+
+static int vip_setup_scaler(struct vip_stream *stream)
+{
+ struct vip_port *port = stream->port;
+ struct vip_dev *dev = port->dev;
+ struct sc_data *sc = dev->sc;
+ struct csc_data *csc = dev->csc;
+ struct vpdma_data *vpdma = dev->shared->vpdma;
+ struct vip_mmr_adb *mmr_adb = port->mmr_adb.addr;
+ int list_num = stream->list_num;
+ int timeout = 500;
+ struct v4l2_format dst_f;
+ struct v4l2_format src_f;
+
+ memset(&src_f, 0, sizeof(src_f));
+ src_f.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ v4l2_fill_pix_format(&src_f.fmt.pix, &port->mbus_framefmt);
+ src_f.fmt.pix.pixelformat = vip_mbus_code_to_fourcc(port->fmt->code);
+
+ dst_f = src_f;
+ dst_f.fmt.pix.pixelformat = port->fmt->fourcc;
+ dst_f.fmt.pix.width = stream->width;
+ dst_f.fmt.pix.height = stream->height;
+
+ /* if scaler not associated with this port then skip */
+ if (port->scaler) {
+ sc_set_hs_coeffs(sc, port->sc_coeff_h.addr,
+ port->mbus_framefmt.width,
+ port->c_rect.width);
+ sc_set_vs_coeffs(sc, port->sc_coeff_v.addr,
+ port->mbus_framefmt.height,
+ port->c_rect.height);
+ sc_config_scaler(sc, &mmr_adb->sc_regs0[0],
+ &mmr_adb->sc_regs8[0], &mmr_adb->sc_regs17[0],
+ port->mbus_framefmt.width,
+ port->mbus_framefmt.height,
+ port->c_rect.width,
+ port->c_rect.height);
+ port->load_mmrs = true;
+ }
+
+ /* if csc not associated with this port then skip */
+ if (port->csc) {
+ csc_set_coeff(csc, &mmr_adb->csc_regs[0],
+ &src_f, &dst_f);
+
+ port->load_mmrs = true;
+ }
+
+ /* If coeff are already loaded then skip */
+ if (!sc->load_coeff_v && !sc->load_coeff_h && !port->load_mmrs)
+ return 0;
+
+ if (vpdma_list_busy(vpdma, list_num)) {
+ vip_dbg(3, stream, "%s: List %d is busy\n",
+ __func__, list_num);
+ }
+
+ /* Make sure we start with a clean list */
+ vpdma_reset_desc_list(&stream->desc_list);
+
+ /* config descriptors */
+ if (port->load_mmrs) {
+ vpdma_map_desc_buf(vpdma, &port->mmr_adb);
+ vpdma_add_cfd_adb(&stream->desc_list, CFD_MMR_CLIENT,
+ &port->mmr_adb);
+
+ port->load_mmrs = false;
+ vip_dbg(3, stream, "Added mmr_adb config desc\n");
+ }
+
+ if (sc->loaded_coeff_h != port->sc_coeff_h.dma_addr ||
+ sc->load_coeff_h) {
+ vpdma_map_desc_buf(vpdma, &port->sc_coeff_h);
+ vpdma_add_cfd_block(&stream->desc_list,
+ VIP_SLICE1_CFD_SC_CLIENT + dev->slice_id,
+ &port->sc_coeff_h, 0);
+
+ sc->loaded_coeff_h = port->sc_coeff_h.dma_addr;
+ sc->load_coeff_h = false;
+ vip_dbg(3, stream, "Added sc_coeff_h config desc\n");
+ }
+
+ if (sc->loaded_coeff_v != port->sc_coeff_v.dma_addr ||
+ sc->load_coeff_v) {
+ vpdma_map_desc_buf(vpdma, &port->sc_coeff_v);
+ vpdma_add_cfd_block(&stream->desc_list,
+ VIP_SLICE1_CFD_SC_CLIENT + dev->slice_id,
+ &port->sc_coeff_v, SC_COEF_SRAM_SIZE >> 4);
+
+ sc->loaded_coeff_v = port->sc_coeff_v.dma_addr;
+ sc->load_coeff_v = false;
+ vip_dbg(3, stream, "Added sc_coeff_v config desc\n");
+ }
+ vip_dbg(3, stream, "CFD_SC_CLIENT %d slice_id: %d\n",
+ VIP_SLICE1_CFD_SC_CLIENT + dev->slice_id, dev->slice_id);
+
+ vpdma_map_desc_buf(vpdma, &stream->desc_list.buf);
+ vip_dbg(3, stream, "Submitting desc on list# %d\n", list_num);
+ vpdma_submit_descs(vpdma, &stream->desc_list, list_num);
+
+ while (vpdma_list_busy(vpdma, list_num) && timeout--)
+ usleep_range(1000, 1100);
+
+ vpdma_unmap_desc_buf(dev->shared->vpdma, &port->mmr_adb);
+ vpdma_unmap_desc_buf(dev->shared->vpdma, &port->sc_coeff_h);
+ vpdma_unmap_desc_buf(dev->shared->vpdma, &port->sc_coeff_v);
+ vpdma_unmap_desc_buf(dev->shared->vpdma, &stream->desc_list.buf);
+
+ vpdma_reset_desc_list(&stream->desc_list);
+
+ if (timeout <= 0) {
+ vip_err(stream, "Timed out setting up scaler through VPDMA list\n");
+ return -EBUSY;
+ }
+
+ return 0;
+}
+
+static int vip_load_vpdma_list_fifo(struct vip_stream *stream)
+{
+ struct vip_port *port = stream->port;
+ struct vip_dev *dev = port->dev;
+ struct vpdma_data *vpdma = dev->shared->vpdma;
+ int list_num = stream->list_num;
+ struct vip_buffer *buf;
+ unsigned long flags;
+ int timeout, i;
+
+ if (vpdma_list_busy(dev->shared->vpdma, stream->list_num))
+ return -EBUSY;
+
+ for (i = 0; i < VIP_VPDMA_FIFO_SIZE; i++) {
+ spin_lock_irqsave(&dev->slock, flags);
+ if (list_empty(&stream->vidq)) {
+ vip_err(stream, "No buffer left!");
+ spin_unlock_irqrestore(&dev->slock, flags);
+ return -EINVAL;
+ }
+
+ buf = list_entry(stream->vidq.next,
+ struct vip_buffer, list);
+ buf->drop = false;
+
+ list_move_tail(&buf->list, &stream->post_bufs);
+ spin_unlock_irqrestore(&dev->slock, flags);
+
+ vip_dbg(2, stream, "%s: start_dma vb2 buf idx:%d\n",
+ __func__, buf->vb.vb2_buf.index);
+ start_dma(stream, buf);
+
+ timeout = 500;
+ while (vpdma_list_busy(vpdma, list_num) && timeout--)
+ usleep_range(1000, 1100);
+
+ if (timeout <= 0) {
+ vip_err(stream, "Timed out loading VPDMA list fifo\n");
+ return -EBUSY;
+ }
+ }
+ return 0;
+}
+
+static int vip_start_streaming(struct vb2_queue *vq, unsigned int count)
+{
+ struct vip_stream *stream = vb2_get_drv_priv(vq);
+ struct vip_port *port = stream->port;
+ struct vip_dev *dev = port->dev;
+ int ret;
+
+ vip_setup_scaler(stream);
+
+ /*
+ * Make sure the scaler is configured before the datapath is
+ * enabled. The scaler can only load the coefficient
+ * parameters when it is idle. If the scaler path is enabled
+ * and video data is being received then the VPDMA transfer will
+ * stall indefinetely.
+ */
+ set_fmt_params(stream);
+ vip_setup_parser(port);
+
+ if (port->subdev) {
+ ret = v4l2_subdev_call(port->subdev, video, s_stream, 1);
+ if (ret < 0 && ret != -ENOIOCTLCMD) {
+ vip_dbg(1, stream, "stream on failed in subdev\n");
+ return ret;
+ }
+ }
+
+ stream->sequence = 0;
+ if (stream->port->flags & FLAG_INTERLACED)
+ stream->field = V4L2_FIELD_TOP;
+ populate_desc_list(stream);
+
+ ret = vip_load_vpdma_list_fifo(stream);
+ if (ret)
+ return ret;
+
+ stream->num_recovery = 0;
+
+ clear_irqs(dev, dev->slice_id, stream->list_num);
+ enable_irqs(dev, dev->slice_id, stream->list_num);
+ vip_schedule_next_buffer(stream);
+ vip_parser_stop_imm(port, false);
+ vip_enable_parser(port, true);
+
+ return 0;
+}
+
+/*
+ * Abort streaming and wait for last buffer
+ */
+static void vip_stop_streaming(struct vb2_queue *vq)
+{
+ struct vip_stream *stream = vb2_get_drv_priv(vq);
+ struct vip_port *port = stream->port;
+ struct vip_dev *dev = port->dev;
+ struct vip_buffer *buf;
+ int ret;
+
+ vip_dbg(2, stream, "%s:\n", __func__);
+
+ vip_parser_stop_imm(port, true);
+ vip_enable_parser(port, false);
+ unset_fmt_params(stream);
+
+ disable_irqs(dev, dev->slice_id, stream->list_num);
+ clear_irqs(dev, dev->slice_id, stream->list_num);
+
+ if (port->subdev) {
+ ret = v4l2_subdev_call(port->subdev, video, s_stream, 0);
+ if (ret < 0 && ret != -ENOIOCTLCMD)
+ vip_dbg(1, stream, "stream on failed in subdev\n");
+ }
+
+ stop_dma(stream, true);
+
+ /* release all active buffers */
+ while (!list_empty(&stream->post_bufs)) {
+ buf = list_entry(stream->post_bufs.next,
+ struct vip_buffer, list);
+ list_del(&buf->list);
+ if (buf->drop == 1)
+ list_add_tail(&buf->list, &stream->dropq);
+ else
+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
+ }
+ while (!list_empty(&stream->vidq)) {
+ buf = list_entry(stream->vidq.next, struct vip_buffer, list);
+ list_del(&buf->list);
+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
+ }
+
+ if (!vb2_is_streaming(vq))
+ return;
+
+ vpdma_unmap_desc_buf(dev->shared->vpdma, &stream->desc_list.buf);
+ vpdma_reset_desc_list(&stream->desc_list);
+}
+
+static const struct vb2_ops vip_video_qops = {
+ .queue_setup = vip_queue_setup,
+ .buf_prepare = vip_buf_prepare,
+ .buf_queue = vip_buf_queue,
+ .start_streaming = vip_start_streaming,
+ .stop_streaming = vip_stop_streaming,
+ .wait_prepare = vb2_ops_wait_prepare,
+ .wait_finish = vb2_ops_wait_finish,
+};
+
+/*
+ * File operations
+ */
+
+static int vip_init_dev(struct vip_dev *dev)
+{
+ if (dev->num_ports != 0)
+ goto done;
+
+ vip_set_clock_enable(dev, 1);
+ vip_module_reset(dev, VIP_SC_RST, false);
+ vip_module_reset(dev, VIP_CSC_RST, false);
+done:
+ dev->num_ports++;
+
+ return 0;
+}
+
+static inline bool is_scaler_available(struct vip_port *port)
+{
+ if (port->endpoint.bus_type == V4L2_MBUS_PARALLEL)
+ if (port->dev->sc_assigned == VIP_NOT_ASSIGNED ||
+ port->dev->sc_assigned == port->port_id)
+ return true;
+ return false;
+}
+
+static inline bool allocate_scaler(struct vip_port *port)
+{
+ if (is_scaler_available(port)) {
+ if (port->dev->sc_assigned == VIP_NOT_ASSIGNED ||
+ port->dev->sc_assigned == port->port_id) {
+ port->dev->sc_assigned = port->port_id;
+ port->scaler = true;
+ return true;
+ }
+ }
+ return false;
+}
+
+static inline void free_scaler(struct vip_port *port)
+{
+ if (port->dev->sc_assigned == port->port_id) {
+ port->dev->sc_assigned = VIP_NOT_ASSIGNED;
+ port->scaler = false;
+ }
+}
+
+static bool is_csc_available(struct vip_port *port)
+{
+ if (port->endpoint.bus_type == V4L2_MBUS_PARALLEL)
+ if (port->dev->csc_assigned == VIP_NOT_ASSIGNED ||
+ port->dev->csc_assigned == port->port_id)
+ return true;
+ return false;
+}
+
+static bool allocate_csc(struct vip_port *port,
+ enum vip_csc_state csc_direction)
+{
+ /* Is CSC needed? */
+ if (csc_direction != VIP_CSC_NA) {
+ if (is_csc_available(port)) {
+ port->dev->csc_assigned = port->port_id;
+ port->csc = csc_direction;
+ vip_dbg(1, port, "%s: csc allocated: dir: %d\n",
+ __func__, csc_direction);
+ return true;
+ }
+ }
+ return false;
+}
+
+static void free_csc(struct vip_port *port)
+{
+ if (port->dev->csc_assigned == port->port_id) {
+ port->dev->csc_assigned = VIP_NOT_ASSIGNED;
+ port->csc = VIP_CSC_NA;
+ vip_dbg(1, port, "%s: csc freed\n",
+ __func__);
+ }
+}
+
+static int vip_init_port(struct vip_port *port)
+{
+ int ret;
+ struct vip_fmt *fmt;
+ struct v4l2_subdev_format sd_fmt;
+ struct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;
+
+ if (port->num_streams != 0)
+ goto done;
+
+ ret = vip_init_dev(port->dev);
+ if (ret)
+ goto done;
+
+ /* Get subdevice current frame format */
+ sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+ sd_fmt.pad = port->source_pad;
+ ret = v4l2_subdev_call(port->subdev, pad, get_fmt, NULL, &sd_fmt);
+ if (ret)
+ vip_dbg(1, port, "init_port get_fmt failed in subdev: (%d)\n",
+ ret);
+
+ /* try to find one that matches */
+ fmt = find_port_format_by_code(port, mbus_fmt->code);
+ if (!fmt) {
+ vip_dbg(1, port, "subdev default mbus_fmt %04x is not matched.\n",
+ mbus_fmt->code);
+ /* if all else fails just pick the first one */
+ fmt = port->active_fmt[0];
+
+ mbus_fmt->code = fmt->code;
+ sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+ sd_fmt.pad = port->source_pad;
+ ret = v4l2_subdev_call(port->subdev, pad, set_fmt,
+ NULL, &sd_fmt);
+ if (ret)
+ vip_dbg(1, port, "init_port set_fmt failed in subdev: (%d)\n",
+ ret);
+ }
+
+ /* Assign current format */
+ port->fmt = fmt;
+ port->mbus_framefmt = *mbus_fmt;
+
+ vip_dbg(3, port, "%s: g_mbus_fmt subdev mbus_code: %04X fourcc:%s size: %dx%d\n",
+ __func__, fmt->code,
+ fourcc_to_str(fmt->fourcc),
+ mbus_fmt->width, mbus_fmt->height);
+
+ if (mbus_fmt->field == V4L2_FIELD_ALTERNATE)
+ port->flags |= FLAG_INTERLACED;
+ else
+ port->flags &= ~FLAG_INTERLACED;
+
+ port->c_rect.left = 0;
+ port->c_rect.top = 0;
+ port->c_rect.width = mbus_fmt->width;
+ port->c_rect.height = mbus_fmt->height;
+
+ ret = vpdma_alloc_desc_buf(&port->sc_coeff_h, SC_COEF_SRAM_SIZE);
+ if (ret != 0)
+ return ret;
+
+ ret = vpdma_alloc_desc_buf(&port->sc_coeff_v, SC_COEF_SRAM_SIZE);
+ if (ret != 0)
+ goto free_sc_h;
+
+ ret = vpdma_alloc_desc_buf(&port->mmr_adb, sizeof(struct vip_mmr_adb));
+ if (ret != 0)
+ goto free_sc_v;
+
+ init_adb_hdrs(port);
+
+ vip_enable_parser(port, false);
+done:
+ port->num_streams++;
+ return 0;
+
+free_sc_v:
+ vpdma_free_desc_buf(&port->sc_coeff_v);
+free_sc_h:
+ vpdma_free_desc_buf(&port->sc_coeff_h);
+ return ret;
+}
+
+static int vip_init_stream(struct vip_stream *stream)
+{
+ struct vip_port *port = stream->port;
+ struct vip_fmt *fmt;
+ struct v4l2_mbus_framefmt *mbus_fmt;
+ struct v4l2_format f;
+ int ret;
+
+ ret = vip_init_port(port);
+ if (ret != 0)
+ return ret;
+
+ fmt = port->fmt;
+ mbus_fmt = &port->mbus_framefmt;
+
+ memset(&f, 0, sizeof(f));
+
+ /* Properly calculate the sizeimage and bytesperline values. */
+ v4l2_fill_pix_format(&f.fmt.pix, mbus_fmt);
+ f.fmt.pix.pixelformat = fmt->fourcc;
+ ret = vip_calc_format_size(port, fmt, &f);
+ if (ret)
+ return ret;
+
+ stream->width = f.fmt.pix.width;
+ stream->height = f.fmt.pix.height;
+ stream->sup_field = f.fmt.pix.field;
+ stream->field = f.fmt.pix.field;
+ stream->bytesperline = f.fmt.pix.bytesperline;
+ stream->sizeimage = f.fmt.pix.sizeimage;
+
+ vip_dbg(3, stream, "init_stream fourcc:%s size: %dx%d bpl:%d img_size:%d\n",
+ fourcc_to_str(f.fmt.pix.pixelformat),
+ f.fmt.pix.width, f.fmt.pix.height,
+ f.fmt.pix.bytesperline, f.fmt.pix.sizeimage);
+ vip_dbg(3, stream, "init_stream vpdma data type: 0x%02X\n",
+ port->fmt->vpdma_fmt[0]->data_type);
+
+ ret = vpdma_create_desc_list(&stream->desc_list, VIP_DESC_LIST_SIZE,
+ VPDMA_LIST_TYPE_NORMAL);
+
+ if (ret != 0)
+ return ret;
+
+ stream->write_desc = (struct vpdma_dtd *)stream->desc_list.buf.addr
+ + 15;
+
+ vip_dbg(1, stream, "%s: stream instance %pa\n",
+ __func__, &stream);
+
+ return 0;
+}
+
+static void vip_release_dev(struct vip_dev *dev)
+{
+ /*
+ * On last close, disable clocks to conserve power
+ */
+
+ if (--dev->num_ports == 0) {
+ /* reset the scaler module */
+ vip_module_reset(dev, VIP_SC_RST, true);
+ vip_module_reset(dev, VIP_CSC_RST, true);
+ vip_set_clock_enable(dev, 0);
+ }
+}
+
+static int vip_set_crop_parser(struct vip_port *port)
+{
+ struct vip_dev *dev = port->dev;
+ struct vip_parser_data *parser = dev->parser;
+ u32 hcrop = 0, vcrop = 0;
+ u32 width = port->mbus_framefmt.width;
+
+ if (port->fmt->vpdma_fmt[0] == &vpdma_raw_fmts[VPDMA_DATA_FMT_RAW8]) {
+ /*
+ * Special case since we are faking a YUV422 16bit format
+ * to have the vpdma perform the needed byte swap
+ * we need to adjust the pixel width accordingly
+ * otherwise the parser will attempt to collect more pixels
+ * then available and the vpdma transfer will exceed the
+ * allocated frame buffer.
+ */
+ width >>= 1;
+ vip_dbg(1, port, "%s: 8 bit raw detected, adjusting width to %d\n",
+ __func__, width);
+ }
+
+ /*
+ * Set Parser Crop parameters to source size otherwise
+ * scaler and colorspace converter will yield garbage.
+ */
+ hcrop = VIP_ACT_BYPASS;
+ insert_field(&hcrop, 0, VIP_ACT_SKIP_NUMPIX_MASK,
+ VIP_ACT_SKIP_NUMPIX_SHFT);
+ insert_field(&hcrop, width,
+ VIP_ACT_USE_NUMPIX_MASK, VIP_ACT_USE_NUMPIX_SHFT);
+ reg_write(parser, VIP_PARSER_CROP_H_PORT(port->port_id), hcrop);
+
+ insert_field(&vcrop, 0, VIP_ACT_SKIP_NUMLINES_MASK,
+ VIP_ACT_SKIP_NUMLINES_SHFT);
+ insert_field(&vcrop, port->mbus_framefmt.height,
+ VIP_ACT_USE_NUMLINES_MASK, VIP_ACT_USE_NUMLINES_SHFT);
+ reg_write(parser, VIP_PARSER_CROP_V_PORT(port->port_id), vcrop);
+
+ return 0;
+}
+
+static int vip_setup_parser(struct vip_port *port)
+{
+ struct vip_dev *dev = port->dev;
+ struct vip_parser_data *parser = dev->parser;
+ struct v4l2_fwnode_endpoint *endpoint = &port->endpoint;
+ struct vip_bt656_bus *bt656_ep = &port->bt656_endpoint;
+ int iface, sync_type;
+ u32 flags = 0, config0;
+
+ /* Reset the port */
+ vip_reset_parser(port, true);
+ usleep_range(200, 250);
+ vip_reset_parser(port, false);
+
+ config0 = reg_read(parser, VIP_PARSER_PORT(port->port_id));
+
+ switch (endpoint->bus.parallel.bus_width) {
+ case 24:
+ iface = SINGLE_24B_INTERFACE;
+ break;
+ case 16:
+ iface = SINGLE_16B_INTERFACE;
+ break;
+ case 8:
+ default:
+ iface = DUAL_8B_INTERFACE;
+ }
+
+ if (endpoint->bus_type == V4L2_MBUS_BT656) {
+ flags = endpoint->bus.parallel.flags;
+
+ /*
+ * Ideally, this should come from subdev
+ * port->fmt can be anything once CSC is enabled
+ */
+ if (vip_is_mbuscode_rgb(port->fmt->code)) {
+ sync_type = EMBEDDED_SYNC_SINGLE_RGB_OR_YUV444;
+ } else {
+ switch (bt656_ep->num_channels) {
+ case 4:
+ sync_type = EMBEDDED_SYNC_4X_MULTIPLEXED_YUV422;
+ break;
+ case 2:
+ sync_type = EMBEDDED_SYNC_2X_MULTIPLEXED_YUV422;
+ break;
+ case 1:
+ sync_type = EMBEDDED_SYNC_SINGLE_YUV422;
+ break;
+ default:
+ sync_type =
+ EMBEDDED_SYNC_LINE_MULTIPLEXED_YUV422;
+ }
+ if (bt656_ep->pixmux == 0)
+ sync_type =
+ EMBEDDED_SYNC_LINE_MULTIPLEXED_YUV422;
+ }
+
+ } else if (endpoint->bus_type == V4L2_MBUS_PARALLEL) {
+ flags = endpoint->bus.parallel.flags;
+
+ if (vip_is_mbuscode_rgb(port->fmt->code))
+ sync_type = DISCRETE_SYNC_SINGLE_RGB_24B;
+ else
+ sync_type = DISCRETE_SYNC_SINGLE_YUV422;
+
+ if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
+ config0 |= VIP_HSYNC_POLARITY;
+ else if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
+ config0 &= ~VIP_HSYNC_POLARITY;
+
+ if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
+ config0 |= VIP_VSYNC_POLARITY;
+ else if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
+ config0 &= ~VIP_VSYNC_POLARITY;
+
+ config0 &= ~VIP_USE_ACTVID_HSYNC_ONLY;
+ config0 |= VIP_ACTVID_POLARITY;
+ config0 |= VIP_DISCRETE_BASIC_MODE;
+
+ } else {
+ vip_err(port, "Device doesn't support CSI2");
+ return -EINVAL;
+ }
+
+ if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) {
+ vip_set_pclk_invert(port);
+ config0 |= VIP_PIXCLK_EDGE_POLARITY;
+ } else {
+ vip_clr_pclk_invert(port);
+ config0 &= ~VIP_PIXCLK_EDGE_POLARITY;
+ }
+
+ config0 |= ((sync_type & VIP_SYNC_TYPE_MASK) << VIP_SYNC_TYPE_SHFT);
+
+ reg_write(parser, VIP_PARSER_PORT(port->port_id), config0);
+
+ vip_set_data_interface(port, iface);
+ vip_set_crop_parser(port);
+
+ return 0;
+}
+
+static void vip_enable_parser(struct vip_port *port, bool on)
+{
+ u32 config0;
+ struct vip_dev *dev = port->dev;
+ struct vip_parser_data *parser = dev->parser;
+
+ config0 = reg_read(parser, VIP_PARSER_PORT(port->port_id));
+
+ if (on) {
+ config0 |= VIP_PORT_ENABLE;
+ config0 &= ~(VIP_ASYNC_FIFO_RD | VIP_ASYNC_FIFO_WR);
+ } else {
+ config0 &= ~VIP_PORT_ENABLE;
+ config0 |= (VIP_ASYNC_FIFO_RD | VIP_ASYNC_FIFO_WR);
+ }
+ reg_write(parser, VIP_PARSER_PORT(port->port_id), config0);
+}
+
+static void vip_reset_parser(struct vip_port *port, bool on)
+{
+ u32 config0;
+ struct vip_dev *dev = port->dev;
+ struct vip_parser_data *parser = dev->parser;
+
+ config0 = reg_read(parser, VIP_PARSER_PORT(port->port_id));
+
+ if (on)
+ config0 |= VIP_SW_RESET;
+ else
+ config0 &= ~VIP_SW_RESET;
+
+ reg_write(parser, VIP_PARSER_PORT(port->port_id), config0);
+}
+
+static void vip_parser_stop_imm(struct vip_port *port, bool on)
+{
+ u32 config0;
+ struct vip_dev *dev = port->dev;
+ struct vip_parser_data *parser = dev->parser;
+
+ config0 = reg_read(parser, VIP_PARSER_STOP_IMM_PORT(port->port_id));
+
+ if (on)
+ config0 = 0xffffffff;
+ else
+ config0 = 0;
+
+ reg_write(parser, VIP_PARSER_STOP_IMM_PORT(port->port_id), config0);
+}
+
+static void vip_release_stream(struct vip_stream *stream)
+{
+ struct vip_dev *dev = stream->port->dev;
+
+ vip_dbg(1, stream, "%s: stream instance %pa\n",
+ __func__, &stream);
+
+ vpdma_unmap_desc_buf(dev->shared->vpdma, &stream->desc_list.buf);
+ vpdma_free_desc_buf(&stream->desc_list.buf);
+ vpdma_free_desc_list(&stream->desc_list);
+}
+
+static void vip_release_port(struct vip_port *port)
+{
+ vip_dbg(1, port, "%s: port instance %pa\n",
+ __func__, &port);
+
+ vpdma_free_desc_buf(&port->mmr_adb);
+ vpdma_free_desc_buf(&port->sc_coeff_h);
+ vpdma_free_desc_buf(&port->sc_coeff_v);
+}
+
+static void stop_dma(struct vip_stream *stream, bool clear_list)
+{
+ struct vip_dev *dev = stream->port->dev;
+ int ch, size = 0;
+
+ /* Create a list of channels to be cleared */
+ for (ch = 0; ch < VPDMA_MAX_CHANNELS; ch++) {
+ if (stream->vpdma_channels[ch] == 1) {
+ stream->vpdma_channels_to_abort[size++] = ch;
+ vip_dbg(2, stream, "Clear channel no: %d\n", ch);
+ }
+ }
+
+ /* Clear all the used channels for the list */
+ vpdma_list_cleanup(dev->shared->vpdma, stream->list_num,
+ stream->vpdma_channels_to_abort, size);
+
+ if (clear_list)
+ for (ch = 0; ch < VPDMA_MAX_CHANNELS; ch++)
+ stream->vpdma_channels[ch] = 0;
+}
+
+static int vip_open(struct file *file)
+{
+ struct vip_stream *stream = video_drvdata(file);
+ struct vip_port *port = stream->port;
+ struct vip_dev *dev = port->dev;
+ int ret = 0;
+
+ vip_dbg(2, stream, "%s\n", __func__);
+
+ mutex_lock(&dev->mutex);
+
+ ret = v4l2_fh_open(file);
+ if (ret) {
+ vip_err(stream, "v4l2_fh_open failed\n");
+ goto unlock;
+ }
+
+ /*
+ * If this is the first open file.
+ * Then initialize hw module.
+ */
+ if (!v4l2_fh_is_singular_file(file))
+ goto unlock;
+
+ if (vip_init_stream(stream))
+ ret = -ENODEV;
+unlock:
+ mutex_unlock(&dev->mutex);
+ return ret;
+}
+
+static int vip_release(struct file *file)
+{
+ struct vip_stream *stream = video_drvdata(file);
+ struct vip_port *port = stream->port;
+ struct vip_dev *dev = port->dev;
+ bool fh_singular;
+ int ret;
+
+ vip_dbg(2, stream, "%s\n", __func__);
+
+ mutex_lock(&dev->mutex);
+
+ /* Save the singular status before we call the clean-up helper */
+ fh_singular = v4l2_fh_is_singular_file(file);
+
+ /* the release helper will cleanup any on-going streaming */
+ ret = _vb2_fop_release(file, NULL);
+
+ free_csc(port);
+ free_scaler(port);
+
+ /*
+ * If this is the last open file.
+ * Then de-initialize hw module.
+ */
+ if (fh_singular) {
+ vip_release_stream(stream);
+
+ if (--port->num_streams == 0) {
+ vip_release_port(port);
+ vip_release_dev(port->dev);
+ }
+ }
+
+ mutex_unlock(&dev->mutex);
+
+ return ret;
+}
+
+static const struct v4l2_file_operations vip_fops = {
+ .owner = THIS_MODULE,
+ .open = vip_open,
+ .release = vip_release,
+ .read = vb2_fop_read,
+ .poll = vb2_fop_poll,
+ .unlocked_ioctl = video_ioctl2,
+ .mmap = vb2_fop_mmap,
+};
+
+static struct video_device vip_videodev = {
+ .name = VIP_MODULE_NAME,
+ .fops = &vip_fops,
+ .ioctl_ops = &vip_ioctl_ops,
+ .minor = -1,
+ .release = video_device_release,
+ .tvnorms = V4L2_STD_NTSC | V4L2_STD_PAL | V4L2_STD_SECAM,
+ .device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE |
+ V4L2_CAP_READWRITE,
+};
+
+static int alloc_stream(struct vip_port *port, int stream_id, int vfl_type)
+{
+ struct vip_stream *stream;
+ struct vip_dev *dev = port->dev;
+ struct vb2_queue *q;
+ struct video_device *vfd;
+ struct vip_buffer *buf;
+ struct list_head *pos, *tmp;
+ int ret, i;
+
+ stream = kzalloc(sizeof(*stream), GFP_KERNEL);
+ if (!stream)
+ return -ENOMEM;
+
+ stream->port = port;
+ stream->stream_id = stream_id;
+ stream->vfl_type = vfl_type;
+ port->cap_streams[stream_id] = stream;
+
+ snprintf(stream->name, sizeof(stream->name), "%s-%d",
+ port->name, stream_id);
+
+ stream->list_num = vpdma_hwlist_alloc(dev->shared->vpdma, stream);
+ if (stream->list_num < 0) {
+ vip_err(stream, "Could not get VPDMA hwlist");
+ ret = -ENODEV;
+ goto do_free_stream;
+ }
+
+ INIT_LIST_HEAD(&stream->post_bufs);
+
+ /*
+ * Initialize queue
+ */
+ q = &stream->vb_vidq;
+ q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
+ q->drv_priv = stream;
+ q->buf_struct_size = sizeof(struct vip_buffer);
+ q->ops = &vip_video_qops;
+ q->mem_ops = &vb2_dma_contig_memops;
+ q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
+ q->lock = &dev->mutex;
+ q->min_buffers_needed = 3;
+ q->dev = dev->v4l2_dev->dev;
+
+ ret = vb2_queue_init(q);
+ if (ret)
+ goto do_free_hwlist;
+
+ INIT_WORK(&stream->recovery_work, vip_overflow_recovery_work);
+
+ INIT_LIST_HEAD(&stream->vidq);
+
+ /* Allocate/populate Drop queue entries */
+ INIT_LIST_HEAD(&stream->dropq);
+ for (i = 0; i < VIP_DROPQ_SIZE; i++) {
+ buf = kzalloc(sizeof(*buf), GFP_ATOMIC);
+ if (!buf) {
+ ret = -ENOMEM;
+ goto do_free_dropq;
+ }
+ buf->drop = true;
+ list_add(&buf->list, &stream->dropq);
+ }
+
+ vfd = video_device_alloc();
+ if (!vfd)
+ goto do_free_dropq;
+ *vfd = vip_videodev;
+ vfd->v4l2_dev = dev->v4l2_dev;
+ vfd->queue = q;
+
+ vfd->lock = &dev->mutex;
+ video_set_drvdata(vfd, stream);
+
+ ret = video_register_device(vfd, vfl_type, -1);
+ if (ret) {
+ vip_err(stream, "Failed to register video device\n");
+ goto do_free_vfd;
+ }
+
+ stream->vfd = vfd;
+
+ vip_info(stream, "device registered as %s\n",
+ video_device_node_name(vfd));
+ return 0;
+
+do_free_vfd:
+ video_device_release(vfd);
+do_free_dropq:
+ list_for_each_safe(pos, tmp, &stream->dropq) {
+ buf = list_entry(pos,
+ struct vip_buffer, list);
+ vip_dbg(1, dev, "dropq buffer\n");
+ list_del(pos);
+ kfree(buf);
+ }
+do_free_hwlist:
+ vpdma_hwlist_release(dev->shared->vpdma, stream->list_num);
+do_free_stream:
+ kfree(stream);
+ return ret;
+}
+
+static void free_stream(struct vip_stream *stream)
+{
+ struct vip_dev *dev;
+ struct vip_buffer *buf;
+ struct list_head *pos, *q;
+
+ if (!stream)
+ return;
+
+ dev = stream->port->dev;
+ /* Free up the Drop queue */
+ list_for_each_safe(pos, q, &stream->dropq) {
+ buf = list_entry(pos,
+ struct vip_buffer, list);
+ vip_dbg(1, stream, "dropq buffer\n");
+ list_del(pos);
+ kfree(buf);
+ }
+
+ video_unregister_device(stream->vfd);
+ vpdma_hwlist_release(dev->shared->vpdma, stream->list_num);
+ stream->port->cap_streams[stream->stream_id] = NULL;
+ kfree(stream);
+}
+
+static int get_subdev_active_format(struct vip_port *port,
+ struct v4l2_subdev *subdev)
+{
+ struct vip_fmt *fmt;
+ struct v4l2_subdev_mbus_code_enum mbus_code;
+ int ret = 0;
+ unsigned int k, i, j;
+ enum vip_csc_state csc;
+
+ /* Enumerate sub device formats and enable all matching local formats */
+ port->num_active_fmt = 0;
+ for (k = 0, i = 0; (ret != -EINVAL); k++) {
+ memset(&mbus_code, 0, sizeof(mbus_code));
+ mbus_code.index = k;
+ mbus_code.which = V4L2_SUBDEV_FORMAT_ACTIVE;
+ ret = v4l2_subdev_call(subdev, pad, enum_mbus_code,
+ NULL, &mbus_code);
+ if (ret)
+ continue;
+
+ vip_dbg(2, port,
+ "subdev %s: code: %04x idx: %d\n",
+ subdev->name, mbus_code.code, k);
+
+ for (j = 0; j < ARRAY_SIZE(vip_formats); j++) {
+ fmt = &vip_formats[j];
+ if (mbus_code.code != fmt->code)
+ continue;
+
+ /*
+ * When the port is configured for BT656
+ * then none of the downstream unit can be used.
+ * So here we need to skip all format requiring
+ * either CSC or CHR_DS
+ */
+ csc = vip_csc_direction(fmt->code, fmt->finfo);
+ if (port->endpoint.bus_type == V4L2_MBUS_BT656 &&
+ (csc != VIP_CSC_NA || fmt->coplanar))
+ continue;
+
+ port->active_fmt[i] = fmt;
+ vip_dbg(2, port,
+ "matched fourcc: %s: code: %04x idx: %d\n",
+ fourcc_to_str(fmt->fourcc), fmt->code, i);
+ port->num_active_fmt = ++i;
+ }
+ }
+
+ if (i == 0) {
+ vip_err(port, "No suitable format reported by subdev %s\n",
+ subdev->name);
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int alloc_port(struct vip_dev *dev, int id, const char *name)
+{
+ struct vip_port *port;
+
+ if (dev->ports[id])
+ return -EINVAL;
+
+ port = devm_kzalloc(&dev->pdev->dev, sizeof(*port), GFP_KERNEL);
+ if (!port)
+ return -ENOMEM;
+
+ dev->ports[id] = port;
+ port->dev = dev;
+ port->port_id = id;
+ port->name = name;
+ port->num_streams = 0;
+ return 0;
+}
+
+static void free_port(struct vip_port *port)
+{
+ if (!port)
+ return;
+
+ v4l2_async_notifier_unregister(&port->notifier);
+ v4l2_async_notifier_cleanup(&port->notifier);
+ free_stream(port->cap_streams[0]);
+}
+
+static int get_field(u32 value, u32 mask, int shift)
+{
+ return (value & (mask << shift)) >> shift;
+}
+
+static int vip_probe_complete(struct platform_device *pdev);
+static void vip_vpdma_fw_cb(struct platform_device *pdev)
+{
+ dev_info(&pdev->dev, "VPDMA firmware loaded\n");
+
+ if (pdev->dev.of_node)
+ vip_probe_complete(pdev);
+}
+
+static int vip_create_streams(struct vip_port *port,
+ struct v4l2_subdev *subdev)
+{
+ struct v4l2_fwnode_bus_parallel *bus;
+ struct vip_bt656_bus *bt656_ep;
+ int i;
+
+ for (i = 0; i < VIP_CAP_STREAMS_PER_PORT; i++)
+ free_stream(port->cap_streams[i]);
+
+ if (get_subdev_active_format(port, subdev))
+ return -ENODEV;
+
+ port->subdev = subdev;
+
+ if (port->endpoint.bus_type == V4L2_MBUS_PARALLEL) {
+ port->flags |= FLAG_MULT_PORT;
+ port->num_streams_configured = 1;
+ alloc_stream(port, 0, VFL_TYPE_VIDEO);
+ } else if (port->endpoint.bus_type == V4L2_MBUS_BT656) {
+ port->flags |= FLAG_MULT_PORT;
+ bus = &port->endpoint.bus.parallel;
+ bt656_ep = &port->bt656_endpoint;
+ port->num_streams_configured = bt656_ep->num_channels;
+ for (i = 0; i < bt656_ep->num_channels; i++) {
+ if (bt656_ep->channels[i] >= 16)
+ continue;
+ alloc_stream(port, bt656_ep->channels[i],
+ VFL_TYPE_VIDEO);
+ }
+ }
+ return 0;
+}
+
+static int vip_async_bound(struct v4l2_async_notifier *notifier,
+ struct v4l2_subdev *subdev,
+ struct v4l2_async_subdev *asd)
+{
+ struct vip_port *port = notifier_to_vip_port(notifier);
+ int ret;
+
+ vip_dbg(1, port, "%s\n", __func__);
+
+ if (port->subdev) {
+ vip_info(port, "Rejecting subdev %s (Already set!!)",
+ subdev->name);
+ return 0;
+ }
+
+ vip_info(port, "Port %c: Using subdev %s for capture\n",
+ port->port_id == VIP_PORTA ? 'A' : 'B', subdev->name);
+
+ ret = vip_find_pad(subdev, MEDIA_PAD_FL_SOURCE);
+ if (ret < 0)
+ return ret;
+ port->source_pad = ret;
+ vip_dbg(1, port, "subdev source_pad: %d\n", port->source_pad);
+
+ ret = vip_create_streams(port, subdev);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int vip_async_complete(struct v4l2_async_notifier *notifier)
+{
+ struct vip_port *port = notifier_to_vip_port(notifier);
+
+ vip_dbg(1, port, "%s\n", __func__);
+ return 0;
+}
+
+static const struct v4l2_async_notifier_operations vip_async_ops = {
+ .bound = vip_async_bound,
+ .complete = vip_async_complete,
+};
+
+static struct fwnode_handle *
+fwnode_graph_get_next_endpoint_by_regs(const struct fwnode_handle *fwnode,
+ int port_reg, int reg)
+{
+ return of_fwnode_handle(of_graph_get_endpoint_by_regs(to_of_node(fwnode),
+ port_reg, reg));
+}
+
+static int vip_register_subdev_notif(struct vip_port *port,
+ struct fwnode_handle *ep)
+{
+ struct v4l2_async_notifier *notifier = &port->notifier;
+ struct vip_dev *dev = port->dev;
+ struct fwnode_handle *subdev;
+ struct v4l2_fwnode_endpoint *vep;
+ struct vip_bt656_bus *bt656_vep;
+ struct v4l2_async_subdev *asd;
+ int ret, rval;
+
+ vep = &port->endpoint;
+ bt656_vep = &port->bt656_endpoint;
+
+ subdev = fwnode_graph_get_remote_port_parent(ep);
+ if (!subdev) {
+ vip_dbg(3, port, "can't get remote parent\n");
+ return -EINVAL;
+ }
+
+ ret = v4l2_fwnode_endpoint_parse(ep, vep);
+ if (ret) {
+ vip_dbg(3, port, "Failed to parse endpoint:\n");
+ fwnode_handle_put(subdev);
+ return -EINVAL;
+ }
+
+ if (vep->bus_type == V4L2_MBUS_BT656) {
+ if (fwnode_property_present(ep, "ti,vip-pixel-mux"))
+ bt656_vep->pixmux = 1;
+ else
+ bt656_vep->pixmux = 0;
+ vip_dbg(3, port, "ti,vip-pixel-mux %u\n", bt656_vep->pixmux);
+
+ bt656_vep->num_channels = 0;
+ rval = fwnode_property_read_u8_array(ep, "ti,vip-channels",
+ NULL, 0);
+ if (rval > 0) {
+ bt656_vep->num_channels =
+ min_t(int, ARRAY_SIZE(bt656_vep->channels),
+ rval);
+
+ fwnode_property_read_u8_array(ep, "ti,vip-channels",
+ bt656_vep->channels,
+ bt656_vep->num_channels);
+ } else {
+ /* channels is not specified then assume 1 channel */
+ bt656_vep->num_channels = 1;
+ bt656_vep->channels[0] = 0;
+ }
+
+ vip_dbg(3, port, "ti,vip-channels %u\n",
+ bt656_vep->num_channels);
+
+ if (bt656_vep->pixmux &&
+ (bt656_vep->num_channels != 1 ||
+ bt656_vep->num_channels != 2 ||
+ bt656_vep->num_channels != 4)) {
+ vip_warn(port,
+ "ti,vip-pixel-mux is set but number of channels is not 1, 2 or 4: (%u), disabling ti,vip-pixel-mux.\n",
+ bt656_vep->num_channels);
+ bt656_vep->pixmux = 0;
+ }
+ }
+
+ v4l2_async_notifier_init(notifier);
+
+ asd = v4l2_async_notifier_add_fwnode_subdev(notifier, subdev,
+ sizeof(*asd));
+ if (IS_ERR(asd)) {
+ vip_dbg(1, port, "Error adding asd\n");
+ fwnode_handle_put(subdev);
+ v4l2_async_notifier_cleanup(notifier);
+ return -EINVAL;
+ }
+
+ notifier->ops = &vip_async_ops;
+ ret = v4l2_async_notifier_register(dev->v4l2_dev, notifier);
+ if (ret) {
+ vip_dbg(1, port, "Error registering async notifier\n");
+ v4l2_async_notifier_cleanup(notifier);
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+static int vip_endpoint_scan(struct platform_device *pdev)
+{
+ struct device_node *parent = pdev->dev.of_node;
+ struct device_node *ep = NULL;
+ int count = 0, p;
+
+ for (p = 0; p < (VIP_NUM_PORTS * VIP_NUM_SLICES); p++) {
+ ep = of_graph_get_endpoint_by_regs(parent, p, 0);
+ if (!ep)
+ continue;
+
+ count++;
+ of_node_put(ep);
+ }
+
+ return count;
+}
+
+static const char *vip_parse_fwnode_label(struct fwnode_handle *fwnode)
+{
+ const char *label = NULL;
+ int ret;
+
+ if (!fwnode)
+ return NULL;
+
+ ret = fwnode_property_read_string(fwnode, "label", &label);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return label;
+}
+
+static int vip_get_clk_polarity(struct platform_device *pdev,
+ struct vip_clk_polarity *pol)
+{
+ struct device_node *parent = pdev->dev.of_node;
+ struct of_phandle_args args;
+ int ret, i;
+
+ if (!pol || !parent ||
+ !of_property_read_bool(parent, "ti,vip-clk-polarity"))
+ return -EINVAL;
+
+ pol->rm_pol = syscon_regmap_lookup_by_phandle(parent,
+ "ti,vip-clk-polarity");
+ if (IS_ERR(pol->rm_pol)) {
+ dev_err(&pdev->dev, "failed to get ti,vip-clk-polarity regmap\n");
+ return PTR_ERR(pol->rm_pol);
+ }
+
+ ret = of_parse_phandle_with_fixed_args(parent, "ti,vip-clk-polarity",
+ 5, 0, &args);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to parse ti,vip-clk-polarity\n");
+ return ret;
+ }
+
+ pol->rm_offset = args.args[0];
+
+ for (i = 0; i < ARRAY_SIZE(pol->rm_bit_field); i++)
+ pol->rm_bit_field[i] = args.args[i + 1];
+
+ return 0;
+}
+
+static int vip_probe_complete(struct platform_device *pdev)
+{
+ struct vip_shared *shared = platform_get_drvdata(pdev);
+ struct vip_clk_polarity *pol;
+ struct vip_port *port;
+ struct vip_dev *dev;
+ struct device_node *parent = pdev->dev.of_node;
+ struct fwnode_handle *ep, *port_node;
+ const char *port_name;
+ int ret, slice_id, port_id, p;
+
+ pol = devm_kzalloc(&pdev->dev, sizeof(*pol), GFP_KERNEL);
+ if (!pol)
+ return -ENOMEM;
+
+ ret = vip_get_clk_polarity(pdev, pol);
+ if (ret)
+ return ret;
+
+ for (p = 0; p < (VIP_NUM_PORTS * VIP_NUM_SLICES); p++) {
+ ep = fwnode_graph_get_next_endpoint_by_regs(of_fwnode_handle(parent),
+ p, 0);
+ if (!ep)
+ continue;
+
+ port_node = fwnode_get_parent(ep);
+ if (!port_node) {
+ dev_err(&pdev->dev, "can't get port of ep(%s)\n",
+ ep->ops->get_name(ep));
+ fwnode_handle_put(ep);
+ return -EINVAL;
+ }
+
+ port_name = vip_parse_fwnode_label(port_node);
+ if (IS_ERR_OR_NULL(port_name)) {
+ dev_err(&pdev->dev, "can't get label of port(%s)\n",
+ port_node->ops->get_name(port_node));
+ fwnode_handle_put(ep);
+ fwnode_handle_put(port_node);
+ return PTR_ERR(port_name);
+ }
+
+ switch (p) {
+ case 0:
+ slice_id = VIP_SLICE1; port_id = VIP_PORTA;
+ break;
+ case 1:
+ slice_id = VIP_SLICE1; port_id = VIP_PORTB;
+ break;
+ case 2:
+ slice_id = VIP_SLICE2; port_id = VIP_PORTA;
+ break;
+ case 3:
+ slice_id = VIP_SLICE2; port_id = VIP_PORTB;
+ break;
+ default:
+ dev_err(&pdev->dev, "Unknown port reg=<%d>\n", p);
+ continue;
+ }
+
+ ret = alloc_port(shared->devs[slice_id], port_id, port_name);
+ if (ret < 0)
+ continue;
+
+ dev = shared->devs[slice_id];
+ dev->pclk_pol = pol;
+ port = dev->ports[port_id];
+
+ vip_register_subdev_notif(port, ep);
+ fwnode_handle_put(ep);
+ fwnode_handle_put(port_node);
+ }
+ return 0;
+}
+
+static int vip_probe_slice(struct platform_device *pdev, int slice)
+{
+ struct vip_shared *shared = platform_get_drvdata(pdev);
+ struct vip_dev *dev;
+ struct vip_parser_data *parser;
+ int ret;
+
+ dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
+ if (!dev)
+ return -ENOMEM;
+
+ snprintf(dev->name, sizeof(dev->name), "%ss%d", shared->name, slice);
+
+ dev->irq = platform_get_irq(pdev, slice);
+ if (dev->irq < 0)
+ return dev->irq;
+
+ ret = devm_request_irq(&pdev->dev, dev->irq, vip_irq,
+ 0, dev->name, dev);
+ if (ret < 0)
+ return -ENOMEM;
+
+ spin_lock_init(&dev->slock);
+ mutex_init(&dev->mutex);
+
+ dev->slice_id = slice;
+ dev->pdev = pdev;
+ dev->res = shared->res;
+ dev->base = shared->base;
+ dev->v4l2_dev = &shared->v4l2_dev;
+
+ dev->shared = shared;
+ shared->devs[slice] = dev;
+
+ vip_top_reset(dev);
+ vip_set_slice_path(dev, VIP_MULTI_CHANNEL_DATA_SELECT, 1);
+
+ parser = devm_kzalloc(&pdev->dev, sizeof(*dev->parser), GFP_KERNEL);
+ if (!parser)
+ return PTR_ERR(parser);
+
+ parser->res = platform_get_resource_byname(pdev,
+ IORESOURCE_MEM,
+ (slice == 0) ?
+ "parser0" :
+ "parser1");
+ parser->base = devm_ioremap_resource(&pdev->dev, parser->res);
+ if (IS_ERR(parser->base))
+ return PTR_ERR(parser->base);
+
+ parser->pdev = pdev;
+ dev->parser = parser;
+
+ dev->sc_assigned = VIP_NOT_ASSIGNED;
+ dev->sc = sc_create(pdev, (slice == 0) ? "sc0" : "sc1");
+ if (IS_ERR(dev->sc))
+ return PTR_ERR(dev->sc);
+
+ dev->csc_assigned = VIP_NOT_ASSIGNED;
+ dev->csc = csc_create(pdev, (slice == 0) ? "csc0" : "csc1");
+ if (IS_ERR(dev->sc))
+ return PTR_ERR(dev->sc);
+
+ return 0;
+}
+
+static int vip_probe(struct platform_device *pdev)
+{
+ struct vip_shared *shared;
+ struct pinctrl *pinctrl;
+ int ret, slice = VIP_SLICE1;
+ u32 tmp, pid;
+ const char *instance_name;
+ struct fwnode_handle *fwnode;
+
+ fwnode = of_fwnode_handle(pdev->dev.of_node);
+ if (!fwnode)
+ return -ENODEV;
+
+ instance_name = vip_parse_fwnode_label(fwnode);
+ if (IS_ERR_OR_NULL(instance_name))
+ return PTR_ERR(instance_name);
+
+ /* If there are no endpoint defined there is nothing to do */
+ if (!vip_endpoint_scan(pdev))
+ return -ENODEV;
+
+ ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
+ if (ret) {
+ dev_err(&pdev->dev,
+ "32-bit consistent DMA enable failed\n");
+ return ret;
+ }
+
+ shared = devm_kzalloc(&pdev->dev, sizeof(*shared), GFP_KERNEL);
+ if (!shared)
+ return -ENOMEM;
+
+ shared->res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vip");
+ shared->base = devm_ioremap_resource(&pdev->dev, shared->res);
+ if (IS_ERR(shared->base))
+ return PTR_ERR(shared->base);
+
+ shared->name = instance_name;
+
+ vip_init_format_info(&pdev->dev);
+
+ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+
+ pm_runtime_enable(&pdev->dev);
+
+ ret = pm_runtime_get_sync(&pdev->dev);
+ if (ret)
+ goto err_runtime_disable;
+
+ /* Make sure H/W module has the right functionality */
+ pid = reg_read(shared, VIP_PID);
+ tmp = get_field(pid, VIP_PID_FUNC_MASK, VIP_PID_FUNC_SHIFT);
+
+ if (tmp != VIP_PID_FUNC) {
+ dev_info(&pdev->dev, "vip: unexpected PID function: 0x%x\n",
+ tmp);
+ ret = -ENODEV;
+ goto err_runtime_put;
+ }
+
+ ret = v4l2_device_register(&pdev->dev, &shared->v4l2_dev);
+ if (ret)
+ goto err_runtime_put;
+
+ /* enable clocks, so the firmware will load properly */
+ vip_shared_set_clock_enable(shared, 1);
+ vip_top_vpdma_reset(shared);
+
+ platform_set_drvdata(pdev, shared);
+
+ v4l2_ctrl_handler_init(&shared->ctrl_handler, 11);
+ shared->v4l2_dev.ctrl_handler = &shared->ctrl_handler;
+
+ for (slice = VIP_SLICE1; slice < VIP_NUM_SLICES; slice++) {
+ ret = vip_probe_slice(pdev, slice);
+ if (ret) {
+ dev_err(&pdev->dev, "Creating slice failed");
+ goto err_dev_unreg;
+ }
+ }
+
+ shared->vpdma = &shared->vpdma_data;
+ ret = vpdma_create(pdev, shared->vpdma, vip_vpdma_fw_cb);
+ if (ret) {
+ dev_err(&pdev->dev, "Creating VPDMA failed");
+ goto err_dev_unreg;
+ }
+
+ return 0;
+
+err_dev_unreg:
+ v4l2_ctrl_handler_free(&shared->ctrl_handler);
+ v4l2_device_unregister(&shared->v4l2_dev);
+err_runtime_put:
+ pm_runtime_put_sync(&pdev->dev);
+err_runtime_disable:
+ pm_runtime_disable(&pdev->dev);
+
+ return ret;
+}
+
+static int vip_remove(struct platform_device *pdev)
+{
+ struct vip_shared *shared = platform_get_drvdata(pdev);
+ struct vip_dev *dev;
+ int slice;
+
+ for (slice = 0; slice < VIP_NUM_SLICES; slice++) {
+ dev = shared->devs[slice];
+ if (!dev)
+ continue;
+
+ free_port(dev->ports[VIP_PORTA]);
+ free_port(dev->ports[VIP_PORTB]);
+ }
+
+ v4l2_ctrl_handler_free(&shared->ctrl_handler);
+
+ pm_runtime_put_sync(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+
+ return 0;
+}
+
+static const struct of_device_id vip_of_match[] = {
+ {
+ .compatible = "ti,dra7-vip",
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, vip_of_match);
+
+static struct platform_driver vip_pdrv = {
+ .probe = vip_probe,
+ .remove = vip_remove,
+ .driver = {
+ .name = VIP_MODULE_NAME,
+ .of_match_table = vip_of_match,
+ },
+};
+
+module_platform_driver(vip_pdrv);
+
+MODULE_DESCRIPTION("TI VIP driver");
+MODULE_AUTHOR("Texas Instruments");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/platform/ti-vpe/vip.h b/drivers/media/platform/ti-vpe/vip.h
new file mode 100644
index 000000000000..f078a16a85b7
--- /dev/null
+++ b/drivers/media/platform/ti-vpe/vip.h
@@ -0,0 +1,724 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * TI VIP capture driver
+ *
+ * Copyright (C) 2018 Texas Instruments Incorpated - http://www.ti.com/
+ * David Griego, <dagriego@biglakesoftware.com>
+ * Dale Farnsworth, <dale@farnsworth.org>
+ * Nikhil Devshatwar, <nikhil.nd@ti.com>
+ * Benoit Parrot, <bparrot@ti.com>
+ */
+
+#ifndef __TI_VIP_H
+#define __TI_VIP_H
+
+#include <linux/videodev2.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-ioctl.h>
+#include <media/videobuf2-core.h>
+#include <media/videobuf2-dma-contig.h>
+#include <media/videobuf2-memops.h>
+#include <media/v4l2-fwnode.h>
+
+#include "vpdma.h"
+#include "vpdma_priv.h"
+#include "sc.h"
+#include "csc.h"
+
+#define VIP_SLICE1 0
+#define VIP_SLICE2 1
+#define VIP_NUM_SLICES 2
+
+/*
+ * Additionnal client identifiers used for VPDMA configuration descriptors
+ */
+#define VIP_SLICE1_CFD_SC_CLIENT 7
+#define VIP_SLICE2_CFD_SC_CLIENT 8
+
+#define VIP_PORTA 0
+#define VIP_PORTB 1
+#define VIP_NUM_PORTS 2
+
+#define VIP_MAX_PLANES 2
+#define VIP_LUMA 0
+#define VIP_CHROMA 1
+
+#define VIP_CAP_STREAMS_PER_PORT 16
+#define VIP_VBI_STREAMS_PER_PORT 16
+
+#define VIP_MAX_SUBDEV 5
+/*
+ * This value needs to be at least as large as the number of entry in
+ * vip_formats[].
+ * When vip_formats[] is modified make sure to adjust this value also.
+ */
+#define VIP_MAX_ACTIVE_FMT 16
+/*
+ * Colorspace conversion unit can be in one of 3 modes:
+ * NA - Not Available on this port
+ * Y2R - Needed for YUV to RGB on this port
+ * R2Y - Needed for RGB to YUV on this port
+ */
+enum vip_csc_state {
+ VIP_CSC_NA = 0,
+ VIP_CSC_Y2R,
+ VIP_CSC_R2Y,
+};
+
+/* buffer for one video frame */
+struct vip_buffer {
+ /* common v4l buffer stuff */
+ struct vb2_v4l2_buffer vb;
+ struct list_head list;
+ bool drop;
+};
+
+/*
+ * struct vip_fmt - VIP media bus format information
+ * @fourcc: V4L2 pixel format FCC identifier
+ * @code: V4L2 media bus format code
+ * @colorspace: V4L2 colorspace identifier
+ * @coplanar: 1 if unpacked Luma and Chroma, 0 otherwise (packed/interleaved)
+ * @vpdma_fmt: VPDMA data format per plane.
+ * @finfo: Cache v4l2_format_info for associated fourcc
+ */
+struct vip_fmt {
+ u32 fourcc;
+ u32 code;
+ u32 colorspace;
+ u8 coplanar;
+ const struct vpdma_data_format *vpdma_fmt[VIP_MAX_PLANES];
+ const struct v4l2_format_info *finfo;
+};
+
+/*
+ * The vip_parser_data structures contains the memory mapped
+ * info to access the parser registers.
+ */
+struct vip_parser_data {
+ void __iomem *base;
+ struct resource *res;
+
+ struct platform_device *pdev;
+};
+
+/*
+ * The vip_shared structure contains data that is shared by both
+ * the VIP1 and VIP2 slices.
+ */
+struct vip_shared {
+ struct list_head list;
+ struct resource *res;
+ void __iomem *base;
+ struct vpdma_data vpdma_data;
+ struct vpdma_data *vpdma;
+ struct v4l2_device v4l2_dev;
+ struct vip_dev *devs[VIP_NUM_SLICES];
+ struct v4l2_ctrl_handler ctrl_handler;
+ const char *name;
+};
+
+/*
+ * The vip_bt656_bus structure contains vip specific bt656 bus data.
+ */
+struct vip_bt656_bus {
+ unsigned char num_channels;
+ unsigned char pixmux;
+ unsigned char channels[16];
+};
+
+/*
+ * The vip_clk_polarity structure contains the regmap, offset and bit field
+ * definitions to control each port clock polarity.
+ */
+struct vip_clk_polarity {
+ struct regmap *rm_pol;
+ u32 rm_offset;
+ u32 rm_bit_field[4];
+};
+/*
+ * There are two vip_dev structure, one for each vip slice: VIP1 & VIP2.
+ */
+struct vip_dev {
+ struct v4l2_device *v4l2_dev;
+ struct platform_device *pdev;
+ struct vip_shared *shared;
+ struct resource *res;
+ struct vip_clk_polarity *pclk_pol;
+ int slice_id;
+ int num_ports; /* count of open ports */
+ struct mutex mutex;
+ spinlock_t slock;
+
+ int irq;
+ void __iomem *base;
+
+ struct vip_port *ports[VIP_NUM_PORTS];
+
+ char name[16];
+ /* parser data handle */
+ struct vip_parser_data *parser;
+ /* scaler data handle */
+ struct sc_data *sc;
+ /* scaler port assignation */
+ int sc_assigned;
+ /* csc data handle */
+ struct csc_data *csc;
+ /* csc port assignation */
+ int csc_assigned;
+};
+
+/*
+ * There are two vip_port structures for each vip_dev, one for port A
+ * and one for port B.
+ */
+struct vip_port {
+ struct vip_dev *dev;
+ int port_id;
+
+ unsigned int flags;
+ struct v4l2_rect c_rect; /* crop rectangle */
+ struct v4l2_mbus_framefmt mbus_framefmt;
+ struct v4l2_mbus_framefmt try_mbus_framefmt;
+
+ const char *name;
+ struct vip_fmt *fmt; /* current format info */
+ /* Number of channels/streams configured */
+ int num_streams_configured;
+ int num_streams; /* count of open streams */
+ struct vip_stream *cap_streams[VIP_CAP_STREAMS_PER_PORT];
+
+ struct v4l2_async_notifier notifier;
+ struct v4l2_subdev *subdev;
+ struct v4l2_fwnode_endpoint endpoint;
+ struct vip_bt656_bus bt656_endpoint;
+ unsigned int source_pad;
+ struct vip_fmt *active_fmt[VIP_MAX_ACTIVE_FMT];
+ int num_active_fmt;
+ /* have new shadow reg values */
+ bool load_mmrs;
+ /* shadow reg addr/data block */
+ struct vpdma_buf mmr_adb;
+ /* h coeff buffer */
+ struct vpdma_buf sc_coeff_h;
+ /* v coeff buffer */
+ struct vpdma_buf sc_coeff_v;
+ /* Show if scaler resource is available on this port */
+ bool scaler;
+ /* Show the csc resource state on this port */
+ enum vip_csc_state csc;
+};
+
+/*
+ * When handling multiplexed video, there can be multiple streams for each
+ * port. The vip_stream structure holds per-stream data.
+ */
+struct vip_stream {
+ struct video_device *vfd;
+ struct vip_port *port;
+ int stream_id;
+ int list_num;
+ int vfl_type;
+ char name[16];
+ struct work_struct recovery_work;
+ int num_recovery;
+ enum v4l2_field field; /* current field */
+ unsigned int sequence; /* current frame/field seq */
+ enum v4l2_field sup_field; /* supported field value */
+ unsigned int width; /* frame width */
+ unsigned int height; /* frame height */
+ unsigned int bytesperline; /* bytes per line in memory */
+ unsigned int sizeimage; /* image size in memory */
+ struct list_head vidq; /* incoming vip_bufs queue */
+ struct list_head dropq; /* drop vip_bufs queue */
+ struct list_head post_bufs; /* vip_bufs to be DMAed */
+ /* Maintain a list of used channels - Needed for VPDMA cleanup */
+ int vpdma_channels[VPDMA_MAX_CHANNELS];
+ int vpdma_channels_to_abort[VPDMA_MAX_CHANNELS];
+ struct vpdma_desc_list desc_list; /* DMA descriptor list */
+ struct vpdma_dtd *write_desc;
+ /* next unused desc_list addr */
+ void *desc_next;
+ struct vb2_queue vb_vidq;
+};
+
+/*
+ * VIP Enumerations
+ */
+enum data_path_select {
+ ALL_FIELDS_DATA_SELECT = 0,
+ VIP_CSC_SRC_DATA_SELECT,
+ VIP_SC_SRC_DATA_SELECT,
+ VIP_RGB_SRC_DATA_SELECT,
+ VIP_RGB_OUT_LO_DATA_SELECT,
+ VIP_RGB_OUT_HI_DATA_SELECT,
+ VIP_CHR_DS_1_SRC_DATA_SELECT,
+ VIP_CHR_DS_2_SRC_DATA_SELECT,
+ VIP_MULTI_CHANNEL_DATA_SELECT,
+ VIP_CHR_DS_1_DATA_BYPASS,
+ VIP_CHR_DS_2_DATA_BYPASS,
+};
+
+
+enum data_interface_modes {
+ SINGLE_24B_INTERFACE = 0,
+ SINGLE_16B_INTERFACE = 1,
+ DUAL_8B_INTERFACE = 2,
+};
+
+enum sync_types {
+ EMBEDDED_SYNC_SINGLE_YUV422 = 0,
+ EMBEDDED_SYNC_2X_MULTIPLEXED_YUV422 = 1,
+ EMBEDDED_SYNC_4X_MULTIPLEXED_YUV422 = 2,
+ EMBEDDED_SYNC_LINE_MULTIPLEXED_YUV422 = 3,
+ DISCRETE_SYNC_SINGLE_YUV422 = 4,
+ EMBEDDED_SYNC_SINGLE_RGB_OR_YUV444 = 5,
+ DISCRETE_SYNC_SINGLE_RGB_24B = 10,
+};
+
+#define VIP_NOT_ASSIGNED -1
+
+/*
+ * Register offsets and field selectors
+ */
+#define VIP_PID_FUNC 0xf02
+
+#define VIP_PID 0x0000
+#define VIP_PID_MINOR_MASK 0x3f
+#define VIP_PID_MINOR_SHIFT 0
+#define VIP_PID_CUSTOM_MASK 0x03
+#define VIP_PID_CUSTOM_SHIFT 6
+#define VIP_PID_MAJOR_MASK 0x07
+#define VIP_PID_MAJOR_SHIFT 8
+#define VIP_PID_RTL_MASK 0x1f
+#define VIP_PID_RTL_SHIFT 11
+#define VIP_PID_FUNC_MASK 0xfff
+#define VIP_PID_FUNC_SHIFT 16
+#define VIP_PID_SCHEME_MASK 0x03
+#define VIP_PID_SCHEME_SHIFT 30
+
+#define VIP_SYSCONFIG 0x0010
+#define VIP_SYSCONFIG_IDLE_MASK 0x03
+#define VIP_SYSCONFIG_IDLE_SHIFT 2
+#define VIP_SYSCONFIG_STANDBY_MASK 0x03
+#define VIP_SYSCONFIG_STANDBY_SHIFT 4
+#define VIP_FORCE_IDLE_MODE 0
+#define VIP_NO_IDLE_MODE 1
+#define VIP_SMART_IDLE_MODE 2
+#define VIP_SMART_IDLE_WAKEUP_MODE 3
+#define VIP_FORCE_STANDBY_MODE 0
+#define VIP_NO_STANDBY_MODE 1
+#define VIP_SMART_STANDBY_MODE 2
+#define VIP_SMART_STANDBY_WAKEUP_MODE 3
+
+#define VIP_INTC_INTX_OFFSET 0x0020
+
+#define VIP_INT0_STATUS0_RAW_SET 0x0020
+#define VIP_INT0_STATUS0_RAW VIP_INT0_STATUS0_RAW_SET
+#define VIP_INT0_STATUS0_CLR 0x0028
+#define VIP_INT0_STATUS0 VIP_INT0_STATUS0_CLR
+#define VIP_INT0_ENABLE0_SET 0x0030
+#define VIP_INT0_ENABLE0 VIP_INT0_ENABLE0_SET
+#define VIP_INT0_ENABLE0_CLR 0x0038
+#define VIP_INT0_LIST0_COMPLETE BIT(0)
+#define VIP_INT0_LIST0_NOTIFY BIT(1)
+#define VIP_INT0_LIST1_COMPLETE BIT(2)
+#define VIP_INT0_LIST1_NOTIFY BIT(3)
+#define VIP_INT0_LIST2_COMPLETE BIT(4)
+#define VIP_INT0_LIST2_NOTIFY BIT(5)
+#define VIP_INT0_LIST3_COMPLETE BIT(6)
+#define VIP_INT0_LIST3_NOTIFY BIT(7)
+#define VIP_INT0_LIST4_COMPLETE BIT(8)
+#define VIP_INT0_LIST4_NOTIFY BIT(9)
+#define VIP_INT0_LIST5_COMPLETE BIT(10)
+#define VIP_INT0_LIST5_NOTIFY BIT(11)
+#define VIP_INT0_LIST6_COMPLETE BIT(12)
+#define VIP_INT0_LIST6_NOTIFY BIT(13)
+#define VIP_INT0_LIST7_COMPLETE BIT(14)
+#define VIP_INT0_LIST7_NOTIFY BIT(15)
+#define VIP_INT0_DESCRIPTOR BIT(16)
+#define VIP_VIP1_PARSER_INT BIT(20)
+#define VIP_VIP2_PARSER_INT BIT(21)
+
+#define VIP_INT0_STATUS1_RAW_SET 0x0024
+#define VIP_INT0_STATUS1_RAW VIP_INT0_STATUS0_RAW_SET
+#define VIP_INT0_STATUS1_CLR 0x002c
+#define VIP_INT0_STATUS1 VIP_INT0_STATUS0_CLR
+#define VIP_INT0_ENABLE1_SET 0x0034
+#define VIP_INT0_ENABLE1 VIP_INT0_ENABLE0_SET
+#define VIP_INT0_ENABLE1_CLR 0x003c
+#define VIP_INT0_ENABLE1_STAT 0x004c
+#define VIP_INT0_CHANNEL_GROUP0 BIT(0)
+#define VIP_INT0_CHANNEL_GROUP1 BIT(1)
+#define VIP_INT0_CHANNEL_GROUP2 BIT(2)
+#define VIP_INT0_CHANNEL_GROUP3 BIT(3)
+#define VIP_INT0_CHANNEL_GROUP4 BIT(4)
+#define VIP_INT0_CHANNEL_GROUP5 BIT(5)
+#define VIP_INT0_CLIENT BIT(7)
+#define VIP_VIP1_DS1_UV_ERROR_INT BIT(22)
+#define VIP_VIP1_DS2_UV_ERROR_INT BIT(23)
+#define VIP_VIP2_DS1_UV_ERROR_INT BIT(24)
+#define VIP_VIP2_DS2_UV_ERROR_INT BIT(25)
+
+#define VIP_INTC_E0I 0x00a0
+
+#define VIP_CLK_ENABLE 0x0100
+#define VIP_VPDMA_CLK_ENABLE BIT(0)
+#define VIP_VIP1_DATA_PATH_CLK_ENABLE BIT(16)
+#define VIP_VIP2_DATA_PATH_CLK_ENABLE BIT(17)
+
+#define VIP_CLK_RESET 0x0104
+#define VIP_VPDMA_RESET BIT(0)
+#define VIP_VPDMA_CLK_RESET_MASK 0x1
+#define VIP_VPDMA_CLK_RESET_SHIFT 0
+#define VIP_DATA_PATH_CLK_RESET_MASK 0x1
+#define VIP_VIP1_DATA_PATH_RESET_SHIFT 16
+#define VIP_VIP2_DATA_PATH_RESET_SHIFT 17
+#define VIP_VIP1_DATA_PATH_RESET BIT(16)
+#define VIP_VIP2_DATA_PATH_RESET BIT(17)
+#define VIP_VIP1_PARSER_RESET BIT(18)
+#define VIP_VIP2_PARSER_RESET BIT(19)
+#define VIP_VIP1_CSC_RESET BIT(20)
+#define VIP_VIP2_CSC_RESET BIT(21)
+#define VIP_VIP1_SC_RESET BIT(22)
+#define VIP_VIP2_SC_RESET BIT(23)
+#define VIP_VIP1_DS1_RESET BIT(25)
+#define VIP_VIP2_DS1_RESET BIT(26)
+#define VIP_VIP1_DS2_RESET BIT(27)
+#define VIP_VIP2_DS2_RESET BIT(28)
+#define VIP_MAIN_RESET BIT(31)
+
+#define VIP_VIP1_DATA_PATH_SELECT 0x010c
+#define VIP_VIP2_DATA_PATH_SELECT 0x0110
+#define VIP_CSC_SRC_SELECT_MASK 0x07
+#define VIP_CSC_SRC_SELECT_SHFT 0
+#define VIP_SC_SRC_SELECT_MASK 0x07
+#define VIP_SC_SRC_SELECT_SHFT 3
+#define VIP_RGB_SRC_SELECT BIT(6)
+#define VIP_RGB_OUT_LO_SRC_SELECT BIT(7)
+#define VIP_RGB_OUT_HI_SRC_SELECT BIT(8)
+#define VIP_DS1_SRC_SELECT_MASK 0x07
+#define VIP_DS1_SRC_SELECT_SHFT 9
+#define VIP_DS2_SRC_SELECT_MASK 0x07
+#define VIP_DS2_SRC_SELECT_SHFT 12
+#define VIP_MULTI_CHANNEL_SELECT BIT(15)
+#define VIP_DS1_BYPASS BIT(16)
+#define VIP_DS2_BYPASS BIT(17)
+#define VIP_TESTPORT_B_SELECT BIT(26)
+#define VIP_TESTPORT_A_SELECT BIT(27)
+#define VIP_DATAPATH_SELECT_MASK 0x0f
+#define VIP_DATAPATH_SELECT_SHFT 28
+
+#define VIP1_PARSER_REG_OFFSET 0x5500
+#define VIP2_PARSER_REG_OFFSET 0x5a00
+
+#define VIP_PARSER_MAIN_CFG 0x0000
+#define VIP_DATA_INTERFACE_MODE_MASK 0x03
+#define VIP_DATA_INTERFACE_MODE_SHFT 0
+#define VIP_CLIP_BLANK BIT(4)
+#define VIP_CLIP_ACTIVE BIT(5)
+
+#define VIP_PARSER_PORTA_0 0x0004
+#define VIP_PARSER_PORTB_0 0x000c
+#define VIP_SYNC_TYPE_MASK 0x0f
+#define VIP_SYNC_TYPE_SHFT 0
+#define VIP_CTRL_CHANNEL_SEL_MASK 0x03
+#define VIP_CTRL_CHANNEL_SEL_SHFT 4
+#define VIP_ASYNC_FIFO_WR BIT(6)
+#define VIP_ASYNC_FIFO_RD BIT(7)
+#define VIP_PORT_ENABLE BIT(8)
+#define VIP_FID_POLARITY BIT(9)
+#define VIP_PIXCLK_EDGE_POLARITY BIT(10)
+#define VIP_HSYNC_POLARITY BIT(11)
+#define VIP_VSYNC_POLARITY BIT(12)
+#define VIP_ACTVID_POLARITY BIT(13)
+#define VIP_FID_DETECT_MODE BIT(14)
+#define VIP_USE_ACTVID_HSYNC_ONLY BIT(15)
+#define VIP_FID_SKEW_PRECOUNT_MASK 0x3f
+#define VIP_FID_SKEW_PRECOUNT_SHFT 16
+#define VIP_DISCRETE_BASIC_MODE BIT(22)
+#define VIP_SW_RESET BIT(23)
+#define VIP_FID_SKEW_POSTCOUNT_MASK 0x3f
+#define VIP_FID_SKEW_POSTCOUNT_SHFT 24
+#define VIP_ANALYZER_2X4X_SRCNUM_POS BIT(30)
+#define VIP_ANALYZER_FVH_ERR_COR_EN BIT(31)
+
+#define VIP_PARSER_PORTA_1 0x0008
+#define VIP_PARSER_PORTB_1 0x0010
+#define VIP_SRC0_NUMLINES_MASK 0x0fff
+#define VIP_SRC0_NUMLINES_SHFT 0
+#define VIP_ANC_CHAN_SEL_8B_MASK 0x03
+#define VIP_ANC_CHAN_SEL_8B_SHFT 13
+#define VIP_SRC0_NUMPIX_MASK 0x0fff
+#define VIP_SRC0_NUMPIX_SHFT 16
+#define VIP_REPACK_SEL_MASK 0x07
+#define VIP_REPACK_SEL_SHFT 28
+
+#define VIP_PARSER_FIQ_MASK 0x0014
+#define VIP_PARSER_FIQ_CLR 0x0018
+#define VIP_PARSER_FIQ_STATUS 0x001c
+#define VIP_PORTA_VDET BIT(0)
+#define VIP_PORTB_VDET BIT(1)
+#define VIP_PORTA_ASYNC_FIFO_OF BIT(2)
+#define VIP_PORTB_ASYNC_FIFO_OF BIT(3)
+#define VIP_PORTA_OUTPUT_FIFO_YUV BIT(4)
+#define VIP_PORTA_OUTPUT_FIFO_ANC BIT(6)
+#define VIP_PORTB_OUTPUT_FIFO_YUV BIT(7)
+#define VIP_PORTB_OUTPUT_FIFO_ANC BIT(9)
+#define VIP_PORTA_CONN BIT(10)
+#define VIP_PORTA_DISCONN BIT(11)
+#define VIP_PORTB_CONN BIT(12)
+#define VIP_PORTB_DISCONN BIT(13)
+#define VIP_PORTA_SRC0_SIZE BIT(14)
+#define VIP_PORTB_SRC0_SIZE BIT(15)
+#define VIP_PORTA_YUV_PROTO_VIOLATION BIT(16)
+#define VIP_PORTA_ANC_PROTO_VIOLATION BIT(17)
+#define VIP_PORTB_YUV_PROTO_VIOLATION BIT(18)
+#define VIP_PORTB_ANC_PROTO_VIOLATION BIT(19)
+#define VIP_PORTA_CFG_DISABLE_COMPLETE BIT(20)
+#define VIP_PORTB_CFG_DISABLE_COMPLETE BIT(21)
+
+#define VIP_PARSER_PORTA_SOURCE_FID 0x0020
+#define VIP_PARSER_PORTA_ENCODER_FID 0x0024
+#define VIP_PARSER_PORTB_SOURCE_FID 0x0028
+#define VIP_PARSER_PORTB_ENCODER_FID 0x002c
+
+#define VIP_PARSER_PORTA_SRC0_SIZE 0x0030
+#define VIP_PARSER_PORTB_SRC0_SIZE 0x0070
+#define VIP_SOURCE_HEIGHT_MASK 0x0fff
+#define VIP_SOURCE_HEIGHT_SHFT 0
+#define VIP_SOURCE_WIDTH_MASK 0x0fff
+#define VIP_SOURCE_WIDTH_SHFT 16
+
+#define VIP_PARSER_PORTA_VDET_VEC 0x00b0
+#define VIP_PARSER_PORTB_VDET_VEC 0x00b4
+
+#define VIP_PARSER_PORTA_EXTRA2 0x00b8
+#define VIP_PARSER_PORTB_EXTRA2 0x00c8
+#define VIP_ANC_SKIP_NUMPIX_MASK 0x0fff
+#define VIP_ANC_SKIP_NUMPIX_SHFT 0
+#define VIP_ANC_BYPASS BIT(15)
+#define VIP_ANC_USE_NUMPIX_MASK 0x0fff
+#define VIP_ANC_USE_NUMPIX_SHFT 16
+#define VIP_ANC_TARGET_SRCNUM_MASK 0x0f
+#define VIP_ANC_TARGET_SRCNUM_SHFT 28
+
+#define VIP_PARSER_PORTA_EXTRA3 0x00bc
+#define VIP_PARSER_PORTB_EXTRA3 0x00cc
+#define VIP_ANC_SKIP_NUMLINES_MASK 0x0fff
+#define VIP_ANC_SKIP_NUMLINES_SHFT 0
+#define VIP_ANC_USE_NUMLINES_MASK 0x0fff
+#define VIP_ANC_USE_NUMLINES_SHFT 16
+
+#define VIP_PARSER_PORTA_EXTRA4 0x00c0
+#define VIP_PARSER_PORTB_EXTRA4 0x00d0
+#define VIP_ACT_SKIP_NUMPIX_MASK 0x0fff
+#define VIP_ACT_SKIP_NUMPIX_SHFT 0
+#define VIP_ACT_BYPASS BIT(15)
+#define VIP_ACT_USE_NUMPIX_MASK 0x0fff
+#define VIP_ACT_USE_NUMPIX_SHFT 16
+#define VIP_ACT_TARGET_SRCNUM_MASK 0x0f
+#define VIP_ACT_TARGET_SRCNUM_SHFT 28
+
+#define VIP_PARSER_PORTA_EXTRA5 0x00c4
+#define VIP_PARSER_PORTB_EXTRA5 0x00d4
+#define VIP_ACT_SKIP_NUMLINES_MASK 0x0fff
+#define VIP_ACT_SKIP_NUMLINES_SHFT 0
+#define VIP_ACT_USE_NUMLINES_MASK 0x0fff
+#define VIP_ACT_USE_NUMLINES_SHFT 16
+
+#define VIP_PARSER_PORTA_EXTRA6 0x00d8
+#define VIP_PARSER_PORTB_EXTRA6 0x00dc
+#define VIP_ANC_SRCNUM_STOP_IMM_SHFT 0
+#define VIP_YUV_SRCNUM_STOP_IMM_SHFT 16
+
+#define VIP_CSC_CSC00 0x0200
+#define VIP_CSC_A0_MASK 0x1fff
+#define VIP_CSC_A0_SHFT 0
+#define VIP_CSC_B0_MASK 0x1fff
+#define VIP_CSC_B0_SHFT 16
+
+#define VIP_CSC_CSC01 0x0204
+#define VIP_CSC_C0_MASK 0x1fff
+#define VIP_CSC_C0_SHFT 0
+#define VIP_CSC_A1_MASK 0x1fff
+#define VIP_CSC_A1_SHFT 16
+
+#define VIP_CSC_CSC02 0x0208
+#define VIP_CSC_B1_MASK 0x1fff
+#define VIP_CSC_B1_SHFT 0
+#define VIP_CSC_C1_MASK 0x1fff
+#define VIP_CSC_C1_SHFT 16
+
+#define VIP_CSC_CSC03 0x020c
+#define VIP_CSC_A2_MASK 0x1fff
+#define VIP_CSC_A2_SHFT 0
+#define VIP_CSC_B2_MASK 0x1fff
+#define VIP_CSC_B2_SHFT 16
+
+#define VIP_CSC_CSC04 0x0210
+#define VIP_CSC_C2_MASK 0x1fff
+#define VIP_CSC_C2_SHFT 0
+#define VIP_CSC_D0_MASK 0x0fff
+#define VIP_CSC_D0_SHFT 16
+
+#define VIP_CSC_CSC05 0x0214
+#define VIP_CSC_D1_MASK 0x0fff
+#define VIP_CSC_D1_SHFT 0
+#define VIP_CSC_D2_MASK 0x0fff
+#define VIP_CSC_D2_SHFT 16
+#define VIP_CSC_BYPASS BIT(28)
+
+#define VIP_SC_MP_SC0 0x0300
+#define VIP_INTERLACE_O BIT(0)
+#define VIP_LINEAR BIT(1)
+#define VIP_SC_BYPASS BIT(2)
+#define VIP_INVT_FID BIT(3)
+#define VIP_USE_RAV BIT(4)
+#define VIP_ENABLE_EV BIT(5)
+#define VIP_AUTH_HS BIT(6)
+#define VIP_DCM_2X BIT(7)
+#define VIP_DCM_4X BIT(8)
+#define VIP_HP_BYPASS BIT(9)
+#define VIP_INTERLACE_I BIT(10)
+#define VIP_ENABLE_SIN2_VER_INTP BIT(11)
+#define VIP_Y_PK_EN BIT(14)
+#define VIP_TRIM BIT(15)
+#define VIP_SELFGEN_FID BIT(16)
+
+#define VIP_SC_MP_SC1 0x0304
+#define VIP_ROW_ACC_INC_MASK 0x07ffffff
+#define VIP_ROW_ACC_INC_SHFT 0
+
+#define VIP_SC_MP_SC2 0x0308
+#define VIP_ROW_ACC_OFFSET_MASK 0x0fffffff
+#define VIP_ROW_ACC_OFFSET_SHFT 0
+
+#define VIP_SC_MP_SC3 0x030c
+#define VIP_ROW_ACC_OFFSET_B_MASK 0x0fffffff
+#define VIP_ROW_ACC_OFFSET_B_SHFT 0
+
+#define VIP_SC_MP_SC4 0x0310
+#define VIP_TAR_H_MASK 0x07ff
+#define VIP_TAR_H_SHFT 0
+#define VIP_TAR_W_MASK 0x07ff
+#define VIP_TAR_W_SHFT 12
+#define VIP_LIN_ACC_INC_U_MASK 0x07
+#define VIP_LIN_ACC_INC_U_SHFT 24
+#define VIP_NLIN_ACC_INIT_U_MASK 0x07
+#define VIP_NLIN_ACC_INIT_U_SHFT 28
+
+#define VIP_SC_MP_SC5 0x0314
+#define VIP_SRC_H_MASK 0x03ff
+#define VIP_SRC_H_SHFT 0
+#define VIP_SRC_W_MASK 0x07ff
+#define VIP_SRC_W_SHFT 12
+#define VIP_NLIN_ACC_INC_U_MASK 0x07
+#define VIP_NLIN_ACC_INC_U_SHFT 24
+
+#define VIP_SC_MP_SC6 0x0318
+#define VIP_ROW_ACC_INIT_RAV_MASK 0x03ff
+#define VIP_ROW_ACC_INIT_RAV_SHFT 0
+#define VIP_ROW_ACC_INIT_RAV_B_MASK 0x03ff
+#define VIP_ROW_ACC_INIT_RAV_B_SHFT 10
+
+#define VIP_SC_MP_SC8 0x0320
+#define VIP_NLIN_LEFT_MASK 0x07ff
+#define VIP_NLIN_LEFT_SHFT 0
+#define VIP_NLIN_RIGHT_MASK 0x07ff
+#define VIP_NLIN_RIGHT_SHFT 12
+
+#define VIP_SC_MP_SC9 0x0324
+#define VIP_LIN_ACC_INC VIP_SC_MP_SC9
+
+#define VIP_SC_MP_SC10 0x0328
+#define VIP_NLIN_ACC_INIT VIP_SC_MP_SC10
+
+#define VIP_SC_MP_SC11 0x032c
+#define VIP_NLIN_ACC_INC VIP_SC_MP_SC11
+
+#define VIP_SC_MP_SC12 0x0330
+#define VIP_COL_ACC_OFFSET_MASK 0x01ffffff
+#define VIP_COL_ACC_OFFSET_SHFT 0
+
+#define VIP_SC_MP_SC13 0x0334
+#define VIP_SC_FACTOR_RAV_MASK 0x03ff
+#define VIP_SC_FACTOR_RAV_SHFT 0
+#define VIP_CHROMA_INTP_THR_MASK 0x03ff
+#define VIP_CHROMA_INTP_THR_SHFT 12
+#define VIP_DELTA_CHROMA_THR_MASK 0x0f
+#define VIP_DELTA_CHROMA_THR_SHFT 24
+
+#define VIP_SC_MP_SC17 0x0344
+#define VIP_EV_THR_MASK 0x03ff
+#define VIP_EV_THR_SHFT 12
+#define VIP_DELTA_LUMA_THR_MASK 0x0f
+#define VIP_DELTA_LUMA_THR_SHFT 24
+#define VIP_DELTA_EV_THR_MASK 0x0f
+#define VIP_DELTA_EV_THR_SHFT 28
+
+#define VIP_SC_MP_SC18 0x0348
+#define VIP_HS_FACTOR_MASK 0x03ff
+#define VIP_HS_FACTOR_SHFT 0
+#define VIP_CONF_DEFAULT_MASK 0x01ff
+#define VIP_CONF_DEFAULT_SHFT 16
+
+#define VIP_SC_MP_SC19 0x034c
+#define VIP_HPF_COEFF0_MASK 0xff
+#define VIP_HPF_COEFF0_SHFT 0
+#define VIP_HPF_COEFF1_MASK 0xff
+#define VIP_HPF_COEFF1_SHFT 8
+#define VIP_HPF_COEFF2_MASK 0xff
+#define VIP_HPF_COEFF2_SHFT 16
+#define VIP_HPF_COEFF3_MASK 0xff
+#define VIP_HPF_COEFF3_SHFT 23
+
+#define VIP_SC_MP_SC20 0x0350
+#define VIP_HPF_COEFF4_MASK 0xff
+#define VIP_HPF_COEFF4_SHFT 0
+#define VIP_HPF_COEFF5_MASK 0xff
+#define VIP_HPF_COEFF5_SHFT 8
+#define VIP_HPF_NORM_SHFT_MASK 0x07
+#define VIP_HPF_NORM_SHFT_SHFT 16
+#define VIP_NL_LIMIT_MASK 0x1ff
+#define VIP_NL_LIMIT_SHFT 20
+
+#define VIP_SC_MP_SC21 0x0354
+#define VIP_NL_LO_THR_MASK 0x01ff
+#define VIP_NL_LO_THR_SHFT 0
+#define VIP_NL_LO_SLOPE_MASK 0xff
+#define VIP_NL_LO_SLOPE_SHFT 16
+
+#define VIP_SC_MP_SC22 0x0358
+#define VIP_NL_HI_THR_MASK 0x01ff
+#define VIP_NL_HI_THR_SHFT 0
+#define VIP_NL_HI_SLOPE_SH_MASK 0x07
+#define VIP_NL_HI_SLOPE_SH_SHFT 16
+
+#define VIP_SC_MP_SC23 0x035c
+#define VIP_GRADIENT_THR_MASK 0x07ff
+#define VIP_GRADIENT_THR_SHFT 0
+#define VIP_GRADIENT_THR_RANGE_MASK 0x0f
+#define VIP_GRADIENT_THR_RANGE_SHFT 12
+#define VIP_MIN_GY_THR_MASK 0xff
+#define VIP_MIN_GY_THR_SHFT 16
+#define VIP_MIN_GY_THR_RANGE_MASK 0x0f
+#define VIP_MIN_GY_THR_RANGE_SHFT 28
+
+#define VIP_SC_MP_SC24 0x0360
+#define VIP_ORG_H_MASK 0x07ff
+#define VIP_ORG_H_SHFT 0
+#define VIP_ORG_W_MASK 0x07ff
+#define VIP_ORG_W_SHFT 16
+
+#define VIP_SC_MP_SC25 0x0364
+#define VIP_OFF_H_MASK 0x07ff
+#define VIP_OFF_H_SHFT 0
+#define VIP_OFF_W_MASK 0x07ff
+#define VIP_OFF_W_SHFT 16
+
+#define VIP_VPDMA_REG_OFFSET 0xd000
+
+#endif
--
2.17.1
^ permalink raw reply related
* [Patch 0/2] media: ti-vpe: Add the VIP driver
From: Benoit Parrot @ 2020-05-22 22:54 UTC (permalink / raw)
To: Hans Verkuil, Rob Herring
Cc: linux-media, devicetree, linux-kernel, Benoit Parrot
This patch series add support for the TI VIP video capture engine.
VIP stands for Video Input Port, it can be found on devices such as
DRA7xx and provides a parallel interface to a video source such as
a sensor or TV decoder. Each VIP can support two inputs (slices) and
a SoC can be configured with a variable number of VIP's.
Each slice can support two ports each connected to its own
sub-device.
Here is the output of v4l2-compliance against this driver:
# v4l2-compliance -s -d 1
v4l2-compliance SHA: not available, 32 bits
Compliance test for vip device /dev/video1:
Driver name : vip
Card type : vip
Bus info : platform:vip1:vin2a:stream0
Driver version : 5.7.0
Capabilities : 0x85200001
Video Capture
Read/Write
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x05200001
Video Capture
Read/Write
Streaming
Extended Pix Format
Required ioctls:
test VIDIOC_QUERYCAP: OK
Allow for multiple opens:
test second /dev/video1 open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 1 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls (Input 0):
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
test VIDIOC_G/S/TRY_EXT_CTRLS: OK
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 5 Private Controls: 0
Format ioctls (Input 0):
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK
test Composing: OK
test Scaling: OK (Not Supported)
Codec ioctls (Input 0):
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls (Input 0):
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test VIDIOC_EXPBUF: OK
test Requests: OK (Not Supported)
Test input 0:
Streaming ioctls:
test read/write: OK
test blocking wait: OK
Video Capture: Frame #002 warn: v4l2-test-buffers.cpp(446): got sequence number 4, expected 3
Video Capture: Frame #005 warn: v4l2-test-buffers.cpp(446): got sequence number 8, expected 7
Video Capture: Frame #008 warn: v4l2-test-buffers.cpp(446): got sequence number 12, expected 11
Video Capture: Frame #011 warn: v4l2-test-buffers.cpp(446): got sequence number 16, expected 15
Video Capture: Frame #014 warn: v4l2-test-buffers.cpp(446): got sequence number 20, expected 19
Video Capture: Frame #017 warn: v4l2-test-buffers.cpp(446): got sequence number 24, expected 23
Video Capture: Frame #020 warn: v4l2-test-buffers.cpp(446): got sequence number 28, expected 27
Video Capture: Frame #023 warn: v4l2-test-buffers.cpp(446): got sequence number 32, expected 31
Video Capture: Frame #026 warn: v4l2-test-buffers.cpp(446): got sequence number 36, expected 35
Video Capture: Frame #029 warn: v4l2-test-buffers.cpp(446): got sequence number 40, expected 39
Video Capture: Frame #032 warn: v4l2-test-buffers.cpp(446): got sequence number 44, expected 43
Video Capture: Frame #035 warn: v4l2-test-buffers.cpp(446): got sequence number 48, expected 47
Video Capture: Frame #038 warn: v4l2-test-buffers.cpp(446): got sequence number 52, expected 51
Video Capture: Frame #041 warn: v4l2-test-buffers.cpp(446): got sequence number 56, expected 55
Video Capture: Frame #044 warn: v4l2-test-buffers.cpp(446): got sequence number 60, expected 59
Video Capture: Frame #047 warn: v4l2-test-buffers.cpp(446): got sequence number 64, expected 63
Video Capture: Frame #050 warn: v4l2-test-buffers.cpp(446): got sequence number 68, expected 67
Video Capture: Frame #053 warn: v4l2-test-buffers.cpp(446): got sequence number 72, expected 71
Video Capture: Frame #056 warn: v4l2-test-buffers.cpp(446): got sequence number 76, expected 75
test MMAP (no poll): OK
Video Capture: Frame #002 (select) warn: v4l2-test-buffers.cpp(446): got sequence number 4, expected 3
Video Capture: Frame #005 (select) warn: v4l2-test-buffers.cpp(446): got sequence number 8, expected 7
Video Capture: Frame #008 (select) warn: v4l2-test-buffers.cpp(446): got sequence number 12, expected 11
Video Capture: Frame #011 (select) warn: v4l2-test-buffers.cpp(446): got sequence number 16, expected 15
Video Capture: Frame #014 (select) warn: v4l2-test-buffers.cpp(446): got sequence number 20, expected 19
Video Capture: Frame #017 (select) warn: v4l2-test-buffers.cpp(446): got sequence number 24, expected 23
Video Capture: Frame #020 (select) warn: v4l2-test-buffers.cpp(446): got sequence number 28, expected 27
Video Capture: Frame #023 (select) warn: v4l2-test-buffers.cpp(446): got sequence number 32, expected 31
Video Capture: Frame #026 (select) warn: v4l2-test-buffers.cpp(446): got sequence number 36, expected 35
Video Capture: Frame #029 (select) warn: v4l2-test-buffers.cpp(446): got sequence number 40, expected 39
Video Capture: Frame #032 (select) warn: v4l2-test-buffers.cpp(446): got sequence number 44, expected 43
Video Capture: Frame #035 (select) warn: v4l2-test-buffers.cpp(446): got sequence number 48, expected 47
Video Capture: Frame #038 (select) warn: v4l2-test-buffers.cpp(446): got sequence number 52, expected 51
Video Capture: Frame #041 (select) warn: v4l2-test-buffers.cpp(446): got sequence number 56, expected 55
Video Capture: Frame #044 (select) warn: v4l2-test-buffers.cpp(446): got sequence number 60, expected 59
Video Capture: Frame #047 (select) warn: v4l2-test-buffers.cpp(446): got sequence number 64, expected 63
Video Capture: Frame #050 (select) warn: v4l2-test-buffers.cpp(446): got sequence number 68, expected 67
Video Capture: Frame #053 (select) warn: v4l2-test-buffers.cpp(446): got sequence number 72, expected 71
Video Capture: Frame #056 (select) warn: v4l2-test-buffers.cpp(446): got sequence number 76, expected 75
test MMAP (select): OK
Video Capture: Frame #002 (epoll) warn: v4l2-test-buffers.cpp(446): got sequence number 4, expected 3
Video Capture: Frame #005 (epoll) warn: v4l2-test-buffers.cpp(446): got sequence number 8, expected 7
Video Capture: Frame #008 (epoll) warn: v4l2-test-buffers.cpp(446): got sequence number 12, expected 11
Video Capture: Frame #011 (epoll) warn: v4l2-test-buffers.cpp(446): got sequence number 16, expected 15
Video Capture: Frame #014 (epoll) warn: v4l2-test-buffers.cpp(446): got sequence number 20, expected 19
Video Capture: Frame #017 (epoll) warn: v4l2-test-buffers.cpp(446): got sequence number 24, expected 23
Video Capture: Frame #020 (epoll) warn: v4l2-test-buffers.cpp(446): got sequence number 28, expected 27
Video Capture: Frame #023 (epoll) warn: v4l2-test-buffers.cpp(446): got sequence number 32, expected 31
Video Capture: Frame #026 (epoll) warn: v4l2-test-buffers.cpp(446): got sequence number 36, expected 35
Video Capture: Frame #029 (epoll) warn: v4l2-test-buffers.cpp(446): got sequence number 40, expected 39
Video Capture: Frame #032 (epoll) warn: v4l2-test-buffers.cpp(446): got sequence number 44, expected 43
Video Capture: Frame #035 (epoll) warn: v4l2-test-buffers.cpp(446): got sequence number 48, expected 47
Video Capture: Frame #038 (epoll) warn: v4l2-test-buffers.cpp(446): got sequence number 52, expected 51
Video Capture: Frame #041 (epoll) warn: v4l2-test-buffers.cpp(446): got sequence number 56, expected 55
Video Capture: Frame #044 (epoll) warn: v4l2-test-buffers.cpp(446): got sequence number 60, expected 59
Video Capture: Frame #047 (epoll) warn: v4l2-test-buffers.cpp(446): got sequence number 64, expected 63
Video Capture: Frame #050 (epoll) warn: v4l2-test-buffers.cpp(446): got sequence number 68, expected 67
Video Capture: Frame #053 (epoll) warn: v4l2-test-buffers.cpp(446): got sequence number 72, expected 71
Video Capture: Frame #056 (epoll) warn: v4l2-test-buffers.cpp(446): got sequence number 76, expected 75
test MMAP (epoll): OK
test USERPTR (no poll): OK (Not Supported)
test USERPTR (select): OK (Not Supported)
test DMABUF: Cannot test, specify --expbuf-device
Total for vip device /dev/video1: 51, Succeeded: 51, Failed: 0, Warnings: 57
Benoit Parrot (2):
dt-binbings: media: ti-vpe: Document the VIP driver
media: ti-vpe: Add the VIP driver
.../devicetree/bindings/media/ti,vip.yaml | 394 ++
MAINTAINERS | 1 +
drivers/media/platform/Kconfig | 13 +
drivers/media/platform/ti-vpe/Makefile | 2 +
drivers/media/platform/ti-vpe/vip.c | 4158 +++++++++++++++++
drivers/media/platform/ti-vpe/vip.h | 724 +++
6 files changed, 5292 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/ti,vip.yaml
create mode 100644 drivers/media/platform/ti-vpe/vip.c
create mode 100644 drivers/media/platform/ti-vpe/vip.h
--
2.17.1
^ permalink raw reply
* Re: [PATCH net-next v3 0/2] DP83869 Enhancements
From: David Miller @ 2020-05-22 23:13 UTC (permalink / raw)
To: dmurphy; +Cc: andrew, f.fainelli, hkallweit1, netdev, linux-kernel, devicetree
In-Reply-To: <20200521174738.3151-1-dmurphy@ti.com>
From: Dan Murphy <dmurphy@ti.com>
Date: Thu, 21 May 2020 12:47:36 -0500
> These are improvements to the DP83869 Ethernet PHY driver. OP-mode and port
> mirroring may be strapped on the device but the software only retrives these
> settings from the device tree. Reading the straps and initializing the
> associated stored variables so when setting the PHY up and down the PHY's
> configuration values will be retained.
Series applied, thank you.
^ permalink raw reply
* Re: [PATCH v5 06/11] net: ethernet: mtk-star-emac: new driver
From: Andrew Lunn @ 2020-05-22 23:36 UTC (permalink / raw)
To: Matthias Brugger
Cc: Bartosz Golaszewski, Rob Herring, David S . Miller, John Crispin,
Sean Wang, Mark Lee, Jakub Kicinski, Arnd Bergmann, Fabien Parent,
Heiner Kallweit, Edwin Peer, devicetree, Stephane Le Provost,
netdev, linux-kernel, Bartosz Golaszewski, linux-mediatek,
Andrew Perepech, Pedro Tsai, linux-arm-kernel
In-Reply-To: <5627e304-3463-9229-fa86-d7d31cad7a61@gmail.com>
On Fri, May 22, 2020 at 05:06:34PM +0200, Matthias Brugger wrote:
>
>
> On 22/05/2020 14:06, Bartosz Golaszewski wrote:
> > From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> >
> > This adds the driver for the MediaTek STAR Ethernet MAC currently used
> > on the MT8* SoC family. For now we only support full-duplex.
>
> MT85** SoC family, AFAIU it's not used on MT81** devices. Correct?
>
> >
> > Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> > ---
> > drivers/net/ethernet/mediatek/Kconfig | 7 +
> > drivers/net/ethernet/mediatek/Makefile | 1 +
> > drivers/net/ethernet/mediatek/mtk_star_emac.c | 1678 +++++++++++++++++
> > 3 files changed, 1686 insertions(+)
> > create mode 100644 drivers/net/ethernet/mediatek/mtk_star_emac.c
> >
> > diff --git a/drivers/net/ethernet/mediatek/Kconfig b/drivers/net/ethernet/mediatek/Kconfig
> > index 5079b8090f16..500c15e7ea4a 100644
> > --- a/drivers/net/ethernet/mediatek/Kconfig
> > +++ b/drivers/net/ethernet/mediatek/Kconfig
> > @@ -14,4 +14,11 @@ config NET_MEDIATEK_SOC
> > This driver supports the gigabit ethernet MACs in the
> > MediaTek SoC family.
> >
> > +config NET_MEDIATEK_STAR_EMAC
> > + tristate "MediaTek STAR Ethernet MAC support"
> > + select PHYLIB
> > + help
> > + This driver supports the ethernet MAC IP first used on
> > + MediaTek MT85** SoCs.
> > +
> > endif #NET_VENDOR_MEDIATEK
> > diff --git a/drivers/net/ethernet/mediatek/Makefile b/drivers/net/ethernet/mediatek/Makefile
> > index 3362fb7ef859..3a777b4a6cd3 100644
> > --- a/drivers/net/ethernet/mediatek/Makefile
> > +++ b/drivers/net/ethernet/mediatek/Makefile
> > @@ -5,3 +5,4 @@
> >
> > obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
> > mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o
> > +obj-$(CONFIG_NET_MEDIATEK_STAR_EMAC) += mtk_star_emac.o
> > diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c
> > new file mode 100644
> > index 000000000000..789c77af501f
> > --- /dev/null
> > +++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c
> > @@ -0,0 +1,1678 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2020 MediaTek Corporation
> > + * Copyright (c) 2020 BayLibre SAS
> > + *
> > + * Author: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> > + */
> > +
> > +#include <linux/bits.h>
> > +#include <linux/clk.h>
> > +#include <linux/compiler.h>
> > +#include <linux/dma-mapping.h>
> > +#include <linux/etherdevice.h>
> > +#include <linux/kernel.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/mii.h>
> > +#include <linux/module.h>
> > +#include <linux/netdevice.h>
> > +#include <linux/of.h>
> > +#include <linux/of_mdio.h>
> > +#include <linux/of_net.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm.h>
> > +#include <linux/regmap.h>
> > +#include <linux/skbuff.h>
> > +#include <linux/spinlock.h>
> > +#include <linux/workqueue.h>
> > +
> > +#define MTK_STAR_DRVNAME "mtk_star_emac"
> > +
> > +#define MTK_STAR_WAIT_TIMEOUT 300
> > +#define MTK_STAR_MAX_FRAME_SIZE 1514
> > +#define MTK_STAR_SKB_ALIGNMENT 16
> > +#define MTK_STAR_NAPI_WEIGHT 64
> > +#define MTK_STAR_HASHTABLE_MC_LIMIT 256
> > +#define MTK_STAR_HASHTABLE_SIZE_MAX 512
> > +
> > +/* Normally we'd use NET_IP_ALIGN but on arm64 its value is 0 and it doesn't
> > + * work for this controller.
> > + */
> > +#define MTK_STAR_IP_ALIGN 2
> > +
> > +static const char *const mtk_star_clk_names[] = { "core", "reg", "trans" };
> > +#define MTK_STAR_NCLKS ARRAY_SIZE(mtk_star_clk_names)
> > +
> > +/* PHY Control Register 0 */
> > +#define MTK_STAR_REG_PHY_CTRL0 0x0000
> > +#define MTK_STAR_BIT_PHY_CTRL0_WTCMD BIT(13)
> > +#define MTK_STAR_BIT_PHY_CTRL0_RDCMD BIT(14)
> > +#define MTK_STAR_BIT_PHY_CTRL0_RWOK BIT(15)
> > +#define MTK_STAR_MSK_PHY_CTRL0_PREG GENMASK(12, 8)
> > +#define MTK_STAR_OFF_PHY_CTRL0_PREG 8
> > +#define MTK_STAR_MSK_PHY_CTRL0_RWDATA GENMASK(31, 16)
> > +#define MTK_STAR_OFF_PHY_CTRL0_RWDATA 16
> > +
> > +/* PHY Control Register 1 */
> > +#define MTK_STAR_REG_PHY_CTRL1 0x0004
> > +#define MTK_STAR_BIT_PHY_CTRL1_LINK_ST BIT(0)
> > +#define MTK_STAR_BIT_PHY_CTRL1_AN_EN BIT(8)
> > +#define MTK_STAR_OFF_PHY_CTRL1_FORCE_SPD 9
> > +#define MTK_STAR_VAL_PHY_CTRL1_FORCE_SPD_10M 0x00
> > +#define MTK_STAR_VAL_PHY_CTRL1_FORCE_SPD_100M 0x01
> > +#define MTK_STAR_VAL_PHY_CTRL1_FORCE_SPD_1000M 0x02
> > +#define MTK_STAR_BIT_PHY_CTRL1_FORCE_DPX BIT(11)
> > +#define MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_RX BIT(12)
> > +#define MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_TX BIT(13)
> > +
> > +/* MAC Configuration Register */
> > +#define MTK_STAR_REG_MAC_CFG 0x0008
> > +#define MTK_STAR_OFF_MAC_CFG_IPG 10
> > +#define MTK_STAR_VAL_MAC_CFG_IPG_96BIT GENMASK(4, 0)
> > +#define MTK_STAR_BIT_MAC_CFG_MAXLEN_1522 BIT(16)
> > +#define MTK_STAR_BIT_MAC_CFG_AUTO_PAD BIT(19)
> > +#define MTK_STAR_BIT_MAC_CFG_CRC_STRIP BIT(20)
> > +#define MTK_STAR_BIT_MAC_CFG_VLAN_STRIP BIT(22)
> > +#define MTK_STAR_BIT_MAC_CFG_NIC_PD BIT(31)
> > +
> > +/* Flow-Control Configuration Register */
> > +#define MTK_STAR_REG_FC_CFG 0x000c
> > +#define MTK_STAR_BIT_FC_CFG_BP_EN BIT(7)
> > +#define MTK_STAR_BIT_FC_CFG_UC_PAUSE_DIR BIT(8)
> > +#define MTK_STAR_OFF_FC_CFG_SEND_PAUSE_TH 16
> > +#define MTK_STAR_MSK_FC_CFG_SEND_PAUSE_TH GENMASK(27, 16)
> > +#define MTK_STAR_VAL_FC_CFG_SEND_PAUSE_TH_2K 0x800
> > +
> > +/* ARL Configuration Register */
> > +#define MTK_STAR_REG_ARL_CFG 0x0010
> > +#define MTK_STAR_BIT_ARL_CFG_HASH_ALG BIT(0)
> > +#define MTK_STAR_BIT_ARL_CFG_MISC_MODE BIT(4)
> > +
> > +/* MAC High and Low Bytes Registers */
> > +#define MTK_STAR_REG_MY_MAC_H 0x0014
> > +#define MTK_STAR_REG_MY_MAC_L 0x0018
> > +
> > +/* Hash Table Control Register */
> > +#define MTK_STAR_REG_HASH_CTRL 0x001c
> > +#define MTK_STAR_MSK_HASH_CTRL_HASH_BIT_ADDR GENMASK(8, 0)
> > +#define MTK_STAR_BIT_HASH_CTRL_HASH_BIT_DATA BIT(12)
> > +#define MTK_STAR_BIT_HASH_CTRL_ACC_CMD BIT(13)
> > +#define MTK_STAR_BIT_HASH_CTRL_CMD_START BIT(14)
> > +#define MTK_STAR_BIT_HASH_CTRL_BIST_OK BIT(16)
> > +#define MTK_STAR_BIT_HASH_CTRL_BIST_DONE BIT(17)
> > +#define MTK_STAR_BIT_HASH_CTRL_BIST_EN BIT(31)
> > +
> > +/* TX DMA Control Register */
> > +#define MTK_STAR_REG_TX_DMA_CTRL 0x0034
> > +#define MTK_STAR_BIT_TX_DMA_CTRL_START BIT(0)
> > +#define MTK_STAR_BIT_TX_DMA_CTRL_STOP BIT(1)
> > +#define MTK_STAR_BIT_TX_DMA_CTRL_RESUME BIT(2)
> > +
> > +/* RX DMA Control Register */
> > +#define MTK_STAR_REG_RX_DMA_CTRL 0x0038
> > +#define MTK_STAR_BIT_RX_DMA_CTRL_START BIT(0)
> > +#define MTK_STAR_BIT_RX_DMA_CTRL_STOP BIT(1)
> > +#define MTK_STAR_BIT_RX_DMA_CTRL_RESUME BIT(2)
> > +
> > +/* DMA Address Registers */
> > +#define MTK_STAR_REG_TX_DPTR 0x003c
> > +#define MTK_STAR_REG_RX_DPTR 0x0040
> > +#define MTK_STAR_REG_TX_BASE_ADDR 0x0044
> > +#define MTK_STAR_REG_RX_BASE_ADDR 0x0048
> > +
> > +/* Interrupt Status Register */
> > +#define MTK_STAR_REG_INT_STS 0x0050
> > +#define MTK_STAR_REG_INT_STS_PORT_STS_CHG BIT(2)
> > +#define MTK_STAR_REG_INT_STS_MIB_CNT_TH BIT(3)
> > +#define MTK_STAR_BIT_INT_STS_FNRC BIT(6)
> > +#define MTK_STAR_BIT_INT_STS_TNTC BIT(8)
> > +
> > +/* Interrupt Mask Register */
> > +#define MTK_STAR_REG_INT_MASK 0x0054
> > +#define MTK_STAR_BIT_INT_MASK_FNRC BIT(6)
> > +
> > +/* Misc. Config Register */
> > +#define MTK_STAR_REG_TEST1 0x005c
> > +#define MTK_STAR_BIT_TEST1_RST_HASH_MBIST BIT(31)
> > +
> > +/* Extended Configuration Register */
> > +#define MTK_STAR_REG_EXT_CFG 0x0060
> > +#define MTK_STAR_OFF_EXT_CFG_SND_PAUSE_RLS 16
> > +#define MTK_STAR_MSK_EXT_CFG_SND_PAUSE_RLS GENMASK(26, 16)
> > +#define MTK_STAR_VAL_EXT_CFG_SND_PAUSE_RLS_1K 0x400
> > +
> > +/* EthSys Configuration Register */
> > +#define MTK_STAR_REG_SYS_CONF 0x0094
> > +#define MTK_STAR_BIT_MII_PAD_OUT_ENABLE BIT(0)
> > +#define MTK_STAR_BIT_EXT_MDC_MODE BIT(1)
> > +#define MTK_STAR_BIT_SWC_MII_MODE BIT(2)
> > +
> > +/* MAC Clock Configuration Register */
> > +#define MTK_STAR_REG_MAC_CLK_CONF 0x00ac
> > +#define MTK_STAR_MSK_MAC_CLK_CONF GENMASK(7, 0)
> > +#define MTK_STAR_BIT_CLK_DIV_10 0x0a
> > +
> > +/* Counter registers. */
> > +#define MTK_STAR_REG_C_RXOKPKT 0x0100
> > +#define MTK_STAR_REG_C_RXOKBYTE 0x0104
> > +#define MTK_STAR_REG_C_RXRUNT 0x0108
> > +#define MTK_STAR_REG_C_RXLONG 0x010c
> > +#define MTK_STAR_REG_C_RXDROP 0x0110
> > +#define MTK_STAR_REG_C_RXCRC 0x0114
> > +#define MTK_STAR_REG_C_RXARLDROP 0x0118
> > +#define MTK_STAR_REG_C_RXVLANDROP 0x011c
> > +#define MTK_STAR_REG_C_RXCSERR 0x0120
> > +#define MTK_STAR_REG_C_RXPAUSE 0x0124
> > +#define MTK_STAR_REG_C_TXOKPKT 0x0128
> > +#define MTK_STAR_REG_C_TXOKBYTE 0x012c
> > +#define MTK_STAR_REG_C_TXPAUSECOL 0x0130
> > +#define MTK_STAR_REG_C_TXRTY 0x0134
> > +#define MTK_STAR_REG_C_TXSKIP 0x0138
> > +#define MTK_STAR_REG_C_TX_ARP 0x013c
> > +#define MTK_STAR_REG_C_RX_RERR 0x01d8
> > +#define MTK_STAR_REG_C_RX_UNI 0x01dc
> > +#define MTK_STAR_REG_C_RX_MULTI 0x01e0
> > +#define MTK_STAR_REG_C_RX_BROAD 0x01e4
> > +#define MTK_STAR_REG_C_RX_ALIGNERR 0x01e8
> > +#define MTK_STAR_REG_C_TX_UNI 0x01ec
> > +#define MTK_STAR_REG_C_TX_MULTI 0x01f0
> > +#define MTK_STAR_REG_C_TX_BROAD 0x01f4
> > +#define MTK_STAR_REG_C_TX_TIMEOUT 0x01f8
> > +#define MTK_STAR_REG_C_TX_LATECOL 0x01fc
> > +#define MTK_STAR_REG_C_RX_LENGTHERR 0x0214
> > +#define MTK_STAR_REG_C_RX_TWIST 0x0218
> > +
> > +/* Ethernet CFG Control */
> > +#define MTK_PERICFG_REG_NIC_CFG_CON 0x03c4
> > +#define MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII GENMASK(3, 0)
> > +#define MTK_PERICFG_BIT_NIC_CFG_CON_RMII BIT(0)
> > +
> > +/* Represents the actual structure of descriptors used by the MAC. We can
> > + * reuse the same structure for both TX and RX - the layout is the same, only
> > + * the flags differ slightly.
> > + */
> > +struct mtk_star_ring_desc {
> > + /* Contains both the status flags as well as packet length. */
> > + u32 status;
> > + u32 data_ptr;
> > + u32 vtag;
> > + u32 reserved;
> > +};
> > +
> > +#define MTK_STAR_DESC_MSK_LEN GENMASK(15, 0)
> > +#define MTK_STAR_DESC_BIT_RX_CRCE BIT(24)
> > +#define MTK_STAR_DESC_BIT_RX_OSIZE BIT(25)
> > +#define MTK_STAR_DESC_BIT_INT BIT(27)
> > +#define MTK_STAR_DESC_BIT_LS BIT(28)
> > +#define MTK_STAR_DESC_BIT_FS BIT(29)
> > +#define MTK_STAR_DESC_BIT_EOR BIT(30)
> > +#define MTK_STAR_DESC_BIT_COWN BIT(31)
> > +
> > +/* Helper structure for storing data read from/written to descriptors in order
> > + * to limit reads from/writes to DMA memory.
> > + */
> > +struct mtk_star_ring_desc_data {
> > + unsigned int len;
> > + unsigned int flags;
> > + dma_addr_t dma_addr;
> > + struct sk_buff *skb;
> > +};
> > +
> > +#define MTK_STAR_RING_NUM_DESCS 128
> > +#define MTK_STAR_NUM_TX_DESCS MTK_STAR_RING_NUM_DESCS
> > +#define MTK_STAR_NUM_RX_DESCS MTK_STAR_RING_NUM_DESCS
> > +#define MTK_STAR_NUM_DESCS_TOTAL (MTK_STAR_RING_NUM_DESCS * 2)
> > +#define MTK_STAR_DMA_SIZE \
> > + (MTK_STAR_NUM_DESCS_TOTAL * sizeof(struct mtk_star_ring_desc))
> > +
> > +struct mtk_star_ring {
> > + struct mtk_star_ring_desc *descs;
> > + struct sk_buff *skbs[MTK_STAR_RING_NUM_DESCS];
> > + dma_addr_t dma_addrs[MTK_STAR_RING_NUM_DESCS];
> > + unsigned int head;
> > + unsigned int tail;
> > +};
> > +
> > +struct mtk_star_priv {
> > + struct net_device *ndev;
> > +
> > + struct regmap *regs;
> > + struct regmap *pericfg;
> > +
> > + struct clk_bulk_data clks[MTK_STAR_NCLKS];
> > +
> > + void *ring_base;
> > + struct mtk_star_ring_desc *descs_base;
> > + dma_addr_t dma_addr;
> > + struct mtk_star_ring tx_ring;
> > + struct mtk_star_ring rx_ring;
> > +
> > + struct mii_bus *mii;
> > + struct napi_struct napi;
> > +
> > + struct device_node *phy_node;
> > + phy_interface_t phy_intf;
> > + struct phy_device *phydev;
> > + unsigned int link;
> > + int speed;
> > + int duplex;
> > + int pause;
> > +
> > + /* Protects against concurrent descriptor access. */
> > + spinlock_t lock;
> > +
> > + struct rtnl_link_stats64 stats;
> > + struct work_struct stats_work;
> > +};
> > +
> > +static struct device *mtk_star_get_dev(struct mtk_star_priv *priv)
> > +{
> > + return priv->ndev->dev.parent;
> > +}
> > +
> > +static const struct regmap_config mtk_star_regmap_config = {
> > + .reg_bits = 32,
> > + .val_bits = 32,
> > + .reg_stride = 4,
> > + .disable_locking = true,
> > +};
> > +
> > +static void mtk_star_ring_init(struct mtk_star_ring *ring,
> > + struct mtk_star_ring_desc *descs)
> > +{
> > + memset(ring, 0, sizeof(*ring));
> > + ring->descs = descs;
> > + ring->head = 0;
> > + ring->tail = 0;
> > +}
> > +
> > +static int mtk_star_ring_pop_tail(struct mtk_star_ring *ring,
> > + struct mtk_star_ring_desc_data *desc_data)
> > +{
> > + struct mtk_star_ring_desc *desc = &ring->descs[ring->tail];
> > + unsigned int status;
> > +
> > + status = READ_ONCE(desc->status);
> > + dma_rmb(); /* Make sure we read the status bits before checking it. */
> > +
> > + if (!(status & MTK_STAR_DESC_BIT_COWN))
> > + return -1;
> > +
> > + desc_data->len = status & MTK_STAR_DESC_MSK_LEN;
> > + desc_data->flags = status & ~MTK_STAR_DESC_MSK_LEN;
> > + desc_data->dma_addr = ring->dma_addrs[ring->tail];
> > + desc_data->skb = ring->skbs[ring->tail];
> > +
> > + ring->dma_addrs[ring->tail] = 0;
> > + ring->skbs[ring->tail] = NULL;
> > +
> > + status &= MTK_STAR_DESC_BIT_COWN | MTK_STAR_DESC_BIT_EOR;
> > +
> > + WRITE_ONCE(desc->data_ptr, 0);
> > + WRITE_ONCE(desc->status, status);
> > +
> > + ring->tail = (ring->tail + 1) % MTK_STAR_RING_NUM_DESCS;
> > +
> > + return 0;
> > +}
> > +
> > +static void mtk_star_ring_push_head(struct mtk_star_ring *ring,
> > + struct mtk_star_ring_desc_data *desc_data,
> > + unsigned int flags)
> > +{
> > + struct mtk_star_ring_desc *desc = &ring->descs[ring->head];
> > + unsigned int status;
> > +
> > + status = READ_ONCE(desc->status);
> > +
> > + ring->skbs[ring->head] = desc_data->skb;
> > + ring->dma_addrs[ring->head] = desc_data->dma_addr;
> > +
> > + status |= desc_data->len;
> > + if (flags)
> > + status |= flags;
> > +
> > + WRITE_ONCE(desc->data_ptr, desc_data->dma_addr);
> > + WRITE_ONCE(desc->status, status);
> > + status &= ~MTK_STAR_DESC_BIT_COWN;
> > + /* Flush previous modifications before ownership change. */
> > + dma_wmb();
> > + WRITE_ONCE(desc->status, status);
> > +
> > + ring->head = (ring->head + 1) % MTK_STAR_RING_NUM_DESCS;
> > +}
> > +
> > +static void
> > +mtk_star_ring_push_head_rx(struct mtk_star_ring *ring,
> > + struct mtk_star_ring_desc_data *desc_data)
> > +{
> > + mtk_star_ring_push_head(ring, desc_data, 0);
> > +}
> > +
> > +static void
> > +mtk_star_ring_push_head_tx(struct mtk_star_ring *ring,
> > + struct mtk_star_ring_desc_data *desc_data)
> > +{
> > + static const unsigned int flags = MTK_STAR_DESC_BIT_FS |
> > + MTK_STAR_DESC_BIT_LS |
> > + MTK_STAR_DESC_BIT_INT;
> > +
> > + mtk_star_ring_push_head(ring, desc_data, flags);
> > +}
> > +
> > +static unsigned int mtk_star_ring_num_used_descs(struct mtk_star_ring *ring)
> > +{
> > + return abs(ring->head - ring->tail);
> > +}
> > +
> > +static bool mtk_star_ring_full(struct mtk_star_ring *ring)
> > +{
> > + return mtk_star_ring_num_used_descs(ring) == MTK_STAR_RING_NUM_DESCS;
> > +}
> > +
> > +static bool mtk_star_ring_descs_available(struct mtk_star_ring *ring)
> > +{
> > + return mtk_star_ring_num_used_descs(ring) > 0;
> > +}
> > +
> > +static dma_addr_t mtk_star_dma_map_rx(struct mtk_star_priv *priv,
> > + struct sk_buff *skb)
> > +{
> > + struct device *dev = mtk_star_get_dev(priv);
> > +
> > + /* Data pointer for the RX DMA descriptor must be aligned to 4N + 2. */
> > + return dma_map_single(dev, skb_tail_pointer(skb) - 2,
> > + skb_tailroom(skb), DMA_FROM_DEVICE);
> > +}
> > +
> > +static void mtk_star_dma_unmap_rx(struct mtk_star_priv *priv,
> > + struct mtk_star_ring_desc_data *desc_data)
> > +{
> > + struct device *dev = mtk_star_get_dev(priv);
> > +
> > + dma_unmap_single(dev, desc_data->dma_addr,
> > + skb_tailroom(desc_data->skb), DMA_FROM_DEVICE);
> > +}
> > +
> > +static dma_addr_t mtk_star_dma_map_tx(struct mtk_star_priv *priv,
> > + struct sk_buff *skb)
> > +{
> > + struct device *dev = mtk_star_get_dev(priv);
> > +
> > + return dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
> > +}
> > +
> > +static void mtk_star_dma_unmap_tx(struct mtk_star_priv *priv,
> > + struct mtk_star_ring_desc_data *desc_data)
> > +{
> > + struct device *dev = mtk_star_get_dev(priv);
> > +
> > + return dma_unmap_single(dev, desc_data->dma_addr,
> > + skb_headlen(desc_data->skb), DMA_TO_DEVICE);
> > +}
> > +
> > +static void mtk_star_nic_disable_pd(struct mtk_star_priv *priv)
> > +{
> > + regmap_update_bits(priv->regs, MTK_STAR_REG_MAC_CFG,
> > + MTK_STAR_BIT_MAC_CFG_NIC_PD, 0);
> > +}
> > +
> > +/* Unmask the three interrupts we care about, mask all others. */
> > +static void mtk_star_intr_enable(struct mtk_star_priv *priv)
> > +{
> > + unsigned int val = MTK_STAR_BIT_INT_STS_TNTC |
> > + MTK_STAR_BIT_INT_STS_FNRC |
> > + MTK_STAR_REG_INT_STS_MIB_CNT_TH;
> > +
> > + regmap_write(priv->regs, MTK_STAR_REG_INT_MASK, ~val);
> > +}
> > +
> > +static void mtk_star_intr_disable(struct mtk_star_priv *priv)
> > +{
> > + regmap_write(priv->regs, MTK_STAR_REG_INT_MASK, ~0);
> > +}
> > +
> > +static void mtk_star_intr_enable_tx(struct mtk_star_priv *priv)
> > +{
> > + regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
> > + MTK_STAR_BIT_INT_STS_TNTC, 0);
> > +}
> > +
> > +static void mtk_star_intr_enable_rx(struct mtk_star_priv *priv)
> > +{
> > + regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
> > + MTK_STAR_BIT_INT_STS_FNRC, 0);
> > +}
> > +
> > +static void mtk_star_intr_enable_stats(struct mtk_star_priv *priv)
> > +{
> > + regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
> > + MTK_STAR_REG_INT_STS_MIB_CNT_TH, 0);
> > +}
> > +
> > +static void mtk_star_intr_disable_tx(struct mtk_star_priv *priv)
> > +{
> > + regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
> > + MTK_STAR_BIT_INT_STS_TNTC,
> > + MTK_STAR_BIT_INT_STS_TNTC);
> > +}
> > +
> > +static void mtk_star_intr_disable_rx(struct mtk_star_priv *priv)
> > +{
> > + regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
> > + MTK_STAR_BIT_INT_STS_FNRC,
> > + MTK_STAR_BIT_INT_STS_FNRC);
> > +}
> > +
> > +static void mtk_star_intr_disable_stats(struct mtk_star_priv *priv)
> > +{
> > + regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
> > + MTK_STAR_REG_INT_STS_MIB_CNT_TH,
> > + MTK_STAR_REG_INT_STS_MIB_CNT_TH);
> > +}
> > +
> > +static unsigned int mtk_star_intr_read(struct mtk_star_priv *priv)
> > +{
> > + unsigned int val;
> > +
> > + regmap_read(priv->regs, MTK_STAR_REG_INT_STS, &val);
> > +
> > + return val;
> > +}
> > +
> > +static unsigned int mtk_star_intr_ack_all(struct mtk_star_priv *priv)
> > +{
> > + unsigned int val;
> > +
> > + val = mtk_star_intr_read(priv);
> > + regmap_write(priv->regs, MTK_STAR_REG_INT_STS, val);
> > +
> > + return val;
> > +}
> > +
> > +static void mtk_star_dma_init(struct mtk_star_priv *priv)
> > +{
> > + struct mtk_star_ring_desc *desc;
> > + unsigned int val;
> > + int i;
> > +
> > + priv->descs_base = (struct mtk_star_ring_desc *)priv->ring_base;
> > +
> > + for (i = 0; i < MTK_STAR_NUM_DESCS_TOTAL; i++) {
> > + desc = &priv->descs_base[i];
> > +
> > + memset(desc, 0, sizeof(*desc));
> > + desc->status = MTK_STAR_DESC_BIT_COWN;
> > + if ((i == MTK_STAR_NUM_TX_DESCS - 1) ||
> > + (i == MTK_STAR_NUM_DESCS_TOTAL - 1))
> > + desc->status |= MTK_STAR_DESC_BIT_EOR;
> > + }
> > +
> > + mtk_star_ring_init(&priv->tx_ring, priv->descs_base);
> > + mtk_star_ring_init(&priv->rx_ring,
> > + priv->descs_base + MTK_STAR_NUM_TX_DESCS);
> > +
> > + /* Set DMA pointers. */
> > + val = (unsigned int)priv->dma_addr;
> > + regmap_write(priv->regs, MTK_STAR_REG_TX_BASE_ADDR, val);
> > + regmap_write(priv->regs, MTK_STAR_REG_TX_DPTR, val);
> > +
> > + val += sizeof(struct mtk_star_ring_desc) * MTK_STAR_NUM_TX_DESCS;
> > + regmap_write(priv->regs, MTK_STAR_REG_RX_BASE_ADDR, val);
> > + regmap_write(priv->regs, MTK_STAR_REG_RX_DPTR, val);
> > +}
> > +
> > +static void mtk_star_dma_start(struct mtk_star_priv *priv)
> > +{
> > + regmap_update_bits(priv->regs, MTK_STAR_REG_TX_DMA_CTRL,
> > + MTK_STAR_BIT_TX_DMA_CTRL_START,
> > + MTK_STAR_BIT_TX_DMA_CTRL_START);
> > + regmap_update_bits(priv->regs, MTK_STAR_REG_RX_DMA_CTRL,
> > + MTK_STAR_BIT_RX_DMA_CTRL_START,
> > + MTK_STAR_BIT_RX_DMA_CTRL_START);
> > +}
> > +
> > +static void mtk_star_dma_stop(struct mtk_star_priv *priv)
> > +{
> > + regmap_write(priv->regs, MTK_STAR_REG_TX_DMA_CTRL,
> > + MTK_STAR_BIT_TX_DMA_CTRL_STOP);
> > + regmap_write(priv->regs, MTK_STAR_REG_RX_DMA_CTRL,
> > + MTK_STAR_BIT_RX_DMA_CTRL_STOP);
> > +}
> > +
> > +static void mtk_star_dma_disable(struct mtk_star_priv *priv)
> > +{
> > + int i;
> > +
> > + mtk_star_dma_stop(priv);
> > +
> > + /* Take back all descriptors. */
> > + for (i = 0; i < MTK_STAR_NUM_DESCS_TOTAL; i++)
> > + priv->descs_base[i].status |= MTK_STAR_DESC_BIT_COWN;
> > +}
> > +
> > +static void mtk_star_dma_resume_rx(struct mtk_star_priv *priv)
> > +{
> > + regmap_update_bits(priv->regs, MTK_STAR_REG_RX_DMA_CTRL,
> > + MTK_STAR_BIT_RX_DMA_CTRL_RESUME,
> > + MTK_STAR_BIT_RX_DMA_CTRL_RESUME);
> > +}
> > +
> > +static void mtk_star_dma_resume_tx(struct mtk_star_priv *priv)
> > +{
> > + regmap_update_bits(priv->regs, MTK_STAR_REG_TX_DMA_CTRL,
> > + MTK_STAR_BIT_TX_DMA_CTRL_RESUME,
> > + MTK_STAR_BIT_TX_DMA_CTRL_RESUME);
> > +}
> > +
> > +static void mtk_star_set_mac_addr(struct net_device *ndev)
> > +{
> > + struct mtk_star_priv *priv = netdev_priv(ndev);
> > + u8 *mac_addr = ndev->dev_addr;
> > + unsigned int high, low;
> > +
> > + high = mac_addr[0] << 8 | mac_addr[1] << 0;
> > + low = mac_addr[2] << 24 | mac_addr[3] << 16 |
> > + mac_addr[4] << 8 | mac_addr[5];
> > +
> > + regmap_write(priv->regs, MTK_STAR_REG_MY_MAC_H, high);
> > + regmap_write(priv->regs, MTK_STAR_REG_MY_MAC_L, low);
> > +}
> > +
> > +static void mtk_star_reset_counters(struct mtk_star_priv *priv)
> > +{
> > + static const unsigned int counter_regs[] = {
> > + MTK_STAR_REG_C_RXOKPKT,
> > + MTK_STAR_REG_C_RXOKBYTE,
> > + MTK_STAR_REG_C_RXRUNT,
> > + MTK_STAR_REG_C_RXLONG,
> > + MTK_STAR_REG_C_RXDROP,
> > + MTK_STAR_REG_C_RXCRC,
> > + MTK_STAR_REG_C_RXARLDROP,
> > + MTK_STAR_REG_C_RXVLANDROP,
> > + MTK_STAR_REG_C_RXCSERR,
> > + MTK_STAR_REG_C_RXPAUSE,
> > + MTK_STAR_REG_C_TXOKPKT,
> > + MTK_STAR_REG_C_TXOKBYTE,
> > + MTK_STAR_REG_C_TXPAUSECOL,
> > + MTK_STAR_REG_C_TXRTY,
> > + MTK_STAR_REG_C_TXSKIP,
> > + MTK_STAR_REG_C_TX_ARP,
> > + MTK_STAR_REG_C_RX_RERR,
> > + MTK_STAR_REG_C_RX_UNI,
> > + MTK_STAR_REG_C_RX_MULTI,
> > + MTK_STAR_REG_C_RX_BROAD,
> > + MTK_STAR_REG_C_RX_ALIGNERR,
> > + MTK_STAR_REG_C_TX_UNI,
> > + MTK_STAR_REG_C_TX_MULTI,
> > + MTK_STAR_REG_C_TX_BROAD,
> > + MTK_STAR_REG_C_TX_TIMEOUT,
> > + MTK_STAR_REG_C_TX_LATECOL,
> > + MTK_STAR_REG_C_RX_LENGTHERR,
> > + MTK_STAR_REG_C_RX_TWIST,
> > + };
> > +
> > + unsigned int i, val;
> > +
> > + for (i = 0; i < ARRAY_SIZE(counter_regs); i++)
> > + regmap_read(priv->regs, counter_regs[i], &val);
> > +}
> > +
> > +static void mtk_star_update_stat(struct mtk_star_priv *priv,
> > + unsigned int reg, u64 *stat)
> > +{
> > + unsigned int val;
> > +
> > + regmap_read(priv->regs, reg, &val);
> > + *stat += val;
> > +}
> > +
> > +/* Try to get as many stats as possible from the internal registers instead
> > + * of tracking them ourselves.
> > + */
> > +static void mtk_star_update_stats(struct mtk_star_priv *priv)
> > +{
> > + struct rtnl_link_stats64 *stats = &priv->stats;
> > +
> > + /* OK packets and bytes. */
> > + mtk_star_update_stat(priv, MTK_STAR_REG_C_RXOKPKT, &stats->rx_packets);
> > + mtk_star_update_stat(priv, MTK_STAR_REG_C_TXOKPKT, &stats->tx_packets);
> > + mtk_star_update_stat(priv, MTK_STAR_REG_C_RXOKBYTE, &stats->rx_bytes);
> > + mtk_star_update_stat(priv, MTK_STAR_REG_C_TXOKBYTE, &stats->tx_bytes);
> > +
> > + /* RX & TX multicast. */
> > + mtk_star_update_stat(priv, MTK_STAR_REG_C_RX_MULTI, &stats->multicast);
> > + mtk_star_update_stat(priv, MTK_STAR_REG_C_TX_MULTI, &stats->multicast);
> > +
> > + /* Collisions. */
> > + mtk_star_update_stat(priv, MTK_STAR_REG_C_TXPAUSECOL,
> > + &stats->collisions);
> > + mtk_star_update_stat(priv, MTK_STAR_REG_C_TX_LATECOL,
> > + &stats->collisions);
> > + mtk_star_update_stat(priv, MTK_STAR_REG_C_RXRUNT, &stats->collisions);
> > +
> > + /* RX Errors. */
> > + mtk_star_update_stat(priv, MTK_STAR_REG_C_RX_LENGTHERR,
> > + &stats->rx_length_errors);
> > + mtk_star_update_stat(priv, MTK_STAR_REG_C_RXLONG,
> > + &stats->rx_over_errors);
> > + mtk_star_update_stat(priv, MTK_STAR_REG_C_RXCRC, &stats->rx_crc_errors);
> > + mtk_star_update_stat(priv, MTK_STAR_REG_C_RX_ALIGNERR,
> > + &stats->rx_frame_errors);
> > + mtk_star_update_stat(priv, MTK_STAR_REG_C_RXDROP,
> > + &stats->rx_fifo_errors);
> > + /* Sum of the general RX error counter + all of the above. */
> > + mtk_star_update_stat(priv, MTK_STAR_REG_C_RX_RERR, &stats->rx_errors);
> > + stats->rx_errors += stats->rx_length_errors;
> > + stats->rx_errors += stats->rx_over_errors;
> > + stats->rx_errors += stats->rx_crc_errors;
> > + stats->rx_errors += stats->rx_frame_errors;
> > + stats->rx_errors += stats->rx_fifo_errors;
> > +}
> > +
> > +/* This runs in process context and parallel TX and RX paths executing in
> > + * napi context may result in losing some stats data but this should happen
> > + * seldom enough to be acceptable.
> > + */
> > +static void mtk_star_update_stats_work(struct work_struct *work)
> > +{
> > + struct mtk_star_priv *priv = container_of(work, struct mtk_star_priv,
> > + stats_work);
> > +
> > + mtk_star_update_stats(priv);
> > + mtk_star_reset_counters(priv);
> > + mtk_star_intr_enable_stats(priv);
> > +}
> > +
> > +static struct sk_buff *mtk_star_alloc_skb(struct net_device *ndev)
> > +{
> > + uintptr_t tail, offset;
> > + struct sk_buff *skb;
> > +
> > + skb = dev_alloc_skb(MTK_STAR_MAX_FRAME_SIZE);
> > + if (!skb)
> > + return NULL;
> > +
> > + /* Align to 16 bytes. */
> > + tail = (uintptr_t)skb_tail_pointer(skb);
> > + if (tail & (MTK_STAR_SKB_ALIGNMENT - 1)) {
> > + offset = tail & (MTK_STAR_SKB_ALIGNMENT - 1);
> > + skb_reserve(skb, MTK_STAR_SKB_ALIGNMENT - offset);
> > + }
> > +
> > + /* Ensure 16-byte alignment of the skb pointer: eth_type_trans() will
> > + * extract the Ethernet header (14 bytes) so we need two more bytes.
> > + */
> > + skb_reserve(skb, MTK_STAR_IP_ALIGN);
> > +
> > + return skb;
> > +}
> > +
> > +static int mtk_star_prepare_rx_skbs(struct net_device *ndev)
> > +{
> > + struct mtk_star_priv *priv = netdev_priv(ndev);
> > + struct mtk_star_ring *ring = &priv->rx_ring;
> > + struct device *dev = mtk_star_get_dev(priv);
> > + struct mtk_star_ring_desc *desc;
> > + struct sk_buff *skb;
> > + dma_addr_t dma_addr;
> > + int i;
> > +
> > + for (i = 0; i < MTK_STAR_NUM_RX_DESCS; i++) {
> > + skb = mtk_star_alloc_skb(ndev);
> > + if (!skb)
> > + return -ENOMEM;
> > +
> > + dma_addr = mtk_star_dma_map_rx(priv, skb);
> > + if (dma_mapping_error(dev, dma_addr)) {
> > + dev_kfree_skb(skb);
> > + return -ENOMEM;
> > + }
> > +
> > + desc = &ring->descs[i];
> > + desc->data_ptr = dma_addr;
> > + desc->status |= skb_tailroom(skb) & MTK_STAR_DESC_MSK_LEN;
> > + desc->status &= ~MTK_STAR_DESC_BIT_COWN;
> > + ring->skbs[i] = skb;
> > + ring->dma_addrs[i] = dma_addr;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static void
> > +mtk_star_ring_free_skbs(struct mtk_star_priv *priv, struct mtk_star_ring *ring,
> > + void (*unmap_func)(struct mtk_star_priv *,
> > + struct mtk_star_ring_desc_data *))
> > +{
> > + struct mtk_star_ring_desc_data desc_data;
> > + struct mtk_star_ring_desc *desc;
> > + int i;
> > +
> > + for (i = 0; i < MTK_STAR_RING_NUM_DESCS; i++) {
> > + if (!ring->dma_addrs[i])
> > + continue;
> > +
> > + desc = &ring->descs[i];
> > +
> > + desc_data.dma_addr = ring->dma_addrs[i];
> > + desc_data.skb = ring->skbs[i];
> > +
> > + unmap_func(priv, &desc_data);
> > + dev_kfree_skb(desc_data.skb);
> > + }
> > +}
> > +
> > +static void mtk_star_free_rx_skbs(struct mtk_star_priv *priv)
> > +{
> > + struct mtk_star_ring *ring = &priv->rx_ring;
> > +
> > + mtk_star_ring_free_skbs(priv, ring, mtk_star_dma_unmap_rx);
> > +}
> > +
> > +static void mtk_star_free_tx_skbs(struct mtk_star_priv *priv)
> > +{
> > + struct mtk_star_ring *ring = &priv->tx_ring;
> > +
> > + mtk_star_ring_free_skbs(priv, ring, mtk_star_dma_unmap_tx);
> > +}
> > +
> > +/* All processing for TX and RX happens in the napi poll callback. */
> > +static irqreturn_t mtk_star_handle_irq(int irq, void *data)
> > +{
> > + struct mtk_star_priv *priv;
> > + struct net_device *ndev;
> > + bool need_napi = false;
> > + unsigned int status;
> > +
> > + ndev = data;
> > + priv = netdev_priv(ndev);
> > +
> > + if (netif_running(ndev)) {
> > + status = mtk_star_intr_read(priv);
> > +
> > + if (status & MTK_STAR_BIT_INT_STS_TNTC) {
> > + mtk_star_intr_disable_tx(priv);
> > + need_napi = true;
> > + }
> > +
> > + if (status & MTK_STAR_BIT_INT_STS_FNRC) {
> > + mtk_star_intr_disable_rx(priv);
> > + need_napi = true;
> > + }
> > +
> > + if (need_napi)
> > + napi_schedule(&priv->napi);
> > +
> > + /* One of the counters reached 0x8000000 - update stats and
> > + * reset all counters.
> > + */
> > + if (unlikely(status & MTK_STAR_REG_INT_STS_MIB_CNT_TH)) {
> > + mtk_star_intr_disable_stats(priv);
> > + schedule_work(&priv->stats_work);
> > + }
> > +
> > + mtk_star_intr_ack_all(priv);
> > + }
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +/* Wait for the completion of any previous command - CMD_START bit must be
> > + * cleared by hardware.
> > + */
> > +static int mtk_star_hash_wait_cmd_start(struct mtk_star_priv *priv)
> > +{
> > + unsigned int val;
> > +
> > + return regmap_read_poll_timeout_atomic(priv->regs,
> > + MTK_STAR_REG_HASH_CTRL, val,
> > + !(val & MTK_STAR_BIT_HASH_CTRL_CMD_START),
> > + 10, MTK_STAR_WAIT_TIMEOUT);
> > +}
> > +
> > +static int mtk_star_hash_wait_ok(struct mtk_star_priv *priv)
> > +{
> > + unsigned int val;
> > + int ret;
> > +
> > + /* Wait for BIST_DONE bit. */
> > + ret = regmap_read_poll_timeout_atomic(priv->regs,
> > + MTK_STAR_REG_HASH_CTRL, val,
> > + val & MTK_STAR_BIT_HASH_CTRL_BIST_DONE,
> > + 10, MTK_STAR_WAIT_TIMEOUT);
> > + if (ret)
> > + return ret;
> > +
> > + /* Check the BIST_OK bit. */
> > + regmap_read(priv->regs, MTK_STAR_REG_HASH_CTRL, &val);
> > + if (!(val & MTK_STAR_BIT_HASH_CTRL_BIST_OK))
> > + return -EIO;
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_star_set_hashbit(struct mtk_star_priv *priv,
> > + unsigned int hash_addr)
> > +{
> > + unsigned int val;
> > + int ret;
> > +
> > + ret = mtk_star_hash_wait_cmd_start(priv);
> > + if (ret)
> > + return ret;
> > +
> > + val = hash_addr & MTK_STAR_MSK_HASH_CTRL_HASH_BIT_ADDR;
> > + val |= MTK_STAR_BIT_HASH_CTRL_ACC_CMD;
> > + val |= MTK_STAR_BIT_HASH_CTRL_CMD_START;
> > + val |= MTK_STAR_BIT_HASH_CTRL_BIST_EN;
> > + val |= MTK_STAR_BIT_HASH_CTRL_HASH_BIT_DATA;
> > + regmap_write(priv->regs, MTK_STAR_REG_HASH_CTRL, val);
> > +
> > + return mtk_star_hash_wait_ok(priv);
> > +}
> > +
> > +static int mtk_star_reset_hash_table(struct mtk_star_priv *priv)
> > +{
> > + int ret;
> > +
> > + ret = mtk_star_hash_wait_cmd_start(priv);
> > + if (ret)
> > + return ret;
> > +
> > + regmap_update_bits(priv->regs, MTK_STAR_REG_HASH_CTRL,
> > + MTK_STAR_BIT_HASH_CTRL_BIST_EN,
> > + MTK_STAR_BIT_HASH_CTRL_BIST_EN);
> > + regmap_update_bits(priv->regs, MTK_STAR_REG_TEST1,
> > + MTK_STAR_BIT_TEST1_RST_HASH_MBIST,
> > + MTK_STAR_BIT_TEST1_RST_HASH_MBIST);
> > +
> > + return mtk_star_hash_wait_ok(priv);
> > +}
> > +
> > +static void mtk_star_phy_config(struct mtk_star_priv *priv)
> > +{
> > + unsigned int val;
> > +
> > + if (priv->speed == SPEED_1000)
> > + val = MTK_STAR_VAL_PHY_CTRL1_FORCE_SPD_1000M;
> > + else if (priv->speed == SPEED_100)
> > + val = MTK_STAR_VAL_PHY_CTRL1_FORCE_SPD_100M;
> > + else
> > + val = MTK_STAR_VAL_PHY_CTRL1_FORCE_SPD_10M;
> > + val <<= MTK_STAR_OFF_PHY_CTRL1_FORCE_SPD;
> > +
> > + val |= MTK_STAR_BIT_PHY_CTRL1_AN_EN;
> > + val |= MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_RX;
> > + val |= MTK_STAR_BIT_PHY_CTRL1_FORCE_FC_TX;
> > + /* Only full-duplex supported for now. */
> > + val |= MTK_STAR_BIT_PHY_CTRL1_FORCE_DPX;
> > +
> > + regmap_write(priv->regs, MTK_STAR_REG_PHY_CTRL1, val);
> > +
> > + if (priv->pause) {
> > + val = MTK_STAR_VAL_FC_CFG_SEND_PAUSE_TH_2K;
> > + val <<= MTK_STAR_OFF_FC_CFG_SEND_PAUSE_TH;
> > + val |= MTK_STAR_BIT_FC_CFG_UC_PAUSE_DIR;
> > + } else {
> > + val = 0;
> > + }
> > +
> > + regmap_update_bits(priv->regs, MTK_STAR_REG_FC_CFG,
> > + MTK_STAR_MSK_FC_CFG_SEND_PAUSE_TH |
> > + MTK_STAR_BIT_FC_CFG_UC_PAUSE_DIR, val);
> > +
> > + if (priv->pause) {
> > + val = MTK_STAR_VAL_EXT_CFG_SND_PAUSE_RLS_1K;
> > + val <<= MTK_STAR_OFF_EXT_CFG_SND_PAUSE_RLS;
> > + } else {
> > + val = 0;
> > + }
> > +
> > + regmap_update_bits(priv->regs, MTK_STAR_REG_EXT_CFG,
> > + MTK_STAR_MSK_EXT_CFG_SND_PAUSE_RLS, val);
> > +}
> > +
> > +static void mtk_star_adjust_link(struct net_device *ndev)
> > +{
> > + struct mtk_star_priv *priv = netdev_priv(ndev);
> > + struct phy_device *phydev = priv->phydev;
> > + bool new_state = false;
> > +
> > + if (phydev->link) {
> > + if (!priv->link) {
> > + priv->link = phydev->link;
> > + new_state = true;
> > + }
> > +
> > + if (priv->speed != phydev->speed) {
> > + priv->speed = phydev->speed;
> > + new_state = true;
> > + }
> > +
> > + if (priv->pause != phydev->pause) {
> > + priv->pause = phydev->pause;
> > + new_state = true;
> > + }
> > + } else {
> > + if (priv->link) {
> > + priv->link = phydev->link;
> > + new_state = true;
> > + }
> > + }
> > +
> > + if (new_state) {
> > + if (phydev->link)
> > + mtk_star_phy_config(priv);
> > +
> > + phy_print_status(ndev->phydev);
> > + }
> > +}
> > +
> > +static void mtk_star_init_config(struct mtk_star_priv *priv)
> > +{
> > + unsigned int val;
> > +
> > + val = (MTK_STAR_BIT_MII_PAD_OUT_ENABLE |
> > + MTK_STAR_BIT_EXT_MDC_MODE |
> > + MTK_STAR_BIT_SWC_MII_MODE);
> > +
> > + regmap_write(priv->regs, MTK_STAR_REG_SYS_CONF, val);
> > + regmap_update_bits(priv->regs, MTK_STAR_REG_MAC_CLK_CONF,
> > + MTK_STAR_MSK_MAC_CLK_CONF,
> > + MTK_STAR_BIT_CLK_DIV_10);
> > +}
> > +
> > +static void mtk_star_set_mode_rmii(struct mtk_star_priv *priv)
> > +{
> > + regmap_update_bits(priv->pericfg, MTK_PERICFG_REG_NIC_CFG_CON,
> > + MTK_PERICFG_MSK_NIC_CFG_CON_CFG_MII,
> > + MTK_PERICFG_BIT_NIC_CFG_CON_RMII);
> > +}
> > +
> > +static int mtk_star_enable(struct net_device *ndev)
> > +{
> > + struct mtk_star_priv *priv = netdev_priv(ndev);
> > + unsigned int val;
> > + int ret;
> > +
> > + mtk_star_nic_disable_pd(priv);
> > + mtk_star_intr_disable(priv);
> > + mtk_star_dma_stop(priv);
> > +
> > + mtk_star_set_mac_addr(ndev);
> > +
> > + /* Configure the MAC */
> > + val = MTK_STAR_VAL_MAC_CFG_IPG_96BIT;
> > + val <<= MTK_STAR_OFF_MAC_CFG_IPG;
> > + val |= MTK_STAR_BIT_MAC_CFG_MAXLEN_1522;
> > + val |= MTK_STAR_BIT_MAC_CFG_AUTO_PAD;
> > + val |= MTK_STAR_BIT_MAC_CFG_CRC_STRIP;
> > + regmap_write(priv->regs, MTK_STAR_REG_MAC_CFG, val);
> > +
> > + /* Enable Hash Table BIST and reset it */
> > + ret = mtk_star_reset_hash_table(priv);
> > + if (ret)
> > + return ret;
> > +
> > + /* Setup the hashing algorithm */
> > + regmap_update_bits(priv->regs, MTK_STAR_REG_ARL_CFG,
> > + MTK_STAR_BIT_ARL_CFG_HASH_ALG |
> > + MTK_STAR_BIT_ARL_CFG_MISC_MODE, 0);
> > +
> > + /* Don't strip VLAN tags */
> > + regmap_update_bits(priv->regs, MTK_STAR_REG_MAC_CFG,
> > + MTK_STAR_BIT_MAC_CFG_VLAN_STRIP, 0);
> > +
> > + /* Setup DMA */
> > + mtk_star_dma_init(priv);
> > +
> > + ret = mtk_star_prepare_rx_skbs(ndev);
> > + if (ret)
> > + goto err_out;
> > +
> > + /* Request the interrupt */
> > + ret = request_irq(ndev->irq, mtk_star_handle_irq,
> > + IRQF_TRIGGER_FALLING, ndev->name, ndev);
> > + if (ret)
> > + goto err_free_skbs;
> > +
> > + napi_enable(&priv->napi);
> > +
> > + mtk_star_intr_ack_all(priv);
> > + mtk_star_intr_enable(priv);
> > +
> > + /* Connect to and start PHY */
> > + priv->phydev = of_phy_connect(ndev, priv->phy_node,
> > + mtk_star_adjust_link, 0, priv->phy_intf);
> > + if (!priv->phydev) {
> > + netdev_err(ndev, "failed to connect to PHY\n");
> > + goto err_free_irq;
> > + }
> > +
> > + mtk_star_dma_start(priv);
> > + phy_start(priv->phydev);
> > + netif_start_queue(ndev);
> > +
> > + return 0;
> > +
> > +err_free_irq:
> > + free_irq(ndev->irq, ndev);
> > +err_free_skbs:
> > + mtk_star_free_rx_skbs(priv);
> > +err_out:
> > + return ret;
> > +}
> > +
> > +static void mtk_star_disable(struct net_device *ndev)
> > +{
> > + struct mtk_star_priv *priv = netdev_priv(ndev);
> > +
> > + netif_stop_queue(ndev);
> > + napi_disable(&priv->napi);
> > + mtk_star_intr_disable(priv);
> > + mtk_star_dma_disable(priv);
> > + mtk_star_intr_ack_all(priv);
> > + phy_stop(priv->phydev);
> > + phy_disconnect(priv->phydev);
> > + free_irq(ndev->irq, ndev);
> > + mtk_star_free_rx_skbs(priv);
> > + mtk_star_free_tx_skbs(priv);
> > +}
> > +
> > +static int mtk_star_netdev_open(struct net_device *ndev)
> > +{
> > + return mtk_star_enable(ndev);
> > +}
> > +
> > +static int mtk_star_netdev_stop(struct net_device *ndev)
> > +{
> > + mtk_star_disable(ndev);
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_star_netdev_ioctl(struct net_device *ndev,
> > + struct ifreq *req, int cmd)
> > +{
> > + if (!netif_running(ndev))
> > + return -EINVAL;
> > +
> > + return phy_mii_ioctl(ndev->phydev, req, cmd);
> > +}
> > +
> > +static int mtk_star_netdev_start_xmit(struct sk_buff *skb,
> > + struct net_device *ndev)
> > +{
> > + struct mtk_star_priv *priv = netdev_priv(ndev);
> > + struct mtk_star_ring *ring = &priv->tx_ring;
> > + struct device *dev = mtk_star_get_dev(priv);
> > + struct mtk_star_ring_desc_data desc_data;
> > +
> > + desc_data.dma_addr = mtk_star_dma_map_tx(priv, skb);
> > + if (dma_mapping_error(dev, desc_data.dma_addr))
> > + goto err_drop_packet;
> > +
> > + desc_data.skb = skb;
> > + desc_data.len = skb->len;
> > +
> > + spin_lock_bh(&priv->lock);
> > +
> > + mtk_star_ring_push_head_tx(ring, &desc_data);
> > +
> > + netdev_sent_queue(ndev, skb->len);
> > +
> > + if (mtk_star_ring_full(ring))
> > + netif_stop_queue(ndev);
> > +
> > + spin_unlock_bh(&priv->lock);
> > +
> > + mtk_star_dma_resume_tx(priv);
> > +
> > + return NETDEV_TX_OK;
> > +
> > +err_drop_packet:
> > + dev_kfree_skb(skb);
> > + ndev->stats.tx_dropped++;
> > + return NETDEV_TX_BUSY;
> > +}
> > +
> > +/* Returns the number of bytes sent or a negative number on the first
> > + * descriptor owned by DMA.
> > + */
> > +static int mtk_star_tx_complete_one(struct mtk_star_priv *priv)
> > +{
> > + struct mtk_star_ring *ring = &priv->tx_ring;
> > + struct mtk_star_ring_desc_data desc_data;
> > + int ret;
> > +
> > + ret = mtk_star_ring_pop_tail(ring, &desc_data);
> > + if (ret)
> > + return ret;
> > +
> > + mtk_star_dma_unmap_tx(priv, &desc_data);
> > + ret = desc_data.skb->len;
> > + dev_kfree_skb_irq(desc_data.skb);
> > +
> > + return ret;
> > +}
> > +
> > +static void mtk_star_tx_complete_all(struct mtk_star_priv *priv)
> > +{
> > + struct mtk_star_ring *ring = &priv->tx_ring;
> > + struct net_device *ndev = priv->ndev;
> > + int ret, pkts_compl, bytes_compl;
> > + bool wake = false;
> > +
> > + spin_lock(&priv->lock);
> > +
> > + for (pkts_compl = 0, bytes_compl = 0;;
> > + pkts_compl++, bytes_compl += ret, wake = true) {
> > + if (!mtk_star_ring_descs_available(ring))
> > + break;
> > +
> > + ret = mtk_star_tx_complete_one(priv);
> > + if (ret < 0)
> > + break;
> > + }
> > +
> > + netdev_completed_queue(ndev, pkts_compl, bytes_compl);
> > +
> > + if (wake && netif_queue_stopped(ndev))
> > + netif_wake_queue(ndev);
> > +
> > + mtk_star_intr_enable_tx(priv);
> > +
> > + spin_unlock(&priv->lock);
> > +}
> > +
> > +static void mtk_star_netdev_get_stats64(struct net_device *ndev,
> > + struct rtnl_link_stats64 *stats)
> > +{
> > + struct mtk_star_priv *priv = netdev_priv(ndev);
> > +
> > + mtk_star_update_stats(priv);
> > +
> > + memcpy(stats, &priv->stats, sizeof(*stats));
> > +}
> > +
> > +static void mtk_star_set_rx_mode(struct net_device *ndev)
> > +{
> > + struct mtk_star_priv *priv = netdev_priv(ndev);
> > + struct netdev_hw_addr *hw_addr;
> > + unsigned int hash_addr, i;
> > + int ret;
> > +
> > + if (ndev->flags & IFF_PROMISC) {
> > + regmap_update_bits(priv->regs, MTK_STAR_REG_ARL_CFG,
> > + MTK_STAR_BIT_ARL_CFG_MISC_MODE,
> > + MTK_STAR_BIT_ARL_CFG_MISC_MODE);
> > + } else if (netdev_mc_count(ndev) > MTK_STAR_HASHTABLE_MC_LIMIT ||
> > + ndev->flags & IFF_ALLMULTI) {
> > + for (i = 0; i < MTK_STAR_HASHTABLE_SIZE_MAX; i++) {
> > + ret = mtk_star_set_hashbit(priv, i);
> > + if (ret)
> > + goto hash_fail;
> > + }
> > + } else {
> > + /* Clear previous settings. */
> > + ret = mtk_star_reset_hash_table(priv);
> > + if (ret)
> > + goto hash_fail;
> > +
> > + netdev_for_each_mc_addr(hw_addr, ndev) {
> > + hash_addr = (hw_addr->addr[0] & 0x01) << 8;
> > + hash_addr += hw_addr->addr[5];
> > + ret = mtk_star_set_hashbit(priv, hash_addr);
> > + if (ret)
> > + goto hash_fail;
> > + }
> > + }
> > +
> > + return;
> > +
> > +hash_fail:
> > + if (ret == -ETIMEDOUT)
> > + netdev_err(ndev, "setting hash bit timed out\n");
> > + else
> > + /* Should be -EIO */
> > + netdev_err(ndev, "unable to set hash bit");
> > +}
> > +
> > +static const struct net_device_ops mtk_star_netdev_ops = {
> > + .ndo_open = mtk_star_netdev_open,
> > + .ndo_stop = mtk_star_netdev_stop,
> > + .ndo_start_xmit = mtk_star_netdev_start_xmit,
> > + .ndo_get_stats64 = mtk_star_netdev_get_stats64,
> > + .ndo_set_rx_mode = mtk_star_set_rx_mode,
> > + .ndo_do_ioctl = mtk_star_netdev_ioctl,
> > + .ndo_set_mac_address = eth_mac_addr,
> > + .ndo_validate_addr = eth_validate_addr,
> > +};
> > +
> > +static void mtk_star_get_drvinfo(struct net_device *dev,
> > + struct ethtool_drvinfo *info)
> > +{
> > + strlcpy(info->driver, MTK_STAR_DRVNAME, sizeof(info->driver));
> > +}
> > +
> > +/* TODO Add ethtool stats. */
> > +static const struct ethtool_ops mtk_star_ethtool_ops = {
> > + .get_drvinfo = mtk_star_get_drvinfo,
> > + .get_link = ethtool_op_get_link,
> > + .get_link_ksettings = phy_ethtool_get_link_ksettings,
> > + .set_link_ksettings = phy_ethtool_set_link_ksettings,
> > +};
> > +
> > +static int mtk_star_receive_packet(struct mtk_star_priv *priv)
> > +{
> > + struct mtk_star_ring *ring = &priv->rx_ring;
> > + struct device *dev = mtk_star_get_dev(priv);
> > + struct mtk_star_ring_desc_data desc_data;
> > + struct net_device *ndev = priv->ndev;
> > + struct sk_buff *curr_skb, *new_skb;
> > + dma_addr_t new_dma_addr;
> > + int ret;
> > +
> > + spin_lock(&priv->lock);
> > + ret = mtk_star_ring_pop_tail(ring, &desc_data);
> > + spin_unlock(&priv->lock);
> > + if (ret)
> > + return -1;
> > +
> > + curr_skb = desc_data.skb;
> > +
> > + if ((desc_data.flags & MTK_STAR_DESC_BIT_RX_CRCE) ||
> > + (desc_data.flags & MTK_STAR_DESC_BIT_RX_OSIZE)) {
> > + /* Error packet -> drop and reuse skb. */
> > + new_skb = curr_skb;
> > + goto push_new_skb;
> > + }
> > +
> > + /* Prepare new skb before receiving the current one. Reuse the current
> > + * skb if we fail at any point.
> > + */
> > + new_skb = mtk_star_alloc_skb(ndev);
> > + if (!new_skb) {
> > + ndev->stats.rx_dropped++;
> > + new_skb = curr_skb;
> > + goto push_new_skb;
> > + }
> > +
> > + new_dma_addr = mtk_star_dma_map_rx(priv, new_skb);
> > + if (dma_mapping_error(dev, new_dma_addr)) {
> > + ndev->stats.rx_dropped++;
> > + dev_kfree_skb(new_skb);
> > + new_skb = curr_skb;
> > + netdev_err(ndev, "DMA mapping error of RX descriptor\n");
> > + goto push_new_skb;
> > + }
> > +
> > + /* We can't fail anymore at this point: it's safe to unmap the skb. */
> > + mtk_star_dma_unmap_rx(priv, &desc_data);
> > +
> > + skb_put(desc_data.skb, desc_data.len);
> > + desc_data.skb->ip_summed = CHECKSUM_NONE;
> > + desc_data.skb->protocol = eth_type_trans(desc_data.skb, ndev);
> > + desc_data.skb->dev = ndev;
> > + netif_receive_skb(desc_data.skb);
> > +
> > +push_new_skb:
> > + desc_data.dma_addr = new_dma_addr;
> > + desc_data.len = skb_tailroom(new_skb);
> > + desc_data.skb = new_skb;
> > +
> > + spin_lock(&priv->lock);
> > + mtk_star_ring_push_head_rx(ring, &desc_data);
> > + spin_unlock(&priv->lock);
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_star_process_rx(struct mtk_star_priv *priv, int budget)
> > +{
> > + int received, ret;
> > +
> > + for (received = 0, ret = 0; received < budget && ret == 0; received++)
> > + ret = mtk_star_receive_packet(priv);
> > +
> > + mtk_star_dma_resume_rx(priv);
> > +
> > + return received;
> > +}
> > +
> > +static int mtk_star_poll(struct napi_struct *napi, int budget)
> > +{
> > + struct mtk_star_priv *priv;
> > + int received = 0;
> > +
> > + priv = container_of(napi, struct mtk_star_priv, napi);
> > +
> > + /* Clean-up all TX descriptors. */
> > + mtk_star_tx_complete_all(priv);
> > + /* Receive up to $budget packets. */
> > + received = mtk_star_process_rx(priv, budget);
> > +
> > + if (received < budget) {
> > + napi_complete_done(napi, received);
> > + mtk_star_intr_enable_rx(priv);
> > + }
> > +
> > + return received;
> > +}
> > +
> > +static void mtk_star_mdio_rwok_clear(struct mtk_star_priv *priv)
> > +{
> > + regmap_write(priv->regs, MTK_STAR_REG_PHY_CTRL0,
> > + MTK_STAR_BIT_PHY_CTRL0_RWOK);
> > +}
> > +
> > +static int mtk_star_mdio_rwok_wait(struct mtk_star_priv *priv)
> > +{
> > + unsigned int val;
> > +
> > + return regmap_read_poll_timeout(priv->regs, MTK_STAR_REG_PHY_CTRL0,
> > + val, val & MTK_STAR_BIT_PHY_CTRL0_RWOK,
> > + 10, MTK_STAR_WAIT_TIMEOUT);
> > +}
> > +
> > +static int mtk_star_mdio_read(struct mii_bus *mii, int phy_id, int regnum)
> > +{
> > + struct mtk_star_priv *priv = mii->priv;
> > + unsigned int val, data;
> > + int ret;
> > +
> > + if (regnum & MII_ADDR_C45)
> > + return -EOPNOTSUPP;
> > +
> > + mtk_star_mdio_rwok_clear(priv);
> > +
> > + val = (regnum << MTK_STAR_OFF_PHY_CTRL0_PREG);
> > + val &= MTK_STAR_MSK_PHY_CTRL0_PREG;
> > + val |= MTK_STAR_BIT_PHY_CTRL0_RDCMD;
> > +
> > + regmap_write(priv->regs, MTK_STAR_REG_PHY_CTRL0, val);
> > +
> > + ret = mtk_star_mdio_rwok_wait(priv);
> > + if (ret)
> > + return ret;
> > +
> > + regmap_read(priv->regs, MTK_STAR_REG_PHY_CTRL0, &data);
> > +
> > + data &= MTK_STAR_MSK_PHY_CTRL0_RWDATA;
> > + data >>= MTK_STAR_OFF_PHY_CTRL0_RWDATA;
> > +
> > + return data;
> > +}
> > +
> > +static int mtk_star_mdio_write(struct mii_bus *mii, int phy_id,
> > + int regnum, u16 data)
> > +{
> > + struct mtk_star_priv *priv = mii->priv;
> > + unsigned int val;
> > +
> > + if (regnum & MII_ADDR_C45)
> > + return -EOPNOTSUPP;
> > +
> > + mtk_star_mdio_rwok_clear(priv);
> > +
> > + val = data;
> > + val <<= MTK_STAR_OFF_PHY_CTRL0_RWDATA;
> > + val &= MTK_STAR_MSK_PHY_CTRL0_RWDATA;
> > + regnum <<= MTK_STAR_OFF_PHY_CTRL0_PREG;
> > + regnum &= MTK_STAR_MSK_PHY_CTRL0_PREG;
> > + val |= regnum;
> > + val |= MTK_STAR_BIT_PHY_CTRL0_WTCMD;
> > +
> > + regmap_write(priv->regs, MTK_STAR_REG_PHY_CTRL0, val);
> > +
> > + return mtk_star_mdio_rwok_wait(priv);
> > +}
> > +
> > +static int mtk_star_mdio_init(struct net_device *ndev)
> > +{
> > + struct mtk_star_priv *priv = netdev_priv(ndev);
> > + struct device *dev = mtk_star_get_dev(priv);
> > + struct device_node *of_node, *mdio_node;
> > + int ret;
> > +
> > + of_node = dev->of_node;
> > +
> > + mdio_node = of_get_child_by_name(of_node, "mdio");
> > + if (!mdio_node)
> > + return -ENODEV;
> > +
> > + if (!of_device_is_available(mdio_node)) {
> > + ret = -ENODEV;
> > + goto out_put_node;
> > + }
> > +
> > + priv->mii = devm_mdiobus_alloc(dev);
> > + if (!priv->mii) {
> > + ret = -ENOMEM;
> > + goto out_put_node;
> > + }
> > +
> > + snprintf(priv->mii->id, MII_BUS_ID_SIZE, "%s", dev_name(dev));
> > + priv->mii->name = "mtk-mac-mdio";
> > + priv->mii->parent = dev;
> > + priv->mii->read = mtk_star_mdio_read;
> > + priv->mii->write = mtk_star_mdio_write;
> > + priv->mii->priv = priv;
> > +
> > + ret = of_mdiobus_register(priv->mii, mdio_node);
> > +
> > +out_put_node:
> > + of_node_put(mdio_node);
> > + return ret;
> > +}
> > +
> > +static int mtk_star_suspend(struct device *dev)
> > +{
> > + struct mtk_star_priv *priv;
> > + struct net_device *ndev;
> > +
> > + ndev = dev_get_drvdata(dev);
> > + priv = netdev_priv(ndev);
> > +
> > + if (netif_running(ndev))
> > + mtk_star_disable(ndev);
> > +
> > + clk_bulk_disable_unprepare(MTK_STAR_NCLKS, priv->clks);
> > +
> > + return 0;
> > +}
> > +
> > +static int mtk_star_resume(struct device *dev)
> > +{
> > + struct mtk_star_priv *priv;
> > + struct net_device *ndev;
> > + int ret;
> > +
> > + ndev = dev_get_drvdata(dev);
> > + priv = netdev_priv(ndev);
> > +
> > + ret = clk_bulk_prepare_enable(MTK_STAR_NCLKS, priv->clks);
> > + if (ret)
> > + return ret;
> > +
> > + if (netif_running(ndev)) {
> > + ret = mtk_star_enable(ndev);
> > + if (ret)
> > + clk_bulk_disable_unprepare(MTK_STAR_NCLKS, priv->clks);
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static void mtk_star_clk_disable_unprepare(void *data)
> > +{
> > + struct mtk_star_priv *priv = data;
> > +
> > + clk_bulk_disable_unprepare(MTK_STAR_NCLKS, priv->clks);
> > +}
> > +
> > +static void mtk_star_mdiobus_unregister(void *data)
> > +{
> > + struct mtk_star_priv *priv = data;
> > +
> > + mdiobus_unregister(priv->mii);
> > +}
> > +
> > +static void mtk_star_unregister_netdev(void *data)
> > +{
> > + struct net_device *ndev = data;
> > +
> > + unregister_netdev(ndev);
> > +}
> > +
> > +static int mtk_star_probe(struct platform_device *pdev)
> > +{
> > + struct device_node *of_node;
> > + struct mtk_star_priv *priv;
> > + struct net_device *ndev;
> > + struct device *dev;
> > + void __iomem *base;
> > + int ret, i;
> > +
> > + dev = &pdev->dev;
> > + of_node = dev->of_node;
> > +
> > + ndev = devm_alloc_etherdev(dev, sizeof(*priv));
> > + if (!ndev)
> > + return -ENOMEM;
> > +
> > + priv = netdev_priv(ndev);
> > + priv->ndev = ndev;
> > + SET_NETDEV_DEV(ndev, dev);
> > + platform_set_drvdata(pdev, ndev);
> > +
> > + ndev->min_mtu = ETH_ZLEN;
> > + ndev->max_mtu = MTK_STAR_MAX_FRAME_SIZE;
> > +
> > + spin_lock_init(&priv->lock);
> > + INIT_WORK(&priv->stats_work, mtk_star_update_stats_work);
> > +
> > + base = devm_platform_ioremap_resource(pdev, 0);
> > + if (IS_ERR(base))
> > + return PTR_ERR(base);
> > +
> > + /* We won't be checking the return values of regmap read & write
> > + * functions. They can only fail for mmio if there's a clock attached
> > + * to regmap which is not the case here.
> > + */
> > + priv->regs = devm_regmap_init_mmio(dev, base,
> > + &mtk_star_regmap_config);
> > + if (IS_ERR(priv->regs))
> > + return PTR_ERR(priv->regs);
> > +
> > + priv->pericfg = syscon_regmap_lookup_by_phandle(of_node,
> > + "mediatek,pericfg");
> > + if (IS_ERR(priv->pericfg)) {
> > + dev_err(dev, "Failed to lookup the PERICFG syscon\n");
> > + return PTR_ERR(priv->pericfg);
> > + }
> > +
> > + ndev->irq = platform_get_irq(pdev, 0);
> > + if (ndev->irq < 0)
> > + return ndev->irq;
> > +
> > + for (i = 0; i < MTK_STAR_NCLKS; i++)
> > + priv->clks[i].id = mtk_star_clk_names[i];
> > + ret = devm_clk_bulk_get(dev, MTK_STAR_NCLKS, priv->clks);
> > + if (ret)
> > + return ret;
> > +
> > + ret = clk_bulk_prepare_enable(MTK_STAR_NCLKS, priv->clks);
> > + if (ret)
> > + return ret;
> > +
> > + ret = devm_add_action_or_reset(dev,
> > + mtk_star_clk_disable_unprepare, priv);
> > + if (ret)
> > + return ret;
> > +
> > + ret = of_get_phy_mode(of_node, &priv->phy_intf);
> > + if (ret) {
> > + return ret;
> > + } else if (priv->phy_intf != PHY_INTERFACE_MODE_RMII) {
> > + dev_err(dev, "unsupported phy mode: %s\n",
> > + phy_modes(priv->phy_intf));
> > + return -EINVAL;
> > + }
> > +
> > + priv->phy_node = of_parse_phandle(of_node, "phy-handle", 0);
> > + if (!priv->phy_node) {
> > + dev_err(dev, "failed to retrieve the phy handle from device tree\n");
> > + return -ENODEV;
> > + }
> > +
> > + mtk_star_set_mode_rmii(priv);
> > +
> > + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
> > + if (ret) {
> > + dev_err(dev, "unsupported DMA mask\n");
> > + return ret;
> > + }
> > +
> > + priv->ring_base = dmam_alloc_coherent(dev, MTK_STAR_DMA_SIZE,
> > + &priv->dma_addr,
> > + GFP_KERNEL | GFP_DMA);
> > + if (!priv->ring_base)
> > + return -ENOMEM;
> > +
> > + mtk_star_nic_disable_pd(priv);
> > + mtk_star_init_config(priv);
> > +
> > + ret = mtk_star_mdio_init(ndev);
> > + if (ret)
> > + return ret;
> > +
> > + ret = devm_add_action_or_reset(dev, mtk_star_mdiobus_unregister, priv);
> > + if (ret)
> > + return ret;
> > +
> > + ret = eth_platform_get_mac_address(dev, ndev->dev_addr);
> > + if (ret || !is_valid_ether_addr(ndev->dev_addr))
> > + eth_hw_addr_random(ndev);
> > +
> > + ndev->netdev_ops = &mtk_star_netdev_ops;
> > + ndev->ethtool_ops = &mtk_star_ethtool_ops;
> > +
> > + netif_napi_add(ndev, &priv->napi, mtk_star_poll, MTK_STAR_NAPI_WEIGHT);
> > +
> > + ret = register_netdev(ndev);
> > + if (ret)
> > + return ret;
> > +
> > + ret = devm_add_action_or_reset(dev, mtk_star_unregister_netdev, ndev);
> > + if (ret)
> > + return ret;
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_star_of_match[] = {
> > + { .compatible = "mediatek,mt8516-eth", },
> > + { .compatible = "mediatek,mt8518-eth", },
> > + { .compatible = "mediatek,mt8175-eth", },
> > + { }
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_star_of_match);
> > +
> > +static SIMPLE_DEV_PM_OPS(mtk_star_pm_ops,
> > + mtk_star_suspend, mtk_star_resume);
> > +
> > +static struct platform_driver mtk_star_driver = {
> > + .driver = {
> > + .name = MTK_STAR_DRVNAME,
> > + .pm = &mtk_star_pm_ops,
> > + .of_match_table = of_match_ptr(mtk_star_of_match),
> > + },
> > + .probe = mtk_star_probe,
> > +};
> > +module_platform_driver(mtk_star_driver);
> > +
> > +MODULE_AUTHOR("Bartosz Golaszewski <bgolaszewski@baylibre.com>");
> > +MODULE_DESCRIPTION("Mediatek STAR Ethernet MAC Driver");
> > +MODULE_LICENSE("GPL");
> >
Hi Matthias
Please trim your emails when replying. It is really annoying to page
down, down and down looking for comments, and find there are none.
Andrew
^ permalink raw reply
* Re: [EXT] Re: [PATCH net 3/4] ARM: dts: imx6: update fec gpr property to match new format
From: Andrew Lunn @ 2020-05-22 23:50 UTC (permalink / raw)
To: Fuzzey, Martin
Cc: Andy Duan, David S. Miller, netdev@vger.kernel.org,
robh+dt@kernel.org, shawnguo@kernel.org,
devicetree@vger.kernel.org
In-Reply-To: <CANh8QzwxfnQ1cACz=6dhYujEVtQoTCw8kTgkHi9BnxESptL=xQ@mail.gmail.com>
> Yes, I don't think anyone is saying otherwise.
Correct.
>
> The problem is just that there are already .dtsi files for i.MX chips
> having multiple ethernet interfaces
> in the mainline kernel (at least imx6ui.dtsi, imx6sx.dts, imx7d.dtsi)
Vybrid is one i use a lot with two FECs.
> but that this patch series does not
> modify those files to use the new DT format.
>
> It currently only modifies the dts files that are already supported by
> hardcoded values in the driver.
Exactly. This patch set itself adds nothing we don't already support.
So the patch set as is, is pointless.
> As to not knowing which instance it shouldn't matter.
> The base dtsi can declare both/all ethernet interfaces with the
> appropriate GPR bits.
I fully agree. All it needs for this patchset to be merged is another
patch which adds GPR properties to all SoC .dtsi files where
appropriate, and optionally to a couple of reference designs which
support WoL on their ports.
Andrew
^ permalink raw reply
* Re: [PATCH V6 6/7] spi: spi-qcom-qspi: Add interconnect support
From: kbuild test robot @ 2020-05-23 1:11 UTC (permalink / raw)
To: Akash Asthana, gregkh, agross, bjorn.andersson, wsa, broonie,
mark.rutland, robh+dt
Cc: kbuild-all, clang-built-linux, linux-i2c, linux-spi, devicetree,
swboyd, mgautam, linux-arm-msm, linux-serial, mka, dianders
In-Reply-To: <1590049764-20912-7-git-send-email-akashast@codeaurora.org>
[-- Attachment #1: Type: text/plain, Size: 7646 bytes --]
Hi Akash,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on tty/tty-testing]
[also build test ERROR on spi/for-next wsa/i2c/for-next usb/usb-testing driver-core/driver-core-testing linus/master v5.7-rc6]
[cannot apply to next-20200522]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Akash-Asthana/Add-interconnect-support-to-QSPI-and-QUP-drivers/20200521-163523
base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git tty-testing
config: arm64-randconfig-r026-20200521 (attached as .config)
compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project 3393cc4cebf9969db94dc424b7a2b6195589c33b)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp@intel.com>
All error/warnings (new ones prefixed by >>, old ones prefixed by <<):
>> drivers/spi/spi-qcom-qspi.c:479:31: error: implicit declaration of function 'devm_of_icc_get' [-Werror,-Wimplicit-function-declaration]
ctrl->icc_path_cpu_to_qspi = devm_of_icc_get(dev, "qspi-config");
^
>> drivers/spi/spi-qcom-qspi.c:479:29: warning: incompatible integer to pointer conversion assigning to 'struct icc_path *' from 'int' [-Wint-conversion]
ctrl->icc_path_cpu_to_qspi = devm_of_icc_get(dev, "qspi-config");
^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/spi/spi-qcom-qspi.c:495:8: error: implicit declaration of function 'icc_disable' [-Werror,-Wimplicit-function-declaration]
ret = icc_disable(ctrl->icc_path_cpu_to_qspi);
^
drivers/spi/spi-qcom-qspi.c:495:8: note: did you mean 'clk_disable'?
include/linux/clk.h:519:6: note: 'clk_disable' declared here
void clk_disable(struct clk *clk);
^
drivers/spi/spi-qcom-qspi.c:559:8: error: implicit declaration of function 'icc_disable' [-Werror,-Wimplicit-function-declaration]
ret = icc_disable(ctrl->icc_path_cpu_to_qspi);
^
>> drivers/spi/spi-qcom-qspi.c:575:8: error: implicit declaration of function 'icc_enable' [-Werror,-Wimplicit-function-declaration]
ret = icc_enable(ctrl->icc_path_cpu_to_qspi);
^
drivers/spi/spi-qcom-qspi.c:575:8: note: did you mean 'clk_enable'?
include/linux/clk.h:491:5: note: 'clk_enable' declared here
int clk_enable(struct clk *clk);
^
1 warning and 4 errors generated.
vim +/devm_of_icc_get +479 drivers/spi/spi-qcom-qspi.c
440
441 static int qcom_qspi_probe(struct platform_device *pdev)
442 {
443 int ret;
444 struct device *dev;
445 struct spi_master *master;
446 struct qcom_qspi *ctrl;
447
448 dev = &pdev->dev;
449
450 master = spi_alloc_master(dev, sizeof(*ctrl));
451 if (!master)
452 return -ENOMEM;
453
454 platform_set_drvdata(pdev, master);
455
456 ctrl = spi_master_get_devdata(master);
457
458 spin_lock_init(&ctrl->lock);
459 ctrl->dev = dev;
460 ctrl->base = devm_platform_ioremap_resource(pdev, 0);
461 if (IS_ERR(ctrl->base)) {
462 ret = PTR_ERR(ctrl->base);
463 goto exit_probe_master_put;
464 }
465
466 ctrl->clks = devm_kcalloc(dev, QSPI_NUM_CLKS,
467 sizeof(*ctrl->clks), GFP_KERNEL);
468 if (!ctrl->clks) {
469 ret = -ENOMEM;
470 goto exit_probe_master_put;
471 }
472
473 ctrl->clks[QSPI_CLK_CORE].id = "core";
474 ctrl->clks[QSPI_CLK_IFACE].id = "iface";
475 ret = devm_clk_bulk_get(dev, QSPI_NUM_CLKS, ctrl->clks);
476 if (ret)
477 goto exit_probe_master_put;
478
> 479 ctrl->icc_path_cpu_to_qspi = devm_of_icc_get(dev, "qspi-config");
480 if (IS_ERR(ctrl->icc_path_cpu_to_qspi)) {
481 ret = PTR_ERR(ctrl->icc_path_cpu_to_qspi);
482 if (ret != -EPROBE_DEFER)
483 dev_err(dev, "Failed to get cpu path :%d\n", ret);
484 goto exit_probe_master_put;
485 }
486 /* Set BW vote for register access */
487 ret = icc_set_bw(ctrl->icc_path_cpu_to_qspi, Bps_to_icc(1000),
488 Bps_to_icc(1000));
489 if (ret) {
490 dev_err(ctrl->dev, "%s: ICC BW voting failed for cpu :%d\n",
491 __func__, ret);
492 goto exit_probe_master_put;
493 }
494
> 495 ret = icc_disable(ctrl->icc_path_cpu_to_qspi);
496 if (ret) {
497 dev_err(ctrl->dev, "%s: ICC disable failed for cpu :%d\n",
498 __func__, ret);
499 goto exit_probe_master_put;
500 }
501
502 ret = platform_get_irq(pdev, 0);
503 if (ret < 0)
504 goto exit_probe_master_put;
505 ret = devm_request_irq(dev, ret, qcom_qspi_irq,
506 IRQF_TRIGGER_HIGH, dev_name(dev), ctrl);
507 if (ret) {
508 dev_err(dev, "Failed to request irq %d\n", ret);
509 goto exit_probe_master_put;
510 }
511
512 master->max_speed_hz = 300000000;
513 master->num_chipselect = QSPI_NUM_CS;
514 master->bus_num = -1;
515 master->dev.of_node = pdev->dev.of_node;
516 master->mode_bits = SPI_MODE_0 |
517 SPI_TX_DUAL | SPI_RX_DUAL |
518 SPI_TX_QUAD | SPI_RX_QUAD;
519 master->flags = SPI_MASTER_HALF_DUPLEX;
520 master->prepare_message = qcom_qspi_prepare_message;
521 master->transfer_one = qcom_qspi_transfer_one;
522 master->handle_err = qcom_qspi_handle_err;
523 master->auto_runtime_pm = true;
524
525 pm_runtime_enable(dev);
526
527 ret = spi_register_master(master);
528 if (!ret)
529 return 0;
530
531 pm_runtime_disable(dev);
532
533 exit_probe_master_put:
534 spi_master_put(master);
535
536 return ret;
537 }
538
539 static int qcom_qspi_remove(struct platform_device *pdev)
540 {
541 struct spi_master *master = platform_get_drvdata(pdev);
542
543 /* Unregister _before_ disabling pm_runtime() so we stop transfers */
544 spi_unregister_master(master);
545
546 pm_runtime_disable(&pdev->dev);
547
548 return 0;
549 }
550
551 static int __maybe_unused qcom_qspi_runtime_suspend(struct device *dev)
552 {
553 struct spi_master *master = dev_get_drvdata(dev);
554 struct qcom_qspi *ctrl = spi_master_get_devdata(master);
555 int ret;
556
557 clk_bulk_disable_unprepare(QSPI_NUM_CLKS, ctrl->clks);
558
559 ret = icc_disable(ctrl->icc_path_cpu_to_qspi);
560 if (ret) {
561 dev_err_ratelimited(ctrl->dev, "%s: ICC disable failed for cpu :%d\n",
562 __func__, ret);
563 return ret;
564 }
565
566 return 0;
567 }
568
569 static int __maybe_unused qcom_qspi_runtime_resume(struct device *dev)
570 {
571 struct spi_master *master = dev_get_drvdata(dev);
572 struct qcom_qspi *ctrl = spi_master_get_devdata(master);
573 int ret;
574
> 575 ret = icc_enable(ctrl->icc_path_cpu_to_qspi);
576 if (ret) {
577 dev_err_ratelimited(ctrl->dev, "%s: ICC enable failed for cpu :%d\n",
578 __func__, ret);
579 return ret;
580 }
581
582 return clk_bulk_prepare_enable(QSPI_NUM_CLKS, ctrl->clks);
583 }
584
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 42362 bytes --]
^ permalink raw reply
* Re: [PATCH v4 07/14] PCI: cadence: Add new *ops* for CPU addr fixup
From: Kishon Vijay Abraham I @ 2020-05-23 1:24 UTC (permalink / raw)
To: Rob Herring
Cc: Bjorn Helgaas, Lorenzo Pieralisi, Arnd Bergmann, Tom Joseph,
Greg Kroah-Hartman, PCI, devicetree, linux-kernel@vger.kernel.org,
linux-omap,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <CAL_Jsq+qcgKvauJ-GjsnmmpmRusyEJ6pRDpBOQKOadig4XfsxQ@mail.gmail.com>
Hi Rob,
On 5/22/2020 10:15 PM, Rob Herring wrote:
> On Thu, May 21, 2020 at 5:35 AM Kishon Vijay Abraham I <kishon@ti.com> wrote:
>>
>> Hi Rob,
>>
>> On 5/21/2020 3:04 AM, Rob Herring wrote:
>>> On Wed, May 06, 2020 at 08:44:22PM +0530, Kishon Vijay Abraham I wrote:
>>>> Cadence driver uses "mem" memory resource to obtain the offset of
>>>> configuration space address region, memory space address region and
>>>> message space address region. The obtained offset is used to program
>>>> the Address Translation Unit (ATU). However certain platforms like TI's
>>>> J721E SoC require the absolute address to be programmed in the ATU and not
>>>> just the offset.
>>>
>>> Once again, Cadence host binding is broken (or at least the example is).
>>> The 'mem' region shouldn't even exist. It is overlapping the config
>>> space and 'ranges':
>>>
>>> reg = <0x0 0xfb000000 0x0 0x01000000>,
>>> <0x0 0x41000000 0x0 0x00001000>,
>>> <0x0 0x40000000 0x0 0x04000000>;
>>> reg-names = "reg", "cfg", "mem";
>>>
>>> ranges = <0x02000000 0x0 0x42000000 0x0 0x42000000 0x0 0x1000000>,
>>> <0x01000000 0x0 0x43000000 0x0 0x43000000 0x0 0x0010000>;
>>>
>>>
>>> 16M of registers looks a bit odd. I guess it doesn't matter
>>> unless you have a 32-bit platform and care about your virtual
>>> space. Probably should have been 3 regions for LM, RP, and AT looking
>>> at the driver.
>>
>> The "mem" region in never ioremapped. However $patch removes requiring to add
>> "mem" memory resource.
>
> I was referring to ioremapping 'reg' region.
>
>>>
>>> Whatever outbound address translation you need should be based on
>>> 'ranges'.
>>
>> You mean we don't need to add "new *ops* for CPU addr fixup"?. The issue is
>> ranges provides CPU address and PCI address. The CPU will access whatever is
>> populated in ranges to access the PCI bus. However while programming the ATU,
>> we cannot use the CPU address provided in ranges directly (in some platforms)
>> because the controller does not see the full address and only the lower 28bits.
>
> Okay, that is clearer as to what the difference is. I think this
> should be 2 patches. One dropping 'mem' usage and using a mask and the
> 2nd making the mask per platform.
hmm okay.
>
> Really, the parent node of the PCI controller should probably have
> 'ranges' and you could extract a mask from that. Looks like that is
> what you had for DRA7... I'm not sure if ABI stability is important
> for the Cadence platform. I'd assume that's just some IP eval system
> and probably not?
Right TI's J721E should be the first HW platform to use Cadence in mainline.
>
> Why do you need an ops here? All you need is a mask value.
So how do we get platform specific mask? Use a different binding to specify the
mask value?
>
>> This similar restriction was there with Designware (mostly an integration
>> issue) and we used *ops* to fixup the address that has to be programmed in ATU.
>> The Designware initially used a wrapper so that ranges property can be directly
>> used [1]. However this approach was later removed in [2]
>>
>> [1] -> https://lore.kernel.org/patchwork/patch/468523/
>> [2] -> https://lkml.org/lkml/2015/10/16/232
>
> So while you had the data for a mask in DT, the driver now hardcodes it?
Yes, that's correct. Which approach should we use for Cadence?
Thanks
Kishon
^ permalink raw reply
* Re: [PATCH v4 3/8] spi: stm32: Add 'SPI_SIMPLEX_RX', 'SPI_3WIRE_RX' support for stm32f4
From: dillon min @ 2020-05-23 1:35 UTC (permalink / raw)
To: Mark Brown
Cc: Rob Herring, p.zabel, Maxime Coquelin,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Alexandre Torgue, thierry.reding, Sam Ravnborg, Dave Airlie,
Daniel Vetter, Michael Turquette, Stephen Boyd, Linux ARM,
linux-kernel, linux-spi, linux-stm32, open list:DRM PANEL DRIVERS,
linux-clk
In-Reply-To: <20200522162901.GP5801@sirena.org.uk>
On Sat, May 23, 2020 at 12:29 AM Mark Brown <broonie@kernel.org> wrote:
>
> On Fri, May 22, 2020 at 11:59:25PM +0800, dillon min wrote:
>
> > but, after spi-core create a dummy tx_buf or rx_buf, then i can't get
> > the correct spi_3wire direction.
> > actually, this dummy tx_buf is useless for SPI_3WIRE. it's has meaning
> > for SPI_SIMPLE_RX mode,
> > simulate SPI_FULL_DUMPLEX
>
> Oh, that's annoying. I think the fix here is in the core, it should
> ignore MUST_TX and MUST_RX in 3WIRE mode since they clearly make no
> sense there.
How about add below changes to spi-core
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 8994545..bfd465c 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -1022,7 +1022,8 @@ static int spi_map_msg(struct spi_controller
*ctlr, struct spi_message *msg)
void *tmp;
unsigned int max_tx, max_rx;
- if (ctlr->flags & (SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX)) {
+ if ((ctlr->flags & (SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX)) &&
+ !(msg->spi->mode & SPI_3WIRE)) {
max_tx = 0;
max_rx = 0;
for my board, lcd panel ilitek ill9341 use 3wire mode, gyro l3gd20 use
simplex rx mode.
it's has benefits to l3gd20, no impact to ili9341.
if it's fine to spi-core, i will include it to my next submits.
thanks
best regards.
Dillon
^ permalink raw reply related
* Re: [PATCH 00/19] Implement NTB Controller using multiple PCI EP
From: Kishon Vijay Abraham I @ 2020-05-23 1:47 UTC (permalink / raw)
To: Rob Herring
Cc: Lorenzo Pieralisi, Arnd Bergmann, Jon Mason, Dave Jiang,
Allen Hubbe, Tom Joseph, Bjorn Helgaas, Greg Kroah-Hartman,
Jonathan Corbet, PCI, Linux Doc Mailing List,
linux-kernel@vger.kernel.org, devicetree, linux-ntb
In-Reply-To: <CAL_JsqKxe5FtZfiQKcQFFLOM5F52kx-q8vZspPTXhcWg+3rJvQ@mail.gmail.com>
Hi Rob,
On 5/22/2020 9:41 PM, Rob Herring wrote:
> On Thu, May 14, 2020 at 8:59 AM Kishon Vijay Abraham I <kishon@ti.com> wrote:
>>
>> This series is about implementing SW defined NTB using
>> multiple endpoint instances. This series has been tested using
>> 2 endpoint instances in J7 connected to two DRA7 boards. However there
>> is nothing platform specific for the NTB functionality.
>>
>> This was presented in Linux Plumbers Conference. The presentation
>> can be found @ [1]
>
> I'd like to know why putting this into DT is better than configfs.
> Does it solve some problem? Doing things in userspace is so much
> easier and more flexible than modifying and updating a DT.
It's a lot cleaner to have an endpoint function bound to two different endpoint
controller using device tree than configfs.
+ epf_bus {
+ compatible = "pci-epf-bus";
+
+ func@0 {
+ compatible = "pci-epf-ntb";
+ epcs = <&pcie0_ep>, <&pcie1_ep>;
+ epc-names = "primary", "secondary";
+ reg = <0>;
+ epf,vendor-id = /bits/ 16 <0x104c>;
+ epf,device-id = /bits/ 16 <0xb00d>;
+ num-mws = <4>;
+ mws-size = <0x0 0x100000>, <0x0 0x100000>, <0x0 0x100000>, <0x0 0x100000>;
+ };
For device tree, just using phandles is enough and the driver can easily parse
DT to get EPCs bound to the endpoint function
+ epcs = <&pcie0_ep>, <&pcie1_ep>;
+ epc-names = "primary", "secondary";
This would be
ln -s functions/pci-epf-ntb/func1 controllers/2900000.pcie-ep/
ln -s functions/pci-epf-ntb/func1 controllers/2910000.pcie-ep/
pci_epc_epf_link() should then maintain the order of EPC bound to EPF and
designate one as PRIMARY_INTERFACE and the second as SECONDARY_INTERFACE.
pci_epf_bind() should be made to behave differently for NTB case.
While the standard properties (like vendorid, deviceid) has configfs entries,
additional logic would be required for adding function specific fields like
num-mws and mws-size above.
While all this support could be added in configfs, it looks simpler to
represent then in DT.
>
> I don't really think the PCI endpoint stuff is mature enough to be
> putting into DT either.
I think this will anyways come when we have to export real HW peripherals to
the remote HOST using EP controller.
Thanks
Kishon
^ permalink raw reply
* Re: [RFC][PATCH 0/2] Add support for using reserved memory for ima buffer pass
From: Thiago Jung Bauermann @ 2020-05-23 4:08 UTC (permalink / raw)
To: Prakhar Srivastava
Cc: Rob Herring, Mark Rutland, linux-arm-kernel, linux-kernel,
linuxppc-dev, devicetree, linux-integrity, linux-security-module,
catalin.marinas, will, mpe, benh, paulus, frowand.list, zohar,
dmitry.kasatkin, jmorris, serge, pasha.tatashin, allison,
kstewart, takahiro.akashi, tglx, vincenzo.frascino, masahiroy,
james.morse, bhsharma, mbrugger, hsinyi, tao.li, christophe.leroy,
gregkh, nramas, tusharsu, balajib
In-Reply-To: <7701df90-a68b-b710-4279-9d64e45ee792@linux.microsoft.com>
Hello Prakhar,
Prakhar Srivastava <prsriva@linux.microsoft.com> writes:
> On 5/12/20 4:05 PM, Rob Herring wrote:
>> On Wed, May 06, 2020 at 10:50:04PM -0700, Prakhar Srivastava wrote:
>>> Hi Mark,
>>
>> Please don't top post.
>>
>>> This patch set currently only address the Pure DT implementation.
>>> EFI and ACPI implementations will be posted in subsequent patchsets.
>>>
>>> The logs are intended to be carried over the kexec and once read the
>>> logs are no longer needed and in prior conversation with James(
>>> https://lore.kernel.org/linux-arm-kernel/0053eb68-0905-4679-c97a-00c5cb6f1abb@arm.com/)
>>> the apporach of using a chosen node doesn't
>>> support the case.
>>>
>>> The DT entries make the reservation permanent and thus doesnt need kernel
>>> segments to be used for this, however using a chosen-node with
>>> reserved memory only changes the node information but memory still is
>>> reserved via reserved-memory section.
>>
>> I think Mark's point was whether it needs to be permanent. We don't
>> hardcode the initrd address for example.
>>
> Thankyou for clarifying my misunderstanding, i am modelling this keeping to the
> TPM log implementation that uses a reserved memory. I will rev up the version
> with chosen-node support.
> That will make the memory reservation free after use.
Nice. Do you intend to use the same property that powerpc uses
(linux,ima-kexec-buffer)?
>>> On 5/5/20 2:59 AM, Mark Rutland wrote:
>>>> Hi Prakhar,
>>>>
>>>> On Mon, May 04, 2020 at 01:38:27PM -0700, Prakhar Srivastava wrote:
>>>>> IMA during kexec(kexec file load) verifies the kernel signature and measures
>>
>> What's IMAIMA is a LSM attempting to detect if files have been accidentally or
> maliciously altered, both remotely and locally, it can also be used
> to appraise a file's measurement against a "good" value stored as an extended
> attribute, and enforce local file integrity.
>
> IMA also validates and measures the signers of the kernel and initrd
> during kexec. The measurements are extended to PCR 10(configurable) and the logs
> stored in memory, however once kexec'd the logs are lost. Kexec is used as
> secondary boot loader in may use cases and loosing the signer
> creates a security hole.
>
> This patch is an implementation to carry over the logs and making it
> possible to remotely validate the signers of the kernel and initrd. Such a
> support exits only in powerpc.
> This patch makes the carry over of logs architecture independent and puts the
> complexity in a driver.
If I'm not mistaken, the code at arch/powerpc/kexec/ima.c isn't actually
powerpc-specific. It could be moved to an arch-independent directory and
used by any other architecture which supports device trees.
I think that's the simplest way forward. And to be honest I'm still
trying to understand why you didn't take that approach. Did you try it
and hit some obstacle or noticed a disadvantage for your use case?
--
Thiago Jung Bauermann
IBM Linux Technology Center
^ permalink raw reply
* [PATCH] arm64: dts: qcom: enable pm8150 rtc
From: Jonathan Marek @ 2020-05-23 4:12 UTC (permalink / raw)
To: linux-arm-msm
Cc: Andy Gross, Bjorn Andersson, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
I don't see any reason for it to be disabled by default.
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
---
arch/arm64/boot/dts/qcom/pm8150.dtsi | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi
index c0b197458665..b738c263f9d1 100644
--- a/arch/arm64/boot/dts/qcom/pm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi
@@ -64,8 +64,6 @@ rtc@6000 {
reg = <0x6000>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
-
- status = "disabled";
};
pm8150_gpios: gpio@c000 {
--
2.26.1
^ permalink raw reply related
* Re: [V8, 2/2] media: i2c: ov02a10: Add OV02A10 image sensor driver
From: Dongchun Zhu @ 2020-05-23 4:50 UTC (permalink / raw)
To: Tomasz Figa
Cc: linus.walleij, bgolaszewski, mchehab, andriy.shevchenko, robh+dt,
mark.rutland, sakari.ailus, drinkcat, matthias.bgg, bingbu.cao,
srv_heupstream, linux-mediatek, linux-arm-kernel, sj.huang,
linux-media, devicetree, louis.kuo, shengnan.wang, dongchun.zhu
In-Reply-To: <20200521193204.GA14214@chromium.org>
Hi Tomasz,
Thanks for the review. My replies are as below.
On Thu, 2020-05-21 at 19:32 +0000, Tomasz Figa wrote:
> Hi Dongchun,
>
> On Sat, May 09, 2020 at 04:06:27PM +0800, Dongchun Zhu wrote:
> > Add a V4L2 sub-device driver for OV02A10 image sensor.
> >
> > Signed-off-by: Dongchun Zhu <dongchun.zhu@mediatek.com>
> > ---
> > MAINTAINERS | 1 +
> > drivers/media/i2c/Kconfig | 13 +
> > drivers/media/i2c/Makefile | 1 +
> > drivers/media/i2c/ov02a10.c | 1094 +++++++++++++++++++++++++++++++++++++++++++
> > 4 files changed, 1109 insertions(+)
> > create mode 100644 drivers/media/i2c/ov02a10.c
> >
>
> Thank you for the patch. Please see my comments inline.
>
> [snip]
> > +struct ov02a10 {
> > + u32 eclk_freq;
> > + u32 mipi_clock_tx_speed;
> > +
> > + struct clk *eclk;
> > + struct gpio_desc *pd_gpio;
> > + struct gpio_desc *n_rst_gpio;
> > + struct regulator_bulk_data supplies[OV02A10_NUM_SUPPLIES];
> > +
> > + bool streaming;
> > + bool upside_down;
> > + bool mipi_clock_tx_speed_select_enable;
> > + bool mipi_clock_hs_mode_enable;
> > +
> > + /*
> > + * Serialize control access, get/set format, get selection
> > + * and start streaming.
> > + */
> > + struct mutex mutex;
> > + struct v4l2_subdev subdev;
> > + struct media_pad pad;
> > + struct v4l2_ctrl *anal_gain;
> > + struct v4l2_ctrl *exposure;
> > + struct v4l2_ctrl *hblank;
> > + struct v4l2_ctrl *vblank;
> > + struct v4l2_ctrl *test_pattern;
> > + struct v4l2_mbus_framefmt fmt;
>
> nit: Remove the tabs between types and names and use single spaces. As you
> can see above, even tabs don't guarantee equal alignment. And they actually
> make adding fields more difficult, because if a longer field is added, the
> alignment breaks.
>
Thanks for sharing the rule of adding new fields.
Fixed in next release.
> [snip]
> > +static int ov02a10_read_smbus(struct ov02a10 *ov02a10, unsigned char reg,
> > + unsigned char *val)
> > +{
> > + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
> > + int ret;
> > +
> > + ret = i2c_smbus_read_byte_data(client, reg);
> > +
>
> nit: Unnecessary blank line.
>
Sorry for the carelessness.
Fixed in next release.
> > + if (ret < 0)
> > + return ret;
> > +
> > + *val = (unsigned char)ret;
> > +
> > + return 0;
> > +}
> [snip]
> > +static int __maybe_unused ov02a10_power_on(struct device *dev)
>
> How is it possible that this function may be unused? If this driver allows
> disabling runtime PM, then there is still a need to configure the clock,
> regulator and GPIO. If not, there shouldn't be a case where this function
> is unused.
>
Thanks for the reminder.
Modifier __maybe_unused would be removed in next release.
> > +{
> > + struct i2c_client *client = to_i2c_client(dev);
> > + struct v4l2_subdev *sd = i2c_get_clientdata(client);
> > + struct ov02a10 *ov02a10 = to_ov02a10(sd);
> > + int ret;
> > +
> > + gpiod_set_value_cansleep(ov02a10->n_rst_gpio, 0);
> > + gpiod_set_value_cansleep(ov02a10->pd_gpio, 0);
> > +
> > + ret = clk_prepare_enable(ov02a10->eclk);
> > + if (ret < 0) {
> > + dev_err(dev, "failed to enable eclk\n");
> > + return ret;
> > + }
> > +
> > + ret = regulator_bulk_enable(OV02A10_NUM_SUPPLIES, ov02a10->supplies);
> > + if (ret < 0) {
> > + dev_err(dev, "failed to enable regulators\n");
> > + goto disable_clk;
> > + }
> > + usleep_range(5000, 6000);
> > +
> > + gpiod_set_value_cansleep(ov02a10->pd_gpio, 1);
>
> This is a "powerdown" GPIO. It must be set to 0 if the sensor is to be
> powered on.
>
The value set by gpiod_set_value_cansleep() API actually depends upon
GPIO polarity defined in DT.
Since I set GPIO_ACTIVE_LOW to powerdown,
gpiod_set_value_cansleep(gpio_desc, value) would set !value to
gpio_desc.
Thus here powerdown would be low-state when sensor is powered on.
For GPIO polarity, I also post a comment to the binding patch.
> > + usleep_range(5000, 6000);
> > +
> > + gpiod_set_value_cansleep(ov02a10->n_rst_gpio, 1);
> > + usleep_range(5000, 6000);
> > +
> > + ret = ov02a10_check_sensor_id(ov02a10);
> > + if (ret)
> > + goto disable_regulator;
> > +
> > + return 0;
> > +
> > +disable_regulator:
> > + regulator_bulk_disable(OV02A10_NUM_SUPPLIES, ov02a10->supplies);
> > +disable_clk:
> > + clk_disable_unprepare(ov02a10->eclk);
> > +
> > + return ret;
> > +}
> > +
> > +static int __maybe_unused ov02a10_power_off(struct device *dev)
> > +{
> > + struct i2c_client *client = to_i2c_client(dev);
> > + struct v4l2_subdev *sd = i2c_get_clientdata(client);
> > + struct ov02a10 *ov02a10 = to_ov02a10(sd);
> > +
> > + gpiod_set_value_cansleep(ov02a10->n_rst_gpio, 0);
> > + clk_disable_unprepare(ov02a10->eclk);
> > + gpiod_set_value_cansleep(ov02a10->pd_gpio, 0);
>
> Similar comment as above. To power off the sensor, the "powerdown" GPIO
> needs to be active, i.e. 1.
>
Similar setting.
It depends upon GPIO polarity.
> [snip]
> > +/*
> > + * ov02a10_set_exposure - Function called when setting exposure time
> > + * @priv: Pointer to device structure
> > + * @val: Variable for exposure time, in the unit of micro-second
> > + *
> > + * Set exposure time based on input value.
> > + *
> > + * Return: 0 on success
> > + */
> > +static int ov02a10_set_exposure(struct ov02a10 *ov02a10, int val)
> > +{
> > + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
> > + int ret;
> > +
> > + ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE);
> > + if (ret < 0)
> > + return ret;
>
> How does this page switch work? According to the documentation I have, the
> register allows selecting between a few different pages. However, there
> should be two page pointers - one for the AP and the other for the sensor,
> so that when the AP is programming page X, the sensor can have consistent
> settings from page Y. But here we only set one register and always with
> page 1.
>
Thanks for the carefully observation.
The style or requirement of register setting here is suggested by OV
vendor.
From hardware signal behavior and effect-test, this setting should be
right.
But for your concern, we can also dig into it with OV.
Let's have time to talk with OV.
> > +
> > + ret = i2c_smbus_write_byte_data(client, OV02A10_REG_EXPOSURE_H,
> > + val >> OV02A10_EXP_SHIFT);
> > + if (ret < 0)
> > + return ret;
> > +
> > + ret = i2c_smbus_write_byte_data(client, OV02A10_REG_EXPOSURE_L, val);
> > + if (ret < 0)
> > + return ret;
> > +
> > + return i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
> > + REG_ENABLE);
>
> This patch defines REG_GLOBAL_EFFECTIVE to 0x01. I don't see such register
> mentioned in the documentation.
>
There may be several editions of sensor documentation.
From OV, 0x01 is one register shall be updated to keep
exposure/gain/test pattern... register settings effective.
> > +}
> > +
> > +static int ov02a10_set_gain(struct ov02a10 *ov02a10, int val)
> > +{
> > + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
> > + int ret;
> > +
> > + ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE);
> > + if (ret < 0)
> > + return ret;
> > +
> > + ret = i2c_smbus_write_byte_data(client, OV02A10_REG_GAIN, val);
> > + if (ret < 0)
> > + return ret;
> > +
> > + return i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
> > + REG_ENABLE);
> > +}
> > +
> > +static int ov02a10_set_vblank(struct ov02a10 *ov02a10, int val)
> > +{
> > + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
> > + u32 vts = val + ov02a10->cur_mode->height - OV02A10_BASIC_LINE;
> > + int ret;
> > +
> > + ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE);
> > + if (ret < 0)
> > + return ret;
> > +
> > + ret = i2c_smbus_write_byte_data(client, OV02A10_REG_VTS_H,
> > + vts >> OV02A10_VTS_SHIFT);
> > + if (ret < 0)
> > + return ret;
> > +
> > + ret = i2c_smbus_write_byte_data(client, OV02A10_REG_VTS_L, vts);
> > + if (ret < 0)
> > + return ret;
> > +
> > + return i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
> > + REG_ENABLE);
> > +}
> > +
> > +static int ov02a10_set_test_pattern(struct ov02a10 *ov02a10, int pattern)
> > +{
> > + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
> > + int ret;
> > +
> > + if (pattern)
> > + pattern = OV02A10_TEST_PATTERN_ENABLE;
>
> Is this necessary? Our control can be 0 for disabled and 1 for color bars.
> The latter is the same as the above macro.
>
Yes. It looks redundant here.
Fixed in next release.
> [snip]
> > +static int ov02a10_initialize_controls(struct ov02a10 *ov02a10)
> > +{
> > + struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
> > + const struct ov02a10_mode *mode;
> > + struct v4l2_ctrl_handler *handler;
> > + struct v4l2_ctrl *ctrl;
> > + u64 exposure_max;
> > + u32 pixel_rate, h_blank;
> > + int ret;
> > +
> > + handler = &ov02a10->ctrl_handler;
> > + mode = ov02a10->cur_mode;
> > + ret = v4l2_ctrl_handler_init(handler, 7);
> > + if (ret)
> > + return ret;
> > +
> > + handler->lock = &ov02a10->mutex;
> > +
> > + ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ, 0, 0,
> > + link_freq_menu_items);
> > + if (ctrl)
> > + ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
> > +
> > + pixel_rate = to_pixel_rate(0);
> > + v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, 0, pixel_rate, 1,
> > + pixel_rate);
> > +
> > + h_blank = mode->hts_def - mode->width;
> > + ov02a10->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
> > + h_blank, h_blank, 1, h_blank);
> > + if (ov02a10->hblank)
> > + ov02a10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
> > +
>
> Do we need to hold a pointer to this control? We don't seem to ever access
> it anywhere else in the driver.
>
No.
These lines would be removed in next release.
> > + ov02a10->vblank = v4l2_ctrl_new_std(handler, &ov02a10_ctrl_ops,
> > + V4L2_CID_VBLANK, mode->vts_def -
> > + mode->height,
> > + OV02A10_VTS_MAX - mode->height, 1,
> > + mode->vts_def - mode->height);
> > +
>
> Ditto.
>
These lines would be removed in next release.
> > + exposure_max = mode->vts_def - 4;
> > + ov02a10->exposure = v4l2_ctrl_new_std(handler, &ov02a10_ctrl_ops,
> > + V4L2_CID_EXPOSURE,
> > + OV02A10_EXPOSURE_MIN,
> > + exposure_max,
> > + OV02A10_EXPOSURE_STEP,
> > + mode->exp_def);
> > +
> > + ov02a10->anal_gain = v4l2_ctrl_new_std(handler, &ov02a10_ctrl_ops,
> > + V4L2_CID_ANALOGUE_GAIN,
> > + OV02A10_GAIN_MIN,
> > + OV02A10_GAIN_MAX,
> > + OV02A10_GAIN_STEP,
> > + OV02A10_GAIN_DEFAULT);
>
> Ditto.
>
Fields: exposure and anal_gain would be removed in next release.
But v4l2_ctrl_new_std remains, as user may set exp/gain.
> > +
> > + ov02a10->test_pattern =
> > + v4l2_ctrl_new_std_menu_items(handler, &ov02a10_ctrl_ops,
> > + V4L2_CID_TEST_PATTERN,
> > + ARRAY_SIZE(ov02a10_test_pattern_menu) -
> > + 1, 0, 0,
> > + ov02a10_test_pattern_menu);
>
> Ditto.
>
Fields: test_pattern would be removed in next release.
But v4l2_ctrl_new_std_menu_items remains.
> [snip]
> > + ov02a10->pd_gpio = devm_gpiod_get(dev, "powerdown", GPIOD_OUT_HIGH);
> > + if (IS_ERR(ov02a10->pd_gpio)) {
> > + ret = PTR_ERR(ov02a10->pd_gpio);
> > + dev_err(dev, "failed to get powerdown-gpios %d\n", ret);
> > + return ret;
> > + }
> > +
> > + ov02a10->n_rst_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
>
> I've asked a question about the right convention to define active low pins,
> but I don't remember seeing an answer. We need to clarify this to avoid
> confusion. Especially since the current binding documentation doesn't
> mention anything about the sensor being active low. Let me also post a
> comment to the binding patch.
>
It depends upon GPIO polarity, however, which may not be emphasized in
current DT version.
> > + if (IS_ERR(ov02a10->n_rst_gpio)) {
> > + ret = PTR_ERR(ov02a10->n_rst_gpio);
> > + dev_err(dev, "failed to get reset-gpios %d\n", ret);
> > + return ret;
> > + }
> > +
> > + for (i = 0; i < OV02A10_NUM_SUPPLIES; i++)
> > + ov02a10->supplies[i].supply = ov02a10_supply_names[i];
> > +
> > + ret = devm_regulator_bulk_get(dev, OV02A10_NUM_SUPPLIES,
> > + ov02a10->supplies);
> > + if (ret) {
> > + dev_err(dev, "failed to get regulators\n");
> > + return ret;
> > + }
> > +
> > + mutex_init(&ov02a10->mutex);
> > + ov02a10->cur_mode = &supported_modes[0];
> > + ret = ov02a10_initialize_controls(ov02a10);
> > + if (ret) {
> > + dev_err(dev, "failed to initialize controls\n");
> > + goto err_destroy_mutex;
> > + }
> > +
> > + ov02a10->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
> > + ov02a10->subdev.entity.ops = &ov02a10_subdev_entity_ops;
> > + ov02a10->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
> > + ov02a10->pad.flags = MEDIA_PAD_FL_SOURCE;
> > + ret = media_entity_pads_init(&ov02a10->subdev.entity, 1, &ov02a10->pad);
> > + if (ret < 0) {
> > + dev_err(dev, "failed to init entity pads: %d", ret);
> > + goto err_free_handler;
> > + }
> > +
> > + pm_runtime_enable(dev);
> > + if (!pm_runtime_enabled(dev)) {
> > + ret = ov02a10_power_on(dev);
> > + if (ret < 0) {
> > + dev_err(dev, "failed to power on: %d\n", ret);
> > + goto err_clean_entity;
> > + }
> > + }
> > +
> > + ret = v4l2_async_register_subdev(&ov02a10->subdev);
> > + if (ret) {
> > + dev_err(dev, "failed to register V4L2 subdev: %d", ret);
> > + goto err_clean_entity;
> > + }
> > +
> > + return 0;
> > +
> > +err_clean_entity:
>
> Need to power off if !pm_runtime_enabled().
>
Thanks for the reminder.
Fixed in next release by adding power off into err_clean_entity.
> Best regards,
> Tomasz
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: enable pm8150 rtc
From: Bjorn Andersson @ 2020-05-23 5:40 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20200523041201.32065-1-jonathan@marek.ca>
On Fri 22 May 21:12 PDT 2020, Jonathan Marek wrote:
> I don't see any reason for it to be disabled by default.
>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Regards,
Bjorn
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> arch/arm64/boot/dts/qcom/pm8150.dtsi | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi
> index c0b197458665..b738c263f9d1 100644
> --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi
> @@ -64,8 +64,6 @@ rtc@6000 {
> reg = <0x6000>;
> reg-names = "rtc", "alarm";
> interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
> -
> - status = "disabled";
> };
>
> pm8150_gpios: gpio@c000 {
> --
> 2.26.1
>
^ permalink raw reply
* RE: [PATCH v1 0/3] fix macb phy probe failure if phy-reset is not handled
From: Sagar Kadam @ 2020-05-23 5:44 UTC (permalink / raw)
To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
devicetree@vger.kernel.org, robh+dt@kernel.org
Cc: palmer@dabbelt.com, Paul Walmsley, atish.patra@wdc.com
In-Reply-To: <1589378222-15238-1-git-send-email-sagar.kadam@sifive.com>
Hello,
A gentle reminder. Any suggestions here?
BR,
Sagar
> -----Original Message-----
> From: Sagar Kadam <sagar.kadam@sifive.com>
> Sent: Wednesday, May 13, 2020 7:27 PM
> To: linux-kernel@vger.kernel.org; linux-riscv@lists.infradead.org;
> devicetree@vger.kernel.org; robh+dt@kernel.org
> Cc: palmer@dabbelt.com; Paul Walmsley <paul.walmsley@sifive.com>;
> atish.patra@wdc.com; Sagar Kadam <sagar.kadam@sifive.com>
> Subject: [PATCH v1 0/3] fix macb phy probe failure if phy-reset is not
> handled
>
> HiFive Unleashed is having VSC8541-01 ethernet phy device and requires a
> specific reset sequence of 0-1-0-1 in order to use it in unmanaged mode.
> This series addresses a corner case where phy reset is not handled by boot
> stages prior to linux.
> Somewhat similar unreliable phy probe failure was reported and discussed
> here [1].
> The macb driver fails to detect the ethernet phy device if the bootloader
> doesn't provide a proper reset sequence to the phy device or the phy itself
> is in some invalid state. Currently, the FSBL is resetting the phy device, and
> so there is no issue observed in the linux network setup.
>
> The series is based on linux-5.7-rc5.
> Patch 1: Add the OUI to the phy dt node to fix issue of missing mdio device
> Patch 2 and 3:
> Resetting phy needs GPIO support so add to dt and defconfig.
>
> [1] https://lkml.org/lkml/2018/11/29/154
>
> To reproduce the issue:
> 1. Comment out VSC8541 reset sequence in fsbl/main.c
> from within the freedom-u540-c000-bootloader.
> 2. Build and flash fsbl.bin to micro sdcard.
>
> Boot the board and bootlog will show network setup failure messages as:
>
> [ 1.069474] libphy: MACB_mii_bus: probed [ 1.073092] mdio_bus
> 10090000.ethernet-ffffffff: MDIO device at address 0
> is missing
> .....
> [ 1.979252] macb 10090000.ethernet eth0: Could not attach PHY (-19)
>
> 3. Now apply the series build, and boot kernel.
> 4. MACB and VSC8541 driver get successfully probed and the network is set
> without any failure.
>
>
> So irrespective of whether the prior stages handle the phy reset sequence,
> the probing is successful in both the cases of cold boot and warm boot.
>
> Change History:
> ===============================
> V1:
> -Ignore 4th patch as suggested and so removed it from the series.
> -Verified this series on 5.7-rc5.
>
> V0: Base RFC patch. Verified on 5.7-rc2
>
>
> Sagar Shrikant Kadam (3):
> dts: phy: fix missing mdio device and probe failure of vsc8541-01
> device
> dts: phy: add GPIO number and active state used for phy reset
> riscv: defconfig: enable gpio support for HiFive Unleashed
>
> arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 2 ++
> arch/riscv/configs/defconfig | 2 ++
> 2 files changed, 4 insertions(+)
>
> --
> 2.7.4
^ permalink raw reply
* Re: [PATCH v4 01/16] spi: dw: Add Tx/Rx finish wait methods to the MID DMA
From: Serge Semin @ 2020-05-23 8:34 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Andy Shevchenko, Linus Walleij, Vinod Koul,
Feng Tang, Grant Likely, Alan Cox, Georgy Vlasov, Ramil Zaripov,
Alexey Malahov, Thomas Bogendoerfer, Paul Burton, Ralf Baechle,
Arnd Bergmann, Rob Herring, linux-mips, devicetree,
Wan Ahmad Zainie, Thomas Gleixner, Jarkko Nikula, wuxu.wu,
Clement Leger, Linus Walleij, linux-spi, linux-kernel
In-Reply-To: <20200522152241.GK5801@sirena.org.uk>
On Fri, May 22, 2020 at 04:22:41PM +0100, Mark Brown wrote:
> On Fri, May 22, 2020 at 05:45:42PM +0300, Serge Semin wrote:
> > On Fri, May 22, 2020 at 05:36:39PM +0300, Andy Shevchenko wrote:
>
> > > My point is: let's warn and see if anybody comes with a bug report. We will
> > > solve an issue when it appears.
>
> > In my environment the stack trace happened (strictly speaking it has been a
> > BUG() invoked due to the sleep_range() called within the tasklet) when SPI bus
> > had been enabled to work with !8MHz! clock. It's quite normal bus speed.
> > So we'll get the bug report pretty soon.)
>
> Right, that definitely needs to be fixed then - 8MHz is indeed a totally
> normal clock rate for SPI so people will hit it. I guess if there's a
> noticable performance hit to defer to thread then we could implement
> both and look at how long the delay is going to be to decide which to
> use, that's annoyingly complicated though so if the overhead is small
> enough we could just not bother.
As I suggested before we can implement a solution without performance drop.
Just wait for the DMA completion locally in the dw_spi_dma_transfer() method and
return 0 instead of 1 from the transfer_one() callback. In that function we'll
wait while DMA finishes its business, after that we can check the Tx/Rx FIFO
emptiness and wait for the data to be completely transferred with delays or
sleeps or whatever.
There are several drawback of the solution:
1) We need to alter the dw_spi_transfer_one() method in a way one would return
0 instead of 1 (for DMA) so the generic spi_transfer_one_message() method would
be aware that the transfer has been finished and it doesn't need to wait by
calling the spi_transfer_wait() method.
2) Locally in the dw_spi_dma_transfer() I have to implement a method similar
to the spi_transfer_wait(). It won't be that similar though. We can predict a
completion timeout better in here due to using a more exact SPI bus frequency.
Anyway in the rest of aspects the functions will be nearly the same.
3) Not using spi_transfer_wait() means we also have to locally add the SPI
timeout statistics incremental.
So to speak the local wait method will be like this:
+static int dw_spi_dma_wait(struct dw_spi *dws, struct spi_transfer *xfer)
+{
+ struct spi_statistics *statm = &dws->master->statistics;
+ struct spi_statistics *stats = &dws->master->cur_msg->spi->statistics;
+ unsigned long ms = 1;
+
+ ms = xfer->len * MSEC_PER_SEC * BITS_PER_BYTE;
+ ms /= xfer->effective_speed_hz;
+ ms += ms + 200;
+
+ ms = wait_for_completion_timeout(&dws->xfer_completion,
+ msecs_to_jiffies(ms));
+
+ if (ms == 0) {
+ SPI_STATISTICS_INCREMENT_FIELD(statm, timedout);
+ SPI_STATISTICS_INCREMENT_FIELD(stats, timedout);
+ dev_err(&dws->master->cur_msg->spi->dev,
+ "SPI transfer timed out\n");
+ return -ETIMEDOUT;
+ }
+}
NOTE Currently the DW APB SSI driver doesn't set xfer->effective_speed_hz, though as
far as I can see that field exists there to be initialized by the SPI controller
driver, right? If so, strange it isn't done in any SPI drivers...
Then we can use that method to wait for the DMA transfers completion:
+static int dw_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)
+{
+ ...
+ /* DMA channels/buffers preparation and the transfers execution */
+ ...
+
+ ret = dw_spi_dma_wait(dws, xfer);
+ if (ret)
+ return ret;
+
+ ret = dw_spi_dma_wait_tx_done(dws);
+ if (ret)
+ return ret;
+
+ ret = dw_spi_dma_wait_rx_done(dws);
+ if (ret)
+ return ret;
+
+ return 0;
+}
What do think about this?
If you don't mind I'll send this fixup separately from the patchset we discuss
here, since it's going to be a series of patches. What would be better for you:
implement it based on the current DW APB SSI driver, or on top of this
patchset "spi: dw: Add generic DW DMA controller support" (it's being under
review in this email thread) ? Anyway, if the fixup is getting to be that
complicated, will it have to be backported to another stable kernels?
-Sergey
^ permalink raw reply
* [V9, 0/2] media: i2c: Add support for OV02A10 sensor
From: Dongchun Zhu @ 2020-05-23 8:41 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, mchehab, andriy.shevchenko, robh+dt,
mark.rutland, sakari.ailus, drinkcat, tfiga, matthias.bgg,
bingbu.cao
Cc: srv_heupstream, linux-mediatek, linux-arm-kernel, sj.huang,
linux-media, devicetree, louis.kuo, shengnan.wang, dongchun.zhu
Hello,
This series adds DT bindings in YAML and V4L2 sub-device driver for Omnivision's
OV02A10 2 megapixel CMOS 1/5" sensor, which has a single MIPI lane interface(I/F)
and output format of 10-bit RAW.
The driver is implemented with V4L2 Framework.
- Async registered as one V4L2 sub-device.
- As the first component of camera system including Seninf/ISP processing pipeline.
- A media entity that provides one source pad in common and two for dual camera.
Previous versions of this patch-set can be found here:
v8: https://lore.kernel.org/linux-media/20200509080627.23222-1-dongchun.zhu@mediatek.com/
v7: https://lore.kernel.org/linux-media/20200430080924.1140-1-dongchun.zhu@mediatek.com/
v6: https://lore.kernel.org/linux-media/20191211112849.16705-1-dongchun.zhu@mediatek.com/
v5: https://lore.kernel.org/linux-media/20191104105713.24311-1-dongchun.zhu@mediatek.com/
v4: https://lore.kernel.org/linux-media/20190907092728.23897-1-dongchun.zhu@mediatek.com/
v3: https://lore.kernel.org/linux-media/20190819034331.13098-1-dongchun.zhu@mediatek.com/
v2: https://lore.kernel.org/linux-media/20190704084651.3105-1-dongchun.zhu@mediatek.com/
v1: https://lore.kernel.org/linux-media/20190523102204.24112-1-dongchun.zhu@mediatek.com/
Changes of v9 mainly address comments from Rob, Sakari, Tomasz, Andy.
Including:
- Add more detailed descriptions for powerdown-gpios and reset-gpios in DT
- Set default to properties: "rotation" and "ovti,mipi-tx-speed"
- Remove reserved values of "ovti,mipi-tx-speed"
- Use ARRAY_SIZE() directly to replace of defining macro function
- Remove __maybe_unused specifier for ov02a10_power_on and ov02a10_power_off
- Refine driver by removing unnecessary logs and unused macros or fields.
- Power off sensor when async register subdev failed and !pm_runtime_enabled()
- Fix other review comments in v8
Please review.
Thanks.
Dongchun Zhu (2):
media: dt-bindings: media: i2c: Document OV02A10 bindings
media: i2c: ov02a10: Add OV02A10 image sensor driver
.../bindings/media/i2c/ovti,ov02a10.yaml | 172 ++++
MAINTAINERS | 8 +
drivers/media/i2c/Kconfig | 13 +
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/ov02a10.c | 1025 ++++++++++++++++++++
5 files changed, 1219 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/i2c/ovti,ov02a10.yaml
create mode 100644 drivers/media/i2c/ov02a10.c
--
2.9.2
^ permalink raw reply
* [V9, 2/2] media: i2c: ov02a10: Add OV02A10 image sensor driver
From: Dongchun Zhu @ 2020-05-23 8:41 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, mchehab, andriy.shevchenko, robh+dt,
mark.rutland, sakari.ailus, drinkcat, tfiga, matthias.bgg,
bingbu.cao
Cc: srv_heupstream, linux-mediatek, linux-arm-kernel, sj.huang,
linux-media, devicetree, louis.kuo, shengnan.wang, dongchun.zhu
In-Reply-To: <20200523084103.31276-1-dongchun.zhu@mediatek.com>
Add a V4L2 sub-device driver for OV02A10 image sensor.
Signed-off-by: Dongchun Zhu <dongchun.zhu@mediatek.com>
---
MAINTAINERS | 1 +
drivers/media/i2c/Kconfig | 13 +
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/ov02a10.c | 1025 +++++++++++++++++++++++++++++++++++++++++++
4 files changed, 1040 insertions(+)
create mode 100644 drivers/media/i2c/ov02a10.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 63a2335..e7677c5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12395,6 +12395,7 @@ L: linux-media@vger.kernel.org
S: Maintained
T: git git://linuxtv.org/media_tree.git
F: Documentation/devicetree/bindings/media/i2c/ovti,ov02a10.yaml
+F: drivers/media/i2c/ov02a10.c
OMNIVISION OV13858 SENSOR DRIVER
M: Sakari Ailus <sakari.ailus@linux.intel.com>
diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index 125d596..d8572cd 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -655,6 +655,19 @@ config VIDEO_IMX355
To compile this driver as a module, choose M here: the
module will be called imx355.
+config VIDEO_OV02A10
+ tristate "OmniVision OV02A10 sensor support"
+ depends on I2C && VIDEO_V4L2
+ select MEDIA_CONTROLLER
+ select VIDEO_V4L2_SUBDEV_API
+ select V4L2_FWNODE
+ help
+ This is a Video4Linux2 sensor driver for the OmniVision
+ OV02A10 camera.
+
+ To compile this driver as a module, choose M here: the
+ module will be called ov02a10.
+
config VIDEO_OV2640
tristate "OmniVision OV2640 sensor support"
depends on VIDEO_V4L2 && I2C
diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index 77bf7d0..6566dd9 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -63,6 +63,7 @@ obj-$(CONFIG_VIDEO_VP27SMPX) += vp27smpx.o
obj-$(CONFIG_VIDEO_SONY_BTF_MPX) += sony-btf-mpx.o
obj-$(CONFIG_VIDEO_UPD64031A) += upd64031a.o
obj-$(CONFIG_VIDEO_UPD64083) += upd64083.o
+obj-$(CONFIG_VIDEO_OV02A10) += ov02a10.o
obj-$(CONFIG_VIDEO_OV2640) += ov2640.o
obj-$(CONFIG_VIDEO_OV2680) += ov2680.o
obj-$(CONFIG_VIDEO_OV2685) += ov2685.o
diff --git a/drivers/media/i2c/ov02a10.c b/drivers/media/i2c/ov02a10.c
new file mode 100644
index 0000000..160a0b5
--- /dev/null
+++ b/drivers/media/i2c/ov02a10.c
@@ -0,0 +1,1025 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2020 MediaTek Inc.
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/regulator/consumer.h>
+#include <media/media-entity.h>
+#include <media/v4l2-async.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-subdev.h>
+#include <media/v4l2-fwnode.h>
+
+#define CHIP_ID 0x2509
+#define OV02A10_REG_CHIP_ID_H 0x02
+#define OV02A10_REG_CHIP_ID_L 0x03
+
+/* Bit[1] vertical upside down */
+/* Bit[0] horizontal mirror */
+#define REG_MIRROR_FLIP_CONTROL 0x3f
+
+/* Orientation */
+#define REG_MIRROR_FLIP_ENABLE 0x03
+
+/* Bit[2:0] MIPI transmission speed select */
+#define TX_SPEED_AREA_SEL 0xa1
+#define OV02A10_MIPI_TX_SPEED_DEFAULT 0x03
+
+#define REG_PAGE_SWITCH 0xfd
+#define REG_GLOBAL_EFFECTIVE 0x01
+#define REG_ENABLE BIT(0)
+
+#define REG_SC_CTRL_MODE 0xac
+#define SC_CTRL_MODE_STANDBY 0x00
+#define SC_CTRL_MODE_STREAMING 0x01
+
+#define OV02A10_EXP_SHIFT 8
+#define OV02A10_REG_EXPOSURE_H 0x03
+#define OV02A10_REG_EXPOSURE_L 0x04
+#define OV02A10_EXPOSURE_MIN 4
+#define OV02A10_EXPOSURE_MAX_MARGIN 4
+#define OV02A10_EXPOSURE_STEP 1
+
+#define OV02A10_VTS_SHIFT 8
+#define OV02A10_REG_VTS_H 0x05
+#define OV02A10_REG_VTS_L 0x06
+#define OV02A10_BASIC_LINE 1224
+
+#define OV02A10_REG_GAIN 0x24
+#define OV02A10_GAIN_MIN 0x10
+#define OV02A10_GAIN_MAX 0xf8
+#define OV02A10_GAIN_STEP 0x01
+#define OV02A10_GAIN_DEFAULT 0x40
+
+/* Test pattern control */
+#define OV02A10_REG_TEST_PATTERN 0xb6
+
+#define HZ_PER_MHZ 1000000L
+#define OV02A10_LINK_FREQ_390MHZ (390 * HZ_PER_MHZ)
+#define OV02A10_ECLK_FREQ (24 * HZ_PER_MHZ)
+#define OV02A10_DATA_LANES 1
+#define OV02A10_BITS_PER_SAMPLE 10
+
+static const char * const ov02a10_supply_names[] = {
+ "dovdd", /* Digital I/O power */
+ "avdd", /* Analog power */
+ "dvdd", /* Digital core power */
+};
+
+struct ov02a10_reg {
+ u8 addr;
+ u8 val;
+};
+
+struct ov02a10_reg_list {
+ u32 num_of_regs;
+ const struct ov02a10_reg *regs;
+};
+
+struct ov02a10_mode {
+ u32 width;
+ u32 height;
+ u32 exp_def;
+ u32 hts_def;
+ u32 vts_def;
+ const struct ov02a10_reg_list reg_list;
+};
+
+struct ov02a10 {
+ u32 eclk_freq;
+ u32 mipi_clock_tx_speed;
+
+ struct clk *eclk;
+ struct gpio_desc *pd_gpio;
+ struct gpio_desc *n_rst_gpio;
+ struct regulator_bulk_data supplies[ARRAY_SIZE(ov02a10_supply_names)];
+
+ bool streaming;
+ bool upside_down;
+
+ /*
+ * Serialize control access, get/set format, get selection
+ * and start streaming.
+ */
+ struct mutex mutex;
+ struct v4l2_subdev subdev;
+ struct media_pad pad;
+ struct v4l2_mbus_framefmt fmt;
+ struct v4l2_ctrl_handler ctrl_handler;
+ struct v4l2_ctrl *exposure;
+
+ const struct ov02a10_mode *cur_mode;
+};
+
+static inline struct ov02a10 *to_ov02a10(struct v4l2_subdev *sd)
+{
+ return container_of(sd, struct ov02a10, subdev);
+}
+
+/*
+ * eclk 24Mhz
+ * pclk 39Mhz
+ * linelength 934(0x3a6)
+ * framelength 1390(0x56E)
+ * grabwindow_width 1600
+ * grabwindow_height 1200
+ * max_framerate 30fps
+ * mipi_datarate per lane 780Mbps
+ */
+static const struct ov02a10_reg ov02a10_1600x1200_regs[] = {
+ {0xfd, 0x01},
+ {0xac, 0x00},
+ {0xfd, 0x00},
+ {0x2f, 0x29},
+ {0x34, 0x00},
+ {0x35, 0x21},
+ {0x30, 0x15},
+ {0x33, 0x01},
+ {0xfd, 0x01},
+ {0x44, 0x00},
+ {0x2a, 0x4c},
+ {0x2b, 0x1e},
+ {0x2c, 0x60},
+ {0x25, 0x11},
+ {0x03, 0x01},
+ {0x04, 0xae},
+ {0x09, 0x00},
+ {0x0a, 0x02},
+ {0x06, 0xa6},
+ {0x31, 0x00},
+ {0x24, 0x40},
+ {0x01, 0x01},
+ {0xfb, 0x73},
+ {0xfd, 0x01},
+ {0x16, 0x04},
+ {0x1c, 0x09},
+ {0x21, 0x42},
+ {0x12, 0x04},
+ {0x13, 0x10},
+ {0x11, 0x40},
+ {0x33, 0x81},
+ {0xd0, 0x00},
+ {0xd1, 0x01},
+ {0xd2, 0x00},
+ {0x50, 0x10},
+ {0x51, 0x23},
+ {0x52, 0x20},
+ {0x53, 0x10},
+ {0x54, 0x02},
+ {0x55, 0x20},
+ {0x56, 0x02},
+ {0x58, 0x48},
+ {0x5d, 0x15},
+ {0x5e, 0x05},
+ {0x66, 0x66},
+ {0x68, 0x68},
+ {0x6b, 0x00},
+ {0x6c, 0x00},
+ {0x6f, 0x40},
+ {0x70, 0x40},
+ {0x71, 0x0a},
+ {0x72, 0xf0},
+ {0x73, 0x10},
+ {0x75, 0x80},
+ {0x76, 0x10},
+ {0x84, 0x00},
+ {0x85, 0x10},
+ {0x86, 0x10},
+ {0x87, 0x00},
+ {0x8a, 0x22},
+ {0x8b, 0x22},
+ {0x19, 0xf1},
+ {0x29, 0x01},
+ {0xfd, 0x01},
+ {0x9d, 0x16},
+ {0xa0, 0x29},
+ {0xa1, 0x03},
+ {0xad, 0x62},
+ {0xae, 0x00},
+ {0xaf, 0x85},
+ {0xb1, 0x01},
+ {0x8e, 0x06},
+ {0x8f, 0x40},
+ {0x90, 0x04},
+ {0x91, 0xb0},
+ {0x45, 0x01},
+ {0x46, 0x00},
+ {0x47, 0x6c},
+ {0x48, 0x03},
+ {0x49, 0x8b},
+ {0x4a, 0x00},
+ {0x4b, 0x07},
+ {0x4c, 0x04},
+ {0x4d, 0xb7},
+ {0xf0, 0x40},
+ {0xf1, 0x40},
+ {0xf2, 0x40},
+ {0xf3, 0x40},
+ {0x3f, 0x00},
+ {0xfd, 0x01},
+ {0x05, 0x00},
+ {0x06, 0xa6},
+ {0xfd, 0x01},
+};
+
+static const char * const ov02a10_test_pattern_menu[] = {
+ "Disabled",
+ "Color Bar",
+};
+
+static const s64 link_freq_menu_items[] = {
+ OV02A10_LINK_FREQ_390MHZ,
+};
+
+static u64 to_pixel_rate(u32 f_index)
+{
+ u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV02A10_DATA_LANES;
+
+ do_div(pixel_rate, OV02A10_BITS_PER_SAMPLE);
+
+ return pixel_rate;
+}
+
+static const struct ov02a10_mode supported_modes[] = {
+ {
+ .width = 1600,
+ .height = 1200,
+ .exp_def = 0x01ae,
+ .hts_def = 0x03a6,
+ .vts_def = 0x056e,
+ .reg_list = {
+ .num_of_regs = ARRAY_SIZE(ov02a10_1600x1200_regs),
+ .regs = ov02a10_1600x1200_regs,
+ },
+ },
+};
+
+static int ov02a10_write_array(struct ov02a10 *ov02a10,
+ const struct ov02a10_reg_list *r_list)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ unsigned int i;
+ int ret;
+
+ for (i = 0; i < r_list->num_of_regs; i++) {
+ ret = i2c_smbus_write_byte_data(client, r_list->regs[i].addr,
+ r_list->regs[i].val);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ov02a10_read_smbus(struct ov02a10 *ov02a10, unsigned char reg,
+ unsigned char *val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ int ret;
+
+ ret = i2c_smbus_read_byte_data(client, reg);
+ if (ret < 0)
+ return ret;
+
+ *val = (unsigned char)ret;
+
+ return 0;
+}
+
+static void ov02a10_fill_fmt(const struct ov02a10_mode *mode,
+ struct v4l2_mbus_framefmt *fmt)
+{
+ fmt->width = mode->width;
+ fmt->height = mode->height;
+ fmt->field = V4L2_FIELD_NONE;
+}
+
+static int ov02a10_set_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
+{
+ struct ov02a10 *ov02a10 = to_ov02a10(sd);
+ struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format;
+
+ mutex_lock(&ov02a10->mutex);
+
+ if (ov02a10->streaming) {
+ mutex_unlock(&ov02a10->mutex);
+ return -EBUSY;
+ }
+
+ /* Only one sensor mode supported */
+ mbus_fmt->code = ov02a10->fmt.code;
+ ov02a10_fill_fmt(ov02a10->cur_mode, mbus_fmt);
+ ov02a10->fmt = fmt->format;
+
+ mutex_unlock(&ov02a10->mutex);
+
+ return 0;
+}
+
+static int ov02a10_get_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
+{
+ struct ov02a10 *ov02a10 = to_ov02a10(sd);
+ struct v4l2_mbus_framefmt *mbus_fmt = &fmt->format;
+
+ mutex_lock(&ov02a10->mutex);
+
+ fmt->format = ov02a10->fmt;
+ mbus_fmt->code = ov02a10->fmt.code;
+ ov02a10_fill_fmt(ov02a10->cur_mode, mbus_fmt);
+
+ mutex_unlock(&ov02a10->mutex);
+
+ return 0;
+}
+
+static int ov02a10_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ struct ov02a10 *ov02a10 = to_ov02a10(sd);
+
+ if (code->index >= ARRAY_SIZE(supported_modes))
+ return -EINVAL;
+
+ code->code = ov02a10->fmt.code;
+
+ return 0;
+}
+
+static int ov02a10_enum_frame_sizes(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_frame_size_enum *fse)
+{
+ if (fse->index >= ARRAY_SIZE(supported_modes))
+ return -EINVAL;
+
+ fse->min_width = supported_modes[fse->index].width;
+ fse->max_width = supported_modes[fse->index].width;
+ fse->max_height = supported_modes[fse->index].height;
+ fse->min_height = supported_modes[fse->index].height;
+
+ return 0;
+}
+
+static int ov02a10_check_sensor_id(struct ov02a10 *ov02a10)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ u16 id;
+ u8 chip_id_h;
+ u8 chip_id_l;
+ int ret;
+
+ /* Check sensor revision */
+ ret = ov02a10_read_smbus(ov02a10, OV02A10_REG_CHIP_ID_H, &chip_id_h);
+ if (ret)
+ return ret;
+
+ ret = ov02a10_read_smbus(ov02a10, OV02A10_REG_CHIP_ID_L, &chip_id_l);
+ if (ret)
+ return ret;
+
+ id = (chip_id_h << 8) | chip_id_l;
+ if (id != CHIP_ID) {
+ dev_err(&client->dev, "Unexpected sensor id(%04x)\n", id);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int ov02a10_power_on(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct ov02a10 *ov02a10 = to_ov02a10(sd);
+ int ret;
+
+ gpiod_set_value_cansleep(ov02a10->n_rst_gpio, 0);
+ gpiod_set_value_cansleep(ov02a10->pd_gpio, 0);
+
+ ret = clk_prepare_enable(ov02a10->eclk);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable eclk\n");
+ return ret;
+ }
+
+ ret = regulator_bulk_enable(ARRAY_SIZE(ov02a10_supply_names),
+ ov02a10->supplies);
+ if (ret < 0) {
+ dev_err(dev, "failed to enable regulators\n");
+ goto disable_clk;
+ }
+ usleep_range(5000, 6000);
+
+ gpiod_set_value_cansleep(ov02a10->pd_gpio, 1);
+ usleep_range(5000, 6000);
+
+ gpiod_set_value_cansleep(ov02a10->n_rst_gpio, 1);
+ usleep_range(5000, 6000);
+
+ ret = ov02a10_check_sensor_id(ov02a10);
+ if (ret)
+ goto disable_regulator;
+
+ return 0;
+
+disable_regulator:
+ regulator_bulk_disable(ARRAY_SIZE(ov02a10_supply_names),
+ ov02a10->supplies);
+disable_clk:
+ clk_disable_unprepare(ov02a10->eclk);
+
+ return ret;
+}
+
+static int ov02a10_power_off(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct ov02a10 *ov02a10 = to_ov02a10(sd);
+
+ gpiod_set_value_cansleep(ov02a10->n_rst_gpio, 0);
+ clk_disable_unprepare(ov02a10->eclk);
+ gpiod_set_value_cansleep(ov02a10->pd_gpio, 0);
+ regulator_bulk_disable(ARRAY_SIZE(ov02a10_supply_names),
+ ov02a10->supplies);
+
+ return 0;
+}
+
+static int __ov02a10_start_stream(struct ov02a10 *ov02a10)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ const struct ov02a10_reg_list *reg_list;
+ int ret;
+
+ /* Apply default values of current mode */
+ reg_list = &ov02a10->cur_mode->reg_list;
+ ret = ov02a10_write_array(ov02a10, reg_list);
+ if (ret)
+ return ret;
+
+ /* Apply customized values from user */
+ ret = __v4l2_ctrl_handler_setup(ov02a10->subdev.ctrl_handler);
+ if (ret)
+ return ret;
+
+ /* Set orientation to 180 degree */
+ if (ov02a10->upside_down) {
+ ret = i2c_smbus_write_byte_data(client, REG_MIRROR_FLIP_CONTROL,
+ REG_MIRROR_FLIP_ENABLE);
+ if (ret) {
+ dev_err(&client->dev, "failed to set orientation\n");
+ return ret;
+ }
+ ret = i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
+ REG_ENABLE);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* Set mipi TX speed according to DT property */
+ if (ov02a10->mipi_clock_tx_speed != OV02A10_MIPI_TX_SPEED_DEFAULT) {
+ ret = i2c_smbus_write_byte_data(client, TX_SPEED_AREA_SEL,
+ ov02a10->mipi_clock_tx_speed);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* Set stream on register */
+ return i2c_smbus_write_byte_data(client, REG_SC_CTRL_MODE,
+ SC_CTRL_MODE_STREAMING);
+}
+
+static int __ov02a10_stop_stream(struct ov02a10 *ov02a10)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+
+ return i2c_smbus_write_byte_data(client, REG_SC_CTRL_MODE,
+ SC_CTRL_MODE_STANDBY);
+}
+
+static int ov02a10_entity_init_cfg(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg)
+{
+ struct v4l2_subdev_format fmt = {
+ .which = cfg ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE,
+ .format = {
+ .width = 1600,
+ .height = 1200,
+ }
+ };
+
+ ov02a10_set_fmt(sd, cfg, &fmt);
+
+ return 0;
+}
+
+static int ov02a10_s_stream(struct v4l2_subdev *sd, int on)
+{
+ struct ov02a10 *ov02a10 = to_ov02a10(sd);
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ int ret;
+
+ mutex_lock(&ov02a10->mutex);
+
+ if (ov02a10->streaming == on)
+ goto unlock_and_return;
+
+ if (on) {
+ ret = pm_runtime_get_sync(&client->dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(&client->dev);
+ goto unlock_and_return;
+ }
+
+ ret = __ov02a10_start_stream(ov02a10);
+ if (ret) {
+ __ov02a10_stop_stream(ov02a10);
+ ov02a10->streaming = !on;
+ goto err_rpm_put;
+ }
+ } else {
+ __ov02a10_stop_stream(ov02a10);
+ pm_runtime_put(&client->dev);
+ }
+
+ ov02a10->streaming = on;
+ mutex_unlock(&ov02a10->mutex);
+
+ return 0;
+
+err_rpm_put:
+ pm_runtime_put(&client->dev);
+unlock_and_return:
+ mutex_unlock(&ov02a10->mutex);
+
+ return ret;
+}
+
+static const struct dev_pm_ops ov02a10_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ pm_runtime_force_resume)
+ SET_RUNTIME_PM_OPS(ov02a10_power_off, ov02a10_power_on, NULL)
+};
+
+/*
+ * ov02a10_set_exposure - Function called when setting exposure time
+ * @priv: Pointer to device structure
+ * @val: Variable for exposure time, in the unit of micro-second
+ *
+ * Set exposure time based on input value.
+ *
+ * Return: 0 on success
+ */
+static int ov02a10_set_exposure(struct ov02a10 *ov02a10, int val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ int ret;
+
+ ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE);
+ if (ret < 0)
+ return ret;
+
+ ret = i2c_smbus_write_byte_data(client, OV02A10_REG_EXPOSURE_H,
+ val >> OV02A10_EXP_SHIFT);
+ if (ret < 0)
+ return ret;
+
+ ret = i2c_smbus_write_byte_data(client, OV02A10_REG_EXPOSURE_L, val);
+ if (ret < 0)
+ return ret;
+
+ return i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
+ REG_ENABLE);
+}
+
+static int ov02a10_set_gain(struct ov02a10 *ov02a10, int val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ int ret;
+
+ ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE);
+ if (ret < 0)
+ return ret;
+
+ ret = i2c_smbus_write_byte_data(client, OV02A10_REG_GAIN, val);
+ if (ret < 0)
+ return ret;
+
+ return i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
+ REG_ENABLE);
+}
+
+static int ov02a10_set_vblank(struct ov02a10 *ov02a10, int val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ u32 vts = val + ov02a10->cur_mode->height - OV02A10_BASIC_LINE;
+ int ret;
+
+ ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE);
+ if (ret < 0)
+ return ret;
+
+ ret = i2c_smbus_write_byte_data(client, OV02A10_REG_VTS_H,
+ vts >> OV02A10_VTS_SHIFT);
+ if (ret < 0)
+ return ret;
+
+ ret = i2c_smbus_write_byte_data(client, OV02A10_REG_VTS_L, vts);
+ if (ret < 0)
+ return ret;
+
+ return i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
+ REG_ENABLE);
+}
+
+static int ov02a10_set_test_pattern(struct ov02a10 *ov02a10, int pattern)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ int ret;
+
+ ret = i2c_smbus_write_byte_data(client, REG_PAGE_SWITCH, REG_ENABLE);
+ if (ret < 0)
+ return ret;
+
+ ret = i2c_smbus_write_byte_data(client, OV02A10_REG_TEST_PATTERN,
+ pattern);
+ if (ret < 0)
+ return ret;
+
+ ret = i2c_smbus_write_byte_data(client, REG_GLOBAL_EFFECTIVE,
+ REG_ENABLE);
+ if (ret < 0)
+ return ret;
+
+ return i2c_smbus_write_byte_data(client, REG_SC_CTRL_MODE,
+ SC_CTRL_MODE_STREAMING);
+}
+
+static int ov02a10_set_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct ov02a10 *ov02a10 = container_of(ctrl->handler,
+ struct ov02a10, ctrl_handler);
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ s64 max_expo;
+ int ret;
+
+ /* Propagate change of current control to all related controls */
+ if (ctrl->id == V4L2_CID_VBLANK) {
+ /* Update max exposure while meeting expected vblanking */
+ max_expo = ov02a10->cur_mode->height + ctrl->val -
+ OV02A10_EXPOSURE_MAX_MARGIN;
+ __v4l2_ctrl_modify_range(ov02a10->exposure,
+ ov02a10->exposure->minimum, max_expo,
+ ov02a10->exposure->step,
+ ov02a10->exposure->default_value);
+ }
+
+ /* V4L2 controls values will be applied only when power is already up */
+ if (!pm_runtime_get_if_in_use(&client->dev))
+ return 0;
+
+ switch (ctrl->id) {
+ case V4L2_CID_EXPOSURE:
+ ret = ov02a10_set_exposure(ov02a10, ctrl->val);
+ break;
+ case V4L2_CID_ANALOGUE_GAIN:
+ ret = ov02a10_set_gain(ov02a10, ctrl->val);
+ break;
+ case V4L2_CID_VBLANK:
+ ret = ov02a10_set_vblank(ov02a10, ctrl->val);
+ break;
+ case V4L2_CID_TEST_PATTERN:
+ ret = ov02a10_set_test_pattern(ov02a10, ctrl->val);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ };
+
+ pm_runtime_put(&client->dev);
+
+ return ret;
+}
+
+static const struct v4l2_subdev_video_ops ov02a10_video_ops = {
+ .s_stream = ov02a10_s_stream,
+};
+
+static const struct v4l2_subdev_pad_ops ov02a10_pad_ops = {
+ .init_cfg = ov02a10_entity_init_cfg,
+ .enum_mbus_code = ov02a10_enum_mbus_code,
+ .enum_frame_size = ov02a10_enum_frame_sizes,
+ .get_fmt = ov02a10_get_fmt,
+ .set_fmt = ov02a10_set_fmt,
+};
+
+static const struct v4l2_subdev_ops ov02a10_subdev_ops = {
+ .video = &ov02a10_video_ops,
+ .pad = &ov02a10_pad_ops,
+};
+
+static const struct media_entity_operations ov02a10_subdev_entity_ops = {
+ .link_validate = v4l2_subdev_link_validate,
+};
+
+static const struct v4l2_ctrl_ops ov02a10_ctrl_ops = {
+ .s_ctrl = ov02a10_set_ctrl,
+};
+
+static int ov02a10_initialize_controls(struct ov02a10 *ov02a10)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov02a10->subdev);
+ const struct ov02a10_mode *mode;
+ struct v4l2_ctrl_handler *handler;
+ struct v4l2_ctrl *ctrl;
+ u64 exposure_max;
+ u32 pixel_rate;
+ int ret;
+
+ handler = &ov02a10->ctrl_handler;
+ mode = ov02a10->cur_mode;
+ ret = v4l2_ctrl_handler_init(handler, 7);
+ if (ret)
+ return ret;
+
+ handler->lock = &ov02a10->mutex;
+
+ ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ, 0, 0,
+ link_freq_menu_items);
+ if (ctrl)
+ ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+
+ pixel_rate = to_pixel_rate(0);
+ v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE, 0, pixel_rate, 1,
+ pixel_rate);
+
+ exposure_max = mode->vts_def - 4;
+ ov02a10->exposure = v4l2_ctrl_new_std(handler, &ov02a10_ctrl_ops,
+ V4L2_CID_EXPOSURE,
+ OV02A10_EXPOSURE_MIN,
+ exposure_max,
+ OV02A10_EXPOSURE_STEP,
+ mode->exp_def);
+
+ v4l2_ctrl_new_std(handler, &ov02a10_ctrl_ops,
+ V4L2_CID_ANALOGUE_GAIN,
+ OV02A10_GAIN_MIN,
+ OV02A10_GAIN_MAX,
+ OV02A10_GAIN_STEP,
+ OV02A10_GAIN_DEFAULT);
+
+ v4l2_ctrl_new_std_menu_items(handler, &ov02a10_ctrl_ops,
+ V4L2_CID_TEST_PATTERN,
+ ARRAY_SIZE(ov02a10_test_pattern_menu) - 1,
+ 0, 0, ov02a10_test_pattern_menu);
+
+ if (handler->error) {
+ ret = handler->error;
+ dev_err(&client->dev, "failed to init controls(%d)\n", ret);
+ goto err_free_handler;
+ }
+
+ ov02a10->subdev.ctrl_handler = handler;
+
+ return 0;
+
+err_free_handler:
+ v4l2_ctrl_handler_free(handler);
+
+ return ret;
+}
+
+static int ov02a10_check_hwcfg(struct device *dev, struct ov02a10 *ov02a10)
+{
+ struct fwnode_handle *ep;
+ struct fwnode_handle *fwnode = dev_fwnode(dev);
+ struct v4l2_fwnode_endpoint bus_cfg = {
+ .bus_type = V4L2_MBUS_CSI2_DPHY,
+ };
+ unsigned int i, j;
+ int ret;
+
+ if (!fwnode)
+ return -EINVAL;
+
+ ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
+ if (!ep)
+ return -ENXIO;
+
+ ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
+ fwnode_handle_put(ep);
+ if (ret)
+ return ret;
+
+ if (!bus_cfg.nr_of_link_frequencies) {
+ dev_err(dev, "no link frequencies defined");
+ ret = -EINVAL;
+ goto check_hwcfg_error;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
+ for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
+ if (link_freq_menu_items[i] ==
+ bus_cfg.link_frequencies[j])
+ break;
+ }
+
+ if (j == bus_cfg.nr_of_link_frequencies) {
+ dev_err(dev, "no link frequency %lld supported",
+ link_freq_menu_items[i]);
+ ret = -EINVAL;
+ goto check_hwcfg_error;
+ }
+ }
+
+check_hwcfg_error:
+ v4l2_fwnode_endpoint_free(&bus_cfg);
+
+ return ret;
+}
+
+static int ov02a10_probe(struct i2c_client *client)
+{
+ struct device *dev = &client->dev;
+ struct ov02a10 *ov02a10;
+ unsigned int rotation;
+ unsigned int clock_lane_tx_speed;
+ unsigned int i;
+ int ret;
+
+ ov02a10 = devm_kzalloc(dev, sizeof(*ov02a10), GFP_KERNEL);
+ if (!ov02a10)
+ return -ENOMEM;
+
+ ret = ov02a10_check_hwcfg(dev, ov02a10);
+ if (ret) {
+ dev_err(dev, "failed to check HW configuration: %d", ret);
+ return ret;
+ }
+
+ v4l2_i2c_subdev_init(&ov02a10->subdev, client, &ov02a10_subdev_ops);
+ ov02a10->mipi_clock_tx_speed = OV02A10_MIPI_TX_SPEED_DEFAULT;
+ ov02a10->fmt.code = MEDIA_BUS_FMT_SBGGR10_1X10;
+
+ /* Optional indication of physical rotation of sensor */
+ ret = fwnode_property_read_u32(dev_fwnode(dev), "rotation", &rotation);
+ if (!ret && rotation == 180) {
+ ov02a10->upside_down = true;
+ ov02a10->fmt.code = MEDIA_BUS_FMT_SRGGB10_1X10;
+ }
+
+ /* Optional indication of mipi TX speed */
+ ret = fwnode_property_read_u32(dev_fwnode(dev), "ovti,mipi-tx-speed",
+ &clock_lane_tx_speed);
+
+ if (!ret)
+ ov02a10->mipi_clock_tx_speed = clock_lane_tx_speed;
+
+ /* Get system clock (eclk) */
+ ov02a10->eclk = devm_clk_get(dev, "eclk");
+ if (IS_ERR(ov02a10->eclk)) {
+ ret = PTR_ERR(ov02a10->eclk);
+ dev_err(dev, "failed to get eclk %d\n", ret);
+ return ret;
+ }
+
+ ret = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
+ &ov02a10->eclk_freq);
+ if (ret) {
+ dev_err(dev, "failed to get eclk frequency\n");
+ return ret;
+ }
+
+ ret = clk_set_rate(ov02a10->eclk, ov02a10->eclk_freq);
+ if (ret) {
+ dev_err(dev, "failed to set eclk frequency (24MHz)\n");
+ return ret;
+ }
+
+ if (clk_get_rate(ov02a10->eclk) != OV02A10_ECLK_FREQ) {
+ dev_warn(dev, "wrong eclk frequency %d Hz, expected: %d Hz\n",
+ ov02a10->eclk_freq, OV02A10_ECLK_FREQ);
+ return -EINVAL;
+ }
+
+ ov02a10->pd_gpio = devm_gpiod_get(dev, "powerdown", GPIOD_OUT_HIGH);
+ if (IS_ERR(ov02a10->pd_gpio)) {
+ ret = PTR_ERR(ov02a10->pd_gpio);
+ dev_err(dev, "failed to get powerdown-gpios %d\n", ret);
+ return ret;
+ }
+
+ ov02a10->n_rst_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
+ if (IS_ERR(ov02a10->n_rst_gpio)) {
+ ret = PTR_ERR(ov02a10->n_rst_gpio);
+ dev_err(dev, "failed to get reset-gpios %d\n", ret);
+ return ret;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(ov02a10_supply_names); i++)
+ ov02a10->supplies[i].supply = ov02a10_supply_names[i];
+
+ ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ov02a10_supply_names),
+ ov02a10->supplies);
+ if (ret) {
+ dev_err(dev, "failed to get regulators\n");
+ return ret;
+ }
+
+ mutex_init(&ov02a10->mutex);
+ ov02a10->cur_mode = &supported_modes[0];
+ ret = ov02a10_initialize_controls(ov02a10);
+ if (ret) {
+ dev_err(dev, "failed to initialize controls\n");
+ goto err_destroy_mutex;
+ }
+
+ ov02a10->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+ ov02a10->subdev.entity.ops = &ov02a10_subdev_entity_ops;
+ ov02a10->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
+ ov02a10->pad.flags = MEDIA_PAD_FL_SOURCE;
+ ret = media_entity_pads_init(&ov02a10->subdev.entity, 1, &ov02a10->pad);
+ if (ret < 0) {
+ dev_err(dev, "failed to init entity pads: %d", ret);
+ goto err_free_handler;
+ }
+
+ pm_runtime_enable(dev);
+ if (!pm_runtime_enabled(dev)) {
+ ret = ov02a10_power_on(dev);
+ if (ret < 0) {
+ dev_err(dev, "failed to power on: %d\n", ret);
+ goto err_free_handler;
+ }
+ }
+
+ ret = v4l2_async_register_subdev(&ov02a10->subdev);
+ if (ret) {
+ dev_err(dev, "failed to register V4L2 subdev: %d", ret);
+ if (!pm_runtime_enabled(dev))
+ ov02a10_power_off(dev);
+ goto err_clean_entity;
+ }
+
+ return 0;
+
+err_clean_entity:
+ media_entity_cleanup(&ov02a10->subdev.entity);
+err_free_handler:
+ v4l2_ctrl_handler_free(ov02a10->subdev.ctrl_handler);
+err_destroy_mutex:
+ mutex_destroy(&ov02a10->mutex);
+
+ return ret;
+}
+
+static int ov02a10_remove(struct i2c_client *client)
+{
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct ov02a10 *ov02a10 = to_ov02a10(sd);
+
+ v4l2_async_unregister_subdev(sd);
+ media_entity_cleanup(&sd->entity);
+ v4l2_ctrl_handler_free(sd->ctrl_handler);
+ pm_runtime_disable(&client->dev);
+ if (!pm_runtime_status_suspended(&client->dev))
+ ov02a10_power_off(&client->dev);
+ pm_runtime_set_suspended(&client->dev);
+ mutex_destroy(&ov02a10->mutex);
+
+ return 0;
+}
+
+static const struct of_device_id ov02a10_of_match[] = {
+ { .compatible = "ovti,ov02a10" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, ov02a10_of_match);
+
+static struct i2c_driver ov02a10_i2c_driver = {
+ .driver = {
+ .name = "ov02a10",
+ .pm = &ov02a10_pm_ops,
+ .of_match_table = ov02a10_of_match,
+ },
+ .probe_new = &ov02a10_probe,
+ .remove = &ov02a10_remove,
+};
+
+module_i2c_driver(ov02a10_i2c_driver);
+
+MODULE_AUTHOR("Dongchun Zhu <dongchun.zhu@mediatek.com>");
+MODULE_DESCRIPTION("OmniVision OV02A10 sensor driver");
+MODULE_LICENSE("GPL v2");
+
--
2.9.2
^ permalink raw reply related
* [V9, 1/2] media: dt-bindings: media: i2c: Document OV02A10 bindings
From: Dongchun Zhu @ 2020-05-23 8:41 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, mchehab, andriy.shevchenko, robh+dt,
mark.rutland, sakari.ailus, drinkcat, tfiga, matthias.bgg,
bingbu.cao
Cc: srv_heupstream, linux-mediatek, linux-arm-kernel, sj.huang,
linux-media, devicetree, louis.kuo, shengnan.wang, dongchun.zhu
In-Reply-To: <20200523084103.31276-1-dongchun.zhu@mediatek.com>
Add DT bindings documentation for Omnivision OV02A10 image sensor.
Signed-off-by: Dongchun Zhu <dongchun.zhu@mediatek.com>
---
.../bindings/media/i2c/ovti,ov02a10.yaml | 172 +++++++++++++++++++++
MAINTAINERS | 7 +
2 files changed, 179 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/i2c/ovti,ov02a10.yaml
diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov02a10.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov02a10.yaml
new file mode 100644
index 0000000..56f31b5
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov02a10.yaml
@@ -0,0 +1,172 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright (c) 2020 MediaTek Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/ovti,ov02a10.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Omnivision OV02A10 CMOS Sensor Device Tree Bindings
+
+maintainers:
+ - Dongchun Zhu <dongchun.zhu@mediatek.com>
+
+description: |-
+ The Omnivision OV02A10 is a low-cost, high performance, 1/5-inch, 2 megapixel
+ image sensor, which is the latest production derived from Omnivision's CMOS
+ image sensor technology. Ihis chip supports high frame rate speeds up to 30fps
+ @ 1600x1200 (UXGA) resolution transferred over a 1-lane MIPI interface. The
+ sensor output is available via CSI-2 serial data output.
+
+properties:
+ compatible:
+ const: ovti,ov02a10
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: top mux camtg clock
+ - description: divider clock
+
+ clock-names:
+ items:
+ - const: eclk
+ - const: freq_mux
+
+ clock-frequency:
+ description:
+ Frequency of the eclk clock in Hertz.
+
+ dovdd-supply:
+ description:
+ Definition of the regulator used as Digital I/O voltage supply.
+
+ avdd-supply:
+ description:
+ Definition of the regulator used as Analog voltage supply.
+
+ dvdd-supply:
+ description:
+ Definition of the regulator used as Digital core voltage supply.
+
+ powerdown-gpios:
+ description:
+ Must be the device tree identifier of the GPIO connected to the
+ PD_PAD pin. This pin is used to place the OV02A10 into Standby mode
+ or Shutdown mode. As the line is active low, it should be
+ marked GPIO_ACTIVE_LOW.
+
+ reset-gpios:
+ description:
+ Must be the device tree identifier of the GPIO connected to the
+ RST_PD pin. If specified, it will be asserted during driver probe.
+ As the line is active high, it should be marked GPIO_ACTIVE_HIGH.
+
+ rotation:
+ description:
+ Definition of the sensor's placement.
+ allOf:
+ - $ref: "/schemas/types.yaml#/definitions/uint32"
+ - enum:
+ - 0 # Sensor Mounted Upright
+ - 180 # Sensor Mounted Upside Down
+ default: 0
+
+ ovti,mipi-tx-speed:
+ description:
+ Indication of MIPI transmission speed select, which is to control D-PHY
+ timing setting by adjusting MIPI clock voltage to improve the clock
+ driver capability.
+ allOf:
+ - $ref: "/schemas/types.yaml#/definitions/uint32"
+ - enum:
+ - 0 # 20MHz - 30MHz
+ - 1 # 30MHz - 50MHz
+ - 2 # 50MHz - 75MHz
+ - 3 # 75MHz - 100MHz
+ - 4 # 100MHz - 130MHz
+ default: 3
+
+ # See ../video-interfaces.txt for details
+ port:
+ type: object
+ additionalProperties: false
+
+ properties:
+ endpoint:
+ type: object
+ additionalProperties: false
+
+ properties:
+ data-lanes:
+ maxItems: 1
+
+ link-frequencies: true
+ remote-endpoint: true
+
+ required:
+ - data-lanes
+ - link-frequencies
+ - remote-endpoint
+
+ required:
+ - endpoint
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - clock-frequency
+ - dovdd-supply
+ - avdd-supply
+ - dvdd-supply
+ - powerdown-gpios
+ - reset-gpios
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ov02a10: camera-sensor@3d {
+ compatible = "ovti,ov02a10";
+ reg = <0x3d>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&clk_24m_cam>;
+
+ clocks = <&topckgen CLK_TOP_MUX_CAMTG>,
+ <&topckgen CLK_TOP_UNIVP_192M_D8>;
+ clock-names = "eclk", "freq_mux";
+ clock-frequency = <24000000>;
+
+ rotation = <180>;
+ ovti,mipi-tx-speed = <4>;
+
+ dovdd-supply = <&mt6358_vcamio_reg>;
+ avdd-supply = <&mt6358_vcama1_reg>;
+ dvdd-supply = <&mt6358_vcn18_reg>;
+
+ powerdown-gpios = <&pio 107 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&pio 109 GPIO_ACTIVE_HIGH>;
+
+ port {
+ wcam_out: endpoint {
+ data-lanes = <1>;
+ link-frequencies = /bits/ 64 <390000000>;
+ remote-endpoint = <&mipi_in_wcam>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index e64e5db..63a2335 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12389,6 +12389,13 @@ M: Harald Welte <laforge@gnumonks.org>
S: Maintained
F: drivers/char/pcmcia/cm4040_cs.*
+OMNIVISION OV02A10 SENSOR DRIVER
+M: Dongchun Zhu <dongchun.zhu@mediatek.com>
+L: linux-media@vger.kernel.org
+S: Maintained
+T: git git://linuxtv.org/media_tree.git
+F: Documentation/devicetree/bindings/media/i2c/ovti,ov02a10.yaml
+
OMNIVISION OV13858 SENSOR DRIVER
M: Sakari Ailus <sakari.ailus@linux.intel.com>
L: linux-media@vger.kernel.org
--
2.9.2
^ permalink raw reply related
* Re: [PATCH net 1/4] net: ethernet: fec: move GPR register offset and bit into DT
From: Fuzzey, Martin @ 2020-05-23 9:55 UTC (permalink / raw)
To: Andy Duan; +Cc: David S. Miller, netdev, Rob Herring, Shawn Guo, devicetree
In-Reply-To: <1589963516-26703-2-git-send-email-fugang.duan@nxp.com>
Hi Andy,
> Fixes: da722186f654(net: fec: set GPR bit on suspend by DT configuration)
Just a nitpick maybe but I don't really think this need as Fixes: tag.
That commit didn't actually *break* anything AFAIK.
It added WoL support for *some* SoCs that didn't have any in mainline
and didn't hurt the others.
Of course it turned out to be insufficient for the multiple FEC case
so this patch series is a welcome improvement.
> struct fec_devinfo {
> u32 quirks;
> - u8 stop_gpr_reg;
> - u8 stop_gpr_bit;
> };
This structure has become redundant now that it only contains a single
u32 quirks field.
So we *could* go back to storing the quirks bitmask directly in
.driver_data as was done before.
It's a slight wastage to keep the, now unnecessary, indirection,
though the size impact is small
and it's only used at probe() time not on a hot path.
But switching back could be seen as code churn too...
I don't have a strong opinion on this, so just noting it to see what
others think.
Martin
^ permalink raw reply
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