* Re: [PATCH V5 5/5] dt-bindings: clock: Convert i.MX6UL clock to json-schema
From: Rob Herring @ 2020-05-26 22:31 UTC (permalink / raw)
To: Anson Huang
Cc: linux-kernel, Linux-imx, shawnguo, robh+dt, sboyd,
linux-arm-kernel, devicetree, linux-clk, s.hauer, mturquette,
festevam, kernel
In-Reply-To: <1589328684-1397-6-git-send-email-Anson.Huang@nxp.com>
On Wed, 13 May 2020 08:11:24 +0800, Anson Huang wrote:
> Convert the i.MX6UL clock binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> Acked-by: Stephen Boyd <sboyd@kernel.org>
> ---
> Changes since V4:
> - add descriptions for interrupts and each item of it.
> ---
> .../devicetree/bindings/clock/imx6ul-clock.txt | 13 -----
> .../devicetree/bindings/clock/imx6ul-clock.yaml | 66 ++++++++++++++++++++++
> 2 files changed, 66 insertions(+), 13 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/imx6ul-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/imx6ul-clock.yaml
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH V5 4/5] dt-bindings: clock: Convert i.MX6SLL clock to json-schema
From: Rob Herring @ 2020-05-26 22:31 UTC (permalink / raw)
To: Anson Huang
Cc: linux-clk, linux-kernel, robh+dt, mturquette, festevam, shawnguo,
sboyd, kernel, linux-arm-kernel, devicetree, Linux-imx, s.hauer
In-Reply-To: <1589328684-1397-5-git-send-email-Anson.Huang@nxp.com>
On Wed, 13 May 2020 08:11:23 +0800, Anson Huang wrote:
> Convert the i.MX6SLL clock binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> Acked-by: Stephen Boyd <sboyd@kernel.org>
> ---
> Changes since V4:
> - add descriptions for interrupts and each item of it.
> ---
> .../devicetree/bindings/clock/imx6sll-clock.txt | 36 ------------
> .../devicetree/bindings/clock/imx6sll-clock.yaml | 66 ++++++++++++++++++++++
> 2 files changed, 66 insertions(+), 36 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/imx6sll-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/imx6sll-clock.yaml
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH V5 3/5] dt-bindings: clock: Convert i.MX6SL clock to json-schema
From: Rob Herring @ 2020-05-26 22:31 UTC (permalink / raw)
To: Anson Huang
Cc: mturquette, Linux-imx, linux-clk, shawnguo, festevam,
linux-kernel, devicetree, linux-arm-kernel, kernel, s.hauer,
sboyd, robh+dt
In-Reply-To: <1589328684-1397-4-git-send-email-Anson.Huang@nxp.com>
On Wed, 13 May 2020 08:11:22 +0800, Anson Huang wrote:
> Convert the i.MX6SL clock binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> Acked-by: Stephen Boyd <sboyd@kernel.org>
> ---
> Changes since V4:
> - add descriptions for interrupts and each item of it.
> ---
> .../devicetree/bindings/clock/imx6sl-clock.txt | 10 -----
> .../devicetree/bindings/clock/imx6sl-clock.yaml | 48 ++++++++++++++++++++++
> 2 files changed, 48 insertions(+), 10 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/imx6sl-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/imx6sl-clock.yaml
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH V5 2/5] dt-bindings: clock: Convert i.MX6SX clock to json-schema
From: Rob Herring @ 2020-05-26 22:30 UTC (permalink / raw)
To: Anson Huang
Cc: devicetree, festevam, sboyd, mturquette, robh+dt, linux-kernel,
s.hauer, kernel, linux-clk, linux-arm-kernel, shawnguo, Linux-imx
In-Reply-To: <1589328684-1397-3-git-send-email-Anson.Huang@nxp.com>
On Wed, 13 May 2020 08:11:21 +0800, Anson Huang wrote:
> Convert the i.MX6SX clock binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> Acked-by: Stephen Boyd <sboyd@kernel.org>
> ---
> Changes since V4:
> - add descriptions for interrupts and each item of it.
> ---
> .../devicetree/bindings/clock/imx6sx-clock.txt | 13 ----
> .../devicetree/bindings/clock/imx6sx-clock.yaml | 70 ++++++++++++++++++++++
> 2 files changed, 70 insertions(+), 13 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/imx6sx-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/imx6sx-clock.yaml
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH V5 1/5] dt-bindings: clock: Convert i.MX6Q clock to json-schema
From: Rob Herring @ 2020-05-26 22:30 UTC (permalink / raw)
To: Anson Huang
Cc: robh+dt, linux-arm-kernel, Linux-imx, mturquette, shawnguo,
kernel, devicetree, linux-clk, sboyd, linux-kernel, s.hauer,
festevam
In-Reply-To: <1589328684-1397-2-git-send-email-Anson.Huang@nxp.com>
On Wed, 13 May 2020 08:11:20 +0800, Anson Huang wrote:
> Convert the i.MX6Q clock binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> Acked-by: Stephen Boyd <sboyd@kernel.org>
> ---
> Changes since V4:
> - add descriptions for interrupts and each item of it.
> ---
> .../devicetree/bindings/clock/imx6q-clock.txt | 41 ------------
> .../devicetree/bindings/clock/imx6q-clock.yaml | 72 ++++++++++++++++++++++
> 2 files changed, 72 insertions(+), 41 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/imx6q-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/imx6q-clock.yaml
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH v6 3/5] dt-bindings: iio: magnetometer: ak8975: add gpio reset support
From: Rob Herring @ 2020-05-26 22:29 UTC (permalink / raw)
To: Jonathan Albrieux
Cc: Peter Meerwald-Stadler, Lars-Peter Clausen, Jonathan Cameron,
linux-iio, Andy Shevchenko, Linus Walleij, Jonathan Cameron,
Rob Herring, linux-kernel, Hartmut Knaack,
~postmarketos/upstreaming, devicetree
In-Reply-To: <20200525151117.32540-4-jonathan.albrieux@gmail.com>
On Mon, 25 May 2020 17:10:37 +0200, Jonathan Albrieux wrote:
> Add reset-gpio support.
>
> Without reset's deassertion during ak8975_power_on(), driver's probe fails
> on ak8975_who_i_am() while checking for device identity for AK09911 chip.
>
> AK09911 has an active low reset gpio to handle register's reset.
> AK09911 datasheet says that, if not used, reset pin should be connected
> to VID. This patch emulates this situation.
>
> Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com>
> ---
> .../bindings/iio/magnetometer/asahi-kasei,ak8975.yaml | 7 +++++++
> 1 file changed, 7 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v6 2/5] dt-bindings: iio: magnetometer: ak8975: convert format to yaml, add maintainer
From: Rob Herring @ 2020-05-26 22:28 UTC (permalink / raw)
To: Jonathan Albrieux
Cc: linux-kernel, ~postmarketos/upstreaming, Andy Shevchenko,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Hartmut Knaack, Jonathan Cameron, Lars-Peter Clausen,
Linus Walleij, open list:IIO SUBSYSTEM AND DRIVERS,
Peter Meerwald-Stadler, Jonathan Cameron
In-Reply-To: <20200525151117.32540-3-jonathan.albrieux@gmail.com>
On Mon, May 25, 2020 at 05:10:36PM +0200, Jonathan Albrieux wrote:
> Converts documentation from txt format to yaml.
I would have converted to yaml and do any re-formatting/wording, then
added 'interrupts', but this is fine.
> Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com>
> ---
> .../bindings/iio/magnetometer/ak8975.txt | 37 ---------
> .../iio/magnetometer/asahi-kasei,ak8975.yaml | 78 +++++++++++++++++++
> 2 files changed, 78 insertions(+), 37 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/iio/magnetometer/ak8975.txt
> create mode 100644 Documentation/devicetree/bindings/iio/magnetometer/asahi-kasei,ak8975.yaml
>
> diff --git a/Documentation/devicetree/bindings/iio/magnetometer/ak8975.txt b/Documentation/devicetree/bindings/iio/magnetometer/ak8975.txt
> deleted file mode 100644
> index 0576b9df0bf2..000000000000
> --- a/Documentation/devicetree/bindings/iio/magnetometer/ak8975.txt
> +++ /dev/null
> @@ -1,37 +0,0 @@
> -* AsahiKASEI AK8975 magnetometer sensor
> -
> -Required properties:
> -
> - - compatible : should be "asahi-kasei,ak8975".
> - - reg : the I2C address of the magnetometer.
> -
> -Optional properties:
> -
> - - gpios : AK8975 has a "Data ready" pin (DRDY) which informs that data
> - is ready to be read and is possible to listen on it. If used,
> - this should be active high. Prefer interrupt over this.
> -
> - - interrupts : interrupt for DRDY pin. Triggered on rising edge.
> -
> - - vdd-supply: an optional regulator that needs to be on to provide VDD.
> -
> - - mount-matrix: an optional 3x3 mounting rotation matrix.
> -
> -Example:
> -
> -ak8975@c {
> - compatible = "asahi-kasei,ak8975";
> - reg = <0x0c>;
> - interrupt-parent = <&gpio6>;
> - interrupts = <15 IRQ_TYPE_EDGE_RISING>;
> - vdd-supply = <&ldo_3v3_gnss>;
> - mount-matrix = "-0.984807753012208", /* x0 */
> - "0", /* y0 */
> - "-0.173648177666930", /* z0 */
> - "0", /* x1 */
> - "-1", /* y1 */
> - "0", /* z1 */
> - "-0.173648177666930", /* x2 */
> - "0", /* y2 */
> - "0.984807753012208"; /* z2 */
> -};
> diff --git a/Documentation/devicetree/bindings/iio/magnetometer/asahi-kasei,ak8975.yaml b/Documentation/devicetree/bindings/iio/magnetometer/asahi-kasei,ak8975.yaml
> new file mode 100644
> index 000000000000..a603659d5fa5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/magnetometer/asahi-kasei,ak8975.yaml
> @@ -0,0 +1,78 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/iio/magnetometer/asahi-kasei,ak8975.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: AsahiKASEI AK8975 magnetometer sensor
> +
> +maintainers:
> + - Jonathan Albrieux <jonathan.albrieux@gmail.com>
> +
> +properties:
> + compatible:
> + oneOf:
> + - const: asahi-kasei,ak8975
> + - const: asahi-kasei,ak8963
> + - const: asahi-kasei,ak09911
> + - const: asahi-kasei,ak09912
These 4 can be an enum.
> + - const: ak8975
> + deprecated: true
> + - const: ak8963
> + deprecated: true
> + - const: ak09911
> + deprecated: true
> + - const: ak09912
> + deprecated: true
And these 4 can be an enum+deprecated.
> +
> + reg:
> + maxItems: 1
> + description: the I2C address of the magnetometer.
Don't need a description.
> +
> + gpios:
> + description: |
> + AK8975 has a "Data ready" pin (DRDY) which informs that data
> + is ready to be read and is possible to listen on it. If used,
> + this should be active high. Prefer interrupt over this.
Need to define how many GPIOs (maxItems: 1).
> +
> + interrupts:
> + maxItems: 1
> + description: interrupt for DRDY pin. Triggered on rising edge.
> +
> + vdd-supply:
> + maxItems: 1
> + description: |
> + an optional regulator that needs to be on to provide VDD power to
> + the sensor.
> +
> + mount-matrix:
> + description: an optional 3x3 mounting rotation matrix.
> +
> +required:
> + - compatible
> + - reg
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/irq.h>
> + i2c {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + magnetometer@c {
> + compatible = "asahi-kasei,ak8975";
> + reg = <0x0c>;
> + interrupt-parent = <&gpio6>;
> + interrupts = <15 IRQ_TYPE_EDGE_RISING>;
> + vdd-supply = <&ldo_3v3_gnss>;
> + mount-matrix = "-0.984807753012208", /* x0 */
> + "0", /* y0 */
> + "-0.173648177666930", /* z0 */
> + "0", /* x1 */
> + "-1", /* y1 */
> + "0", /* z1 */
> + "-0.173648177666930", /* x2 */
> + "0", /* y2 */
> + "0.984807753012208"; /* z2 */
> + };
> + };
> --
> 2.17.1
>
^ permalink raw reply
* Re: [PATCH v6 1/5] dt-bindings: iio: magnetometer: ak8975: reword gpios, add interrupts, fix style
From: Rob Herring @ 2020-05-26 22:24 UTC (permalink / raw)
To: Jonathan Albrieux
Cc: linux-kernel, Rob Herring, ~postmarketos/upstreaming,
Jonathan Cameron, Lars-Peter Clausen, Andy Shevchenko, devicetree,
linux-iio, Linus Walleij, Jonathan Cameron, Hartmut Knaack,
Peter Meerwald-Stadler
In-Reply-To: <20200525151117.32540-2-jonathan.albrieux@gmail.com>
On Mon, 25 May 2020 17:10:35 +0200, Jonathan Albrieux wrote:
> Reword gpios documentation, add interrupt documentation and fix styles.
> Update example to use interrupts instead of gpios.
>
> Signed-off-by: Jonathan Albrieux <jonathan.albrieux@gmail.com>
> ---
> .../bindings/iio/magnetometer/ak8975.txt | 19 +++++++++++++------
> 1 file changed, 13 insertions(+), 6 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v6 3/3] dt-bindings: drm/bridge: ti-sn65dsi86: Document no-hpd
From: Rob Herring @ 2020-05-26 22:22 UTC (permalink / raw)
To: Douglas Anderson
Cc: linus.walleij, bgolaszewski, airlied, daniel, narmstrong, a.hajda,
Laurent.pinchart, spanda, bjorn.andersson, dri-devel, swboyd,
devicetree, jeffrey.l.hugo, jernej.skrabec, linux-arm-msm,
robdclark, jonas, linux-gpio, linux-kernel
In-Reply-To: <20200513145807.v6.3.I72892d485088e57378a4748c86bc0f6c2494d807@changeid>
On Wed, May 13, 2020 at 02:59:02PM -0700, Douglas Anderson wrote:
> The ti-sn65dsi86 MIPI DSI to eDP bridge chip has a dedicated hardware
> HPD (Hot Plug Detect) pin on it, but it's mostly useless for eDP
> because of excessive debouncing in hardware. Specifically there is no
> way to disable the debouncing and for eDP debouncing hurts you because
> HPD is just used for knowing when the panel is ready, not for
> detecting physical plug events.
>
> Currently the driver in Linux just assumes that nobody has HPD hooked
> up. It relies on folks setting the "no-hpd" property in the panel
> node to specify that HPD isn't hooked up and then the panel driver
> using this to add some worst case delays when turning on the panel.
>
> Apparently it's also useful to specify "no-hpd" in the bridge node so
> that the bridge driver can make sure it's doing the right thing
> without peeking into the panel [1]. This would be used if anyone ever
> found it useful to implement support for the HW HPD pin on the bridge.
> Let's add this property to the bindings.
>
> NOTES:
> - This is somewhat of a backward-incompatible change. All current
> known users of ti-sn65dsi86 didn't have "no-hpd" specified in the
> bridge node yet none of them had HPD hooked up. This worked because
> the current Linux driver just assumed that HPD was never hooked up.
> We could make it less incompatible by saying that for this bridge
> it's assumed HPD isn't hooked up _unless_ a property is defined, but
> "no-hpd" is much more standard and it's unlikely to matter unless
> someone quickly goes and implements HPD in the driver.
> - It is sensible to specify "no-hpd" at the bridge chip level and
> specify "hpd-gpios" at the panel level. That would mean HPD is
> hooked up to some other GPIO in the system, just not the hardware
> HPD pin on the bridge chip.
I would say 'no-hpd' belongs wherever HPD is broken. So it may still
make sense in the panel. (Otherwise, it needs to be removed from
panel-common.yaml and some panel bindings, right?)
> [1] https://lore.kernel.org/r/20200417180819.GE5861@pendragon.ideasonboard.com
>
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
In any case,
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v3 0/4] clk: Add Baikal-T1 SoC Clock Control Unit support
From: Serge Semin @ 2020-05-26 22:20 UTC (permalink / raw)
To: Thomas Bogendoerfer, Stephen Boyd, Michael Turquette
Cc: Serge Semin, Serge Semin, Alexey Malahov, Maxim Kaurkin,
Pavel Parkhomenko, Ramil Zaripov, Ekaterina Skachko, Vadim Vlasov,
Alexey Kolotnikov, Arnd Bergmann, Rob Herring, linux-clk,
linux-mips, devicetree, linux-kernel
Stephen, Michael, the merge window is upon us, please review/merge in/whatever
this patchset.
Clocks Control Unit is the core of Baikal-T1 SoC responsible for the chip
subsystems clocking and resetting. The CCU is connected with an external
fixed rate oscillator, which signal is transformed into clocks of various
frequencies and then propagated to either individual IP-blocks or to groups
of blocks (clock domains). The transformation is done by means of PLLs and
gateable/non-gateable, fixed/variable dividers embedded into the CCU. There
are five PLLs to create a clock for the MIPS P5600 cores, the embedded DDR
controller, SATA, Ethernet and PCIe domains. The last three PLLs CLKOUT are
then passed over CCU dividers to create signals required for the target clock
domains: individual AXI and APB bus clocks, SoC devices reference clocks.
The CCU divider registers may also provide a way to reset the target devices
state.
So this patchset introduces the Baikal-T1 clock and reset drivers of CCU
PLLs, AXI-bus clock dividers and system devices clock dividers.
This patchset is rebased and tested on the mainline Linux kernel 5.7-rc4:
0e698dfa2822 ("Linux 5.7-rc4")
tag: v5.7-rc4
Changelog v2:
- Rearrange the SoBs.
- Discard comments in the binding files headers.
- Add dual GPL/BSD license to the bindings.
- Add spaces around the ASCII-graphics in the bindings description.
- Discard redundant dt objects check against "/schemas/clock/clock.yaml#"
schema.
- Discard redundant descriptions of the "#clock-cells" and "#reset-cells"
properties in dt bindings schema.
- Discard "reg" property since the CCU dividers DT nodes are supposed be
children of the syscon-compatible system controller node.
- Remove "clock-output-names" property support.
- Replace "additionalProperties: false" with "unevaluatedProperties: false"
in the bindings.
- Lowercase the nodes name in the binding examples.
- Use "clock-controller" node name suffix in the binding examples.
- Remove unnecessary comments in the clocks and resets dt-binding header
files.
- Don't enable the CCU clock drivers by default for COMPILE_TEST config.
- Make sure the CCU drivers depend on OF kernel config only when built for
Baikal-T1-based platform.
- Fix spelling in the CCU PLL and Dividers kernel configs description.
- Replace lock delay and frequency calculation macros with inline functions.
- Use 64-bits arithmetics in the CCU PLL frequency calculation function.
- Use FIELD_{GET,PREP}() macro instead of handwritten field setters and
getters.
- Discard CLK_IGNORE_UNUSED flag setting. It's redundant since CLK_IS_CRITICAL
is enough for cases when it's appropriate.
- Comment out the CLK_IS_CRITICAL flag settings.
- Discard !pll and !div tests from ccu_pll_hw_unregister() and ccu_div_get_clk_id()
methods respectively.
- Discard alive probe messages.
- Convert the drivers to using syscon regmap instead of direct IO methods,
since now the PLLs DT node is supposed to be a sub-node of the Baikal-T1
System Controller node.
- Add DebugFS nodes in RO-mode by default.
Link: https://lore.kernel.org/linux-clk/20200506222300.30895-1-Sergey.Semin@baikalelectronics.ru/
Changelog v3:
- Get the reg property back to the DT bindings even though the driver is
using the parental syscon regmap.
- The DT schema will live separately from the system controller, but the
corresponding sub-node of the later DT schema will $ref this one.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Maxim Kaurkin <Maxim.Kaurkin@baikalelectronics.ru>
Cc: Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>
Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Cc: Ekaterina Skachko <Ekaterina.Skachko@baikalelectronics.ru>
Cc: Vadim Vlasov <V.Vlasov@baikalelectronics.ru>
Cc: Alexey Kolotnikov <Alexey.Kolotnikov@baikalelectronics.ru>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-clk@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Serge Semin (4):
dt-bindings: clk: Add Baikal-T1 CCU PLLs binding
dt-bindings: clk: Add Baikal-T1 CCU Dividers binding
clk: Add Baikal-T1 CCU PLLs driver
clk: Add Baikal-T1 CCU Dividers driver
.../bindings/clock/baikal,bt1-ccu-div.yaml | 188 ++++++
.../bindings/clock/baikal,bt1-ccu-pll.yaml | 131 ++++
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/baikal-t1/Kconfig | 42 ++
drivers/clk/baikal-t1/Makefile | 3 +
drivers/clk/baikal-t1/ccu-div.c | 602 ++++++++++++++++++
drivers/clk/baikal-t1/ccu-div.h | 110 ++++
drivers/clk/baikal-t1/ccu-pll.c | 558 ++++++++++++++++
drivers/clk/baikal-t1/ccu-pll.h | 64 ++
drivers/clk/baikal-t1/clk-ccu-div.c | 487 ++++++++++++++
drivers/clk/baikal-t1/clk-ccu-pll.c | 204 ++++++
include/dt-bindings/clock/bt1-ccu.h | 48 ++
include/dt-bindings/reset/bt1-ccu.h | 25 +
14 files changed, 2464 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml
create mode 100644 Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml
create mode 100644 drivers/clk/baikal-t1/Kconfig
create mode 100644 drivers/clk/baikal-t1/Makefile
create mode 100644 drivers/clk/baikal-t1/ccu-div.c
create mode 100644 drivers/clk/baikal-t1/ccu-div.h
create mode 100644 drivers/clk/baikal-t1/ccu-pll.c
create mode 100644 drivers/clk/baikal-t1/ccu-pll.h
create mode 100644 drivers/clk/baikal-t1/clk-ccu-div.c
create mode 100644 drivers/clk/baikal-t1/clk-ccu-pll.c
create mode 100644 include/dt-bindings/clock/bt1-ccu.h
create mode 100644 include/dt-bindings/reset/bt1-ccu.h
--
2.26.2
^ permalink raw reply
* [PATCH v3 3/4] clk: Add Baikal-T1 CCU PLLs driver
From: Serge Semin @ 2020-05-26 22:20 UTC (permalink / raw)
To: Thomas Bogendoerfer, Stephen Boyd, Michael Turquette
Cc: Serge Semin, Serge Semin, Alexey Malahov, Arnd Bergmann,
Rob Herring, linux-mips, devicetree, linux-kernel, linux-clk
In-Reply-To: <20200526222056.18072-1-Sergey.Semin@baikalelectronics.ru>
Baikal-T1 is supposed to be supplied with a high-frequency external
oscillator. But in order to create signals suitable for each IP-block
embedded into the SoC the oscillator output is primarily connected to
a set of CCU PLLs. There are five of them to create clocks for the MIPS
P5600 cores, an embedded DDR controller, SATA, Ethernet and PCIe domains.
The last three domains though named by the biggest system interfaces in
fact include nearly all of the rest SoC peripherals. Each of the PLLs is
based on True Circuits TSMC CLN28HPM IP-core with an interface wrapper
(so called safe PLL' clocks switcher) to simplify the PLL configuration
procedure.
This driver creates the of-based hardware clocks to use them then in
the corresponding subsystems. In order to simplify the driver code we
split the functionality up into the PLLs clocks operations and hardware
clocks declaration/registration procedures.
Even though the PLLs are based on the same IP-core, they may have some
differences. In particular, some CCU PLLs support the output clock change
without gating them (like CPU or PCIe PLLs), while the others don't, some
CCU PLLs are critical and aren't supposed to be gated. In order to cover
all of these cases the hardware clocks driver is designed with an
info-descriptor pattern. So there are special static descriptors declared
for each PLL, which is then used to create a hardware clock with proper
operations. Additionally debugfs-files are provided for each PLL' field
to make sure the implemented rate-PLLs-dividers calculation algorithm is
correct.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
Changelog v2:
- Rearrange the SoBs.
- Don't enable the CCU clock drivers by default for COMPILE_TEST config.
- Make sure the CCU drivers depend on OF kernel config only when built for
Baikal-T1-based platform.
- Fix spelling in the CCU PLL kernel config description.
- Replace lock delay and frequency calculation macro with inline functions.
- Use 64-bits arithmetics in the PLL output frequency calculation method.
- Use readl_poll_timeout_atomic() to poll the PLL lock state.
- Use FIELD_{GET,PREP}() macro instead of handwritten field setters and
getters.
- Discard CLK_IGNORE_UNUSED flag setting. It's redundant since CLK_IS_CRITICAL
is enough for cases when it's appropriate.
- Don't declare private copies of the Common Clock Flags.
- Comment out the CLK_IS_CRITICAL flag settings.
- Discard !pll test in ccu_pll_hw_unregister() method.
- Discard ccu_pll_get_clk_id() method. Use not-null check instead of FFs-
based invalid ID value.
- Discard alive probe message.
- Remove "clock-output-names" property support.
- Convert the driver to using syscon regmap instead of direct IO methods,
since now the PLLs DT node is supposed to be a sub-node of the Baikal-T1
System Controller node.
- Add DebugFS nodes in RO-mode by default.
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/baikal-t1/Kconfig | 30 ++
drivers/clk/baikal-t1/Makefile | 2 +
drivers/clk/baikal-t1/ccu-pll.c | 558 ++++++++++++++++++++++++++++
drivers/clk/baikal-t1/ccu-pll.h | 64 ++++
drivers/clk/baikal-t1/clk-ccu-pll.c | 204 ++++++++++
7 files changed, 860 insertions(+)
create mode 100644 drivers/clk/baikal-t1/Kconfig
create mode 100644 drivers/clk/baikal-t1/Makefile
create mode 100644 drivers/clk/baikal-t1/ccu-pll.c
create mode 100644 drivers/clk/baikal-t1/ccu-pll.h
create mode 100644 drivers/clk/baikal-t1/clk-ccu-pll.c
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index bcb257baed06..b32da34ebcf9 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -341,6 +341,7 @@ config COMMON_CLK_FIXED_MMIO
source "drivers/clk/actions/Kconfig"
source "drivers/clk/analogbits/Kconfig"
+source "drivers/clk/baikal-t1/Kconfig"
source "drivers/clk/bcm/Kconfig"
source "drivers/clk/hisilicon/Kconfig"
source "drivers/clk/imgtec/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index f4169cc2fd31..1496045d4e01 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -75,6 +75,7 @@ obj-y += analogbits/
obj-$(CONFIG_COMMON_CLK_AT91) += at91/
obj-$(CONFIG_ARCH_ARTPEC) += axis/
obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/
+obj-$(CONFIG_CLK_BAIKAL_T1) += baikal-t1/
obj-y += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
obj-$(CONFIG_ARCH_DAVINCI) += davinci/
diff --git a/drivers/clk/baikal-t1/Kconfig b/drivers/clk/baikal-t1/Kconfig
new file mode 100644
index 000000000000..00398ee916dc
--- /dev/null
+++ b/drivers/clk/baikal-t1/Kconfig
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config CLK_BAIKAL_T1
+ bool "Baikal-T1 Clocks Control Unit interface"
+ depends on (MIPS_BAIKAL_T1 && OF) || COMPILE_TEST
+ default MIPS_BAIKAL_T1
+ help
+ Clocks Control Unit is the core of Baikal-T1 SoC System Controller
+ responsible for the chip subsystems clocking and resetting. It
+ consists of multiple global clock domains, which can be reset by
+ means of the CCU control registers. These domains and devices placed
+ in them are fed with clocks generated by a hierarchy of PLLs,
+ configurable and fixed clock dividers. Enable this option to be able
+ to select Baikal-T1 CCU PLLs and Dividers drivers.
+
+if CLK_BAIKAL_T1
+
+config CLK_BT1_CCU_PLL
+ bool "Baikal-T1 CCU PLLs support"
+ select MFD_SYSCON
+ default MIPS_BAIKAL_T1
+ help
+ Enable this to support the PLLs embedded into the Baikal-T1 SoC
+ System Controller. These are five PLLs placed at the root of the
+ clocks hierarchy, right after an external reference oscillator
+ (normally of 25MHz). They are used to generate high frequency
+ signals, which are either directly wired to the consumers (like
+ CPUs, DDR, etc.) or passed over the clock dividers to be only
+ then used as an individual reference clock of a target device.
+
+endif
diff --git a/drivers/clk/baikal-t1/Makefile b/drivers/clk/baikal-t1/Makefile
new file mode 100644
index 000000000000..4a612bbacc37
--- /dev/null
+++ b/drivers/clk/baikal-t1/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_CLK_BT1_CCU_PLL) += ccu-pll.o clk-ccu-pll.o
diff --git a/drivers/clk/baikal-t1/ccu-pll.c b/drivers/clk/baikal-t1/ccu-pll.c
new file mode 100644
index 000000000000..758393122d2f
--- /dev/null
+++ b/drivers/clk/baikal-t1/ccu-pll.c
@@ -0,0 +1,558 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
+ *
+ * Authors:
+ * Serge Semin <Sergey.Semin@baikalelectronics.ru>
+ * Dmitry Dunaev <dmitry.dunaev@baikalelectronics.ru>
+ *
+ * Baikal-T1 CCU PLL interface driver
+ */
+
+#define pr_fmt(fmt) "bt1-ccu-pll: " fmt
+
+#include <linux/kernel.h>
+#include <linux/printk.h>
+#include <linux/limits.h>
+#include <linux/bits.h>
+#include <linux/bitfield.h>
+#include <linux/slab.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/spinlock.h>
+#include <linux/regmap.h>
+#include <linux/iopoll.h>
+#include <linux/time64.h>
+#include <linux/rational.h>
+#include <linux/debugfs.h>
+
+#include "ccu-pll.h"
+
+#define CCU_PLL_CTL 0x000
+#define CCU_PLL_CTL_EN BIT(0)
+#define CCU_PLL_CTL_RST BIT(1)
+#define CCU_PLL_CTL_CLKR_FLD 2
+#define CCU_PLL_CTL_CLKR_MASK GENMASK(7, CCU_PLL_CTL_CLKR_FLD)
+#define CCU_PLL_CTL_CLKF_FLD 8
+#define CCU_PLL_CTL_CLKF_MASK GENMASK(20, CCU_PLL_CTL_CLKF_FLD)
+#define CCU_PLL_CTL_CLKOD_FLD 21
+#define CCU_PLL_CTL_CLKOD_MASK GENMASK(24, CCU_PLL_CTL_CLKOD_FLD)
+#define CCU_PLL_CTL_BYPASS BIT(30)
+#define CCU_PLL_CTL_LOCK BIT(31)
+#define CCU_PLL_CTL1 0x004
+#define CCU_PLL_CTL1_BWADJ_FLD 3
+#define CCU_PLL_CTL1_BWADJ_MASK GENMASK(14, CCU_PLL_CTL1_BWADJ_FLD)
+
+#define CCU_PLL_LOCK_CHECK_RETRIES 50
+
+#define CCU_PLL_NR_MAX \
+ ((CCU_PLL_CTL_CLKR_MASK >> CCU_PLL_CTL_CLKR_FLD) + 1)
+#define CCU_PLL_NF_MAX \
+ ((CCU_PLL_CTL_CLKF_MASK >> (CCU_PLL_CTL_CLKF_FLD + 1)) + 1)
+#define CCU_PLL_OD_MAX \
+ ((CCU_PLL_CTL_CLKOD_MASK >> CCU_PLL_CTL_CLKOD_FLD) + 1)
+#define CCU_PLL_NB_MAX \
+ ((CCU_PLL_CTL1_BWADJ_MASK >> CCU_PLL_CTL1_BWADJ_FLD) + 1)
+#define CCU_PLL_FDIV_MIN 427000UL
+#define CCU_PLL_FDIV_MAX 3500000000UL
+#define CCU_PLL_FOUT_MIN 200000000UL
+#define CCU_PLL_FOUT_MAX 2500000000UL
+#define CCU_PLL_FVCO_MIN 700000000UL
+#define CCU_PLL_FVCO_MAX 3500000000UL
+#define CCU_PLL_CLKOD_FACTOR 2
+
+static inline unsigned long ccu_pll_lock_delay_us(unsigned long ref_clk,
+ unsigned long nr)
+{
+ u64 us = 500ULL * nr * USEC_PER_SEC;
+
+ do_div(us, ref_clk);
+
+ return us;
+}
+
+static inline unsigned long ccu_pll_calc_freq(unsigned long ref_clk,
+ unsigned long nr,
+ unsigned long nf,
+ unsigned long od)
+{
+ u64 tmp = ref_clk;
+
+ do_div(tmp, nr);
+ tmp *= nf;
+ do_div(tmp, od);
+
+ return tmp;
+}
+
+static int ccu_pll_reset(struct ccu_pll *pll, unsigned long ref_clk,
+ unsigned long nr)
+{
+ unsigned long ud, ut;
+ u32 val;
+
+ ud = ccu_pll_lock_delay_us(ref_clk, nr);
+ ut = ud * CCU_PLL_LOCK_CHECK_RETRIES;
+
+ regmap_update_bits(pll->sys_regs, pll->reg_ctl,
+ CCU_PLL_CTL_RST, CCU_PLL_CTL_RST);
+
+ return regmap_read_poll_timeout_atomic(pll->sys_regs, pll->reg_ctl, val,
+ val & CCU_PLL_CTL_LOCK, ud, ut);
+}
+
+static int ccu_pll_enable(struct clk_hw *hw)
+{
+ struct clk_hw *parent_hw = clk_hw_get_parent(hw);
+ struct ccu_pll *pll = to_ccu_pll(hw);
+ unsigned long flags;
+ u32 val = 0;
+ int ret;
+
+ if (!parent_hw) {
+ pr_err("Can't enable '%s' with no parent", clk_hw_get_name(hw));
+ return -EINVAL;
+ }
+
+ regmap_read(pll->sys_regs, pll->reg_ctl, &val);
+ if (val & CCU_PLL_CTL_EN)
+ return 0;
+
+ spin_lock_irqsave(&pll->lock, flags);
+ regmap_write(pll->sys_regs, pll->reg_ctl, val | CCU_PLL_CTL_EN);
+ ret = ccu_pll_reset(pll, clk_hw_get_rate(parent_hw),
+ FIELD_GET(CCU_PLL_CTL_CLKR_MASK, val) + 1);
+ spin_unlock_irqrestore(&pll->lock, flags);
+ if (ret)
+ pr_err("PLL '%s' reset timed out\n", clk_hw_get_name(hw));
+
+ return ret;
+}
+
+static void ccu_pll_disable(struct clk_hw *hw)
+{
+ struct ccu_pll *pll = to_ccu_pll(hw);
+ unsigned long flags;
+
+ spin_lock_irqsave(&pll->lock, flags);
+ regmap_update_bits(pll->sys_regs, pll->reg_ctl, CCU_PLL_CTL_EN, 0);
+ spin_unlock_irqrestore(&pll->lock, flags);
+}
+
+static int ccu_pll_is_enabled(struct clk_hw *hw)
+{
+ struct ccu_pll *pll = to_ccu_pll(hw);
+ u32 val = 0;
+
+ regmap_read(pll->sys_regs, pll->reg_ctl, &val);
+
+ return !!(val & CCU_PLL_CTL_EN);
+}
+
+static unsigned long ccu_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct ccu_pll *pll = to_ccu_pll(hw);
+ unsigned long nr, nf, od;
+ u32 val = 0;
+
+ regmap_read(pll->sys_regs, pll->reg_ctl, &val);
+ nr = FIELD_GET(CCU_PLL_CTL_CLKR_MASK, val) + 1;
+ nf = FIELD_GET(CCU_PLL_CTL_CLKF_MASK, val) + 1;
+ od = FIELD_GET(CCU_PLL_CTL_CLKOD_MASK, val) + 1;
+
+ return ccu_pll_calc_freq(parent_rate, nr, nf, od);
+}
+
+static void ccu_pll_calc_factors(unsigned long rate, unsigned long parent_rate,
+ unsigned long *nr, unsigned long *nf,
+ unsigned long *od)
+{
+ unsigned long err, freq, min_err = ULONG_MAX;
+ unsigned long num, denom, n1, d1, nri;
+ unsigned long nr_max, nf_max, od_max;
+
+ /*
+ * Make sure PLL is working with valid input signal (Fdiv). If
+ * you want to speed the function up just reduce CCU_PLL_NR_MAX.
+ * This will cause a worse approximation though.
+ */
+ nri = (parent_rate / CCU_PLL_FDIV_MAX) + 1;
+ nr_max = min(parent_rate / CCU_PLL_FDIV_MIN, CCU_PLL_NR_MAX);
+
+ /*
+ * Find a closest [nr;nf;od] vector taking into account the
+ * limitations like: 1) 700MHz <= Fvco <= 3.5GHz, 2) PLL Od is
+ * either 1 or even number within the acceptable range (alas 1s
+ * is also excluded by the next loop).
+ */
+ for (; nri <= nr_max; ++nri) {
+ /* Use Od factor to fulfill the limitation 2). */
+ num = CCU_PLL_CLKOD_FACTOR * rate;
+ denom = parent_rate / nri;
+
+ /*
+ * Make sure Fvco is within the acceptable range to fulfill
+ * the condition 1). Note due to the CCU_PLL_CLKOD_FACTOR value
+ * the actual upper limit is also divided by that factor.
+ * It's not big problem for us since practically there is no
+ * need in clocks with that high frequency.
+ */
+ nf_max = min(CCU_PLL_FVCO_MAX / denom, CCU_PLL_NF_MAX);
+ od_max = CCU_PLL_OD_MAX / CCU_PLL_CLKOD_FACTOR;
+
+ /*
+ * Bypass the out-of-bound values, which can't be properly
+ * handled by the rational fraction approximation algorithm.
+ */
+ if (num / denom >= nf_max) {
+ n1 = nf_max;
+ d1 = 1;
+ } else if (denom / num >= od_max) {
+ n1 = 1;
+ d1 = od_max;
+ } else {
+ rational_best_approximation(num, denom, nf_max, od_max,
+ &n1, &d1);
+ }
+
+ /* Select the best approximation of the target rate. */
+ freq = ccu_pll_calc_freq(parent_rate, nri, n1, d1);
+ err = abs((int64_t)freq - num);
+ if (err < min_err) {
+ min_err = err;
+ *nr = nri;
+ *nf = n1;
+ *od = CCU_PLL_CLKOD_FACTOR * d1;
+ }
+ }
+}
+
+static long ccu_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned long nr = 1, nf = 1, od = 1;
+
+ ccu_pll_calc_factors(rate, *parent_rate, &nr, &nf, &od);
+
+ return ccu_pll_calc_freq(*parent_rate, nr, nf, od);
+}
+
+/*
+ * This method is used for PLLs, which support the on-the-fly dividers
+ * adjustment. So there is no need in gating such clocks.
+ */
+static int ccu_pll_set_rate_reset(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct ccu_pll *pll = to_ccu_pll(hw);
+ unsigned long nr, nf, od;
+ unsigned long flags;
+ u32 mask, val;
+ int ret;
+
+ ccu_pll_calc_factors(rate, parent_rate, &nr, &nf, &od);
+
+ mask = CCU_PLL_CTL_CLKR_MASK | CCU_PLL_CTL_CLKF_MASK |
+ CCU_PLL_CTL_CLKOD_MASK;
+ val = FIELD_PREP(CCU_PLL_CTL_CLKR_MASK, nr - 1) |
+ FIELD_PREP(CCU_PLL_CTL_CLKF_MASK, nf - 1) |
+ FIELD_PREP(CCU_PLL_CTL_CLKOD_MASK, od - 1);
+
+ spin_lock_irqsave(&pll->lock, flags);
+ regmap_update_bits(pll->sys_regs, pll->reg_ctl, mask, val);
+ ret = ccu_pll_reset(pll, parent_rate, nr);
+ spin_unlock_irqrestore(&pll->lock, flags);
+ if (ret)
+ pr_err("PLL '%s' reset timed out\n", clk_hw_get_name(hw));
+
+ return ret;
+}
+
+/*
+ * This method is used for PLLs, which don't support the on-the-fly dividers
+ * adjustment. So the corresponding clocks are supposed to be gated first.
+ */
+static int ccu_pll_set_rate_norst(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct ccu_pll *pll = to_ccu_pll(hw);
+ unsigned long nr, nf, od;
+ unsigned long flags;
+ u32 mask, val;
+
+ ccu_pll_calc_factors(rate, parent_rate, &nr, &nf, &od);
+
+ /*
+ * Disable PLL if it was enabled by default or left enabled by the
+ * system bootloader.
+ */
+ mask = CCU_PLL_CTL_CLKR_MASK | CCU_PLL_CTL_CLKF_MASK |
+ CCU_PLL_CTL_CLKOD_MASK | CCU_PLL_CTL_EN;
+ val = FIELD_PREP(CCU_PLL_CTL_CLKR_MASK, nr - 1) |
+ FIELD_PREP(CCU_PLL_CTL_CLKF_MASK, nf - 1) |
+ FIELD_PREP(CCU_PLL_CTL_CLKOD_MASK, od - 1);
+
+ spin_lock_irqsave(&pll->lock, flags);
+ regmap_update_bits(pll->sys_regs, pll->reg_ctl, mask, val);
+ spin_unlock_irqrestore(&pll->lock, flags);
+
+ return 0;
+}
+
+#ifdef CONFIG_DEBUG_FS
+
+struct ccu_pll_dbgfs_bit {
+ struct ccu_pll *pll;
+ const char *name;
+ unsigned int reg;
+ u32 mask;
+};
+
+struct ccu_pll_dbgfs_fld {
+ struct ccu_pll *pll;
+ const char *name;
+ unsigned int reg;
+ unsigned int lsb;
+ u32 mask;
+ u32 min;
+ u32 max;
+};
+
+#define CCU_PLL_DBGFS_BIT_ATTR(_name, _reg, _mask) \
+ { \
+ .name = _name, \
+ .reg = _reg, \
+ .mask = _mask \
+ }
+
+#define CCU_PLL_DBGFS_FLD_ATTR(_name, _reg, _lsb, _mask, _min, _max) \
+ { \
+ .name = _name, \
+ .reg = _reg, \
+ .lsb = _lsb, \
+ .mask = _mask, \
+ .min = _min, \
+ .max = _max \
+ }
+
+static const struct ccu_pll_dbgfs_bit ccu_pll_bits[] = {
+ CCU_PLL_DBGFS_BIT_ATTR("pll_en", CCU_PLL_CTL, CCU_PLL_CTL_EN),
+ CCU_PLL_DBGFS_BIT_ATTR("pll_rst", CCU_PLL_CTL, CCU_PLL_CTL_RST),
+ CCU_PLL_DBGFS_BIT_ATTR("pll_bypass", CCU_PLL_CTL, CCU_PLL_CTL_BYPASS),
+ CCU_PLL_DBGFS_BIT_ATTR("pll_lock", CCU_PLL_CTL, CCU_PLL_CTL_LOCK)
+};
+
+#define CCU_PLL_DBGFS_BIT_NUM ARRAY_SIZE(ccu_pll_bits)
+
+static const struct ccu_pll_dbgfs_fld ccu_pll_flds[] = {
+ CCU_PLL_DBGFS_FLD_ATTR("pll_nr", CCU_PLL_CTL, CCU_PLL_CTL_CLKR_FLD,
+ CCU_PLL_CTL_CLKR_MASK, 1, CCU_PLL_NR_MAX),
+ CCU_PLL_DBGFS_FLD_ATTR("pll_nf", CCU_PLL_CTL, CCU_PLL_CTL_CLKF_FLD,
+ CCU_PLL_CTL_CLKF_MASK, 1, CCU_PLL_NF_MAX),
+ CCU_PLL_DBGFS_FLD_ATTR("pll_od", CCU_PLL_CTL, CCU_PLL_CTL_CLKOD_FLD,
+ CCU_PLL_CTL_CLKOD_MASK, 1, CCU_PLL_OD_MAX),
+ CCU_PLL_DBGFS_FLD_ATTR("pll_nb", CCU_PLL_CTL1, CCU_PLL_CTL1_BWADJ_FLD,
+ CCU_PLL_CTL1_BWADJ_MASK, 1, CCU_PLL_NB_MAX)
+};
+
+#define CCU_PLL_DBGFS_FLD_NUM ARRAY_SIZE(ccu_pll_flds)
+
+/*
+ * It can be dangerous to change the PLL settings behind clock framework back,
+ * therefore we don't provide any kernel config based compile time option for
+ * this feature to enable.
+ */
+#undef CCU_PLL_ALLOW_WRITE_DEBUGFS
+#ifdef CCU_PLL_ALLOW_WRITE_DEBUGFS
+
+static int ccu_pll_dbgfs_bit_set(void *priv, u64 val)
+{
+ const struct ccu_pll_dbgfs_bit *bit = priv;
+ struct ccu_pll *pll = bit->pll;
+ unsigned long flags;
+
+ spin_lock_irqsave(&pll->lock, flags);
+ regmap_update_bits(pll->sys_regs, pll->reg_ctl + bit->reg,
+ bit->mask, val ? bit->mask : 0);
+ spin_unlock_irqrestore(&pll->lock, flags);
+
+ return 0;
+}
+
+static int ccu_pll_dbgfs_fld_set(void *priv, u64 val)
+{
+ struct ccu_pll_dbgfs_fld *fld = priv;
+ struct ccu_pll *pll = fld->pll;
+ unsigned long flags;
+ u32 data;
+
+ val = clamp_t(u64, val, fld->min, fld->max);
+ data = ((val - 1) << fld->lsb) & fld->mask;
+
+ spin_lock_irqsave(&pll->lock, flags);
+ regmap_update_bits(pll->sys_regs, pll->reg_ctl + fld->reg, fld->mask,
+ data);
+ spin_unlock_irqrestore(&pll->lock, flags);
+
+ return 0;
+}
+
+#define ccu_pll_dbgfs_mode 0644
+
+#else /* !CCU_PLL_ALLOW_WRITE_DEBUGFS */
+
+#define ccu_pll_dbgfs_bit_set NULL
+#define ccu_pll_dbgfs_fld_set NULL
+#define ccu_pll_dbgfs_mode 0444
+
+#endif /* !CCU_PLL_ALLOW_WRITE_DEBUGFS */
+
+static int ccu_pll_dbgfs_bit_get(void *priv, u64 *val)
+{
+ struct ccu_pll_dbgfs_bit *bit = priv;
+ struct ccu_pll *pll = bit->pll;
+ u32 data = 0;
+
+ regmap_read(pll->sys_regs, pll->reg_ctl + bit->reg, &data);
+ *val = !!(data & bit->mask);
+
+ return 0;
+}
+DEFINE_DEBUGFS_ATTRIBUTE(ccu_pll_dbgfs_bit_fops,
+ ccu_pll_dbgfs_bit_get, ccu_pll_dbgfs_bit_set, "%llu\n");
+
+static int ccu_pll_dbgfs_fld_get(void *priv, u64 *val)
+{
+ struct ccu_pll_dbgfs_fld *fld = priv;
+ struct ccu_pll *pll = fld->pll;
+ u32 data = 0;
+
+ regmap_read(pll->sys_regs, pll->reg_ctl + fld->reg, &data);
+ *val = ((data & fld->mask) >> fld->lsb) + 1;
+
+ return 0;
+}
+DEFINE_DEBUGFS_ATTRIBUTE(ccu_pll_dbgfs_fld_fops,
+ ccu_pll_dbgfs_fld_get, ccu_pll_dbgfs_fld_set, "%llu\n");
+
+static void ccu_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
+{
+ struct ccu_pll *pll = to_ccu_pll(hw);
+ struct ccu_pll_dbgfs_bit *bits;
+ struct ccu_pll_dbgfs_fld *flds;
+ int idx;
+
+ bits = kcalloc(CCU_PLL_DBGFS_BIT_NUM, sizeof(*bits), GFP_KERNEL);
+ if (!bits)
+ return;
+
+ for (idx = 0; idx < CCU_PLL_DBGFS_BIT_NUM; ++idx) {
+ bits[idx] = ccu_pll_bits[idx];
+ bits[idx].pll = pll;
+
+ debugfs_create_file_unsafe(bits[idx].name, ccu_pll_dbgfs_mode,
+ dentry, &bits[idx],
+ &ccu_pll_dbgfs_bit_fops);
+ }
+
+ flds = kcalloc(CCU_PLL_DBGFS_FLD_NUM, sizeof(*flds), GFP_KERNEL);
+ if (!flds)
+ return;
+
+ for (idx = 0; idx < CCU_PLL_DBGFS_FLD_NUM; ++idx) {
+ flds[idx] = ccu_pll_flds[idx];
+ flds[idx].pll = pll;
+
+ debugfs_create_file_unsafe(flds[idx].name, ccu_pll_dbgfs_mode,
+ dentry, &flds[idx],
+ &ccu_pll_dbgfs_fld_fops);
+ }
+}
+
+#else /* !CONFIG_DEBUG_FS */
+
+#define ccu_pll_debug_init NULL
+
+#endif /* !CONFIG_DEBUG_FS */
+
+static const struct clk_ops ccu_pll_gate_to_set_ops = {
+ .enable = ccu_pll_enable,
+ .disable = ccu_pll_disable,
+ .is_enabled = ccu_pll_is_enabled,
+ .recalc_rate = ccu_pll_recalc_rate,
+ .round_rate = ccu_pll_round_rate,
+ .set_rate = ccu_pll_set_rate_norst,
+ .debug_init = ccu_pll_debug_init
+};
+
+static const struct clk_ops ccu_pll_straight_set_ops = {
+ .enable = ccu_pll_enable,
+ .disable = ccu_pll_disable,
+ .is_enabled = ccu_pll_is_enabled,
+ .recalc_rate = ccu_pll_recalc_rate,
+ .round_rate = ccu_pll_round_rate,
+ .set_rate = ccu_pll_set_rate_reset,
+ .debug_init = ccu_pll_debug_init
+};
+
+struct ccu_pll *ccu_pll_hw_register(const struct ccu_pll_init_data *pll_init)
+{
+ struct clk_parent_data parent_data = {0};
+ struct clk_init_data hw_init = {0};
+ struct ccu_pll *pll;
+ int ret;
+
+ if (!pll_init)
+ return ERR_PTR(-EINVAL);
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ /*
+ * Note since Baikal-T1 System Controller registers are MMIO-backed
+ * we won't check the regmap IO operations return status, because it
+ * must be zero anyway.
+ */
+ pll->hw.init = &hw_init;
+ pll->reg_ctl = pll_init->base + CCU_PLL_CTL;
+ pll->reg_ctl1 = pll_init->base + CCU_PLL_CTL1;
+ pll->sys_regs = pll_init->sys_regs;
+ pll->id = pll_init->id;
+ spin_lock_init(&pll->lock);
+
+ hw_init.name = pll_init->name;
+ hw_init.flags = pll_init->flags;
+
+ if (hw_init.flags & CLK_SET_RATE_GATE)
+ hw_init.ops = &ccu_pll_gate_to_set_ops;
+ else
+ hw_init.ops = &ccu_pll_straight_set_ops;
+
+ if (!pll_init->parent_name) {
+ ret = -EINVAL;
+ goto err_free_pll;
+ }
+ parent_data.fw_name = pll_init->parent_name;
+ hw_init.parent_data = &parent_data;
+ hw_init.num_parents = 1;
+
+ ret = of_clk_hw_register(pll_init->np, &pll->hw);
+ if (ret)
+ goto err_free_pll;
+
+ return pll;
+
+err_free_pll:
+ kfree(pll);
+
+ return ERR_PTR(ret);
+}
+
+void ccu_pll_hw_unregister(struct ccu_pll *pll)
+{
+ clk_hw_unregister(&pll->hw);
+
+ kfree(pll);
+}
diff --git a/drivers/clk/baikal-t1/ccu-pll.h b/drivers/clk/baikal-t1/ccu-pll.h
new file mode 100644
index 000000000000..76cd9132a219
--- /dev/null
+++ b/drivers/clk/baikal-t1/ccu-pll.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
+ *
+ * Baikal-T1 CCU PLL interface driver
+ */
+#ifndef __CLK_BT1_CCU_PLL_H__
+#define __CLK_BT1_CCU_PLL_H__
+
+#include <linux/clk-provider.h>
+#include <linux/spinlock.h>
+#include <linux/regmap.h>
+#include <linux/bits.h>
+#include <linux/of.h>
+
+/*
+ * struct ccu_pll_init_data - CCU PLL initialization data
+ * @id: Clock private identifier.
+ * @name: Clocks name.
+ * @parent_name: Clocks parent name in a fw node.
+ * @base: PLL registers base address with respect to the sys_regs base.
+ * @sys_regs: Baikal-T1 System Controller registers map.
+ * @np: Pointer to the node describing the CCU PLLs.
+ * @flags: PLL clock flags.
+ */
+struct ccu_pll_init_data {
+ unsigned int id;
+ const char *name;
+ const char *parent_name;
+ unsigned int base;
+ struct regmap *sys_regs;
+ struct device_node *np;
+ unsigned long flags;
+};
+
+/*
+ * struct ccu_pll - CCU PLL descriptor
+ * @hw: clk_hw of the PLL.
+ * @id: Clock private identifier.
+ * @reg_ctl: PLL control register base.
+ * @reg_ctl1: PLL control1 register base.
+ * @sys_regs: Baikal-T1 System Controller registers map.
+ * @lock: PLL state change spin-lock.
+ */
+struct ccu_pll {
+ struct clk_hw hw;
+ unsigned int id;
+ unsigned int reg_ctl;
+ unsigned int reg_ctl1;
+ struct regmap *sys_regs;
+ spinlock_t lock;
+};
+#define to_ccu_pll(_hw) container_of(_hw, struct ccu_pll, hw)
+
+static inline struct clk_hw *ccu_pll_get_clk_hw(struct ccu_pll *pll)
+{
+ return pll ? &pll->hw : NULL;
+}
+
+struct ccu_pll *ccu_pll_hw_register(const struct ccu_pll_init_data *init);
+
+void ccu_pll_hw_unregister(struct ccu_pll *pll);
+
+#endif /* __CLK_BT1_CCU_PLL_H__ */
diff --git a/drivers/clk/baikal-t1/clk-ccu-pll.c b/drivers/clk/baikal-t1/clk-ccu-pll.c
new file mode 100644
index 000000000000..1eec8c0b8f50
--- /dev/null
+++ b/drivers/clk/baikal-t1/clk-ccu-pll.c
@@ -0,0 +1,204 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
+ *
+ * Authors:
+ * Serge Semin <Sergey.Semin@baikalelectronics.ru>
+ * Dmitry Dunaev <dmitry.dunaev@baikalelectronics.ru>
+ *
+ * Baikal-T1 CCU PLL clocks driver
+ */
+
+#define pr_fmt(fmt) "bt1-ccu-pll: " fmt
+
+#include <linux/kernel.h>
+#include <linux/printk.h>
+#include <linux/slab.h>
+#include <linux/clk-provider.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/ioport.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/bt1-ccu.h>
+
+#include "ccu-pll.h"
+
+#define CCU_CPU_PLL_BASE 0x000
+#define CCU_SATA_PLL_BASE 0x008
+#define CCU_DDR_PLL_BASE 0x010
+#define CCU_PCIE_PLL_BASE 0x018
+#define CCU_ETH_PLL_BASE 0x020
+
+#define CCU_PLL_INFO(_id, _name, _pname, _base, _flags) \
+ { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _pname, \
+ .base = _base, \
+ .flags = _flags \
+ }
+
+#define CCU_PLL_NUM ARRAY_SIZE(pll_info)
+
+struct ccu_pll_info {
+ unsigned int id;
+ const char *name;
+ const char *parent_name;
+ unsigned int base;
+ unsigned long flags;
+};
+
+/*
+ * Mark as critical all PLLs except Ethernet one. CPU and DDR PLLs are sources
+ * of CPU cores and DDR controller reference clocks, due to which they
+ * obviously shouldn't be ever gated. SATA and PCIe PLLs are the parents of
+ * APB-bus and DDR controller AXI-bus clocks. If they are gated the system will
+ * be unusable.
+ */
+static const struct ccu_pll_info pll_info[] = {
+ CCU_PLL_INFO(CCU_CPU_PLL, "cpu_pll", "ref_clk", CCU_CPU_PLL_BASE,
+ CLK_IS_CRITICAL),
+ CCU_PLL_INFO(CCU_SATA_PLL, "sata_pll", "ref_clk", CCU_SATA_PLL_BASE,
+ CLK_IS_CRITICAL | CLK_SET_RATE_GATE),
+ CCU_PLL_INFO(CCU_DDR_PLL, "ddr_pll", "ref_clk", CCU_DDR_PLL_BASE,
+ CLK_IS_CRITICAL | CLK_SET_RATE_GATE),
+ CCU_PLL_INFO(CCU_PCIE_PLL, "pcie_pll", "ref_clk", CCU_PCIE_PLL_BASE,
+ CLK_IS_CRITICAL),
+ CCU_PLL_INFO(CCU_ETH_PLL, "eth_pll", "ref_clk", CCU_ETH_PLL_BASE,
+ CLK_SET_RATE_GATE)
+};
+
+struct ccu_pll_data {
+ struct device_node *np;
+ struct regmap *sys_regs;
+ struct ccu_pll *plls[CCU_PLL_NUM];
+};
+
+static struct ccu_pll *ccu_pll_find_desc(struct ccu_pll_data *data,
+ unsigned int clk_id)
+{
+ struct ccu_pll *pll;
+ int idx;
+
+ for (idx = 0; idx < CCU_PLL_NUM; ++idx) {
+ pll = data->plls[idx];
+ if (pll && pll->id == clk_id)
+ return pll;
+ }
+
+ return ERR_PTR(-EINVAL);
+}
+
+static struct ccu_pll_data *ccu_pll_create_data(struct device_node *np)
+{
+ struct ccu_pll_data *data;
+
+ data = kzalloc(sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return ERR_PTR(-ENOMEM);
+
+ data->np = np;
+
+ return data;
+}
+
+static void ccu_pll_free_data(struct ccu_pll_data *data)
+{
+ kfree(data);
+}
+
+static int ccu_pll_find_sys_regs(struct ccu_pll_data *data)
+{
+ data->sys_regs = syscon_node_to_regmap(data->np->parent);
+ if (IS_ERR(data->sys_regs)) {
+ pr_err("Failed to find syscon regs for '%s'\n",
+ of_node_full_name(data->np));
+ return PTR_ERR(data->sys_regs);
+ }
+
+ return 0;
+}
+
+static struct clk_hw *ccu_pll_of_clk_hw_get(struct of_phandle_args *clkspec,
+ void *priv)
+{
+ struct ccu_pll_data *data = priv;
+ struct ccu_pll *pll;
+ unsigned int clk_id;
+
+ clk_id = clkspec->args[0];
+ pll = ccu_pll_find_desc(data, clk_id);
+ if (IS_ERR(pll)) {
+ pr_info("Invalid PLL clock ID %d specified\n", clk_id);
+ return ERR_CAST(pll);
+ }
+
+ return ccu_pll_get_clk_hw(pll);
+}
+
+static int ccu_pll_clk_register(struct ccu_pll_data *data)
+{
+ int idx, ret;
+
+ for (idx = 0; idx < CCU_PLL_NUM; ++idx) {
+ const struct ccu_pll_info *info = &pll_info[idx];
+ struct ccu_pll_init_data init = {0};
+
+ init.id = info->id;
+ init.name = info->name;
+ init.parent_name = info->parent_name;
+ init.base = info->base;
+ init.sys_regs = data->sys_regs;
+ init.np = data->np;
+ init.flags = info->flags;
+
+ data->plls[idx] = ccu_pll_hw_register(&init);
+ if (IS_ERR(data->plls[idx])) {
+ ret = PTR_ERR(data->plls[idx]);
+ pr_err("Couldn't register PLL hw '%s'\n",
+ init.name);
+ goto err_hw_unregister;
+ }
+ }
+
+ ret = of_clk_add_hw_provider(data->np, ccu_pll_of_clk_hw_get, data);
+ if (ret) {
+ pr_err("Couldn't register PLL provider of '%s'\n",
+ of_node_full_name(data->np));
+ goto err_hw_unregister;
+ }
+
+ return 0;
+
+err_hw_unregister:
+ for (--idx; idx >= 0; --idx)
+ ccu_pll_hw_unregister(data->plls[idx]);
+
+ return ret;
+}
+
+static __init void ccu_pll_init(struct device_node *np)
+{
+ struct ccu_pll_data *data;
+ int ret;
+
+ data = ccu_pll_create_data(np);
+ if (IS_ERR(data))
+ return;
+
+ ret = ccu_pll_find_sys_regs(data);
+ if (ret)
+ goto err_free_data;
+
+ ret = ccu_pll_clk_register(data);
+ if (ret)
+ goto err_free_data;
+
+ return;
+
+err_free_data:
+ ccu_pll_free_data(data);
+}
+CLK_OF_DECLARE(ccu_pll, "baikal,bt1-ccu-pll", ccu_pll_init);
--
2.26.2
^ permalink raw reply related
* [PATCH v3 4/4] clk: Add Baikal-T1 CCU Dividers driver
From: Serge Semin @ 2020-05-26 22:20 UTC (permalink / raw)
To: Thomas Bogendoerfer, Stephen Boyd, Michael Turquette
Cc: Serge Semin, Serge Semin, Alexey Malahov, Arnd Bergmann,
Rob Herring, linux-mips, devicetree, linux-kernel, linux-clk
In-Reply-To: <20200526222056.18072-1-Sergey.Semin@baikalelectronics.ru>
Nearly each Baikal-T1 IP-core is supposed to have a clock source
of particular frequency. But since there are greater than five
IP-blocks embedded into the SoC, the CCU PLLs can't fulfill all the
needs. Baikal-T1 CCU provides a set of fixed and configurable clock
dividers in order to generate a necessary signal for each chip
sub-block.
This driver creates the of-based hardware clocks for each divider
available in Baikal-T1 CCU. The same way as for PLLs we split the
functionality up into the clocks operations (gate, ungate, set rate,
etc) and hardware clocks declaration/registration procedures.
In accordance with the CCU documentation all its dividers are distributed
into two CCU sub-blocks: AXI-bus and system devices reference clocks.
The former sub-block is used to supply the clocks for AXI-bus interfaces
(AXI clock domains) and the later one provides the SoC IP-cores reference
clocks. Each sub-block is represented by a dedicated DT node, so they
have different compatible strings to distinguish one from another.
For some reason CCU provides the dividers of different types. Some
dividers can be gateable some can't, some are fixed while the others
are variable, some have special divider' limitations, some've got a
non-standard register layout and so on. In order to cover all of these
cases the hardware clocks driver is designed with an info-descriptor
pattern. So there are special static descriptors declared for the
dividers of each type with additional flags describing the block
peculiarity. These descriptors are then used to create hardware clocks
with proper operations.
Some CCU dividers provide a way to reset a domain they generate
a clock for. So the CCU AXI-bus and CCU system devices clock
drivers also perform the reset controller registration.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
Changelog v2:
- Rearrange the SoBs.
- Alter the commit message, since CCU isn't considered as MFD anymore.
- Enable the CCU Divider clock driver by default only if MIPS_BAIKAL_T1
config.
- Fix spelling in the CCU Dividers kernel config description.
- Replace lock delay and frequency calculation macros with inline functions.
- Replace the data field setter and getter macro with handwritten inliners.
Alas FIELD_{GET,PREP} can't be used here due to non-constant mask.
- Discard CLK_IGNORE_UNUSED flag setting. It's redundant since CLK_IS_CRITICAL
is enough for cases when it's appropriate.
- Don't declare private copies of the Common Clock flags. Driver specific flags
I renamed to "features".
- Comment out the CLK_IS_CRITICAL flag settings.
- Discard !div test in ccu_div_hw_unregister() method.
- Discard ccu_div_get_clk_id() method. Use not-null check instead of FFs-based
invalid ID value.
- Discard alive probe message.
- Remove "clock-output-names" property support.
- Convert the driver to using syscon regmap instead of direct IO methods,
since now the PLLs DT node is supposed to be a sub-node of the Baikal-T1
System Controller node.
- Add DebugFS nodes in RO-mode by default.
---
drivers/clk/baikal-t1/Kconfig | 12 +
drivers/clk/baikal-t1/Makefile | 1 +
drivers/clk/baikal-t1/ccu-div.c | 602 ++++++++++++++++++++++++++++
drivers/clk/baikal-t1/ccu-div.h | 110 +++++
drivers/clk/baikal-t1/clk-ccu-div.c | 487 ++++++++++++++++++++++
5 files changed, 1212 insertions(+)
create mode 100644 drivers/clk/baikal-t1/ccu-div.c
create mode 100644 drivers/clk/baikal-t1/ccu-div.h
create mode 100644 drivers/clk/baikal-t1/clk-ccu-div.c
diff --git a/drivers/clk/baikal-t1/Kconfig b/drivers/clk/baikal-t1/Kconfig
index 00398ee916dc..03102f1094bc 100644
--- a/drivers/clk/baikal-t1/Kconfig
+++ b/drivers/clk/baikal-t1/Kconfig
@@ -27,4 +27,16 @@ config CLK_BT1_CCU_PLL
CPUs, DDR, etc.) or passed over the clock dividers to be only
then used as an individual reference clock of a target device.
+config CLK_BT1_CCU_DIV
+ bool "Baikal-T1 CCU Dividers support"
+ select RESET_CONTROLLER
+ select MFD_SYSCON
+ default MIPS_BAIKAL_T1
+ help
+ Enable this to support the CCU dividers used to distribute clocks
+ between AXI-bus and system devices coming from CCU PLLs of Baikal-T1
+ SoC. CCU dividers can be either configurable or with fixed divider,
+ either gateable or ungateable. Some of the CCU dividers can be as well
+ used to reset the domains they're supplying clock to.
+
endif
diff --git a/drivers/clk/baikal-t1/Makefile b/drivers/clk/baikal-t1/Makefile
index 4a612bbacc37..b3b9590b95ed 100644
--- a/drivers/clk/baikal-t1/Makefile
+++ b/drivers/clk/baikal-t1/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_CLK_BT1_CCU_PLL) += ccu-pll.o clk-ccu-pll.o
+obj-$(CONFIG_CLK_BT1_CCU_DIV) += ccu-div.o clk-ccu-div.o
diff --git a/drivers/clk/baikal-t1/ccu-div.c b/drivers/clk/baikal-t1/ccu-div.c
new file mode 100644
index 000000000000..26aae8eec5ec
--- /dev/null
+++ b/drivers/clk/baikal-t1/ccu-div.c
@@ -0,0 +1,602 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
+ *
+ * Authors:
+ * Serge Semin <Sergey.Semin@baikalelectronics.ru>
+ * Dmitry Dunaev <dmitry.dunaev@baikalelectronics.ru>
+ *
+ * Baikal-T1 CCU Dividers interface driver
+ */
+
+#define pr_fmt(fmt) "bt1-ccu-div: " fmt
+
+#include <linux/kernel.h>
+#include <linux/printk.h>
+#include <linux/bits.h>
+#include <linux/bitfield.h>
+#include <linux/slab.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/spinlock.h>
+#include <linux/regmap.h>
+#include <linux/delay.h>
+#include <linux/time64.h>
+#include <linux/debugfs.h>
+
+#include "ccu-div.h"
+
+#define CCU_DIV_CTL 0x00
+#define CCU_DIV_CTL_EN BIT(0)
+#define CCU_DIV_CTL_RST BIT(1)
+#define CCU_DIV_CTL_SET_CLKDIV BIT(2)
+#define CCU_DIV_CTL_CLKDIV_FLD 4
+#define CCU_DIV_CTL_CLKDIV_MASK(_width) \
+ GENMASK((_width) + CCU_DIV_CTL_CLKDIV_FLD - 1, CCU_DIV_CTL_CLKDIV_FLD)
+#define CCU_DIV_CTL_LOCK_SHIFTED BIT(27)
+#define CCU_DIV_CTL_LOCK_NORMAL BIT(31)
+
+#define CCU_DIV_RST_DELAY_US 1
+#define CCU_DIV_LOCK_CHECK_RETRIES 50
+
+#define CCU_DIV_CLKDIV_MIN 0
+#define CCU_DIV_CLKDIV_MAX(_mask) \
+ ((_mask) >> CCU_DIV_CTL_CLKDIV_FLD)
+
+/*
+ * Use the next two methods until there are generic field setter and
+ * getter available with non-constant mask support.
+ */
+static inline u32 ccu_div_get(u32 mask, u32 val)
+{
+ return (val & mask) >> CCU_DIV_CTL_CLKDIV_FLD;
+}
+
+static inline u32 ccu_div_prep(u32 mask, u32 val)
+{
+ return (val << CCU_DIV_CTL_CLKDIV_FLD) & mask;
+}
+
+static inline unsigned long ccu_div_lock_delay_ns(unsigned long ref_clk,
+ unsigned long div)
+{
+ u64 ns = 4ULL * (div ?: 1) * NSEC_PER_SEC;
+
+ do_div(ns, ref_clk);
+
+ return ns;
+}
+
+static inline unsigned long ccu_div_calc_freq(unsigned long ref_clk,
+ unsigned long div)
+{
+ return ref_clk / (div ?: 1);
+}
+
+static int ccu_div_var_update_clkdiv(struct ccu_div *div,
+ unsigned long parent_rate,
+ unsigned long divider)
+{
+ unsigned long nd;
+ u32 val = 0;
+ u32 lock;
+ int count;
+
+ nd = ccu_div_lock_delay_ns(parent_rate, divider);
+
+ if (div->features & CCU_DIV_LOCK_SHIFTED)
+ lock = CCU_DIV_CTL_LOCK_SHIFTED;
+ else
+ lock = CCU_DIV_CTL_LOCK_NORMAL;
+
+ regmap_update_bits(div->sys_regs, div->reg_ctl,
+ CCU_DIV_CTL_SET_CLKDIV, CCU_DIV_CTL_SET_CLKDIV);
+
+ /*
+ * Until there is nsec-version of readl_poll_timeout() is available
+ * we have to implement the next polling loop.
+ */
+ count = CCU_DIV_LOCK_CHECK_RETRIES;
+ do {
+ ndelay(nd);
+ regmap_read(div->sys_regs, div->reg_ctl, &val);
+ if (val & lock)
+ return 0;
+ } while (--count);
+
+ return -ETIMEDOUT;
+}
+
+static int ccu_div_var_enable(struct clk_hw *hw)
+{
+ struct clk_hw *parent_hw = clk_hw_get_parent(hw);
+ struct ccu_div *div = to_ccu_div(hw);
+ unsigned long flags;
+ u32 val = 0;
+ int ret;
+
+ if (!parent_hw) {
+ pr_err("Can't enable '%s' with no parent", clk_hw_get_name(hw));
+ return -EINVAL;
+ }
+
+ regmap_read(div->sys_regs, div->reg_ctl, &val);
+ if (val & CCU_DIV_CTL_EN)
+ return 0;
+
+ spin_lock_irqsave(&div->lock, flags);
+ ret = ccu_div_var_update_clkdiv(div, clk_hw_get_rate(parent_hw),
+ ccu_div_get(div->mask, val));
+ if (!ret)
+ regmap_update_bits(div->sys_regs, div->reg_ctl,
+ CCU_DIV_CTL_EN, CCU_DIV_CTL_EN);
+ spin_unlock_irqrestore(&div->lock, flags);
+ if (ret)
+ pr_err("Divider '%s' lock timed out\n", clk_hw_get_name(hw));
+
+ return ret;
+}
+
+static int ccu_div_gate_enable(struct clk_hw *hw)
+{
+ struct ccu_div *div = to_ccu_div(hw);
+ unsigned long flags;
+
+ spin_lock_irqsave(&div->lock, flags);
+ regmap_update_bits(div->sys_regs, div->reg_ctl,
+ CCU_DIV_CTL_EN, CCU_DIV_CTL_EN);
+ spin_unlock_irqrestore(&div->lock, flags);
+
+ return 0;
+}
+
+static void ccu_div_gate_disable(struct clk_hw *hw)
+{
+ struct ccu_div *div = to_ccu_div(hw);
+ unsigned long flags;
+
+ spin_lock_irqsave(&div->lock, flags);
+ regmap_update_bits(div->sys_regs, div->reg_ctl, CCU_DIV_CTL_EN, 0);
+ spin_unlock_irqrestore(&div->lock, flags);
+}
+
+static int ccu_div_gate_is_enabled(struct clk_hw *hw)
+{
+ struct ccu_div *div = to_ccu_div(hw);
+ u32 val = 0;
+
+ regmap_read(div->sys_regs, div->reg_ctl, &val);
+
+ return !!(val & CCU_DIV_CTL_EN);
+}
+
+static unsigned long ccu_div_var_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct ccu_div *div = to_ccu_div(hw);
+ unsigned long divider;
+ u32 val = 0;
+
+ regmap_read(div->sys_regs, div->reg_ctl, &val);
+ divider = ccu_div_get(div->mask, val);
+
+ return ccu_div_calc_freq(parent_rate, divider);
+}
+
+static inline unsigned long ccu_div_var_calc_divider(unsigned long rate,
+ unsigned long parent_rate,
+ unsigned int mask)
+{
+ unsigned long divider;
+
+ divider = parent_rate / rate;
+ return clamp_t(unsigned long, divider, CCU_DIV_CLKDIV_MIN,
+ CCU_DIV_CLKDIV_MAX(mask));
+}
+
+static long ccu_div_var_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct ccu_div *div = to_ccu_div(hw);
+ unsigned long divider;
+
+ divider = ccu_div_var_calc_divider(rate, *parent_rate, div->mask);
+
+ return ccu_div_calc_freq(*parent_rate, divider);
+}
+
+/*
+ * This method is used for the clock divider blocks, which support the
+ * on-the-fly rate change. So due to lacking the EN bit functionality
+ * they can't be gated before the rate adjustment.
+ */
+static int ccu_div_var_set_rate_slow(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct ccu_div *div = to_ccu_div(hw);
+ unsigned long flags, divider;
+ u32 val;
+ int ret;
+
+ divider = ccu_div_var_calc_divider(rate, parent_rate, div->mask);
+ if (divider == 1 && div->features & CCU_DIV_SKIP_ONE) {
+ divider = 0;
+ } else if (div->features & CCU_DIV_SKIP_ONE_TO_THREE) {
+ if (divider == 1 || divider == 2)
+ divider = 0;
+ else if (divider == 3)
+ divider = 4;
+ }
+
+ val = ccu_div_prep(div->mask, divider);
+
+ spin_lock_irqsave(&div->lock, flags);
+ regmap_update_bits(div->sys_regs, div->reg_ctl, div->mask, val);
+ ret = ccu_div_var_update_clkdiv(div, parent_rate, divider);
+ spin_unlock_irqrestore(&div->lock, flags);
+ if (ret)
+ pr_err("Divider '%s' lock timed out\n", clk_hw_get_name(hw));
+
+ return ret;
+}
+
+/*
+ * This method is used for the clock divider blocks, which don't support
+ * the on-the-fly rate change.
+ */
+static int ccu_div_var_set_rate_fast(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct ccu_div *div = to_ccu_div(hw);
+ unsigned long flags, divider = 1;
+ u32 val;
+
+ divider = ccu_div_var_calc_divider(rate, parent_rate, div->mask);
+ val = ccu_div_prep(div->mask, divider);
+
+ /*
+ * Also disable the clock divider block if it was enabled by default
+ * or by the bootloader.
+ */
+ spin_lock_irqsave(&div->lock, flags);
+ regmap_update_bits(div->sys_regs, div->reg_ctl,
+ div->mask | CCU_DIV_CTL_EN, val);
+ spin_unlock_irqrestore(&div->lock, flags);
+
+ return 0;
+}
+
+static unsigned long ccu_div_fixed_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct ccu_div *div = to_ccu_div(hw);
+
+ return ccu_div_calc_freq(parent_rate, div->divider);
+}
+
+static long ccu_div_fixed_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct ccu_div *div = to_ccu_div(hw);
+
+ return ccu_div_calc_freq(*parent_rate, div->divider);
+}
+
+static int ccu_div_fixed_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ return 0;
+}
+
+int ccu_div_reset_domain(struct ccu_div *div)
+{
+ unsigned long flags;
+
+ if (!div || !(div->features & CCU_DIV_RESET_DOMAIN))
+ return -EINVAL;
+
+ spin_lock_irqsave(&div->lock, flags);
+ regmap_update_bits(div->sys_regs, div->reg_ctl,
+ CCU_DIV_CTL_RST, CCU_DIV_CTL_RST);
+ spin_unlock_irqrestore(&div->lock, flags);
+
+ /* The next delay must be enough to cover all the resets. */
+ udelay(CCU_DIV_RST_DELAY_US);
+
+ return 0;
+}
+
+#ifdef CONFIG_DEBUG_FS
+
+struct ccu_div_dbgfs_bit {
+ struct ccu_div *div;
+ const char *name;
+ u32 mask;
+};
+
+#define CCU_DIV_DBGFS_BIT_ATTR(_name, _mask) { \
+ .name = _name, \
+ .mask = _mask \
+ }
+
+static const struct ccu_div_dbgfs_bit ccu_div_bits[] = {
+ CCU_DIV_DBGFS_BIT_ATTR("div_en", CCU_DIV_CTL_EN),
+ CCU_DIV_DBGFS_BIT_ATTR("div_rst", CCU_DIV_CTL_RST),
+ CCU_DIV_DBGFS_BIT_ATTR("div_bypass", CCU_DIV_CTL_SET_CLKDIV),
+ CCU_DIV_DBGFS_BIT_ATTR("div_lock", CCU_DIV_CTL_LOCK_NORMAL)
+};
+
+#define CCU_DIV_DBGFS_BIT_NUM ARRAY_SIZE(ccu_div_bits)
+
+/*
+ * It can be dangerous to change the Divider settings behind clock framework
+ * back, therefore we don't provide any kernel config based compile time option
+ * for this feature to enable.
+ */
+#undef CCU_DIV_ALLOW_WRITE_DEBUGFS
+#ifdef CCU_DIV_ALLOW_WRITE_DEBUGFS
+
+static int ccu_div_dbgfs_bit_set(void *priv, u64 val)
+{
+ const struct ccu_div_dbgfs_bit *bit = priv;
+ struct ccu_div *div = bit->div;
+ unsigned long flags;
+
+ spin_lock_irqsave(&div->lock, flags);
+ regmap_update_bits(div->sys_regs, div->reg_ctl,
+ bit->mask, val ? bit->mask : 0);
+ spin_unlock_irqrestore(&div->lock, flags);
+
+ return 0;
+}
+
+static int ccu_div_dbgfs_var_clkdiv_set(void *priv, u64 val)
+{
+ struct ccu_div *div = priv;
+ unsigned long flags;
+ u32 data;
+
+ val = clamp_t(u64, val, CCU_DIV_CLKDIV_MIN,
+ CCU_DIV_CLKDIV_MAX(div->mask));
+ data = ccu_div_prep(div->mask, val);
+
+ spin_lock_irqsave(&div->lock, flags);
+ regmap_update_bits(div->sys_regs, div->reg_ctl, div->mask, data);
+ spin_unlock_irqrestore(&div->lock, flags);
+
+ return 0;
+}
+
+#define ccu_div_dbgfs_mode 0644
+
+#else /* !CCU_DIV_ALLOW_WRITE_DEBUGFS */
+
+#define ccu_div_dbgfs_bit_set NULL
+#define ccu_div_dbgfs_var_clkdiv_set NULL
+#define ccu_div_dbgfs_mode 0444
+
+#endif /* !CCU_DIV_ALLOW_WRITE_DEBUGFS */
+
+static int ccu_div_dbgfs_bit_get(void *priv, u64 *val)
+{
+ const struct ccu_div_dbgfs_bit *bit = priv;
+ struct ccu_div *div = bit->div;
+ u32 data = 0;
+
+ regmap_read(div->sys_regs, div->reg_ctl, &data);
+ *val = !!(data & bit->mask);
+
+ return 0;
+}
+DEFINE_DEBUGFS_ATTRIBUTE(ccu_div_dbgfs_bit_fops,
+ ccu_div_dbgfs_bit_get, ccu_div_dbgfs_bit_set, "%llu\n");
+
+static int ccu_div_dbgfs_var_clkdiv_get(void *priv, u64 *val)
+{
+ struct ccu_div *div = priv;
+ u32 data = 0;
+
+ regmap_read(div->sys_regs, div->reg_ctl, &data);
+ *val = ccu_div_get(div->mask, data);
+
+ return 0;
+}
+DEFINE_DEBUGFS_ATTRIBUTE(ccu_div_dbgfs_var_clkdiv_fops,
+ ccu_div_dbgfs_var_clkdiv_get, ccu_div_dbgfs_var_clkdiv_set, "%llu\n");
+
+static int ccu_div_dbgfs_fixed_clkdiv_get(void *priv, u64 *val)
+{
+ struct ccu_div *div = priv;
+
+ *val = div->divider;
+
+ return 0;
+}
+DEFINE_DEBUGFS_ATTRIBUTE(ccu_div_dbgfs_fixed_clkdiv_fops,
+ ccu_div_dbgfs_fixed_clkdiv_get, NULL, "%llu\n");
+
+static void ccu_div_var_debug_init(struct clk_hw *hw, struct dentry *dentry)
+{
+ struct ccu_div *div = to_ccu_div(hw);
+ struct ccu_div_dbgfs_bit *bits;
+ int didx, bidx, num = 2;
+ const char *name;
+
+ num += !!(div->flags & CLK_SET_RATE_GATE) +
+ !!(div->features & CCU_DIV_RESET_DOMAIN);
+
+ bits = kcalloc(num, sizeof(*bits), GFP_KERNEL);
+ if (!bits)
+ return;
+
+ for (didx = 0, bidx = 0; bidx < CCU_DIV_DBGFS_BIT_NUM; ++bidx) {
+ name = ccu_div_bits[bidx].name;
+ if (!(div->flags & CLK_SET_RATE_GATE) &&
+ !strcmp("div_en", name)) {
+ continue;
+ }
+
+ if (!(div->features & CCU_DIV_RESET_DOMAIN) &&
+ !strcmp("div_rst", name)) {
+ continue;
+ }
+
+ bits[didx] = ccu_div_bits[bidx];
+ bits[didx].div = div;
+
+ if (div->features & CCU_DIV_LOCK_SHIFTED &&
+ !strcmp("div_lock", name)) {
+ bits[didx].mask = CCU_DIV_CTL_LOCK_SHIFTED;
+ }
+
+ debugfs_create_file_unsafe(bits[didx].name, ccu_div_dbgfs_mode,
+ dentry, &bits[didx],
+ &ccu_div_dbgfs_bit_fops);
+ ++didx;
+ }
+
+ debugfs_create_file_unsafe("div_clkdiv", ccu_div_dbgfs_mode, dentry,
+ div, &ccu_div_dbgfs_var_clkdiv_fops);
+}
+
+static void ccu_div_gate_debug_init(struct clk_hw *hw, struct dentry *dentry)
+{
+ struct ccu_div *div = to_ccu_div(hw);
+ struct ccu_div_dbgfs_bit *bit;
+
+ bit = kmalloc(sizeof(*bit), GFP_KERNEL);
+ if (!bit)
+ return;
+
+ *bit = ccu_div_bits[0];
+ bit->div = div;
+ debugfs_create_file_unsafe(bit->name, ccu_div_dbgfs_mode, dentry, bit,
+ &ccu_div_dbgfs_bit_fops);
+
+ debugfs_create_file_unsafe("div_clkdiv", 0400, dentry, div,
+ &ccu_div_dbgfs_fixed_clkdiv_fops);
+}
+
+static void ccu_div_fixed_debug_init(struct clk_hw *hw, struct dentry *dentry)
+{
+ struct ccu_div *div = to_ccu_div(hw);
+
+ debugfs_create_file_unsafe("div_clkdiv", 0400, dentry, div,
+ &ccu_div_dbgfs_fixed_clkdiv_fops);
+}
+
+#else /* !CONFIG_DEBUG_FS */
+
+#define ccu_div_var_debug_init NULL
+#define ccu_div_gate_debug_init NULL
+#define ccu_div_fixed_debug_init NULL
+
+#endif /* !CONFIG_DEBUG_FS */
+
+static const struct clk_ops ccu_div_var_gate_to_set_ops = {
+ .enable = ccu_div_var_enable,
+ .disable = ccu_div_gate_disable,
+ .is_enabled = ccu_div_gate_is_enabled,
+ .recalc_rate = ccu_div_var_recalc_rate,
+ .round_rate = ccu_div_var_round_rate,
+ .set_rate = ccu_div_var_set_rate_fast,
+ .debug_init = ccu_div_var_debug_init
+};
+
+static const struct clk_ops ccu_div_var_nogate_ops = {
+ .recalc_rate = ccu_div_var_recalc_rate,
+ .round_rate = ccu_div_var_round_rate,
+ .set_rate = ccu_div_var_set_rate_slow,
+ .debug_init = ccu_div_var_debug_init
+};
+
+static const struct clk_ops ccu_div_gate_ops = {
+ .enable = ccu_div_gate_enable,
+ .disable = ccu_div_gate_disable,
+ .is_enabled = ccu_div_gate_is_enabled,
+ .recalc_rate = ccu_div_fixed_recalc_rate,
+ .round_rate = ccu_div_fixed_round_rate,
+ .set_rate = ccu_div_fixed_set_rate,
+ .debug_init = ccu_div_gate_debug_init
+};
+
+static const struct clk_ops ccu_div_fixed_ops = {
+ .recalc_rate = ccu_div_fixed_recalc_rate,
+ .round_rate = ccu_div_fixed_round_rate,
+ .set_rate = ccu_div_fixed_set_rate,
+ .debug_init = ccu_div_fixed_debug_init
+};
+
+struct ccu_div *ccu_div_hw_register(const struct ccu_div_init_data *div_init)
+{
+ struct clk_parent_data parent_data = {0};
+ struct clk_init_data hw_init = {0};
+ struct ccu_div *div;
+ int ret;
+
+ if (!div_init)
+ return ERR_PTR(-EINVAL);
+
+ div = kzalloc(sizeof(*div), GFP_KERNEL);
+ if (!div)
+ return ERR_PTR(-ENOMEM);
+
+ /*
+ * Note since Baikal-T1 System Controller registers are MMIO-backed
+ * we won't check the regmap IO operations return status, because it
+ * must be zero anyway.
+ */
+ div->hw.init = &hw_init;
+ div->id = div_init->id;
+ div->reg_ctl = div_init->base + CCU_DIV_CTL;
+ div->sys_regs = div_init->sys_regs;
+ div->flags = div_init->flags;
+ div->features = div_init->features;
+ spin_lock_init(&div->lock);
+
+ hw_init.name = div_init->name;
+ hw_init.flags = div_init->flags;
+
+ if (div_init->type == CCU_DIV_VAR) {
+ if (hw_init.flags & CLK_SET_RATE_GATE)
+ hw_init.ops = &ccu_div_var_gate_to_set_ops;
+ else
+ hw_init.ops = &ccu_div_var_nogate_ops;
+ div->mask = CCU_DIV_CTL_CLKDIV_MASK(div_init->width);
+ } else if (div_init->type == CCU_DIV_GATE) {
+ hw_init.ops = &ccu_div_gate_ops;
+ div->divider = div_init->divider;
+ } else if (div_init->type == CCU_DIV_FIXED) {
+ hw_init.ops = &ccu_div_fixed_ops;
+ div->divider = div_init->divider;
+ } else {
+ ret = -EINVAL;
+ goto err_free_div;
+ }
+
+ if (!div_init->parent_name) {
+ ret = -EINVAL;
+ goto err_free_div;
+ }
+ parent_data.fw_name = div_init->parent_name;
+ hw_init.parent_data = &parent_data;
+ hw_init.num_parents = 1;
+
+ ret = of_clk_hw_register(div_init->np, &div->hw);
+ if (ret)
+ goto err_free_div;
+
+ return div;
+
+err_free_div:
+ kfree(div);
+
+ return ERR_PTR(ret);
+}
+
+void ccu_div_hw_unregister(struct ccu_div *div)
+{
+ clk_hw_unregister(&div->hw);
+
+ kfree(div);
+}
diff --git a/drivers/clk/baikal-t1/ccu-div.h b/drivers/clk/baikal-t1/ccu-div.h
new file mode 100644
index 000000000000..795665caefbd
--- /dev/null
+++ b/drivers/clk/baikal-t1/ccu-div.h
@@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
+ *
+ * Baikal-T1 CCU Dividers interface driver
+ */
+#ifndef __CLK_BT1_CCU_DIV_H__
+#define __CLK_BT1_CCU_DIV_H__
+
+#include <linux/clk-provider.h>
+#include <linux/spinlock.h>
+#include <linux/regmap.h>
+#include <linux/bits.h>
+#include <linux/of.h>
+
+/*
+ * CCU Divider private flags
+ * @CCU_DIV_SKIP_ONE: Due to some reason divider can't be set to 1.
+ * It can be 0 though, which is functionally the same.
+ * @CCU_DIV_SKIP_ONE_TO_THREE: For some reason divider can't be within [1,3].
+ * It can be either 0 or greater than 3.
+ * @CCU_DIV_LOCK_SHIFTED: Find lock-bit at non-standard position.
+ * @CCU_DIV_RESET_DOMAIN: Provide reset clock domain method.
+ */
+#define CCU_DIV_SKIP_ONE BIT(1)
+#define CCU_DIV_SKIP_ONE_TO_THREE BIT(2)
+#define CCU_DIV_LOCK_SHIFTED BIT(3)
+#define CCU_DIV_RESET_DOMAIN BIT(4)
+
+/*
+ * enum ccu_div_type - CCU Divider types
+ * @CCU_DIV_VAR: Clocks gate with variable divider.
+ * @CCU_DIV_GATE: Clocks gate with fixed divider.
+ * @CCU_DIV_FIXED: Ungateable clock with fixed divider.
+ */
+enum ccu_div_type {
+ CCU_DIV_VAR,
+ CCU_DIV_GATE,
+ CCU_DIV_FIXED
+};
+
+/*
+ * struct ccu_div_init_data - CCU Divider initialization data
+ * @id: Clocks private identifier.
+ * @name: Clocks name.
+ * @parent_name: Parent clocks name in a fw node.
+ * @base: Divider register base address with respect to the sys_regs base.
+ * @sys_regs: Baikal-T1 System Controller registers map.
+ * @np: Pointer to the node describing the CCU Dividers.
+ * @type: CCU divider type (variable, fixed with and without gate).
+ * @width: Divider width if it's variable.
+ * @divider: Divider fixed value.
+ * @flags: CCU Divider clock flags.
+ * @features: CCU Divider private features.
+ */
+struct ccu_div_init_data {
+ unsigned int id;
+ const char *name;
+ const char *parent_name;
+ unsigned int base;
+ struct regmap *sys_regs;
+ struct device_node *np;
+ enum ccu_div_type type;
+ union {
+ unsigned int width;
+ unsigned int divider;
+ };
+ unsigned long flags;
+ unsigned long features;
+};
+
+/*
+ * struct ccu_div - CCU Divider descriptor
+ * @hw: clk_hw of the divider.
+ * @id: Clock private identifier.
+ * @reg_ctl: Divider control register base address.
+ * @sys_regs: Baikal-T1 System Controller registers map.
+ * @lock: Divider state change spin-lock.
+ * @mask: Divider field mask.
+ * @divider: Divider fixed value.
+ * @flags: Divider clock flags.
+ * @features: CCU Divider private features.
+ */
+struct ccu_div {
+ struct clk_hw hw;
+ unsigned int id;
+ unsigned int reg_ctl;
+ struct regmap *sys_regs;
+ spinlock_t lock;
+ union {
+ u32 mask;
+ unsigned int divider;
+ };
+ unsigned long flags;
+ unsigned long features;
+};
+#define to_ccu_div(_hw) container_of(_hw, struct ccu_div, hw)
+
+static inline struct clk_hw *ccu_div_get_clk_hw(struct ccu_div *div)
+{
+ return div ? &div->hw : NULL;
+}
+
+struct ccu_div *ccu_div_hw_register(const struct ccu_div_init_data *init);
+
+void ccu_div_hw_unregister(struct ccu_div *div);
+
+int ccu_div_reset_domain(struct ccu_div *div);
+
+#endif /* __CLK_BT1_CCU_DIV_H__ */
diff --git a/drivers/clk/baikal-t1/clk-ccu-div.c b/drivers/clk/baikal-t1/clk-ccu-div.c
new file mode 100644
index 000000000000..3931a2d33943
--- /dev/null
+++ b/drivers/clk/baikal-t1/clk-ccu-div.c
@@ -0,0 +1,487 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
+ *
+ * Authors:
+ * Serge Semin <Sergey.Semin@baikalelectronics.ru>
+ * Dmitry Dunaev <dmitry.dunaev@baikalelectronics.ru>
+ *
+ * Baikal-T1 CCU Dividers clock driver
+ */
+
+#define pr_fmt(fmt) "bt1-ccu-div: " fmt
+
+#include <linux/kernel.h>
+#include <linux/printk.h>
+#include <linux/slab.h>
+#include <linux/clk-provider.h>
+#include <linux/reset-controller.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/ioport.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/bt1-ccu.h>
+#include <dt-bindings/reset/bt1-ccu.h>
+
+#include "ccu-div.h"
+
+#define CCU_AXI_MAIN_BASE 0x030
+#define CCU_AXI_DDR_BASE 0x034
+#define CCU_AXI_SATA_BASE 0x038
+#define CCU_AXI_GMAC0_BASE 0x03C
+#define CCU_AXI_GMAC1_BASE 0x040
+#define CCU_AXI_XGMAC_BASE 0x044
+#define CCU_AXI_PCIE_M_BASE 0x048
+#define CCU_AXI_PCIE_S_BASE 0x04C
+#define CCU_AXI_USB_BASE 0x050
+#define CCU_AXI_HWA_BASE 0x054
+#define CCU_AXI_SRAM_BASE 0x058
+
+#define CCU_SYS_SATA_REF_BASE 0x060
+#define CCU_SYS_APB_BASE 0x064
+#define CCU_SYS_GMAC0_BASE 0x068
+#define CCU_SYS_GMAC1_BASE 0x06C
+#define CCU_SYS_XGMAC_BASE 0x070
+#define CCU_SYS_USB_BASE 0x074
+#define CCU_SYS_PVT_BASE 0x078
+#define CCU_SYS_HWA_BASE 0x07C
+#define CCU_SYS_UART_BASE 0x084
+#define CCU_SYS_TIMER0_BASE 0x088
+#define CCU_SYS_TIMER1_BASE 0x08C
+#define CCU_SYS_TIMER2_BASE 0x090
+#define CCU_SYS_WDT_BASE 0x150
+
+#define CCU_DIV_VAR_INFO(_id, _name, _pname, _base, _width, _flags, _features) \
+ { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _pname, \
+ .base = _base, \
+ .type = CCU_DIV_VAR, \
+ .width = _width, \
+ .flags = _flags, \
+ .features = _features \
+ }
+
+#define CCU_DIV_GATE_INFO(_id, _name, _pname, _base, _divider) \
+ { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _pname, \
+ .base = _base, \
+ .type = CCU_DIV_GATE, \
+ .divider = _divider \
+ }
+
+#define CCU_DIV_FIXED_INFO(_id, _name, _pname, _divider) \
+ { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _pname, \
+ .type = CCU_DIV_FIXED, \
+ .divider = _divider \
+ }
+
+#define CCU_DIV_RST_MAP(_rst_id, _clk_id) \
+ { \
+ .rst_id = _rst_id, \
+ .clk_id = _clk_id \
+ }
+
+struct ccu_div_info {
+ unsigned int id;
+ const char *name;
+ const char *parent_name;
+ unsigned int base;
+ enum ccu_div_type type;
+ union {
+ unsigned int width;
+ unsigned int divider;
+ };
+ unsigned long flags;
+ unsigned long features;
+};
+
+struct ccu_div_rst_map {
+ unsigned int rst_id;
+ unsigned int clk_id;
+};
+
+struct ccu_div_data {
+ struct device_node *np;
+ struct regmap *sys_regs;
+
+ unsigned int divs_num;
+ const struct ccu_div_info *divs_info;
+ struct ccu_div **divs;
+
+ unsigned int rst_num;
+ const struct ccu_div_rst_map *rst_map;
+ struct reset_controller_dev rcdev;
+};
+#define to_ccu_div_data(_rcdev) container_of(_rcdev, struct ccu_div_data, rcdev)
+
+/*
+ * AXI Main Interconnect (axi_main_clk) and DDR AXI-bus (axi_ddr_clk) clocks
+ * must be left enabled in any case, since former one is responsible for
+ * clocking a bus between CPU cores and the rest of the SoC components, while
+ * the later is clocking the AXI-bus between DDR controller and the Main
+ * Interconnect. So should any of these clocks get to be disabled, the system
+ * will literally stop working. That's why we marked them as critical.
+ */
+static const struct ccu_div_info axi_info[] = {
+ CCU_DIV_VAR_INFO(CCU_AXI_MAIN_CLK, "axi_main_clk", "pcie_clk",
+ CCU_AXI_MAIN_BASE, 4,
+ CLK_IS_CRITICAL, CCU_DIV_RESET_DOMAIN),
+ CCU_DIV_VAR_INFO(CCU_AXI_DDR_CLK, "axi_ddr_clk", "sata_clk",
+ CCU_AXI_DDR_BASE, 4,
+ CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
+ CCU_DIV_RESET_DOMAIN),
+ CCU_DIV_VAR_INFO(CCU_AXI_SATA_CLK, "axi_sata_clk", "sata_clk",
+ CCU_AXI_SATA_BASE, 4,
+ CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
+ CCU_DIV_VAR_INFO(CCU_AXI_GMAC0_CLK, "axi_gmac0_clk", "eth_clk",
+ CCU_AXI_GMAC0_BASE, 4,
+ CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
+ CCU_DIV_VAR_INFO(CCU_AXI_GMAC1_CLK, "axi_gmac1_clk", "eth_clk",
+ CCU_AXI_GMAC1_BASE, 4,
+ CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
+ CCU_DIV_VAR_INFO(CCU_AXI_XGMAC_CLK, "axi_xgmac_clk", "eth_clk",
+ CCU_AXI_XGMAC_BASE, 4,
+ CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
+ CCU_DIV_VAR_INFO(CCU_AXI_PCIE_M_CLK, "axi_pcie_m_clk", "pcie_clk",
+ CCU_AXI_PCIE_M_BASE, 4,
+ CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
+ CCU_DIV_VAR_INFO(CCU_AXI_PCIE_S_CLK, "axi_pcie_s_clk", "pcie_clk",
+ CCU_AXI_PCIE_S_BASE, 4,
+ CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
+ CCU_DIV_VAR_INFO(CCU_AXI_USB_CLK, "axi_usb_clk", "sata_clk",
+ CCU_AXI_USB_BASE, 4,
+ CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
+ CCU_DIV_VAR_INFO(CCU_AXI_HWA_CLK, "axi_hwa_clk", "sata_clk",
+ CCU_AXI_HWA_BASE, 4,
+ CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
+ CCU_DIV_VAR_INFO(CCU_AXI_SRAM_CLK, "axi_sram_clk", "eth_clk",
+ CCU_AXI_SRAM_BASE, 4,
+ CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN)
+};
+
+static const struct ccu_div_rst_map axi_rst_map[] = {
+ CCU_DIV_RST_MAP(CCU_AXI_MAIN_RST, CCU_AXI_MAIN_CLK),
+ CCU_DIV_RST_MAP(CCU_AXI_DDR_RST, CCU_AXI_DDR_CLK),
+ CCU_DIV_RST_MAP(CCU_AXI_SATA_RST, CCU_AXI_SATA_CLK),
+ CCU_DIV_RST_MAP(CCU_AXI_GMAC0_RST, CCU_AXI_GMAC0_CLK),
+ CCU_DIV_RST_MAP(CCU_AXI_GMAC1_RST, CCU_AXI_GMAC1_CLK),
+ CCU_DIV_RST_MAP(CCU_AXI_XGMAC_RST, CCU_AXI_XGMAC_CLK),
+ CCU_DIV_RST_MAP(CCU_AXI_PCIE_M_RST, CCU_AXI_PCIE_M_CLK),
+ CCU_DIV_RST_MAP(CCU_AXI_PCIE_S_RST, CCU_AXI_PCIE_S_CLK),
+ CCU_DIV_RST_MAP(CCU_AXI_USB_RST, CCU_AXI_USB_CLK),
+ CCU_DIV_RST_MAP(CCU_AXI_HWA_RST, CCU_AXI_HWA_CLK),
+ CCU_DIV_RST_MAP(CCU_AXI_SRAM_RST, CCU_AXI_SRAM_CLK)
+};
+
+/*
+ * APB-bus clock is marked as critical since it's a main communication bus
+ * for the SoC devices registers IO-operations.
+ */
+static const struct ccu_div_info sys_info[] = {
+ CCU_DIV_VAR_INFO(CCU_SYS_SATA_REF_CLK, "sys_sata_ref_clk",
+ "sata_clk", CCU_SYS_SATA_REF_BASE, 4,
+ CLK_SET_RATE_GATE,
+ CCU_DIV_SKIP_ONE | CCU_DIV_LOCK_SHIFTED |
+ CCU_DIV_RESET_DOMAIN),
+ CCU_DIV_VAR_INFO(CCU_SYS_APB_CLK, "sys_apb_clk",
+ "pcie_clk", CCU_SYS_APB_BASE, 5,
+ CLK_IS_CRITICAL, CCU_DIV_RESET_DOMAIN),
+ CCU_DIV_GATE_INFO(CCU_SYS_GMAC0_TX_CLK, "sys_gmac0_tx_clk",
+ "eth_clk", CCU_SYS_GMAC0_BASE, 5),
+ CCU_DIV_FIXED_INFO(CCU_SYS_GMAC0_PTP_CLK, "sys_gmac0_ptp_clk",
+ "eth_clk", 10),
+ CCU_DIV_GATE_INFO(CCU_SYS_GMAC1_TX_CLK, "sys_gmac1_tx_clk",
+ "eth_clk", CCU_SYS_GMAC1_BASE, 5),
+ CCU_DIV_FIXED_INFO(CCU_SYS_GMAC1_PTP_CLK, "sys_gmac1_ptp_clk",
+ "eth_clk", 10),
+ CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",
+ "eth_clk", CCU_SYS_XGMAC_BASE, 8),
+ CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_PTP_CLK, "sys_xgmac_ptp_clk",
+ "eth_clk", 10),
+ CCU_DIV_GATE_INFO(CCU_SYS_USB_CLK, "sys_usb_clk",
+ "eth_clk", CCU_SYS_USB_BASE, 10),
+ CCU_DIV_VAR_INFO(CCU_SYS_PVT_CLK, "sys_pvt_clk",
+ "ref_clk", CCU_SYS_PVT_BASE, 5,
+ CLK_SET_RATE_GATE, 0),
+ CCU_DIV_VAR_INFO(CCU_SYS_HWA_CLK, "sys_hwa_clk",
+ "sata_clk", CCU_SYS_HWA_BASE, 4,
+ CLK_SET_RATE_GATE, 0),
+ CCU_DIV_VAR_INFO(CCU_SYS_UART_CLK, "sys_uart_clk",
+ "eth_clk", CCU_SYS_UART_BASE, 17,
+ CLK_SET_RATE_GATE, 0),
+ CCU_DIV_FIXED_INFO(CCU_SYS_I2C1_CLK, "sys_i2c1_clk",
+ "eth_clk", 10),
+ CCU_DIV_FIXED_INFO(CCU_SYS_I2C2_CLK, "sys_i2c2_clk",
+ "eth_clk", 10),
+ CCU_DIV_FIXED_INFO(CCU_SYS_GPIO_CLK, "sys_gpio_clk",
+ "ref_clk", 25),
+ CCU_DIV_VAR_INFO(CCU_SYS_TIMER0_CLK, "sys_timer0_clk",
+ "ref_clk", CCU_SYS_TIMER0_BASE, 17,
+ CLK_SET_RATE_GATE, 0),
+ CCU_DIV_VAR_INFO(CCU_SYS_TIMER1_CLK, "sys_timer1_clk",
+ "ref_clk", CCU_SYS_TIMER1_BASE, 17,
+ CLK_SET_RATE_GATE, 0),
+ CCU_DIV_VAR_INFO(CCU_SYS_TIMER2_CLK, "sys_timer2_clk",
+ "ref_clk", CCU_SYS_TIMER2_BASE, 17,
+ CLK_SET_RATE_GATE, 0),
+ CCU_DIV_VAR_INFO(CCU_SYS_WDT_CLK, "sys_wdt_clk",
+ "eth_clk", CCU_SYS_WDT_BASE, 17,
+ CLK_SET_RATE_GATE, CCU_DIV_SKIP_ONE_TO_THREE)
+};
+
+static const struct ccu_div_rst_map sys_rst_map[] = {
+ CCU_DIV_RST_MAP(CCU_SYS_SATA_REF_RST, CCU_SYS_SATA_REF_CLK),
+ CCU_DIV_RST_MAP(CCU_SYS_APB_RST, CCU_SYS_APB_CLK),
+};
+
+static struct ccu_div *ccu_div_find_desc(struct ccu_div_data *data,
+ unsigned int clk_id)
+{
+ struct ccu_div *div;
+ int idx;
+
+ for (idx = 0; idx < data->divs_num; ++idx) {
+ div = data->divs[idx];
+ if (div && div->id == clk_id)
+ return div;
+ }
+
+ return ERR_PTR(-EINVAL);
+}
+
+static int ccu_div_reset(struct reset_controller_dev *rcdev,
+ unsigned long rst_id)
+{
+ struct ccu_div_data *data = to_ccu_div_data(rcdev);
+ const struct ccu_div_rst_map *map;
+ struct ccu_div *div;
+ int idx, ret;
+
+ for (idx = 0, map = data->rst_map; idx < data->rst_num; ++idx, ++map) {
+ if (map->rst_id == rst_id)
+ break;
+ }
+ if (idx == data->rst_num) {
+ pr_err("Invalid reset ID %lu specified\n", rst_id);
+ return -EINVAL;
+ }
+
+ div = ccu_div_find_desc(data, map->clk_id);
+ if (IS_ERR(div)) {
+ pr_err("Invalid clock ID %d in mapping\n", map->clk_id);
+ return PTR_ERR(div);
+ }
+
+ ret = ccu_div_reset_domain(div);
+ if (ret) {
+ pr_err("Reset isn't supported by divider %s\n",
+ clk_hw_get_name(ccu_div_get_clk_hw(div)));
+ }
+
+ return ret;
+}
+
+static const struct reset_control_ops ccu_div_rst_ops = {
+ .reset = ccu_div_reset,
+};
+
+static struct ccu_div_data *ccu_div_create_data(struct device_node *np)
+{
+ struct ccu_div_data *data;
+ int ret;
+
+ data = kzalloc(sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return ERR_PTR(-ENOMEM);
+
+ data->np = np;
+ if (of_device_is_compatible(np, "baikal,bt1-ccu-axi")) {
+ data->divs_num = ARRAY_SIZE(axi_info);
+ data->divs_info = axi_info;
+ data->rst_num = ARRAY_SIZE(axi_rst_map);
+ data->rst_map = axi_rst_map;
+ } else if (of_device_is_compatible(np, "baikal,bt1-ccu-sys")) {
+ data->divs_num = ARRAY_SIZE(sys_info);
+ data->divs_info = sys_info;
+ data->rst_num = ARRAY_SIZE(sys_rst_map);
+ data->rst_map = sys_rst_map;
+ } else {
+ pr_err("Uncompatible DT node '%s' specified\n",
+ of_node_full_name(np));
+ ret = -EINVAL;
+ goto err_kfree_data;
+ }
+
+ data->divs = kcalloc(data->divs_num, sizeof(*data->divs), GFP_KERNEL);
+ if (!data->divs) {
+ ret = -ENOMEM;
+ goto err_kfree_data;
+ }
+
+ return data;
+
+err_kfree_data:
+ kfree(data);
+
+ return ERR_PTR(ret);
+}
+
+static void ccu_div_free_data(struct ccu_div_data *data)
+{
+ kfree(data->divs);
+
+ kfree(data);
+}
+
+static int ccu_div_find_sys_regs(struct ccu_div_data *data)
+{
+ data->sys_regs = syscon_node_to_regmap(data->np->parent);
+ if (IS_ERR(data->sys_regs)) {
+ pr_err("Failed to find syscon regs for '%s'\n",
+ of_node_full_name(data->np));
+ return PTR_ERR(data->sys_regs);
+ }
+
+ return 0;
+}
+
+static struct clk_hw *ccu_div_of_clk_hw_get(struct of_phandle_args *clkspec,
+ void *priv)
+{
+ struct ccu_div_data *data = priv;
+ struct ccu_div *div;
+ unsigned int clk_id;
+
+ clk_id = clkspec->args[0];
+ div = ccu_div_find_desc(data, clk_id);
+ if (IS_ERR(div)) {
+ pr_info("Invalid clock ID %d specified\n", clk_id);
+ return ERR_CAST(div);
+ }
+
+ return ccu_div_get_clk_hw(div);
+}
+
+static int ccu_div_clk_register(struct ccu_div_data *data)
+{
+ int idx, ret;
+
+ for (idx = 0; idx < data->divs_num; ++idx) {
+ const struct ccu_div_info *info = &data->divs_info[idx];
+ struct ccu_div_init_data init = {0};
+
+ init.id = info->id;
+ init.name = info->name;
+ init.parent_name = info->parent_name;
+ init.np = data->np;
+ init.type = info->type;
+ init.flags = info->flags;
+ init.features = info->features;
+
+ if (init.type == CCU_DIV_VAR) {
+ init.base = info->base;
+ init.sys_regs = data->sys_regs;
+ init.width = info->width;
+ } else if (init.type == CCU_DIV_GATE) {
+ init.base = info->base;
+ init.sys_regs = data->sys_regs;
+ init.divider = info->divider;
+ } else {
+ init.divider = info->divider;
+ }
+
+ data->divs[idx] = ccu_div_hw_register(&init);
+ if (IS_ERR(data->divs[idx])) {
+ ret = PTR_ERR(data->divs[idx]);
+ pr_err("Couldn't register divider '%s' hw\n",
+ init.name);
+ goto err_hw_unregister;
+ }
+ }
+
+ ret = of_clk_add_hw_provider(data->np, ccu_div_of_clk_hw_get, data);
+ if (ret) {
+ pr_err("Couldn't register dividers '%s' clock provider\n",
+ of_node_full_name(data->np));
+ goto err_hw_unregister;
+ }
+
+ return 0;
+
+err_hw_unregister:
+ for (--idx; idx >= 0; --idx)
+ ccu_div_hw_unregister(data->divs[idx]);
+
+ return ret;
+}
+
+static void ccu_div_clk_unregister(struct ccu_div_data *data)
+{
+ int idx;
+
+ of_clk_del_provider(data->np);
+
+ for (idx = 0; idx < data->divs_num; ++idx)
+ ccu_div_hw_unregister(data->divs[idx]);
+}
+
+static int ccu_div_rst_register(struct ccu_div_data *data)
+{
+ int ret;
+
+ data->rcdev.ops = &ccu_div_rst_ops;
+ data->rcdev.of_node = data->np;
+ data->rcdev.nr_resets = data->rst_num;
+
+ ret = reset_controller_register(&data->rcdev);
+ if (ret)
+ pr_err("Couldn't register divider '%s' reset controller\n",
+ of_node_full_name(data->np));
+
+ return ret;
+}
+
+static void ccu_div_init(struct device_node *np)
+{
+ struct ccu_div_data *data;
+ int ret;
+
+ data = ccu_div_create_data(np);
+ if (IS_ERR(data))
+ return;
+
+ ret = ccu_div_find_sys_regs(data);
+ if (ret)
+ goto err_free_data;
+
+ ret = ccu_div_clk_register(data);
+ if (ret)
+ goto err_free_data;
+
+ ret = ccu_div_rst_register(data);
+ if (ret)
+ goto err_clk_unregister;
+
+ return;
+
+err_clk_unregister:
+ ccu_div_clk_unregister(data);
+
+err_free_data:
+ ccu_div_free_data(data);
+
+ return;
+}
+
+CLK_OF_DECLARE(ccu_axi, "baikal,bt1-ccu-axi", ccu_div_init);
+CLK_OF_DECLARE(ccu_sys, "baikal,bt1-ccu-sys", ccu_div_init);
--
2.26.2
^ permalink raw reply related
* [PATCH v3 2/4] dt-bindings: clk: Add Baikal-T1 CCU Dividers binding
From: Serge Semin @ 2020-05-26 22:20 UTC (permalink / raw)
To: Thomas Bogendoerfer, Stephen Boyd, Michael Turquette, Rob Herring,
Philipp Zabel
Cc: Serge Semin, Serge Semin, Alexey Malahov, Arnd Bergmann,
linux-mips, linux-clk, devicetree, linux-kernel
In-Reply-To: <20200526222056.18072-1-Sergey.Semin@baikalelectronics.ru>
After being gained by the CCU PLLs the signals must be transformed to
be suitable for the clock-consumers. This is done by a set of dividers
embedded into the CCU. A first block of dividers is used to create
reference clocks for AXI-bus of high-speed peripheral IP-cores of the
chip. The second block dividers alter the PLLs output signals to be then
consumed by SoC peripheral devices. Both block DT nodes are ordinary
clock-providers with standard set of properties supported. But in addition
to that each clock provider can be used to reset the corresponding clock
domain. This makes the AXI-bus and System Devices CCU DT nodes to be also
reset-providers.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: linux-mips@vger.kernel.org
---
Changelog v2:
- Rearrange the SoBs.
- Combine AXI-bus and System Devices CCU bindings into a single file.
- Discard comments in the bindings file header.
- Add dual GPL/BSD license.
- Add spaces around the ASCII-graphics in the binding description.
- Remove reference to Documentation/devicetree/bindings/clock/clock-bindings.txt
file.
- Discard redundant object check against "/schemas/clock/clock.yaml#" schema.
- Discard redundant descriptions of "#clock-cells" and "#reset-cells"
properties.
- Discard "reg" property since the CCU dividers DT nodes are supposed be
children of the syscon-compatible system controller node.
- Remove "clock-output-names" property support.
- Replace "additionalProperties: false" with "unevaluatedProperties: false".
- Lowercase the nodes name in the examples.
- Use "clock-controller" node name suffix in the examples.
- Remove unnecessary comments in the clocks and resets dt-binding header
files.
- Discard label definitions in the examples.
Changelog v3:
- Get the reg property back even though the driver is using the parental
syscon regmap.
- The DT schema will live separately from the system controller, but the
corresponding sub-node of the later DT schema will $ref this one.
---
.../bindings/clock/baikal,bt1-ccu-div.yaml | 188 ++++++++++++++++++
include/dt-bindings/clock/bt1-ccu.h | 32 +++
include/dt-bindings/reset/bt1-ccu.h | 25 +++
3 files changed, 245 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml
create mode 100644 include/dt-bindings/reset/bt1-ccu.h
diff --git a/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml b/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml
new file mode 100644
index 000000000000..2821425ee445
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-div.yaml
@@ -0,0 +1,188 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Baikal-T1 Clock Control Unit Dividers
+
+maintainers:
+ - Serge Semin <fancer.lancer@gmail.com>
+
+description: |
+ Clocks Control Unit is the core of Baikal-T1 SoC System Controller
+ responsible for the chip subsystems clocking and resetting. The CCU is
+ connected with an external fixed rate oscillator, which signal is transformed
+ into clocks of various frequencies and then propagated to either individual
+ IP-blocks or to groups of blocks (clock domains). The transformation is done
+ by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
+ later ones are described in this binding. Each clock domain can be also
+ individually reset by using the domain clocks divider configuration
+ registers. Baikal-T1 CCU is logically divided into the next components:
+ 1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
+ in general can provide any frequency supported by the CCU PLLs).
+ 2) PLLs clocks generators (PLLs).
+ 3) AXI-bus clock dividers (AXI) - described in this binding file.
+ 4) System devices reference clock dividers (SYS) - described in this binding
+ file.
+ which are connected with each other as shown on the next figure:
+
+ +---------------+
+ | Baikal-T1 CCU |
+ | +----+------|- MIPS P5600 cores
+ | +-|PLLs|------|- DDR controller
+ | | +----+ |
+ +----+ | | | | |
+ |XTAL|--|-+ | | +---+-|
+ +----+ | | | +-|AXI|-|- AXI-bus
+ | | | +---+-|
+ | | | |
+ | | +----+---+-|- APB-bus
+ | +-------|SYS|-|- Low-speed Devices
+ | +---+-|- High-speed Devices
+ +---------------+
+
+ Each sub-block is represented as a separate DT node and has an individual
+ driver to be bound with.
+
+ In order to create signals of wide range frequencies the external oscillator
+ output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are
+ then passed over CCU dividers to create signals required for the target clock
+ domain (like AXI-bus or System Device consumers). The dividers have the
+ following structure:
+
+ +--------------+
+ CLKIN --|->+----+ 1|\ |
+ SETCLK--|--|/DIV|->| | |
+ CLKDIV--|--| | | |-|->CLKLOUT
+ LOCK----|--+----+ | | |
+ | |/ |
+ | | |
+ EN------|-----------+ |
+ RST-----|--------------|->RSTOUT
+ +--------------+
+
+ where CLKIN is the reference clock coming either from CCU PLLs or from an
+ external clock oscillator, SETCLK - a command to update the output clock in
+ accordance with a set divider, CLKDIV - clocks divider, LOCK - a signal of
+ the output clock stabilization, EN - enable/disable the divider block,
+ RST/RSTOUT - reset clocks domain signal. Depending on the consumer IP-core
+ peculiarities the dividers may lack of some functionality depicted on the
+ figure above (like EN, CLKDIV/LOCK/SETCLK). In this case the corresponding
+ clock provider just doesn't expose either switching functions, or the rate
+ configuration, or both of them.
+
+ The clock dividers, which output clock is then consumed by the SoC individual
+ devices, are united into a single clocks provider called System Devices CCU.
+ Similarly the dividers with output clocks utilized as AXI-bus reference clocks
+ are called AXI-bus CCU. Both of them use the common clock bindings with no
+ custom properties. The list of exported clocks and reset signals can be found
+ in the files: 'include/dt-bindings/clock/bt1-ccu.h' and
+ 'include/dt-bindings/reset/bt1-ccu.h'. Since System Devices and AXI-bus CCU
+ are a part of the Baikal-T1 SoC System Controller their DT nodes are supposed
+ to be a children of later one.
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: baikal,bt1-ccu-axi
+
+then:
+ properties:
+ clocks:
+ items:
+ - description: CCU SATA PLL output clock
+ - description: CCU PCIe PLL output clock
+ - description: CCU Ethernet PLL output clock
+
+ clock-names:
+ items:
+ - const: sata_clk
+ - const: pcie_clk
+ - const: eth_clk
+
+else:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock
+ - description: CCU SATA PLL output clock
+ - description: CCU PCIe PLL output clock
+ - description: CCU Ethernet PLL output clock
+
+ clock-names:
+ items:
+ - const: ref_clk
+ - const: sata_clk
+ - const: pcie_clk
+ - const: eth_clk
+
+properties:
+ compatible:
+ enum:
+ - baikal,bt1-ccu-axi
+ - baikal,bt1-ccu-sys
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - clock-names
+
+examples:
+ # AXI-bus Clock Control Unit node:
+ - |
+ #include <dt-bindings/clock/bt1-ccu.h>
+
+ clock-controller@1f04d030 {
+ compatible = "baikal,bt1-ccu-axi";
+ reg = <0x1f04d030 0x030>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+
+ clocks = <&ccu_pll CCU_SATA_PLL>,
+ <&ccu_pll CCU_PCIE_PLL>,
+ <&ccu_pll CCU_ETH_PLL>;
+ clock-names = "sata_clk", "pcie_clk", "eth_clk";
+ };
+ # System Devices Clock Control Unit node:
+ - |
+ #include <dt-bindings/clock/bt1-ccu.h>
+
+ clock-controller@1f04d060 {
+ compatible = "baikal,bt1-ccu-sys";
+ reg = <0x1f04d060 0x0a0>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+
+ clocks = <&clk25m>,
+ <&ccu_pll CCU_SATA_PLL>,
+ <&ccu_pll CCU_PCIE_PLL>,
+ <&ccu_pll CCU_ETH_PLL>;
+ clock-names = "ref_clk", "sata_clk", "pcie_clk",
+ "eth_clk";
+ };
+ # Required Clock Control Unit PLL node:
+ - |
+ ccu_pll: clock-controller@1f04d000 {
+ compatible = "baikal,bt1-ccu-pll";
+ reg = <0x1f04d000 0x028>;
+ #clock-cells = <1>;
+
+ clocks = <&clk25m>;
+ clock-names = "ref_clk";
+ };
+...
diff --git a/include/dt-bindings/clock/bt1-ccu.h b/include/dt-bindings/clock/bt1-ccu.h
index 931a4bea67c0..5f166d27a00a 100644
--- a/include/dt-bindings/clock/bt1-ccu.h
+++ b/include/dt-bindings/clock/bt1-ccu.h
@@ -13,4 +13,36 @@
#define CCU_PCIE_PLL 3
#define CCU_ETH_PLL 4
+#define CCU_AXI_MAIN_CLK 0
+#define CCU_AXI_DDR_CLK 1
+#define CCU_AXI_SATA_CLK 2
+#define CCU_AXI_GMAC0_CLK 3
+#define CCU_AXI_GMAC1_CLK 4
+#define CCU_AXI_XGMAC_CLK 5
+#define CCU_AXI_PCIE_M_CLK 6
+#define CCU_AXI_PCIE_S_CLK 7
+#define CCU_AXI_USB_CLK 8
+#define CCU_AXI_HWA_CLK 9
+#define CCU_AXI_SRAM_CLK 10
+
+#define CCU_SYS_SATA_REF_CLK 0
+#define CCU_SYS_APB_CLK 1
+#define CCU_SYS_GMAC0_TX_CLK 2
+#define CCU_SYS_GMAC0_PTP_CLK 3
+#define CCU_SYS_GMAC1_TX_CLK 4
+#define CCU_SYS_GMAC1_PTP_CLK 5
+#define CCU_SYS_XGMAC_REF_CLK 6
+#define CCU_SYS_XGMAC_PTP_CLK 7
+#define CCU_SYS_USB_CLK 8
+#define CCU_SYS_PVT_CLK 9
+#define CCU_SYS_HWA_CLK 10
+#define CCU_SYS_UART_CLK 11
+#define CCU_SYS_I2C1_CLK 12
+#define CCU_SYS_I2C2_CLK 13
+#define CCU_SYS_GPIO_CLK 14
+#define CCU_SYS_TIMER0_CLK 15
+#define CCU_SYS_TIMER1_CLK 16
+#define CCU_SYS_TIMER2_CLK 17
+#define CCU_SYS_WDT_CLK 18
+
#endif /* __DT_BINDINGS_CLOCK_BT1_CCU_H */
diff --git a/include/dt-bindings/reset/bt1-ccu.h b/include/dt-bindings/reset/bt1-ccu.h
new file mode 100644
index 000000000000..3578e83026bc
--- /dev/null
+++ b/include/dt-bindings/reset/bt1-ccu.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
+ *
+ * Baikal-T1 CCU reset indices
+ */
+#ifndef __DT_BINDINGS_RESET_BT1_CCU_H
+#define __DT_BINDINGS_RESET_BT1_CCU_H
+
+#define CCU_AXI_MAIN_RST 0
+#define CCU_AXI_DDR_RST 1
+#define CCU_AXI_SATA_RST 2
+#define CCU_AXI_GMAC0_RST 3
+#define CCU_AXI_GMAC1_RST 4
+#define CCU_AXI_XGMAC_RST 5
+#define CCU_AXI_PCIE_M_RST 6
+#define CCU_AXI_PCIE_S_RST 7
+#define CCU_AXI_USB_RST 8
+#define CCU_AXI_HWA_RST 9
+#define CCU_AXI_SRAM_RST 10
+
+#define CCU_SYS_SATA_REF_RST 0
+#define CCU_SYS_APB_RST 1
+
+#endif /* __DT_BINDINGS_RESET_BT1_CCU_H */
--
2.26.2
^ permalink raw reply related
* [PATCH v3 1/4] dt-bindings: clk: Add Baikal-T1 CCU PLLs binding
From: Serge Semin @ 2020-05-26 22:20 UTC (permalink / raw)
To: Thomas Bogendoerfer, Stephen Boyd, Michael Turquette, Rob Herring
Cc: Serge Semin, Serge Semin, Alexey Malahov, Arnd Bergmann,
linux-mips, linux-clk, devicetree, linux-kernel
In-Reply-To: <20200526222056.18072-1-Sergey.Semin@baikalelectronics.ru>
Baikal-T1 Clocks Control Unit is responsible for transformation of a
signal coming from an external oscillator into clocks of various
frequencies to propagate them then to the corresponding clocks
consumers (either individual IP-blocks or clock domains). In order
to create a set of high-frequency clocks the external signal is
firstly handled by the embedded into CCU PLLs. So the corresponding
dts-node is just a normal clock-provider node with standard set of
properties. Note as being part of the Baikal-T1 System Controller its
DT node is supposed to be a child the system controller node.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: linux-mips@vger.kernel.org
---
Changelog v2:
- Rearrange the SoBs.
- Discard comments in the bindings file header.
- Add dual GPL/BSD license.
- Add spaces around the ASCII-graphics in the binding description.
- Remove reference to Documentation/devicetree/bindings/clock/clock-bindings.txt
file.
- Discard redundant object check against "/schemas/clock/clock.yaml#" schema.
- Discard redundant descriptions of the "#clock-cells" property.
- Remove "reg" property since from now the clock DT node is supposed to be
a child of the syscon-compatible system controller node.
- Remove "clock-output-names" property support.
- Replace "additionalProperties: false" with "unevaluatedProperties: false".
- Lowercase the nodes name in the examples.
- Use "clock-controller" node name suffix in the examples.
- Remove unnecessary comments in the clocks dt-bindings header file.
Changelog v3:
- Get the reg property back even though the driver is using the parental
syscon regmap.
- The DT schema will live separately from the system controller, but the
corresponding sub-node of the later DT schema will $ref this one.
---
.../bindings/clock/baikal,bt1-ccu-pll.yaml | 131 ++++++++++++++++++
include/dt-bindings/clock/bt1-ccu.h | 16 +++
2 files changed, 147 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml
create mode 100644 include/dt-bindings/clock/bt1-ccu.h
diff --git a/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml b/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml
new file mode 100644
index 000000000000..97131bfa6f87
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/baikal,bt1-ccu-pll.yaml
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Baikal-T1 Clock Control Unit PLL
+
+maintainers:
+ - Serge Semin <fancer.lancer@gmail.com>
+
+description: |
+ Clocks Control Unit is the core of Baikal-T1 SoC System Controller
+ responsible for the chip subsystems clocking and resetting. The CCU is
+ connected with an external fixed rate oscillator, which signal is transformed
+ into clocks of various frequencies and then propagated to either individual
+ IP-blocks or to groups of blocks (clock domains). The transformation is done
+ by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
+ It's logically divided into the next components:
+ 1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
+ in general can provide any frequency supported by the CCU PLLs).
+ 2) PLLs clocks generators (PLLs) - described in this binding file.
+ 3) AXI-bus clock dividers (AXI).
+ 4) System devices reference clock dividers (SYS).
+ which are connected with each other as shown on the next figure:
+
+ +---------------+
+ | Baikal-T1 CCU |
+ | +----+------|- MIPS P5600 cores
+ | +-|PLLs|------|- DDR controller
+ | | +----+ |
+ +----+ | | | | |
+ |XTAL|--|-+ | | +---+-|
+ +----+ | | | +-|AXI|-|- AXI-bus
+ | | | +---+-|
+ | | | |
+ | | +----+---+-|- APB-bus
+ | +-------|SYS|-|- Low-speed Devices
+ | +---+-|- High-speed Devices
+ +---------------+
+
+ Each CCU sub-block is represented as a separate dts-node and has an
+ individual driver to be bound with.
+
+ In order to create signals of wide range frequencies the external oscillator
+ output is primarily connected to a set of CCU PLLs. There are five PLLs
+ to create a clock for the MIPS P5600 cores, the embedded DDR controller,
+ SATA, Ethernet and PCIe domains. The last three domains though named by the
+ biggest system interfaces in fact include nearly all of the rest SoC
+ peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core
+ with an interface wrapper (so called safe PLL' clocks switcher) to simplify
+ the PLL configuration procedure. The PLLs work as depicted on the next
+ diagram:
+
+ +--------------------------+
+ | |
+ +-->+---+ +---+ +---+ | +---+ 0|\
+ CLKF--->|/NF|--->|PFD|...|VCO|-+->|/OD|--->| |
+ +---+ +->+---+ +---+ /->+---+ | |--->CLKOUT
+ CLKOD---------C----------------+ 1| |
+ +--------C--------------------------->|/
+ | | ^
+ Rclk-+->+---+ | |
+ CLKR--->|/NR|-+ |
+ +---+ |
+ BYPASS--------------------------------------+
+ BWADJ--->
+
+ where Rclk is the reference clock coming from XTAL, NR - reference clock
+ divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -
+ output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment
+ the binding supports the PLL dividers configuration in accordance with a
+ requested rate, while bypassing and bandwidth adjustment settings can be
+ added in future if it gets to be necessary.
+
+ The PLLs CLKOUT is then either directly connected with the corresponding
+ clocks consumer (like P5600 cores or DDR controller) or passed over a CCU
+ divider to create a signal required for the clock domain.
+
+ The CCU PLL dts-node uses the common clock bindings with no custom
+ parameters. The list of exported clocks can be found in
+ 'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the
+ Baikal-T1 SoC System Controller its DT node is supposed to be a child of
+ later one.
+
+properties:
+ compatible:
+ const: baikal,bt1-ccu-pll
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ clocks:
+ description: External reference clock
+ maxItems: 1
+
+ clock-names:
+ const: ref_clk
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - clock-names
+
+examples:
+ # Clock Control Unit PLL node:
+ - |
+ clock-controller@1f04d000 {
+ compatible = "baikal,bt1-ccu-pll";
+ reg = <0x1f04d000 0x028>;
+ #clock-cells = <1>;
+
+ clocks = <&clk25m>;
+ clock-names = "ref_clk";
+ };
+ # Required external oscillator:
+ - |
+ clk25m: clock-oscillator-25m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ clock-output-names = "clk25m";
+ };
+...
diff --git a/include/dt-bindings/clock/bt1-ccu.h b/include/dt-bindings/clock/bt1-ccu.h
new file mode 100644
index 000000000000..931a4bea67c0
--- /dev/null
+++ b/include/dt-bindings/clock/bt1-ccu.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
+ *
+ * Baikal-T1 CCU clock indices
+ */
+#ifndef __DT_BINDINGS_CLOCK_BT1_CCU_H
+#define __DT_BINDINGS_CLOCK_BT1_CCU_H
+
+#define CCU_CPU_PLL 0
+#define CCU_SATA_PLL 1
+#define CCU_DDR_PLL 2
+#define CCU_PCIE_PLL 3
+#define CCU_ETH_PLL 4
+
+#endif /* __DT_BINDINGS_CLOCK_BT1_CCU_H */
--
2.26.2
^ permalink raw reply related
* Re: [PATCH v6 2/3] dt-bindings: drm/bridge: ti-sn65dsi86: Convert to yaml
From: Rob Herring @ 2020-05-26 22:08 UTC (permalink / raw)
To: Douglas Anderson
Cc: daniel, linux-arm-msm, jonas, linus.walleij, devicetree,
dri-devel, robh+dt, Paul Walmsley, a.hajda, narmstrong,
Laurent Pinchart, linux-gpio, Krzysztof Kozlowski, robdclark,
jeffrey.l.hugo, jernej.skrabec, airlied, spanda, Laurent.pinchart,
swboyd, bgolaszewski, bjorn.andersson, linux-kernel
In-Reply-To: <20200513145807.v6.2.Ifcdc4ecb12742a27862744ee1e8753cb95a38a7f@changeid>
On Wed, 13 May 2020 14:59:01 -0700, Douglas Anderson wrote:
> This moves the bindings over, based a lot on toshiba,tc358768.yaml.
> Unless there's someone known to be better, I've set the maintainer in
> the yaml as the first person to submit bindings.
>
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
> ---
> I removed Stephen's review tag on v5 since I squashed in a bunch of
> other stuff.
>
> Changes in v6: None
> Changes in v5:
> - Squash https://lore.kernel.org/r/20200506140208.v2.2.I0a2bca02b09c1fcb6b09479b489736d600b3e57f@changeid/
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - specification => specifier.
> - power up => power.
> - Added back missing suspend-gpios.
> - data-lanes and lane-polarities are are the right place now.
> - endpoints don't need to be patternProperties.
> - Specified more details for data-lanes and lane-polarities.
> - Added old example back in, fixing bugs in it.
> - Example i2c bus is just called "i2c", not "i2c1" now.
>
> .../bindings/display/bridge/ti,sn65dsi86.txt | 87 ------
> .../bindings/display/bridge/ti,sn65dsi86.yaml | 285 ++++++++++++++++++
> 2 files changed, 285 insertions(+), 87 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt
> create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v7 2/2] dt-bindings: usb: qcom,dwc3: Add compatible for SC7180
From: Rob Herring @ 2020-05-26 22:04 UTC (permalink / raw)
To: Sandeep Maheswaram
Cc: Andy Gross, Bjorn Andersson, Greg Kroah-Hartman, Mark Rutland,
Felipe Balbi, Stephen Boyd, Doug Anderson, Matthias Kaehlcke,
linux-arm-msm, linux-usb, devicetree, linux-kernel, Manu Gautam
In-Reply-To: <1590075499-21350-3-git-send-email-sanm@codeaurora.org>
On Thu, May 21, 2020 at 09:08:19PM +0530, Sandeep Maheswaram wrote:
> Add compatible for SC7180 in usb dwc3 bindings.
>
> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
> Reviewed-by: Douglas Anderson <dianders@chromium.org>
> Acked-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
> ---
> Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 1 +
> 1 file changed, 1 insertion(+)
Applied, thanks!
^ permalink raw reply
* Re: [PATCH v7 1/2] dt-bindings: usb: qcom,dwc3: Convert USB DWC3 bindings
From: Rob Herring @ 2020-05-26 22:02 UTC (permalink / raw)
To: Sandeep Maheswaram
Cc: Matthias Kaehlcke, Bjorn Andersson, linux-arm-msm, devicetree,
Doug Anderson, Manu Gautam, linux-kernel, Mark Rutland, linux-usb,
Greg Kroah-Hartman, Felipe Balbi, Stephen Boyd, Andy Gross,
Rob Herring
In-Reply-To: <1590075499-21350-2-git-send-email-sanm@codeaurora.org>
On Thu, 21 May 2020 21:08:18 +0530, Sandeep Maheswaram wrote:
> Convert USB DWC3 bindings to DT schema format using json-schema.
>
> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
> ---
> .../devicetree/bindings/usb/qcom,dwc3.txt | 104 -------------
> .../devicetree/bindings/usb/qcom,dwc3.yaml | 167 +++++++++++++++++++++
> 2 files changed, 167 insertions(+), 104 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/usb/qcom,dwc3.txt
> create mode 100644 Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH v2 09/14] device core: Add ability to handle multiple dma offsets
From: Jim Quinlan @ 2020-05-26 22:01 UTC (permalink / raw)
To: Andy Shevchenko
Cc: open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS,
Christoph Hellwig, Nicolas Saenz Julienne,
maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE, Rob Herring,
Frank Rowand, Greg Kroah-Hartman, Marek Szyprowski, Robin Murphy,
Alan Stern, Oliver Neukum, Rafael J. Wysocki, Wolfram Sang,
Corey Minyard, Srinivas Kandagatla, Suzuki K Poulose,
Saravana Kannan, Heikki Krogerus, Dan Williams,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE, open list,
open list:USB SUBSYSTEM, open list:DMA MAPPING HELPERS
In-Reply-To: <20200526205448.GA1634618@smile.fi.intel.com>
Hello Andy,
On Tue, May 26, 2020 at 4:54 PM Andy Shevchenko
<andriy.shevchenko@linux.intel.com> wrote:
>
> On Tue, May 26, 2020 at 03:12:48PM -0400, Jim Quinlan wrote:
> > The new field in struct device 'dma_pfn_offset_map' is used to facilitate
> > the use of multiple pfn offsets between cpu addrs and dma addrs. It is
> > similar to 'dma_pfn_offset' except that the offset chosen depends on the
> > cpu or dma address involved.
> >
> > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> > ---
> > drivers/of/address.c | 65 +++++++++++++++++++++++++++++++++++--
> > drivers/usb/core/message.c | 3 ++
> > drivers/usb/core/usb.c | 3 ++
> > include/linux/device.h | 10 +++++-
> > include/linux/dma-direct.h | 10 ++++--
> > include/linux/dma-mapping.h | 46 ++++++++++++++++++++++++++
> > kernel/dma/Kconfig | 13 ++++++++
> > 7 files changed, 144 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/of/address.c b/drivers/of/address.c
> > index 96d8cfb14a60..a01afffcde7d 100644
> > --- a/drivers/of/address.c
> > +++ b/drivers/of/address.c
> > @@ -918,6 +918,47 @@ void __iomem *of_io_request_and_map(struct device_node *np, int index,
> > }
> > EXPORT_SYMBOL(of_io_request_and_map);
> >
> > +#ifdef CONFIG_DMA_PFN_OFFSET_MAP
> > +static int attach_dma_pfn_offset_map(struct device *dev,
> > + struct device_node *node, int num_ranges)
> > +{
> > + struct of_range_parser parser;
> > + struct of_range range;
> > + size_t r_size = (num_ranges + 1)
> > + * sizeof(struct dma_pfn_offset_region);
> > + struct dma_pfn_offset_region *r;
> > +
>
> > + r = devm_kzalloc(dev, r_size, GFP_KERNEL);
>
> devm_?!
Yes, otherwise if the device gets unbound/bound repeatedly then there
would be a memory leak.
>
>
> Looking at r_size it should be rather kcalloc().
Yep.
>
>
> > + if (!r)
> > + return -ENOMEM;
> > + dev->dma_pfn_offset_map = r;
> > + of_dma_range_parser_init(&parser, node);
> > +
> > + /*
> > + * Record all info for DMA ranges array. We could
> > + * just use the of_range struct, but if we did that it
> > + * would require more calculations for phys_to_dma and
> > + * dma_to_phys conversions.
> > + */
> > + for_each_of_range(&parser, &range) {
> > + r->cpu_beg = range.cpu_addr;
> > + r->cpu_end = r->cpu_beg + range.size;
> > + r->dma_beg = range.bus_addr;
> > + r->dma_end = r->dma_beg + range.size;
> > + r->pfn_offset = PFN_DOWN(range.cpu_addr)
> > + - PFN_DOWN(range.bus_addr);
> > + r++;
> > + }
> > + return 0;
> > +}
> > +#else
> > +static int attach_dma_pfn_offset_map(struct device *dev,
> > + struct device_node *node, int num_ranges)
> > +{
> > + return 0;
> > +}
> > +#endif
> > +
> > /**
> > * of_dma_get_range - Get DMA range info
> > * @dev: device pointer; only needed for a corner case.
> > @@ -947,6 +988,8 @@ int of_dma_get_range(struct device *dev, struct device_node *np, u64 *dma_addr,
> > struct of_range_parser parser;
> > struct of_range range;
> > u64 dma_start = U64_MAX, dma_end = 0, dma_offset = 0;
> > + bool dma_multi_pfn_offset = false;
> > + int num_ranges = 0;
> >
> > while (node) {
> > ranges = of_get_property(node, "dma-ranges", &len);
> > @@ -977,10 +1020,19 @@ int of_dma_get_range(struct device *dev, struct device_node *np, u64 *dma_addr,
> > pr_debug("dma_addr(%llx) cpu_addr(%llx) size(%llx)\n",
> > range.bus_addr, range.cpu_addr, range.size);
> >
> > + num_ranges++;
> > if (dma_offset && range.cpu_addr - range.bus_addr != dma_offset) {
> > - pr_warn("Can't handle multiple dma-ranges with different offsets on node(%pOF)\n", node);
> > - /* Don't error out as we'd break some existing DTs */
> > - continue;
> > + if (!IS_ENABLED(CONFIG_DMA_PFN_OFFSET_MAP)) {
> > + pr_warn("Can't handle multiple dma-ranges with different offsets on node(%pOF)\n", node);
> > + pr_warn("Perhaps set DMA_PFN_OFFSET_MAP=y?\n");
> > + /*
> > + * Don't error out as we'd break some existing
> > + * DTs that are using configs w/o
> > + * CONFIG_DMA_PFN_OFFSET_MAP set.
> > + */
> > + continue;
> > + }
> > + dma_multi_pfn_offset = true;
> > }
> > dma_offset = range.cpu_addr - range.bus_addr;
> >
> > @@ -991,6 +1043,13 @@ int of_dma_get_range(struct device *dev, struct device_node *np, u64 *dma_addr,
> > dma_end = range.bus_addr + range.size;
> > }
> >
> > + if (dma_multi_pfn_offset) {
> > + dma_offset = 0;
> > + ret = attach_dma_pfn_offset_map(dev, node, num_ranges);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > if (dma_start >= dma_end) {
> > ret = -EINVAL;
> > pr_debug("Invalid DMA ranges configuration on node(%pOF)\n",
> > diff --git a/drivers/usb/core/message.c b/drivers/usb/core/message.c
> > index 6197938dcc2d..aaa3e58f5eb4 100644
> > --- a/drivers/usb/core/message.c
> > +++ b/drivers/usb/core/message.c
> > @@ -1960,6 +1960,9 @@ int usb_set_configuration(struct usb_device *dev, int configuration)
> > */
> > intf->dev.dma_mask = dev->dev.dma_mask;
> > intf->dev.dma_pfn_offset = dev->dev.dma_pfn_offset;
> > +#ifdef CONFIG_DMA_PFN_OFFSET_MAP
> > + intf->dev.dma_pfn_offset_map = dev->dev.dma_pfn_offset_map;
> > +#endif
> > INIT_WORK(&intf->reset_ws, __usb_queue_reset_device);
> > intf->minor = -1;
> > device_initialize(&intf->dev);
> > diff --git a/drivers/usb/core/usb.c b/drivers/usb/core/usb.c
> > index f16c26dc079d..d2ed4d90e56e 100644
> > --- a/drivers/usb/core/usb.c
> > +++ b/drivers/usb/core/usb.c
> > @@ -612,6 +612,9 @@ struct usb_device *usb_alloc_dev(struct usb_device *parent,
> > */
> > dev->dev.dma_mask = bus->sysdev->dma_mask;
> > dev->dev.dma_pfn_offset = bus->sysdev->dma_pfn_offset;
> > +#ifdef CONFIG_DMA_PFN_OFFSET_MAP
> > + dev->dev.dma_pfn_offset_map = bus->sysdev->dma_pfn_offset_map;
> > +#endif
> > set_dev_node(&dev->dev, dev_to_node(bus->sysdev));
> > dev->state = USB_STATE_ATTACHED;
> > dev->lpm_disable_count = 1;
> > diff --git a/include/linux/device.h b/include/linux/device.h
> > index ac8e37cd716a..67a240ad4fc5 100644
> > --- a/include/linux/device.h
> > +++ b/include/linux/device.h
> > @@ -493,6 +493,8 @@ struct dev_links_info {
> > * @bus_dma_limit: Limit of an upstream bridge or bus which imposes a smaller
> > * DMA limit than the device itself supports.
> > * @dma_pfn_offset: offset of DMA memory range relatively of RAM
> > + * @dma_pfn_offset_map: Like dma_pfn_offset but used when there are multiple
> > + * pfn offsets for multiple dma-ranges.
> > * @dma_parms: A low level driver may set these to teach IOMMU code about
> > * segment limitations.
> > * @dma_pools: Dma pools (if dma'ble device).
> > @@ -578,7 +580,13 @@ struct device {
> > allocations such descriptors. */
> > u64 bus_dma_limit; /* upstream dma constraint */
> > unsigned long dma_pfn_offset;
> > -
> > +#ifdef CONFIG_DMA_PFN_OFFSET_MAP
> > + const struct dma_pfn_offset_region *dma_pfn_offset_map;
>
> > + /* Like dma_pfn_offset, but for
> > + * the unlikely case of multiple
> > + * offsets. If non-null, dma_pfn_offset
> > + * will be set to 0. */
>
> A bit harder to read comment indented too much and located after the declared variable.
Okay, will change. I was trying to keep the comment style of the other
variables.
> > +#endif
> > struct device_dma_parameters *dma_parms;
> >
> > struct list_head dma_pools; /* dma pools (if dma'ble) */
> > diff --git a/include/linux/dma-direct.h b/include/linux/dma-direct.h
> > index 24b8684aa21d..03110a57eabc 100644
> > --- a/include/linux/dma-direct.h
> > +++ b/include/linux/dma-direct.h
> > @@ -14,15 +14,21 @@ extern unsigned int zone_dma_bits;
> > static inline dma_addr_t __phys_to_dma(struct device *dev, phys_addr_t paddr)
> > {
> > dma_addr_t dev_addr = (dma_addr_t)paddr;
> > + /* The compiler should remove the 2nd term if !DMA_PFN_OFFSET_MAP */
> > + unsigned long dma_pfn_offset = dev->dma_pfn_offset
> > + + dma_pfn_offset_from_phys_addr(dev, paddr);
> >
> > - return dev_addr - ((dma_addr_t)dev->dma_pfn_offset << PAGE_SHIFT);
> > + return dev_addr - ((dma_addr_t)dma_pfn_offset << PAGE_SHIFT);
> > }
> >
> > static inline phys_addr_t __dma_to_phys(struct device *dev, dma_addr_t dev_addr)
> > {
> > phys_addr_t paddr = (phys_addr_t)dev_addr;
> > + /* The compiler should remove the 2nd term if !DMA_PFN_OFFSET_MAP */
> > + unsigned long dma_pfn_offset = dev->dma_pfn_offset
> > + + dma_pfn_offset_from_dma_addr(dev, paddr);
> >
> > - return paddr + ((phys_addr_t)dev->dma_pfn_offset << PAGE_SHIFT);
> > + return paddr + ((phys_addr_t)dma_pfn_offset << PAGE_SHIFT);
> > }
> > #endif /* !CONFIG_ARCH_HAS_PHYS_TO_DMA */
> >
> > diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
> > index 330ad58fbf4d..91940bba2229 100644
> > --- a/include/linux/dma-mapping.h
> > +++ b/include/linux/dma-mapping.h
> > @@ -256,6 +256,52 @@ static inline void dma_direct_sync_sg_for_cpu(struct device *dev,
> > size_t dma_direct_max_mapping_size(struct device *dev);
> >
> > #ifdef CONFIG_HAS_DMA
> > +#ifdef CONFIG_DMA_PFN_OFFSET_MAP
> > +struct dma_pfn_offset_region {
>
> > + phys_addr_t cpu_beg;
> > + phys_addr_t cpu_end;
> > + dma_addr_t dma_beg;
> > + dma_addr_t dma_end;
>
> Perhaps
> s,beg,start,
> in above names
>
Okay.
>
> > + unsigned long pfn_offset;
> > +};
> > +
> > +static inline unsigned long dma_pfn_offset_from_dma_addr(struct device *dev,
> > + dma_addr_t dma_addr)
> > +{
> > + const struct dma_pfn_offset_region *m = dev->dma_pfn_offset_map;
>
> > + if (m)
> > + for (; m->cpu_end; m++)
>
> Why not simple
>
> while (m) {
> ...
> }
>
> ?
>
That won't work; 'm' is either null or a valid pointer to an array
which has an additional entry that is 0-filled.. If non-null, 'm'
will never turn into NULL via 'm++' and the while loop will not
terminate.
>
>
> > + if (dma_addr >= m->dma_beg && dma_addr < m->dma_end)
> > + return m->pfn_offset;
> > + return 0;
> > +}
> > +
> > +static inline unsigned long dma_pfn_offset_from_phys_addr(struct device *dev,
> > + phys_addr_t paddr)
> > +{
> > + const struct dma_pfn_offset_region *m = dev->dma_pfn_offset_map;
> > +
>
> > + if (m)
> > + for (; m->cpu_end; m++)
>
> Ditto.
>
> > + if (paddr >= m->cpu_beg && paddr < m->cpu_end)
> > + return m->pfn_offset;
> > + return 0;
> > +}
> > +#else /* CONFIG_DMA_PFN_OFFSET_MAP */
> > +static inline unsigned long dma_pfn_offset_from_dma_addr(struct device *dev,
> > + dma_addr_t dma_addr)
> > +{
> > + return 0;
> > +}
> > +
> > +static inline unsigned long dma_pfn_offset_from_phys_addr(struct device *dev,
> > + phys_addr_t paddr)
> > +{
> > + return 0;
> > +}
> > +#endif /* CONFIG_DMA_PFN_OFFSET_MAP */
> > +
> > #include <asm/dma-mapping.h>
> >
> > static inline const struct dma_map_ops *get_dma_ops(struct device *dev)
> > diff --git a/kernel/dma/Kconfig b/kernel/dma/Kconfig
> > index 4c103a24e380..ceb7e5e8f501 100644
> > --- a/kernel/dma/Kconfig
> > +++ b/kernel/dma/Kconfig
> > @@ -195,3 +195,16 @@ config DMA_API_DEBUG_SG
> > is technically out-of-spec.
> >
> > If unsure, say N.
> > +
> > +config DMA_PFN_OFFSET_MAP
> > + bool "Uses a DMA range map to calculate PFN offset"
> > + depends on PCIE_BRCMSTB
>
> > + default n
>
> Redundant.
Okay.
>
> > + help
> > + Some devices have a dma-range that gets converted to
> > + a dev->dma_pfn_offset value. This option is for the
> > + atypical case of there being multiple dma-ranges requiring
> > + multiple pfn offsets, which are selected from when
> > + converting to phys to dma and vice versa.
> > +
> > + If unsure, say N.
> > --
> > 2.17.1
> >
>
> --
> With Best Regards,
> Andy Shevchenko
Thanks!
Jim Quinlan
^ permalink raw reply
* Re: [Patch 2/2] media: ti-vpe: Add the VIP driver
From: Benoit Parrot @ 2020-05-26 21:57 UTC (permalink / raw)
To: Hans Verkuil
Cc: Rob Herring, linux-media, devicetree, linux-kernel,
Nikhil Devshatwar
In-Reply-To: <6155dc6e-0899-fc66-dc5c-2f7cd5e23dae@xs4all.nl>
Hans,
Thanks for the review.
Hans Verkuil <hverkuil@xs4all.nl> wrote on Tue [2020-May-26 13:48:35 +0200]:
> On 23/05/2020 00:54, Benoit Parrot wrote:
> > VIP stands for Video Input Port, it can be found on devices such as
> > DRA7xx and provides a parallel interface to a video source such as
> > a sensor or TV decoder. Each VIP can support two inputs (slices) and
> > a SoC can be configured with a variable number of VIP's.
> > Each slice can supports two ports each connected to its own
> > sub-device.
> >
> > Signed-off-by: Benoit Parrot <bparrot@ti.com>
> > Signed-off-by: Nikhil Devshatwar <nikhil.nd@ti.com>
> > ---
> > drivers/media/platform/Kconfig | 13 +
> > drivers/media/platform/ti-vpe/Makefile | 2 +
> > drivers/media/platform/ti-vpe/vip.c | 4158 ++++++++++++++++++++++++
> > drivers/media/platform/ti-vpe/vip.h | 724 +++++
> > 4 files changed, 4897 insertions(+)
> > create mode 100644 drivers/media/platform/ti-vpe/vip.c
> > create mode 100644 drivers/media/platform/ti-vpe/vip.h
> >
> > diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
> > index c57ee78fa99d..f4100a1aad58 100644
> > --- a/drivers/media/platform/Kconfig
> > +++ b/drivers/media/platform/Kconfig
> > @@ -168,6 +168,19 @@ config VIDEO_TI_CAL
> > In TI Technical Reference Manual this module is referred as
> > Camera Interface Subsystem (CAMSS).
> >
> > +config VIDEO_TI_VIP
> > + tristate "TI Video Input Port"
> > + default n
> > + depends on VIDEO_DEV && VIDEO_V4L2 && SOC_DRA7XX
> > + depends on HAS_DMA
> > + select VIDEOBUF2_DMA_CONTIG
> > + select VIDEO_TI_VPDMA
> > + select VIDEO_TI_SC
> > + select VIDEO_TI_CSC
> > + help
> > + Driver support for VIP module on certain TI SoC's
> > + VIP = Video Input Port.
> > +
> > endif # V4L_PLATFORM_DRIVERS
> >
> > menuconfig V4L_MEM2MEM_DRIVERS
> > diff --git a/drivers/media/platform/ti-vpe/Makefile b/drivers/media/platform/ti-vpe/Makefile
> > index 886ac5ec073f..cdbecadf7191 100644
> > --- a/drivers/media/platform/ti-vpe/Makefile
> > +++ b/drivers/media/platform/ti-vpe/Makefile
> > @@ -3,11 +3,13 @@ obj-$(CONFIG_VIDEO_TI_VPE) += ti-vpe.o
> > obj-$(CONFIG_VIDEO_TI_VPDMA) += ti-vpdma.o
> > obj-$(CONFIG_VIDEO_TI_SC) += ti-sc.o
> > obj-$(CONFIG_VIDEO_TI_CSC) += ti-csc.o
> > +obj-$(CONFIG_VIDEO_TI_VIP) += ti-vip.o
> >
> > ti-vpe-y := vpe.o
> > ti-vpdma-y := vpdma.o
> > ti-sc-y := sc.o
> > ti-csc-y := csc.o
> > +ti-vip-y := vip.o
> >
> > ccflags-$(CONFIG_VIDEO_TI_VPE_DEBUG) += -DDEBUG
> >
> > diff --git a/drivers/media/platform/ti-vpe/vip.c b/drivers/media/platform/ti-vpe/vip.c
> > new file mode 100644
> > index 000000000000..307b01851a14
> > --- /dev/null
> > +++ b/drivers/media/platform/ti-vpe/vip.c
> > @@ -0,0 +1,4158 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * TI VIP capture driver
> > + *
> > + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
> > + * David Griego, <dagriego@biglakesoftware.com>
> > + * Dale Farnsworth, <dale@farnsworth.org>
> > + * Nikhil Devshatwar, <nikhil.nd@ti.com>
> > + * Benoit Parrot, <bparrot@ti.com>
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/delay.h>
> > +#include <linux/dma-mapping.h>
> > +#include <linux/err.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/module.h>
> > +#include <linux/workqueue.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/sched.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/regmap.h>
> > +
> > +#include <linux/pinctrl/consumer.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_graph.h>
> > +
> > +#include "vip.h"
> > +
> > +#define VIP_MODULE_NAME "vip"
> > +
> > +static int debug;
> > +module_param(debug, int, 0644);
> > +MODULE_PARM_DESC(debug, "debug level (0-8)");
> > +
> > +/*
> > + * Minimum and maximum frame sizes
> > + */
> > +#define MIN_W 128
> > +#define MIN_H 128
> > +#define MAX_W 2048
> > +#define MAX_H 1536
> > +
> > +/*
> > + * Required alignments
> > + */
> > +#define S_ALIGN 0 /* multiple of 1 */
> > +#define H_ALIGN 1 /* multiple of 2 */
> > +#define W_ALIGN 1 /* multiple of 2 */
> > +#define L_ALIGN 7 /* multiple of 128, line stride, 16 bytes */
> > +
> > +/*
> > + * Need a descriptor entry for each of up to 15 outputs,
> > + * and up to 2 control transfers.
> > + */
> > +#define VIP_DESC_LIST_SIZE (17 * sizeof(struct vpdma_dtd))
> > +
> > +#define vip_dbg(level, dev, fmt, arg...) \
> > + v4l2_dbg(level, debug, dev, fmt, ##arg)
> > +#define vip_err(dev, fmt, arg...) \
> > + v4l2_err(dev, fmt, ##arg)
> > +#define vip_warn(dev, fmt, arg...) \
> > + v4l2_err(dev, fmt, ##arg)
> > +#define vip_info(dev, fmt, arg...) \
> > + v4l2_info(dev, fmt, ##arg)
>
> These defines are just aliases. Any reason for not just using v4l2_info etc.?
Yeah at some point the macros were abstracting the &dev->v4l2_dev but not
any longeri since I figured out they are only using the ->name member, so I
guess I could remove them.
>
> > +
> > +#define CTRL_CORE_SMA_SW_1 0x534
> > +/*
> > + * The srce_info structure contains per-srce data.
> > + */
> > +struct vip_srce_info {
> > + u8 base_channel; /* the VPDMA channel nummber */
> > + u8 vb_index; /* input frame f, f-1, f-2 index */
> > + u8 vb_part; /* identifies section of co-planar formats */
> > +};
> > +
> > +#define VIP_VPDMA_FIFO_SIZE 2
> > +#define VIP_DROPQ_SIZE 3
> > +
> > +/*
> > + * Define indices into the srce_info tables
> > + */
> > +
> > +#define VIP_SRCE_MULT_PORT 0
> > +#define VIP_SRCE_MULT_ANC 1
> > +#define VIP_SRCE_LUMA 2
> > +#define VIP_SRCE_CHROMA 3
> > +#define VIP_SRCE_RGB 4
> > +
> > +static struct vip_srce_info srce_info[5] = {
> > + [VIP_SRCE_MULT_PORT] = {
> > + .base_channel = VIP1_CHAN_NUM_MULT_PORT_A_SRC0,
> > + .vb_index = 0,
> > + .vb_part = VIP_CHROMA,
> > + },
> > + [VIP_SRCE_MULT_ANC] = {
> > + .base_channel = VIP1_CHAN_NUM_MULT_ANC_A_SRC0,
> > + .vb_index = 0,
> > + .vb_part = VIP_LUMA,
> > + },
> > + [VIP_SRCE_LUMA] = {
> > + .base_channel = VIP1_CHAN_NUM_PORT_A_LUMA,
> > + .vb_index = 1,
> > + .vb_part = VIP_LUMA,
> > + },
> > + [VIP_SRCE_CHROMA] = {
> > + .base_channel = VIP1_CHAN_NUM_PORT_A_CHROMA,
> > + .vb_index = 1,
> > + .vb_part = VIP_CHROMA,
> > + },
> > + [VIP_SRCE_RGB] = {
> > + .base_channel = VIP1_CHAN_NUM_PORT_A_RGB,
> > + .vb_part = VIP_LUMA,
> > + },
> > +};
> > +
> > +static struct vip_fmt vip_formats[VIP_MAX_ACTIVE_FMT] = {
> > + {
> > + .fourcc = V4L2_PIX_FMT_NV12,
> > + .code = MEDIA_BUS_FMT_UYVY8_2X8,
> > + .colorspace = V4L2_COLORSPACE_SMPTE170M,
>
> Colorspace information should come from the subdev (sensor or video receiver).
>
> You really don't know what the colorspace is here.
Ah yes, this has been here for a long time...
I'll clean it up.
>
> > + .coplanar = 1,
> > + .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y420],
> > + &vpdma_yuv_fmts[VPDMA_DATA_FMT_C420],
> > + },
> > + },
> > + {
> > + .fourcc = V4L2_PIX_FMT_UYVY,
> > + .code = MEDIA_BUS_FMT_UYVY8_2X8,
> > + .colorspace = V4L2_COLORSPACE_SMPTE170M,
> > + .coplanar = 0,
> > + .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_CBY422],
> > + },
> > + },
> > + {
> > + .fourcc = V4L2_PIX_FMT_YUYV,
> > + .code = MEDIA_BUS_FMT_UYVY8_2X8,
> > + .colorspace = V4L2_COLORSPACE_SMPTE170M,
> > + .coplanar = 0,
> > + .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_YCB422],
> > + },
> > + },
> > + {
> > + .fourcc = V4L2_PIX_FMT_VYUY,
> > + .code = MEDIA_BUS_FMT_UYVY8_2X8,
> > + .colorspace = V4L2_COLORSPACE_SMPTE170M,
> > + .coplanar = 0,
> > + .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_CRY422],
> > + },
> > + },
> > + {
> > + .fourcc = V4L2_PIX_FMT_YVYU,
> > + .code = MEDIA_BUS_FMT_UYVY8_2X8,
> > + .colorspace = V4L2_COLORSPACE_SMPTE170M,
> > + .coplanar = 0,
> > + .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_YCR422],
> > + },
> > + },
> > + {
> > + .fourcc = V4L2_PIX_FMT_RGB24,
> > + .code = MEDIA_BUS_FMT_UYVY8_2X8,
> > + .colorspace = V4L2_COLORSPACE_SRGB,
> > + .coplanar = 0,
> > + .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB24],
> > + },
> > + },
> > + {
> > + .fourcc = V4L2_PIX_FMT_RGB32,
> > + .code = MEDIA_BUS_FMT_UYVY8_2X8,
> > + .colorspace = V4L2_COLORSPACE_SRGB,
> > + .coplanar = 0,
> > + .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ARGB32],
> > + },
> > + },
> > + {
> > + .fourcc = V4L2_PIX_FMT_BGR24,
> > + .code = MEDIA_BUS_FMT_UYVY8_2X8,
> > + .colorspace = V4L2_COLORSPACE_SRGB,
> > + .coplanar = 0,
> > + .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_BGR24],
> > + },
> > + },
> > + {
> > + .fourcc = V4L2_PIX_FMT_BGR32,
> > + .code = MEDIA_BUS_FMT_UYVY8_2X8,
> > + .colorspace = V4L2_COLORSPACE_SRGB,
> > + .coplanar = 0,
> > + .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ABGR32],
> > + },
> > + },
> > + {
> > + .fourcc = V4L2_PIX_FMT_RGB24,
> > + .code = MEDIA_BUS_FMT_RGB888_1X24,
> > + .colorspace = V4L2_COLORSPACE_SRGB,
> > + .coplanar = 0,
> > + .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB24],
> > + },
> > + },
> > + {
> > + .fourcc = V4L2_PIX_FMT_RGB32,
> > + .code = MEDIA_BUS_FMT_ARGB8888_1X32,
> > + .colorspace = V4L2_COLORSPACE_SRGB,
> > + .coplanar = 0,
> > + .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ARGB32],
> > + },
> > + },
> > + {
> > + .fourcc = V4L2_PIX_FMT_SBGGR8,
> > + .code = MEDIA_BUS_FMT_SBGGR8_1X8,
> > + .colorspace = V4L2_COLORSPACE_SMPTE170M,
>
> SMPTE 170M for a Bayer format? That can't be right. But as mentioned above,
> this should come from the subdev.
Same here.
>
> > + .coplanar = 0,
> > + .vpdma_fmt = { &vpdma_raw_fmts[VPDMA_DATA_FMT_RAW8],
> > + },
> > + },
> > + {
> > + .fourcc = V4L2_PIX_FMT_SGBRG8,
> > + .code = MEDIA_BUS_FMT_SGBRG8_1X8,
> > + .colorspace = V4L2_COLORSPACE_SMPTE170M,
> > + .coplanar = 0,
> > + .vpdma_fmt = { &vpdma_raw_fmts[VPDMA_DATA_FMT_RAW8],
> > + },
> > + },
> > + {
> > + .fourcc = V4L2_PIX_FMT_SGRBG8,
> > + .code = MEDIA_BUS_FMT_SGRBG8_1X8,
> > + .colorspace = V4L2_COLORSPACE_SMPTE170M,
> > + .coplanar = 0,
> > + .vpdma_fmt = { &vpdma_raw_fmts[VPDMA_DATA_FMT_RAW8],
> > + },
> > + },
> > + {
> > + .fourcc = V4L2_PIX_FMT_SRGGB8,
> > + .code = MEDIA_BUS_FMT_SRGGB8_1X8,
> > + .colorspace = V4L2_COLORSPACE_SMPTE170M,
> > + .coplanar = 0,
> > + .vpdma_fmt = { &vpdma_raw_fmts[VPDMA_DATA_FMT_RAW8],
> > + },
> > + },
> > + {
> > + /* V4L2 currently only defines one 16 bit variant */
> > + .fourcc = V4L2_PIX_FMT_SBGGR16,
> > + .code = MEDIA_BUS_FMT_SBGGR16_1X16,
> > + .colorspace = V4L2_COLORSPACE_SMPTE170M,
> > + .coplanar = 0,
> > + .vpdma_fmt = { &vpdma_raw_fmts[VPDMA_DATA_FMT_RAW16],
> > + },
> > + },
> > +};
> > +
> > +/* initialize v4l2_format_info member in vip_formats array */
> > +static void vip_init_format_info(struct device *dev)
> > +{
> > + struct vip_fmt *fmt;
> > + int i;
> > +
> > + for (i = 0; i < ARRAY_SIZE(vip_formats); i++) {
> > + fmt = &vip_formats[i];
> > + fmt->finfo = v4l2_format_info(fmt->fourcc);
> > + }
> > +}
> > +
> > +/* Print Four-character-code (FOURCC) */
> > +static char *fourcc_to_str(u32 fmt)
> > +{
> > + static char code[5];
> > +
> > + code[0] = (unsigned char)(fmt & 0xff);
> > + code[1] = (unsigned char)((fmt >> 8) & 0xff);
> > + code[2] = (unsigned char)((fmt >> 16) & 0xff);
> > + code[3] = (unsigned char)((fmt >> 24) & 0xff);
> > + code[4] = '\0';
> > +
> > + return code;
> > +}
> > +
> > +/*
> > + * Find our format description corresponding to the passed v4l2_format
> > + */
> > +
> > +static struct vip_fmt *find_port_format_by_pix(struct vip_port *port,
> > + u32 pixelformat)
> > +{
> > + struct vip_fmt *fmt;
> > + unsigned int k;
> > +
> > + for (k = 0; k < port->num_active_fmt; k++) {
> > + fmt = port->active_fmt[k];
> > + if (fmt->fourcc == pixelformat)
> > + return fmt;
> > + }
> > +
> > + return NULL;
> > +}
> > +
> > +static struct vip_fmt *find_port_format_by_code(struct vip_port *port,
> > + u32 code)
> > +{
> > + struct vip_fmt *fmt;
> > + unsigned int k;
> > +
> > + for (k = 0; k < port->num_active_fmt; k++) {
> > + fmt = port->active_fmt[k];
> > + if (fmt->code == code)
> > + return fmt;
> > + }
> > +
> > + return NULL;
> > +}
> > +
> > +static int vip_find_pad(struct v4l2_subdev *sd, int direction)
> > +{
> > + unsigned int pad;
> > +
> > + if (sd->entity.num_pads <= 1)
> > + return 0;
> > +
> > + for (pad = 0; pad < sd->entity.num_pads; pad++)
> > + if (sd->entity.pads[pad].flags & direction)
> > + return pad;
> > +
> > + return -EINVAL;
> > +}
> > +
> > +inline struct vip_port *notifier_to_vip_port(struct v4l2_async_notifier *n)
> > +{
> > + return container_of(n, struct vip_port, notifier);
> > +}
> > +
> > +static bool vip_is_mbuscode_yuv(u32 code)
> > +{
> > + return ((code & 0xFF00) == 0x2000);
>
> Use lower-case hex.
Will do.
>
> > +}
> > +
> > +static bool vip_is_mbuscode_rgb(u32 code)
> > +{
> > + return ((code & 0xFF00) == 0x1000);
> > +}
> > +
> > +static bool vip_is_mbuscode_raw(u32 code)
> > +{
> > + return ((code & 0xFF00) == 0x3000);
> > +}
> > +
> > +/*
> > + * This is not an accurate conversion but it is only used to
> > + * assess if color conversion is needed.
> > + */
> > +static u32 vip_mbus_code_to_fourcc(u32 code)
> > +{
> > + if (vip_is_mbuscode_rgb(code))
> > + return V4L2_PIX_FMT_RGB24;
> > +
> > + if (vip_is_mbuscode_yuv(code))
> > + return V4L2_PIX_FMT_UYVY;
> > +
> > + return V4L2_PIX_FMT_SBGGR8;
> > +}
> > +
> > +static enum vip_csc_state
> > +vip_csc_direction(u32 src_code, const struct v4l2_format_info *dfinfo)
> > +{
> > + if (vip_is_mbuscode_yuv(src_code) && v4l2_is_format_rgb(dfinfo))
> > + return VIP_CSC_Y2R;
> > + else if (vip_is_mbuscode_rgb(src_code) && v4l2_is_format_yuv(dfinfo))
> > + return VIP_CSC_R2Y;
> > + else
> > + return VIP_CSC_NA;
> > +}
> > +
> > +/*
> > + * port flag bits
> > + */
> > +#define FLAG_FRAME_1D BIT(0)
> > +#define FLAG_EVEN_LINE_SKIP BIT(1)
> > +#define FLAG_ODD_LINE_SKIP BIT(2)
> > +#define FLAG_MODE_TILED BIT(3)
> > +#define FLAG_INTERLACED BIT(4)
> > +#define FLAG_MULTIPLEXED BIT(5)
> > +#define FLAG_MULT_PORT BIT(6)
> > +#define FLAG_MULT_ANC BIT(7)
> > +
> > +/*
> > + * Function prototype declarations
> > + */
> > +static int alloc_port(struct vip_dev *, int, const char *);
> > +static void free_port(struct vip_port *);
> > +static int vip_setup_parser(struct vip_port *port);
> > +static int vip_setup_scaler(struct vip_stream *stream);
> > +static void vip_enable_parser(struct vip_port *port, bool on);
> > +static void vip_reset_parser(struct vip_port *port, bool on);
> > +static void vip_parser_stop_imm(struct vip_port *port, bool on);
> > +static void stop_dma(struct vip_stream *stream, bool clear_list);
> > +static int vip_load_vpdma_list_fifo(struct vip_stream *stream);
> > +static inline bool is_scaler_available(struct vip_port *port);
> > +static inline bool allocate_scaler(struct vip_port *port);
> > +static inline void free_scaler(struct vip_port *port);
> > +static bool is_csc_available(struct vip_port *port);
> > +static bool allocate_csc(struct vip_port *port,
> > + enum vip_csc_state csc_direction);
> > +static void free_csc(struct vip_port *port);
> > +
> > +#define reg_read(dev, offset) ioread32(dev->base + offset)
> > +#define reg_write(dev, offset, val) iowrite32(val, dev->base + offset)
> > +
> > +/*
> > + * Insert a masked field into a 32-bit field
> > + */
> > +static void insert_field(u32 *valp, u32 field, u32 mask, int shift)
> > +{
> > + u32 val = *valp;
> > +
> > + val &= ~(mask << shift);
> > + val |= (field & mask) << shift;
> > + *valp = val;
> > +}
> > +
> > +/*
> > + * DMA address/data block for the shadow registers
> > + */
> > +struct vip_mmr_adb {
> > + struct vpdma_adb_hdr sc_hdr0;
> > + u32 sc_regs0[7];
> > + u32 sc_pad0[1];
> > + struct vpdma_adb_hdr sc_hdr8;
> > + u32 sc_regs8[6];
> > + u32 sc_pad8[2];
> > + struct vpdma_adb_hdr sc_hdr17;
> > + u32 sc_regs17[9];
> > + u32 sc_pad17[3];
> > + struct vpdma_adb_hdr csc_hdr;
> > + u32 csc_regs[6];
> > + u32 csc_pad[2];
> > +};
> > +
> > +#define GET_OFFSET_TOP(port, obj, reg) \
> > + ((obj)->res->start - port->dev->res->start + reg)
> > +
> > +#define VIP_SET_MMR_ADB_HDR(port, hdr, regs, offset_a) \
> > + VPDMA_SET_MMR_ADB_HDR(port->mmr_adb, vip_mmr_adb, hdr, regs, offset_a)
> > +
> > +/*
> > + * Set the headers for all of the address/data block structures.
> > + */
> > +static void init_adb_hdrs(struct vip_port *port)
> > +{
> > + VIP_SET_MMR_ADB_HDR(port, sc_hdr0, sc_regs0,
> > + GET_OFFSET_TOP(port, port->dev->sc, CFG_SC0));
> > + VIP_SET_MMR_ADB_HDR(port, sc_hdr8, sc_regs8,
> > + GET_OFFSET_TOP(port, port->dev->sc, CFG_SC8));
> > + VIP_SET_MMR_ADB_HDR(port, sc_hdr17, sc_regs17,
> > + GET_OFFSET_TOP(port, port->dev->sc, CFG_SC17));
> > + VIP_SET_MMR_ADB_HDR(port, csc_hdr, csc_regs,
> > + GET_OFFSET_TOP(port, port->dev->csc, CSC_CSC00));
> > +
> > +};
> > +
> > +/*
> > + * These represent the module resets bit for slice 1
> > + * Upon detecting slice2 we simply left shift by 1
> > + */
> > +#define VIP_DP_RST BIT(16)
> > +#define VIP_PARSER_RST BIT(18)
> > +#define VIP_CSC_RST BIT(20)
> > +#define VIP_SC_RST BIT(22)
> > +#define VIP_DS0_RST BIT(25)
> > +#define VIP_DS1_RST BIT(27)
> > +
> > +static void vip_module_reset(struct vip_dev *dev, uint32_t module, bool on)
> > +{
> > + u32 val = 0;
> > +
> > + val = reg_read(dev, VIP_CLK_RESET);
> > +
> > + if (dev->slice_id == VIP_SLICE2)
> > + module <<= 1;
> > +
> > + if (on)
> > + val |= module;
> > + else
> > + val &= ~module;
> > +
> > + reg_write(dev, VIP_CLK_RESET, val);
> > +}
> > +
> > +/*
> > + * Enable or disable the VIP clocks
> > + */
> > +static void vip_set_clock_enable(struct vip_dev *dev, bool on)
> > +{
> > + u32 val = 0;
> > +
> > + val = reg_read(dev, VIP_CLK_ENABLE);
> > + if (on) {
> > + val |= VIP_VPDMA_CLK_ENABLE;
> > + if (dev->slice_id == VIP_SLICE1)
> > + val |= VIP_VIP1_DATA_PATH_CLK_ENABLE;
> > + else
> > + val |= VIP_VIP2_DATA_PATH_CLK_ENABLE;
> > + } else {
> > + if (dev->slice_id == VIP_SLICE1)
> > + val &= ~VIP_VIP1_DATA_PATH_CLK_ENABLE;
> > + else
> > + val &= ~VIP_VIP2_DATA_PATH_CLK_ENABLE;
> > +
> > + /* Both VIP are disabled then shutdown VPDMA also */
> > + if (!(val & (VIP_VIP1_DATA_PATH_CLK_ENABLE |
> > + VIP_VIP2_DATA_PATH_CLK_ENABLE)))
> > + val = 0;
> > + }
> > +
> > + reg_write(dev, VIP_CLK_ENABLE, val);
> > +}
> > +
> > +/* This helper function is used to enable the clock early on to
> > + * enable vpdma firmware loading before the slice device are created
> > + */
> > +static void vip_shared_set_clock_enable(struct vip_shared *shared, bool on)
> > +{
> > + u32 val = 0;
> > +
> > + if (on)
> > + val = VIP_VIP1_DATA_PATH_CLK_ENABLE | VIP_VPDMA_CLK_ENABLE;
> > +
> > + reg_write(shared, VIP_CLK_ENABLE, val);
> > +}
> > +
> > +static void vip_top_reset(struct vip_dev *dev)
> > +{
> > + u32 val = 0;
> > +
> > + val = reg_read(dev, VIP_CLK_RESET);
> > +
> > + if (dev->slice_id == VIP_SLICE1)
> > + insert_field(&val, 1, VIP_DATA_PATH_CLK_RESET_MASK,
> > + VIP_VIP1_DATA_PATH_RESET_SHIFT);
> > + else
> > + insert_field(&val, 1, VIP_DATA_PATH_CLK_RESET_MASK,
> > + VIP_VIP2_DATA_PATH_RESET_SHIFT);
> > +
> > + reg_write(dev, VIP_CLK_RESET, val);
> > +
> > + usleep_range(200, 250);
> > +
> > + val = reg_read(dev, VIP_CLK_RESET);
> > +
> > + if (dev->slice_id == VIP_SLICE1)
> > + insert_field(&val, 0, VIP_DATA_PATH_CLK_RESET_MASK,
> > + VIP_VIP1_DATA_PATH_RESET_SHIFT);
> > + else
> > + insert_field(&val, 0, VIP_DATA_PATH_CLK_RESET_MASK,
> > + VIP_VIP2_DATA_PATH_RESET_SHIFT);
> > + reg_write(dev, VIP_CLK_RESET, val);
> > +}
> > +
> > +static void vip_top_vpdma_reset(struct vip_shared *shared)
> > +{
> > + u32 val;
> > +
> > + val = reg_read(shared, VIP_CLK_RESET);
> > + insert_field(&val, 1, VIP_VPDMA_CLK_RESET_MASK,
> > + VIP_VPDMA_CLK_RESET_SHIFT);
> > + reg_write(shared, VIP_CLK_RESET, val);
> > +
> > + usleep_range(200, 250);
> > +
> > + val = reg_read(shared, VIP_CLK_RESET);
> > + insert_field(&val, 0, VIP_VPDMA_CLK_RESET_MASK,
> > + VIP_VPDMA_CLK_RESET_SHIFT);
> > + reg_write(shared, VIP_CLK_RESET, val);
> > +}
> > +
> > +static void vip_set_pclk_invert(struct vip_port *port)
> > +{
> > + struct vip_clk_polarity *pclk = port->dev->pclk_pol;
> > + u32 index;
> > +
> > + /*
> > + * When the VIP parser is configured to so that the pixel clock
> > + * is to be sampled at falling edge, the pixel clock needs to be
> > + * inverted before it is given to the VIP module. This is done
> > + * by setting a bit in the CTRL_CORE_SMA_SW1 register.
> > + */
> > +
> > + index = 2 * port->dev->slice_id + port->port_id;
> > + vip_dbg(3, port, "%s: slice%d:port%d -> index: %d\n", __func__,
> > + port->dev->slice_id, port->port_id, index);
> > +
> > + if (pclk->rm_pol)
> > + regmap_update_bits(pclk->rm_pol,
> > + pclk->rm_offset,
> > + pclk->rm_bit_field[index],
> > + pclk->rm_bit_field[index]);
> > +}
> > +
> > +static void vip_clr_pclk_invert(struct vip_port *port)
> > +{
> > + struct vip_clk_polarity *pclk = port->dev->pclk_pol;
> > + u32 index;
> > +
> > + index = 2 * port->dev->slice_id + port->port_id;
> > + vip_dbg(3, port, "%s: slice%d:port%d -> index: %d\n", __func__,
> > + port->dev->slice_id, port->port_id, index);
> > +
> > + if (pclk->rm_pol)
> > + regmap_update_bits(pclk->rm_pol, pclk->rm_offset,
> > + pclk->rm_bit_field[index], 0);
> > +}
> > +
> > +#define VIP_PARSER_PORT(p) (VIP_PARSER_PORTA_0 + (p * 0x8U))
> > +#define VIP_PARSER_EXTRA_PORT(p) (VIP_PARSER_PORTA_1 + (p * 0x8U))
> > +#define VIP_PARSER_CROP_H_PORT(p) (VIP_PARSER_PORTA_EXTRA4 + (p * 0x10U))
> > +#define VIP_PARSER_CROP_V_PORT(p) (VIP_PARSER_PORTA_EXTRA5 + (p * 0x10U))
> > +#define VIP_PARSER_STOP_IMM_PORT(p) (VIP_PARSER_PORTA_EXTRA6 + (p * 0x4U))
> > +
> > +static void vip_set_data_interface(struct vip_port *port,
> > + enum data_interface_modes mode)
> > +{
> > + u32 val = 0;
> > +
> > + insert_field(&val, mode, VIP_DATA_INTERFACE_MODE_MASK,
> > + VIP_DATA_INTERFACE_MODE_SHFT);
> > +
> > + reg_write(port->dev->parser, VIP_PARSER_MAIN_CFG, val);
> > +}
> > +
> > +static void vip_set_slice_path(struct vip_dev *dev,
> > + enum data_path_select data_path, u32 path_val)
> > +{
> > + u32 val = 0;
> > + int data_path_reg;
> > +
> > + vip_dbg(3, dev, "%s:\n", __func__);
> > +
> > + data_path_reg = VIP_VIP1_DATA_PATH_SELECT + 4 * dev->slice_id;
> > +
> > + switch (data_path) {
> > + case ALL_FIELDS_DATA_SELECT:
> > + val |= path_val;
> > + break;
> > + case VIP_CSC_SRC_DATA_SELECT:
> > + insert_field(&val, path_val, VIP_CSC_SRC_SELECT_MASK,
> > + VIP_CSC_SRC_SELECT_SHFT);
> > + break;
> > + case VIP_SC_SRC_DATA_SELECT:
> > + insert_field(&val, path_val, VIP_SC_SRC_SELECT_MASK,
> > + VIP_SC_SRC_SELECT_SHFT);
> > + break;
> > + case VIP_RGB_SRC_DATA_SELECT:
> > + val |= (path_val) ? VIP_RGB_SRC_SELECT : 0;
> > + break;
> > + case VIP_RGB_OUT_LO_DATA_SELECT:
> > + val |= (path_val) ? VIP_RGB_OUT_LO_SRC_SELECT : 0;
> > + break;
> > + case VIP_RGB_OUT_HI_DATA_SELECT:
> > + val |= (path_val) ? VIP_RGB_OUT_HI_SRC_SELECT : 0;
> > + break;
> > + case VIP_CHR_DS_1_SRC_DATA_SELECT:
> > + insert_field(&val, path_val, VIP_DS1_SRC_SELECT_MASK,
> > + VIP_DS1_SRC_SELECT_SHFT);
> > + break;
> > + case VIP_CHR_DS_2_SRC_DATA_SELECT:
> > + insert_field(&val, path_val, VIP_DS2_SRC_SELECT_MASK,
> > + VIP_DS2_SRC_SELECT_SHFT);
> > + break;
> > + case VIP_MULTI_CHANNEL_DATA_SELECT:
> > + val |= (path_val) ? VIP_MULTI_CHANNEL_SELECT : 0;
> > + break;
> > + case VIP_CHR_DS_1_DATA_BYPASS:
> > + val |= (path_val) ? VIP_DS1_BYPASS : 0;
> > + break;
> > + case VIP_CHR_DS_2_DATA_BYPASS:
> > + val |= (path_val) ? VIP_DS2_BYPASS : 0;
> > + break;
> > + default:
> > + vip_err(dev, "%s: data_path 0x%x is not valid\n",
> > + __func__, data_path);
> > + return;
> > + }
> > + insert_field(&val, data_path, VIP_DATAPATH_SELECT_MASK,
> > + VIP_DATAPATH_SELECT_SHFT);
> > + reg_write(dev, data_path_reg, val);
> > + vip_dbg(3, dev, "%s: DATA_PATH_SELECT(%08X): %08X\n", __func__,
> > + data_path_reg, reg_read(dev, data_path_reg));
> > +}
> > +
> > +/*
> > + * Return the vip_stream structure for a given struct file
> > + */
> > +static inline struct vip_stream *file2stream(struct file *file)
> > +{
> > + return video_drvdata(file);
> > +}
> > +
> > +/*
> > + * Append a destination descriptor to the current descriptor list,
> > + * setting up dma to the given srce.
> > + */
> > +static int add_out_dtd(struct vip_stream *stream, int srce_type)
> > +{
> > + struct vip_port *port = stream->port;
> > + struct vip_dev *dev = port->dev;
> > + struct vip_srce_info *sinfo = &srce_info[srce_type];
> > + struct v4l2_rect *c_rect = &port->c_rect;
> > + struct vip_fmt *fmt = port->fmt;
> > + int channel, plane = 0;
> > + int max_width, max_height;
> > + dma_addr_t dma_addr;
> > + u32 flags;
> > + u32 width = stream->width;
> > +
> > + channel = sinfo->base_channel;
> > +
> > + switch (srce_type) {
> > + case VIP_SRCE_MULT_PORT:
> > + case VIP_SRCE_MULT_ANC:
> > + if (port->port_id == VIP_PORTB)
> > + channel += VIP_CHAN_MULT_PORTB_OFFSET;
> > + channel += stream->stream_id;
> > + flags = 0;
> > + break;
> > + case VIP_SRCE_CHROMA:
> > + plane = 1;
> > + /* fallthrough */
> > + case VIP_SRCE_LUMA:
> > + if (port->port_id == VIP_PORTB) {
> > + if (port->scaler && !port->fmt->coplanar)
> > + /*
> > + * In this case Port A Chroma channel
> > + * is used to carry Port B scaled YUV422
> > + */
> > + channel += 1;
> > + else
> > + channel += VIP_CHAN_YUV_PORTB_OFFSET;
> > + }
> > + flags = port->flags;
> > + break;
> > + case VIP_SRCE_RGB:
> > + if ((port->port_id == VIP_PORTB) ||
> > + ((port->port_id == VIP_PORTA) &&
> > + (port->csc == VIP_CSC_NA) &&
> > + v4l2_is_format_rgb(port->fmt->finfo)))
> > + /*
> > + * RGB sensor only connect to Y_LO
> > + * channel i.e. port B channel.
> > + */
> > + channel += VIP_CHAN_RGB_PORTB_OFFSET;
> > + flags = port->flags;
> > + break;
> > + default:
> > + vip_err(stream, "%s: srce_type 0x%x is not valid\n",
> > + __func__, srce_type);
> > + return -1;
> > + }
> > +
> > + if (dev->slice_id == VIP_SLICE2)
> > + channel += VIP_CHAN_VIP2_OFFSET;
> > +
> > + /* This is just for initialization purposes.
> > + * The actual dma_addr will be configured in vpdma_update_dma_addr
> > + */
> > + dma_addr = 0;
> > +
> > + if (port->fmt->vpdma_fmt[0] == &vpdma_raw_fmts[VPDMA_DATA_FMT_RAW8]) {
> > + /*
> > + * Special case since we are faking a YUV422 16bit format
> > + * to have the vpdma perform the needed byte swap
> > + * we need to adjust the pixel width accordingly
> > + * otherwise the parser will attempt to collect more pixels
> > + * then available and the vpdma transfer will exceed the
> > + * allocated frame buffer.
> > + */
> > + width >>= 1;
> > + vip_dbg(1, stream, "%s: 8 bit raw detected, adjusting width to %d\n",
> > + __func__, width);
> > + }
> > +
> > + /*
> > + * Use VPDMA_MAX_SIZE1 or VPDMA_MAX_SIZE2 register for slice0/1
> > + */
> > +
> > + if (dev->slice_id == VIP_SLICE1) {
> > + vpdma_set_max_size(dev->shared->vpdma, VPDMA_MAX_SIZE1,
> > + width, stream->height);
> > +
> > + max_width = MAX_OUT_WIDTH_REG1;
> > + max_height = MAX_OUT_HEIGHT_REG1;
> > + } else {
> > + vpdma_set_max_size(dev->shared->vpdma, VPDMA_MAX_SIZE2,
> > + width, stream->height);
> > +
> > + max_width = MAX_OUT_WIDTH_REG2;
> > + max_height = MAX_OUT_HEIGHT_REG2;
> > + }
> > +
> > + /*
> > + * Mark this channel to be cleared while cleaning up resources
> > + * This will make sure that an abort descriptor for this channel
> > + * would be submitted to VPDMA causing any ongoing transaction to be
> > + * aborted and cleanup the VPDMA FSM for this channel
> > + */
> > + stream->vpdma_channels[channel] = 1;
> > +
> > + vpdma_rawchan_add_out_dtd(&stream->desc_list, c_rect->width,
> > + stream->bytesperline, c_rect,
> > + fmt->vpdma_fmt[plane], dma_addr,
> > + max_width, max_height, channel, flags);
> > +
> > + return 0;
> > +}
> > +
> > +/*
> > + * add_stream_dtds - prepares and starts DMA for pending transfers
> > + */
> > +static void add_stream_dtds(struct vip_stream *stream)
> > +{
> > + struct vip_port *port = stream->port;
> > + int srce_type;
> > +
> > + if (port->flags & FLAG_MULT_PORT)
> > + srce_type = VIP_SRCE_MULT_PORT;
> > + else if (port->flags & FLAG_MULT_ANC)
> > + srce_type = VIP_SRCE_MULT_ANC;
> > + else if (v4l2_is_format_rgb(port->fmt->finfo))
> > + srce_type = VIP_SRCE_RGB;
> > + else
> > + srce_type = VIP_SRCE_LUMA;
> > +
> > + add_out_dtd(stream, srce_type);
> > +
> > + if (srce_type == VIP_SRCE_LUMA && port->fmt->coplanar)
> > + add_out_dtd(stream, VIP_SRCE_CHROMA);
> > +}
> > +
> > +#define PARSER_IRQ_MASK (VIP_PORTA_OUTPUT_FIFO_YUV | \
> > + VIP_PORTB_OUTPUT_FIFO_YUV)
> > +
> > +static void enable_irqs(struct vip_dev *dev, int irq_num, int list_num)
> > +{
> > + struct vip_parser_data *parser = dev->parser;
> > + u32 reg_addr = VIP_INT0_ENABLE0_SET +
> > + VIP_INTC_INTX_OFFSET * irq_num;
> > + u32 irq_val = (1 << (list_num * 2)) |
> > + (VIP_VIP1_PARSER_INT << (irq_num * 1));
> > +
> > + /* Enable Parser Interrupt */
> > + reg_write(parser, VIP_PARSER_FIQ_MASK, ~PARSER_IRQ_MASK);
> > +
> > + reg_write(dev->shared, reg_addr, irq_val);
> > +
> > + vpdma_enable_list_complete_irq(dev->shared->vpdma,
> > + irq_num, list_num, true);
> > +}
> > +
> > +static void disable_irqs(struct vip_dev *dev, int irq_num, int list_num)
> > +{
> > + struct vip_parser_data *parser = dev->parser;
> > + u32 reg_addr = VIP_INT0_ENABLE0_CLR +
> > + VIP_INTC_INTX_OFFSET * irq_num;
> > + u32 irq_val = (1 << (list_num * 2)) |
> > + (VIP_VIP1_PARSER_INT << (irq_num * 1));
> > +
> > + /* Disable all Parser Interrupt */
> > + reg_write(parser, VIP_PARSER_FIQ_MASK, 0xffffffff);
> > +
> > + reg_write(dev->shared, reg_addr, irq_val);
> > +
> > + vpdma_enable_list_complete_irq(dev->shared->vpdma,
> > + irq_num, list_num, false);
> > +}
> > +
> > +static void clear_irqs(struct vip_dev *dev, int irq_num, int list_num)
> > +{
> > + struct vip_parser_data *parser = dev->parser;
> > + u32 reg_addr = VIP_INT0_STATUS0_CLR +
> > + VIP_INTC_INTX_OFFSET * irq_num;
> > + u32 irq_val = (1 << (list_num * 2)) |
> > + (VIP_VIP1_PARSER_INT << (irq_num * 1));
> > +
> > + /* Clear all Parser Interrupt */
> > + reg_write(parser, VIP_PARSER_FIQ_CLR, 0xffffffff);
> > + reg_write(parser, VIP_PARSER_FIQ_CLR, 0x0);
> > +
> > + reg_write(dev->shared, reg_addr, irq_val);
> > +
> > + vpdma_clear_list_stat(dev->shared->vpdma, irq_num, dev->slice_id);
> > +}
> > +
> > +static void populate_desc_list(struct vip_stream *stream)
> > +{
> > + struct vip_port *port = stream->port;
> > + struct vip_dev *dev = port->dev;
> > + unsigned int list_length;
> > +
> > + stream->desc_next = stream->desc_list.buf.addr;
> > + add_stream_dtds(stream);
> > +
> > + list_length = stream->desc_next - stream->desc_list.buf.addr;
> > + vpdma_map_desc_buf(dev->shared->vpdma, &stream->desc_list.buf);
> > +}
> > +
> > +/*
> > + * start_dma - adds descriptors to the dma list and submits them.
> > + * Should be called after a new vb is queued and on a vpdma list
> > + * completion interrupt.
> > + */
> > +static void start_dma(struct vip_stream *stream, struct vip_buffer *buf)
> > +{
> > + struct vip_dev *dev = stream->port->dev;
> > + struct vpdma_data *vpdma = dev->shared->vpdma;
> > + int list_num = stream->list_num;
> > + dma_addr_t dma_addr;
> > + int drop_data;
> > +
> > + if (vpdma_list_busy(vpdma, list_num)) {
> > + vip_err(stream, "vpdma list busy, cannot post\n");
> > + return; /* nothing to do */
> > + }
> > +
> > + if (buf) {
> > + dma_addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
> > + drop_data = 0;
> > + vip_dbg(4, stream, "%s: vb2 buf idx:%d, dma_addr:%pad\n",
> > + __func__, buf->vb.vb2_buf.index, &dma_addr);
> > + } else {
> > + dma_addr = 0;
> > + drop_data = 1;
> > + vip_dbg(4, stream, "%s: dropped\n", __func__);
> > + }
> > +
> > + vpdma_update_dma_addr(dev->shared->vpdma, &stream->desc_list,
> > + dma_addr, stream->write_desc, drop_data, 0);
> > +
> > + if (stream->port->fmt->coplanar) {
> > + dma_addr += stream->bytesperline * stream->height;
> > + vpdma_update_dma_addr(dev->shared->vpdma, &stream->desc_list,
> > + dma_addr, stream->write_desc + 1,
> > + drop_data, 1);
> > + }
> > +
> > + vpdma_submit_descs(dev->shared->vpdma,
> > + &stream->desc_list, stream->list_num);
> > +}
> > +
> > +static void vip_schedule_next_buffer(struct vip_stream *stream)
> > +{
> > + struct vip_dev *dev = stream->port->dev;
> > + struct vip_buffer *buf;
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(&dev->slock, flags);
> > + if (list_empty(&stream->vidq)) {
> > + vip_dbg(4, stream, "Dropping frame\n");
> > + if (list_empty(&stream->dropq)) {
> > + vip_err(stream, "No dropq buffer left!");
> > + spin_unlock_irqrestore(&dev->slock, flags);
> > + return;
> > + }
> > + buf = list_entry(stream->dropq.next,
> > + struct vip_buffer, list);
> > +
> > + buf->drop = true;
> > + list_move_tail(&buf->list, &stream->post_bufs);
> > + buf = NULL;
> > + } else {
> > + buf = list_entry(stream->vidq.next,
> > + struct vip_buffer, list);
> > + buf->drop = false;
> > + list_move_tail(&buf->list, &stream->post_bufs);
> > + vip_dbg(4, stream, "added next buffer\n");
> > + }
> > +
> > + spin_unlock_irqrestore(&dev->slock, flags);
> > + start_dma(stream, buf);
> > +}
> > +
> > +static void vip_process_buffer_complete(struct vip_stream *stream)
> > +{
> > + struct vip_dev *dev = stream->port->dev;
> > + struct vip_buffer *buf;
> > + struct vb2_v4l2_buffer *vb = NULL;
> > + unsigned long flags, fld;
> > +
> > + buf = list_first_entry(&stream->post_bufs, struct vip_buffer, list);
> > +
> > + if (stream->port->flags & FLAG_INTERLACED) {
> > + vpdma_unmap_desc_buf(dev->shared->vpdma,
> > + &stream->desc_list.buf);
> > +
> > + fld = dtd_get_field(stream->write_desc);
> > + stream->field = fld ? V4L2_FIELD_BOTTOM : V4L2_FIELD_TOP;
> > +
> > + vpdma_map_desc_buf(dev->shared->vpdma, &stream->desc_list.buf);
> > + }
> > +
> > + if (buf) {
> > + vip_dbg(4, stream, "vip buffer complete 0x%x, 0x%x\n",
> > + (unsigned int)buf, buf->drop);
> > +
> > + vb = &buf->vb;
> > + vb->field = stream->field;
> > + vb->sequence = stream->sequence;
> > + vb->vb2_buf.timestamp = ktime_get_ns();
> > +
> > + if (buf->drop) {
> > + spin_lock_irqsave(&dev->slock, flags);
> > + list_move_tail(&buf->list, &stream->dropq);
> > + spin_unlock_irqrestore(&dev->slock, flags);
> > + } else {
> > + spin_lock_irqsave(&dev->slock, flags);
> > + list_del(&buf->list);
> > + spin_unlock_irqrestore(&dev->slock, flags);
> > + vb2_buffer_done(&vb->vb2_buf, VB2_BUF_STATE_DONE);
> > + }
> > + } else {
> > + vip_err(stream, "%s: buf is null!!!\n", __func__);
> > + return;
> > + }
> > +
> > + stream->sequence++;
> > +}
> > +
> > +static int vip_reset_vpdma(struct vip_stream *stream)
> > +{
> > + struct vip_port *port = stream->port;
> > + struct vip_dev *dev = port->dev;
> > + struct vip_buffer *buf;
> > + unsigned long flags;
> > +
> > + stop_dma(stream, false);
> > +
> > + spin_lock_irqsave(&dev->slock, flags);
> > + /* requeue all active buffers in the opposite order */
> > + while (!list_empty(&stream->post_bufs)) {
> > + buf = list_last_entry(&stream->post_bufs,
> > + struct vip_buffer, list);
> > + list_del(&buf->list);
> > + if (buf->drop == 1) {
> > + list_add_tail(&buf->list, &stream->dropq);
> > + vip_dbg(4, stream, "requeueing drop buffer on dropq\n");
> > + } else {
> > + list_add(&buf->list, &stream->vidq);
> > + vip_dbg(4, stream, "requeueing vb2 buf idx:%d on vidq\n",
> > + buf->vb.vb2_buf.index);
> > + }
> > + }
> > + spin_unlock_irqrestore(&dev->slock, flags);
> > +
> > + /* Make sure the desc_list is unmapped */
> > + vpdma_unmap_desc_buf(dev->shared->vpdma, &stream->desc_list.buf);
> > +
> > + return 0;
> > +}
> > +
> > +static void vip_overflow_recovery_work(struct work_struct *work)
>
> This function requires some additional comments about when it should
> be called and what it does. Recovery is always tricky, and so it is
> worthwhile spending additional time on commenting it.
Ok I'll add a comments and also a reference to the related TRM section.
>
> > +{
> > + struct vip_stream *stream = container_of(work, struct vip_stream,
> > + recovery_work);
> > + struct vip_port *port = stream->port;
> > + struct vip_dev *dev = port->dev;
> > +
> > + vip_err(stream, "%s: Port %c\n", __func__,
> > + port->port_id == VIP_PORTA ? 'A' : 'B');
> > +
> > + disable_irqs(dev, dev->slice_id, stream->list_num);
> > + clear_irqs(dev, dev->slice_id, stream->list_num);
> > +
> > + /* 1. Set VIP_XTRA6_PORT_A[31:16] YUV_SRCNUM_STOP_IMMEDIATELY */
> > + /* 2. Set VIP_XTRA6_PORT_A[15:0] ANC_SRCNUM_STOP_IMMEDIATELY */
> > + vip_parser_stop_imm(port, 1);
> > +
> > + /* 3. Clear VIP_PORT_A[8] ENABLE */
> > + /*
> > + * 4. Set VIP_PORT_A[7] CLR_ASYNC_FIFO_RD
> > + * Set VIP_PORT_A[6] CLR_ASYNC_FIFO_WR
> > + */
> > + vip_enable_parser(port, false);
> > +
> > + /* 5. Set VIP_PORT_A[23] SW_RESET */
> > + vip_reset_parser(port, 1);
> > +
> > + /*
> > + * 6. Reset other VIP modules
> > + * For each module used downstream of VIP_PARSER, write 1 to the
> > + * bit location of the VIP_CLKC_RST register which is connected
> > + * to VIP_PARSER
> > + */
> > + vip_module_reset(dev, VIP_DP_RST, true);
> > +
> > + usleep_range(200, 250);
> > +
> > + /*
> > + * 7. Abort VPDMA channels
> > + * Write to list attribute to stop list 0
> > + * Write to list address register location of abort list
> > + * Write to list attribute register list 0 and size of abort list
> > + */
> > + vip_reset_vpdma(stream);
> > +
> > + /* 8. Clear VIP_PORT_A[23] SW_RESET */
> > + vip_reset_parser(port, 0);
> > +
> > + /*
> > + * 9. Un-reset other VIP modules
> > + * For each module used downstream of VIP_PARSER, write 0 to
> > + * the bit location of the VIP_CLKC_RST register which is
> > + * connected to VIP_PARSER
> > + */
> > + vip_module_reset(dev, VIP_DP_RST, false);
> > +
> > + /* 10. (Delay) */
> > + /* 11. SC coeff downloaded (if VIP_SCALER is being used) */
> > + vip_setup_scaler(stream);
> > +
> > + /* 12. (Delay) */
> > + /* the above are not needed here yet */
> > +
> > + populate_desc_list(stream);
> > + stream->num_recovery++;
> > + if (stream->num_recovery < 5) {
> > + /* Reload the vpdma */
> > + vip_load_vpdma_list_fifo(stream);
> > +
> > + enable_irqs(dev, dev->slice_id, stream->list_num);
> > + vip_schedule_next_buffer(stream);
> > +
> > + /* 13. Clear VIP_XTRA6_PORT_A[31:16] YUV_SRCNUM_STOP_IMM */
> > + /* 14. Clear VIP_XTRA6_PORT_A[15:0] ANC_SRCNUM_STOP_IMM */
> > +
> > + vip_parser_stop_imm(port, 0);
> > +
> > + /* 15. Set VIP_PORT_A[8] ENABLE */
> > + /*
> > + * 16. Clear VIP_PORT_A[7] CLR_ASYNC_FIFO_RD
> > + * Clear VIP_PORT_A[6] CLR_ASYNC_FIFO_WR
> > + */
> > + vip_enable_parser(port, true);
> > + } else {
> > + vip_err(stream, "%s: num_recovery limit exceeded leaving disabled\n",
> > + __func__);
> > + }
> > +}
> > +
> > +static void handle_parser_irqs(struct vip_dev *dev)
> > +{
> > + struct vip_parser_data *parser = dev->parser;
> > + struct vip_port *porta = dev->ports[VIP_PORTA];
> > + struct vip_port *portb = dev->ports[VIP_PORTB];
> > + struct vip_stream *stream = NULL;
> > + u32 irq_stat = reg_read(parser, VIP_PARSER_FIQ_STATUS);
> > + int i;
> > +
> > + vip_dbg(3, dev, "%s: FIQ_STATUS: 0x%08x\n", __func__, irq_stat);
> > +
> > + /* Clear all Parser Interrupt */
> > + reg_write(parser, VIP_PARSER_FIQ_CLR, irq_stat);
> > + reg_write(parser, VIP_PARSER_FIQ_CLR, 0x0);
> > +
> > + if (irq_stat & VIP_PORTA_VDET)
> > + vip_dbg(3, dev, "VIP_PORTA_VDET\n");
> > + if (irq_stat & VIP_PORTB_VDET)
> > + vip_dbg(3, dev, "VIP_PORTB_VDET\n");
> > + if (irq_stat & VIP_PORTA_ASYNC_FIFO_OF)
> > + vip_err(dev, "VIP_PORTA_ASYNC_FIFO_OF\n");
> > + if (irq_stat & VIP_PORTB_ASYNC_FIFO_OF)
> > + vip_err(dev, "VIP_PORTB_ASYNC_FIFO_OF\n");
> > + if (irq_stat & VIP_PORTA_OUTPUT_FIFO_YUV)
> > + vip_err(dev, "VIP_PORTA_OUTPUT_FIFO_YUV\n");
> > + if (irq_stat & VIP_PORTA_OUTPUT_FIFO_ANC)
> > + vip_err(dev, "VIP_PORTA_OUTPUT_FIFO_ANC\n");
> > + if (irq_stat & VIP_PORTB_OUTPUT_FIFO_YUV)
> > + vip_err(dev, "VIP_PORTB_OUTPUT_FIFO_YUV\n");
> > + if (irq_stat & VIP_PORTB_OUTPUT_FIFO_ANC)
> > + vip_err(dev, "VIP_PORTB_OUTPUT_FIFO_ANC\n");
> > + if (irq_stat & VIP_PORTA_CONN)
> > + vip_dbg(3, dev, "VIP_PORTA_CONN\n");
> > + if (irq_stat & VIP_PORTA_DISCONN)
> > + vip_dbg(3, dev, "VIP_PORTA_DISCONN\n");
> > + if (irq_stat & VIP_PORTB_CONN)
> > + vip_dbg(3, dev, "VIP_PORTB_CONN\n");
> > + if (irq_stat & VIP_PORTB_DISCONN)
> > + vip_dbg(3, dev, "VIP_PORTB_DISCONN\n");
> > + if (irq_stat & VIP_PORTA_SRC0_SIZE)
> > + vip_dbg(3, dev, "VIP_PORTA_SRC0_SIZE\n");
> > + if (irq_stat & VIP_PORTB_SRC0_SIZE)
> > + vip_dbg(3, dev, "VIP_PORTB_SRC0_SIZE\n");
> > + if (irq_stat & VIP_PORTA_YUV_PROTO_VIOLATION)
> > + vip_dbg(3, dev, "VIP_PORTA_YUV_PROTO_VIOLATION\n");
> > + if (irq_stat & VIP_PORTA_ANC_PROTO_VIOLATION)
> > + vip_dbg(3, dev, "VIP_PORTA_ANC_PROTO_VIOLATION\n");
> > + if (irq_stat & VIP_PORTB_YUV_PROTO_VIOLATION)
> > + vip_dbg(3, dev, "VIP_PORTB_YUV_PROTO_VIOLATION\n");
> > + if (irq_stat & VIP_PORTB_ANC_PROTO_VIOLATION)
> > + vip_dbg(3, dev, "VIP_PORTB_ANC_PROTO_VIOLATION\n");
> > + if (irq_stat & VIP_PORTA_CFG_DISABLE_COMPLETE)
> > + vip_dbg(3, dev, "VIP_PORTA_CFG_DISABLE_COMPLETE\n");
> > + if (irq_stat & VIP_PORTB_CFG_DISABLE_COMPLETE)
> > + vip_dbg(3, dev, "VIP_PORTB_CFG_DISABLE_COMPLETE\n");
> > +
> > + if (irq_stat & (VIP_PORTA_ASYNC_FIFO_OF |
> > + VIP_PORTA_OUTPUT_FIFO_YUV |
> > + VIP_PORTA_OUTPUT_FIFO_ANC)) {
> > + for (i = 0; i < VIP_CAP_STREAMS_PER_PORT; i++) {
> > + if (porta->cap_streams[i] &&
> > + porta->cap_streams[i]->port->port_id ==
> > + porta->port_id) {
> > + stream = porta->cap_streams[i];
> > + break;
> > + }
> > + }
> > + if (stream) {
> > + disable_irqs(dev, dev->slice_id,
> > + stream->list_num);
> > + schedule_work(&stream->recovery_work);
> > + return;
> > + }
> > + }
> > + if (irq_stat & (VIP_PORTB_ASYNC_FIFO_OF |
> > + VIP_PORTB_OUTPUT_FIFO_YUV |
> > + VIP_PORTB_OUTPUT_FIFO_ANC)) {
> > + for (i = 0; i < VIP_CAP_STREAMS_PER_PORT; i++) {
> > + if (portb->cap_streams[i] &&
> > + portb->cap_streams[i]->port->port_id ==
> > + portb->port_id) {
> > + stream = portb->cap_streams[i];
> > + break;
> > + }
> > + }
> > + if (stream) {
> > + disable_irqs(dev, dev->slice_id,
> > + stream->list_num);
> > + schedule_work(&stream->recovery_work);
> > + return;
> > + }
> > + }
> > +}
> > +
> > +static irqreturn_t vip_irq(int irq_vip, void *data)
> > +{
> > + struct vip_dev *dev = (struct vip_dev *)data;
> > + struct vpdma_data *vpdma;
> > + struct vip_stream *stream;
> > + int list_num;
> > + int irq_num = dev->slice_id;
> > + u32 irqst, irqst_saved, reg_addr;
> > +
> > + if (!dev->shared)
> > + return IRQ_HANDLED;
> > +
> > + vpdma = dev->shared->vpdma;
> > + reg_addr = VIP_INT0_STATUS0 +
> > + VIP_INTC_INTX_OFFSET * irq_num;
> > + irqst_saved = reg_read(dev->shared, reg_addr);
> > + irqst = irqst_saved;
> > +
> > + vip_dbg(8, dev, "IRQ %d VIP_INT%d_STATUS0 0x%x\n",
> > + irq_vip, irq_num, irqst);
> > + if (irqst) {
> > + if (irqst & (VIP_VIP1_PARSER_INT << (irq_num * 1))) {
> > + irqst &= ~(VIP_VIP1_PARSER_INT << (irq_num * 1));
> > + handle_parser_irqs(dev);
> > + }
> > +
> > + for (list_num = 0; irqst && (list_num < 8); list_num++) {
> > + /* Check for LIST_COMPLETE IRQ */
> > + if (!(irqst & (1 << list_num * 2)))
> > + continue;
> > +
> > + vip_dbg(8, dev, "IRQ %d: handling LIST%d_COMPLETE\n",
> > + irq_num, list_num);
> > +
> > + stream = vpdma_hwlist_get_priv(vpdma, list_num);
> > + if (!stream || stream->list_num != list_num) {
> > + vip_err(dev, "IRQ occurred for unused list");
> > + continue;
> > + }
> > +
> > + vpdma_clear_list_stat(vpdma, irq_num, list_num);
> > +
> > + vip_process_buffer_complete(stream);
> > +
> > + vip_schedule_next_buffer(stream);
> > +
> > + irqst &= ~((1 << list_num * 2));
> > + }
> > + }
> > +
> > + /* Acknowledge that we are done with all interrupts */
> > + reg_write(dev->shared, VIP_INTC_E0I, 1 << irq_num);
> > +
> > + /* Clear handled events from status register */
> > + reg_addr = VIP_INT0_STATUS0_CLR +
> > + VIP_INTC_INTX_OFFSET * irq_num;
> > + reg_write(dev->shared, reg_addr, irqst_saved);
> > +
> > + return IRQ_HANDLED;
> > +}
> > +
> > +/*
> > + * video ioctls
> > + */
> > +static int vip_querycap(struct file *file, void *priv,
> > + struct v4l2_capability *cap)
> > +{
> > + struct vip_stream *stream = file2stream(file);
> > + struct vip_port *port = stream->port;
> > + struct vip_dev *dev = port->dev;
> > +
> > + strscpy(cap->driver, VIP_MODULE_NAME, sizeof(cap->driver));
> > + strscpy(cap->card, VIP_MODULE_NAME, sizeof(cap->card));
> > +
> > + snprintf(cap->bus_info, sizeof(cap->bus_info),
> > + "platform:%s:%s:stream%1d", dev->shared->name, port->name,
> > + stream->stream_id);
> > + return 0;
> > +}
> > +
> > +static int vip_enuminput(struct file *file, void *priv,
> > + struct v4l2_input *inp)
> > +{
> > + struct vip_stream *stream = file2stream(file);
> > +
> > + if (inp->index)
> > + return -EINVAL;
> > +
> > + inp->type = V4L2_INPUT_TYPE_CAMERA;
> > + inp->std = stream->vfd->tvnorms;
> > + snprintf(inp->name, sizeof(inp->name), "camera %u", stream->vfd->num);
> > +
> > + return 0;
> > +}
> > +
> > +static int vip_g_input(struct file *file, void *priv, unsigned int *i)
> > +{
> > + *i = 0;
> > + return 0;
> > +}
> > +
> > +static int vip_s_input(struct file *file, void *priv, unsigned int i)
> > +{
> > + if (i != 0)
> > + return -EINVAL;
> > + return 0;
> > +}
> > +
> > +static int vip_querystd(struct file *file, void *fh, v4l2_std_id *std)
> > +{
> > + struct vip_stream *stream = file2stream(file);
> > + struct vip_port *port = stream->port;
> > +
> > + *std = stream->vfd->tvnorms;
> > + v4l2_subdev_call(port->subdev, video, querystd, std);
> > + vip_dbg(1, stream, "querystd: 0x%lx\n", (unsigned long)*std);
> > + return 0;
> > +}
> > +
> > +static int vip_g_std(struct file *file, void *fh, v4l2_std_id *std)
> > +{
> > + struct vip_stream *stream = file2stream(file);
> > + struct vip_port *port = stream->port;
> > +
> > + *std = stream->vfd->tvnorms;
> > + v4l2_subdev_call(port->subdev, video, g_std_output, std);
>
> g_std_output? Shouldn't this just be g_std? The g_std_output op is for
> video transmitters.
Yes, I'll fix those.
>
> > + vip_dbg(1, stream, "g_std: 0x%lx\n", (unsigned long)*std);
> > +
> > + return 0;
> > +}
> > +
> > +static int vip_s_std(struct file *file, void *fh, v4l2_std_id std)
> > +{
> > + struct vip_stream *stream = file2stream(file);
> > + struct vip_port *port = stream->port;
> > +
> > + vip_dbg(1, stream, "s_std: 0x%lx\n", (unsigned long)std);
> > +
> > + if (!(std & stream->vfd->tvnorms)) {
> > + vip_dbg(1, stream, "s_std after check: 0x%lx\n",
> > + (unsigned long)std);
> > + return -EINVAL;
> > + }
> > +
> > + v4l2_subdev_call(port->subdev, video, s_std_output, std);
>
> Ditto.
Yes, I'll fix those.
>
> > + return 0;
> > +}
> > +
> > +static int vip_enum_fmt_vid_cap(struct file *file, void *priv,
> > + struct v4l2_fmtdesc *f)
> > +{
> > + struct vip_stream *stream = file2stream(file);
> > + struct vip_port *port = stream->port;
> > + struct vip_fmt *fmt;
> > +
> > + vip_dbg(3, stream, "enum_fmt index:%d\n", f->index);
> > + if (f->index >= port->num_active_fmt)
> > + return -EINVAL;
> > +
> > + fmt = port->active_fmt[f->index];
> > +
> > + f->pixelformat = fmt->fourcc;
> > + f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
>
> No need to set the type field.
Ok.
>
> > + vip_dbg(3, stream, "enum_fmt fourcc:%s\n",
> > + fourcc_to_str(f->pixelformat));
>
> Excessive debugging.
Why excessive?
>
> > +
> > + return 0;
> > +}
> > +
> > +static int vip_enum_framesizes(struct file *file, void *priv,
> > + struct v4l2_frmsizeenum *f)
> > +{
> > + struct vip_stream *stream = file2stream(file);
> > + struct vip_port *port = stream->port;
> > + struct vip_fmt *fmt;
> > + struct v4l2_subdev_frame_size_enum fse;
> > + int ret;
> > +
> > + fmt = find_port_format_by_pix(port, f->pixel_format);
> > + if (!fmt)
> > + return -EINVAL;
> > +
> > + fse.index = f->index;
> > + fse.pad = port->source_pad;
> > + fse.code = fmt->code;
> > + fse.which = V4L2_SUBDEV_FORMAT_ACTIVE;
> > + ret = v4l2_subdev_call(port->subdev, pad, enum_frame_size, NULL, &fse);
> > + if (ret == -ENOIOCTLCMD && !f->index) {
> > + /*
> > + * if subdev does not support enum_frame_size
> > + * then use get_fmt
>
> I don't think that's right. If the subdev doesn't support this, then
> this ioctl should be disabled altogether. Typically this ioctl is only
> valid for sensor subdevs, not for video receivers.
>
> Use v4l2_subdev_has_op() and v4l2_disable_ioctl().
You mean to check if the subdev support this ioctl and if not disable it
for the current video device only, correct?
>
> > + */
> > + struct v4l2_subdev_format format = {
> > + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> > + .pad = port->source_pad,
> > + };
> > + ret = v4l2_subdev_call(port->subdev, pad, get_fmt, NULL,
> > + &format);
> > + if (ret)
> > + return ret;
> > +
> > + fse.max_width = format.format.width;
> > + fse.max_height = format.format.height;
> > + } else if (ret) {
> > + return -EINVAL;
> > + }
> > +
> > + vip_dbg(1, stream, "%s: index: %d code: %x W:[%d,%d] H:[%d,%d]\n",
> > + __func__, fse.index, fse.code, fse.min_width, fse.max_width,
> > + fse.min_height, fse.max_height);
> > +
> > + f->type = V4L2_FRMSIZE_TYPE_DISCRETE;
> > + f->discrete.width = fse.max_width;
> > + f->discrete.height = fse.max_height;
> > +
> > + return 0;
> > +}
> > +
> > +static int vip_enum_frameintervals(struct file *file, void *priv,
> > + struct v4l2_frmivalenum *f)
> > +{
> > + struct vip_stream *stream = file2stream(file);
> > + struct vip_port *port = stream->port;
> > + struct vip_fmt *fmt;
> > + struct v4l2_subdev_frame_interval_enum fie = {
> > + .index = f->index,
> > + .width = f->width,
> > + .height = f->height,
> > + .which = V4L2_SUBDEV_FORMAT_ACTIVE,
> > + };
> > + int ret;
> > +
> > + fmt = find_port_format_by_pix(port, f->pixel_format);
> > + if (!fmt)
> > + return -EINVAL;
> > +
> > + fie.code = fmt->code;
> > + ret = v4l2_subdev_call(port->subdev, pad, enum_frame_interval,
> > + NULL, &fie);
> > + if (ret)
> > + return ret;
> > + f->type = V4L2_FRMIVAL_TYPE_DISCRETE;
> > + f->discrete = fie.interval;
>
> Same here: disable this ioctl if the subdev doesn't support enum_frame_interval.
>
> > +
> > + return 0;
> > +}
> > +
> > +static int vip_g_parm(struct file *file, void *priv,
> > + struct v4l2_streamparm *parm)
> > +{
> > + struct vip_stream *stream = file2stream(file);
> > + struct vip_port *port = stream->port;
> > +
> > + return v4l2_g_parm_cap(stream->vfd, port->subdev, parm);
> > +}
> > +
> > +static int vip_s_parm(struct file *file, void *priv,
> > + struct v4l2_streamparm *parm)
> > +{
> > + struct vip_stream *stream = file2stream(file);
> > + struct vip_port *port = stream->port;
> > +
> > + return v4l2_s_parm_cap(stream->vfd, port->subdev, parm);
>
> Same here: typically this is not supported for video receivers.
>
> > +}
> > +
> > +static int vip_calc_format_size(struct vip_port *port,
> > + struct vip_fmt *fmt,
> > + struct v4l2_format *f)
> > +{
> > + enum v4l2_field *field;
> > + unsigned int stride;
> > +
> > + if (!fmt) {
> > + vip_dbg(2, port,
> > + "no vip_fmt format provided!\n");
> > + return -EINVAL;
> > + }
> > +
> > + field = &f->fmt.pix.field;
> > + if (*field == V4L2_FIELD_ANY)
> > + *field = V4L2_FIELD_NONE;
> > + else if (V4L2_FIELD_NONE != *field && V4L2_FIELD_ALTERNATE != *field)
> > + return -EINVAL;
> > +
> > + v4l_bound_align_image(&f->fmt.pix.width, MIN_W, MAX_W, W_ALIGN,
> > + &f->fmt.pix.height, MIN_H, MAX_H, H_ALIGN,
> > + S_ALIGN);
> > +
> > + stride = f->fmt.pix.width * (fmt->vpdma_fmt[0]->depth >> 3);
> > + if (stride > f->fmt.pix.bytesperline)
> > + f->fmt.pix.bytesperline = stride;
> > +
> > + f->fmt.pix.bytesperline = clamp_t(u32, f->fmt.pix.bytesperline,
> > + stride, VPDMA_MAX_STRIDE);
> > + f->fmt.pix.bytesperline = ALIGN(f->fmt.pix.bytesperline,
> > + VPDMA_STRIDE_ALIGN);
> > +
> > + f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;
> > + if (fmt->coplanar) {
> > + f->fmt.pix.sizeimage += f->fmt.pix.height *
> > + f->fmt.pix.bytesperline *
> > + fmt->vpdma_fmt[VIP_CHROMA]->depth >> 3;
> > + }
> > +
> > + f->fmt.pix.colorspace = fmt->colorspace;
> > + f->fmt.pix.priv = 0;
>
> No need to set this.
You mean pix.priv? I thought I remember v4l2-compliance complaining about
something like this?
>
> > +
> > + vip_dbg(3, port, "calc_format_size: fourcc:%s size: %dx%d bpl:%d img_size:%d\n",
> > + fourcc_to_str(f->fmt.pix.pixelformat),
> > + f->fmt.pix.width, f->fmt.pix.height,
> > + f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);
> > +
> > + return 0;
> > +}
> > +
> > +static inline bool vip_is_size_dma_aligned(u32 bpp, u32 width)
> > +{
> > + return ((width * bpp) == ALIGN(width * bpp, VPDMA_STRIDE_ALIGN));
> > +}
> > +
> > +static int vip_try_fmt_vid_cap(struct file *file, void *priv,
> > + struct v4l2_format *f)
> > +{
> > + struct vip_stream *stream = file2stream(file);
> > + struct vip_port *port = stream->port;
> > + struct v4l2_subdev_frame_size_enum fse;
> > + struct vip_fmt *fmt;
> > + u32 best_width, best_height, largest_width, largest_height;
> > + int ret, found;
> > + enum vip_csc_state csc_direction;
> > +
> > + vip_dbg(3, stream, "try_fmt fourcc:%s size: %dx%d\n",
> > + fourcc_to_str(f->fmt.pix.pixelformat),
> > + f->fmt.pix.width, f->fmt.pix.height);
> > +
> > + fmt = find_port_format_by_pix(port, f->fmt.pix.pixelformat);
> > + if (!fmt) {
> > + vip_dbg(2, stream,
> > + "Fourcc format (0x%08x) not found.\n",
> > + f->fmt.pix.pixelformat);
> > +
> > + /* Just get the first one enumerated */
> > + fmt = port->active_fmt[0];
> > + f->fmt.pix.pixelformat = fmt->fourcc;
> > + }
> > +
> > + csc_direction = vip_csc_direction(fmt->code, fmt->finfo);
> > + if (csc_direction != VIP_CSC_NA) {
> > + if (!is_csc_available(port)) {
> > + vip_dbg(2, stream,
> > + "CSC not available for Fourcc format (0x%08x).\n",
> > + f->fmt.pix.pixelformat);
> > +
> > + /* Just get the first one enumerated */
> > + fmt = port->active_fmt[0];
> > + f->fmt.pix.pixelformat = fmt->fourcc;
> > + /* re-evaluate the csc_direction here */
> > + csc_direction = vip_csc_direction(fmt->code,
> > + fmt->finfo);
> > + } else {
> > + vip_dbg(3, stream, "CSC active on Port %c: going %s\n",
> > + port->port_id == VIP_PORTA ? 'A' : 'B',
> > + (csc_direction == VIP_CSC_Y2R) ? "Y2R" : "R2Y");
> > + }
> > + }
> > +
> > + /*
> > + * Given that sensors might support multiple mbus code we need
> > + * to use the one that matches the requested pixel format
> > + */
> > + port->try_mbus_framefmt = port->mbus_framefmt;
> > + port->try_mbus_framefmt.code = fmt->code;
> > +
> > + /* check for/find a valid width/height */
> > + ret = 0;
> > + found = false;
> > + best_width = 0;
> > + best_height = 0;
> > + largest_width = 0;
> > + largest_height = 0;
> > + fse.pad = port->source_pad;
> > + fse.code = fmt->code;
> > + fse.which = V4L2_SUBDEV_FORMAT_ACTIVE;
> > + for (fse.index = 0; ; fse.index++) {
> > + u32 bpp = fmt->vpdma_fmt[0]->depth >> 3;
> > +
> > + ret = v4l2_subdev_call(port->subdev, pad,
> > + enum_frame_size, NULL, &fse);
> > + if (ret == -ENOIOCTLCMD) {
> > + /*
> > + * if subdev does not support enum_frame_size
> > + * then just try to set_fmt directly
> > + */
> > + struct v4l2_subdev_format format = {
> > + .which = V4L2_SUBDEV_FORMAT_TRY,
> > + };
> > + struct v4l2_subdev_pad_config *pad_cfg;
> > +
> > + pad_cfg = v4l2_subdev_alloc_pad_config(port->subdev);
> > + if (!pad_cfg)
> > + return -ENOMEM;
> > +
> > + v4l2_fill_mbus_format(&format.format, &f->fmt.pix,
> > + fmt->code);
> > + ret = v4l2_subdev_call(port->subdev, pad, set_fmt,
> > + pad_cfg, &format);
> > + if (ret)
> > + /* here regardless of the reason we give up */
> > + break;
> > +
> > + if (f->fmt.pix.width == format.format.width &&
> > + f->fmt.pix.height == format.format.height) {
> > + found = true;
> > + vip_dbg(3, stream, "try_fmt loop:%d found direct match: %dx%d\n",
> > + fse.index, format.format.width,
> > + format.format.height);
> > + }
> > + largest_width = format.format.width;
> > + largest_height = format.format.height;
> > + best_width = format.format.width;
> > + best_height = format.format.height;
> > +
> > + v4l2_subdev_free_pad_config(pad_cfg);
> > + break;
> > +
> > + } else if (ret) {
> > + break;
> > + }
> > +
> > + vip_dbg(3, stream, "try_fmt loop:%d fourcc:%s size: %dx%d\n",
> > + fse.index, fourcc_to_str(f->fmt.pix.pixelformat),
> > + fse.max_width, fse.max_height);
> > +
> > + if (!vip_is_size_dma_aligned(bpp, fse.max_width))
> > + continue;
> > +
> > + if ((fse.max_width >= largest_width) &&
> > + (fse.max_height >= largest_height)) {
> > + vip_dbg(3, stream, "try_fmt loop:%d found new larger: %dx%d\n",
> > + fse.index, fse.max_width, fse.max_height);
> > + largest_width = fse.max_width;
> > + largest_height = fse.max_height;
> > + }
> > +
> > + if ((fse.max_width >= f->fmt.pix.width) &&
> > + (fse.max_height >= f->fmt.pix.height)) {
> > + vip_dbg(3, stream, "try_fmt loop:%d found at least larger: %dx%d\n",
> > + fse.index, fse.max_width, fse.max_height);
> > +
> > + if (!best_width ||
> > + ((abs(best_width - f->fmt.pix.width) >=
> > + abs(fse.max_width - f->fmt.pix.width)) &&
> > + (abs(best_height - f->fmt.pix.height) >=
> > + abs(fse.max_height - f->fmt.pix.height)))) {
> > + best_width = fse.max_width;
> > + best_height = fse.max_height;
> > + vip_dbg(3, stream, "try_fmt loop:%d found new best: %dx%d\n",
> > + fse.index, fse.max_width,
> > + fse.max_height);
> > + }
> > + }
> > +
> > + if ((f->fmt.pix.width == fse.max_width) &&
> > + (f->fmt.pix.height == fse.max_height)) {
> > + found = true;
> > + vip_dbg(3, stream, "try_fmt loop:%d found direct match: %dx%d\n",
> > + fse.index, fse.max_width,
> > + fse.max_height);
> > + break;
> > + }
> > +
> > + if ((f->fmt.pix.width >= fse.min_width) &&
> > + (f->fmt.pix.width <= fse.max_width) &&
> > + (f->fmt.pix.height >= fse.min_height) &&
> > + (f->fmt.pix.height <= fse.max_height)) {
> > + found = true;
> > + vip_dbg(3, stream, "try_fmt loop:%d found direct range match: %dx%d\n",
> > + fse.index, fse.max_width,
> > + fse.max_height);
> > + break;
> > + }
> > + }
> > +
> > + if (found) {
> > + port->try_mbus_framefmt.width = f->fmt.pix.width;
> > + port->try_mbus_framefmt.height = f->fmt.pix.height;
> > + /* No need to check for scaling */
> > + goto calc_size;
> > + } else if (largest_width && f->fmt.pix.width > largest_width) {
> > + port->try_mbus_framefmt.width = largest_width;
> > + port->try_mbus_framefmt.height = largest_height;
> > + } else if (best_width) {
> > + port->try_mbus_framefmt.width = best_width;
> > + port->try_mbus_framefmt.height = best_height;
> > + } else {
> > + /* use existing values as default */
> > + }
> > +
> > + vip_dbg(3, stream, "try_fmt best subdev size: %dx%d\n",
> > + port->try_mbus_framefmt.width,
> > + port->try_mbus_framefmt.height);
> > +
> > + if (is_scaler_available(port) &&
> > + csc_direction != VIP_CSC_Y2R &&
> > + !vip_is_mbuscode_raw(fmt->code) &&
> > + f->fmt.pix.height <= port->try_mbus_framefmt.height &&
> > + port->try_mbus_framefmt.height <= SC_MAX_PIXEL_HEIGHT &&
> > + port->try_mbus_framefmt.width <= SC_MAX_PIXEL_WIDTH) {
> > + /*
> > + * Scaler is only accessible if the dst colorspace is YUV.
> > + * As the input to the scaler must be in YUV mode only.
> > + *
> > + * Scaling up is allowed only horizontally.
> > + */
> > + unsigned int hratio, vratio, width_align, height_align;
> > + u32 bpp = fmt->vpdma_fmt[0]->depth >> 3;
> > +
> > + vip_dbg(3, stream, "Scaler active on Port %c: requesting %dx%d\n",
> > + port->port_id == VIP_PORTA ? 'A' : 'B',
> > + f->fmt.pix.width, f->fmt.pix.height);
> > +
> > + /* Just make sure everything is properly aligned */
> > + width_align = ALIGN(f->fmt.pix.width * bpp, VPDMA_STRIDE_ALIGN);
> > + width_align /= bpp;
> > + height_align = ALIGN(f->fmt.pix.height, 2);
> > +
> > + f->fmt.pix.width = width_align;
> > + f->fmt.pix.height = height_align;
> > +
> > + hratio = f->fmt.pix.width * 1000 /
> > + port->try_mbus_framefmt.width;
> > + vratio = f->fmt.pix.height * 1000 /
> > + port->try_mbus_framefmt.height;
> > + if (hratio < 125) {
> > + f->fmt.pix.width = port->try_mbus_framefmt.width / 8;
> > + vip_dbg(3, stream, "Horizontal scaling ratio out of range adjusting -> %d\n",
> > + f->fmt.pix.width);
> > + }
> > +
> > + if (vratio < 188) {
> > + f->fmt.pix.height = port->try_mbus_framefmt.height / 4;
> > + vip_dbg(3, stream, "Vertical scaling ratio out of range adjusting -> %d\n",
> > + f->fmt.pix.height);
> > + }
> > + vip_dbg(3, stream, "Scaler: got %dx%d\n",
> > + f->fmt.pix.width, f->fmt.pix.height);
> > + } else {
> > + /* use existing values as default */
> > + f->fmt.pix.width = port->try_mbus_framefmt.width;
> > + f->fmt.pix.height = port->try_mbus_framefmt.height;
> > + }
> > +
> > +calc_size:
> > + /* That we have a fmt calculate imagesize and bytesperline */
> > + return vip_calc_format_size(port, fmt, f);
> > +}
> > +
> > +static int vip_g_fmt_vid_cap(struct file *file, void *priv,
> > + struct v4l2_format *f)
> > +{
> > + struct vip_stream *stream = file2stream(file);
> > + struct vip_port *port = stream->port;
> > + struct vip_fmt *fmt = port->fmt;
> > +
> > + /* Use last known values or defaults */
> > + f->fmt.pix.width = stream->width;
> > + f->fmt.pix.height = stream->height;
> > + f->fmt.pix.pixelformat = port->fmt->fourcc;
> > + f->fmt.pix.field = stream->sup_field;
> > + f->fmt.pix.colorspace = port->fmt->colorspace;
> > + f->fmt.pix.bytesperline = stream->bytesperline;
> > + f->fmt.pix.sizeimage = stream->sizeimage;
> > +
> > + vip_dbg(3, stream,
> > + "g_fmt fourcc:%s code: %04x size: %dx%d bpl:%d img_size:%d\n",
> > + fourcc_to_str(f->fmt.pix.pixelformat),
> > + fmt->code,
> > + f->fmt.pix.width, f->fmt.pix.height,
> > + f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);
> > + vip_dbg(3, stream, "g_fmt vpdma data type: 0x%02X\n",
> > + port->fmt->vpdma_fmt[0]->data_type);
> > +
> > + return 0;
> > +}
> > +
> > +static int vip_s_fmt_vid_cap(struct file *file, void *priv,
> > + struct v4l2_format *f)
> > +{
> > + struct vip_stream *stream = file2stream(file);
> > + struct vip_port *port = stream->port;
> > + struct v4l2_subdev_format sfmt;
> > + struct v4l2_mbus_framefmt *mf;
> > + enum vip_csc_state csc_direction;
> > + int ret;
> > +
> > + vip_dbg(3, stream, "s_fmt input fourcc:%s size: %dx%d bpl:%d img_size:%d\n",
> > + fourcc_to_str(f->fmt.pix.pixelformat),
> > + f->fmt.pix.width, f->fmt.pix.height,
> > + f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);
> > +
> > + ret = vip_try_fmt_vid_cap(file, priv, f);
> > + if (ret)
> > + return ret;
> > +
> > + vip_dbg(3, stream, "s_fmt try_fmt fourcc:%s size: %dx%d bpl:%d img_size:%d\n",
> > + fourcc_to_str(f->fmt.pix.pixelformat),
> > + f->fmt.pix.width, f->fmt.pix.height,
> > + f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);
> > +
> > + if (vb2_is_busy(&stream->vb_vidq)) {
> > + vip_err(stream, "%s queue busy\n", __func__);
> > + return -EBUSY;
> > + }
> > +
> > + /*
> > + * Check if we need the scaler or not
> > + *
> > + * Since on previous S_FMT call the scaler might have been
> > + * allocated if it is not needed in this instance we will
> > + * attempt to free it just in case.
> > + *
> > + * free_scaler() is harmless unless the current port
> > + * allocated it.
> > + */
> > + if (f->fmt.pix.width == port->try_mbus_framefmt.width &&
> > + f->fmt.pix.height == port->try_mbus_framefmt.height)
> > + free_scaler(port);
> > + else
> > + allocate_scaler(port);
> > +
> > + port->fmt = find_port_format_by_pix(port,
> > + f->fmt.pix.pixelformat);
> > + stream->width = f->fmt.pix.width;
> > + stream->height = f->fmt.pix.height;
> > + stream->bytesperline = f->fmt.pix.bytesperline;
> > + stream->sizeimage = f->fmt.pix.sizeimage;
> > + stream->sup_field = f->fmt.pix.field;
> > + stream->field = f->fmt.pix.field;
> > +
> > + port->c_rect.left = 0;
> > + port->c_rect.top = 0;
> > + port->c_rect.width = stream->width;
> > + port->c_rect.height = stream->height;
> > +
> > + /*
> > + * Check if we need the csc unit or not
> > + *
> > + * Since on previous S_FMT call, the csc might have been
> > + * allocated if it is not needed in this instance we will
> > + * attempt to free it just in case.
> > + *
> > + * free_csc() is harmless unless the current port
> > + * allocated it.
> > + */
> > + csc_direction = vip_csc_direction(port->fmt->code, port->fmt->finfo);
> > + if (csc_direction == VIP_CSC_NA)
> > + free_csc(port);
> > + else
> > + allocate_csc(port, csc_direction);
> > +
> > + if (stream->sup_field == V4L2_FIELD_ALTERNATE)
> > + port->flags |= FLAG_INTERLACED;
> > + else
> > + port->flags &= ~FLAG_INTERLACED;
> > +
> > + vip_dbg(3, stream, "s_fmt fourcc:%s size: %dx%d bpl:%d img_size:%d\n",
> > + fourcc_to_str(f->fmt.pix.pixelformat),
> > + f->fmt.pix.width, f->fmt.pix.height,
> > + f->fmt.pix.bytesperline, f->fmt.pix.sizeimage);
> > +
> > + mf = &sfmt.format;
> > + v4l2_fill_mbus_format(mf, &f->fmt.pix, port->fmt->code);
> > + /* Make sure to use the subdev size found in the try_fmt */
> > + mf->width = port->try_mbus_framefmt.width;
> > + mf->height = port->try_mbus_framefmt.height;
> > +
> > + vip_dbg(3, stream, "s_fmt pix_to_mbus mbus_code: %04X size: %dx%d\n",
> > + mf->code,
> > + mf->width, mf->height);
> > +
> > + sfmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
> > + sfmt.pad = port->source_pad;
> > + ret = v4l2_subdev_call(port->subdev, pad, set_fmt, NULL, &sfmt);
> > + if (ret) {
> > + vip_dbg(1, stream, "set_fmt failed in subdev\n");
> > + return ret;
> > + }
> > +
> > + /* Save it */
> > + port->mbus_framefmt = *mf;
> > +
> > + vip_dbg(3, stream, "s_fmt subdev fmt mbus_code: %04X size: %dx%d\n",
> > + port->mbus_framefmt.code,
> > + port->mbus_framefmt.width, port->mbus_framefmt.height);
> > + vip_dbg(3, stream, "s_fmt vpdma data type: 0x%02X\n",
> > + port->fmt->vpdma_fmt[0]->data_type);
> > +
> > + return 0;
> > +}
> > +
> > +/*
> > + * Does the exact opposite of set_fmt_params
> > + * It makes sure the DataPath register is sane after tear down
> > + */
> > +static void unset_fmt_params(struct vip_stream *stream)
> > +{
> > + struct vip_dev *dev = stream->port->dev;
> > + struct vip_port *port = stream->port;
> > +
> > + stream->sequence = 0;
> > + if (stream->port->flags & FLAG_INTERLACED)
> > + stream->field = V4L2_FIELD_TOP;
> > +
> > + if (port->csc == VIP_CSC_Y2R) {
> > + if (port->port_id == VIP_PORTA) {
> > + vip_set_slice_path(dev, VIP_CSC_SRC_DATA_SELECT, 0);
> > + vip_set_slice_path(dev,
> > + VIP_MULTI_CHANNEL_DATA_SELECT, 0);
> > + vip_set_slice_path(dev, VIP_RGB_OUT_HI_DATA_SELECT, 0);
> > + vip_set_slice_path(dev, VIP_RGB_SRC_DATA_SELECT, 0);
> > + } else {
> > + vip_set_slice_path(dev, VIP_CSC_SRC_DATA_SELECT, 0);
> > + vip_set_slice_path(dev,
> > + VIP_MULTI_CHANNEL_DATA_SELECT, 0);
> > + vip_set_slice_path(dev, VIP_RGB_OUT_LO_DATA_SELECT, 0);
> > + }
> > + /* We are done */
> > + return;
> > + } else if (port->csc == VIP_CSC_R2Y) {
> > + if (port->scaler && port->fmt->coplanar) {
> > + if (port->port_id == VIP_PORTA) {
> > + vip_set_slice_path(dev,
> > + VIP_CSC_SRC_DATA_SELECT, 0);
> > + vip_set_slice_path(dev,
> > + VIP_SC_SRC_DATA_SELECT, 0);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_1_SRC_DATA_SELECT,
> > + 0);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_1_DATA_BYPASS, 0);
> > + vip_set_slice_path(dev,
> > + VIP_RGB_OUT_HI_DATA_SELECT,
> > + 0);
> > + }
> > + } else if (port->scaler) {
> > + if (port->port_id == VIP_PORTA) {
> > + vip_set_slice_path(dev,
> > + VIP_CSC_SRC_DATA_SELECT, 0);
> > + vip_set_slice_path(dev,
> > + VIP_SC_SRC_DATA_SELECT, 0);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_1_SRC_DATA_SELECT,
> > + 0);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_1_DATA_BYPASS, 0);
> > + vip_set_slice_path(dev,
> > + VIP_RGB_OUT_HI_DATA_SELECT,
> > + 0);
> > + }
> > + } else if (port->fmt->coplanar) {
> > + if (port->port_id == VIP_PORTA) {
> > + vip_set_slice_path(dev,
> > + VIP_CSC_SRC_DATA_SELECT, 0);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_1_SRC_DATA_SELECT,
> > + 0);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_1_DATA_BYPASS, 0);
> > + vip_set_slice_path(dev,
> > + VIP_RGB_OUT_HI_DATA_SELECT,
> > + 0);
> > + }
> > + } else {
> > + if (port->port_id == VIP_PORTA) {
> > + vip_set_slice_path(dev,
> > + VIP_CSC_SRC_DATA_SELECT, 0);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_1_SRC_DATA_SELECT,
> > + 0);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_1_DATA_BYPASS, 0);
> > + vip_set_slice_path(dev,
> > + VIP_RGB_OUT_HI_DATA_SELECT,
> > + 0);
> > + }
> > + }
> > + /* We are done */
> > + return;
> > + } else if (v4l2_is_format_rgb(port->fmt->finfo)) {
> > + if (port->port_id == VIP_PORTA) {
> > + vip_set_slice_path(dev,
> > + VIP_MULTI_CHANNEL_DATA_SELECT, 0);
> > + vip_set_slice_path(dev, VIP_RGB_OUT_LO_DATA_SELECT, 0);
> > + }
> > + /* We are done */
> > + return;
> > + }
> > +
> > + if (port->scaler && port->fmt->coplanar) {
> > + if (port->port_id == VIP_PORTA) {
> > + vip_set_slice_path(dev, VIP_SC_SRC_DATA_SELECT, 0);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_1_SRC_DATA_SELECT, 0);
> > + vip_set_slice_path(dev, VIP_CHR_DS_1_DATA_BYPASS, 0);
> > + vip_set_slice_path(dev, VIP_RGB_OUT_HI_DATA_SELECT, 0);
> > + } else {
> > + vip_set_slice_path(dev, VIP_SC_SRC_DATA_SELECT, 0);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_2_SRC_DATA_SELECT, 0);
> > + vip_set_slice_path(dev, VIP_CHR_DS_1_DATA_BYPASS, 0);
> > + vip_set_slice_path(dev, VIP_RGB_OUT_LO_DATA_SELECT, 0);
> > + vip_set_slice_path(dev,
> > + VIP_MULTI_CHANNEL_DATA_SELECT, 0);
> > + }
> > + } else if (port->scaler) {
> > + if (port->port_id == VIP_PORTA) {
> > + vip_set_slice_path(dev, VIP_SC_SRC_DATA_SELECT, 0);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_1_SRC_DATA_SELECT, 0);
> > + vip_set_slice_path(dev, VIP_CHR_DS_1_DATA_BYPASS, 0);
> > + vip_set_slice_path(dev, VIP_RGB_OUT_HI_DATA_SELECT, 0);
> > + } else {
> > + vip_set_slice_path(dev, VIP_SC_SRC_DATA_SELECT, 0);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_2_SRC_DATA_SELECT, 0);
> > + vip_set_slice_path(dev, VIP_CHR_DS_1_DATA_BYPASS, 0);
> > + vip_set_slice_path(dev, VIP_CHR_DS_2_DATA_BYPASS, 0);
> > + vip_set_slice_path(dev, VIP_RGB_OUT_HI_DATA_SELECT, 0);
> > + }
> > + } else if (port->fmt->coplanar) {
> > + if (port->port_id == VIP_PORTA) {
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_1_SRC_DATA_SELECT, 0);
> > + vip_set_slice_path(dev, VIP_CHR_DS_1_DATA_BYPASS, 0);
> > + vip_set_slice_path(dev, VIP_RGB_OUT_HI_DATA_SELECT, 0);
> > + } else {
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_2_SRC_DATA_SELECT, 0);
> > + vip_set_slice_path(dev, VIP_CHR_DS_2_DATA_BYPASS, 0);
> > + vip_set_slice_path(dev,
> > + VIP_MULTI_CHANNEL_DATA_SELECT, 0);
> > + vip_set_slice_path(dev, VIP_RGB_OUT_LO_DATA_SELECT, 0);
> > + }
> > + } else {
> > + /*
> > + * We undo all data path setting except for the multi
> > + * stream case.
> > + * Because we cannot disrupt other on-going capture if only
> > + * one stream is terminated the other might still be going
> > + */
> > + vip_set_slice_path(dev, VIP_MULTI_CHANNEL_DATA_SELECT, 1);
> > + vip_set_slice_path(dev, VIP_RGB_OUT_LO_DATA_SELECT, 0);
> > + }
> > +}
> > +
> > +/*
> > + * Set the registers that are modified when the video format changes.
> > + */
> > +static void set_fmt_params(struct vip_stream *stream)
> > +{
>
> Hmm, this is a *very* long function. Perhaps this could be split up a bit,
> or reorganized?
Yeah, I'll start by removing the extra comment lines and reformat it.
>
> > + struct vip_dev *dev = stream->port->dev;
> > + struct vip_port *port = stream->port;
> > +
> > + stream->sequence = 0;
> > + if (stream->port->flags & FLAG_INTERLACED)
> > + stream->field = V4L2_FIELD_TOP;
> > +
> > + if (port->csc == VIP_CSC_Y2R) {
> > + port->flags &= ~FLAG_MULT_PORT;
> > + /* Set alpha component in background color */
> > + vpdma_set_bg_color(dev->shared->vpdma,
> > + (struct vpdma_data_format *)
> > + port->fmt->vpdma_fmt[0],
> > + 0xff);
> > + if (port->port_id == VIP_PORTA) {
> > + /*
> > + * Input A: YUV422
> > + * Output: Y_UP/UV_UP: RGB
> > + * CSC_SRC_SELECT = 1
> > + * RGB_OUT_HI_SELECT = 1
> > + * RGB_SRC_SELECT = 1
> > + * MULTI_CHANNEL_SELECT = 0
>
> It's a bit pointless to comment what the register values should be when you
> set them in the code below. I'd drop that part, it will make the code
> shorter.
Ok.
>
> > + */
> > + vip_set_slice_path(dev, VIP_CSC_SRC_DATA_SELECT, 1);
> > + vip_set_slice_path(dev,
> > + VIP_MULTI_CHANNEL_DATA_SELECT, 0);
>
> For readability purposes I think it is better to keep this on one line. Same for
> the other vip_set_slice_path calls.
Ok.
>
> > + vip_set_slice_path(dev, VIP_RGB_OUT_HI_DATA_SELECT, 1);
> > + vip_set_slice_path(dev, VIP_RGB_SRC_DATA_SELECT, 1);
> > + } else {
> > + /*
> > + * Input B: YUV422
> > + * Output: Y_UP/UV_UP: RGB
> > + * CSC_SRC_SELECT = 2
> > + * RGB_OUT_LO_SELECT = 1
> > + * MULTI_CHANNEL_SELECT = 0
> > + */
> > + vip_set_slice_path(dev, VIP_CSC_SRC_DATA_SELECT, 2);
> > + vip_set_slice_path(dev,
> > + VIP_MULTI_CHANNEL_DATA_SELECT, 0);
> > + vip_set_slice_path(dev, VIP_RGB_OUT_LO_DATA_SELECT, 1);
> > + }
> > + /* We are done */
> > + return;
> > + } else if (port->csc == VIP_CSC_R2Y) {
> > + port->flags &= ~FLAG_MULT_PORT;
> > + if (port->scaler && port->fmt->coplanar) {
> > + if (port->port_id == VIP_PORTA) {
> > + /*
> > + * Input A: RGB
> > + * Output: Y_UP/UV_UP: Scaled YUV420
> > + * CSC_SRC_SELECT = 4
> > + * SC_SRC_SELECT = 1
> > + * CHR_DS_1_SRC_SELECT = 1
> > + * CHR_DS_1_BYPASS = 0
> > + * RGB_OUT_HI_SELECT = 0
> > + */
> > + vip_set_slice_path(dev,
> > + VIP_CSC_SRC_DATA_SELECT, 4);
> > + vip_set_slice_path(dev,
> > + VIP_SC_SRC_DATA_SELECT, 1);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_1_SRC_DATA_SELECT,
> > + 1);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_1_DATA_BYPASS, 0);
> > + vip_set_slice_path(dev,
> > + VIP_RGB_OUT_HI_DATA_SELECT,
> > + 0);
> > + } else {
> > + vip_err(stream, "RGB sensor can only be on Port A\n");
> > + }
> > + } else if (port->scaler) {
> > + if (port->port_id == VIP_PORTA) {
> > + /*
> > + * Input A: RGB
> > + * Output: Y_UP: Scaled YUV422
> > + * CSC_SRC_SELECT = 4
> > + * SC_SRC_SELECT = 1
> > + * CHR_DS_1_SRC_SELECT = 1
> > + * CHR_DS_1_BYPASS = 1
> > + * RGB_OUT_HI_SELECT = 0
> > + */
> > + vip_set_slice_path(dev,
> > + VIP_CSC_SRC_DATA_SELECT, 4);
> > + vip_set_slice_path(dev,
> > + VIP_SC_SRC_DATA_SELECT, 1);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_1_SRC_DATA_SELECT,
> > + 1);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_1_DATA_BYPASS, 1);
> > + vip_set_slice_path(dev,
> > + VIP_RGB_OUT_HI_DATA_SELECT,
> > + 0);
> > + } else {
> > + vip_err(stream, "RGB sensor can only be on Port A\n");
> > + }
> > + } else if (port->fmt->coplanar) {
> > + if (port->port_id == VIP_PORTA) {
> > + /*
> > + * Input A: RGB
> > + * Output: Y_UP/UV_UP: YUV420
> > + * CSC_SRC_SELECT = 4
> > + * CHR_DS_1_SRC_SELECT = 2
> > + * CHR_DS_1_BYPASS = 0
> > + * RGB_OUT_HI_SELECT = 0
> > + */
> > + vip_set_slice_path(dev,
> > + VIP_CSC_SRC_DATA_SELECT, 4);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_1_SRC_DATA_SELECT,
> > + 2);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_1_DATA_BYPASS, 0);
> > + vip_set_slice_path(dev,
> > + VIP_RGB_OUT_HI_DATA_SELECT,
> > + 0);
> > + } else {
> > + vip_err(stream, "RGB sensor can only be on Port A\n");
> > + }
> > + } else {
> > + if (port->port_id == VIP_PORTA) {
> > + /*
> > + * Input A: RGB
> > + * Output: Y_UP/UV_UP: YUV420
> > + * CSC_SRC_SELECT = 4
> > + * CHR_DS_1_SRC_SELECT = 2
> > + * CHR_DS_1_BYPASS = 1
> > + * RGB_OUT_HI_SELECT = 0
> > + */
> > + vip_set_slice_path(dev,
> > + VIP_CSC_SRC_DATA_SELECT, 4);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_1_SRC_DATA_SELECT,
> > + 2);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_1_DATA_BYPASS, 1);
> > + vip_set_slice_path(dev,
> > + VIP_RGB_OUT_HI_DATA_SELECT,
> > + 0);
> > + } else {
> > + vip_err(stream, "RGB sensor can only be on Port A\n");
> > + }
> > + }
> > + /* We are done */
> > + return;
> > + } else if (v4l2_is_format_rgb(port->fmt->finfo)) {
> > + port->flags &= ~FLAG_MULT_PORT;
> > + /* Set alpha component in background color */
> > + vpdma_set_bg_color(dev->shared->vpdma,
> > + (struct vpdma_data_format *)
> > + port->fmt->vpdma_fmt[0],
> > + 0xff);
> > + if (port->port_id == VIP_PORTA) {
> > + /*
> > + * Input A: RGB
> > + * Output: Y_LO/UV_LO: RGB
> > + * RGB_OUT_LO_SELECT = 1
> > + * MULTI_CHANNEL_SELECT = 1
> > + */
> > + vip_set_slice_path(dev,
> > + VIP_MULTI_CHANNEL_DATA_SELECT, 1);
> > + vip_set_slice_path(dev, VIP_RGB_OUT_LO_DATA_SELECT, 1);
> > + } else {
> > + vip_err(stream, "RGB sensor can only be on Port A\n");
> > + }
> > + /* We are done */
> > + return;
> > + }
> > +
> > + if (port->scaler && port->fmt->coplanar) {
> > + port->flags &= ~FLAG_MULT_PORT;
> > + if (port->port_id == VIP_PORTA) {
> > + /*
> > + * Input A: YUV422
> > + * Output: Y_UP/UV_UP: Scaled YUV420
> > + * SC_SRC_SELECT = 2
> > + * CHR_DS_1_SRC_SELECT = 1
> > + * CHR_DS_1_BYPASS = 0
> > + * RGB_OUT_HI_SELECT = 0
> > + */
> > + vip_set_slice_path(dev, VIP_SC_SRC_DATA_SELECT, 2);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_1_SRC_DATA_SELECT, 1);
> > + vip_set_slice_path(dev, VIP_CHR_DS_1_DATA_BYPASS, 0);
> > + vip_set_slice_path(dev, VIP_RGB_OUT_HI_DATA_SELECT, 0);
> > + } else {
> > + /*
> > + * Input B: YUV422
> > + * Output: Y_LO/UV_LO: Scaled YUV420
> > + * SC_SRC_SELECT = 3
> > + * CHR_DS_2_SRC_SELECT = 1
> > + * RGB_OUT_LO_SELECT = 0
> > + * MULTI_CHANNEL_SELECT = 0
> > + */
> > + vip_set_slice_path(dev, VIP_SC_SRC_DATA_SELECT, 3);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_2_SRC_DATA_SELECT, 1);
> > + vip_set_slice_path(dev, VIP_CHR_DS_1_DATA_BYPASS, 0);
> > + vip_set_slice_path(dev, VIP_RGB_OUT_LO_DATA_SELECT, 0);
> > + vip_set_slice_path(dev,
> > + VIP_MULTI_CHANNEL_DATA_SELECT, 0);
> > + }
> > + } else if (port->scaler) {
> > + port->flags &= ~FLAG_MULT_PORT;
> > + if (port->port_id == VIP_PORTA) {
> > + /*
> > + * Input A: YUV422
> > + * Output: Y_UP: Scaled YUV422
> > + * SC_SRC_SELECT = 2
> > + * CHR_DS_1_SRC_SELECT = 1
> > + * CHR_DS_1_BYPASS = 1
> > + * RGB_OUT_HI_SELECT = 0
> > + */
> > + vip_set_slice_path(dev, VIP_SC_SRC_DATA_SELECT, 2);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_1_SRC_DATA_SELECT, 1);
> > + vip_set_slice_path(dev, VIP_CHR_DS_1_DATA_BYPASS, 1);
> > + vip_set_slice_path(dev, VIP_RGB_OUT_HI_DATA_SELECT, 0);
> > + } else {
> > + /*
> > + * Input B: YUV422
> > + * Output: UV_UP: Scaled YUV422
> > + * SC_SRC_SELECT = 3
> > + * CHR_DS_2_SRC_SELECT = 1
> > + * CHR_DS_1_BYPASS = 1
> > + * CHR_DS_2_BYPASS = 1
> > + * RGB_OUT_HI_SELECT = 0
> > + */
> > + vip_set_slice_path(dev, VIP_SC_SRC_DATA_SELECT, 3);
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_2_SRC_DATA_SELECT, 1);
> > + vip_set_slice_path(dev, VIP_CHR_DS_1_DATA_BYPASS, 1);
> > + vip_set_slice_path(dev, VIP_CHR_DS_2_DATA_BYPASS, 1);
> > + vip_set_slice_path(dev, VIP_RGB_OUT_HI_DATA_SELECT, 0);
> > + }
> > + } else if (port->fmt->coplanar) {
> > + port->flags &= ~FLAG_MULT_PORT;
> > + if (port->port_id == VIP_PORTA) {
> > + /*
> > + * Input A: YUV422
> > + * Output: Y_UP/UV_UP: YUV420
> > + * CHR_DS_1_SRC_SELECT = 3
> > + * CHR_DS_1_BYPASS = 0
> > + * RGB_OUT_HI_SELECT = 0
> > + */
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_1_SRC_DATA_SELECT, 3);
> > + vip_set_slice_path(dev, VIP_CHR_DS_1_DATA_BYPASS, 0);
> > + vip_set_slice_path(dev, VIP_RGB_OUT_HI_DATA_SELECT, 0);
> > + } else {
> > + /*
> > + * Input B: YUV422
> > + * Output: Y_LO/UV_LO: YUV420
> > + * CHR_DS_2_SRC_SELECT = 4
> > + * CHR_DS_2_BYPASS = 0
> > + * RGB_OUT_LO_SELECT = 0
> > + * MULTI_CHANNEL_SELECT = 0
> > + */
> > + vip_set_slice_path(dev,
> > + VIP_CHR_DS_2_SRC_DATA_SELECT, 4);
> > + vip_set_slice_path(dev, VIP_CHR_DS_2_DATA_BYPASS, 0);
> > + vip_set_slice_path(dev,
> > + VIP_MULTI_CHANNEL_DATA_SELECT, 0);
> > + vip_set_slice_path(dev, VIP_RGB_OUT_LO_DATA_SELECT, 0);
> > + }
> > + } else {
> > + port->flags |= FLAG_MULT_PORT;
> > + /*
> > + * Input A/B: YUV422
> > + * Output: Y_LO: YUV422 - UV_LO: YUV422
> > + * MULTI_CHANNEL_SELECT = 1
> > + * RGB_OUT_LO_SELECT = 0
> > + */
> > + vip_set_slice_path(dev, VIP_MULTI_CHANNEL_DATA_SELECT, 1);
> > + vip_set_slice_path(dev, VIP_RGB_OUT_LO_DATA_SELECT, 0);
> > + }
> > +}
> > +
> > +static int vip_g_selection(struct file *file, void *fh,
> > + struct v4l2_selection *s)
> > +{
> > + struct vip_stream *stream = file2stream(file);
> > +
> > + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
> > + return -EINVAL;
> > +
> > + switch (s->target) {
> > + case V4L2_SEL_TGT_COMPOSE_DEFAULT:
> > + case V4L2_SEL_TGT_COMPOSE_BOUNDS:
> > + case V4L2_SEL_TGT_CROP_BOUNDS:
> > + case V4L2_SEL_TGT_CROP_DEFAULT:
> > + s->r.left = 0;
> > + s->r.top = 0;
> > + s->r.width = stream->width;
> > + s->r.height = stream->height;
> > + return 0;
> > +
> > + case V4L2_SEL_TGT_COMPOSE:
> > + case V4L2_SEL_TGT_CROP:
> > + s->r = stream->port->c_rect;
> > + return 0;
> > + }
> > +
> > + return -EINVAL;
> > +}
> > +
> > +static int enclosed_rectangle(struct v4l2_rect *a, struct v4l2_rect *b)
> > +{
> > + if (a->left < b->left || a->top < b->top)
> > + return 0;
> > + if (a->left + a->width > b->left + b->width)
> > + return 0;
> > + if (a->top + a->height > b->top + b->height)
> > + return 0;
> > +
> > + return 1;
> > +}
>
> There are helper functions in include/media/v4l2-rect.h, it would make
> sense to add this one to that header.
I'll check that out.
>
> > +
> > +static int vip_s_selection(struct file *file, void *fh,
> > + struct v4l2_selection *s)
> > +{
> > + struct vip_stream *stream = file2stream(file);
> > + struct v4l2_rect r = s->r;
> > +
> > + if (s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
> > + return -EINVAL;
> > +
> > + switch (s->target) {
> > + case V4L2_SEL_TGT_COMPOSE:
> > + case V4L2_SEL_TGT_CROP:
>
> Why both crop and compose when it is the same c_rect? That makes no sense.
Yeah, this is always puzzling to me. When to use which and what not.
I'll catch you on IRC sometime to chat about this.
>
> > + v4l_bound_align_image(&r.width, 0, stream->width, 0,
> > + &r.height, 0, stream->height, 0, 0);
> > +
> > + r.left = clamp_t(unsigned int, r.left, 0,
> > + stream->width - r.width);
> > + r.top = clamp_t(unsigned int, r.top, 0,
> > + stream->height - r.height);
> > +
> > + if (s->flags & V4L2_SEL_FLAG_LE &&
> > + !enclosed_rectangle(&r, &s->r))
> > + return -ERANGE;
> > +
> > + if (s->flags & V4L2_SEL_FLAG_GE &&
> > + !enclosed_rectangle(&s->r, &r))
> > + return -ERANGE;
> > +
> > + s->r = r;
> > + stream->port->c_rect = r;
> > +
> > + vip_dbg(1, stream, "cropped (%d,%d)/%dx%d of %dx%d\n",
> > + r.left, r.top, r.width, r.height,
> > + stream->width, stream->height);
> > +
> > + s->r = stream->port->c_rect;
> > + return 0;
> > + default:
> > + return -EINVAL;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static long vip_ioctl_default(struct file *file, void *fh, bool valid_prio,
> > + unsigned int cmd, void *arg)
> > +{
> > + struct vip_stream *stream = file2stream(file);
> > +
> > + if (!valid_prio) {
> > + vip_err(stream, "%s device busy\n", __func__);
> > + return -EBUSY;
> > + }
> > +
> > + switch (cmd) {
> > + default:
> > + return -ENOTTY;
> > + }
> > +}
>
> Huh?
Yeah, I don't when this was added or for what purpose.
I should probably just remove it.
>
> > +
> > +static const struct v4l2_ioctl_ops vip_ioctl_ops = {
> > + .vidioc_querycap = vip_querycap,
> > + .vidioc_enum_input = vip_enuminput,
> > + .vidioc_g_input = vip_g_input,
> > + .vidioc_s_input = vip_s_input,
> > +
> > + .vidioc_querystd = vip_querystd,
> > + .vidioc_g_std = vip_g_std,
> > + .vidioc_s_std = vip_s_std,
> > +
> > + .vidioc_enum_fmt_vid_cap = vip_enum_fmt_vid_cap,
> > + .vidioc_g_fmt_vid_cap = vip_g_fmt_vid_cap,
> > + .vidioc_try_fmt_vid_cap = vip_try_fmt_vid_cap,
> > + .vidioc_s_fmt_vid_cap = vip_s_fmt_vid_cap,
> > +
> > + .vidioc_enum_frameintervals = vip_enum_frameintervals,
> > + .vidioc_enum_framesizes = vip_enum_framesizes,
> > + .vidioc_s_parm = vip_s_parm,
> > + .vidioc_g_parm = vip_g_parm,
> > + .vidioc_g_selection = vip_g_selection,
> > + .vidioc_s_selection = vip_s_selection,
> > + .vidioc_reqbufs = vb2_ioctl_reqbufs,
> > + .vidioc_create_bufs = vb2_ioctl_create_bufs,
> > + .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
> > + .vidioc_querybuf = vb2_ioctl_querybuf,
> > + .vidioc_qbuf = vb2_ioctl_qbuf,
> > + .vidioc_dqbuf = vb2_ioctl_dqbuf,
> > + .vidioc_expbuf = vb2_ioctl_expbuf,
> > +
> > + .vidioc_streamon = vb2_ioctl_streamon,
> > + .vidioc_streamoff = vb2_ioctl_streamoff,
> > + .vidioc_log_status = v4l2_ctrl_log_status,
> > + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
> > + .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
> > + .vidioc_default = vip_ioctl_default,
> > +};
> > +
> > +/*
> > + * Videobuf operations
> > + */
> > +static int vip_queue_setup(struct vb2_queue *vq,
> > + unsigned int *nbuffers, unsigned int *nplanes,
> > + unsigned int sizes[], struct device *alloc_devs[])
> > +{
> > + struct vip_stream *stream = vb2_get_drv_priv(vq);
> > + unsigned int size = stream->sizeimage;
> > +
> > + if (vq->num_buffers + *nbuffers < 3)
> > + *nbuffers = 3 - vq->num_buffers;
> > +
> > + if (*nplanes) {
> > + if (sizes[0] < size)
> > + return -EINVAL;
> > + size = sizes[0];
> > + }
> > +
> > + *nplanes = 1;
> > + sizes[0] = size;
> > +
> > + vip_dbg(1, stream, "get %d buffer(s) of size %d each.\n",
> > + *nbuffers, sizes[0]);
> > +
> > + return 0;
> > +}
> > +
> > +static int vip_buf_prepare(struct vb2_buffer *vb)
> > +{
> > + struct vip_stream *stream = vb2_get_drv_priv(vb->vb2_queue);
> > +
> > + if (vb2_plane_size(vb, 0) < stream->sizeimage) {
> > + vip_dbg(1, stream,
> > + "%s data will not fit into plane (%lu < %lu)\n",
> > + __func__, vb2_plane_size(vb, 0),
> > + (long)stream->sizeimage);
> > + return -EINVAL;
> > + }
> > +
> > + vb2_set_plane_payload(vb, 0, stream->sizeimage);
> > +
> > + return 0;
> > +}
> > +
> > +static void vip_buf_queue(struct vb2_buffer *vb)
> > +{
> > + struct vip_stream *stream = vb2_get_drv_priv(vb->vb2_queue);
> > + struct vip_dev *dev = stream->port->dev;
> > + struct vip_buffer *buf = container_of(vb, struct vip_buffer,
> > + vb.vb2_buf);
> > + unsigned long flags;
> > +
> > + spin_lock_irqsave(&dev->slock, flags);
> > + list_add_tail(&buf->list, &stream->vidq);
> > + spin_unlock_irqrestore(&dev->slock, flags);
> > +}
> > +
> > +static int vip_setup_scaler(struct vip_stream *stream)
> > +{
> > + struct vip_port *port = stream->port;
> > + struct vip_dev *dev = port->dev;
> > + struct sc_data *sc = dev->sc;
> > + struct csc_data *csc = dev->csc;
> > + struct vpdma_data *vpdma = dev->shared->vpdma;
> > + struct vip_mmr_adb *mmr_adb = port->mmr_adb.addr;
> > + int list_num = stream->list_num;
> > + int timeout = 500;
> > + struct v4l2_format dst_f;
> > + struct v4l2_format src_f;
> > +
> > + memset(&src_f, 0, sizeof(src_f));
> > + src_f.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
> > + v4l2_fill_pix_format(&src_f.fmt.pix, &port->mbus_framefmt);
> > + src_f.fmt.pix.pixelformat = vip_mbus_code_to_fourcc(port->fmt->code);
> > +
> > + dst_f = src_f;
> > + dst_f.fmt.pix.pixelformat = port->fmt->fourcc;
> > + dst_f.fmt.pix.width = stream->width;
> > + dst_f.fmt.pix.height = stream->height;
> > +
> > + /* if scaler not associated with this port then skip */
> > + if (port->scaler) {
> > + sc_set_hs_coeffs(sc, port->sc_coeff_h.addr,
> > + port->mbus_framefmt.width,
> > + port->c_rect.width);
> > + sc_set_vs_coeffs(sc, port->sc_coeff_v.addr,
> > + port->mbus_framefmt.height,
> > + port->c_rect.height);
> > + sc_config_scaler(sc, &mmr_adb->sc_regs0[0],
> > + &mmr_adb->sc_regs8[0], &mmr_adb->sc_regs17[0],
> > + port->mbus_framefmt.width,
> > + port->mbus_framefmt.height,
> > + port->c_rect.width,
> > + port->c_rect.height);
> > + port->load_mmrs = true;
> > + }
> > +
> > + /* if csc not associated with this port then skip */
> > + if (port->csc) {
> > + csc_set_coeff(csc, &mmr_adb->csc_regs[0],
> > + &src_f, &dst_f);
> > +
> > + port->load_mmrs = true;
> > + }
> > +
> > + /* If coeff are already loaded then skip */
> > + if (!sc->load_coeff_v && !sc->load_coeff_h && !port->load_mmrs)
> > + return 0;
> > +
> > + if (vpdma_list_busy(vpdma, list_num)) {
> > + vip_dbg(3, stream, "%s: List %d is busy\n",
> > + __func__, list_num);
> > + }
> > +
> > + /* Make sure we start with a clean list */
> > + vpdma_reset_desc_list(&stream->desc_list);
> > +
> > + /* config descriptors */
> > + if (port->load_mmrs) {
> > + vpdma_map_desc_buf(vpdma, &port->mmr_adb);
> > + vpdma_add_cfd_adb(&stream->desc_list, CFD_MMR_CLIENT,
> > + &port->mmr_adb);
> > +
> > + port->load_mmrs = false;
> > + vip_dbg(3, stream, "Added mmr_adb config desc\n");
> > + }
> > +
> > + if (sc->loaded_coeff_h != port->sc_coeff_h.dma_addr ||
> > + sc->load_coeff_h) {
> > + vpdma_map_desc_buf(vpdma, &port->sc_coeff_h);
> > + vpdma_add_cfd_block(&stream->desc_list,
> > + VIP_SLICE1_CFD_SC_CLIENT + dev->slice_id,
> > + &port->sc_coeff_h, 0);
> > +
> > + sc->loaded_coeff_h = port->sc_coeff_h.dma_addr;
> > + sc->load_coeff_h = false;
> > + vip_dbg(3, stream, "Added sc_coeff_h config desc\n");
> > + }
> > +
> > + if (sc->loaded_coeff_v != port->sc_coeff_v.dma_addr ||
> > + sc->load_coeff_v) {
> > + vpdma_map_desc_buf(vpdma, &port->sc_coeff_v);
> > + vpdma_add_cfd_block(&stream->desc_list,
> > + VIP_SLICE1_CFD_SC_CLIENT + dev->slice_id,
> > + &port->sc_coeff_v, SC_COEF_SRAM_SIZE >> 4);
> > +
> > + sc->loaded_coeff_v = port->sc_coeff_v.dma_addr;
> > + sc->load_coeff_v = false;
> > + vip_dbg(3, stream, "Added sc_coeff_v config desc\n");
> > + }
> > + vip_dbg(3, stream, "CFD_SC_CLIENT %d slice_id: %d\n",
> > + VIP_SLICE1_CFD_SC_CLIENT + dev->slice_id, dev->slice_id);
> > +
> > + vpdma_map_desc_buf(vpdma, &stream->desc_list.buf);
> > + vip_dbg(3, stream, "Submitting desc on list# %d\n", list_num);
> > + vpdma_submit_descs(vpdma, &stream->desc_list, list_num);
> > +
> > + while (vpdma_list_busy(vpdma, list_num) && timeout--)
> > + usleep_range(1000, 1100);
> > +
> > + vpdma_unmap_desc_buf(dev->shared->vpdma, &port->mmr_adb);
> > + vpdma_unmap_desc_buf(dev->shared->vpdma, &port->sc_coeff_h);
> > + vpdma_unmap_desc_buf(dev->shared->vpdma, &port->sc_coeff_v);
> > + vpdma_unmap_desc_buf(dev->shared->vpdma, &stream->desc_list.buf);
> > +
> > + vpdma_reset_desc_list(&stream->desc_list);
> > +
> > + if (timeout <= 0) {
> > + vip_err(stream, "Timed out setting up scaler through VPDMA list\n");
> > + return -EBUSY;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int vip_load_vpdma_list_fifo(struct vip_stream *stream)
> > +{
> > + struct vip_port *port = stream->port;
> > + struct vip_dev *dev = port->dev;
> > + struct vpdma_data *vpdma = dev->shared->vpdma;
> > + int list_num = stream->list_num;
> > + struct vip_buffer *buf;
> > + unsigned long flags;
> > + int timeout, i;
> > +
> > + if (vpdma_list_busy(dev->shared->vpdma, stream->list_num))
> > + return -EBUSY;
> > +
> > + for (i = 0; i < VIP_VPDMA_FIFO_SIZE; i++) {
> > + spin_lock_irqsave(&dev->slock, flags);
> > + if (list_empty(&stream->vidq)) {
> > + vip_err(stream, "No buffer left!");
> > + spin_unlock_irqrestore(&dev->slock, flags);
> > + return -EINVAL;
> > + }
> > +
> > + buf = list_entry(stream->vidq.next,
> > + struct vip_buffer, list);
> > + buf->drop = false;
> > +
> > + list_move_tail(&buf->list, &stream->post_bufs);
> > + spin_unlock_irqrestore(&dev->slock, flags);
> > +
> > + vip_dbg(2, stream, "%s: start_dma vb2 buf idx:%d\n",
> > + __func__, buf->vb.vb2_buf.index);
> > + start_dma(stream, buf);
> > +
> > + timeout = 500;
> > + while (vpdma_list_busy(vpdma, list_num) && timeout--)
> > + usleep_range(1000, 1100);
> > +
> > + if (timeout <= 0) {
> > + vip_err(stream, "Timed out loading VPDMA list fifo\n");
> > + return -EBUSY;
> > + }
> > + }
> > + return 0;
> > +}
> > +
> > +static int vip_start_streaming(struct vb2_queue *vq, unsigned int count)
> > +{
> > + struct vip_stream *stream = vb2_get_drv_priv(vq);
> > + struct vip_port *port = stream->port;
> > + struct vip_dev *dev = port->dev;
> > + int ret;
> > +
> > + vip_setup_scaler(stream);
> > +
> > + /*
> > + * Make sure the scaler is configured before the datapath is
> > + * enabled. The scaler can only load the coefficient
> > + * parameters when it is idle. If the scaler path is enabled
> > + * and video data is being received then the VPDMA transfer will
> > + * stall indefinetely.
> > + */
> > + set_fmt_params(stream);
> > + vip_setup_parser(port);
> > +
> > + if (port->subdev) {
> > + ret = v4l2_subdev_call(port->subdev, video, s_stream, 1);
> > + if (ret < 0 && ret != -ENOIOCTLCMD) {
> > + vip_dbg(1, stream, "stream on failed in subdev\n");
>
> On error, all pending buffers need to be returned to vb2 with
> vb2_buffer_done and state VB2_BUF_STATE_QUEUED.
Ah yes missed this.
>
> > + return ret;
> > + }
> > + }
> > +
> > + stream->sequence = 0;
> > + if (stream->port->flags & FLAG_INTERLACED)
> > + stream->field = V4L2_FIELD_TOP;
> > + populate_desc_list(stream);
> > +
> > + ret = vip_load_vpdma_list_fifo(stream);
> > + if (ret)
> > + return ret;
> > +
> > + stream->num_recovery = 0;
> > +
> > + clear_irqs(dev, dev->slice_id, stream->list_num);
> > + enable_irqs(dev, dev->slice_id, stream->list_num);
> > + vip_schedule_next_buffer(stream);
> > + vip_parser_stop_imm(port, false);
> > + vip_enable_parser(port, true);
> > +
> > + return 0;
> > +}
> > +
> > +/*
> > + * Abort streaming and wait for last buffer
> > + */
> > +static void vip_stop_streaming(struct vb2_queue *vq)
> > +{
> > + struct vip_stream *stream = vb2_get_drv_priv(vq);
> > + struct vip_port *port = stream->port;
> > + struct vip_dev *dev = port->dev;
> > + struct vip_buffer *buf;
> > + int ret;
> > +
> > + vip_dbg(2, stream, "%s:\n", __func__);
> > +
> > + vip_parser_stop_imm(port, true);
> > + vip_enable_parser(port, false);
> > + unset_fmt_params(stream);
> > +
> > + disable_irqs(dev, dev->slice_id, stream->list_num);
> > + clear_irqs(dev, dev->slice_id, stream->list_num);
> > +
> > + if (port->subdev) {
> > + ret = v4l2_subdev_call(port->subdev, video, s_stream, 0);
> > + if (ret < 0 && ret != -ENOIOCTLCMD)
> > + vip_dbg(1, stream, "stream on failed in subdev\n");
> > + }
> > +
> > + stop_dma(stream, true);
> > +
> > + /* release all active buffers */
> > + while (!list_empty(&stream->post_bufs)) {
> > + buf = list_entry(stream->post_bufs.next,
> > + struct vip_buffer, list);
> > + list_del(&buf->list);
> > + if (buf->drop == 1)
> > + list_add_tail(&buf->list, &stream->dropq);
> > + else
> > + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
> > + }
> > + while (!list_empty(&stream->vidq)) {
> > + buf = list_entry(stream->vidq.next, struct vip_buffer, list);
> > + list_del(&buf->list);
> > + vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
> > + }
> > +
> > + if (!vb2_is_streaming(vq))
> > + return;
> > +
> > + vpdma_unmap_desc_buf(dev->shared->vpdma, &stream->desc_list.buf);
> > + vpdma_reset_desc_list(&stream->desc_list);
> > +}
> > +
> > +static const struct vb2_ops vip_video_qops = {
> > + .queue_setup = vip_queue_setup,
> > + .buf_prepare = vip_buf_prepare,
> > + .buf_queue = vip_buf_queue,
> > + .start_streaming = vip_start_streaming,
> > + .stop_streaming = vip_stop_streaming,
> > + .wait_prepare = vb2_ops_wait_prepare,
> > + .wait_finish = vb2_ops_wait_finish,
> > +};
> > +
> > +/*
> > + * File operations
> > + */
> > +
> > +static int vip_init_dev(struct vip_dev *dev)
> > +{
> > + if (dev->num_ports != 0)
> > + goto done;
> > +
> > + vip_set_clock_enable(dev, 1);
> > + vip_module_reset(dev, VIP_SC_RST, false);
> > + vip_module_reset(dev, VIP_CSC_RST, false);
> > +done:
> > + dev->num_ports++;
> > +
> > + return 0;
> > +}
> > +
> > +static inline bool is_scaler_available(struct vip_port *port)
> > +{
> > + if (port->endpoint.bus_type == V4L2_MBUS_PARALLEL)
> > + if (port->dev->sc_assigned == VIP_NOT_ASSIGNED ||
> > + port->dev->sc_assigned == port->port_id)
> > + return true;
> > + return false;
> > +}
> > +
> > +static inline bool allocate_scaler(struct vip_port *port)
> > +{
> > + if (is_scaler_available(port)) {
> > + if (port->dev->sc_assigned == VIP_NOT_ASSIGNED ||
> > + port->dev->sc_assigned == port->port_id) {
> > + port->dev->sc_assigned = port->port_id;
> > + port->scaler = true;
> > + return true;
> > + }
> > + }
> > + return false;
> > +}
> > +
> > +static inline void free_scaler(struct vip_port *port)
> > +{
> > + if (port->dev->sc_assigned == port->port_id) {
> > + port->dev->sc_assigned = VIP_NOT_ASSIGNED;
> > + port->scaler = false;
> > + }
> > +}
> > +
> > +static bool is_csc_available(struct vip_port *port)
> > +{
> > + if (port->endpoint.bus_type == V4L2_MBUS_PARALLEL)
> > + if (port->dev->csc_assigned == VIP_NOT_ASSIGNED ||
> > + port->dev->csc_assigned == port->port_id)
> > + return true;
> > + return false;
> > +}
> > +
> > +static bool allocate_csc(struct vip_port *port,
> > + enum vip_csc_state csc_direction)
> > +{
> > + /* Is CSC needed? */
> > + if (csc_direction != VIP_CSC_NA) {
> > + if (is_csc_available(port)) {
> > + port->dev->csc_assigned = port->port_id;
> > + port->csc = csc_direction;
> > + vip_dbg(1, port, "%s: csc allocated: dir: %d\n",
> > + __func__, csc_direction);
> > + return true;
> > + }
> > + }
> > + return false;
> > +}
> > +
> > +static void free_csc(struct vip_port *port)
> > +{
> > + if (port->dev->csc_assigned == port->port_id) {
> > + port->dev->csc_assigned = VIP_NOT_ASSIGNED;
> > + port->csc = VIP_CSC_NA;
> > + vip_dbg(1, port, "%s: csc freed\n",
> > + __func__);
> > + }
> > +}
> > +
> > +static int vip_init_port(struct vip_port *port)
> > +{
> > + int ret;
> > + struct vip_fmt *fmt;
> > + struct v4l2_subdev_format sd_fmt;
> > + struct v4l2_mbus_framefmt *mbus_fmt = &sd_fmt.format;
> > +
> > + if (port->num_streams != 0)
> > + goto done;
> > +
> > + ret = vip_init_dev(port->dev);
> > + if (ret)
> > + goto done;
> > +
> > + /* Get subdevice current frame format */
> > + sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
> > + sd_fmt.pad = port->source_pad;
> > + ret = v4l2_subdev_call(port->subdev, pad, get_fmt, NULL, &sd_fmt);
> > + if (ret)
> > + vip_dbg(1, port, "init_port get_fmt failed in subdev: (%d)\n",
> > + ret);
> > +
> > + /* try to find one that matches */
> > + fmt = find_port_format_by_code(port, mbus_fmt->code);
> > + if (!fmt) {
> > + vip_dbg(1, port, "subdev default mbus_fmt %04x is not matched.\n",
> > + mbus_fmt->code);
> > + /* if all else fails just pick the first one */
> > + fmt = port->active_fmt[0];
> > +
> > + mbus_fmt->code = fmt->code;
> > + sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
> > + sd_fmt.pad = port->source_pad;
> > + ret = v4l2_subdev_call(port->subdev, pad, set_fmt,
> > + NULL, &sd_fmt);
> > + if (ret)
> > + vip_dbg(1, port, "init_port set_fmt failed in subdev: (%d)\n",
> > + ret);
> > + }
> > +
> > + /* Assign current format */
> > + port->fmt = fmt;
> > + port->mbus_framefmt = *mbus_fmt;
> > +
> > + vip_dbg(3, port, "%s: g_mbus_fmt subdev mbus_code: %04X fourcc:%s size: %dx%d\n",
> > + __func__, fmt->code,
> > + fourcc_to_str(fmt->fourcc),
> > + mbus_fmt->width, mbus_fmt->height);
> > +
> > + if (mbus_fmt->field == V4L2_FIELD_ALTERNATE)
> > + port->flags |= FLAG_INTERLACED;
> > + else
> > + port->flags &= ~FLAG_INTERLACED;
> > +
> > + port->c_rect.left = 0;
> > + port->c_rect.top = 0;
> > + port->c_rect.width = mbus_fmt->width;
> > + port->c_rect.height = mbus_fmt->height;
> > +
> > + ret = vpdma_alloc_desc_buf(&port->sc_coeff_h, SC_COEF_SRAM_SIZE);
> > + if (ret != 0)
> > + return ret;
> > +
> > + ret = vpdma_alloc_desc_buf(&port->sc_coeff_v, SC_COEF_SRAM_SIZE);
> > + if (ret != 0)
> > + goto free_sc_h;
> > +
> > + ret = vpdma_alloc_desc_buf(&port->mmr_adb, sizeof(struct vip_mmr_adb));
> > + if (ret != 0)
> > + goto free_sc_v;
> > +
> > + init_adb_hdrs(port);
> > +
> > + vip_enable_parser(port, false);
> > +done:
> > + port->num_streams++;
> > + return 0;
> > +
> > +free_sc_v:
> > + vpdma_free_desc_buf(&port->sc_coeff_v);
> > +free_sc_h:
> > + vpdma_free_desc_buf(&port->sc_coeff_h);
> > + return ret;
> > +}
> > +
> > +static int vip_init_stream(struct vip_stream *stream)
> > +{
> > + struct vip_port *port = stream->port;
> > + struct vip_fmt *fmt;
> > + struct v4l2_mbus_framefmt *mbus_fmt;
> > + struct v4l2_format f;
> > + int ret;
> > +
> > + ret = vip_init_port(port);
> > + if (ret != 0)
> > + return ret;
> > +
> > + fmt = port->fmt;
> > + mbus_fmt = &port->mbus_framefmt;
> > +
> > + memset(&f, 0, sizeof(f));
> > +
> > + /* Properly calculate the sizeimage and bytesperline values. */
> > + v4l2_fill_pix_format(&f.fmt.pix, mbus_fmt);
> > + f.fmt.pix.pixelformat = fmt->fourcc;
> > + ret = vip_calc_format_size(port, fmt, &f);
> > + if (ret)
> > + return ret;
> > +
> > + stream->width = f.fmt.pix.width;
> > + stream->height = f.fmt.pix.height;
> > + stream->sup_field = f.fmt.pix.field;
> > + stream->field = f.fmt.pix.field;
> > + stream->bytesperline = f.fmt.pix.bytesperline;
> > + stream->sizeimage = f.fmt.pix.sizeimage;
> > +
> > + vip_dbg(3, stream, "init_stream fourcc:%s size: %dx%d bpl:%d img_size:%d\n",
> > + fourcc_to_str(f.fmt.pix.pixelformat),
> > + f.fmt.pix.width, f.fmt.pix.height,
> > + f.fmt.pix.bytesperline, f.fmt.pix.sizeimage);
> > + vip_dbg(3, stream, "init_stream vpdma data type: 0x%02X\n",
> > + port->fmt->vpdma_fmt[0]->data_type);
> > +
> > + ret = vpdma_create_desc_list(&stream->desc_list, VIP_DESC_LIST_SIZE,
> > + VPDMA_LIST_TYPE_NORMAL);
> > +
> > + if (ret != 0)
> > + return ret;
> > +
> > + stream->write_desc = (struct vpdma_dtd *)stream->desc_list.buf.addr
> > + + 15;
> > +
> > + vip_dbg(1, stream, "%s: stream instance %pa\n",
> > + __func__, &stream);
> > +
> > + return 0;
> > +}
> > +
> > +static void vip_release_dev(struct vip_dev *dev)
> > +{
> > + /*
> > + * On last close, disable clocks to conserve power
> > + */
> > +
> > + if (--dev->num_ports == 0) {
> > + /* reset the scaler module */
> > + vip_module_reset(dev, VIP_SC_RST, true);
> > + vip_module_reset(dev, VIP_CSC_RST, true);
> > + vip_set_clock_enable(dev, 0);
> > + }
> > +}
> > +
> > +static int vip_set_crop_parser(struct vip_port *port)
> > +{
> > + struct vip_dev *dev = port->dev;
> > + struct vip_parser_data *parser = dev->parser;
> > + u32 hcrop = 0, vcrop = 0;
> > + u32 width = port->mbus_framefmt.width;
> > +
> > + if (port->fmt->vpdma_fmt[0] == &vpdma_raw_fmts[VPDMA_DATA_FMT_RAW8]) {
> > + /*
> > + * Special case since we are faking a YUV422 16bit format
> > + * to have the vpdma perform the needed byte swap
> > + * we need to adjust the pixel width accordingly
> > + * otherwise the parser will attempt to collect more pixels
> > + * then available and the vpdma transfer will exceed the
> > + * allocated frame buffer.
> > + */
> > + width >>= 1;
> > + vip_dbg(1, port, "%s: 8 bit raw detected, adjusting width to %d\n",
> > + __func__, width);
> > + }
> > +
> > + /*
> > + * Set Parser Crop parameters to source size otherwise
> > + * scaler and colorspace converter will yield garbage.
> > + */
> > + hcrop = VIP_ACT_BYPASS;
> > + insert_field(&hcrop, 0, VIP_ACT_SKIP_NUMPIX_MASK,
> > + VIP_ACT_SKIP_NUMPIX_SHFT);
> > + insert_field(&hcrop, width,
> > + VIP_ACT_USE_NUMPIX_MASK, VIP_ACT_USE_NUMPIX_SHFT);
> > + reg_write(parser, VIP_PARSER_CROP_H_PORT(port->port_id), hcrop);
> > +
> > + insert_field(&vcrop, 0, VIP_ACT_SKIP_NUMLINES_MASK,
> > + VIP_ACT_SKIP_NUMLINES_SHFT);
> > + insert_field(&vcrop, port->mbus_framefmt.height,
> > + VIP_ACT_USE_NUMLINES_MASK, VIP_ACT_USE_NUMLINES_SHFT);
> > + reg_write(parser, VIP_PARSER_CROP_V_PORT(port->port_id), vcrop);
> > +
> > + return 0;
> > +}
> > +
> > +static int vip_setup_parser(struct vip_port *port)
> > +{
> > + struct vip_dev *dev = port->dev;
> > + struct vip_parser_data *parser = dev->parser;
> > + struct v4l2_fwnode_endpoint *endpoint = &port->endpoint;
> > + struct vip_bt656_bus *bt656_ep = &port->bt656_endpoint;
> > + int iface, sync_type;
> > + u32 flags = 0, config0;
> > +
> > + /* Reset the port */
> > + vip_reset_parser(port, true);
> > + usleep_range(200, 250);
> > + vip_reset_parser(port, false);
> > +
> > + config0 = reg_read(parser, VIP_PARSER_PORT(port->port_id));
> > +
> > + switch (endpoint->bus.parallel.bus_width) {
> > + case 24:
> > + iface = SINGLE_24B_INTERFACE;
> > + break;
> > + case 16:
> > + iface = SINGLE_16B_INTERFACE;
> > + break;
> > + case 8:
> > + default:
> > + iface = DUAL_8B_INTERFACE;
> > + }
> > +
> > + if (endpoint->bus_type == V4L2_MBUS_BT656) {
> > + flags = endpoint->bus.parallel.flags;
> > +
> > + /*
> > + * Ideally, this should come from subdev
> > + * port->fmt can be anything once CSC is enabled
> > + */
> > + if (vip_is_mbuscode_rgb(port->fmt->code)) {
> > + sync_type = EMBEDDED_SYNC_SINGLE_RGB_OR_YUV444;
> > + } else {
> > + switch (bt656_ep->num_channels) {
> > + case 4:
> > + sync_type = EMBEDDED_SYNC_4X_MULTIPLEXED_YUV422;
> > + break;
> > + case 2:
> > + sync_type = EMBEDDED_SYNC_2X_MULTIPLEXED_YUV422;
> > + break;
> > + case 1:
> > + sync_type = EMBEDDED_SYNC_SINGLE_YUV422;
> > + break;
> > + default:
> > + sync_type =
> > + EMBEDDED_SYNC_LINE_MULTIPLEXED_YUV422;
> > + }
> > + if (bt656_ep->pixmux == 0)
> > + sync_type =
> > + EMBEDDED_SYNC_LINE_MULTIPLEXED_YUV422;
> > + }
> > +
> > + } else if (endpoint->bus_type == V4L2_MBUS_PARALLEL) {
> > + flags = endpoint->bus.parallel.flags;
> > +
> > + if (vip_is_mbuscode_rgb(port->fmt->code))
> > + sync_type = DISCRETE_SYNC_SINGLE_RGB_24B;
> > + else
> > + sync_type = DISCRETE_SYNC_SINGLE_YUV422;
> > +
> > + if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
> > + config0 |= VIP_HSYNC_POLARITY;
> > + else if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
> > + config0 &= ~VIP_HSYNC_POLARITY;
> > +
> > + if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
> > + config0 |= VIP_VSYNC_POLARITY;
> > + else if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
> > + config0 &= ~VIP_VSYNC_POLARITY;
> > +
> > + config0 &= ~VIP_USE_ACTVID_HSYNC_ONLY;
> > + config0 |= VIP_ACTVID_POLARITY;
> > + config0 |= VIP_DISCRETE_BASIC_MODE;
> > +
> > + } else {
> > + vip_err(port, "Device doesn't support CSI2");
> > + return -EINVAL;
> > + }
> > +
> > + if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING) {
> > + vip_set_pclk_invert(port);
> > + config0 |= VIP_PIXCLK_EDGE_POLARITY;
> > + } else {
> > + vip_clr_pclk_invert(port);
> > + config0 &= ~VIP_PIXCLK_EDGE_POLARITY;
> > + }
> > +
> > + config0 |= ((sync_type & VIP_SYNC_TYPE_MASK) << VIP_SYNC_TYPE_SHFT);
> > +
> > + reg_write(parser, VIP_PARSER_PORT(port->port_id), config0);
> > +
> > + vip_set_data_interface(port, iface);
> > + vip_set_crop_parser(port);
> > +
> > + return 0;
> > +}
> > +
> > +static void vip_enable_parser(struct vip_port *port, bool on)
> > +{
> > + u32 config0;
> > + struct vip_dev *dev = port->dev;
> > + struct vip_parser_data *parser = dev->parser;
> > +
> > + config0 = reg_read(parser, VIP_PARSER_PORT(port->port_id));
> > +
> > + if (on) {
> > + config0 |= VIP_PORT_ENABLE;
> > + config0 &= ~(VIP_ASYNC_FIFO_RD | VIP_ASYNC_FIFO_WR);
> > + } else {
> > + config0 &= ~VIP_PORT_ENABLE;
> > + config0 |= (VIP_ASYNC_FIFO_RD | VIP_ASYNC_FIFO_WR);
> > + }
> > + reg_write(parser, VIP_PARSER_PORT(port->port_id), config0);
> > +}
> > +
> > +static void vip_reset_parser(struct vip_port *port, bool on)
> > +{
> > + u32 config0;
> > + struct vip_dev *dev = port->dev;
> > + struct vip_parser_data *parser = dev->parser;
> > +
> > + config0 = reg_read(parser, VIP_PARSER_PORT(port->port_id));
> > +
> > + if (on)
> > + config0 |= VIP_SW_RESET;
> > + else
> > + config0 &= ~VIP_SW_RESET;
> > +
> > + reg_write(parser, VIP_PARSER_PORT(port->port_id), config0);
> > +}
> > +
> > +static void vip_parser_stop_imm(struct vip_port *port, bool on)
> > +{
> > + u32 config0;
> > + struct vip_dev *dev = port->dev;
> > + struct vip_parser_data *parser = dev->parser;
> > +
> > + config0 = reg_read(parser, VIP_PARSER_STOP_IMM_PORT(port->port_id));
> > +
> > + if (on)
> > + config0 = 0xffffffff;
> > + else
> > + config0 = 0;
> > +
> > + reg_write(parser, VIP_PARSER_STOP_IMM_PORT(port->port_id), config0);
> > +}
> > +
> > +static void vip_release_stream(struct vip_stream *stream)
> > +{
> > + struct vip_dev *dev = stream->port->dev;
> > +
> > + vip_dbg(1, stream, "%s: stream instance %pa\n",
> > + __func__, &stream);
> > +
> > + vpdma_unmap_desc_buf(dev->shared->vpdma, &stream->desc_list.buf);
> > + vpdma_free_desc_buf(&stream->desc_list.buf);
> > + vpdma_free_desc_list(&stream->desc_list);
> > +}
> > +
> > +static void vip_release_port(struct vip_port *port)
> > +{
> > + vip_dbg(1, port, "%s: port instance %pa\n",
> > + __func__, &port);
> > +
> > + vpdma_free_desc_buf(&port->mmr_adb);
> > + vpdma_free_desc_buf(&port->sc_coeff_h);
> > + vpdma_free_desc_buf(&port->sc_coeff_v);
> > +}
> > +
> > +static void stop_dma(struct vip_stream *stream, bool clear_list)
> > +{
> > + struct vip_dev *dev = stream->port->dev;
> > + int ch, size = 0;
> > +
> > + /* Create a list of channels to be cleared */
> > + for (ch = 0; ch < VPDMA_MAX_CHANNELS; ch++) {
> > + if (stream->vpdma_channels[ch] == 1) {
> > + stream->vpdma_channels_to_abort[size++] = ch;
> > + vip_dbg(2, stream, "Clear channel no: %d\n", ch);
> > + }
> > + }
> > +
> > + /* Clear all the used channels for the list */
> > + vpdma_list_cleanup(dev->shared->vpdma, stream->list_num,
> > + stream->vpdma_channels_to_abort, size);
> > +
> > + if (clear_list)
> > + for (ch = 0; ch < VPDMA_MAX_CHANNELS; ch++)
> > + stream->vpdma_channels[ch] = 0;
> > +}
> > +
> > +static int vip_open(struct file *file)
> > +{
> > + struct vip_stream *stream = video_drvdata(file);
> > + struct vip_port *port = stream->port;
> > + struct vip_dev *dev = port->dev;
> > + int ret = 0;
> > +
> > + vip_dbg(2, stream, "%s\n", __func__);
> > +
> > + mutex_lock(&dev->mutex);
> > +
> > + ret = v4l2_fh_open(file);
> > + if (ret) {
> > + vip_err(stream, "v4l2_fh_open failed\n");
> > + goto unlock;
> > + }
> > +
> > + /*
> > + * If this is the first open file.
> > + * Then initialize hw module.
> > + */
> > + if (!v4l2_fh_is_singular_file(file))
> > + goto unlock;
> > +
> > + if (vip_init_stream(stream))
> > + ret = -ENODEV;
> > +unlock:
> > + mutex_unlock(&dev->mutex);
> > + return ret;
> > +}
> > +
> > +static int vip_release(struct file *file)
> > +{
> > + struct vip_stream *stream = video_drvdata(file);
> > + struct vip_port *port = stream->port;
> > + struct vip_dev *dev = port->dev;
> > + bool fh_singular;
> > + int ret;
> > +
> > + vip_dbg(2, stream, "%s\n", __func__);
> > +
> > + mutex_lock(&dev->mutex);
> > +
> > + /* Save the singular status before we call the clean-up helper */
> > + fh_singular = v4l2_fh_is_singular_file(file);
> > +
> > + /* the release helper will cleanup any on-going streaming */
> > + ret = _vb2_fop_release(file, NULL);
> > +
> > + free_csc(port);
> > + free_scaler(port);
> > +
> > + /*
> > + * If this is the last open file.
> > + * Then de-initialize hw module.
> > + */
> > + if (fh_singular) {
> > + vip_release_stream(stream);
> > +
> > + if (--port->num_streams == 0) {
> > + vip_release_port(port);
> > + vip_release_dev(port->dev);
> > + }
> > + }
> > +
> > + mutex_unlock(&dev->mutex);
> > +
> > + return ret;
> > +}
> > +
> > +static const struct v4l2_file_operations vip_fops = {
> > + .owner = THIS_MODULE,
> > + .open = vip_open,
> > + .release = vip_release,
> > + .read = vb2_fop_read,
> > + .poll = vb2_fop_poll,
> > + .unlocked_ioctl = video_ioctl2,
> > + .mmap = vb2_fop_mmap,
> > +};
> > +
> > +static struct video_device vip_videodev = {
> > + .name = VIP_MODULE_NAME,
> > + .fops = &vip_fops,
> > + .ioctl_ops = &vip_ioctl_ops,
> > + .minor = -1,
> > + .release = video_device_release,
> > + .tvnorms = V4L2_STD_NTSC | V4L2_STD_PAL | V4L2_STD_SECAM,
> > + .device_caps = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE |
> > + V4L2_CAP_READWRITE,
> > +};
> > +
> > +static int alloc_stream(struct vip_port *port, int stream_id, int vfl_type)
> > +{
> > + struct vip_stream *stream;
> > + struct vip_dev *dev = port->dev;
> > + struct vb2_queue *q;
> > + struct video_device *vfd;
> > + struct vip_buffer *buf;
> > + struct list_head *pos, *tmp;
> > + int ret, i;
> > +
> > + stream = kzalloc(sizeof(*stream), GFP_KERNEL);
> > + if (!stream)
> > + return -ENOMEM;
> > +
> > + stream->port = port;
> > + stream->stream_id = stream_id;
> > + stream->vfl_type = vfl_type;
> > + port->cap_streams[stream_id] = stream;
> > +
> > + snprintf(stream->name, sizeof(stream->name), "%s-%d",
> > + port->name, stream_id);
> > +
> > + stream->list_num = vpdma_hwlist_alloc(dev->shared->vpdma, stream);
> > + if (stream->list_num < 0) {
> > + vip_err(stream, "Could not get VPDMA hwlist");
> > + ret = -ENODEV;
> > + goto do_free_stream;
> > + }
> > +
> > + INIT_LIST_HEAD(&stream->post_bufs);
> > +
> > + /*
> > + * Initialize queue
> > + */
> > + q = &stream->vb_vidq;
> > + q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
> > + q->io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
> > + q->drv_priv = stream;
> > + q->buf_struct_size = sizeof(struct vip_buffer);
> > + q->ops = &vip_video_qops;
> > + q->mem_ops = &vb2_dma_contig_memops;
> > + q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
> > + q->lock = &dev->mutex;
> > + q->min_buffers_needed = 3;
> > + q->dev = dev->v4l2_dev->dev;
> > +
> > + ret = vb2_queue_init(q);
> > + if (ret)
> > + goto do_free_hwlist;
> > +
> > + INIT_WORK(&stream->recovery_work, vip_overflow_recovery_work);
> > +
> > + INIT_LIST_HEAD(&stream->vidq);
> > +
> > + /* Allocate/populate Drop queue entries */
> > + INIT_LIST_HEAD(&stream->dropq);
> > + for (i = 0; i < VIP_DROPQ_SIZE; i++) {
> > + buf = kzalloc(sizeof(*buf), GFP_ATOMIC);
> > + if (!buf) {
> > + ret = -ENOMEM;
> > + goto do_free_dropq;
> > + }
> > + buf->drop = true;
> > + list_add(&buf->list, &stream->dropq);
> > + }
> > +
> > + vfd = video_device_alloc();
> > + if (!vfd)
> > + goto do_free_dropq;
> > + *vfd = vip_videodev;
> > + vfd->v4l2_dev = dev->v4l2_dev;
> > + vfd->queue = q;
> > +
> > + vfd->lock = &dev->mutex;
> > + video_set_drvdata(vfd, stream);
> > +
> > + ret = video_register_device(vfd, vfl_type, -1);
> > + if (ret) {
> > + vip_err(stream, "Failed to register video device\n");
> > + goto do_free_vfd;
> > + }
> > +
> > + stream->vfd = vfd;
>
> Shouldn't this be done before the call to video_register_device()?
Yep most likely.
>
> > +
> > + vip_info(stream, "device registered as %s\n",
> > + video_device_node_name(vfd));
> > + return 0;
> > +
> > +do_free_vfd:
> > + video_device_release(vfd);
> > +do_free_dropq:
> > + list_for_each_safe(pos, tmp, &stream->dropq) {
> > + buf = list_entry(pos,
> > + struct vip_buffer, list);
> > + vip_dbg(1, dev, "dropq buffer\n");
> > + list_del(pos);
> > + kfree(buf);
> > + }
> > +do_free_hwlist:
> > + vpdma_hwlist_release(dev->shared->vpdma, stream->list_num);
> > +do_free_stream:
> > + kfree(stream);
> > + return ret;
> > +}
> > +
> > +static void free_stream(struct vip_stream *stream)
> > +{
> > + struct vip_dev *dev;
> > + struct vip_buffer *buf;
> > + struct list_head *pos, *q;
> > +
> > + if (!stream)
> > + return;
> > +
> > + dev = stream->port->dev;
> > + /* Free up the Drop queue */
> > + list_for_each_safe(pos, q, &stream->dropq) {
> > + buf = list_entry(pos,
> > + struct vip_buffer, list);
> > + vip_dbg(1, stream, "dropq buffer\n");
> > + list_del(pos);
> > + kfree(buf);
> > + }
> > +
> > + video_unregister_device(stream->vfd);
> > + vpdma_hwlist_release(dev->shared->vpdma, stream->list_num);
> > + stream->port->cap_streams[stream->stream_id] = NULL;
> > + kfree(stream);
> > +}
> > +
> > +static int get_subdev_active_format(struct vip_port *port,
> > + struct v4l2_subdev *subdev)
> > +{
> > + struct vip_fmt *fmt;
> > + struct v4l2_subdev_mbus_code_enum mbus_code;
> > + int ret = 0;
> > + unsigned int k, i, j;
> > + enum vip_csc_state csc;
> > +
> > + /* Enumerate sub device formats and enable all matching local formats */
> > + port->num_active_fmt = 0;
> > + for (k = 0, i = 0; (ret != -EINVAL); k++) {
> > + memset(&mbus_code, 0, sizeof(mbus_code));
> > + mbus_code.index = k;
> > + mbus_code.which = V4L2_SUBDEV_FORMAT_ACTIVE;
> > + ret = v4l2_subdev_call(subdev, pad, enum_mbus_code,
> > + NULL, &mbus_code);
> > + if (ret)
> > + continue;
> > +
> > + vip_dbg(2, port,
> > + "subdev %s: code: %04x idx: %d\n",
> > + subdev->name, mbus_code.code, k);
> > +
> > + for (j = 0; j < ARRAY_SIZE(vip_formats); j++) {
> > + fmt = &vip_formats[j];
> > + if (mbus_code.code != fmt->code)
> > + continue;
> > +
> > + /*
> > + * When the port is configured for BT656
> > + * then none of the downstream unit can be used.
> > + * So here we need to skip all format requiring
> > + * either CSC or CHR_DS
> > + */
> > + csc = vip_csc_direction(fmt->code, fmt->finfo);
> > + if (port->endpoint.bus_type == V4L2_MBUS_BT656 &&
> > + (csc != VIP_CSC_NA || fmt->coplanar))
> > + continue;
> > +
> > + port->active_fmt[i] = fmt;
> > + vip_dbg(2, port,
> > + "matched fourcc: %s: code: %04x idx: %d\n",
> > + fourcc_to_str(fmt->fourcc), fmt->code, i);
> > + port->num_active_fmt = ++i;
> > + }
> > + }
> > +
> > + if (i == 0) {
> > + vip_err(port, "No suitable format reported by subdev %s\n",
> > + subdev->name);
> > + return -EINVAL;
> > + }
> > + return 0;
> > +}
> > +
> > +static int alloc_port(struct vip_dev *dev, int id, const char *name)
> > +{
> > + struct vip_port *port;
> > +
> > + if (dev->ports[id])
> > + return -EINVAL;
> > +
> > + port = devm_kzalloc(&dev->pdev->dev, sizeof(*port), GFP_KERNEL);
> > + if (!port)
> > + return -ENOMEM;
> > +
> > + dev->ports[id] = port;
> > + port->dev = dev;
> > + port->port_id = id;
> > + port->name = name;
> > + port->num_streams = 0;
> > + return 0;
> > +}
> > +
> > +static void free_port(struct vip_port *port)
> > +{
> > + if (!port)
> > + return;
> > +
> > + v4l2_async_notifier_unregister(&port->notifier);
> > + v4l2_async_notifier_cleanup(&port->notifier);
> > + free_stream(port->cap_streams[0]);
> > +}
> > +
> > +static int get_field(u32 value, u32 mask, int shift)
> > +{
> > + return (value & (mask << shift)) >> shift;
> > +}
> > +
> > +static int vip_probe_complete(struct platform_device *pdev);
> > +static void vip_vpdma_fw_cb(struct platform_device *pdev)
> > +{
> > + dev_info(&pdev->dev, "VPDMA firmware loaded\n");
> > +
> > + if (pdev->dev.of_node)
> > + vip_probe_complete(pdev);
> > +}
> > +
> > +static int vip_create_streams(struct vip_port *port,
> > + struct v4l2_subdev *subdev)
> > +{
> > + struct v4l2_fwnode_bus_parallel *bus;
> > + struct vip_bt656_bus *bt656_ep;
> > + int i;
> > +
> > + for (i = 0; i < VIP_CAP_STREAMS_PER_PORT; i++)
> > + free_stream(port->cap_streams[i]);
> > +
> > + if (get_subdev_active_format(port, subdev))
> > + return -ENODEV;
> > +
> > + port->subdev = subdev;
> > +
> > + if (port->endpoint.bus_type == V4L2_MBUS_PARALLEL) {
> > + port->flags |= FLAG_MULT_PORT;
> > + port->num_streams_configured = 1;
> > + alloc_stream(port, 0, VFL_TYPE_VIDEO);
> > + } else if (port->endpoint.bus_type == V4L2_MBUS_BT656) {
> > + port->flags |= FLAG_MULT_PORT;
> > + bus = &port->endpoint.bus.parallel;
> > + bt656_ep = &port->bt656_endpoint;
> > + port->num_streams_configured = bt656_ep->num_channels;
> > + for (i = 0; i < bt656_ep->num_channels; i++) {
> > + if (bt656_ep->channels[i] >= 16)
> > + continue;
> > + alloc_stream(port, bt656_ep->channels[i],
> > + VFL_TYPE_VIDEO);
> > + }
> > + }
> > + return 0;
> > +}
> > +
> > +static int vip_async_bound(struct v4l2_async_notifier *notifier,
> > + struct v4l2_subdev *subdev,
> > + struct v4l2_async_subdev *asd)
> > +{
> > + struct vip_port *port = notifier_to_vip_port(notifier);
> > + int ret;
> > +
> > + vip_dbg(1, port, "%s\n", __func__);
> > +
> > + if (port->subdev) {
> > + vip_info(port, "Rejecting subdev %s (Already set!!)",
> > + subdev->name);
> > + return 0;
> > + }
> > +
> > + vip_info(port, "Port %c: Using subdev %s for capture\n",
> > + port->port_id == VIP_PORTA ? 'A' : 'B', subdev->name);
> > +
> > + ret = vip_find_pad(subdev, MEDIA_PAD_FL_SOURCE);
> > + if (ret < 0)
> > + return ret;
> > + port->source_pad = ret;
> > + vip_dbg(1, port, "subdev source_pad: %d\n", port->source_pad);
> > +
> > + ret = vip_create_streams(port, subdev);
> > + if (ret)
> > + return ret;
> > +
> > + return 0;
> > +}
> > +
> > +static int vip_async_complete(struct v4l2_async_notifier *notifier)
> > +{
> > + struct vip_port *port = notifier_to_vip_port(notifier);
> > +
> > + vip_dbg(1, port, "%s\n", __func__);
> > + return 0;
> > +}
> > +
> > +static const struct v4l2_async_notifier_operations vip_async_ops = {
> > + .bound = vip_async_bound,
> > + .complete = vip_async_complete,
> > +};
> > +
> > +static struct fwnode_handle *
> > +fwnode_graph_get_next_endpoint_by_regs(const struct fwnode_handle *fwnode,
> > + int port_reg, int reg)
> > +{
> > + return of_fwnode_handle(of_graph_get_endpoint_by_regs(to_of_node(fwnode),
> > + port_reg, reg));
> > +}
> > +
> > +static int vip_register_subdev_notif(struct vip_port *port,
> > + struct fwnode_handle *ep)
> > +{
> > + struct v4l2_async_notifier *notifier = &port->notifier;
> > + struct vip_dev *dev = port->dev;
> > + struct fwnode_handle *subdev;
> > + struct v4l2_fwnode_endpoint *vep;
> > + struct vip_bt656_bus *bt656_vep;
> > + struct v4l2_async_subdev *asd;
> > + int ret, rval;
> > +
> > + vep = &port->endpoint;
> > + bt656_vep = &port->bt656_endpoint;
> > +
> > + subdev = fwnode_graph_get_remote_port_parent(ep);
> > + if (!subdev) {
> > + vip_dbg(3, port, "can't get remote parent\n");
> > + return -EINVAL;
> > + }
> > +
> > + ret = v4l2_fwnode_endpoint_parse(ep, vep);
> > + if (ret) {
> > + vip_dbg(3, port, "Failed to parse endpoint:\n");
> > + fwnode_handle_put(subdev);
> > + return -EINVAL;
> > + }
> > +
> > + if (vep->bus_type == V4L2_MBUS_BT656) {
> > + if (fwnode_property_present(ep, "ti,vip-pixel-mux"))
> > + bt656_vep->pixmux = 1;
> > + else
> > + bt656_vep->pixmux = 0;
> > + vip_dbg(3, port, "ti,vip-pixel-mux %u\n", bt656_vep->pixmux);
> > +
> > + bt656_vep->num_channels = 0;
> > + rval = fwnode_property_read_u8_array(ep, "ti,vip-channels",
> > + NULL, 0);
> > + if (rval > 0) {
> > + bt656_vep->num_channels =
> > + min_t(int, ARRAY_SIZE(bt656_vep->channels),
> > + rval);
> > +
> > + fwnode_property_read_u8_array(ep, "ti,vip-channels",
> > + bt656_vep->channels,
> > + bt656_vep->num_channels);
> > + } else {
> > + /* channels is not specified then assume 1 channel */
> > + bt656_vep->num_channels = 1;
> > + bt656_vep->channels[0] = 0;
> > + }
> > +
> > + vip_dbg(3, port, "ti,vip-channels %u\n",
> > + bt656_vep->num_channels);
> > +
> > + if (bt656_vep->pixmux &&
> > + (bt656_vep->num_channels != 1 ||
> > + bt656_vep->num_channels != 2 ||
> > + bt656_vep->num_channels != 4)) {
> > + vip_warn(port,
> > + "ti,vip-pixel-mux is set but number of channels is not 1, 2 or 4: (%u), disabling ti,vip-pixel-mux.\n",
> > + bt656_vep->num_channels);
> > + bt656_vep->pixmux = 0;
> > + }
> > + }
> > +
> > + v4l2_async_notifier_init(notifier);
> > +
> > + asd = v4l2_async_notifier_add_fwnode_subdev(notifier, subdev,
> > + sizeof(*asd));
> > + if (IS_ERR(asd)) {
> > + vip_dbg(1, port, "Error adding asd\n");
> > + fwnode_handle_put(subdev);
> > + v4l2_async_notifier_cleanup(notifier);
> > + return -EINVAL;
> > + }
> > +
> > + notifier->ops = &vip_async_ops;
> > + ret = v4l2_async_notifier_register(dev->v4l2_dev, notifier);
> > + if (ret) {
> > + vip_dbg(1, port, "Error registering async notifier\n");
> > + v4l2_async_notifier_cleanup(notifier);
> > + ret = -EINVAL;
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +static int vip_endpoint_scan(struct platform_device *pdev)
> > +{
> > + struct device_node *parent = pdev->dev.of_node;
> > + struct device_node *ep = NULL;
> > + int count = 0, p;
> > +
> > + for (p = 0; p < (VIP_NUM_PORTS * VIP_NUM_SLICES); p++) {
> > + ep = of_graph_get_endpoint_by_regs(parent, p, 0);
> > + if (!ep)
> > + continue;
> > +
> > + count++;
> > + of_node_put(ep);
> > + }
> > +
> > + return count;
> > +}
> > +
> > +static const char *vip_parse_fwnode_label(struct fwnode_handle *fwnode)
> > +{
> > + const char *label = NULL;
> > + int ret;
> > +
> > + if (!fwnode)
> > + return NULL;
> > +
> > + ret = fwnode_property_read_string(fwnode, "label", &label);
> > + if (ret)
> > + return ERR_PTR(ret);
> > +
> > + return label;
> > +}
> > +
> > +static int vip_get_clk_polarity(struct platform_device *pdev,
> > + struct vip_clk_polarity *pol)
> > +{
> > + struct device_node *parent = pdev->dev.of_node;
> > + struct of_phandle_args args;
> > + int ret, i;
> > +
> > + if (!pol || !parent ||
> > + !of_property_read_bool(parent, "ti,vip-clk-polarity"))
> > + return -EINVAL;
> > +
> > + pol->rm_pol = syscon_regmap_lookup_by_phandle(parent,
> > + "ti,vip-clk-polarity");
> > + if (IS_ERR(pol->rm_pol)) {
> > + dev_err(&pdev->dev, "failed to get ti,vip-clk-polarity regmap\n");
> > + return PTR_ERR(pol->rm_pol);
> > + }
> > +
> > + ret = of_parse_phandle_with_fixed_args(parent, "ti,vip-clk-polarity",
> > + 5, 0, &args);
> > + if (ret) {
> > + dev_err(&pdev->dev, "failed to parse ti,vip-clk-polarity\n");
> > + return ret;
> > + }
> > +
> > + pol->rm_offset = args.args[0];
> > +
> > + for (i = 0; i < ARRAY_SIZE(pol->rm_bit_field); i++)
> > + pol->rm_bit_field[i] = args.args[i + 1];
> > +
> > + return 0;
> > +}
> > +
> > +static int vip_probe_complete(struct platform_device *pdev)
> > +{
> > + struct vip_shared *shared = platform_get_drvdata(pdev);
> > + struct vip_clk_polarity *pol;
> > + struct vip_port *port;
> > + struct vip_dev *dev;
> > + struct device_node *parent = pdev->dev.of_node;
> > + struct fwnode_handle *ep, *port_node;
> > + const char *port_name;
> > + int ret, slice_id, port_id, p;
> > +
> > + pol = devm_kzalloc(&pdev->dev, sizeof(*pol), GFP_KERNEL);
> > + if (!pol)
> > + return -ENOMEM;
> > +
> > + ret = vip_get_clk_polarity(pdev, pol);
> > + if (ret)
> > + return ret;
> > +
> > + for (p = 0; p < (VIP_NUM_PORTS * VIP_NUM_SLICES); p++) {
> > + ep = fwnode_graph_get_next_endpoint_by_regs(of_fwnode_handle(parent),
> > + p, 0);
> > + if (!ep)
> > + continue;
> > +
> > + port_node = fwnode_get_parent(ep);
> > + if (!port_node) {
> > + dev_err(&pdev->dev, "can't get port of ep(%s)\n",
> > + ep->ops->get_name(ep));
> > + fwnode_handle_put(ep);
> > + return -EINVAL;
> > + }
> > +
> > + port_name = vip_parse_fwnode_label(port_node);
> > + if (IS_ERR_OR_NULL(port_name)) {
> > + dev_err(&pdev->dev, "can't get label of port(%s)\n",
> > + port_node->ops->get_name(port_node));
> > + fwnode_handle_put(ep);
> > + fwnode_handle_put(port_node);
> > + return PTR_ERR(port_name);
> > + }
> > +
> > + switch (p) {
> > + case 0:
> > + slice_id = VIP_SLICE1; port_id = VIP_PORTA;
> > + break;
> > + case 1:
> > + slice_id = VIP_SLICE1; port_id = VIP_PORTB;
> > + break;
> > + case 2:
> > + slice_id = VIP_SLICE2; port_id = VIP_PORTA;
> > + break;
> > + case 3:
> > + slice_id = VIP_SLICE2; port_id = VIP_PORTB;
> > + break;
> > + default:
> > + dev_err(&pdev->dev, "Unknown port reg=<%d>\n", p);
> > + continue;
> > + }
> > +
> > + ret = alloc_port(shared->devs[slice_id], port_id, port_name);
> > + if (ret < 0)
> > + continue;
> > +
> > + dev = shared->devs[slice_id];
> > + dev->pclk_pol = pol;
> > + port = dev->ports[port_id];
> > +
> > + vip_register_subdev_notif(port, ep);
> > + fwnode_handle_put(ep);
> > + fwnode_handle_put(port_node);
> > + }
> > + return 0;
> > +}
> > +
> > +static int vip_probe_slice(struct platform_device *pdev, int slice)
> > +{
> > + struct vip_shared *shared = platform_get_drvdata(pdev);
> > + struct vip_dev *dev;
> > + struct vip_parser_data *parser;
> > + int ret;
> > +
> > + dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
> > + if (!dev)
> > + return -ENOMEM;
> > +
> > + snprintf(dev->name, sizeof(dev->name), "%ss%d", shared->name, slice);
> > +
> > + dev->irq = platform_get_irq(pdev, slice);
> > + if (dev->irq < 0)
> > + return dev->irq;
> > +
> > + ret = devm_request_irq(&pdev->dev, dev->irq, vip_irq,
> > + 0, dev->name, dev);
> > + if (ret < 0)
> > + return -ENOMEM;
> > +
> > + spin_lock_init(&dev->slock);
> > + mutex_init(&dev->mutex);
> > +
> > + dev->slice_id = slice;
> > + dev->pdev = pdev;
> > + dev->res = shared->res;
> > + dev->base = shared->base;
> > + dev->v4l2_dev = &shared->v4l2_dev;
> > +
> > + dev->shared = shared;
> > + shared->devs[slice] = dev;
> > +
> > + vip_top_reset(dev);
> > + vip_set_slice_path(dev, VIP_MULTI_CHANNEL_DATA_SELECT, 1);
> > +
> > + parser = devm_kzalloc(&pdev->dev, sizeof(*dev->parser), GFP_KERNEL);
> > + if (!parser)
> > + return PTR_ERR(parser);
> > +
> > + parser->res = platform_get_resource_byname(pdev,
> > + IORESOURCE_MEM,
> > + (slice == 0) ?
> > + "parser0" :
> > + "parser1");
> > + parser->base = devm_ioremap_resource(&pdev->dev, parser->res);
> > + if (IS_ERR(parser->base))
> > + return PTR_ERR(parser->base);
> > +
> > + parser->pdev = pdev;
> > + dev->parser = parser;
> > +
> > + dev->sc_assigned = VIP_NOT_ASSIGNED;
> > + dev->sc = sc_create(pdev, (slice == 0) ? "sc0" : "sc1");
> > + if (IS_ERR(dev->sc))
> > + return PTR_ERR(dev->sc);
> > +
> > + dev->csc_assigned = VIP_NOT_ASSIGNED;
> > + dev->csc = csc_create(pdev, (slice == 0) ? "csc0" : "csc1");
> > + if (IS_ERR(dev->sc))
> > + return PTR_ERR(dev->sc);
> > +
> > + return 0;
> > +}
> > +
> > +static int vip_probe(struct platform_device *pdev)
> > +{
> > + struct vip_shared *shared;
> > + struct pinctrl *pinctrl;
> > + int ret, slice = VIP_SLICE1;
> > + u32 tmp, pid;
> > + const char *instance_name;
> > + struct fwnode_handle *fwnode;
> > +
> > + fwnode = of_fwnode_handle(pdev->dev.of_node);
> > + if (!fwnode)
> > + return -ENODEV;
> > +
> > + instance_name = vip_parse_fwnode_label(fwnode);
> > + if (IS_ERR_OR_NULL(instance_name))
> > + return PTR_ERR(instance_name);
> > +
> > + /* If there are no endpoint defined there is nothing to do */
> > + if (!vip_endpoint_scan(pdev))
> > + return -ENODEV;
> > +
> > + ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
> > + if (ret) {
> > + dev_err(&pdev->dev,
> > + "32-bit consistent DMA enable failed\n");
> > + return ret;
> > + }
> > +
> > + shared = devm_kzalloc(&pdev->dev, sizeof(*shared), GFP_KERNEL);
> > + if (!shared)
> > + return -ENOMEM;
> > +
> > + shared->res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vip");
> > + shared->base = devm_ioremap_resource(&pdev->dev, shared->res);
> > + if (IS_ERR(shared->base))
> > + return PTR_ERR(shared->base);
> > +
> > + shared->name = instance_name;
> > +
> > + vip_init_format_info(&pdev->dev);
> > +
> > + pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
> > +
> > + pm_runtime_enable(&pdev->dev);
> > +
> > + ret = pm_runtime_get_sync(&pdev->dev);
> > + if (ret)
> > + goto err_runtime_disable;
> > +
> > + /* Make sure H/W module has the right functionality */
> > + pid = reg_read(shared, VIP_PID);
> > + tmp = get_field(pid, VIP_PID_FUNC_MASK, VIP_PID_FUNC_SHIFT);
> > +
> > + if (tmp != VIP_PID_FUNC) {
> > + dev_info(&pdev->dev, "vip: unexpected PID function: 0x%x\n",
> > + tmp);
> > + ret = -ENODEV;
> > + goto err_runtime_put;
> > + }
> > +
> > + ret = v4l2_device_register(&pdev->dev, &shared->v4l2_dev);
> > + if (ret)
> > + goto err_runtime_put;
> > +
> > + /* enable clocks, so the firmware will load properly */
> > + vip_shared_set_clock_enable(shared, 1);
> > + vip_top_vpdma_reset(shared);
> > +
> > + platform_set_drvdata(pdev, shared);
> > +
> > + v4l2_ctrl_handler_init(&shared->ctrl_handler, 11);
> > + shared->v4l2_dev.ctrl_handler = &shared->ctrl_handler;
> > +
> > + for (slice = VIP_SLICE1; slice < VIP_NUM_SLICES; slice++) {
> > + ret = vip_probe_slice(pdev, slice);
> > + if (ret) {
> > + dev_err(&pdev->dev, "Creating slice failed");
> > + goto err_dev_unreg;
> > + }
> > + }
> > +
> > + shared->vpdma = &shared->vpdma_data;
> > + ret = vpdma_create(pdev, shared->vpdma, vip_vpdma_fw_cb);
> > + if (ret) {
> > + dev_err(&pdev->dev, "Creating VPDMA failed");
> > + goto err_dev_unreg;
> > + }
> > +
> > + return 0;
> > +
> > +err_dev_unreg:
> > + v4l2_ctrl_handler_free(&shared->ctrl_handler);
> > + v4l2_device_unregister(&shared->v4l2_dev);
> > +err_runtime_put:
> > + pm_runtime_put_sync(&pdev->dev);
> > +err_runtime_disable:
> > + pm_runtime_disable(&pdev->dev);
> > +
> > + return ret;
> > +}
> > +
> > +static int vip_remove(struct platform_device *pdev)
> > +{
> > + struct vip_shared *shared = platform_get_drvdata(pdev);
> > + struct vip_dev *dev;
> > + int slice;
> > +
> > + for (slice = 0; slice < VIP_NUM_SLICES; slice++) {
> > + dev = shared->devs[slice];
> > + if (!dev)
> > + continue;
> > +
> > + free_port(dev->ports[VIP_PORTA]);
> > + free_port(dev->ports[VIP_PORTB]);
> > + }
> > +
> > + v4l2_ctrl_handler_free(&shared->ctrl_handler);
> > +
> > + pm_runtime_put_sync(&pdev->dev);
> > + pm_runtime_disable(&pdev->dev);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id vip_of_match[] = {
> > + {
> > + .compatible = "ti,dra7-vip",
> > + },
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, vip_of_match);
> > +
> > +static struct platform_driver vip_pdrv = {
> > + .probe = vip_probe,
> > + .remove = vip_remove,
> > + .driver = {
> > + .name = VIP_MODULE_NAME,
> > + .of_match_table = vip_of_match,
> > + },
> > +};
> > +
> > +module_platform_driver(vip_pdrv);
> > +
> > +MODULE_DESCRIPTION("TI VIP driver");
> > +MODULE_AUTHOR("Texas Instruments");
> > +MODULE_LICENSE("GPL v2");
> > diff --git a/drivers/media/platform/ti-vpe/vip.h b/drivers/media/platform/ti-vpe/vip.h
> > new file mode 100644
> > index 000000000000..f078a16a85b7
> > --- /dev/null
> > +++ b/drivers/media/platform/ti-vpe/vip.h
> > @@ -0,0 +1,724 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * TI VIP capture driver
> > + *
> > + * Copyright (C) 2018 Texas Instruments Incorpated - http://www.ti.com/
> > + * David Griego, <dagriego@biglakesoftware.com>
> > + * Dale Farnsworth, <dale@farnsworth.org>
> > + * Nikhil Devshatwar, <nikhil.nd@ti.com>
> > + * Benoit Parrot, <bparrot@ti.com>
> > + */
> > +
> > +#ifndef __TI_VIP_H
> > +#define __TI_VIP_H
> > +
> > +#include <linux/videodev2.h>
> > +#include <media/v4l2-ctrls.h>
> > +#include <media/v4l2-device.h>
> > +#include <media/v4l2-event.h>
> > +#include <media/v4l2-ioctl.h>
> > +#include <media/videobuf2-core.h>
> > +#include <media/videobuf2-dma-contig.h>
> > +#include <media/videobuf2-memops.h>
> > +#include <media/v4l2-fwnode.h>
> > +
> > +#include "vpdma.h"
> > +#include "vpdma_priv.h"
> > +#include "sc.h"
> > +#include "csc.h"
> > +
> > +#define VIP_SLICE1 0
> > +#define VIP_SLICE2 1
> > +#define VIP_NUM_SLICES 2
> > +
> > +/*
> > + * Additionnal client identifiers used for VPDMA configuration descriptors
> > + */
> > +#define VIP_SLICE1_CFD_SC_CLIENT 7
> > +#define VIP_SLICE2_CFD_SC_CLIENT 8
> > +
> > +#define VIP_PORTA 0
> > +#define VIP_PORTB 1
> > +#define VIP_NUM_PORTS 2
> > +
> > +#define VIP_MAX_PLANES 2
> > +#define VIP_LUMA 0
> > +#define VIP_CHROMA 1
> > +
> > +#define VIP_CAP_STREAMS_PER_PORT 16
> > +#define VIP_VBI_STREAMS_PER_PORT 16
> > +
> > +#define VIP_MAX_SUBDEV 5
> > +/*
> > + * This value needs to be at least as large as the number of entry in
> > + * vip_formats[].
> > + * When vip_formats[] is modified make sure to adjust this value also.
> > + */
> > +#define VIP_MAX_ACTIVE_FMT 16
> > +/*
> > + * Colorspace conversion unit can be in one of 3 modes:
> > + * NA - Not Available on this port
> > + * Y2R - Needed for YUV to RGB on this port
> > + * R2Y - Needed for RGB to YUV on this port
> > + */
> > +enum vip_csc_state {
> > + VIP_CSC_NA = 0,
> > + VIP_CSC_Y2R,
> > + VIP_CSC_R2Y,
> > +};
> > +
> > +/* buffer for one video frame */
> > +struct vip_buffer {
> > + /* common v4l buffer stuff */
> > + struct vb2_v4l2_buffer vb;
> > + struct list_head list;
> > + bool drop;
> > +};
> > +
> > +/*
> > + * struct vip_fmt - VIP media bus format information
> > + * @fourcc: V4L2 pixel format FCC identifier
> > + * @code: V4L2 media bus format code
> > + * @colorspace: V4L2 colorspace identifier
> > + * @coplanar: 1 if unpacked Luma and Chroma, 0 otherwise (packed/interleaved)
> > + * @vpdma_fmt: VPDMA data format per plane.
> > + * @finfo: Cache v4l2_format_info for associated fourcc
> > + */
> > +struct vip_fmt {
> > + u32 fourcc;
> > + u32 code;
> > + u32 colorspace;
> > + u8 coplanar;
> > + const struct vpdma_data_format *vpdma_fmt[VIP_MAX_PLANES];
> > + const struct v4l2_format_info *finfo;
> > +};
> > +
> > +/*
> > + * The vip_parser_data structures contains the memory mapped
> > + * info to access the parser registers.
> > + */
> > +struct vip_parser_data {
> > + void __iomem *base;
> > + struct resource *res;
> > +
> > + struct platform_device *pdev;
> > +};
> > +
> > +/*
> > + * The vip_shared structure contains data that is shared by both
> > + * the VIP1 and VIP2 slices.
> > + */
> > +struct vip_shared {
> > + struct list_head list;
> > + struct resource *res;
> > + void __iomem *base;
> > + struct vpdma_data vpdma_data;
> > + struct vpdma_data *vpdma;
> > + struct v4l2_device v4l2_dev;
> > + struct vip_dev *devs[VIP_NUM_SLICES];
> > + struct v4l2_ctrl_handler ctrl_handler;
> > + const char *name;
> > +};
> > +
> > +/*
> > + * The vip_bt656_bus structure contains vip specific bt656 bus data.
> > + */
> > +struct vip_bt656_bus {
> > + unsigned char num_channels;
> > + unsigned char pixmux;
> > + unsigned char channels[16];
> > +};
> > +
> > +/*
> > + * The vip_clk_polarity structure contains the regmap, offset and bit field
> > + * definitions to control each port clock polarity.
> > + */
> > +struct vip_clk_polarity {
> > + struct regmap *rm_pol;
> > + u32 rm_offset;
> > + u32 rm_bit_field[4];
> > +};
> > +/*
> > + * There are two vip_dev structure, one for each vip slice: VIP1 & VIP2.
> > + */
> > +struct vip_dev {
> > + struct v4l2_device *v4l2_dev;
> > + struct platform_device *pdev;
> > + struct vip_shared *shared;
> > + struct resource *res;
> > + struct vip_clk_polarity *pclk_pol;
> > + int slice_id;
> > + int num_ports; /* count of open ports */
> > + struct mutex mutex;
> > + spinlock_t slock;
> > +
> > + int irq;
> > + void __iomem *base;
> > +
> > + struct vip_port *ports[VIP_NUM_PORTS];
> > +
> > + char name[16];
> > + /* parser data handle */
> > + struct vip_parser_data *parser;
> > + /* scaler data handle */
> > + struct sc_data *sc;
> > + /* scaler port assignation */
> > + int sc_assigned;
> > + /* csc data handle */
> > + struct csc_data *csc;
> > + /* csc port assignation */
> > + int csc_assigned;
> > +};
> > +
> > +/*
> > + * There are two vip_port structures for each vip_dev, one for port A
> > + * and one for port B.
> > + */
> > +struct vip_port {
> > + struct vip_dev *dev;
> > + int port_id;
> > +
> > + unsigned int flags;
> > + struct v4l2_rect c_rect; /* crop rectangle */
> > + struct v4l2_mbus_framefmt mbus_framefmt;
> > + struct v4l2_mbus_framefmt try_mbus_framefmt;
> > +
> > + const char *name;
> > + struct vip_fmt *fmt; /* current format info */
> > + /* Number of channels/streams configured */
> > + int num_streams_configured;
> > + int num_streams; /* count of open streams */
> > + struct vip_stream *cap_streams[VIP_CAP_STREAMS_PER_PORT];
> > +
> > + struct v4l2_async_notifier notifier;
> > + struct v4l2_subdev *subdev;
> > + struct v4l2_fwnode_endpoint endpoint;
> > + struct vip_bt656_bus bt656_endpoint;
> > + unsigned int source_pad;
> > + struct vip_fmt *active_fmt[VIP_MAX_ACTIVE_FMT];
> > + int num_active_fmt;
> > + /* have new shadow reg values */
> > + bool load_mmrs;
> > + /* shadow reg addr/data block */
> > + struct vpdma_buf mmr_adb;
> > + /* h coeff buffer */
> > + struct vpdma_buf sc_coeff_h;
> > + /* v coeff buffer */
> > + struct vpdma_buf sc_coeff_v;
> > + /* Show if scaler resource is available on this port */
> > + bool scaler;
> > + /* Show the csc resource state on this port */
> > + enum vip_csc_state csc;
> > +};
> > +
> > +/*
> > + * When handling multiplexed video, there can be multiple streams for each
> > + * port. The vip_stream structure holds per-stream data.
> > + */
> > +struct vip_stream {
> > + struct video_device *vfd;
> > + struct vip_port *port;
> > + int stream_id;
> > + int list_num;
> > + int vfl_type;
> > + char name[16];
> > + struct work_struct recovery_work;
> > + int num_recovery;
> > + enum v4l2_field field; /* current field */
> > + unsigned int sequence; /* current frame/field seq */
> > + enum v4l2_field sup_field; /* supported field value */
> > + unsigned int width; /* frame width */
> > + unsigned int height; /* frame height */
> > + unsigned int bytesperline; /* bytes per line in memory */
> > + unsigned int sizeimage; /* image size in memory */
> > + struct list_head vidq; /* incoming vip_bufs queue */
> > + struct list_head dropq; /* drop vip_bufs queue */
> > + struct list_head post_bufs; /* vip_bufs to be DMAed */
> > + /* Maintain a list of used channels - Needed for VPDMA cleanup */
> > + int vpdma_channels[VPDMA_MAX_CHANNELS];
> > + int vpdma_channels_to_abort[VPDMA_MAX_CHANNELS];
> > + struct vpdma_desc_list desc_list; /* DMA descriptor list */
> > + struct vpdma_dtd *write_desc;
> > + /* next unused desc_list addr */
> > + void *desc_next;
> > + struct vb2_queue vb_vidq;
> > +};
> > +
> > +/*
> > + * VIP Enumerations
> > + */
> > +enum data_path_select {
> > + ALL_FIELDS_DATA_SELECT = 0,
> > + VIP_CSC_SRC_DATA_SELECT,
> > + VIP_SC_SRC_DATA_SELECT,
> > + VIP_RGB_SRC_DATA_SELECT,
> > + VIP_RGB_OUT_LO_DATA_SELECT,
> > + VIP_RGB_OUT_HI_DATA_SELECT,
> > + VIP_CHR_DS_1_SRC_DATA_SELECT,
> > + VIP_CHR_DS_2_SRC_DATA_SELECT,
> > + VIP_MULTI_CHANNEL_DATA_SELECT,
> > + VIP_CHR_DS_1_DATA_BYPASS,
> > + VIP_CHR_DS_2_DATA_BYPASS,
> > +};
> > +
> > +
> > +enum data_interface_modes {
> > + SINGLE_24B_INTERFACE = 0,
> > + SINGLE_16B_INTERFACE = 1,
> > + DUAL_8B_INTERFACE = 2,
> > +};
> > +
> > +enum sync_types {
> > + EMBEDDED_SYNC_SINGLE_YUV422 = 0,
> > + EMBEDDED_SYNC_2X_MULTIPLEXED_YUV422 = 1,
> > + EMBEDDED_SYNC_4X_MULTIPLEXED_YUV422 = 2,
> > + EMBEDDED_SYNC_LINE_MULTIPLEXED_YUV422 = 3,
> > + DISCRETE_SYNC_SINGLE_YUV422 = 4,
> > + EMBEDDED_SYNC_SINGLE_RGB_OR_YUV444 = 5,
> > + DISCRETE_SYNC_SINGLE_RGB_24B = 10,
> > +};
> > +
> > +#define VIP_NOT_ASSIGNED -1
> > +
> > +/*
> > + * Register offsets and field selectors
> > + */
> > +#define VIP_PID_FUNC 0xf02
> > +
> > +#define VIP_PID 0x0000
> > +#define VIP_PID_MINOR_MASK 0x3f
> > +#define VIP_PID_MINOR_SHIFT 0
> > +#define VIP_PID_CUSTOM_MASK 0x03
> > +#define VIP_PID_CUSTOM_SHIFT 6
> > +#define VIP_PID_MAJOR_MASK 0x07
> > +#define VIP_PID_MAJOR_SHIFT 8
> > +#define VIP_PID_RTL_MASK 0x1f
> > +#define VIP_PID_RTL_SHIFT 11
> > +#define VIP_PID_FUNC_MASK 0xfff
> > +#define VIP_PID_FUNC_SHIFT 16
> > +#define VIP_PID_SCHEME_MASK 0x03
> > +#define VIP_PID_SCHEME_SHIFT 30
> > +
> > +#define VIP_SYSCONFIG 0x0010
> > +#define VIP_SYSCONFIG_IDLE_MASK 0x03
> > +#define VIP_SYSCONFIG_IDLE_SHIFT 2
> > +#define VIP_SYSCONFIG_STANDBY_MASK 0x03
> > +#define VIP_SYSCONFIG_STANDBY_SHIFT 4
> > +#define VIP_FORCE_IDLE_MODE 0
> > +#define VIP_NO_IDLE_MODE 1
> > +#define VIP_SMART_IDLE_MODE 2
> > +#define VIP_SMART_IDLE_WAKEUP_MODE 3
> > +#define VIP_FORCE_STANDBY_MODE 0
> > +#define VIP_NO_STANDBY_MODE 1
> > +#define VIP_SMART_STANDBY_MODE 2
> > +#define VIP_SMART_STANDBY_WAKEUP_MODE 3
> > +
> > +#define VIP_INTC_INTX_OFFSET 0x0020
> > +
> > +#define VIP_INT0_STATUS0_RAW_SET 0x0020
> > +#define VIP_INT0_STATUS0_RAW VIP_INT0_STATUS0_RAW_SET
> > +#define VIP_INT0_STATUS0_CLR 0x0028
> > +#define VIP_INT0_STATUS0 VIP_INT0_STATUS0_CLR
> > +#define VIP_INT0_ENABLE0_SET 0x0030
> > +#define VIP_INT0_ENABLE0 VIP_INT0_ENABLE0_SET
> > +#define VIP_INT0_ENABLE0_CLR 0x0038
> > +#define VIP_INT0_LIST0_COMPLETE BIT(0)
> > +#define VIP_INT0_LIST0_NOTIFY BIT(1)
> > +#define VIP_INT0_LIST1_COMPLETE BIT(2)
> > +#define VIP_INT0_LIST1_NOTIFY BIT(3)
> > +#define VIP_INT0_LIST2_COMPLETE BIT(4)
> > +#define VIP_INT0_LIST2_NOTIFY BIT(5)
> > +#define VIP_INT0_LIST3_COMPLETE BIT(6)
> > +#define VIP_INT0_LIST3_NOTIFY BIT(7)
> > +#define VIP_INT0_LIST4_COMPLETE BIT(8)
> > +#define VIP_INT0_LIST4_NOTIFY BIT(9)
> > +#define VIP_INT0_LIST5_COMPLETE BIT(10)
> > +#define VIP_INT0_LIST5_NOTIFY BIT(11)
> > +#define VIP_INT0_LIST6_COMPLETE BIT(12)
> > +#define VIP_INT0_LIST6_NOTIFY BIT(13)
> > +#define VIP_INT0_LIST7_COMPLETE BIT(14)
> > +#define VIP_INT0_LIST7_NOTIFY BIT(15)
> > +#define VIP_INT0_DESCRIPTOR BIT(16)
> > +#define VIP_VIP1_PARSER_INT BIT(20)
> > +#define VIP_VIP2_PARSER_INT BIT(21)
> > +
> > +#define VIP_INT0_STATUS1_RAW_SET 0x0024
> > +#define VIP_INT0_STATUS1_RAW VIP_INT0_STATUS0_RAW_SET
> > +#define VIP_INT0_STATUS1_CLR 0x002c
> > +#define VIP_INT0_STATUS1 VIP_INT0_STATUS0_CLR
> > +#define VIP_INT0_ENABLE1_SET 0x0034
> > +#define VIP_INT0_ENABLE1 VIP_INT0_ENABLE0_SET
> > +#define VIP_INT0_ENABLE1_CLR 0x003c
> > +#define VIP_INT0_ENABLE1_STAT 0x004c
> > +#define VIP_INT0_CHANNEL_GROUP0 BIT(0)
> > +#define VIP_INT0_CHANNEL_GROUP1 BIT(1)
> > +#define VIP_INT0_CHANNEL_GROUP2 BIT(2)
> > +#define VIP_INT0_CHANNEL_GROUP3 BIT(3)
> > +#define VIP_INT0_CHANNEL_GROUP4 BIT(4)
> > +#define VIP_INT0_CHANNEL_GROUP5 BIT(5)
> > +#define VIP_INT0_CLIENT BIT(7)
> > +#define VIP_VIP1_DS1_UV_ERROR_INT BIT(22)
> > +#define VIP_VIP1_DS2_UV_ERROR_INT BIT(23)
> > +#define VIP_VIP2_DS1_UV_ERROR_INT BIT(24)
> > +#define VIP_VIP2_DS2_UV_ERROR_INT BIT(25)
> > +
> > +#define VIP_INTC_E0I 0x00a0
> > +
> > +#define VIP_CLK_ENABLE 0x0100
> > +#define VIP_VPDMA_CLK_ENABLE BIT(0)
> > +#define VIP_VIP1_DATA_PATH_CLK_ENABLE BIT(16)
> > +#define VIP_VIP2_DATA_PATH_CLK_ENABLE BIT(17)
> > +
> > +#define VIP_CLK_RESET 0x0104
> > +#define VIP_VPDMA_RESET BIT(0)
> > +#define VIP_VPDMA_CLK_RESET_MASK 0x1
> > +#define VIP_VPDMA_CLK_RESET_SHIFT 0
> > +#define VIP_DATA_PATH_CLK_RESET_MASK 0x1
> > +#define VIP_VIP1_DATA_PATH_RESET_SHIFT 16
> > +#define VIP_VIP2_DATA_PATH_RESET_SHIFT 17
> > +#define VIP_VIP1_DATA_PATH_RESET BIT(16)
> > +#define VIP_VIP2_DATA_PATH_RESET BIT(17)
> > +#define VIP_VIP1_PARSER_RESET BIT(18)
> > +#define VIP_VIP2_PARSER_RESET BIT(19)
> > +#define VIP_VIP1_CSC_RESET BIT(20)
> > +#define VIP_VIP2_CSC_RESET BIT(21)
> > +#define VIP_VIP1_SC_RESET BIT(22)
> > +#define VIP_VIP2_SC_RESET BIT(23)
> > +#define VIP_VIP1_DS1_RESET BIT(25)
> > +#define VIP_VIP2_DS1_RESET BIT(26)
> > +#define VIP_VIP1_DS2_RESET BIT(27)
> > +#define VIP_VIP2_DS2_RESET BIT(28)
> > +#define VIP_MAIN_RESET BIT(31)
> > +
> > +#define VIP_VIP1_DATA_PATH_SELECT 0x010c
> > +#define VIP_VIP2_DATA_PATH_SELECT 0x0110
> > +#define VIP_CSC_SRC_SELECT_MASK 0x07
> > +#define VIP_CSC_SRC_SELECT_SHFT 0
> > +#define VIP_SC_SRC_SELECT_MASK 0x07
> > +#define VIP_SC_SRC_SELECT_SHFT 3
> > +#define VIP_RGB_SRC_SELECT BIT(6)
> > +#define VIP_RGB_OUT_LO_SRC_SELECT BIT(7)
> > +#define VIP_RGB_OUT_HI_SRC_SELECT BIT(8)
> > +#define VIP_DS1_SRC_SELECT_MASK 0x07
> > +#define VIP_DS1_SRC_SELECT_SHFT 9
> > +#define VIP_DS2_SRC_SELECT_MASK 0x07
> > +#define VIP_DS2_SRC_SELECT_SHFT 12
> > +#define VIP_MULTI_CHANNEL_SELECT BIT(15)
> > +#define VIP_DS1_BYPASS BIT(16)
> > +#define VIP_DS2_BYPASS BIT(17)
> > +#define VIP_TESTPORT_B_SELECT BIT(26)
> > +#define VIP_TESTPORT_A_SELECT BIT(27)
> > +#define VIP_DATAPATH_SELECT_MASK 0x0f
> > +#define VIP_DATAPATH_SELECT_SHFT 28
> > +
> > +#define VIP1_PARSER_REG_OFFSET 0x5500
> > +#define VIP2_PARSER_REG_OFFSET 0x5a00
> > +
> > +#define VIP_PARSER_MAIN_CFG 0x0000
> > +#define VIP_DATA_INTERFACE_MODE_MASK 0x03
> > +#define VIP_DATA_INTERFACE_MODE_SHFT 0
> > +#define VIP_CLIP_BLANK BIT(4)
> > +#define VIP_CLIP_ACTIVE BIT(5)
> > +
> > +#define VIP_PARSER_PORTA_0 0x0004
> > +#define VIP_PARSER_PORTB_0 0x000c
> > +#define VIP_SYNC_TYPE_MASK 0x0f
> > +#define VIP_SYNC_TYPE_SHFT 0
> > +#define VIP_CTRL_CHANNEL_SEL_MASK 0x03
> > +#define VIP_CTRL_CHANNEL_SEL_SHFT 4
> > +#define VIP_ASYNC_FIFO_WR BIT(6)
> > +#define VIP_ASYNC_FIFO_RD BIT(7)
> > +#define VIP_PORT_ENABLE BIT(8)
> > +#define VIP_FID_POLARITY BIT(9)
> > +#define VIP_PIXCLK_EDGE_POLARITY BIT(10)
> > +#define VIP_HSYNC_POLARITY BIT(11)
> > +#define VIP_VSYNC_POLARITY BIT(12)
> > +#define VIP_ACTVID_POLARITY BIT(13)
> > +#define VIP_FID_DETECT_MODE BIT(14)
> > +#define VIP_USE_ACTVID_HSYNC_ONLY BIT(15)
> > +#define VIP_FID_SKEW_PRECOUNT_MASK 0x3f
> > +#define VIP_FID_SKEW_PRECOUNT_SHFT 16
> > +#define VIP_DISCRETE_BASIC_MODE BIT(22)
> > +#define VIP_SW_RESET BIT(23)
> > +#define VIP_FID_SKEW_POSTCOUNT_MASK 0x3f
> > +#define VIP_FID_SKEW_POSTCOUNT_SHFT 24
> > +#define VIP_ANALYZER_2X4X_SRCNUM_POS BIT(30)
> > +#define VIP_ANALYZER_FVH_ERR_COR_EN BIT(31)
> > +
> > +#define VIP_PARSER_PORTA_1 0x0008
> > +#define VIP_PARSER_PORTB_1 0x0010
> > +#define VIP_SRC0_NUMLINES_MASK 0x0fff
> > +#define VIP_SRC0_NUMLINES_SHFT 0
> > +#define VIP_ANC_CHAN_SEL_8B_MASK 0x03
> > +#define VIP_ANC_CHAN_SEL_8B_SHFT 13
> > +#define VIP_SRC0_NUMPIX_MASK 0x0fff
> > +#define VIP_SRC0_NUMPIX_SHFT 16
> > +#define VIP_REPACK_SEL_MASK 0x07
> > +#define VIP_REPACK_SEL_SHFT 28
> > +
> > +#define VIP_PARSER_FIQ_MASK 0x0014
> > +#define VIP_PARSER_FIQ_CLR 0x0018
> > +#define VIP_PARSER_FIQ_STATUS 0x001c
> > +#define VIP_PORTA_VDET BIT(0)
> > +#define VIP_PORTB_VDET BIT(1)
> > +#define VIP_PORTA_ASYNC_FIFO_OF BIT(2)
> > +#define VIP_PORTB_ASYNC_FIFO_OF BIT(3)
> > +#define VIP_PORTA_OUTPUT_FIFO_YUV BIT(4)
> > +#define VIP_PORTA_OUTPUT_FIFO_ANC BIT(6)
> > +#define VIP_PORTB_OUTPUT_FIFO_YUV BIT(7)
> > +#define VIP_PORTB_OUTPUT_FIFO_ANC BIT(9)
> > +#define VIP_PORTA_CONN BIT(10)
> > +#define VIP_PORTA_DISCONN BIT(11)
> > +#define VIP_PORTB_CONN BIT(12)
> > +#define VIP_PORTB_DISCONN BIT(13)
> > +#define VIP_PORTA_SRC0_SIZE BIT(14)
> > +#define VIP_PORTB_SRC0_SIZE BIT(15)
> > +#define VIP_PORTA_YUV_PROTO_VIOLATION BIT(16)
> > +#define VIP_PORTA_ANC_PROTO_VIOLATION BIT(17)
> > +#define VIP_PORTB_YUV_PROTO_VIOLATION BIT(18)
> > +#define VIP_PORTB_ANC_PROTO_VIOLATION BIT(19)
> > +#define VIP_PORTA_CFG_DISABLE_COMPLETE BIT(20)
> > +#define VIP_PORTB_CFG_DISABLE_COMPLETE BIT(21)
> > +
> > +#define VIP_PARSER_PORTA_SOURCE_FID 0x0020
> > +#define VIP_PARSER_PORTA_ENCODER_FID 0x0024
> > +#define VIP_PARSER_PORTB_SOURCE_FID 0x0028
> > +#define VIP_PARSER_PORTB_ENCODER_FID 0x002c
> > +
> > +#define VIP_PARSER_PORTA_SRC0_SIZE 0x0030
> > +#define VIP_PARSER_PORTB_SRC0_SIZE 0x0070
> > +#define VIP_SOURCE_HEIGHT_MASK 0x0fff
> > +#define VIP_SOURCE_HEIGHT_SHFT 0
> > +#define VIP_SOURCE_WIDTH_MASK 0x0fff
> > +#define VIP_SOURCE_WIDTH_SHFT 16
> > +
> > +#define VIP_PARSER_PORTA_VDET_VEC 0x00b0
> > +#define VIP_PARSER_PORTB_VDET_VEC 0x00b4
> > +
> > +#define VIP_PARSER_PORTA_EXTRA2 0x00b8
> > +#define VIP_PARSER_PORTB_EXTRA2 0x00c8
> > +#define VIP_ANC_SKIP_NUMPIX_MASK 0x0fff
> > +#define VIP_ANC_SKIP_NUMPIX_SHFT 0
> > +#define VIP_ANC_BYPASS BIT(15)
> > +#define VIP_ANC_USE_NUMPIX_MASK 0x0fff
> > +#define VIP_ANC_USE_NUMPIX_SHFT 16
> > +#define VIP_ANC_TARGET_SRCNUM_MASK 0x0f
> > +#define VIP_ANC_TARGET_SRCNUM_SHFT 28
> > +
> > +#define VIP_PARSER_PORTA_EXTRA3 0x00bc
> > +#define VIP_PARSER_PORTB_EXTRA3 0x00cc
> > +#define VIP_ANC_SKIP_NUMLINES_MASK 0x0fff
> > +#define VIP_ANC_SKIP_NUMLINES_SHFT 0
> > +#define VIP_ANC_USE_NUMLINES_MASK 0x0fff
> > +#define VIP_ANC_USE_NUMLINES_SHFT 16
> > +
> > +#define VIP_PARSER_PORTA_EXTRA4 0x00c0
> > +#define VIP_PARSER_PORTB_EXTRA4 0x00d0
> > +#define VIP_ACT_SKIP_NUMPIX_MASK 0x0fff
> > +#define VIP_ACT_SKIP_NUMPIX_SHFT 0
> > +#define VIP_ACT_BYPASS BIT(15)
> > +#define VIP_ACT_USE_NUMPIX_MASK 0x0fff
> > +#define VIP_ACT_USE_NUMPIX_SHFT 16
> > +#define VIP_ACT_TARGET_SRCNUM_MASK 0x0f
> > +#define VIP_ACT_TARGET_SRCNUM_SHFT 28
> > +
> > +#define VIP_PARSER_PORTA_EXTRA5 0x00c4
> > +#define VIP_PARSER_PORTB_EXTRA5 0x00d4
> > +#define VIP_ACT_SKIP_NUMLINES_MASK 0x0fff
> > +#define VIP_ACT_SKIP_NUMLINES_SHFT 0
> > +#define VIP_ACT_USE_NUMLINES_MASK 0x0fff
> > +#define VIP_ACT_USE_NUMLINES_SHFT 16
> > +
> > +#define VIP_PARSER_PORTA_EXTRA6 0x00d8
> > +#define VIP_PARSER_PORTB_EXTRA6 0x00dc
> > +#define VIP_ANC_SRCNUM_STOP_IMM_SHFT 0
> > +#define VIP_YUV_SRCNUM_STOP_IMM_SHFT 16
> > +
> > +#define VIP_CSC_CSC00 0x0200
> > +#define VIP_CSC_A0_MASK 0x1fff
> > +#define VIP_CSC_A0_SHFT 0
> > +#define VIP_CSC_B0_MASK 0x1fff
> > +#define VIP_CSC_B0_SHFT 16
> > +
> > +#define VIP_CSC_CSC01 0x0204
> > +#define VIP_CSC_C0_MASK 0x1fff
> > +#define VIP_CSC_C0_SHFT 0
> > +#define VIP_CSC_A1_MASK 0x1fff
> > +#define VIP_CSC_A1_SHFT 16
> > +
> > +#define VIP_CSC_CSC02 0x0208
> > +#define VIP_CSC_B1_MASK 0x1fff
> > +#define VIP_CSC_B1_SHFT 0
> > +#define VIP_CSC_C1_MASK 0x1fff
> > +#define VIP_CSC_C1_SHFT 16
> > +
> > +#define VIP_CSC_CSC03 0x020c
> > +#define VIP_CSC_A2_MASK 0x1fff
> > +#define VIP_CSC_A2_SHFT 0
> > +#define VIP_CSC_B2_MASK 0x1fff
> > +#define VIP_CSC_B2_SHFT 16
> > +
> > +#define VIP_CSC_CSC04 0x0210
> > +#define VIP_CSC_C2_MASK 0x1fff
> > +#define VIP_CSC_C2_SHFT 0
> > +#define VIP_CSC_D0_MASK 0x0fff
> > +#define VIP_CSC_D0_SHFT 16
> > +
> > +#define VIP_CSC_CSC05 0x0214
> > +#define VIP_CSC_D1_MASK 0x0fff
> > +#define VIP_CSC_D1_SHFT 0
> > +#define VIP_CSC_D2_MASK 0x0fff
> > +#define VIP_CSC_D2_SHFT 16
> > +#define VIP_CSC_BYPASS BIT(28)
> > +
> > +#define VIP_SC_MP_SC0 0x0300
> > +#define VIP_INTERLACE_O BIT(0)
> > +#define VIP_LINEAR BIT(1)
> > +#define VIP_SC_BYPASS BIT(2)
> > +#define VIP_INVT_FID BIT(3)
> > +#define VIP_USE_RAV BIT(4)
> > +#define VIP_ENABLE_EV BIT(5)
> > +#define VIP_AUTH_HS BIT(6)
> > +#define VIP_DCM_2X BIT(7)
> > +#define VIP_DCM_4X BIT(8)
> > +#define VIP_HP_BYPASS BIT(9)
> > +#define VIP_INTERLACE_I BIT(10)
> > +#define VIP_ENABLE_SIN2_VER_INTP BIT(11)
> > +#define VIP_Y_PK_EN BIT(14)
> > +#define VIP_TRIM BIT(15)
> > +#define VIP_SELFGEN_FID BIT(16)
> > +
> > +#define VIP_SC_MP_SC1 0x0304
> > +#define VIP_ROW_ACC_INC_MASK 0x07ffffff
> > +#define VIP_ROW_ACC_INC_SHFT 0
> > +
> > +#define VIP_SC_MP_SC2 0x0308
> > +#define VIP_ROW_ACC_OFFSET_MASK 0x0fffffff
> > +#define VIP_ROW_ACC_OFFSET_SHFT 0
> > +
> > +#define VIP_SC_MP_SC3 0x030c
> > +#define VIP_ROW_ACC_OFFSET_B_MASK 0x0fffffff
> > +#define VIP_ROW_ACC_OFFSET_B_SHFT 0
> > +
> > +#define VIP_SC_MP_SC4 0x0310
> > +#define VIP_TAR_H_MASK 0x07ff
> > +#define VIP_TAR_H_SHFT 0
> > +#define VIP_TAR_W_MASK 0x07ff
> > +#define VIP_TAR_W_SHFT 12
> > +#define VIP_LIN_ACC_INC_U_MASK 0x07
> > +#define VIP_LIN_ACC_INC_U_SHFT 24
> > +#define VIP_NLIN_ACC_INIT_U_MASK 0x07
> > +#define VIP_NLIN_ACC_INIT_U_SHFT 28
> > +
> > +#define VIP_SC_MP_SC5 0x0314
> > +#define VIP_SRC_H_MASK 0x03ff
> > +#define VIP_SRC_H_SHFT 0
> > +#define VIP_SRC_W_MASK 0x07ff
> > +#define VIP_SRC_W_SHFT 12
> > +#define VIP_NLIN_ACC_INC_U_MASK 0x07
> > +#define VIP_NLIN_ACC_INC_U_SHFT 24
> > +
> > +#define VIP_SC_MP_SC6 0x0318
> > +#define VIP_ROW_ACC_INIT_RAV_MASK 0x03ff
> > +#define VIP_ROW_ACC_INIT_RAV_SHFT 0
> > +#define VIP_ROW_ACC_INIT_RAV_B_MASK 0x03ff
> > +#define VIP_ROW_ACC_INIT_RAV_B_SHFT 10
> > +
> > +#define VIP_SC_MP_SC8 0x0320
> > +#define VIP_NLIN_LEFT_MASK 0x07ff
> > +#define VIP_NLIN_LEFT_SHFT 0
> > +#define VIP_NLIN_RIGHT_MASK 0x07ff
> > +#define VIP_NLIN_RIGHT_SHFT 12
> > +
> > +#define VIP_SC_MP_SC9 0x0324
> > +#define VIP_LIN_ACC_INC VIP_SC_MP_SC9
> > +
> > +#define VIP_SC_MP_SC10 0x0328
> > +#define VIP_NLIN_ACC_INIT VIP_SC_MP_SC10
> > +
> > +#define VIP_SC_MP_SC11 0x032c
> > +#define VIP_NLIN_ACC_INC VIP_SC_MP_SC11
> > +
> > +#define VIP_SC_MP_SC12 0x0330
> > +#define VIP_COL_ACC_OFFSET_MASK 0x01ffffff
> > +#define VIP_COL_ACC_OFFSET_SHFT 0
> > +
> > +#define VIP_SC_MP_SC13 0x0334
> > +#define VIP_SC_FACTOR_RAV_MASK 0x03ff
> > +#define VIP_SC_FACTOR_RAV_SHFT 0
> > +#define VIP_CHROMA_INTP_THR_MASK 0x03ff
> > +#define VIP_CHROMA_INTP_THR_SHFT 12
> > +#define VIP_DELTA_CHROMA_THR_MASK 0x0f
> > +#define VIP_DELTA_CHROMA_THR_SHFT 24
> > +
> > +#define VIP_SC_MP_SC17 0x0344
> > +#define VIP_EV_THR_MASK 0x03ff
> > +#define VIP_EV_THR_SHFT 12
> > +#define VIP_DELTA_LUMA_THR_MASK 0x0f
> > +#define VIP_DELTA_LUMA_THR_SHFT 24
> > +#define VIP_DELTA_EV_THR_MASK 0x0f
> > +#define VIP_DELTA_EV_THR_SHFT 28
> > +
> > +#define VIP_SC_MP_SC18 0x0348
> > +#define VIP_HS_FACTOR_MASK 0x03ff
> > +#define VIP_HS_FACTOR_SHFT 0
> > +#define VIP_CONF_DEFAULT_MASK 0x01ff
> > +#define VIP_CONF_DEFAULT_SHFT 16
> > +
> > +#define VIP_SC_MP_SC19 0x034c
> > +#define VIP_HPF_COEFF0_MASK 0xff
> > +#define VIP_HPF_COEFF0_SHFT 0
> > +#define VIP_HPF_COEFF1_MASK 0xff
> > +#define VIP_HPF_COEFF1_SHFT 8
> > +#define VIP_HPF_COEFF2_MASK 0xff
> > +#define VIP_HPF_COEFF2_SHFT 16
> > +#define VIP_HPF_COEFF3_MASK 0xff
> > +#define VIP_HPF_COEFF3_SHFT 23
> > +
> > +#define VIP_SC_MP_SC20 0x0350
> > +#define VIP_HPF_COEFF4_MASK 0xff
> > +#define VIP_HPF_COEFF4_SHFT 0
> > +#define VIP_HPF_COEFF5_MASK 0xff
> > +#define VIP_HPF_COEFF5_SHFT 8
> > +#define VIP_HPF_NORM_SHFT_MASK 0x07
> > +#define VIP_HPF_NORM_SHFT_SHFT 16
> > +#define VIP_NL_LIMIT_MASK 0x1ff
> > +#define VIP_NL_LIMIT_SHFT 20
> > +
> > +#define VIP_SC_MP_SC21 0x0354
> > +#define VIP_NL_LO_THR_MASK 0x01ff
> > +#define VIP_NL_LO_THR_SHFT 0
> > +#define VIP_NL_LO_SLOPE_MASK 0xff
> > +#define VIP_NL_LO_SLOPE_SHFT 16
> > +
> > +#define VIP_SC_MP_SC22 0x0358
> > +#define VIP_NL_HI_THR_MASK 0x01ff
> > +#define VIP_NL_HI_THR_SHFT 0
> > +#define VIP_NL_HI_SLOPE_SH_MASK 0x07
> > +#define VIP_NL_HI_SLOPE_SH_SHFT 16
> > +
> > +#define VIP_SC_MP_SC23 0x035c
> > +#define VIP_GRADIENT_THR_MASK 0x07ff
> > +#define VIP_GRADIENT_THR_SHFT 0
> > +#define VIP_GRADIENT_THR_RANGE_MASK 0x0f
> > +#define VIP_GRADIENT_THR_RANGE_SHFT 12
> > +#define VIP_MIN_GY_THR_MASK 0xff
> > +#define VIP_MIN_GY_THR_SHFT 16
> > +#define VIP_MIN_GY_THR_RANGE_MASK 0x0f
> > +#define VIP_MIN_GY_THR_RANGE_SHFT 28
> > +
> > +#define VIP_SC_MP_SC24 0x0360
> > +#define VIP_ORG_H_MASK 0x07ff
> > +#define VIP_ORG_H_SHFT 0
> > +#define VIP_ORG_W_MASK 0x07ff
> > +#define VIP_ORG_W_SHFT 16
> > +
> > +#define VIP_SC_MP_SC25 0x0364
> > +#define VIP_OFF_H_MASK 0x07ff
> > +#define VIP_OFF_H_SHFT 0
> > +#define VIP_OFF_W_MASK 0x07ff
> > +#define VIP_OFF_W_SHFT 16
> > +
> > +#define VIP_VPDMA_REG_OFFSET 0xd000
> > +
> > +#endif
> >
>
> Regards,
>
> Hans
Regards,
Benoit
^ permalink raw reply
* [PATCH v3 03/12] dt-bindings: i2c: Discard i2c-slave flag from the DW I2C example
From: Serge Semin @ 2020-05-26 21:55 UTC (permalink / raw)
To: Jarkko Nikula, Wolfram Sang, Rob Herring
Cc: Serge Semin, Serge Semin, Alexey Malahov, Thomas Bogendoerfer,
Andy Shevchenko, Mika Westerberg, linux-mips, linux-i2c,
devicetree, linux-kernel
In-Reply-To: <20200526215528.16417-1-Sergey.Semin@baikalelectronics.ru>
dtc currently doesn't support I2C_OWN_SLAVE_ADDRESS flag set in the
i2c "reg" property. If it is the compiler will print a warning:
Warning (i2c_bus_reg): /example-2/i2c@1120000/eeprom@64: I2C bus unit address format error, expected "40000064"
Warning (i2c_bus_reg): /example-2/i2c@1120000/eeprom@64:reg: I2C address must be less than 10-bits, got "0x40000064"
In order to silence dtc up let's discard the flag from the DW I2C DT
binding example for now. Just revert this commit when dtc is fixed.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: linux-mips@vger.kernel.org
---
Changelog v3:
- This is a new patch created as a result of the Rob request to remove
the EEPROM-slave bit setting in the DT binndings example until the dtc
is fixed.
---
Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
index 4bd430b2b41d..101d78e8f19d 100644
--- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
@@ -137,7 +137,7 @@ examples:
eeprom@64 {
compatible = "linux,slave-24c02";
- reg = <0x40000064>;
+ reg = <0x64>;
};
};
- |
--
2.26.2
^ permalink raw reply related
* [PATCH v3 04/12] dt-bindings: i2c: dw: Add Baikal-T1 SoC I2C controller
From: Serge Semin @ 2020-05-26 21:55 UTC (permalink / raw)
To: Jarkko Nikula, Wolfram Sang, Rob Herring
Cc: Serge Semin, Serge Semin, Alexey Malahov, Thomas Bogendoerfer,
Andy Shevchenko, Mika Westerberg, linux-mips, linux-i2c,
devicetree, linux-kernel
In-Reply-To: <20200526215528.16417-1-Sergey.Semin@baikalelectronics.ru>
Add the "baikal,bt1-sys-i2c" compatible string to the DW I2C binding. Even
though the corresponding node is supposed to be a child of the Baikal-T1
System Controller, its reg property is left required for compatibility.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: linux-mips@vger.kernel.org
---
Changelog v2:
- Make the reg property being optional if it's Baikal-T1 System I2C DT
node.
Changelog v3:
- Get back the reg property being mandatory even if it's Baikal-T1 System
I2C DT node. Rob says it has to be in the DT node if there is a
dedicated registers range in the System Controller registers space.
---
Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
index 101d78e8f19d..8c9b3db1b1b8 100644
--- a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
@@ -31,6 +31,8 @@ properties:
items:
- const: mscc,ocelot-i2c
- const: snps,designware-i2c
+ - description: Baikal-T1 SoC System I2C controller
+ const: baikal,bt1-sys-i2c
reg:
minItems: 1
--
2.26.2
^ permalink raw reply related
* [PATCH v3 05/12] i2c: designware: Use `-y` to build multi-object modules
From: Serge Semin @ 2020-05-26 21:55 UTC (permalink / raw)
To: Jarkko Nikula, Wolfram Sang
Cc: Serge Semin, Serge Semin, Alexey Malahov, Thomas Bogendoerfer,
Andy Shevchenko, Mika Westerberg, Rob Herring, linux-mips,
devicetree, linux-i2c, linux-kernel
In-Reply-To: <20200526215528.16417-1-Sergey.Semin@baikalelectronics.ru>
Since commit 4f8272802739 ("Documentation: update kbuild loadable modules
goals & examples") `-objs` is fitted for building host programs, lets
change DW I2C core, platform and PCI driver kbuild directives to using
`-y`, which more straightforward for device drivers. By doing so we can
discard the ifeq construction in favor to the more natural and less bulky
`<module>-$(CONFIG_X) += x.o`
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
drivers/i2c/busses/Makefile | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 25d60889713c..c6813d7b2780 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -48,16 +48,15 @@ obj-$(CONFIG_I2C_CADENCE) += i2c-cadence.o
obj-$(CONFIG_I2C_CBUS_GPIO) += i2c-cbus-gpio.o
obj-$(CONFIG_I2C_CPM) += i2c-cpm.o
obj-$(CONFIG_I2C_DAVINCI) += i2c-davinci.o
-obj-$(CONFIG_I2C_DESIGNWARE_CORE) += i2c-designware-core.o
-i2c-designware-core-objs := i2c-designware-common.o i2c-designware-master.o
-ifeq ($(CONFIG_I2C_DESIGNWARE_SLAVE),y)
-i2c-designware-core-objs += i2c-designware-slave.o
-endif
-obj-$(CONFIG_I2C_DESIGNWARE_PLATFORM) += i2c-designware-platform.o
-i2c-designware-platform-objs := i2c-designware-platdrv.o
+obj-$(CONFIG_I2C_DESIGNWARE_CORE) += i2c-designware-core.o
+i2c-designware-core-y := i2c-designware-common.o
+i2c-designware-core-y += i2c-designware-master.o
+i2c-designware-core-$(CONFIG_I2C_DESIGNWARE_SLAVE) += i2c-designware-slave.o
+obj-$(CONFIG_I2C_DESIGNWARE_PLATFORM) += i2c-designware-platform.o
+i2c-designware-platform-y := i2c-designware-platdrv.o
i2c-designware-platform-$(CONFIG_I2C_DESIGNWARE_BAYTRAIL) += i2c-designware-baytrail.o
-obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o
-i2c-designware-pci-objs := i2c-designware-pcidrv.o
+obj-$(CONFIG_I2C_DESIGNWARE_PCI) += i2c-designware-pci.o
+i2c-designware-pci-y := i2c-designware-pcidrv.o
obj-$(CONFIG_I2C_DIGICOLOR) += i2c-digicolor.o
obj-$(CONFIG_I2C_EFM32) += i2c-efm32.o
obj-$(CONFIG_I2C_EG20T) += i2c-eg20t.o
--
2.26.2
^ permalink raw reply related
* [PATCH v3 02/12] dt-bindings: i2c: Convert DW I2C binding to DT schema
From: Serge Semin @ 2020-05-26 21:55 UTC (permalink / raw)
To: Jarkko Nikula, Wolfram Sang, Rob Herring
Cc: Serge Semin, Serge Semin, Alexey Malahov, Thomas Bogendoerfer,
Andy Shevchenko, Mika Westerberg, linux-mips, linux-i2c,
devicetree, linux-kernel
In-Reply-To: <20200526215528.16417-1-Sergey.Semin@baikalelectronics.ru>
Modern device tree bindings are supposed to be created as YAML-files
in accordance with dt-schema. This commit replaces Synopsys DW I2C
legacy bare text bindings with YAML file. As before the bindings file
states that the corresponding dts node is supposed to be compatible
either with generic DW I2C controller or with Microsemi Ocelot SoC I2C
one, to have registers, interrupts and clocks properties. In addition
the node may have clock-frequency, i2c-sda-hold-time-ns,
i2c-scl-falling-time-ns and i2c-sda-falling-time-ns optional properties.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: linux-mips@vger.kernel.org
---
Changelog v2:
- Make sure that "mscc,ocelot-i2c" compatible node may have up to two
registers space defined, while normal DW I2C controller will have only
one registers space.
- Add "mscc,ocelot-i2c" example to test the previous fix.
- Declare "unevaluatedProperties" property instead of
"additionalProperties" one.
- Due to the previous fix we can now discard the dummy boolean properties
definitions, since the proper type evaluation will be performed by the
generic i2c-controller.yaml schema.
Changelog v3:
- Discard $ref from the "-ns" suffixed properties since they've got the
uint32-array type by default applied in the common schema. Set "maxItems: 1"
there instead to make sure the property will have a single value specified.
---
.../bindings/i2c/i2c-designware.txt | 73 ---------
.../bindings/i2c/snps,designware-i2c.yaml | 154 ++++++++++++++++++
2 files changed, 154 insertions(+), 73 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/i2c/i2c-designware.txt
create mode 100644 Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
diff --git a/Documentation/devicetree/bindings/i2c/i2c-designware.txt b/Documentation/devicetree/bindings/i2c/i2c-designware.txt
deleted file mode 100644
index 08be4d3846e5..000000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-designware.txt
+++ /dev/null
@@ -1,73 +0,0 @@
-* Synopsys DesignWare I2C
-
-Required properties :
-
- - compatible : should be "snps,designware-i2c"
- or "mscc,ocelot-i2c" with "snps,designware-i2c" for fallback
- - reg : Offset and length of the register set for the device
- - interrupts : <IRQ> where IRQ is the interrupt number.
- - clocks : phandles for the clocks, see the description of clock-names below.
- The phandle for the "ic_clk" clock is required. The phandle for the "pclk"
- clock is optional. If a single clock is specified but no clock-name, it is
- the "ic_clk" clock. If both clocks are listed, the "ic_clk" must be first.
-
-Recommended properties :
-
- - clock-frequency : desired I2C bus clock frequency in Hz.
-
-Optional properties :
-
- - clock-names : Contains the names of the clocks:
- "ic_clk", for the core clock used to generate the external I2C clock.
- "pclk", the interface clock, required for register access.
-
- - reg : for "mscc,ocelot-i2c", a second register set to configure the SDA hold
- time, named ICPU_CFG:TWI_DELAY in the datasheet.
-
- - i2c-sda-hold-time-ns : should contain the SDA hold time in nanoseconds.
- This option is only supported in hardware blocks version 1.11a or newer and
- on Microsemi SoCs ("mscc,ocelot-i2c" compatible).
-
- - i2c-scl-falling-time-ns : should contain the SCL falling time in nanoseconds.
- This value which is by default 300ns is used to compute the tLOW period.
-
- - i2c-sda-falling-time-ns : should contain the SDA falling time in nanoseconds.
- This value which is by default 300ns is used to compute the tHIGH period.
-
-Examples :
-
- i2c@f0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0xf0000 0x1000>;
- interrupts = <11>;
- clock-frequency = <400000>;
- };
-
- i2c@1120000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0x1120000 0x1000>;
- interrupt-parent = <&ictl>;
- interrupts = <12 1>;
- clock-frequency = <400000>;
- i2c-sda-hold-time-ns = <300>;
- i2c-sda-falling-time-ns = <300>;
- i2c-scl-falling-time-ns = <300>;
- };
-
- i2c@1120000 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x2000 0x100>;
- clock-frequency = <400000>;
- clocks = <&i2cclk>;
- interrupts = <0>;
-
- eeprom@64 {
- compatible = "linux,slave-24c02";
- reg = <0x40000064>;
- };
- };
diff --git a/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
new file mode 100644
index 000000000000..4bd430b2b41d
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml
@@ -0,0 +1,154 @@
+# SPDX-License-Identifier: GPL-2.0-only
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare APB I2C Controller
+
+maintainers:
+ - Jarkko Nikula <jarkko.nikula@linux.intel.com>
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ not:
+ contains:
+ const: mscc,ocelot-i2c
+ then:
+ properties:
+ reg:
+ maxItems: 1
+
+properties:
+ compatible:
+ oneOf:
+ - description: Generic Synopsys DesignWare I2C controller
+ const: snps,designware-i2c
+ - description: Microsemi Ocelot SoCs I2C controller
+ items:
+ - const: mscc,ocelot-i2c
+ - const: snps,designware-i2c
+
+ reg:
+ minItems: 1
+ items:
+ - description: DW APB I2C controller memory mapped registers
+ - description: |
+ ICPU_CFG:TWI_DELAY registers to setup the SDA hold time.
+ This registers are specific to the Ocelot I2C-controller.
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ items:
+ - description: I2C controller reference clock source
+ - description: APB interface clock source
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: ref
+ - const: pclk
+
+ resets:
+ maxItems: 1
+
+ clock-frequency:
+ description: Desired I2C bus clock frequency in Hz
+ enum: [100000, 400000, 1000000, 3400000]
+ default: 400000
+
+ i2c-sda-hold-time-ns:
+ maxItems: 1
+ description: |
+ The property should contain the SDA hold time in nanoseconds. This option
+ is only supported in hardware blocks version 1.11a or newer or on
+ Microsemi SoCs.
+
+ i2c-scl-falling-time-ns:
+ maxItems: 1
+ description: |
+ The property should contain the SCL falling time in nanoseconds.
+ This value is used to compute the tLOW period.
+ default: 300
+
+ i2c-sda-falling-time-ns:
+ maxItems: 1
+ description: |
+ The property should contain the SDA falling time in nanoseconds.
+ This value is used to compute the tHIGH period.
+ default: 300
+
+ dmas:
+ items:
+ - description: TX DMA Channel
+ - description: RX DMA Channel
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+
+unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - interrupts
+
+examples:
+ - |
+ i2c@f0000 {
+ compatible = "snps,designware-i2c";
+ reg = <0xf0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <11>;
+ clock-frequency = <400000>;
+ };
+ - |
+ i2c@1120000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x1120000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <12 1>;
+ clock-frequency = <400000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <300>;
+ i2c-scl-falling-time-ns = <300>;
+ };
+ - |
+ i2c@2000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x2000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <400000>;
+ clocks = <&i2cclk>;
+ interrupts = <0>;
+
+ eeprom@64 {
+ compatible = "linux,slave-24c02";
+ reg = <0x40000064>;
+ };
+ };
+ - |
+ i2c@100400 {
+ compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
+ reg = <0x100400 0x100>, <0x198 0x8>;
+ pinctrl-0 = <&i2c_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <8>;
+ clocks = <&ahb_clk>;
+ };
+...
--
2.26.2
^ permalink raw reply related
* [PATCH v3 07/12] i2c: designware: Add Baytrail sem config DW I2C platform dependency
From: Serge Semin @ 2020-05-26 21:55 UTC (permalink / raw)
To: Jarkko Nikula, Wolfram Sang
Cc: Serge Semin, Serge Semin, Alexey Malahov, Thomas Bogendoerfer,
Andy Shevchenko, Mika Westerberg, Rob Herring, linux-mips,
devicetree, linux-i2c, linux-kernel
In-Reply-To: <20200526215528.16417-1-Sergey.Semin@baikalelectronics.ru>
Currently Intel Baytrail I2C semaphore is a feature of the DW APB I2C
platform driver. It's a bit confusing to see it's config in the menu at
some separated place with no reference to the platform code. Let's move the
config definition to be below the I2C_DESIGNWARE_PLATFORM config and mark
it with "depends on I2C_DESIGNWARE_PLATFORM" statement. By doing so the
config menu will display the feature right below the DW I2C platform
driver item and will indent it to the right so signifying its belonging.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
Changelog v3:
- Replace if-endif clause around the I2C_DESIGNWARE_BAYTRAIL config
with "depends on" operator.
---
drivers/i2c/busses/Kconfig | 25 +++++++++++++------------
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index b907d4046942..4e1997642e73 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -538,6 +538,19 @@ config I2C_DESIGNWARE_PLATFORM
This driver can also be built as a module. If so, the module
will be called i2c-designware-platform.
+config I2C_DESIGNWARE_BAYTRAIL
+ bool "Intel Baytrail I2C semaphore support"
+ depends on ACPI
+ depends on I2C_DESIGNWARE_PLATFORM
+ depends on (I2C_DESIGNWARE_PLATFORM=m && IOSF_MBI) || \
+ (I2C_DESIGNWARE_PLATFORM=y && IOSF_MBI=y)
+ help
+ This driver enables managed host access to the PMIC I2C bus on select
+ Intel BayTrail platforms using the X-Powers AXP288 PMIC. It allows
+ the host to request uninterrupted access to the PMIC's I2C bus from
+ the platform firmware controlling it. You should say Y if running on
+ a BayTrail system using the AXP288.
+
config I2C_DESIGNWARE_SLAVE
bool "Synopsys DesignWare Slave"
depends on I2C_DESIGNWARE_CORE
@@ -560,18 +573,6 @@ config I2C_DESIGNWARE_PCI
This driver can also be built as a module. If so, the module
will be called i2c-designware-pci.
-config I2C_DESIGNWARE_BAYTRAIL
- bool "Intel Baytrail I2C semaphore support"
- depends on ACPI
- depends on (I2C_DESIGNWARE_PLATFORM=m && IOSF_MBI) || \
- (I2C_DESIGNWARE_PLATFORM=y && IOSF_MBI=y)
- help
- This driver enables managed host access to the PMIC I2C bus on select
- Intel BayTrail platforms using the X-Powers AXP288 PMIC. It allows
- the host to request uninterrupted access to the PMIC's I2C bus from
- the platform firmware controlling it. You should say Y if running on
- a BayTrail system using the AXP288.
-
config I2C_DIGICOLOR
tristate "Conexant Digicolor I2C driver"
depends on ARCH_DIGICOLOR || COMPILE_TEST
--
2.26.2
^ permalink raw reply related
* [PATCH v3 08/12] i2c: designware: Discard Cherry Trail model flag
From: Serge Semin @ 2020-05-26 21:55 UTC (permalink / raw)
To: Jarkko Nikula, Wolfram Sang, Andy Shevchenko, Mika Westerberg
Cc: Serge Semin, Serge Semin, Alexey Malahov, Thomas Bogendoerfer,
Rob Herring, linux-mips, devicetree, linux-i2c, linux-kernel
In-Reply-To: <20200526215528.16417-1-Sergey.Semin@baikalelectronics.ru>
A PM workaround activated by the flag MODEL_CHERRYTRAIL has been removed
since commit 9cbeeca05049 ("i2c: designware: Remove Cherry Trail PMIC I2C
bus pm_disabled workaround"), but the flag most likely by mistake has been
left in the Dw I2C drivers. Lets remove it.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Acked-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
Changelog v3:
- Since MSCC and Baikal-T1 will be a part of the platform driver code, we
have to preserve the MODEL_MASK macro to use it to filter the model
flags during the IP-specific quirks activation.
---
drivers/i2c/busses/i2c-designware-core.h | 3 +--
drivers/i2c/busses/i2c-designware-pcidrv.c | 1 -
drivers/i2c/busses/i2c-designware-platdrv.c | 2 +-
3 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
index b220ad64c38d..e036e7268d3b 100644
--- a/drivers/i2c/busses/i2c-designware-core.h
+++ b/drivers/i2c/busses/i2c-designware-core.h
@@ -281,8 +281,7 @@ struct dw_i2c_dev {
#define ACCESS_INTR_MASK 0x00000004
#define ACCESS_NO_IRQ_SUSPEND 0x00000008
-#define MODEL_CHERRYTRAIL 0x00000100
-#define MODEL_MSCC_OCELOT 0x00000200
+#define MODEL_MSCC_OCELOT 0x00000100
#define MODEL_MASK 0x00000f00
u32 dw_readl(struct dw_i2c_dev *dev, int offset);
diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c
index 7a0b65b5b5b5..76357b575aa5 100644
--- a/drivers/i2c/busses/i2c-designware-pcidrv.c
+++ b/drivers/i2c/busses/i2c-designware-pcidrv.c
@@ -166,7 +166,6 @@ static struct dw_pci_controller dw_pci_controllers[] = {
.tx_fifo_depth = 32,
.rx_fifo_depth = 32,
.functionality = I2C_FUNC_10BIT_ADDR,
- .flags = MODEL_CHERRYTRAIL,
.scl_sda_cfg = &byt_config,
},
[elkhartlake] = {
diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
index 5536673060cc..57475f19448a 100644
--- a/drivers/i2c/busses/i2c-designware-platdrv.c
+++ b/drivers/i2c/busses/i2c-designware-platdrv.c
@@ -123,7 +123,7 @@ static const struct acpi_device_id dw_i2c_acpi_match[] = {
{ "INT3432", 0 },
{ "INT3433", 0 },
{ "80860F41", ACCESS_NO_IRQ_SUSPEND },
- { "808622C1", ACCESS_NO_IRQ_SUSPEND | MODEL_CHERRYTRAIL },
+ { "808622C1", ACCESS_NO_IRQ_SUSPEND },
{ "AMD0010", ACCESS_INTR_MASK },
{ "AMDI0010", ACCESS_INTR_MASK },
{ "AMDI0510", 0 },
--
2.26.2
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