* Re: [PATCH v4 06/12] cpufreq: qcom: Update the bandwidth levels on frequency change
From: Viresh Kumar @ 2020-05-27 4:05 UTC (permalink / raw)
To: Sibi Sankar
Cc: sboyd, georgi.djakov, bjorn.andersson, saravanak, mka, nm, agross,
david.brown, robh+dt, mark.rutland, rjw, linux-arm-msm,
devicetree, linux-kernel, linux-pm, dianders, vincent.guittot,
amit.kucheria, ulf.hansson, lukasz.luba, sudeep.holla
In-Reply-To: <20200527035349.mrvvxeg3lqv53jm2@vireshk-i7>
On 27-05-20, 09:23, Viresh Kumar wrote:
> On 26-05-20, 23:18, Sibi Sankar wrote:
> > https://patchwork.kernel.org/cover/11548479/
> > GPU driver uses Georgi's series
> > for scaling and will need a way to
> > remove the icc votes in the suspend
> > path, (this looks like a pattern
> > that might be used by other clients
> > as well) I could probably update
> > opp_set_bw to support removing bw
> > when NULL opp is specified. Similarly
> > opp_set_rate will need to support
> > set bw to 0 when set_rate is passed
> > 0 as target freq for the same use case.
>
> Sure, please send a patch for that.
On a second thought, here is the patch. Please test it.
-------------------------8<-------------------------
Subject: [PATCH] opp: Remove bandwidth votes when target_freq is zero
We already drop several votes when target_freq is set to zero, drop
bandwidth votes as well.
Reported-by: Sibi Sankar <sibis@codeaurora.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
---
drivers/opp/core.c | 47 +++++++++++++++++++++++++++++++++++-----------
1 file changed, 36 insertions(+), 11 deletions(-)
diff --git a/drivers/opp/core.c b/drivers/opp/core.c
index 56d3022c1ca2..0c259d5ed232 100644
--- a/drivers/opp/core.c
+++ b/drivers/opp/core.c
@@ -725,6 +725,34 @@ static int _generic_set_opp_regulator(struct opp_table *opp_table,
return ret;
}
+static int _set_opp_bw(const struct opp_table *opp_table,
+ struct dev_pm_opp *opp, bool remove)
+{
+ u32 avg, peak;
+ int i, ret;
+
+ if (!opp_table->paths)
+ return 0;
+
+ for (i = 0; i < opp_table->path_count; i++) {
+ if (remove) {
+ avg = 0;
+ peak = 0;
+ } else {
+ avg = opp->bandwidth[i].avg;
+ peak = opp->bandwidth[i].peak;
+ }
+ ret = icc_set_bw(opp_table->paths[i], avg, peak);
+ if (ret) {
+ dev_err(dev, "Failed to %s bandwidth[%d]: %d\n",
+ remove ? "remove" : "set", i, ret);
+ retrun ret;
+ }
+ }
+
+ return 0;
+}
+
static int _set_opp_custom(const struct opp_table *opp_table,
struct device *dev, unsigned long old_freq,
unsigned long freq,
@@ -837,12 +865,17 @@ int dev_pm_opp_set_rate(struct device *dev, unsigned long target_freq)
if (!_get_opp_count(opp_table))
return 0;
- if (!opp_table->required_opp_tables && !opp_table->regulators) {
+ if (!opp_table->required_opp_tables && !opp_table->regulators &&
+ !opp_table->paths) {
dev_err(dev, "target frequency can't be 0\n");
ret = -EINVAL;
goto put_opp_table;
}
+ ret = _set_opp_bw(opp_table, opp, true);
+ if (ret)
+ return ret;
+
if (opp_table->regulator_enabled) {
regulator_disable(opp_table->regulators[0]);
opp_table->regulator_enabled = false;
@@ -932,16 +965,8 @@ int dev_pm_opp_set_rate(struct device *dev, unsigned long target_freq)
dev_err(dev, "Failed to set required opps: %d\n", ret);
}
- if (!ret && opp_table->paths) {
- for (i = 0; i < opp_table->path_count; i++) {
- ret = icc_set_bw(opp_table->paths[i],
- opp->bandwidth[i].avg,
- opp->bandwidth[i].peak);
- if (ret)
- dev_err(dev, "Failed to set bandwidth[%d]: %d\n",
- i, ret);
- }
- }
+ if (!ret)
+ ret = _set_opp_bw(opp_table, opp, false);
put_opp:
dev_pm_opp_put(opp);
^ permalink raw reply related
* Re: [PATCH v8 00/13] add ecspi ERR009165 for i.mx6/7 soc family
From: Sascha Hauer @ 2020-05-27 5:03 UTC (permalink / raw)
To: Robin Gong
Cc: mark.rutland, broonie, robh+dt, catalin.marinas, vkoul,
will.deacon, shawnguo, festevam, martin.fuzzey, u.kleine-koenig,
dan.j.williams, linux-spi, linux-kernel, devicetree,
linux-arm-kernel, kernel, linux-imx
In-Reply-To: <1590006865-20900-1-git-send-email-yibin.gong@nxp.com>
On Thu, May 21, 2020 at 04:34:12AM +0800, Robin Gong wrote:
> There is ecspi ERR009165 on i.mx6/7 soc family, which cause FIFO
> transfer to be send twice in DMA mode. Please get more information from:
> https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf. The workaround is adding
> new sdma ram script which works in XCH mode as PIO inside sdma instead
> of SMC mode, meanwhile, 'TX_THRESHOLD' should be 0. The issue should be
> exist on all legacy i.mx6/7 soc family before i.mx6ul.
> NXP fix this design issue from i.mx6ul, so newer chips including i.mx6ul/
> 6ull/6sll do not need this workaroud anymore. All other i.mx6/7/8 chips
> still need this workaroud. This patch set add new 'fsl,imx6ul-ecspi'
> for ecspi driver and 'ecspi_fixed' in sdma driver to choose if need errata
> or not.
> The first two reverted patches should be the same issue, though, it
> seems 'fixed' by changing to other shp script. Hope Sean or Sascha could
> have the chance to test this patch set if could fix their issues.
> Besides, enable sdma support for i.mx8mm/8mq and fix ecspi1 not work
> on i.mx8mm because the event id is zero.
For the series:
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH v6 2/5] remoteproc: qcom: Introduce helper to store pil info in IMEM
From: Bjorn Andersson @ 2020-05-27 5:48 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Ohad Ben-Cohen
Cc: Rob Herring, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel, Mathieu Poirier, Vinod Koul
In-Reply-To: <20200527054850.2067032-1-bjorn.andersson@linaro.org>
A region in IMEM is used to communicate load addresses of remoteproc to
post mortem debug tools. Implement a helper function that can be used to
store this information in order to enable these tools to process
collected ramdumps.
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes since v5:
- Picked up reviewed-bys
drivers/remoteproc/Kconfig | 3 +
drivers/remoteproc/Makefile | 1 +
drivers/remoteproc/qcom_pil_info.c | 124 +++++++++++++++++++++++++++++
drivers/remoteproc/qcom_pil_info.h | 7 ++
4 files changed, 135 insertions(+)
create mode 100644 drivers/remoteproc/qcom_pil_info.c
create mode 100644 drivers/remoteproc/qcom_pil_info.h
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index c4d1731295eb..f4bd96d1a1a3 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -116,6 +116,9 @@ config KEYSTONE_REMOTEPROC
It's safe to say N here if you're not interested in the Keystone
DSPs or just want to use a bare minimum kernel.
+config QCOM_PIL_INFO
+ tristate
+
config QCOM_RPROC_COMMON
tristate
diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile
index e8b886e511f0..fe398f82d550 100644
--- a/drivers/remoteproc/Makefile
+++ b/drivers/remoteproc/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_OMAP_REMOTEPROC) += omap_remoteproc.o
obj-$(CONFIG_WKUP_M3_RPROC) += wkup_m3_rproc.o
obj-$(CONFIG_DA8XX_REMOTEPROC) += da8xx_remoteproc.o
obj-$(CONFIG_KEYSTONE_REMOTEPROC) += keystone_remoteproc.o
+obj-$(CONFIG_QCOM_PIL_INFO) += qcom_pil_info.o
obj-$(CONFIG_QCOM_RPROC_COMMON) += qcom_common.o
obj-$(CONFIG_QCOM_Q6V5_COMMON) += qcom_q6v5.o
obj-$(CONFIG_QCOM_Q6V5_ADSP) += qcom_q6v5_adsp.o
diff --git a/drivers/remoteproc/qcom_pil_info.c b/drivers/remoteproc/qcom_pil_info.c
new file mode 100644
index 000000000000..0785c7cde2d3
--- /dev/null
+++ b/drivers/remoteproc/qcom_pil_info.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2019-2020 Linaro Ltd.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of_address.h>
+
+#define PIL_RELOC_NAME_LEN 8
+
+struct pil_reloc_entry {
+ char name[PIL_RELOC_NAME_LEN];
+ __le64 base;
+ __le32 size;
+} __packed;
+
+struct pil_reloc {
+ struct device *dev;
+ void __iomem *base;
+ size_t num_entries;
+};
+
+static struct pil_reloc _reloc __read_mostly;
+static DEFINE_MUTEX(reloc_mutex);
+
+static int qcom_pil_info_init(void)
+{
+ struct device_node *np;
+ struct resource imem;
+ void __iomem *base;
+ int ret;
+
+ /* Already initialized? */
+ if (_reloc.base)
+ return 0;
+
+ np = of_find_compatible_node(NULL, NULL, "qcom,pil-reloc-info");
+ if (!np)
+ return -ENOENT;
+
+ ret = of_address_to_resource(np, 0, &imem);
+ of_node_put(np);
+ if (ret < 0)
+ return ret;
+
+ base = ioremap(imem.start, resource_size(&imem));
+ if (!base) {
+ pr_err("failed to map PIL relocation info region\n");
+ return -ENOMEM;
+ }
+
+ memset_io(base, 0, resource_size(&imem));
+
+ _reloc.base = base;
+ _reloc.num_entries = resource_size(&imem) / sizeof(struct pil_reloc_entry);
+
+ return 0;
+}
+
+/**
+ * qcom_pil_info_store() - store PIL information of image in IMEM
+ * @image: name of the image
+ * @base: base address of the loaded image
+ * @size: size of the loaded image
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int qcom_pil_info_store(const char *image, phys_addr_t base, size_t size)
+{
+ char buf[PIL_RELOC_NAME_LEN];
+ void __iomem *entry;
+ int ret;
+ int i;
+
+ mutex_lock(&reloc_mutex);
+ ret = qcom_pil_info_init();
+ if (ret < 0) {
+ mutex_unlock(&reloc_mutex);
+ return ret;
+ }
+
+ for (i = 0; i < _reloc.num_entries; i++) {
+ entry = _reloc.base + i * sizeof(struct pil_reloc_entry);
+
+ memcpy_fromio(buf, entry, PIL_RELOC_NAME_LEN);
+
+ /*
+ * An empty record means we didn't find it, given that the
+ * records are packed.
+ */
+ if (!buf[0])
+ goto found_unused;
+
+ if (!strncmp(buf, image, PIL_RELOC_NAME_LEN))
+ goto found_existing;
+ }
+
+ pr_warn("insufficient PIL info slots\n");
+ mutex_unlock(&reloc_mutex);
+ return -ENOMEM;
+
+found_unused:
+ memcpy_toio(entry, image, PIL_RELOC_NAME_LEN);
+found_existing:
+ writel(base, entry + offsetof(struct pil_reloc_entry, base));
+ writel(size, entry + offsetof(struct pil_reloc_entry, size));
+ mutex_unlock(&reloc_mutex);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(qcom_pil_info_store);
+
+static void __exit pil_reloc_exit(void)
+{
+ mutex_lock(&reloc_mutex);
+ iounmap(_reloc.base);
+ _reloc.base = NULL;
+ mutex_unlock(&reloc_mutex);
+}
+module_exit(pil_reloc_exit);
+
+MODULE_DESCRIPTION("Qualcomm PIL relocation info");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/remoteproc/qcom_pil_info.h b/drivers/remoteproc/qcom_pil_info.h
new file mode 100644
index 000000000000..1b89a63ba82f
--- /dev/null
+++ b/drivers/remoteproc/qcom_pil_info.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __QCOM_PIL_INFO_H__
+#define __QCOM_PIL_INFO_H__
+
+int qcom_pil_info_store(const char *image, phys_addr_t base, size_t size);
+
+#endif
--
2.26.2
^ permalink raw reply related
* [PATCH v6 5/5] arm64: dts: qcom: sdm845: Add IMEM and PIL info region
From: Bjorn Andersson @ 2020-05-27 5:48 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Ohad Ben-Cohen
Cc: Rob Herring, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel, Stephen Boyd, Vinod Koul
In-Reply-To: <20200527054850.2067032-1-bjorn.andersson@linaro.org>
Add a simple-mfd representing IMEM on SDM845 and define the PIL
relocation info region, so that post mortem tools will be able to locate
the loaded remoteprocs.
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes since v5:
- Picked up reviewed-bys
arch/arm64/boot/dts/qcom/sdm845.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 8eb5a31346d2..fee50d979dc3 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -3724,6 +3724,21 @@ spmi_bus: spmi@c440000 {
cell-index = <0>;
};
+ imem@146bf000 {
+ compatible = "simple-mfd";
+ reg = <0 0x146bf000 0 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0 0x146bf000 0x1000>;
+
+ pil-reloc@94c {
+ compatible = "qcom,pil-reloc-info";
+ reg = <0x94c 0xc8>;
+ };
+ };
+
apps_smmu: iommu@15000000 {
compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
reg = <0 0x15000000 0 0x80000>;
--
2.26.2
^ permalink raw reply related
* [PATCH v6 4/5] arm64: dts: qcom: qcs404: Add IMEM and PIL info region
From: Bjorn Andersson @ 2020-05-27 5:48 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Ohad Ben-Cohen
Cc: Rob Herring, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel, Stephen Boyd, Vinod Koul
In-Reply-To: <20200527054850.2067032-1-bjorn.andersson@linaro.org>
Add a simple-mfd representing IMEM on QCS404 and define the PIL
relocation info region, so that post mortem tools will be able to locate
the loaded remoteprocs.
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes since v5:
- Picked up reviewed-bys
arch/arm64/boot/dts/qcom/qcs404.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index c685a1664810..b654b802e95c 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -1097,6 +1097,21 @@ blsp2_spi0: spi@7af5000 {
status = "disabled";
};
+ imem@8600000 {
+ compatible = "simple-mfd";
+ reg = <0x08600000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0x08600000 0x1000>;
+
+ pil-reloc@94c {
+ compatible = "qcom,pil-reloc-info";
+ reg = <0x94c 0xc8>;
+ };
+ };
+
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
--
2.26.2
^ permalink raw reply related
* [PATCH v6 3/5] remoteproc: qcom: Update PIL relocation info on load
From: Bjorn Andersson @ 2020-05-27 5:48 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Ohad Ben-Cohen
Cc: Rob Herring, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel, Vinod Koul
In-Reply-To: <20200527054850.2067032-1-bjorn.andersson@linaro.org>
Update the PIL relocation information in IMEM with information about
where the firmware for various remoteprocs are loaded.
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes since v5:
- Added select QCOM_PIL_INFO to all relevant Kconfig options
- Replaced mem_reloc with mem_phys, to get the start of the memory region,
rather than the bottom address prior to relocation.
- Include qcom_pil_info.h in qcom_q6v5_wcss.c
drivers/remoteproc/Kconfig | 5 +++++
drivers/remoteproc/qcom_q6v5_adsp.c | 16 +++++++++++++---
drivers/remoteproc/qcom_q6v5_mss.c | 3 +++
drivers/remoteproc/qcom_q6v5_pas.c | 15 ++++++++++++---
drivers/remoteproc/qcom_q6v5_wcss.c | 14 +++++++++++---
drivers/remoteproc/qcom_wcnss.c | 14 +++++++++++---
6 files changed, 55 insertions(+), 12 deletions(-)
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index f4bd96d1a1a3..3e8d5d1a2b9e 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -135,6 +135,7 @@ config QCOM_Q6V5_ADSP
depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
depends on QCOM_SYSMON || QCOM_SYSMON=n
select MFD_SYSCON
+ select QCOM_PIL_INFO
select QCOM_MDT_LOADER
select QCOM_Q6V5_COMMON
select QCOM_RPROC_COMMON
@@ -151,6 +152,7 @@ config QCOM_Q6V5_MSS
depends on QCOM_SYSMON || QCOM_SYSMON=n
select MFD_SYSCON
select QCOM_MDT_LOADER
+ select QCOM_PIL_INFO
select QCOM_Q6V5_COMMON
select QCOM_Q6V5_IPA_NOTIFY
select QCOM_RPROC_COMMON
@@ -167,6 +169,7 @@ config QCOM_Q6V5_PAS
depends on RPMSG_QCOM_GLINK_SMEM || RPMSG_QCOM_GLINK_SMEM=n
depends on QCOM_SYSMON || QCOM_SYSMON=n
select MFD_SYSCON
+ select QCOM_PIL_INFO
select QCOM_MDT_LOADER
select QCOM_Q6V5_COMMON
select QCOM_RPROC_COMMON
@@ -185,6 +188,7 @@ config QCOM_Q6V5_WCSS
depends on QCOM_SYSMON || QCOM_SYSMON=n
select MFD_SYSCON
select QCOM_MDT_LOADER
+ select QCOM_PIL_INFO
select QCOM_Q6V5_COMMON
select QCOM_RPROC_COMMON
select QCOM_SCM
@@ -218,6 +222,7 @@ config QCOM_WCNSS_PIL
depends on QCOM_SMEM
depends on QCOM_SYSMON || QCOM_SYSMON=n
select QCOM_MDT_LOADER
+ select QCOM_PIL_INFO
select QCOM_RPROC_COMMON
select QCOM_SCM
help
diff --git a/drivers/remoteproc/qcom_q6v5_adsp.c b/drivers/remoteproc/qcom_q6v5_adsp.c
index d2a2574dcf35..efb2c1aa80a3 100644
--- a/drivers/remoteproc/qcom_q6v5_adsp.c
+++ b/drivers/remoteproc/qcom_q6v5_adsp.c
@@ -26,6 +26,7 @@
#include <linux/soc/qcom/smem_state.h>
#include "qcom_common.h"
+#include "qcom_pil_info.h"
#include "qcom_q6v5.h"
#include "remoteproc_internal.h"
@@ -82,6 +83,7 @@ struct qcom_adsp {
unsigned int halt_lpass;
int crash_reason_smem;
+ const char *info_name;
struct completion start_done;
struct completion stop_done;
@@ -164,10 +166,17 @@ static int qcom_adsp_shutdown(struct qcom_adsp *adsp)
static int adsp_load(struct rproc *rproc, const struct firmware *fw)
{
struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
+ int ret;
+
+ ret = qcom_mdt_load_no_init(adsp->dev, fw, rproc->firmware, 0,
+ adsp->mem_region, adsp->mem_phys,
+ adsp->mem_size, &adsp->mem_reloc);
+ if (ret)
+ return ret;
+
+ qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size);
- return qcom_mdt_load_no_init(adsp->dev, fw, rproc->firmware, 0,
- adsp->mem_region, adsp->mem_phys, adsp->mem_size,
- &adsp->mem_reloc);
+ return 0;
}
static int adsp_start(struct rproc *rproc)
@@ -436,6 +445,7 @@ static int adsp_probe(struct platform_device *pdev)
adsp = (struct qcom_adsp *)rproc->priv;
adsp->dev = &pdev->dev;
adsp->rproc = rproc;
+ adsp->info_name = desc->sysmon_name;
platform_set_drvdata(pdev, adsp);
ret = adsp_alloc_memory_region(adsp);
diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q6v5_mss.c
index feb70283b6a2..dd37e462ed61 100644
--- a/drivers/remoteproc/qcom_q6v5_mss.c
+++ b/drivers/remoteproc/qcom_q6v5_mss.c
@@ -29,6 +29,7 @@
#include "remoteproc_internal.h"
#include "qcom_common.h"
+#include "qcom_pil_info.h"
#include "qcom_q6v5.h"
#include <linux/qcom_scm.h>
@@ -1189,6 +1190,8 @@ static int q6v5_mpss_load(struct q6v5 *qproc)
else if (ret < 0)
dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
+ qcom_pil_info_store("modem", qproc->mpss_phys, qproc->mpss_size);
+
release_firmware:
release_firmware(fw);
out:
diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c
index 61791a03f648..3837f23995e0 100644
--- a/drivers/remoteproc/qcom_q6v5_pas.c
+++ b/drivers/remoteproc/qcom_q6v5_pas.c
@@ -25,6 +25,7 @@
#include <linux/soc/qcom/smem_state.h>
#include "qcom_common.h"
+#include "qcom_pil_info.h"
#include "qcom_q6v5.h"
#include "remoteproc_internal.h"
@@ -64,6 +65,7 @@ struct qcom_adsp {
int pas_id;
int crash_reason_smem;
bool has_aggre2_clk;
+ const char *info_name;
struct completion start_done;
struct completion stop_done;
@@ -117,11 +119,17 @@ static void adsp_pds_disable(struct qcom_adsp *adsp, struct device **pds,
static int adsp_load(struct rproc *rproc, const struct firmware *fw)
{
struct qcom_adsp *adsp = (struct qcom_adsp *)rproc->priv;
+ int ret;
- return qcom_mdt_load(adsp->dev, fw, rproc->firmware, adsp->pas_id,
- adsp->mem_region, adsp->mem_phys, adsp->mem_size,
- &adsp->mem_reloc);
+ ret = qcom_mdt_load(adsp->dev, fw, rproc->firmware, adsp->pas_id,
+ adsp->mem_region, adsp->mem_phys, adsp->mem_size,
+ &adsp->mem_reloc);
+ if (ret)
+ return ret;
+ qcom_pil_info_store(adsp->info_name, adsp->mem_phys, adsp->mem_size);
+
+ return 0;
}
static int adsp_start(struct rproc *rproc)
@@ -405,6 +413,7 @@ static int adsp_probe(struct platform_device *pdev)
adsp->rproc = rproc;
adsp->pas_id = desc->pas_id;
adsp->has_aggre2_clk = desc->has_aggre2_clk;
+ adsp->info_name = desc->sysmon_name;
platform_set_drvdata(pdev, adsp);
device_wakeup_enable(adsp->dev);
diff --git a/drivers/remoteproc/qcom_q6v5_wcss.c b/drivers/remoteproc/qcom_q6v5_wcss.c
index 88c76b9417fa..8846ef0b0f1a 100644
--- a/drivers/remoteproc/qcom_q6v5_wcss.c
+++ b/drivers/remoteproc/qcom_q6v5_wcss.c
@@ -14,6 +14,7 @@
#include <linux/reset.h>
#include <linux/soc/qcom/mdt_loader.h>
#include "qcom_common.h"
+#include "qcom_pil_info.h"
#include "qcom_q6v5.h"
#define WCSS_CRASH_REASON 421
@@ -424,10 +425,17 @@ static void *q6v5_wcss_da_to_va(struct rproc *rproc, u64 da, size_t len)
static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw)
{
struct q6v5_wcss *wcss = rproc->priv;
+ int ret;
+
+ ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
+ 0, wcss->mem_region, wcss->mem_phys,
+ wcss->mem_size, &wcss->mem_reloc);
+ if (ret)
+ return ret;
+
+ qcom_pil_info_store("wcnss", wcss->mem_phys, wcss->mem_size);
- return qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware,
- 0, wcss->mem_region, wcss->mem_phys,
- wcss->mem_size, &wcss->mem_reloc);
+ return ret;
}
static const struct rproc_ops q6v5_wcss_ops = {
diff --git a/drivers/remoteproc/qcom_wcnss.c b/drivers/remoteproc/qcom_wcnss.c
index 5d65e1a9329a..e2573f79a137 100644
--- a/drivers/remoteproc/qcom_wcnss.c
+++ b/drivers/remoteproc/qcom_wcnss.c
@@ -27,6 +27,7 @@
#include "qcom_common.h"
#include "remoteproc_internal.h"
+#include "qcom_pil_info.h"
#include "qcom_wcnss.h"
#define WCNSS_CRASH_REASON_SMEM 422
@@ -145,10 +146,17 @@ void qcom_wcnss_assign_iris(struct qcom_wcnss *wcnss,
static int wcnss_load(struct rproc *rproc, const struct firmware *fw)
{
struct qcom_wcnss *wcnss = (struct qcom_wcnss *)rproc->priv;
+ int ret;
+
+ ret = qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID,
+ wcnss->mem_region, wcnss->mem_phys,
+ wcnss->mem_size, &wcnss->mem_reloc);
+ if (ret)
+ return ret;
+
+ qcom_pil_info_store("wcnss", wcnss->mem_phys, wcnss->mem_size);
- return qcom_mdt_load(wcnss->dev, fw, rproc->firmware, WCNSS_PAS_ID,
- wcnss->mem_region, wcnss->mem_phys,
- wcnss->mem_size, &wcnss->mem_reloc);
+ return 0;
}
static void wcnss_indicate_nv_download(struct qcom_wcnss *wcnss)
--
2.26.2
^ permalink raw reply related
* [PATCH v6 0/5] remoteproc: qcom: PIL info support
From: Bjorn Andersson @ 2020-05-27 5:48 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Ohad Ben-Cohen
Cc: Rob Herring, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel
Introduce support for filling out the relocation information in IMEM, to aid
post mortem debug tools to locate the various remoteprocs.
Bjorn Andersson (5):
dt-bindings: remoteproc: Add Qualcomm PIL info binding
remoteproc: qcom: Introduce helper to store pil info in IMEM
remoteproc: qcom: Update PIL relocation info on load
arm64: dts: qcom: qcs404: Add IMEM and PIL info region
arm64: dts: qcom: sdm845: Add IMEM and PIL info region
.../bindings/remoteproc/qcom,pil-info.yaml | 44 +++++++
arch/arm64/boot/dts/qcom/qcs404.dtsi | 15 +++
arch/arm64/boot/dts/qcom/sdm845.dtsi | 15 +++
drivers/remoteproc/Kconfig | 8 ++
drivers/remoteproc/Makefile | 1 +
drivers/remoteproc/qcom_pil_info.c | 124 ++++++++++++++++++
drivers/remoteproc/qcom_pil_info.h | 7 +
drivers/remoteproc/qcom_q6v5_adsp.c | 16 ++-
drivers/remoteproc/qcom_q6v5_mss.c | 3 +
drivers/remoteproc/qcom_q6v5_pas.c | 15 ++-
drivers/remoteproc/qcom_q6v5_wcss.c | 14 +-
drivers/remoteproc/qcom_wcnss.c | 14 +-
12 files changed, 264 insertions(+), 12 deletions(-)
create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,pil-info.yaml
create mode 100644 drivers/remoteproc/qcom_pil_info.c
create mode 100644 drivers/remoteproc/qcom_pil_info.h
--
2.26.2
^ permalink raw reply
* [PATCH v6 1/5] dt-bindings: remoteproc: Add Qualcomm PIL info binding
From: Bjorn Andersson @ 2020-05-27 5:48 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Ohad Ben-Cohen
Cc: Rob Herring, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel, Mathieu Poirier, Rob Herring, Stephen Boyd,
Vinod Koul
In-Reply-To: <20200527054850.2067032-1-bjorn.andersson@linaro.org>
Add a devicetree binding for the Qualcomm peripheral image loader
relocation information region found in the IMEM.
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
Changes since v5:
- Picked up reviewed-bys
.../bindings/remoteproc/qcom,pil-info.yaml | 44 +++++++++++++++++++
1 file changed, 44 insertions(+)
create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,pil-info.yaml
diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,pil-info.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,pil-info.yaml
new file mode 100644
index 000000000000..87c52316ddbd
--- /dev/null
+++ b/Documentation/devicetree/bindings/remoteproc/qcom,pil-info.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/remoteproc/qcom,pil-info.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm peripheral image loader relocation info binding
+
+maintainers:
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+
+description:
+ The Qualcomm peripheral image loader relocation memory region, in IMEM, is
+ used for communicating remoteproc relocation information to post mortem
+ debugging tools.
+
+properties:
+ compatible:
+ const: qcom,pil-reloc-info
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+examples:
+ - |
+ imem@146bf000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x146bf000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ranges = <0 0x146bf000 0x1000>;
+
+ pil-reloc@94c {
+ compatible = "qcom,pil-reloc-info";
+ reg = <0x94c 0xc8>;
+ };
+ };
+...
--
2.26.2
^ permalink raw reply related
* Re: [PATCH v8 4/6] dt-bindings: MIPS: Document Ingenic SoCs binding.
From: Zhou Yanjie @ 2020-05-27 5:59 UTC (permalink / raw)
To: Rob Herring
Cc: linux-mips, linux-kernel, devicetree, tsbogend, paulburton,
jiaxun.yang, chenhc, tglx, daniel.lezcano, keescook, paul, krzk,
hns, ebiederm, dongsheng.qiu, yanfei.li, rick.tyliu, sernia.zhou,
zhenwenjin, aric.pzqi
In-Reply-To: <20200526192947.GA140311@bogus>
在 2020/5/27 上午3:29, Rob Herring 写道:
> On Tue, May 19, 2020 at 10:35:21PM +0800, 周琰杰 (Zhou Yanjie) wrote:
>> Document the available properties for the SoC root node and the
>> CPU nodes of the devicetree for the Ingenic XBurst SoCs.
>>
>> Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
>> Tested-by: Paul Boddie <paul@boddie.org.uk>
>> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
>> ---
>>
>> Notes:
>> v1->v2:
>> Change the two Document from txt to yaml.
>>
>> v2->v3:
>> Fix formatting errors.
>>
>> v3->v4:
>> Fix bugs in the two yaml files.
>>
>> v4->v5:
>> No change.
>>
>> v5->v6:
>> Rewrite the two yaml files.
>>
>> v6->v7:
>> 1.Update compatible strings in "ingenic,cpu.yaml".
>> 2.Fix formatting errors, and enum for compatible strings.
>> 3.Remove unnecessary "ingenic,soc.yaml".
>>
>> v7->v8:
>> No change.
>>
>> .../bindings/mips/ingenic/ingenic,cpu.yaml | 57 ++++++++++++++++++++++
>> 1 file changed, 57 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
>> new file mode 100644
>> index 00000000..afb0207
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
>> @@ -0,0 +1,57 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Bindings for Ingenic XBurst family CPUs
>> +
>> +maintainers:
>> + - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
>> +
>> +description:
>> + Ingenic XBurst family CPUs shall have the following properties.
>> +
>> +properties:
>> + compatible:
>> + oneOf:
>> +
>> + - description: Ingenic XBurst®1 CPU Cores
>> + items:
> This is a single compatible string, right? If so, drop items.
Sure, I'll drop it. And because the SMP driver has some other work that
can't be completed in a short time, so I will send this patch separately.
>> + enum:
>> + - ingenic,xburst-mxu1.0
>> + - ingenic,xburst-fpu1.0-mxu1.1
>> + - ingenic,xburst-fpu2.0-mxu2.0
>> +
>> + - description: Ingenic XBurst®2 CPU Cores
>> + items:
>> + enum:
>> + - ingenic,xburst2-fpu2.1-mxu2.1-smt
> Just: const: ingenic,xburst2-fpu2.1-mxu2.1-smt
>
> Continuing to append CPU features isn't going to scale well. Does
> 'xburst2' imply certain features? If so, not really any need to have
> them be explicit.
XBurst (XBurst1) is the first generation CPU core of Ingenic, its basic
property is single-issue in-order execution, XBurst2 is the second
generation CPU core of Ingenic, its basic property is daul-issue limited
out-of-order execution, and both CPU cores can cooperate with some
extended propeties, such as different versions of FPU, different
versions of MXU instruction set, with or without simultaneous
multi-threading.
Currently there is only one processor entity based on XBurst2 is
produced, so there is only one string for now.
Thanks and best regards!
>> +
>> + reg:
>> + maxItems: 1
>> +
>> +required:
>> + - device_type
>> + - compatible
>> + - reg
>> +
>> +examples:
>> + - |
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu0: cpu@0 {
>> + device_type = "cpu";
>> + compatible = "ingenic,xburst-fpu1.0-mxu1.1";
>> + reg = <0>;
>> + };
>> +
>> + cpu1: cpu@1 {
>> + device_type = "cpu";
>> + compatible = "ingenic,xburst-fpu1.0-mxu1.1";
>> + reg = <1>;
>> + };
>> + };
>> +...
>> --
>> 2.7.4
>>
^ permalink raw reply
* Re: [PATCH 1/1] dt-bindings: MIPS: Document Ingenic SoCs binding.
From: Zhou Yanjie @ 2020-05-27 6:10 UTC (permalink / raw)
To: Paul Cercueil
Cc: linux-mips, linux-kernel, devicetree, robh+dt, tsbogend, hns,
paul, dongsheng.qiu, aric.pzqi, sernia.zhou, zhenwenjin
In-Reply-To: <H9DYAQ.4YAB8VVZPLZO@crapouillou.net>
Hi Paul,
在 2020/5/27 上午3:10, Paul Cercueil 写道:
> Hi Zhou,
>
> Le mer. 27 mai 2020 à 1:07, 周琰杰 (Zhou Yanjie)
> <zhouyanjie@wanyeetech.com> a écrit :
>> Document the available properties for the SoC root node and the
>> CPU nodes of the devicetree for the Ingenic XBurst SoCs.
>>
>> Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
>> Tested-by: Paul Boddie <paul@boddie.org.uk>
>> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
>> ---
>> .../bindings/mips/ingenic/ingenic,cpu.yaml | 57
>> ++++++++++++++++++++++
>> 1 file changed, 57 insertions(+)
>> create mode 100644
>> Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
>>
>> diff --git
>> a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
>> b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
>> new file mode 100644
>> index 000000000000..afb02071a756
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
>> @@ -0,0 +1,57 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Bindings for Ingenic XBurst family CPUs
>> +
>> +maintainers:
>> + - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
>> +
>> +description:
>> + Ingenic XBurst family CPUs shall have the following properties.
>> +
>> +properties:
>> + compatible:
>> + oneOf:
>> +
>> + - description: Ingenic XBurst®1 CPU Cores
>> + items:
>
> Strip the 'items', put the enum directly.
>
Sure, I'll drop it in the next version.
>> + enum:
>> + - ingenic,xburst-mxu1.0
>> + - ingenic,xburst-fpu1.0-mxu1.1
>> + - ingenic,xburst-fpu2.0-mxu2.0
>> +
>> + - description: Ingenic XBurst®2 CPU Cores
>> + items:
>
> Same here.
>
Sure.
>> + enum:
>> + - ingenic,xburst2-fpu2.1-mxu2.1-smt
>> +
>> + reg:
>> + maxItems: 1
>> +
>> +required:
>> + - device_type
>> + - compatible
>> + - reg
>
> device_type is not in the list of your properties.
>
> Also, I think you need a clock in there.
>
Sure, I will add it.
Thanks and best regards!
> -Paul
>
>> +
>> +examples:
>> + - |
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + cpu0: cpu@0 {
>> + device_type = "cpu";
>> + compatible = "ingenic,xburst-fpu1.0-mxu1.1";
>> + reg = <0>;
>> + };
>> +
>> + cpu1: cpu@1 {
>> + device_type = "cpu";
>> + compatible = "ingenic,xburst-fpu1.0-mxu1.1";
>> + reg = <1>;
>> + };
>> + };
>> +...
>> --
>> 2.11.0
>>
>
^ permalink raw reply
* [PATCH V7 2/3] dt-bindings: geni-se: Add interconnect binding for GENI QUP
From: Akash Asthana @ 2020-05-27 6:27 UTC (permalink / raw)
To: robh+dt
Cc: linux-arm-msm, devicetree, linux-kernel, mgautam, rojay, skakit,
msavaliy, Akash Asthana
In-Reply-To: <1590560864-27037-1-git-send-email-akashast@codeaurora.org>
Add documentation for the interconnect and interconnect-names properties
for the GENI QUP.
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
Changes in V5:
- Add interconnect property for QUP wrapper (parent node).
- Add minItems = 2 for interconnect property in child nodes
Changes in V6:
- As per Rob's comment added minItems = 2 for interconnect-names.
Changes in V7:
- No change.
.../devicetree/bindings/soc/qcom/qcom,geni-se.yaml | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
index 885966f..b19505b 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
@@ -46,6 +46,12 @@ properties:
ranges: true
+ interconnects:
+ maxItems: 1
+
+ interconnect-names:
+ const: qup-core
+
required:
- compatible
- reg
@@ -73,6 +79,17 @@ patternProperties:
description: Serial engine core clock needed by the device.
maxItems: 1
+ interconnects:
+ minItems: 2
+ maxItems: 3
+
+ interconnect-names:
+ minItems: 2
+ items:
+ - const: qup-core
+ - const: qup-config
+ - const: qup-memory
+
required:
- reg
- clock-names
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH V7 3/3] dt-bindings: serial: Add binding for UART pin swap
From: Akash Asthana @ 2020-05-27 6:27 UTC (permalink / raw)
To: robh+dt
Cc: linux-arm-msm, devicetree, linux-kernel, mgautam, rojay, skakit,
msavaliy, Akash Asthana
In-Reply-To: <1590560864-27037-1-git-send-email-akashast@codeaurora.org>
Add documentation to support RX-TX & CTS-RTS GPIO pin swap in HW.
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
Changes in V7:
- As per Rob's comment, added type: boolean to properties.
Documentation/devicetree/bindings/serial/serial.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/serial/serial.yaml b/Documentation/devicetree/bindings/serial/serial.yaml
index 53204d9..8645d0e 100644
--- a/Documentation/devicetree/bindings/serial/serial.yaml
+++ b/Documentation/devicetree/bindings/serial/serial.yaml
@@ -67,6 +67,14 @@ properties:
(wired and enabled by pinmux configuration). This depends on both the
UART hardware and the board wiring.
+ rx-tx-swap:
+ type: boolean
+ description: RX and TX pins are swapped.
+
+ cts-rts-swap:
+ type: boolean
+ description: CTS and RTS pins are swapped.
+
if:
required:
- uart-has-rtscts
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply related
* Re: [PATCH v1 2/2] Add PWM driver for LGM
From: Tanwar, Rahul @ 2020-05-27 6:28 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: thierry.reding, p.zabel, linux-pwm, robh+dt, linux-kernel,
devicetree, andriy.shevchenko, songjun.Wu, cheol.yong.kim,
qi-ming.wu
In-Reply-To: <20200522085613.ktb2ruw2virj337v@pengutronix.de>
Hi Uwe,
Thanks for review.
On 22/5/2020 4:56 pm, Uwe Kleine-König wrote:
> Hello,
>
> On Fri, May 22, 2020 at 03:41:59PM +0800, Rahul Tanwar wrote:
>> Add PWM controller driver for Intel's Lightning Mountain(LGM) SoC.
>>
>> Signed-off-by: Rahul Tanwar <rahul.tanwar@linux.intel.com>
>> ---
>> drivers/pwm/Kconfig | 9 ++
>> drivers/pwm/Makefile | 1 +
>> drivers/pwm/pwm-intel-lgm.c | 356 ++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 366 insertions(+)
>> create mode 100644 drivers/pwm/pwm-intel-lgm.c
>>
>> diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
>> index eebbc917ac97..a582214f50b2 100644
>> --- a/drivers/pwm/Kconfig
>> +++ b/drivers/pwm/Kconfig
>> @@ -232,6 +232,15 @@ config PWM_IMX_TPM
>> To compile this driver as a module, choose M here: the module
>> will be called pwm-imx-tpm.
>>
>> +config PWM_INTEL_LGM
>> + tristate "Intel LGM PWM support"
>> + depends on X86 || COMPILE_TEST
>> + help
>> + Generic PWM framework driver for LGM SoC.
[...]
>> +};
>> +
>> +static void tach_work(struct work_struct *work)
>> +{
>> + struct intel_pwm_chip *pc = container_of(work, struct intel_pwm_chip,
>> + work.work);
>> + struct regmap *regmap = pc->regmap;
>> + u32 fan_tach, fan_dc, val;
>> + s32 diff;
>> + static u32 fanspeed_err_cnt, time_window, delta_dc;
>> +
>> + /*
>> + * Fan speed is tracked by reading the active duty cycle of PWM output
>> + * from the active duty cycle register. Some variance in the duty cycle
>> + * register value is expected. So we set a time window of 30 seconds and
>> + * if we detect inaccurate fan speed 6 times within 30 seconds then we
>> + * mark it as fan speed problem and fix it by readjusting the duty cycle.
>> + */
> I'm a unhappy to have this in the PWM driver. The PWM driver is supposed
> to be generic and I think this belongs into a dedicated driver.
Well noted about all other review concerns. I will rework the driver in v2.
However, i am not very sure about the above point - of having a separate
dedicated driver for tach_work because its logic is tightly coupled with
this driver.
Regards,
Rahul
^ permalink raw reply
* Re: [PATCH v6 2/5] remoteproc: qcom: Introduce helper to store pil info in IMEM
From: Stephen Boyd @ 2020-05-27 6:29 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Ohad Ben-Cohen
Cc: Rob Herring, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel, Mathieu Poirier, Vinod Koul
In-Reply-To: <20200527054850.2067032-3-bjorn.andersson@linaro.org>
Quoting Bjorn Andersson (2020-05-26 22:48:46)
> diff --git a/drivers/remoteproc/qcom_pil_info.c b/drivers/remoteproc/qcom_pil_info.c
> new file mode 100644
> index 000000000000..0785c7cde2d3
> --- /dev/null
> +++ b/drivers/remoteproc/qcom_pil_info.c
> @@ -0,0 +1,124 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2019-2020 Linaro Ltd.
> + */
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/mutex.h>
> +#include <linux/of_address.h>
> +
> +#define PIL_RELOC_NAME_LEN 8
> +
> +struct pil_reloc_entry {
> + char name[PIL_RELOC_NAME_LEN];
> + __le64 base;
> + __le32 size;
> +} __packed;
> +
> +struct pil_reloc {
> + struct device *dev;
This isn't assigned. Remove it?
> + void __iomem *base;
> + size_t num_entries;
> +};
> +
> +static struct pil_reloc _reloc __read_mostly;
> +static DEFINE_MUTEX(reloc_mutex);
reloc_mutex is a little generic. Maybe pil_reloc_lock or
qcom_pil_reloc_lock?
> +
> +static int qcom_pil_info_init(void)
> +{
> + struct device_node *np;
> + struct resource imem;
> + void __iomem *base;
> + int ret;
> +
> + /* Already initialized? */
> + if (_reloc.base)
> + return 0;
> +
> + np = of_find_compatible_node(NULL, NULL, "qcom,pil-reloc-info");
> + if (!np)
> + return -ENOENT;
> +
> + ret = of_address_to_resource(np, 0, &imem);
> + of_node_put(np);
> + if (ret < 0)
> + return ret;
> +
> + base = ioremap(imem.start, resource_size(&imem));
> + if (!base) {
> + pr_err("failed to map PIL relocation info region\n");
> + return -ENOMEM;
> + }
> +
> + memset_io(base, 0, resource_size(&imem));
> +
> + _reloc.base = base;
> + _reloc.num_entries = resource_size(&imem) / sizeof(struct pil_reloc_entry);
> +
> + return 0;
> +}
> +
> +/**
> + * qcom_pil_info_store() - store PIL information of image in IMEM
> + * @image: name of the image
> + * @base: base address of the loaded image
> + * @size: size of the loaded image
> + *
> + * Return: 0 on success, negative errno on failure
> + */
> +int qcom_pil_info_store(const char *image, phys_addr_t base, size_t size)
> +{
> + char buf[PIL_RELOC_NAME_LEN];
> + void __iomem *entry;
> + int ret;
> + int i;
> +
> + mutex_lock(&reloc_mutex);
> + ret = qcom_pil_info_init();
> + if (ret < 0) {
> + mutex_unlock(&reloc_mutex);
> + return ret;
> + }
> +
> + for (i = 0; i < _reloc.num_entries; i++) {
> + entry = _reloc.base + i * sizeof(struct pil_reloc_entry);
> +
> + memcpy_fromio(buf, entry, PIL_RELOC_NAME_LEN);
> +
> + /*
> + * An empty record means we didn't find it, given that the
> + * records are packed.
> + */
> + if (!buf[0])
> + goto found_unused;
> +
> + if (!strncmp(buf, image, PIL_RELOC_NAME_LEN))
> + goto found_existing;
> + }
> +
> + pr_warn("insufficient PIL info slots\n");
> + mutex_unlock(&reloc_mutex);
> + return -ENOMEM;
> +
> +found_unused:
> + memcpy_toio(entry, image, PIL_RELOC_NAME_LEN);
> +found_existing:
> + writel(base, entry + offsetof(struct pil_reloc_entry, base));
> + writel(size, entry + offsetof(struct pil_reloc_entry, size));
It makes me nervous to see offsetof() used in the same line as writel()
because who knows what the compiler does, even with __packed and stuff.
I guess I tried and failed to convince you earlier to change this code
to use fixed offsets instead of structs to describe the memory layout
but that must have failed!
> + mutex_unlock(&reloc_mutex);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(qcom_pil_info_store);
> +
> +static void __exit pil_reloc_exit(void)
> +{
> + mutex_lock(&reloc_mutex);
> + iounmap(_reloc.base);
> + _reloc.base = NULL;
> + mutex_unlock(&reloc_mutex);
> +}
> +module_exit(pil_reloc_exit);
> +
> +MODULE_DESCRIPTION("Qualcomm PIL relocation info");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/remoteproc/qcom_pil_info.h b/drivers/remoteproc/qcom_pil_info.h
> new file mode 100644
> index 000000000000..1b89a63ba82f
> --- /dev/null
> +++ b/drivers/remoteproc/qcom_pil_info.h
> @@ -0,0 +1,7 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __QCOM_PIL_INFO_H__
> +#define __QCOM_PIL_INFO_H__
Probably need <linux/types.h> here for phys_addr_t definition to make
this header self-contained.
> +
> +int qcom_pil_info_store(const char *image, phys_addr_t base, size_t size);
> +
> +#endif
^ permalink raw reply
* Re: [PATCH v6 3/5] remoteproc: qcom: Update PIL relocation info on load
From: Stephen Boyd @ 2020-05-27 6:31 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Ohad Ben-Cohen
Cc: Rob Herring, linux-arm-msm, linux-remoteproc, devicetree,
linux-kernel, Vinod Koul
In-Reply-To: <20200527054850.2067032-4-bjorn.andersson@linaro.org>
Quoting Bjorn Andersson (2020-05-26 22:48:47)
> Update the PIL relocation information in IMEM with information about
> where the firmware for various remoteprocs are loaded.
>
> Reviewed-by: Vinod Koul <vkoul@kernel.org>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> ---
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
^ permalink raw reply
* [PATCH V7 0/3] Convert QUP bindings to YAML and add ICC, pin swap doc
From: Akash Asthana @ 2020-05-27 6:27 UTC (permalink / raw)
To: robh+dt
Cc: linux-arm-msm, devicetree, linux-kernel, mgautam, rojay, skakit,
msavaliy, Akash Asthana
Changes in V6:
- As per Rob's suggestion moved pin swap documentation from QUP to
serial.yaml file[PATCH V6 3/3].
Changes in V4:
- Add interconnect binding patch.
- Add UART pin swap binding patch.
Akash Asthana (3):
dt-bindings: geni-se: Convert QUP geni-se bindings to YAML
dt-bindings: geni-se: Add interconnect binding for GENI QUP
dt-bindings: serial: Add binding for UART pin swap
.../devicetree/bindings/serial/serial.yaml | 6 +
.../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 94 ---------
.../devicetree/bindings/soc/qcom/qcom,geni-se.yaml | 227 +++++++++++++++++++++
3 files changed, 233 insertions(+), 94 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH V7 1/3] dt-bindings: geni-se: Convert QUP geni-se bindings to YAML
From: Akash Asthana @ 2020-05-27 6:27 UTC (permalink / raw)
To: robh+dt
Cc: linux-arm-msm, devicetree, linux-kernel, mgautam, rojay, skakit,
msavaliy, Akash Asthana
In-Reply-To: <1590560864-27037-1-git-send-email-akashast@codeaurora.org>
Convert QUP geni-se bindings to DT schema format using json-schema.
Signed-off-by: Akash Asthana <akashast@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
Changes in V2:
- As per Stephen's comment corrected defintion of interrupts for UART node.
Any valid UART node must contain atleast 1 interrupts.
Changes in V3:
- As per Rob's comment, added number of reg entries for reg property.
- As per Rob's comment, corrected unit address to hex.
- As per Rob's comment, created a pattern which matches everything common
to geni based I2C, SPI and UART controller and then one pattern for each.
- As per Rob's comment, restored original example.
Changes in V4:
- Resolve below compilation error reported from bot.
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/qcom/
qcom,geni-se.yaml: properties:clocks:minItems: False schema does not allow 2
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/soc/qcom/
qcom,geni-se.yaml: properties:clocks:maxItems: False schema does not allow 2
Documentation/devicetree/bindings/Makefile:12: recipe for target
'Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dts' failed
make[1]: *** [Documentation/devicetree/bindings/soc/qcom/
qcom,geni-se.example.dts] Error 1
Makefile:1263: recipe for target 'dt_binding_check' failed
make: *** [dt_binding_check] Error 2
Changes in V6:
- Added reg entry for soc@0 example node to address below warning.
Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.example.dts:22.20-60.11
: Warning (unit_address_vs_reg): /example-0/soc@0: node has a unit name,
but no reg or ranges property
Changes in V7:
- No change.
.../devicetree/bindings/soc/qcom/qcom,geni-se.txt | 94 ---------
.../devicetree/bindings/soc/qcom/qcom,geni-se.yaml | 210 +++++++++++++++++++++
2 files changed, 210 insertions(+), 94 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
deleted file mode 100644
index dab7ca9..0000000
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.txt
+++ /dev/null
@@ -1,94 +0,0 @@
-Qualcomm Technologies, Inc. GENI Serial Engine QUP Wrapper Controller
-
-Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
-is a programmable module for supporting a wide range of serial interfaces
-like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
-Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
-Wrapper controller is modeled as a node with zero or more child nodes each
-representing a serial engine.
-
-Required properties:
-- compatible: Must be "qcom,geni-se-qup".
-- reg: Must contain QUP register address and length.
-- clock-names: Must contain "m-ahb" and "s-ahb".
-- clocks: AHB clocks needed by the device.
-
-Required properties if child node exists:
-- #address-cells: Must be <1> for Serial Engine Address
-- #size-cells: Must be <1> for Serial Engine Address Size
-- ranges: Must be present
-
-Properties for children:
-
-A GENI based QUP wrapper controller node can contain 0 or more child nodes
-representing serial devices. These serial devices can be a QCOM UART, I2C
-controller, SPI controller, or some combination of aforementioned devices.
-Please refer below the child node definitions for the supported serial
-interface protocols.
-
-Qualcomm Technologies Inc. GENI Serial Engine based I2C Controller
-
-Required properties:
-- compatible: Must be "qcom,geni-i2c".
-- reg: Must contain QUP register address and length.
-- interrupts: Must contain I2C interrupt.
-- clock-names: Must contain "se".
-- clocks: Serial engine core clock needed by the device.
-- #address-cells: Must be <1> for I2C device address.
-- #size-cells: Must be <0> as I2C addresses have no size component.
-
-Optional property:
-- clock-frequency: Desired I2C bus clock frequency in Hz.
- When missing default to 100000Hz.
-
-Child nodes should conform to I2C bus binding as described in i2c.txt.
-
-Qualcomm Technologies Inc. GENI Serial Engine based UART Controller
-
-Required properties:
-- compatible: Must be "qcom,geni-debug-uart" or "qcom,geni-uart".
-- reg: Must contain UART register location and length.
-- interrupts: Must contain UART core interrupts.
-- clock-names: Must contain "se".
-- clocks: Serial engine core clock needed by the device.
-
-Qualcomm Technologies Inc. GENI Serial Engine based SPI Controller
-node binding is described in
-Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.txt.
-
-Example:
- geniqup@8c0000 {
- compatible = "qcom,geni-se-qup";
- reg = <0x8c0000 0x6000>;
- clock-names = "m-ahb", "s-ahb";
- clocks = <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
- <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- i2c0: i2c@a94000 {
- compatible = "qcom,geni-i2c";
- reg = <0xa94000 0x4000>;
- interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "se";
- clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>;
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qup_1_i2c_5_active>;
- pinctrl-1 = <&qup_1_i2c_5_sleep>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- uart0: serial@a88000 {
- compatible = "qcom,geni-debug-uart";
- reg = <0xa88000 0x7000>;
- interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "se";
- clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&qup_1_uart_3_active>;
- pinctrl-1 = <&qup_1_uart_3_sleep>;
- };
-
- }
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
new file mode 100644
index 0000000..885966f
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
@@ -0,0 +1,210 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: GENI Serial Engine QUP Wrapper Controller
+
+maintainers:
+ - Mukesh Savaliya <msavaliy@codeaurora.org>
+ - Akash Asthana <akashast@codeaurora.org>
+
+description: |
+ Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
+ is a programmable module for supporting a wide range of serial interfaces
+ like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
+ Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
+ Wrapper controller is modeled as a node with zero or more child nodes each
+ representing a serial engine.
+
+properties:
+ compatible:
+ enum:
+ - qcom,geni-se-qup
+
+ reg:
+ description: QUP wrapper common register address and length.
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: m-ahb
+ - const: s-ahb
+
+ clocks:
+ items:
+ - description: Master AHB Clock
+ - description: Slave AHB Clock
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ ranges: true
+
+required:
+ - compatible
+ - reg
+ - clock-names
+ - clocks
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+patternProperties:
+ "^.*@[0-9a-f]+$":
+ type: object
+ description: Common properties for GENI Serial Engine based I2C, SPI and
+ UART controller.
+
+ properties:
+ reg:
+ description: GENI Serial Engine register address and length.
+ maxItems: 1
+
+ clock-names:
+ const: se
+
+ clocks:
+ description: Serial engine core clock needed by the device.
+ maxItems: 1
+
+ required:
+ - reg
+ - clock-names
+ - clocks
+
+ "spi@[0-9a-f]+$":
+ type: object
+ description: GENI serial engine based SPI controller. SPI in master mode
+ supports up to 50MHz, up to four chip selects, programmable
+ data path from 4 bits to 32 bits and numerous protocol
+ variants.
+ allOf:
+ - $ref: /spi/spi-controller.yaml#
+
+ properties:
+ compatible:
+ enum:
+ - qcom,geni-spi
+
+ interrupts:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ required:
+ - compatible
+ - interrupts
+ - "#address-cells"
+ - "#size-cells"
+
+ "i2c@[0-9a-f]+$":
+ type: object
+ description: GENI serial engine based I2C controller.
+ allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+ properties:
+ compatible:
+ enum:
+ - qcom,geni-i2c
+
+ interrupts:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ clock-frequency:
+ description: Desired I2C bus clock frequency in Hz.
+ default: 100000
+
+ required:
+ - compatible
+ - interrupts
+ - "#address-cells"
+ - "#size-cells"
+
+ "serial@[0-9a-f]+$":
+ type: object
+ description: GENI Serial Engine based UART Controller.
+ allOf:
+ - $ref: /schemas/serial.yaml#
+
+ properties:
+ compatible:
+ enum:
+ - qcom,geni-uart
+ - qcom,geni-debug-uart
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: UART core irq
+ - description: Wakeup irq (RX GPIO)
+
+ required:
+ - compatible
+ - interrupts
+
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc: soc@0 {
+ reg = <0 0x10000000 0 0x0fffffff>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ geniqup@8c0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0 0x008c0000 0 0x6000>;
+ clock-names = "m-ahb", "s-ahb";
+ clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ i2c0: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0xa94000 0 0x4000>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qup_1_i2c_5_active>;
+ pinctrl-1 = <&qup_1_i2c_5_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ uart0: serial@a88000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0xa88000 0 0x7000>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&qup_1_uart_3_active>;
+ pinctrl-1 = <&qup_1_uart_3_sleep>;
+ };
+ };
+ };
+
+...
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
^ permalink raw reply related
* Re: [PATCH v3 03/16] mfd: mfd-core: match device tree node against reg property
From: Lee Jones @ 2020-05-27 6:53 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Michael Walle, Linus Walleij, Bartosz Golaszewski, Rob Herring,
Jean Delvare, Guenter Roeck, Thierry Reding,
Uwe Kleine-König, Wim Van Sebroeck, Shawn Guo, Li Yang,
Thomas Gleixner, Jason Cooper, Marc Zyngier, Mark Brown,
Greg Kroah-Hartman, linux-gpio, devicetree, linux-kernel,
linux-hwmon, linux-pwm, linux-watchdog, linux-arm-kernel
In-Reply-To: <20200526160336.GV1634618@smile.fi.intel.com>
On Tue, 26 May 2020, Andy Shevchenko wrote:
> On Tue, May 26, 2020 at 05:54:38PM +0200, Michael Walle wrote:
> > Am 2020-05-26 09:24, schrieb Lee Jones:
>
> ...
>
> > Like I said, in the long term I would like to have support for
> > different versions of the board management controller
>
> > without having to change the device tree and have device tree bindings for the
> > subdevices at the same time.
>
> But isn't device tree to describe *very specific platform* rather than *class
> of platforms*?
Yes. Device Tree describes the hardware.
If the hardware changes, so must the Device Tree.
--
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* Re: [PATCH v2 25/91] clk: bcm: Add BCM2711 DVP driver
From: Stephen Boyd @ 2020-05-27 7:06 UTC (permalink / raw)
To: Eric Anholt, Maxime Ripard, Nicolas Saenz Julienne
Cc: dri-devel, linux-rpi-kernel, bcm-kernel-feedback-list,
linux-arm-kernel, linux-kernel, Dave Stevenson, Tim Gover,
Phil Elwell, Maxime Ripard, Michael Turquette, Rob Herring,
linux-clk, devicetree
In-Reply-To: <a1efabae8d7df30c987bff10544c2071e906e07a.1587742492.git-series.maxime@cerno.tech>
Quoting Maxime Ripard (2020-04-24 08:34:06)
> The HDMI block has a block that controls clocks and reset signals to the
> HDMI0 and HDMI1 controllers.
>
> Let's expose that through a clock driver implementing a clock and reset
> provider.
>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-clk@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
> diff --git a/drivers/clk/bcm/clk-bcm2711-dvp.c b/drivers/clk/bcm/clk-bcm2711-dvp.c
> new file mode 100644
> index 000000000000..c1c4b5857d32
> --- /dev/null
> +++ b/drivers/clk/bcm/clk-bcm2711-dvp.c
> @@ -0,0 +1,127 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +// Copyright 2020 Cerno
> +
> +#include <linux/clk-provider.h>
> +#include <linux/module.h>
[...]
> +
> +static int clk_dvp_probe(struct platform_device *pdev)
> +{
> + struct clk_hw_onecell_data *data;
> + struct resource *res;
> + struct clk_dvp *dvp;
> + void __iomem *base;
> + int ret;
> +
> + dvp = devm_kzalloc(&pdev->dev, sizeof(*dvp), GFP_KERNEL);
> + if (!dvp)
> + return -ENOMEM;
> + platform_set_drvdata(pdev, dvp);
> +
> + dvp->data = devm_kzalloc(&pdev->dev,
> + struct_size(dvp->data, hws, NR_CLOCKS),
> + GFP_KERNEL);
> + if (!dvp->data)
> + return -ENOMEM;
> + data = dvp->data;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(&pdev->dev, res);
devm_platform_ioremap_resource()?
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
^ permalink raw reply
* [PATCH v6 0/9] Enable ili9341 and l3gd20 on stm32f429-disco
From: dillon.minfei @ 2020-05-27 7:27 UTC (permalink / raw)
To: robh+dt, p.zabel, mcoquelin.stm32, alexandre.torgue,
thierry.reding, sam, airlied, daniel, mturquette, sboyd,
andy.shevchenko, noralf, linus.walleij, broonie
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-spi,
linux-stm32, dri-devel, linux-clk, dillonhua, dillon min
From: dillon min <dillon.minfei@gmail.com>
V6:
1 separate '[PATCH v5 5/8]' patchs to two, each one has a Fixes tags according
to Stephen Boyd's suggestion
2 fix panel-ilitek-ili9341 compile warning 'warning: Function parameter or
member xxx not described in xxx' with W=1
V5's update based on Mark Brown's suggestion, use 'SPI_MASTER_MUST_RX'
for SPI_SIMPLEX_RX mode on stm32 spi controller.
V5:
1 instead of add send dummy data out under SIMPLEX_RX mode,
add flags 'SPI_CONTROLLER_MUST_TX' for stm32 spi driver
2 bypass 'SPI_CONTROLLER_MUST_TX' and 'SPI_CONTROLLER_MUST_RX' under
'SPI_3WIRE' mode
V4:
According to alexandre torgue's suggestion, combine ili9341 and
l3gd20's modification on stm32f429-disco board to one patchset.
Changes:
ili9341:
1 update ili9341 panel driver according to Linus's suggestion
2 drop V1's No.5 patch, sumbit new changes for clk-stm32f4
3 merge l3gd20's change to this patchset
V3:
1 merge original tiny/ili9341.c driver to panel/panel-ilitek-ili9341.c
to support serial spi & parallel rgb interface in one driver.
2 update ilitek,ili9341.yaml dts binding documentation.
3 update stm32f429-disco dts binding
V2:
1 verify ilitek,ili9341.yaml with make O=../linux-stm32
dt_binding_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/display/panel/
ilitek,ili9341.yaml
V1:
1 add ili9341 drm panel driver
2 add ltdc, spi5 controller for stm32f429-disco
3 add ltdc, spi5 pin map for stm32f429-disco
4 add docs about ili9341
5 fix ltdc driver loading hang in clk set rate bug
L3gd20:
V3:
1 merge stm32f429-disco dtbs binding with ili9341 part
V2:
1 insert blank line at stm32f420-disco.dts line 143
2 add more description for l3gd20 in commit message
V1:
1 enable spi5 controller on stm32f429-disco (dts)
2 add spi5 pinmap for stm32f429-disco (dts)
3 add SPI_SIMPLEX_RX, SPI_3WIRE_RX support for stm32f4
dillon min (9):
ARM: dts: stm32: Add dma config for spi5
ARM: dts: stm32: Add pin map for ltdc & spi5 on stm32f429-disco board
ARM: dts: stm32: enable ltdc binding with ili9341, gyro l3gd20 on
stm32429-disco board
dt-bindings: display: panel: Add ilitek ili9341 panel bindings
clk: stm32: Fix stm32f429's ltdc driver hang in set clock rate
clk: stm32: Fix ltdc's clock turn off by clk_disable_unused() after
kernel startup
drm/panel: Add ilitek ili9341 panel driver
spi: stm32: Add 'SPI_SIMPLEX_RX', 'SPI_3WIRE_RX' support for stm32f4
spi: flags 'SPI_CONTROLLER_MUST_RX' and 'SPI_CONTROLLER_MUST_TX' can't
be coexit with 'SPI_3WIRE' mode
.../bindings/display/panel/ilitek,ili9341.yaml | 69 ++
arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 67 +
arch/arm/boot/dts/stm32f429-disco.dts | 48 +
arch/arm/boot/dts/stm32f429.dtsi | 3 +
drivers/clk/clk-stm32f4.c | 7 +-
drivers/gpu/drm/panel/Kconfig | 12 +
drivers/gpu/drm/panel/Makefile | 1 +
drivers/gpu/drm/panel/panel-ilitek-ili9341.c | 1288 ++++++++++++++++++++
drivers/spi/spi-stm32.c | 19 +-
drivers/spi/spi.c | 3 +-
10 files changed, 1508 insertions(+), 9 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
create mode 100644 drivers/gpu/drm/panel/panel-ilitek-ili9341.c
--
2.7.4
^ permalink raw reply
* [PATCH v6 1/9] ARM: dts: stm32: Add dma config for spi5
From: dillon.minfei @ 2020-05-27 7:27 UTC (permalink / raw)
To: robh+dt, p.zabel, mcoquelin.stm32, alexandre.torgue,
thierry.reding, sam, airlied, daniel, mturquette, sboyd,
andy.shevchenko, noralf, linus.walleij, broonie
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-spi,
linux-stm32, dri-devel, linux-clk, dillonhua, dillon min
In-Reply-To: <1590564453-24499-1-git-send-email-dillon.minfei@gmail.com>
From: dillon min <dillon.minfei@gmail.com>
Enable spi5's dma configuration. for graphics data output to
ilitek ili9341 panel via mipi dbi interface
Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
arch/arm/boot/dts/stm32f429.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index d7770699feb5..5820b11e7365 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -660,6 +660,9 @@
reg = <0x40015000 0x400>;
interrupts = <85>;
clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
+ dmas = <&dma2 3 2 0x400 0x0>,
+ <&dma2 4 2 0x400 0x0>;
+ dma-names = "rx", "tx";
status = "disabled";
};
--
2.7.4
^ permalink raw reply related
* [PATCH v6 2/9] ARM: dts: stm32: Add pin map for ltdc & spi5 on stm32f429-disco board
From: dillon.minfei @ 2020-05-27 7:27 UTC (permalink / raw)
To: robh+dt, p.zabel, mcoquelin.stm32, alexandre.torgue,
thierry.reding, sam, airlied, daniel, mturquette, sboyd,
andy.shevchenko, noralf, linus.walleij, broonie
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-spi,
linux-stm32, dri-devel, linux-clk, dillonhua, dillon min
In-Reply-To: <1590564453-24499-1-git-send-email-dillon.minfei@gmail.com>
From: dillon min <dillon.minfei@gmail.com>
This patch adds the pin configuration for ltdc and spi5 controller
on stm32f429-disco board.
Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 67 ++++++++++++++++++++++++++++++++++
1 file changed, 67 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
index 392fa143ce07..0eb107f968cd 100644
--- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
@@ -316,6 +316,73 @@
};
};
+ ltdc_pins_f429_disco: ltdc-1 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 6, AF14)>,
+ /* LCD_HSYNC */
+ <STM32_PINMUX('A', 4, AF14)>,
+ /* LCD_VSYNC */
+ <STM32_PINMUX('G', 7, AF14)>,
+ /* LCD_CLK */
+ <STM32_PINMUX('C', 10, AF14)>,
+ /* LCD_R2 */
+ <STM32_PINMUX('B', 0, AF9)>,
+ /* LCD_R3 */
+ <STM32_PINMUX('A', 11, AF14)>,
+ /* LCD_R4 */
+ <STM32_PINMUX('A', 12, AF14)>,
+ /* LCD_R5 */
+ <STM32_PINMUX('B', 1, AF9)>,
+ /* LCD_R6*/
+ <STM32_PINMUX('G', 6, AF14)>,
+ /* LCD_R7 */
+ <STM32_PINMUX('A', 6, AF14)>,
+ /* LCD_G2 */
+ <STM32_PINMUX('G', 10, AF9)>,
+ /* LCD_G3 */
+ <STM32_PINMUX('B', 10, AF14)>,
+ /* LCD_G4 */
+ <STM32_PINMUX('D', 6, AF14)>,
+ /* LCD_B2 */
+ <STM32_PINMUX('G', 11, AF14)>,
+ /* LCD_B3*/
+ <STM32_PINMUX('B', 11, AF14)>,
+ /* LCD_G5 */
+ <STM32_PINMUX('C', 7, AF14)>,
+ /* LCD_G6 */
+ <STM32_PINMUX('D', 3, AF14)>,
+ /* LCD_G7 */
+ <STM32_PINMUX('G', 12, AF9)>,
+ /* LCD_B4 */
+ <STM32_PINMUX('A', 3, AF14)>,
+ /* LCD_B5 */
+ <STM32_PINMUX('B', 8, AF14)>,
+ /* LCD_B6 */
+ <STM32_PINMUX('B', 9, AF14)>,
+ /* LCD_B7 */
+ <STM32_PINMUX('F', 10, AF14)>;
+ /* LCD_DE */
+ slew-rate = <2>;
+ };
+ };
+
+ spi5_pins: spi5-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('F', 7, AF5)>,
+ /* SPI5_CLK */
+ <STM32_PINMUX('F', 9, AF5)>;
+ /* SPI5_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 8, AF5)>;
+ /* SPI5_MISO */
+ bias-disable;
+ };
+ };
+
dcmi_pins: dcmi-0 {
pins {
pinmux = <STM32_PINMUX('A', 4, AF13)>, /* DCMI_HSYNC */
--
2.7.4
^ permalink raw reply related
* [PATCH v6 3/9] ARM: dts: stm32: enable ltdc binding with ili9341, gyro l3gd20 on stm32429-disco board
From: dillon.minfei @ 2020-05-27 7:27 UTC (permalink / raw)
To: robh+dt, p.zabel, mcoquelin.stm32, alexandre.torgue,
thierry.reding, sam, airlied, daniel, mturquette, sboyd,
andy.shevchenko, noralf, linus.walleij, broonie
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-spi,
linux-stm32, dri-devel, linux-clk, dillonhua, dillon min
In-Reply-To: <1590564453-24499-1-git-send-email-dillon.minfei@gmail.com>
From: dillon min <dillon.minfei@gmail.com>
Enable the ltdc & ili9341, gyro l3gd20 on stm32429-disco board.
Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
arch/arm/boot/dts/stm32f429-disco.dts | 48 +++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429-disco.dts b/arch/arm/boot/dts/stm32f429-disco.dts
index 30c0f6717871..365d16fd3934 100644
--- a/arch/arm/boot/dts/stm32f429-disco.dts
+++ b/arch/arm/boot/dts/stm32f429-disco.dts
@@ -49,6 +49,8 @@
#include "stm32f429.dtsi"
#include "stm32f429-pinctrl.dtsi"
#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "STMicroelectronics STM32F429i-DISCO board";
@@ -127,3 +129,49 @@
pinctrl-names = "default";
status = "okay";
};
+
+<dc {
+ status = "okay";
+ pinctrl-0 = <<dc_pins_f429_disco>;
+ pinctrl-names = "default";
+
+ port {
+ ltdc_out_rgb: endpoint {
+ remote-endpoint = <&panel_in_rgb>;
+ };
+ };
+};
+
+&spi5 {
+ status = "okay";
+ pinctrl-0 = <&spi5_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cs-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>, <&gpioc 2 GPIO_ACTIVE_LOW>;
+
+ l3gd20: l3gd20@0 {
+ compatible = "st,l3gd20-gyro";
+ spi-max-frequency = <10000000>;
+ st,drdy-int-pin = <2>;
+ interrupt-parent = <&gpioa>;
+ interrupts = <1 IRQ_TYPE_EDGE_RISING>,
+ <2 IRQ_TYPE_EDGE_RISING>;
+ reg = <0>;
+ status = "okay";
+ };
+
+ display: display@1{
+ /* Connect panel-ilitek-9341 to ltdc */
+ compatible = "st,sf-tc240t-9370-t";
+ reg = <1>;
+ spi-3wire;
+ spi-max-frequency = <10000000>;
+ dc-gpios = <&gpiod 13 0>;
+ port {
+ panel_in_rgb: endpoint {
+ remote-endpoint = <<dc_out_rgb>;
+ };
+ };
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH v6 4/9] dt-bindings: display: panel: Add ilitek ili9341 panel bindings
From: dillon.minfei @ 2020-05-27 7:27 UTC (permalink / raw)
To: robh+dt, p.zabel, mcoquelin.stm32, alexandre.torgue,
thierry.reding, sam, airlied, daniel, mturquette, sboyd,
andy.shevchenko, noralf, linus.walleij, broonie
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-spi,
linux-stm32, dri-devel, linux-clk, dillonhua, dillon min
In-Reply-To: <1590564453-24499-1-git-send-email-dillon.minfei@gmail.com>
From: dillon min <dillon.minfei@gmail.com>
Add documentation for "ilitek,ili9341" panel.
Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
.../bindings/display/panel/ilitek,ili9341.yaml | 69 ++++++++++++++++++++++
1 file changed, 69 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
new file mode 100644
index 000000000000..2172f889af3c
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9341.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/ilitek,ili9341.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Ilitek-9341 Display Panel
+
+maintainers:
+ - Dillon Min <dillon.minfei@gmail.com>
+
+description: |
+ Ilitek ILI9341 TFT panel driver with SPI control bus
+ This is a driver for 320x240 TFT panels, accepting a rgb input
+ streams with 16 bits or 18 bits.
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ # ili9341 240*320 Color on stm32f429-disco board
+ - st,sf-tc240t-9370-t
+ - const: ilitek,ili9341
+
+ reg: true
+
+ dc-gpios:
+ maxItems: 1
+ description: Display data/command selection (D/CX)
+
+ spi-3wire: true
+
+ spi-max-frequency:
+ const: 10000000
+
+ port: true
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - dc-gpios
+ - port
+
+examples:
+ - |+
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ panel: display@0 {
+ compatible = "st,sf-tc240t-9370-t",
+ "ilitek,ili9341";
+ reg = <0>;
+ spi-3wire;
+ spi-max-frequency = <10000000>;
+ dc-gpios = <&gpiod 13 0>;
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&display_out>;
+ };
+ };
+ };
+ };
+...
+
--
2.7.4
^ permalink raw reply related
* [PATCH v6 5/9] clk: stm32: Fix stm32f429's ltdc driver hang in set clock rate
From: dillon.minfei @ 2020-05-27 7:27 UTC (permalink / raw)
To: robh+dt, p.zabel, mcoquelin.stm32, alexandre.torgue,
thierry.reding, sam, airlied, daniel, mturquette, sboyd,
andy.shevchenko, noralf, linus.walleij, broonie
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-spi,
linux-stm32, dri-devel, linux-clk, dillonhua, dillon min
In-Reply-To: <1590564453-24499-1-git-send-email-dillon.minfei@gmail.com>
From: dillon min <dillon.minfei@gmail.com>
This is due to misuse ‘PLL_VCO_SAI' and'PLL_SAI' in clk-stm32f4.c
'PLL_SAI' is 2, 'PLL_VCO_SAI' is 7(defined in
include/dt-bindings/clock/stm32fx-clock.h).
'post_div' point to 'post_div_data[]', 'post_div->pll_num'
is PLL_I2S or PLL_SAI.
'clks[PLL_VCO_SAI]' has valid 'struct clk_hw* ' return
from stm32f4_rcc_register_pll() but, at line 1777 of
driver/clk/clk-stm32f4.c, use the 'clks[post_div->pll_num]',
equal to 'clks[PLL_SAI]', this is invalid array member at that time.
Fixes: 517633ef630e ("clk: stm32f4: Add post divisor for I2S & SAI PLLs")
Signed-off-by: dillon min <dillon.minfei@gmail.com>
---
Hi Stephen Boyd,
This update include below changes since V5
1 separate '[PATCH v5 5/8]' patch to two submits
2 each one has a Fixes tags
best regards.
drivers/clk/clk-stm32f4.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index 18117ce5ff85..42ca2dd86aea 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -557,13 +557,13 @@ static const struct clk_div_table post_divr_table[] = {
#define MAX_POST_DIV 3
static const struct stm32f4_pll_post_div_data post_div_data[MAX_POST_DIV] = {
- { CLK_I2SQ_PDIV, PLL_I2S, "plli2s-q-div", "plli2s-q",
+ { CLK_I2SQ_PDIV, PLL_VCO_I2S, "plli2s-q-div", "plli2s-q",
CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL},
- { CLK_SAIQ_PDIV, PLL_SAI, "pllsai-q-div", "pllsai-q",
+ { CLK_SAIQ_PDIV, PLL_VCO_SAI, "pllsai-q-div", "pllsai-q",
CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL },
- { NO_IDX, PLL_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
+ { NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table },
};
--
2.7.4
^ permalink raw reply related
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