* Re: [PATCH 16/17] dt-bindings: watchdog: renesas,wdt: Document r8a7742 support
From: Rob Herring @ 2020-05-27 14:38 UTC (permalink / raw)
To: Lad, Prabhakar
Cc: Lad Prabhakar, Geert Uytterhoeven, Jens Axboe, Wolfram Sang,
Ulf Hansson, Sergei Shtylyov, David S. Miller, Wim Van Sebroeck,
Guenter Roeck,
open list:LIBATA SUBSYSTEM (Serial and Parallel ATA drivers),
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, LKML,
Linux I2C, Linux MMC List, netdev, Linux-Renesas,
Linux Watchdog Mailing List
In-Reply-To: <CA+V-a8t6mXkTUac69V=T8_27r_sdN+=MktDTM1mmtbXRn8SSQQ@mail.gmail.com>
On Wed, May 27, 2020 at 5:23 AM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
>
> Hi Rob,
>
> On Wed, May 27, 2020 at 2:31 AM Rob Herring <robh@kernel.org> wrote:
> >
> > On Fri, May 15, 2020 at 04:08:56PM +0100, Lad Prabhakar wrote:
> > > RZ/G1H (R8A7742) watchdog implementation is compatible with R-Car Gen2,
> > > therefore add relevant documentation.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
> > > ---
> > > Documentation/devicetree/bindings/watchdog/renesas,wdt.txt | 1 +
> > > 1 file changed, 1 insertion(+)
> >
> > Meanwhile in the DT tree, converting this schema landed. Can you prepare
> > a version based on the schema.
> >
> This was kindly taken care by Stephen during merge in linux-next [1].
Yes, I'm aware of that. I was hoping for a better commit message which
stands on its own (essentially the one here).
Rob
^ permalink raw reply
* Re: [PATCH V1 RESEND 1/3] perf/imx_ddr: Add system PMU identifier for userspace
From: John Garry @ 2020-05-27 14:34 UTC (permalink / raw)
To: Will Deacon, Rob Herring
Cc: Mark Rutland, devicetree, Joakim Zhang,
linux-kernel@vger.kernel.org, NXP Linux Team, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Zhangshaokun
In-Reply-To: <c3be06c5-781f-384f-768b-d809da99b7e0@huawei.com>
>>>>
>>>> I also really dislike this. What's the preferred way to identify the
>>>> SoC
>>>> from userspace?
>>>
>>> /proc/cpuinfo? ;)
>>
>> The *SoC*!
>>
>>> For an non-firmware specific case, I'd say soc_device should be. I'd
>>> guess ACPI systems don't use it and for them it's dmidecode typically.
>>> The other problem I have with soc_device is it is optional.
>>
>
> Hi Will,
>
>> John -- what do you think about using soc_device to expose this
>> information,
>> with ACPI systems using DMI data instead?
>
> Generally I don't think that DMI is reliable, and I saw this as the
> least preferred choice. I'm looking at the sysfs DMI info for my dev
> board, and I don't even see anything like a SoC identifier.
>
> As for the event_source device sysfs identifier file, it would not
> always contain effectively the same as the SoC ID.
>
> Certain PMUs which I'm interested in plan to have probe-able
> identification info available in future.
>
BTW, Shaokun now tells me that the HiSi uncore PMU HW have such
registers to identify the implementation. I didn't know.
So we could add that identifier file for those PMUs as proof-of-concept,
exposing that register.
As for other PMUs which I'm interested in, again, future versions should
have such registers to self-identify.
So using something derived from the DT compat string would hopefully be
the uncommon case.
Cheers,
John
^ permalink raw reply
* Re: [PATCH v25 01/16] dt: bindings: Add multicolor class dt bindings documention
From: Rob Herring @ 2020-05-27 14:35 UTC (permalink / raw)
To: Pavel Machek
Cc: Dan Murphy, Jacek Anaszewski, devicetree, Linux LED Subsystem,
linux-kernel@vger.kernel.org
In-Reply-To: <20200527133948.GA5011@amd>
On Wed, May 27, 2020 at 7:39 AM Pavel Machek <pavel@ucw.cz> wrote:
>
> Hi!
>
> Thanks for reviews!
>
> > > +additionalProperties: false
> > > +...
> > > diff --git a/drivers/leds/led-core.c b/drivers/leds/led-core.c
> >
> > This isn't a binding file. Belongs in another patch.
>
> These constants are directly related to the binding. It makes sense to
> go in one patch...
Yes, the header does go in this patch, but kernel subsystem files do not.
Part of the reason for separating is we generate a DT only repository
which filters out all the kernel code. Ideally this is just filtering
out commits and the commit messages still make sense.
Rob
^ permalink raw reply
* Re: [PATCH 12/14] clk: sparx5: Add Sparx5 SoC DPLL clock driver
From: Lars Povlsen @ 2020-05-27 14:29 UTC (permalink / raw)
To: Stephen Boyd
Cc: Arnd Bergmann, Linus Walleij, SoC Team, Lars Povlsen,
Steen Hegelund, Microchip Linux Driver Support, Olof Johansson,
Michael Turquette, devicetree, linux-clk, linux-gpio,
linux-arm-kernel, linux-kernel, Alexandre Belloni
In-Reply-To: <159054818459.88029.10644772284176356883@swboyd.mtv.corp.google.com>
Stephen Boyd writes:
> Quoting Lars Povlsen (2020-05-13 05:55:30)
>> diff --git a/drivers/clk/clk-sparx5.c b/drivers/clk/clk-sparx5.c
>> new file mode 100644
>> index 0000000000000..685b3028a7071
>> --- /dev/null
>> +++ b/drivers/clk/clk-sparx5.c
>> @@ -0,0 +1,269 @@
>> +// SPDX-License-Identifier: GPL-2.0-or-later
>> +/*
>> + * Microchip Sparx5 SoC Clock driver.
>> + *
>> + * Copyright (c) 2019 Microchip Inc.
>> + *
>> + * Author: Lars Povlsen <lars.povlsen@microchip.com>
>> + */
>> +
>> +#include <linux/io.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/of.h>
>> +#include <linux/of_address.h>
>> +#include <linux/slab.h>
>> +#include <linux/platform_device.h>
>> +#include <dt-bindings/clock/microchip,sparx5.h>
>> +
>> +#define PLL_DIV_MASK GENMASK(7, 0)
>> +#define PLL_PRE_DIV_MASK GENMASK(10, 8)
>> +#define PLL_PRE_DIV_SHIFT 8
>> +#define PLL_ROT_DIR BIT(11)
>> +#define PLL_ROT_SEL_MASK GENMASK(13, 12)
>> +#define PLL_ROT_SEL_SHIFT 12
>> +#define PLL_ROT_ENA BIT(14)
>> +#define PLL_CLK_ENA BIT(15)
>> +
>> +#define MAX_SEL 4
>> +#define MAX_PRE BIT(3)
>> +
>> +#define KHZ 1000
>> +#define MHZ (KHZ*KHZ)
>
> I suspect (1000 * KHZ) would make more sense.
>
Fine.
>> +
>> +#define BASE_CLOCK (2500UL*MHZ)
>> +
>> +static u8 sel_rates[MAX_SEL] = { 0, 2*8, 2*4, 2*2 };
>
> const?
>
Yes, sure.
>> +
>> +static const char *clk_names[N_CLOCKS] = {
>> + "core", "ddr", "cpu2", "arm2",
>> + "aux1", "aux2", "aux3", "aux4",
>> + "synce",
>> +};
>> +
>> +struct s5_hw_clk {
>> + struct clk_hw hw;
>> + void __iomem *reg;
>> + int index;
>> +};
>> +
>> +struct s5_clk_data {
>> + void __iomem *base;
>> + struct s5_hw_clk s5_hw[N_CLOCKS];
>> +};
>> +
>> +struct pll_conf {
>> + int freq;
>> + u8 div;
>> + bool rot_ena;
>> + u8 rot_sel;
>> + u8 rot_dir;
>> + u8 pre_div;
>> +};
>> +
>> +#define to_clk_pll(hw) container_of(hw, struct s5_hw_clk, hw)
>> +
>> +unsigned long calc_freq(const struct pll_conf *pdata)
>> +{
>> + unsigned long rate = BASE_CLOCK / pdata->div;
>> +
>> + if (pdata->rot_ena) {
>> + unsigned long base = BASE_CLOCK / pdata->div;
>> + int sign = pdata->rot_dir ? -1 : 1;
>> + int divt = sel_rates[pdata->rot_sel] * (1 + pdata->pre_div);
>> + int divb = divt + sign;
>> +
>> + rate = mult_frac(base, divt, divb);
>> + rate = roundup(rate, 1000);
>> + }
>> +
>> + return rate;
>> +}
>> +
>> +static unsigned long clk_calc_params(unsigned long rate,
>> + struct pll_conf *conf)
>> +{
>> + memset(conf, 0, sizeof(*conf));
>> +
>> + conf->div = DIV_ROUND_CLOSEST_ULL(BASE_CLOCK, rate);
>> +
>> + if (BASE_CLOCK % rate) {
>> + struct pll_conf best;
>> + ulong cur_offset, best_offset = rate;
>> + int i, j;
>> +
>> + /* Enable fractional rotation */
>> + conf->rot_ena = true;
>> +
>> + if ((BASE_CLOCK / rate) != conf->div) {
>> + /* Overshoot, adjust other direction */
>> + conf->rot_dir = 1;
>> + }
>> +
>> + /* Brute force search over MAX_PRE * (MAX_SEL - 1) = 24 */
>> + for (i = 0; i < MAX_PRE; i++) {
>> + conf->pre_div = i;
>> + for (j = 1; j < MAX_SEL; j++) {
>> + conf->rot_sel = j;
>> + conf->freq = calc_freq(conf);
>> + cur_offset = abs(rate - conf->freq);
>> + if (cur_offset == 0)
>> + /* Perfect fit */
>> + goto done;
>
> Why not 'break' and drop the label?
>
Its a dual loop. Anyway, I changed it to add "best_offset > 0" in the
loop guards and drop "cur_offset == 0" as a special case, so no goto.
>> + if (cur_offset < best_offset) {
>> + /* Better fit found */
>> + best_offset = cur_offset;
>> + best = *conf;
>> + }
>> + }
>> + }
>> + /* Best match */
>> + *conf = best;
>> + }
>> +
>> +done:
>> + return conf->freq;
>> +}
>> +
>> +static int clk_pll_enable(struct clk_hw *hw)
>> +{
>> + struct s5_hw_clk *pll = to_clk_pll(hw);
>> + u32 val = readl(pll->reg);
>> +
>> + val |= PLL_CLK_ENA;
>> + writel(val, pll->reg);
>> + pr_debug("%s: Enable val %04x\n", clk_names[pll->index], val);
>> + return 0;
>> +}
>> +
>> +static void clk_pll_disable(struct clk_hw *hw)
>> +{
>> + struct s5_hw_clk *pll = to_clk_pll(hw);
>> + u32 val = readl(pll->reg);
>> +
>> + val &= ~PLL_CLK_ENA;
>> + writel(val, pll->reg);
>> + pr_debug("%s: Disable val %04x\n", clk_names[pll->index], val);
>
> Can we drop these pr_debug() prints? They're probably never going to be
> used after developing this driver.
>
>> +}
>> +
>> +static int clk_pll_set_rate(struct clk_hw *hw,
>
> Please rename clk_pll to something less generic, like s5_pll or
> something.
>
Yeah, I see that. I changed all generic symbols to use s5_ prefix where
applicable. Also fixed non-static calc_freq() symbol.
>> + unsigned long rate,
>> + unsigned long parent_rate)
>> +{
>> + struct s5_hw_clk *pll = to_clk_pll(hw);
>> + struct pll_conf conf;
>> + unsigned long eff_rate;
>> + int ret = 0;
>> +
>> + eff_rate = clk_calc_params(rate, &conf);
>> + if (eff_rate == rate) {
>> + u32 val;
>> +
>> + val = readl(pll->reg) & PLL_CLK_ENA;
>> + val |= PLL_DIV_MASK & conf.div;
>> + if (conf.rot_ena) {
>> + val |= (PLL_ROT_ENA |
>> + (PLL_ROT_SEL_MASK &
>> + (conf.rot_sel << PLL_ROT_SEL_SHIFT)) |
>> + (PLL_PRE_DIV_MASK &
>> + (conf.pre_div << PLL_PRE_DIV_SHIFT)));
>
> This can use the FIELD_GET and helpers?
>
Yes, makes sense. Done.
>> + if (conf.rot_dir)
>> + val |= PLL_ROT_DIR;
>> + }
>> + pr_debug("%s: Rate %ld >= 0x%04x\n",
>> + clk_names[pll->index], rate, val);
>> + writel(val, pll->reg);
>> + } else {
>> + pr_err("%s: freq unsupported: %ld paren %ld\n",
>> + clk_names[pll->index], rate, parent_rate);
>> + ret = -ENOTSUPP;
>
> I'd prefer we short circuit the function
>
> eff_rate = clk_calc_params(...);
> if (eff_rate != rate)
> return -ENOTSUPP;
>
> do the other things...
>
> This avoids lots of indentation.
Ok, noted.
>
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
>> + unsigned long parent_rate)
>> +{
>> + /* Don't care */
>
> What does this mean? recalc_rate is supposed to tell us what rate has
> been achieved for this clk.
I added a proper implementation for this.
>
>> + return 0;
>> +}
>> +
>> +static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
>> + unsigned long *parent_rate)
>> +{
>> + struct pll_conf conf;
>> + unsigned long eff_rate;
>> +
>> + eff_rate = clk_calc_params(rate, &conf);
>> + pr_debug("%s: Rate %ld rounded to %ld\n", __func__, rate, eff_rate);
>> +
>> + return eff_rate;
>> +}
>> +
>> +static const struct clk_ops s5_pll_ops = {
>> + .enable = clk_pll_enable,
>> + .disable = clk_pll_disable,
>> + .set_rate = clk_pll_set_rate,
>> + .round_rate = clk_pll_round_rate,
>> + .recalc_rate = clk_pll_recalc_rate,
>> +};
>> +
>> +static struct s5_clk_data *s5_clk_alloc(struct device_node *np)
>> +{
>> + struct s5_clk_data *clk_data;
>> +
>> + clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
>> + if (WARN_ON(!clk_data))
>
> Drop the WARN_ON(), kzalloc() already prints a big stacktrace when it
> fails.
Yes.
>
>> + return NULL;
>> +
>> + clk_data->base = of_iomap(np, 0);
>> + if (WARN_ON(!clk_data->base))
>> + return NULL;
>> +
>> + return clk_data;
>
> Just inline this function at the callsite please.
>
Yes.
>> +}
>> +
>> +static struct clk_hw *s5_clk_hw_get(struct of_phandle_args *clkspec, void *data)
>> +{
>> + struct s5_clk_data *pll_clk = data;
>> + unsigned int idx = clkspec->args[0];
>> +
>> + if (idx >= N_CLOCKS) {
>> + pr_err("%s: invalid index %u\n", __func__, idx);
>> + return ERR_PTR(-EINVAL);
>> + }
>> +
>> + return &pll_clk->s5_hw[idx].hw;
>> +}
>> +
>> +static void __init s5_pll_init(struct device_node *np)
>> +{
>> + int i, ret;
>> + struct s5_clk_data *pll_clk;
>> + struct clk_init_data init = { 0 };
>
> Just do init = { } so that 0 doesn't trip up sparse.
I'm not sure what you mean by "trip up sparse", but its changed now.
>
>> +
>> + pll_clk = s5_clk_alloc(np);
>> + if (!pll_clk)
>> + return;
>> +
>> + init.ops = &s5_pll_ops;
>> + init.parent_names = NULL;
>> + init.num_parents = 0;
>
> Drop these last two lines if there aren't any parents.
>
OK.
>> +
>> + for (i = 0; i < N_CLOCKS; i++) {
>> + struct s5_hw_clk *s5_hw = &pll_clk->s5_hw[i];
>> +
>> + init.name = clk_names[i];
>> + s5_hw->index = i;
>> + s5_hw->reg = pll_clk->base + (i * sizeof(u32));
>> + s5_hw->hw.init = &init;
>> + ret = of_clk_hw_register(np, &s5_hw->hw);
>> + if (ret) {
>> + pr_err("failed to register %s clock\n", init.name);
>> + return;
>> + }
>> + }
>> +
>> + of_clk_add_hw_provider(np, s5_clk_hw_get, pll_clk);
>> +}
>> +CLK_OF_DECLARE_DRIVER(microchip_s5, "microchip,sparx5-dpll", s5_pll_init);
>
> Why DECLARE_DRIVER? Please add a comment indicating the other driver
> that is supposed to probe against this node. And is there any reason
> this can't be a platform driver? That is preferred over
> CLK_OF_DECLARE*() usage.
I will change it to a platform driver.
Thank you very much for your comments, they are highly appreciated.
---Lars
--
Lars Povlsen,
Microchip
^ permalink raw reply
* Re: [PATCH v4 07/11] i2c: designware: Discard Cherry Trail model flag
From: Serge Semin @ 2020-05-27 14:29 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Serge Semin, Jarkko Nikula, Wolfram Sang, Mika Westerberg,
Alexey Malahov, Thomas Bogendoerfer, Rob Herring, linux-mips,
devicetree, linux-i2c, linux-kernel
In-Reply-To: <20200527134339.GY1634618@smile.fi.intel.com>
On Wed, May 27, 2020 at 04:43:39PM +0300, Andy Shevchenko wrote:
> On Wed, May 27, 2020 at 03:01:07PM +0300, Serge Semin wrote:
> > A PM workaround activated by the flag MODEL_CHERRYTRAIL has been removed
> > since commit 9cbeeca05049 ("i2c: designware: Remove Cherry Trail PMIC I2C
> > bus pm_disabled workaround"), but the flag most likely by mistake has been
> > left in the Dw I2C drivers. Let's remove it.
>
> ...
>
> > -#define MODEL_MSCC_OCELOT 0x00000200
> > +#define MODEL_MSCC_OCELOT 0x00000100
>
> But why?
>
> Does 0x200 work or not? I didn't see this in commit message.
I removed the MODEL_CHERRYTRAIL flag and redefined the only left
MODEL_MSCC_OCELOT flag to set the very first bit allocated for the model
flags. Isn't that obvious?
-Sergey
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
^ permalink raw reply
* Re: [PATCH v4 06/11] i2c: designware: Add Baytrail sem config DW I2C platform dependency
From: Serge Semin @ 2020-05-27 14:24 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Serge Semin, Jarkko Nikula, Wolfram Sang, Alexey Malahov,
Thomas Bogendoerfer, Mika Westerberg, Rob Herring, linux-mips,
devicetree, linux-i2c, linux-kernel
In-Reply-To: <20200527134220.GX1634618@smile.fi.intel.com>
On Wed, May 27, 2020 at 04:42:20PM +0300, Andy Shevchenko wrote:
> On Wed, May 27, 2020 at 03:01:06PM +0300, Serge Semin wrote:
> > Currently Intel Baytrail I2C semaphore is a feature of the DW APB I2C
> > platform driver. It's a bit confusing to see it's config in the menu at
> > some separated place with no reference to the platform code. Let's move the
> > config definition to be below the I2C_DESIGNWARE_PLATFORM config and mark
> > it with "depends on I2C_DESIGNWARE_PLATFORM" statement. By doing so the
> > config menu will display the feature right below the DW I2C platform
> > driver item and will indent it to the right so signifying its belonging.
>
> ...
>
> > config I2C_DESIGNWARE_BAYTRAIL
> > bool "Intel Baytrail I2C semaphore support"
> > depends on ACPI
> > + depends on I2C_DESIGNWARE_PLATFORM
> > depends on (I2C_DESIGNWARE_PLATFORM=m && IOSF_MBI) || \
> > (I2C_DESIGNWARE_PLATFORM=y && IOSF_MBI=y)
>
> I didn't get this. What is broken now with existing dependencies?
With no explicit "depends on I2C_DESIGNWARE_PLATFORM" the entry isn't right
shifted with respect to the I2C_DESIGNWARE_PLATFORM config entry in the kernel
menuconfig. So it looks like a normal no-yes driver without it.
-Sergey
>
> (The move of the PCI part is fine)
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
^ permalink raw reply
* [PATCH v2] check: Add 10bit/slave i2c reg flags support
From: Serge Semin @ 2020-05-27 14:15 UTC (permalink / raw)
To: devicetree-compiler
Cc: Serge Semin, Serge Semin, Alexey Malahov, Thomas Bogendoerfer,
Wolfram Sang, Jarkko Nikula, Andy Shevchenko, Frank Rowand,
Rob Herring, devicetree, linux-i2c, linux-kernel
In-Reply-To: <20200527122525.6929-1-Sergey.Semin@baikalelectronics.ru>
Recently the I2C-controllers slave interface support was added to the
kernel I2C subsystem. In this case Linux can be used as, for example,
a I2C EEPROM machine. See [1] for details. Other than instantiating
the EEPROM-slave device from user-space there is a way to declare the
device in dts. In this case firstly the I2C bus controller must support
the slave interface. Secondly I2C-slave sub-node of that controller
must have "reg"-property with flag I2C_OWN_SLAVE_ADDRESS set (flag is
declared in [2]). That flag is declared as (1 << 30), which when set
makes dtc unhappy about too big address set for a I2C-slave:
Warning (i2c_bus_reg): /example-2/i2c@1120000/eeprom@64: I2C bus unit address format error, expected "40000064"
Warning (i2c_bus_reg): /example-2/i2c@1120000/eeprom@64:reg: I2C address must be less than 10-bits, got "0x40000064"
Similar problem would have happened if we had set the 10-bit address
flag I2C_TEN_BIT_ADDRESS in the "reg"-property.
In order to fix the problem we suggest to alter the I2C-bus reg-check
algorithm, so one would be aware of the upper bits set. Normally if no
flag specified, the 7-bit address is expected in the "reg"-property.
If I2C_TEN_BIT_ADDRESS is set, then the 10-bit address check will be
performed. The I2C_OWN_SLAVE_ADDRESS flag will be just ignored.
[1] kernel/Documentation/i2c/slave-interface.rst
[2] kernel/include/dt-bindings/i2c/i2c.h
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Frank Rowand <frowand.list@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree-compiler@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-i2c@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
Changelog v2:
- Use unsigned numeric literal in the left-shit operation to avoid UB.
---
checks.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/checks.c b/checks.c
index 4b3c486f1399..7091d1bc38d2 100644
--- a/checks.c
+++ b/checks.c
@@ -1028,6 +1028,7 @@ static void check_i2c_bus_reg(struct check *c, struct dt_info *dti, struct node
const char *unitname = get_unitname(node);
char unit_addr[17];
uint32_t reg = 0;
+ uint32_t addr;
int len;
cell_t *cells = NULL;
@@ -1044,17 +1045,21 @@ static void check_i2c_bus_reg(struct check *c, struct dt_info *dti, struct node
}
reg = fdt32_to_cpu(*cells);
- snprintf(unit_addr, sizeof(unit_addr), "%x", reg);
+ addr = reg & 0x3FFFFFFFU;
+ snprintf(unit_addr, sizeof(unit_addr), "%x", addr);
if (!streq(unitname, unit_addr))
FAIL(c, dti, node, "I2C bus unit address format error, expected \"%s\"",
unit_addr);
for (len = prop->val.len; len > 0; len -= 4) {
reg = fdt32_to_cpu(*(cells++));
- if (reg > 0x3ff)
+ addr = reg & 0x3FFFFFFFU;
+ if ((reg & (1U << 31)) && addr > 0x3ff)
FAIL_PROP(c, dti, node, prop, "I2C address must be less than 10-bits, got \"0x%x\"",
- reg);
-
+ addr);
+ else if (!(reg & (1U << 31)) && addr > 0x7f)
+ FAIL_PROP(c, dti, node, prop, "I2C address must be less than 7-bits, got \"0x%x\"",
+ addr);
}
}
WARNING(i2c_bus_reg, check_i2c_bus_reg, NULL, ®_format, &i2c_bus_bridge);
--
2.26.2
^ permalink raw reply related
* Re: [PATCH v10 3/6] dt-bindings: clock: Add X1830 bindings.
From: Zhou Yanjie @ 2020-05-27 14:13 UTC (permalink / raw)
To: Stephen Boyd, linux-clk
Cc: linux-kernel, devicetree, mturquette, robh+dt, dongsheng.qiu,
aric.pzqi, sernia.zhou, zhenwenjin, paul
In-Reply-To: <159056716225.88029.7227987261941853085@swboyd.mtv.corp.google.com>
Hi Stephen,
I may have misunderstood what you meant (I did not notice that you have
taken other v10 patches, so I sent the entire v11 series by mistake), do
I need to resend the split bindings patches separately again?
Thanks and best regards!
在 2020/5/27 下午4:12, Stephen Boyd 写道:
> Quoting 周琰杰 (Zhou Yanjie) (2020-05-26 07:40:41)
>> Add the clock bindings for the X1830 Soc from Ingenic.
>>
>> Signed-off-by: \u5468\u7430\u6770 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> ---
>>
>> Notes:
>> v2->v3:
>> Adjust order from [3/5] in v2 to [4/5] in v3.
>>
>> v3->v4:
>> Adjust order from [4/5] in v3 to [3/4] in v4.
>>
>> v4->v5:
>> Rebase on top of kernel 5.6-rc1.
>>
>> v5->v6:
>> Add missing part of X1830's CGU.
>>
>> v6->v7:
>> No change.
>>
>> v7->v8:
>> Rebase on top of linux-next.
>>
>> v8->v9:
>> No change.
>>
>> v9->v10:
>> Add missing "X1830_CLK_TCU".
>>
>> .../devicetree/bindings/clock/ingenic,cgu.yaml | 2 +
>> include/dt-bindings/clock/x1830-cgu.h | 55 ++++++++++++++++++++++
>> 2 files changed, 57 insertions(+)
>> create mode 100644 include/dt-bindings/clock/x1830-cgu.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml
> This file is in Rob's DT tree staged for the next release, not in the
> clk tree. Can you split this patch into two, one for the compatible
> update and another for the header file update and send again? Then Rob
> can pick up the yaml file change and I can pick up the header file
> change.
>
>> index 0281cd1d7e1b..a952d5811823 100644
>> --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml
>> +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml
>> @@ -25,6 +25,7 @@ select:
>> - ingenic,jz4770-cgu
>> - ingenic,jz4780-cgu
>> - ingenic,x1000-cgu
>> + - ingenic,x1830-cgu
>> required:
>> - compatible
>>
>> @@ -51,6 +52,7 @@ properties:
>> - ingenic,jz4770-cgu
>> - ingenic,jz4780-cgu
>> - ingenic,x1000-cgu
>> + - ingenic,x1830-cgu
>> - const: simple-mfd
>> minItems: 1
>>
^ permalink raw reply
* RE: [PATCH v13 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem
From: Vishal Sagar @ 2020-05-27 14:13 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Hyun Kwon, mchehab@kernel.org, robh+dt@kernel.org,
mark.rutland@arm.com, Michal Simek, linux-media@vger.kernel.org,
devicetree@vger.kernel.org, hans.verkuil@cisco.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Dinesh Kumar, Sandip Kothari,
Luca Ceresoli, Jacopo Mondi, Rob Herring
In-Reply-To: <20200527132344.GC6171@pendragon.ideasonboard.com>
Hi Laurent,
> -----Original Message-----
> From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Sent: Wednesday, May 27, 2020 6:54 PM
> To: Vishal Sagar <vsagar@xilinx.com>
> Cc: Hyun Kwon <hyunk@xilinx.com>; mchehab@kernel.org;
> robh+dt@kernel.org; mark.rutland@arm.com; Michal Simek
> <michals@xilinx.com>; linux-media@vger.kernel.org;
> devicetree@vger.kernel.org; hans.verkuil@cisco.com; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Dinesh Kumar
> <dineshk@xilinx.com>; Sandip Kothari <sandipk@xilinx.com>; Luca Ceresoli
> <luca@lucaceresoli.net>; Jacopo Mondi <jacopo@jmondi.org>; Rob Herring
> <robh@kernel.org>
> Subject: Re: [PATCH v13 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI
> CSI-2 Rx Subsystem
>
> Hi Vishal,
>
> On Wed, May 27, 2020 at 11:53:01AM +0000, Vishal Sagar wrote:
> > On Sunday, May 24, 2020 7:32 AM, Laurent Pinchart wrote:
> > > On Tue, May 12, 2020 at 08:49:46PM +0530, Vishal Sagar wrote:
> > > > Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.
> > > >
> > > > The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx
> > > > controller, a D-PHY in Rx mode and a Video Format Bridge.
> > > >
> > > > Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
> > > > Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
> > > > Reviewed-by: Rob Herring <robh@kernel.org>
> > > > Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
> > > > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > > > ---
> > > > v13
> > > > - Based on Laurent's suggestions
> > > > - Fixed the datatypes values as minimum and maximum
> > > > - condition added for en-vcx property
> > > >
> > > > v12
> > > > - Moved to yaml format
> > > > - Update CSI-2 and D-PHY
> > > > - Mention that bindings for D-PHY not here
> > > > - reset -> video-reset
> > > >
> > > > v11
> > > > - Modify compatible string from 4.0 to 5.0
> > > >
> > > > v10
> > > > - No changes
> > > >
> > > > v9
> > > > - Fix xlnx,vfb description.
> > > > - s/Optional/Required endpoint property.
> > > > - Move data-lanes description from Ports to endpoint property section.
> > > >
> > > > v8
> > > > - Added reset-gpios optional property to assert video_aresetn
> > > >
> > > > v7
> > > > - Removed the control name from dt bindings
> > > > - Updated the example dt node name to csi2rx
> > > >
> > > > v6
> > > > - Added "control" after V4L2_CID_XILINX_MIPICSISS_ACT_LANES as
> > > > suggested by Luca
> > > > - Added reviewed by Rob Herring
> > > >
> > > > v5
> > > > - Incorporated comments by Luca Cersoli
> > > > - Removed DPHY clock from description and example
> > > > - Removed bayer pattern from device tree MIPI CSI IP
> > > > doesn't deal with bayer pattern.
> > > >
> > > > v4
> > > > - Added reviewed by Hyun Kwon
> > > >
> > > > v3
> > > > - removed interrupt parent as suggested by Rob
> > > > - removed dphy clock
> > > > - moved vfb to optional properties
> > > > - Added required and optional port properties section
> > > > - Added endpoint property section
> > > >
> > > > v2
> > > > - updated the compatible string to latest version supported
> > > > - removed DPHY related parameters
> > > > - added CSI v2.0 related property (including VCX for supporting upto 16
> > > > virtual channels).
> > > > - modified csi-pxl-format from string to unsigned int type where the value
> > > > is as per the CSI specification
> > > > - Defined port 0 and port 1 as sink and source ports.
> > > > - Removed max-lanes property as suggested by Rob and Sakari
> > > > .../bindings/media/xilinx/xlnx,csi2rxss.yaml | 226
> > > > ++++++++++++++++++
> > > > 1 file changed, 226 insertions(+) create mode 100644
> > > > Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
> > > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yam
> > > > l
> > > > b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yam
> > > > l
> > > > new file mode 100644
> > > > index 000000000000..b0885f461785
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss
> > > > +++ .yam
> > > > +++ l
> > > > @@ -0,0 +1,226 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> > > > +1.2
> > > > +---
> > > > +$id:
> > > > +http://devicetree.org/schemas/media/xilinx/xlnx,csi2rxss.yaml#
> > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > +
> > > > +title: Xilinx MIPI CSI-2 Receiver Subsystem
> > > > +
> > > > +maintainers:
> > > > + - Vishal Sagar <vishal.sagar@xilinx.com>
> > > > +
> > > > +description: |
> > > > + The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture
> > > > +MIPI
> > > > +CSI-2
> > > > + traffic from compliant camera sensors and send the output as
> > > > +AXI4 Stream
> > > > + video data for image processing.
> > > > + The subsystem consists of a MIPI D-PHY in slave mode which
> > > > +captures the
> > > > + data packets. This is passed along the MIPI CSI-2 Rx IP which
> > > > +extracts the
> > > > + packet data. The optional Video Format Bridge (VFB) converts
> > > > +this data to
> > > > + AXI4 Stream video data.
> > > > + For more details, please refer to PG232 Xilinx MIPI CSI-2
> > > > +Receiver
> > > Subsystem.
> > > > + Please note that this bindings includes only the MIPI CSI-2 Rx
> > > > +controller
> > > > + and Video Format Bridge and not D-PHY.
> > > > +
> > > > +properties:
> > > > + compatible:
> > > > + items:
> > > > + - enum:
> > > > + - xlnx,mipi-csi2-rx-subsystem-5.0
> > > > +
> > > > + reg:
> > > > + maxItems: 1
> > > > +
> > > > + interrupts:
> > > > + maxItems: 1
> > > > +
> > > > + clocks:
> > > > + description: List of clock specifiers
> > > > + items:
> > > > + - description: AXI Lite clock
> > > > + - description: Video clock
> > > > +
> > > > + clock-names:
> > > > + items:
> > > > + - const: lite_aclk
> > > > + - const: video_aclk
> > > > +
> > > > + xlnx,csi-pxl-format:
> > > > + description: |
> > > > + This denotes the CSI Data type selected in hw design.
> > > > + Packets other than this data type (except for RAW8 and
> > > > + User defined data types) will be filtered out.
> > > > + Possible values are as below -
> > > > + 0x1e - YUV4228B
> > > > + 0x1f - YUV42210B
> > > > + 0x20 - RGB444
> > > > + 0x21 - RGB555
> > > > + 0x22 - RGB565
> > > > + 0x23 - RGB666
> > > > + 0x24 - RGB888
> > > > + 0x28 - RAW6
> > > > + 0x29 - RAW7
> > > > + 0x2a - RAW8
> > > > + 0x2b - RAW10
> > > > + 0x2c - RAW12
> > > > + 0x2d - RAW14
> > > > + 0x2e - RAW16
> > > > + 0x2f - RAW20
> > > > + allOf:
> > > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > > + - anyOf:
> > > > + - minimum: 0x1e
> > > > + - maximum: 0x24
> > > > + - minimum: 0x28
> > > > + - maximum: 0x2f
> > > > +
> > > > + xlnx,vfb:
> > > > + type: boolean
> > > > + description: Present when Video Format Bridge is enabled in
> > > > + IP configuration
> > > > +
> > > > + xlnx,en-csi-v2-0:
> > > > + type: boolean
> > > > + description: Present if CSI v2 is enabled in IP configuration.
> > > > +
> > > > + xlnx,en-vcx:
> > > > + type: boolean
> > > > + description: |
> > > > + When present, there are maximum 16 virtual channels, else only 4.
> > > > +
> > > > + xlnx,en-active-lanes:
> > > > + type: boolean
> > > > + description: |
> > > > + Present if the number of active lanes can be re-configured at
> > > > + runtime in the Protocol Configuration Register. Otherwise all lanes,
> > > > + as set in IP configuration, are always active.
> > > > +
> > > > + video-reset-gpios:
> > > > + description: Optional specifier for a GPIO that asserts video_aresetn.
> > > > + maxItems: 1
> > > > +
> > > > + ports:
> > > > + type: object
> > > > +
> > > > + properties:
> > > > + port@0:
> > > > + type: object
> > > > + description: |
> > > > + Input / sink port node, single endpoint describing the
> > > > + CSI-2 transmitter.
> > > > +
> > > > + properties:
> > > > + reg:
> > > > + const: 0
> > > > +
> > > > + endpoint:
> > > > + type: object
> > > > +
> > > > + properties:
> > > > +
> > > > + data-lanes:
> > > > + description: |
> > > > + This is required only in the sink port 0 endpoint which
> > > > + connects to MIPI CSI-2 source like sensor.
> > > > + The possible values are -
> > > > + 1 - For 1 lane enabled in IP.
> > > > + 1 2 - For 2 lanes enabled in IP.
> > > > + 1 2 3 - For 3 lanes enabled in IP.
> > > > + 1 2 3 4 - For 4 lanes enabled in IP.
> > > > + items:
> > > > + - const: 1
> > > > + - const: 2
> > > > + - const: 3
> > > > + - const: 4
> > > > +
> > > > + remote-endpoint: true
> > > > +
> > > > + required:
> > > > + - data-lanes
> > > > + - remote-endpoint
> > > > +
> > > > + additionalProperties: false
> > > > +
> > > > + additionalProperties: false
> > > > +
> > > > + port@1:
> > > > + type: object
> > > > + description: |
> > > > + Output / source port node, endpoint describing modules
> > > > + connected the CSI-2 receiver.
> > > > +
> > > > + properties:
> > > > +
> > > > + reg:
> > > > + const: 1
> > > > +
> > > > + endpoint:
> > > > + type: object
> > > > +
> > > > + properties:
> > > > +
> > > > + remote-endpoint: true
> > > > +
> > > > + required:
> > > > + - remote-endpoint
> > > > +
> > > > + additionalProperties: false
> > > > +
> > > > + additionalProperties: false
> > > > +
> > > > +required:
> > > > + - compatible
> > > > + - reg
> > > > + - interrupts
> > > > + - clocks
> > > > + - clock-names
> > > > + - xlnx,csi-pxl-format
> > > > + - ports
> > > > +
> > > > +if:
> > > > + not:
> > > > + required:
> > > > + - xlnx,en-csi-v2-0
> > > > +then:
> > > > + properties:
> > > > + xlnx,en-vcx: false
> > >
> > > As I've just commented on v12, I think we should condition the
> > > xlnx,csi-pxl- format property to xlnx,vfb being set.
> > > xlnx,csi-pxl-format should be removed from the required properties above,
> and the following conditions added:
> > >
> > > allOf:
> > > - if:
> > > required:
> > > - xlnx,vfb
> > > then:
> > > required:
> > > - xlnx,csi-pxl-format
> > > else:
> > > properties:
> > > xlnx,csi-pxl-format: false
> > >
> > > - if:
> > > not:
> > > required:
> > > - xlnx,en-csi-v2-0
> > > then:
> > > properties:
> > > xlnx,en-vcx: false
> > >
> > > The 'allOf' is needed as you can't have two 'if' constructs at the top level.
> > >
> > Thanks for sharing the explanation for this.
> > Can you please share where I can get this info?
>
> The json-schema specification is available at https://json-
> schema.org/specification.html. allOf is defined in https://json-
> schema.org/draft/2019-09/json-schema-core.html#allOf.
>
> JSON schemas are expressed in JSON format, and YAML is a (more readable)
> superset syntax of JSON. A YAML document contains lists and objects:
>
> - this
> - is
> - a
> - list
>
> object:
> can: have
> properties:
> that: can
> be: other
> objects
>
> An object is similar to a Python dictionary, it can't have multiple entries with
> the same key. So having
>
> if:
> required:
> - xlnx,vfb
> then:
> required:
> - xlnx,csi-pxl-format
> else:
> properties:
> xlnx,csi-pxl-format: false
>
> if:
> not:
> required:
> - xlnx,en-csi-v2-0
> then:
> properties:
> xlnx,en-vcx: false
>
> at the top level is not valid, the same way that
>
> properties:
> reg:
> maxItems: 1
> reg:
> maxItems: 1
>
> wouldn't be valid. The allOf object has a value that is a list of
> schemas:
>
> allOf:
> - schema1
> - schema2
> - schema3
>
> and in this case, we use it with a if...then...else for each of the schemas. As
> documented in the spec, "An instance validates successfully against [allOf] if it
> validates successfully against all schemas defined by [allOf]'s value".
>
> allOf is also used to include sub-schemas, as explained in
> Documentation/devicetree/bindings/example-schema.yaml.
>
> vendor,int-property:
> description: Vendor specific properties must have a description
> # 'allOf' is the json-schema way of subclassing a schema. Here the base
> # type schema is referenced and then additional constraints on the values
> # are added.
> allOf:
> - $ref: /schemas/types.yaml#/definitions/uint32
> - enum: [2, 4, 6, 8, 10]
>
> If this was written
>
> vendor,int-property:
> $ref: /schemas/types.yaml#/definitions/uint32
> enum: [2, 4, 6, 8, 10]
>
> we would have an issue (among other problems) if
> /schemas/types.yaml#/definitions/uint32 contained an enum, as there would
> be two enum properties for vendor,int-property.
>
Thanks for the detailed explanation Laurent!
> > > Please however let me know if my understanding is wrong and
> > > xlnx,csi-pxl- format is needed even when xlnx,vfb is not set. In
> > > that case please ignore this change (but please add the ... below).
> >
> > Ok. I will add ... in the end.
> >
> > > > +
> > > > +additionalProperties: false
> > > > +
> > > > +examples:
> > > > + - |
> > > > + #include <dt-bindings/gpio/gpio.h>
> > > > + xcsi2rxss_1: csi2rx@a0020000 {
> > > > + compatible = "xlnx,mipi-csi2-rx-subsystem-5.0";
> > > > + reg = <0x0 0xa0020000 0x0 0x10000>;
> > > > + interrupt-parent = <&gic>;
> > > > + interrupts = <0 95 4>;
> > > > + xlnx,csi-pxl-format = <0x2a>;
> > > > + xlnx,vfb;
> > > > + xlnx,en-active-lanes;
> > > > + xlnx,en-csi-v2-0;
> > > > + xlnx,en-vcx;
> > > > + clock-names = "lite_aclk", "video_aclk";
> > > > + clocks = <&misc_clk_0>, <&misc_clk_1>;
> > > > + video-reset-gpios = <&gpio 86 GPIO_ACTIVE_LOW>;
> > > > +
> > > > + ports {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > +
> > > > + port@0 {
> > > > + /* Sink port */
> > > > + reg = <0>;
> > > > + csiss_in: endpoint {
> > > > + data-lanes = <1 2 3 4>;
> > > > + /* MIPI CSI-2 Camera handle */
> > > > + remote-endpoint = <&camera_out>;
> > > > + };
> > > > + };
> > > > + port@1 {
> > > > + /* Source port */
> > > > + reg = <1>;
> > > > + csiss_out: endpoint {
> > > > + remote-endpoint = <&vproc_in>;
> > > > + };
> > > > + };
> > > > + };
> > > > + };
> > >
> > > YAML files usually end with
> > >
> > > ...
> > >
> > > on the last line to mark the end of file.
> > >
> >
> > Ok I will add this to the end of the file.
> >
> > > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
>
> --
> Regards,
>
> Laurent Pinchart
Regards
Vishal Sagar
^ permalink raw reply
* Re: [RESEND v5 01/21] mtd: Fix typo in mtd_ooblayout_set_databytes() description
From: Miquel Raynal @ 2020-05-27 14:11 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Tudor Ambarus, linux-mtd
Cc: Mark Rutland, devicetree, Rob Herring, Boris Brezillon
In-Reply-To: <20200526195633.11543-2-miquel.raynal@bootlin.com>
On Tue, 2020-05-26 at 19:56:13 UTC, Miquel Raynal wrote:
> Fix a probable copy/paste error: the function works like
> mtd_ooblayout_set_bytes(), not *_get_bytes().
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next.
Miquel
^ permalink raw reply
* Re: [RESEND v5 02/21] mtd: rawnand: Avoid a typedef
From: Miquel Raynal @ 2020-05-27 14:11 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Tudor Ambarus, linux-mtd
Cc: Mark Rutland, devicetree, Rob Herring, Boris Brezillon
In-Reply-To: <20200526195633.11543-3-miquel.raynal@bootlin.com>
On Tue, 2020-05-26 at 19:56:14 UTC, Miquel Raynal wrote:
> In new code, the use of typedef is discouraged. Turn this one in the
> raw NAND core into a regular enumeration.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next.
Miquel
^ permalink raw reply
* Re: [RESEND v5 03/21] mtd: rawnand: Drop OOB_FIRST placement scheme
From: Miquel Raynal @ 2020-05-27 14:11 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Tudor Ambarus, linux-mtd
Cc: Mark Rutland, devicetree, Rob Herring, Boris Brezillon
In-Reply-To: <20200526195633.11543-4-miquel.raynal@bootlin.com>
On Tue, 2020-05-26 at 19:56:15 UTC, Miquel Raynal wrote:
> This scheme has been introduced for the Davinci controller and means
> that the OOB area must be read *before* the rest of the data. This has
> nothing to do with the ECC in OOB placement as it could be understood
> and most importantly, there is no point in having this function out of
> the Davinci NAND controller driver. A DT property for this scheme has
> been added but never used, even by the Davinci driver which only uses
> this scheme to change the default nand_read_page().
>
> Move the main read_page() helper into the Davinci driver and remove
> the remaining boilerplate.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next.
Miquel
^ permalink raw reply
* Re: [RESEND v5 04/21] dt-bindings: mtd: Deprecate OOB_FIRST mode
From: Miquel Raynal @ 2020-05-27 14:11 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Tudor Ambarus, linux-mtd
Cc: Mark Rutland, devicetree, Rob Herring, Boris Brezillon
In-Reply-To: <20200526195633.11543-5-miquel.raynal@bootlin.com>
On Tue, 2020-05-26 at 19:56:16 UTC, Miquel Raynal wrote:
> This mode has never actually been used, it was introduced for a single
> driver and even this driver did not use it in the DT but only in the
> code. Now that this mode has been removed, let's trim the bindings
> definition to avoid carrying useless properties.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next.
Miquel
^ permalink raw reply
* Re: [RESEND v5 05/21] mtd: rawnand: Return an enum from of_get_nand_ecc_algo()
From: Miquel Raynal @ 2020-05-27 14:11 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Tudor Ambarus, linux-mtd
Cc: Mark Rutland, devicetree, Rob Herring, Boris Brezillon
In-Reply-To: <20200526195633.11543-6-miquel.raynal@bootlin.com>
On Tue, 2020-05-26 at 19:56:17 UTC, Miquel Raynal wrote:
> There is an enumeration to list ECC algorithm, let's use it instead of
> returning an int.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next.
Miquel
^ permalink raw reply
* Re: [RESEND v5 06/21] mtd: rawnand: Add an invalid ECC mode to discriminate with valid ones
From: Miquel Raynal @ 2020-05-27 14:11 UTC (permalink / raw)
To: Miquel Raynal, Richard Weinberger, Vignesh Raghavendra,
Tudor Ambarus, linux-mtd
Cc: Mark Rutland, devicetree, Rob Herring, Boris Brezillon
In-Reply-To: <20200526195633.11543-7-miquel.raynal@bootlin.com>
On Tue, 2020-05-26 at 19:56:18 UTC, Miquel Raynal wrote:
> NAND ECC modes (or providers) have their own enumeration but, unlike
> their algorithms counterpart, there is no invalid or uninitialized
> value to discriminate between an error and having chosen a no-ECC
> situation. Add an "invalid" entry for this purpose.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next.
Miquel
^ permalink raw reply
* Re: [PATCH v4 11/11] i2c: designware: Add Baikal-T1 System I2C support
From: Andy Shevchenko @ 2020-05-27 14:03 UTC (permalink / raw)
To: Serge Semin
Cc: Jarkko Nikula, Wolfram Sang, Mika Westerberg, Serge Semin,
Alexey Malahov, Thomas Bogendoerfer, Rob Herring, linux-mips,
devicetree, linux-i2c, linux-kernel
In-Reply-To: <20200527120111.5781-12-Sergey.Semin@baikalelectronics.ru>
On Wed, May 27, 2020 at 03:01:11PM +0300, Serge Semin wrote:
> Baikal-T1 System Controller is equipped with a dedicated I2C Controller
> which functionality is based on the DW APB I2C IP-core, the only
> difference in a way it' registers are accessed. There are three access
> register provided in the System Controller registers map, which indirectly
> address the normal DW APB I2C registers space. So in order to have the
> Baikal-T1 System I2C Controller supported by the common DW APB I2C driver
> we created a dedicated Dw I2C controller model quirk, which retrieves the
> syscon regmap from the parental dt node and creates a new regmap based on
> it.
Yes, you see how cool it is now! FWIW,
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
>
> ---
>
> Changelog v3:
> - This is a new patch, which has been created due to declining the
> glue-layer approach.
>
> Changelog v4:
> - Use PTR_ERR_OR_ZERO() helper in the bt1_i2c_request_regs() method.
> ---
> drivers/i2c/busses/Kconfig | 3 +-
> drivers/i2c/busses/i2c-designware-core.h | 3 +
> drivers/i2c/busses/i2c-designware-platdrv.c | 78 ++++++++++++++++++++-
> 3 files changed, 81 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> index 259e2325712a..0cf7aea30138 100644
> --- a/drivers/i2c/busses/Kconfig
> +++ b/drivers/i2c/busses/Kconfig
> @@ -541,8 +541,9 @@ config I2C_DESIGNWARE_SLAVE
>
> config I2C_DESIGNWARE_PLATFORM
> tristate "Synopsys DesignWare Platform"
> - select I2C_DESIGNWARE_CORE
> depends on (ACPI && COMMON_CLK) || !ACPI
> + select I2C_DESIGNWARE_CORE
> + select MFD_SYSCON if MIPS_BAIKAL_T1
> help
> If you say yes to this option, support will be included for the
> Synopsys DesignWare I2C adapter.
> diff --git a/drivers/i2c/busses/i2c-designware-core.h b/drivers/i2c/busses/i2c-designware-core.h
> index f5bbe3d6bcf8..556673a1f61b 100644
> --- a/drivers/i2c/busses/i2c-designware-core.h
> +++ b/drivers/i2c/busses/i2c-designware-core.h
> @@ -183,6 +183,7 @@ struct reset_control;
> * struct dw_i2c_dev - private i2c-designware data
> * @dev: driver model device node
> * @map: IO registers map
> + * @sysmap: System controller registers map
> * @base: IO registers pointer
> * @ext: Extended IO registers pointer
> * @cmd_complete: tx completion indicator
> @@ -235,6 +236,7 @@ struct reset_control;
> struct dw_i2c_dev {
> struct device *dev;
> struct regmap *map;
> + struct regmap *sysmap;
> void __iomem *base;
> void __iomem *ext;
> struct completion cmd_complete;
> @@ -290,6 +292,7 @@ struct dw_i2c_dev {
> #define ACCESS_NO_IRQ_SUSPEND 0x00000002
>
> #define MODEL_MSCC_OCELOT 0x00000100
> +#define MODEL_BAIKAL_BT1 0x00000200
> #define MODEL_MASK 0x00000f00
>
> int i2c_dw_init_regmap(struct dw_i2c_dev *dev);
> diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
> index 061c8d506c7c..d9c5337bb22b 100644
> --- a/drivers/i2c/busses/i2c-designware-platdrv.c
> +++ b/drivers/i2c/busses/i2c-designware-platdrv.c
> @@ -18,6 +18,7 @@
> #include <linux/interrupt.h>
> #include <linux/io.h>
> #include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> #include <linux/module.h>
> #include <linux/of.h>
> #include <linux/platform_data/i2c-designware.h>
> @@ -25,6 +26,7 @@
> #include <linux/pm.h>
> #include <linux/pm_runtime.h>
> #include <linux/property.h>
> +#include <linux/regmap.h>
> #include <linux/reset.h>
> #include <linux/sched.h>
> #include <linux/slab.h>
> @@ -58,6 +60,63 @@ MODULE_DEVICE_TABLE(acpi, dw_i2c_acpi_match);
> #endif
>
> #ifdef CONFIG_OF
> +#define BT1_I2C_CTL 0x100
> +#define BT1_I2C_CTL_ADDR_MASK GENMASK(7, 0)
> +#define BT1_I2C_CTL_WR BIT(8)
> +#define BT1_I2C_CTL_GO BIT(31)
> +#define BT1_I2C_DI 0x104
> +#define BT1_I2C_DO 0x108
> +
> +static int bt1_i2c_read(void *context, unsigned int reg, unsigned int *val)
> +{
> + struct dw_i2c_dev *dev = context;
> + int ret;
> +
> + /*
> + * Note these methods shouldn't ever fail because the system controller
> + * registers are memory mapped. We check the return value just in case.
> + */
> + ret = regmap_write(dev->sysmap, BT1_I2C_CTL,
> + BT1_I2C_CTL_GO | (reg & BT1_I2C_CTL_ADDR_MASK));
> + if (ret)
> + return ret;
> +
> + return regmap_read(dev->sysmap, BT1_I2C_DO, val);
> +}
> +
> +static int bt1_i2c_write(void *context, unsigned int reg, unsigned int val)
> +{
> + struct dw_i2c_dev *dev = context;
> + int ret;
> +
> + ret = regmap_write(dev->sysmap, BT1_I2C_DI, val);
> + if (ret)
> + return ret;
> +
> + return regmap_write(dev->sysmap, BT1_I2C_CTL,
> + BT1_I2C_CTL_GO | BT1_I2C_CTL_WR | (reg & BT1_I2C_CTL_ADDR_MASK));
> +}
> +
> +static struct regmap_config bt1_i2c_cfg = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = 4,
> + .fast_io = true,
> + .reg_read = bt1_i2c_read,
> + .reg_write = bt1_i2c_write,
> + .max_register = DW_IC_COMP_TYPE
> +};
> +
> +static int bt1_i2c_request_regs(struct dw_i2c_dev *dev)
> +{
> + dev->sysmap = syscon_node_to_regmap(dev->dev->of_node->parent);
> + if (IS_ERR(dev->sysmap))
> + return PTR_ERR(dev->sysmap);
> +
> + dev->map = devm_regmap_init(dev->dev, NULL, dev, &bt1_i2c_cfg);
> + return PTR_ERR_OR_ZERO(dev->map);
> +}
> +
> #define MSCC_ICPU_CFG_TWI_DELAY 0x0
> #define MSCC_ICPU_CFG_TWI_DELAY_ENABLE BIT(0)
> #define MSCC_ICPU_CFG_TWI_SPIKE_FILTER 0x4
> @@ -90,10 +149,16 @@ static int dw_i2c_of_configure(struct platform_device *pdev)
> static const struct of_device_id dw_i2c_of_match[] = {
> { .compatible = "snps,designware-i2c", },
> { .compatible = "mscc,ocelot-i2c", .data = (void *)MODEL_MSCC_OCELOT },
> + { .compatible = "baikal,bt1-sys-i2c", .data = (void *)MODEL_BAIKAL_BT1 },
> {},
> };
> MODULE_DEVICE_TABLE(of, dw_i2c_of_match);
> #else
> +static int bt1_i2c_request_regs(struct dw_i2c_dev *dev)
> +{
> + return -ENODEV;
> +}
> +
> static inline int dw_i2c_of_configure(struct platform_device *pdev)
> {
> return -ENODEV;
> @@ -111,10 +176,19 @@ static void dw_i2c_plat_pm_cleanup(struct dw_i2c_dev *dev)
> static int dw_i2c_plat_request_regs(struct dw_i2c_dev *dev)
> {
> struct platform_device *pdev = to_platform_device(dev->dev);
> + int ret;
>
> - dev->base = devm_platform_ioremap_resource(pdev, 0);
> + switch (dev->flags & MODEL_MASK) {
> + case MODEL_BAIKAL_BT1:
> + ret = bt1_i2c_request_regs(dev);
> + break;
> + default:
> + dev->base = devm_platform_ioremap_resource(pdev, 0);
> + ret = PTR_ERR_OR_ZERO(dev->base);
> + break;
> + }
>
> - return PTR_ERR_OR_ZERO(dev->base);
> + return ret;
> }
>
> static int dw_i2c_plat_probe(struct platform_device *pdev)
> --
> 2.26.2
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH] check: Add 10bit/slave i2c reg flags support
From: Serge Semin @ 2020-05-27 14:00 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Serge Semin, devicetree-compiler, Alexey Malahov,
Thomas Bogendoerfer, Wolfram Sang, Jarkko Nikula, Frank Rowand,
Rob Herring, devicetree, linux-i2c, linux-kernel
In-Reply-To: <20200527133656.GV1634618@smile.fi.intel.com>
On Wed, May 27, 2020 at 04:36:56PM +0300, Andy Shevchenko wrote:
> On Wed, May 27, 2020 at 03:25:25PM +0300, Serge Semin wrote:
> > Recently the I2C-controllers slave interface support was added to the
> > kernel I2C subsystem. In this case Linux can be used as, for example,
> > a I2C EEPROM machine. See [1] for details. Other than instantiating
> > the EEPROM-slave device from user-space there is a way to declare the
> > device in dts. In this case firstly the I2C bus controller must support
> > the slave interface. Secondly I2C-slave sub-node of that controller
> > must have "reg"-property with flag I2C_OWN_SLAVE_ADDRESS set (flag is
> > declared in [2]). That flag is declared as (1 << 30), which when set
> > makes dtc unhappy about too big address set for a I2C-slave:
> >
> > Warning (i2c_bus_reg): /example-2/i2c@1120000/eeprom@64: I2C bus unit address format error, expected "40000064"
> > Warning (i2c_bus_reg): /example-2/i2c@1120000/eeprom@64:reg: I2C address must be less than 10-bits, got "0x40000064"
> >
> > Similar problem would have happened if we had set the 10-bit address
> > flag I2C_TEN_BIT_ADDRESS in the "reg"-property.
> >
> > In order to fix the problem we suggest to alter the I2C-bus reg-check
> > algorithm, so one would be aware of the upper bits set. Normally if no
> > flag specified, the 7-bit address is expected in the "reg"-property.
> > If I2C_TEN_BIT_ADDRESS is set, then the 10-bit address check will be
> > performed. The I2C_OWN_SLAVE_ADDRESS flag will be just ignored.
> >
> > [1] kernel/Documentation/i2c/slave-interface.rst
> > [2] kernel/include/dt-bindings/i2c/i2c.h
>
> ...
>
> > + addr = reg & 0x3FFFFFFFU;
> > + if ((reg & (1 << 31)) && addr > 0x3ff)
> > FAIL_PROP(c, dti, node, prop, "I2C address must be less than 10-bits, got \"0x%x\"",
> > - reg);
> > -
> > + addr);
> > + else if (!(reg & (1 << 31)) && addr > 0x7f)
> > + FAIL_PROP(c, dti, node, prop, "I2C address must be less than 7-bits, got \"0x%x\"",
> > + addr);
>
> 1 << 31 is UB.
Good point. Thanks.
-Sergey
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
^ permalink raw reply
* Re: [PATCH v25 03/16] dt: bindings: lp50xx: Introduce the lp50xx family of RGB drivers
From: Pavel Machek @ 2020-05-27 13:58 UTC (permalink / raw)
To: Dan Murphy; +Cc: jacek.anaszewski, robh, devicetree, linux-leds, linux-kernel
In-Reply-To: <20200526164652.2331-4-dmurphy@ti.com>
[-- Attachment #1: Type: text/plain, Size: 456 bytes --]
Hi!
> + There can only be one instance of the ti,led-bank
> + property for each device node. This is a required node is the LED
> + modules are to be backed.
I don't understand the second sentence. Pretty sure it is not valid
english.
Best regards,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 181 bytes --]
^ permalink raw reply
* [PATCH v14 2/2] media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver
From: Vishal Sagar @ 2020-05-27 13:57 UTC (permalink / raw)
To: Hyun Kwon, laurent.pinchart, mchehab, robh+dt, mark.rutland,
Michal Simek, linux-media, devicetree, hans.verkuil,
linux-arm-kernel, linux-kernel, Dinesh Kumar, Sandip Kothari,
Luca Ceresoli, Jacopo Mondi
Cc: Vishal Sagar
In-Reply-To: <1590587839-129558-1-git-send-email-vishal.sagar@xilinx.com>
The Xilinx MIPI CSI-2 Rx Subsystem soft IP is used to capture images
from MIPI CSI-2 camera sensors and output AXI4-Stream video data ready
for image processing. Please refer to PG232 for details.
The CSI2 Rx controller filters out all packets except for the packets
with data type fixed in hardware. RAW8 packets are always allowed to
pass through.
It is also used to setup and handle interrupts and enable the core. It
logs all the events in respective counters between streaming on and off.
The driver supports only the video format bridge enabled configuration.
Some data types like YUV 422 10bpc, RAW16, RAW20 are supported when the
CSI v2.0 feature is enabled in design. When the VCX feature is enabled,
the maximum number of virtual channels becomes 16 from 4.
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
---
v14
- Fixed condition to check ret in xcsi2rxss_start_stream
- Use BIT(i) instead of (1 << i)
- Moved "only sink pad format can be updated" in xcsi2rxss_set_format
- Added Reviewed by Luca Ceresoli
- Replace "tr" and "fa" to "true" and "false" in xcsi2rxss_log_status
- Remove setting streaming state to false in SLBF case. The app should
stop the streaming in case of SLBF.
- Made xcsi2rxss_enum_mbus_code() static as reported by kbuild bot
- Added Reviewed by Laurent
v13
- Based on Laurent's suggestions
- Removed unnecessary debug statement for vep
- Added TODO for clock to enable disable at streamon/off
- Fix for index to start from 0 for get_nth_mbus_format
- Removed macro XCSI_TIMEOUT_VAL
- Remove ndelay from hard reset
- Remove hard reset from irq handler
- Fix short packet fifo clear
- Add TODO for v4l2_subdev_notify for SLBF error
- Fix the enable condition in s_stream
- Fix condition in xcsi2rxss_set_format
- Fix enum_mbus_code for double enumeration of RAW8 Data type
- Removed core struct
- Added reviewed by Laurent
v12
- Changes done as suggested by Laurent Pinchart and Luca Ceresoli
- Removed unused macros
- No local storage of supported formats
- Dropped init mbus fmts and removed xcsi2rxss_init_mbus_fmts()
- XCSI_GET_BITSET_STR removed
- Add data type and mbus LUT
- Added xcsi2rxss_get_nth_mbus() and xcsi2rxss_get_dt()
- Replaced all core->dev with dev in dev_dbg() and related debug prints
- Replaced xcsi2rxss_log_ipconfig() with single line
- Removed small functions to enable/disable interrupts and core
- Now save remote subdev in state struct before streaming on
- Made xcsi2rxss_reset as soft_reset()
- Added hard reset using video-reset gpio
- 2 modes one with delay and another sleep
- Instead of reset-gpios it is not video-reset-gpios
- In irq handler
- Moved clearing of ISR up
- Dump / empty short packet fifo
- Irq handler is now threaded
- Added init_cfg pad ops and removed open()
- Updated xcsi2rxss_set_format(), xcsi2rxss_enum_mbus_code() to use the dt mbus lut
- xcsi2rxss_set_default_format() updated
- Moved mutex_init()
- Updated graph handling
- Removed unnecessary prints
- Use devm_platform_ioremap_resource() and platform_get_irq()
- Update KConfig description
v11
- Fixed changes as suggested by Sakari Ailus
- Removed VIDEO_XILINX from KConfig
- Minor formatting
- Start / Stop upstream sub-device in xcsi2rxss_start_stream()
and xcsi2rxss_stop_stream()
- Added v4l2_subdev_link_validate_default() in v4l2_subdev_pad_ops()
- Use fwnode_graph_get_endpoint_by_id() instead of parsing by self
- Set bus type as V4L2_MBUS_CSI2_DPHY in struct v4l2_fwnode_endpoint
- Remove num_clks from core. Instead use ARRAY_SIZE()
- Fixed SPDX header to GPL-2.0
- Update copyright year to 2020
v10
- Removed all V4L2 controls and events based on Sakari's comments.
- Now stop_stream() before toggling rst_gpio
- Updated init_mbus() to throw error on array out of bound access
- Make events and vcx_events as counters instead of structures
- Minor fixes in set_format() enum_mbus_code() as suggested by Sakari
v9
- Moved all controls and events to xilinx-csi2rxss.h
- Updated name and description of controls and events
- Get control base address from v4l2-controls.h (0x10c0)
- Fix KConfig for dependency on VIDEO_XILINX
- Added enum_mbus_code() support
- Added default format to be returned on open()
- Mark variables are const
- Remove references to short packet in comments
- Add check for streaming before setting active lanes control
- strlcpy -> strscpy
- Fix xcsi2rxss_set_format()
v8
- Use clk_bulk* APIs
- Add gpio reset for asserting video_aresetn when stream line buffer occurs
- Removed short packet related events and irq handling
- V4L2_EVENT_XLNXCSIRX_SPKT and V4L2_EVENT_XLNXCSIRX_SPKT_OVF removed
- Removed frame counter control V4L2_CID_XILINX_MIPICSISS_FRAME_COUNTER
and xcsi2rxss_g_volatile_ctrl()
- Minor formatting fixes
v7
- No change
v6
- No change
v5
- Removed bayer and updated related parts like set default format based
on Luca Cersoli's comments.
- Added correct YUV422 10bpc media bus format
v4
- Removed irq member from core structure
- Consolidated IP config prints in xcsi2rxss_log_ipconfig()
- Return -EINVAL in case of invalid ioctl
- Code formatting
- Added reviewed by Hyun Kwon
v3
- Fixed comments given by Hyun.
- Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
- Minor code formatting
- en_csi_v20 and vfb members removed from struct and made local to dt parsing
- lock description updated
- changed to ratelimited type for all dev prints in irq handler
- Removed YUV 422 10bpc media format
v2
- Fixed comments given by Hyun and Sakari.
- Made all bitmask using BIT() and GENMASK()
- Removed unused definitions
- Removed DPHY access. This will be done by separate DPHY PHY driver.
- Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
virtual channels
- Fixed the ports as sink and source
- Now use the v4l2fwnode API to get number of data-lanes
- Added clock framework support
- Removed the close() function
- updated the set format function
- support only VFB enabled configuration
drivers/media/platform/xilinx/Kconfig | 7 +
drivers/media/platform/xilinx/Makefile | 1 +
drivers/media/platform/xilinx/xilinx-csi2rxss.c | 1111 +++++++++++++++++++++++
3 files changed, 1119 insertions(+)
create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c
diff --git a/drivers/media/platform/xilinx/Kconfig b/drivers/media/platform/xilinx/Kconfig
index 01c96fb..44587dc 100644
--- a/drivers/media/platform/xilinx/Kconfig
+++ b/drivers/media/platform/xilinx/Kconfig
@@ -12,6 +12,13 @@ config VIDEO_XILINX
if VIDEO_XILINX
+config VIDEO_XILINX_CSI2RXSS
+ tristate "Xilinx CSI-2 Rx Subsystem"
+ help
+ Driver for Xilinx MIPI CSI-2 Rx Subsystem. This is a V4L sub-device
+ based driver that takes input from CSI-2 Tx source and converts
+ it into an AXI4-Stream.
+
config VIDEO_XILINX_TPG
tristate "Xilinx Video Test Pattern Generator"
depends on VIDEO_XILINX
diff --git a/drivers/media/platform/xilinx/Makefile b/drivers/media/platform/xilinx/Makefile
index 4cdc0b1..6119a34 100644
--- a/drivers/media/platform/xilinx/Makefile
+++ b/drivers/media/platform/xilinx/Makefile
@@ -3,5 +3,6 @@
xilinx-video-objs += xilinx-dma.o xilinx-vip.o xilinx-vipp.o
obj-$(CONFIG_VIDEO_XILINX) += xilinx-video.o
+obj-$(CONFIG_VIDEO_XILINX_CSI2RXSS) += xilinx-csi2rxss.o
obj-$(CONFIG_VIDEO_XILINX_TPG) += xilinx-tpg.o
obj-$(CONFIG_VIDEO_XILINX_VTC) += xilinx-vtc.o
diff --git a/drivers/media/platform/xilinx/xilinx-csi2rxss.c b/drivers/media/platform/xilinx/xilinx-csi2rxss.c
new file mode 100644
index 0000000..fff7dde
--- /dev/null
+++ b/drivers/media/platform/xilinx/xilinx-csi2rxss.c
@@ -0,0 +1,1111 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for Xilinx MIPI CSI-2 Rx Subsystem
+ *
+ * Copyright (C) 2016 - 2020 Xilinx, Inc.
+ *
+ * Contacts: Vishal Sagar <vishal.sagar@xilinx.com>
+ *
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/v4l2-subdev.h>
+#include <media/media-entity.h>
+#include <media/v4l2-common.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-fwnode.h>
+#include <media/v4l2-subdev.h>
+#include "xilinx-vip.h"
+
+/* Register register map */
+#define XCSI_CCR_OFFSET 0x00
+#define XCSI_CCR_SOFTRESET BIT(1)
+#define XCSI_CCR_ENABLE BIT(0)
+
+#define XCSI_PCR_OFFSET 0x04
+#define XCSI_PCR_MAXLANES_MASK GENMASK(4, 3)
+#define XCSI_PCR_ACTLANES_MASK GENMASK(1, 0)
+
+#define XCSI_CSR_OFFSET 0x10
+#define XCSI_CSR_PKTCNT GENMASK(31, 16)
+#define XCSI_CSR_SPFIFOFULL BIT(3)
+#define XCSI_CSR_SPFIFONE BIT(2)
+#define XCSI_CSR_SLBF BIT(1)
+#define XCSI_CSR_RIPCD BIT(0)
+
+#define XCSI_GIER_OFFSET 0x20
+#define XCSI_GIER_GIE BIT(0)
+
+#define XCSI_ISR_OFFSET 0x24
+#define XCSI_IER_OFFSET 0x28
+
+#define XCSI_ISR_FR BIT(31)
+#define XCSI_ISR_VCXFE BIT(30)
+#define XCSI_ISR_WCC BIT(22)
+#define XCSI_ISR_ILC BIT(21)
+#define XCSI_ISR_SPFIFOF BIT(20)
+#define XCSI_ISR_SPFIFONE BIT(19)
+#define XCSI_ISR_SLBF BIT(18)
+#define XCSI_ISR_STOP BIT(17)
+#define XCSI_ISR_SOTERR BIT(13)
+#define XCSI_ISR_SOTSYNCERR BIT(12)
+#define XCSI_ISR_ECC2BERR BIT(11)
+#define XCSI_ISR_ECC1BERR BIT(10)
+#define XCSI_ISR_CRCERR BIT(9)
+#define XCSI_ISR_DATAIDERR BIT(8)
+#define XCSI_ISR_VC3FSYNCERR BIT(7)
+#define XCSI_ISR_VC3FLVLERR BIT(6)
+#define XCSI_ISR_VC2FSYNCERR BIT(5)
+#define XCSI_ISR_VC2FLVLERR BIT(4)
+#define XCSI_ISR_VC1FSYNCERR BIT(3)
+#define XCSI_ISR_VC1FLVLERR BIT(2)
+#define XCSI_ISR_VC0FSYNCERR BIT(1)
+#define XCSI_ISR_VC0FLVLERR BIT(0)
+
+#define XCSI_ISR_ALLINTR_MASK (0xc07e3fff)
+
+/*
+ * Removed VCXFE mask as it doesn't exist in IER
+ * Removed STOP state irq as this will keep driver in irq handler only
+ */
+#define XCSI_IER_INTR_MASK (XCSI_ISR_ALLINTR_MASK &\
+ ~(XCSI_ISR_STOP | XCSI_ISR_VCXFE))
+
+#define XCSI_SPKTR_OFFSET 0x30
+#define XCSI_SPKTR_DATA GENMASK(23, 8)
+#define XCSI_SPKTR_VC GENMASK(7, 6)
+#define XCSI_SPKTR_DT GENMASK(5, 0)
+#define XCSI_SPKT_FIFO_DEPTH 31
+
+#define XCSI_VCXR_OFFSET 0x34
+#define XCSI_VCXR_VCERR GENMASK(23, 0)
+#define XCSI_VCXR_FSYNCERR BIT(1)
+#define XCSI_VCXR_FLVLERR BIT(0)
+
+#define XCSI_CLKINFR_OFFSET 0x3C
+#define XCSI_CLKINFR_STOP BIT(1)
+
+#define XCSI_DLXINFR_OFFSET 0x40
+#define XCSI_DLXINFR_STOP BIT(5)
+#define XCSI_DLXINFR_SOTERR BIT(1)
+#define XCSI_DLXINFR_SOTSYNCERR BIT(0)
+#define XCSI_MAXDL_COUNT 0x4
+
+#define XCSI_VCXINF1R_OFFSET 0x60
+#define XCSI_VCXINF1R_LINECOUNT GENMASK(31, 16)
+#define XCSI_VCXINF1R_LINECOUNT_SHIFT 16
+#define XCSI_VCXINF1R_BYTECOUNT GENMASK(15, 0)
+
+#define XCSI_VCXINF2R_OFFSET 0x64
+#define XCSI_VCXINF2R_DT GENMASK(5, 0)
+#define XCSI_MAXVCX_COUNT 16
+
+/*
+ * Sink pad connected to sensor source pad.
+ * Source pad connected to next module like demosaic.
+ */
+#define XCSI_MEDIA_PADS 2
+#define XCSI_DEFAULT_WIDTH 1920
+#define XCSI_DEFAULT_HEIGHT 1080
+
+/* MIPI CSI-2 Data Types from spec */
+#define XCSI_DT_YUV4228B 0x1e
+#define XCSI_DT_YUV42210B 0x1f
+#define XCSI_DT_RGB444 0x20
+#define XCSI_DT_RGB555 0x21
+#define XCSI_DT_RGB565 0x22
+#define XCSI_DT_RGB666 0x23
+#define XCSI_DT_RGB888 0x24
+#define XCSI_DT_RAW6 0x28
+#define XCSI_DT_RAW7 0x29
+#define XCSI_DT_RAW8 0x2a
+#define XCSI_DT_RAW10 0x2b
+#define XCSI_DT_RAW12 0x2c
+#define XCSI_DT_RAW14 0x2d
+#define XCSI_DT_RAW16 0x2e
+#define XCSI_DT_RAW20 0x2f
+
+#define XCSI_VCX_START 4
+#define XCSI_MAX_VC 4
+#define XCSI_MAX_VCX 16
+
+#define XCSI_NEXTREG_OFFSET 4
+
+/* There are 2 events frame sync and frame level error per VC */
+#define XCSI_VCX_NUM_EVENTS ((XCSI_MAX_VCX - XCSI_MAX_VC) * 2)
+
+/**
+ * struct xcsi2rxss_event - Event log structure
+ * @mask: Event mask
+ * @name: Name of the event
+ */
+struct xcsi2rxss_event {
+ u32 mask;
+ const char *name;
+};
+
+static const struct xcsi2rxss_event xcsi2rxss_events[] = {
+ { XCSI_ISR_FR, "Frame Received" },
+ { XCSI_ISR_VCXFE, "VCX Frame Errors" },
+ { XCSI_ISR_WCC, "Word Count Errors" },
+ { XCSI_ISR_ILC, "Invalid Lane Count Error" },
+ { XCSI_ISR_SPFIFOF, "Short Packet FIFO OverFlow Error" },
+ { XCSI_ISR_SPFIFONE, "Short Packet FIFO Not Empty" },
+ { XCSI_ISR_SLBF, "Streamline Buffer Full Error" },
+ { XCSI_ISR_STOP, "Lane Stop State" },
+ { XCSI_ISR_SOTERR, "SOT Error" },
+ { XCSI_ISR_SOTSYNCERR, "SOT Sync Error" },
+ { XCSI_ISR_ECC2BERR, "2 Bit ECC Unrecoverable Error" },
+ { XCSI_ISR_ECC1BERR, "1 Bit ECC Recoverable Error" },
+ { XCSI_ISR_CRCERR, "CRC Error" },
+ { XCSI_ISR_DATAIDERR, "Data Id Error" },
+ { XCSI_ISR_VC3FSYNCERR, "Virtual Channel 3 Frame Sync Error" },
+ { XCSI_ISR_VC3FLVLERR, "Virtual Channel 3 Frame Level Error" },
+ { XCSI_ISR_VC2FSYNCERR, "Virtual Channel 2 Frame Sync Error" },
+ { XCSI_ISR_VC2FLVLERR, "Virtual Channel 2 Frame Level Error" },
+ { XCSI_ISR_VC1FSYNCERR, "Virtual Channel 1 Frame Sync Error" },
+ { XCSI_ISR_VC1FLVLERR, "Virtual Channel 1 Frame Level Error" },
+ { XCSI_ISR_VC0FSYNCERR, "Virtual Channel 0 Frame Sync Error" },
+ { XCSI_ISR_VC0FLVLERR, "Virtual Channel 0 Frame Level Error" }
+};
+
+#define XCSI_NUM_EVENTS ARRAY_SIZE(xcsi2rxss_events)
+
+/*
+ * This table provides a mapping between CSI-2 Data type
+ * and media bus formats
+ */
+static const u32 xcsi2dt_mbus_lut[][2] = {
+ { XCSI_DT_YUV4228B, MEDIA_BUS_FMT_UYVY8_1X16 },
+ { XCSI_DT_YUV42210B, MEDIA_BUS_FMT_UYVY10_1X20 },
+ { XCSI_DT_RGB444, 0 },
+ { XCSI_DT_RGB555, 0 },
+ { XCSI_DT_RGB565, 0 },
+ { XCSI_DT_RGB666, 0 },
+ { XCSI_DT_RGB888, MEDIA_BUS_FMT_RBG888_1X24 },
+ { XCSI_DT_RAW6, 0 },
+ { XCSI_DT_RAW7, 0 },
+ { XCSI_DT_RAW8, MEDIA_BUS_FMT_SRGGB8_1X8 },
+ { XCSI_DT_RAW8, MEDIA_BUS_FMT_SBGGR8_1X8 },
+ { XCSI_DT_RAW8, MEDIA_BUS_FMT_SGBRG8_1X8 },
+ { XCSI_DT_RAW8, MEDIA_BUS_FMT_SGRBG8_1X8 },
+ { XCSI_DT_RAW10, MEDIA_BUS_FMT_SRGGB10_1X10 },
+ { XCSI_DT_RAW10, MEDIA_BUS_FMT_SBGGR10_1X10 },
+ { XCSI_DT_RAW10, MEDIA_BUS_FMT_SGBRG10_1X10 },
+ { XCSI_DT_RAW10, MEDIA_BUS_FMT_SGRBG10_1X10 },
+ { XCSI_DT_RAW12, MEDIA_BUS_FMT_SRGGB12_1X12 },
+ { XCSI_DT_RAW12, MEDIA_BUS_FMT_SBGGR12_1X12 },
+ { XCSI_DT_RAW12, MEDIA_BUS_FMT_SGBRG12_1X12 },
+ { XCSI_DT_RAW12, MEDIA_BUS_FMT_SGRBG12_1X12 },
+ { XCSI_DT_RAW16, MEDIA_BUS_FMT_SRGGB16_1X16 },
+ { XCSI_DT_RAW16, MEDIA_BUS_FMT_SBGGR16_1X16 },
+ { XCSI_DT_RAW16, MEDIA_BUS_FMT_SGBRG16_1X16 },
+ { XCSI_DT_RAW16, MEDIA_BUS_FMT_SGRBG16_1X16 },
+ { XCSI_DT_RAW20, 0 },
+};
+
+/**
+ * struct xcsi2rxss_state - CSI-2 Rx Subsystem device structure
+ * @subdev: The v4l2 subdev structure
+ * @format: Active V4L2 formats on each pad
+ * @default_format: Default V4L2 format
+ * @events: counter for events
+ * @vcx_events: counter for vcx_events
+ * @dev: Platform structure
+ * @rsubdev: Remote subdev connected to sink pad
+ * @rst_gpio: reset to video_aresetn
+ * @clks: array of clocks
+ * @iomem: Base address of subsystem
+ * @max_num_lanes: Maximum number of lanes present
+ * @datatype: Data type filter
+ * @lock: mutex for accessing this structure
+ * @pads: media pads
+ * @streaming: Flag for storing streaming state
+ * @enable_active_lanes: If number of active lanes can be modified
+ * @en_vcx: If more than 4 VC are enabled
+ *
+ * This structure contains the device driver related parameters
+ */
+struct xcsi2rxss_state {
+ struct v4l2_subdev subdev;
+ struct v4l2_mbus_framefmt format;
+ struct v4l2_mbus_framefmt default_format;
+ u32 events[XCSI_NUM_EVENTS];
+ u32 vcx_events[XCSI_VCX_NUM_EVENTS];
+ struct device *dev;
+ struct v4l2_subdev *rsubdev;
+ struct gpio_desc *rst_gpio;
+ struct clk_bulk_data *clks;
+ void __iomem *iomem;
+ u32 max_num_lanes;
+ u32 datatype;
+ /* used to protect access to this struct */
+ struct mutex lock;
+ struct media_pad pads[XCSI_MEDIA_PADS];
+ bool streaming;
+ bool enable_active_lanes;
+ bool en_vcx;
+};
+
+static const struct clk_bulk_data xcsi2rxss_clks[] = {
+ { .id = "lite_aclk" },
+ { .id = "video_aclk" },
+};
+
+static inline struct xcsi2rxss_state *
+to_xcsi2rxssstate(struct v4l2_subdev *subdev)
+{
+ return container_of(subdev, struct xcsi2rxss_state, subdev);
+}
+
+/*
+ * Register related operations
+ */
+static inline u32 xcsi2rxss_read(struct xcsi2rxss_state *xcsi2rxss, u32 addr)
+{
+ return ioread32(xcsi2rxss->iomem + addr);
+}
+
+static inline void xcsi2rxss_write(struct xcsi2rxss_state *xcsi2rxss, u32 addr,
+ u32 value)
+{
+ iowrite32(value, xcsi2rxss->iomem + addr);
+}
+
+static inline void xcsi2rxss_clr(struct xcsi2rxss_state *xcsi2rxss, u32 addr,
+ u32 clr)
+{
+ xcsi2rxss_write(xcsi2rxss, addr,
+ xcsi2rxss_read(xcsi2rxss, addr) & ~clr);
+}
+
+static inline void xcsi2rxss_set(struct xcsi2rxss_state *xcsi2rxss, u32 addr,
+ u32 set)
+{
+ xcsi2rxss_write(xcsi2rxss, addr, xcsi2rxss_read(xcsi2rxss, addr) | set);
+}
+
+/*
+ * This function returns the nth mbus for a data type.
+ * In case of error, mbus code returned is 0.
+ */
+static u32 xcsi2rxss_get_nth_mbus(u32 dt, u32 n)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(xcsi2dt_mbus_lut); i++) {
+ if (xcsi2dt_mbus_lut[i][0] == dt) {
+ if (n-- == 0)
+ return xcsi2dt_mbus_lut[i][1];
+ }
+ }
+
+ return 0;
+}
+
+/* This returns the data type for a media bus format else 0 */
+static u32 xcsi2rxss_get_dt(u32 mbus)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(xcsi2dt_mbus_lut); i++) {
+ if (xcsi2dt_mbus_lut[i][1] == mbus)
+ return xcsi2dt_mbus_lut[i][0];
+ }
+
+ return 0;
+}
+
+/**
+ * xcsi2rxss_soft_reset - Does a soft reset of the MIPI CSI-2 Rx Subsystem
+ * @state: Xilinx CSI-2 Rx Subsystem structure pointer
+ *
+ * Core takes less than 100 video clock cycles to reset.
+ * So a larger timeout value is chosen for margin.
+ *
+ * Return: 0 - on success OR -ETIME if reset times out
+ */
+static int xcsi2rxss_soft_reset(struct xcsi2rxss_state *state)
+{
+ u32 timeout = 1000; /* us */
+
+ xcsi2rxss_set(state, XCSI_CCR_OFFSET, XCSI_CCR_SOFTRESET);
+
+ while (xcsi2rxss_read(state, XCSI_CSR_OFFSET) & XCSI_CSR_RIPCD) {
+ if (timeout == 0) {
+ dev_err(state->dev, "soft reset timed out!\n");
+ return -ETIME;
+ }
+
+ timeout--;
+ udelay(1);
+ }
+
+ xcsi2rxss_clr(state, XCSI_CCR_OFFSET, XCSI_CCR_SOFTRESET);
+ return 0;
+}
+
+static void xcsi2rxss_hard_reset(struct xcsi2rxss_state *state)
+{
+ if (!state->rst_gpio)
+ return;
+
+ /* minimum of 40 dphy_clk_200M cycles */
+ gpiod_set_value_cansleep(state->rst_gpio, 1);
+ usleep_range(1, 2);
+ gpiod_set_value_cansleep(state->rst_gpio, 0);
+}
+
+static void xcsi2rxss_reset_event_counters(struct xcsi2rxss_state *state)
+{
+ unsigned int i;
+
+ for (i = 0; i < XCSI_NUM_EVENTS; i++)
+ state->events[i] = 0;
+
+ for (i = 0; i < XCSI_VCX_NUM_EVENTS; i++)
+ state->vcx_events[i] = 0;
+}
+
+/* Print event counters */
+static void xcsi2rxss_log_counters(struct xcsi2rxss_state *state)
+{
+ struct device *dev = state->dev;
+ unsigned int i;
+
+ for (i = 0; i < XCSI_NUM_EVENTS; i++) {
+ if (state->events[i] > 0) {
+ dev_info(dev, "%s events: %d\n",
+ xcsi2rxss_events[i].name,
+ state->events[i]);
+ }
+ }
+
+ if (state->en_vcx) {
+ for (i = 0; i < XCSI_VCX_NUM_EVENTS; i++) {
+ if (state->vcx_events[i] > 0) {
+ dev_info(dev,
+ "VC %d Frame %s err vcx events: %d\n",
+ (i / 2) + XCSI_VCX_START,
+ i & 1 ? "Sync" : "Level",
+ state->vcx_events[i]);
+ }
+ }
+ }
+}
+
+/**
+ * xcsi2rxss_log_status - Logs the status of the CSI-2 Receiver
+ * @sd: Pointer to V4L2 subdevice structure
+ *
+ * This function prints the current status of Xilinx MIPI CSI-2
+ *
+ * Return: 0 on success
+ */
+static int xcsi2rxss_log_status(struct v4l2_subdev *sd)
+{
+ struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);
+ struct device *dev = xcsi2rxss->dev;
+ u32 reg, data;
+ unsigned int i, max_vc;
+
+ mutex_lock(&xcsi2rxss->lock);
+
+ xcsi2rxss_log_counters(xcsi2rxss);
+
+ dev_info(dev, "***** Core Status *****\n");
+ data = xcsi2rxss_read(xcsi2rxss, XCSI_CSR_OFFSET);
+ dev_info(dev, "Short Packet FIFO Full = %s\n",
+ data & XCSI_CSR_SPFIFOFULL ? "true" : "false");
+ dev_info(dev, "Short Packet FIFO Not Empty = %s\n",
+ data & XCSI_CSR_SPFIFONE ? "true" : "false");
+ dev_info(dev, "Stream line buffer full = %s\n",
+ data & XCSI_CSR_SLBF ? "true" : "false");
+ dev_info(dev, "Soft reset/Core disable in progress = %s\n",
+ data & XCSI_CSR_RIPCD ? "true" : "false");
+
+ /* Clk & Lane Info */
+ dev_info(dev, "******** Clock Lane Info *********\n");
+ data = xcsi2rxss_read(xcsi2rxss, XCSI_CLKINFR_OFFSET);
+ dev_info(dev, "Clock Lane in Stop State = %s\n",
+ data & XCSI_CLKINFR_STOP ? "true" : "false");
+
+ dev_info(dev, "******** Data Lane Info *********\n");
+ dev_info(dev, "Lane\tSoT Error\tSoT Sync Error\tStop State\n");
+ reg = XCSI_DLXINFR_OFFSET;
+ for (i = 0; i < XCSI_MAXDL_COUNT; i++) {
+ data = xcsi2rxss_read(xcsi2rxss, reg);
+
+ dev_info(dev, "%d\t%s\t\t%s\t\t%s\n", i,
+ data & XCSI_DLXINFR_SOTERR ? "true" : "false",
+ data & XCSI_DLXINFR_SOTSYNCERR ? "true" : "false",
+ data & XCSI_DLXINFR_STOP ? "true" : "false");
+
+ reg += XCSI_NEXTREG_OFFSET;
+ }
+
+ /* Virtual Channel Image Information */
+ dev_info(dev, "********** Virtual Channel Info ************\n");
+ dev_info(dev, "VC\tLine Count\tByte Count\tData Type\n");
+ if (xcsi2rxss->en_vcx)
+ max_vc = XCSI_MAX_VCX;
+ else
+ max_vc = XCSI_MAX_VC;
+
+ reg = XCSI_VCXINF1R_OFFSET;
+ for (i = 0; i < max_vc; i++) {
+ u32 line_count, byte_count, data_type;
+
+ /* Get line and byte count from VCXINFR1 Register */
+ data = xcsi2rxss_read(xcsi2rxss, reg);
+ byte_count = data & XCSI_VCXINF1R_BYTECOUNT;
+ line_count = data & XCSI_VCXINF1R_LINECOUNT;
+ line_count >>= XCSI_VCXINF1R_LINECOUNT_SHIFT;
+
+ /* Get data type from VCXINFR2 Register */
+ reg += XCSI_NEXTREG_OFFSET;
+ data = xcsi2rxss_read(xcsi2rxss, reg);
+ data_type = data & XCSI_VCXINF2R_DT;
+
+ dev_info(dev, "%d\t%d\t\t%d\t\t0x%x\n", i, line_count,
+ byte_count, data_type);
+
+ /* Move to next pair of VC Info registers */
+ reg += XCSI_NEXTREG_OFFSET;
+ }
+
+ mutex_unlock(&xcsi2rxss->lock);
+
+ return 0;
+}
+
+static struct v4l2_subdev *xcsi2rxss_get_remote_subdev(struct media_pad *local)
+{
+ struct media_pad *remote;
+
+ remote = media_entity_remote_pad(local);
+ if (!remote || !is_media_entity_v4l2_subdev(remote->entity))
+ return NULL;
+
+ return media_entity_to_v4l2_subdev(remote->entity);
+}
+
+static int xcsi2rxss_start_stream(struct xcsi2rxss_state *state)
+{
+ int ret = 0;
+
+ /* enable core */
+ xcsi2rxss_set(state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE);
+
+ ret = xcsi2rxss_soft_reset(state);
+ if (ret) {
+ state->streaming = false;
+ return ret;
+ }
+
+ /* enable interrupts */
+ xcsi2rxss_clr(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
+ xcsi2rxss_write(state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK);
+ xcsi2rxss_set(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
+
+ state->streaming = true;
+
+ state->rsubdev =
+ xcsi2rxss_get_remote_subdev(&state->pads[XVIP_PAD_SINK]);
+
+ ret = v4l2_subdev_call(state->rsubdev, video, s_stream, 1);
+ if (ret) {
+ /* disable interrupts */
+ xcsi2rxss_clr(state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK);
+ xcsi2rxss_clr(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
+
+ /* disable core */
+ xcsi2rxss_clr(state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE);
+ state->streaming = false;
+ }
+
+ return ret;
+}
+
+static void xcsi2rxss_stop_stream(struct xcsi2rxss_state *state)
+{
+ v4l2_subdev_call(state->rsubdev, video, s_stream, 0);
+
+ /* disable interrupts */
+ xcsi2rxss_clr(state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK);
+ xcsi2rxss_clr(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
+
+ /* disable core */
+ xcsi2rxss_clr(state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE);
+ state->streaming = false;
+}
+
+/**
+ * xcsi2rxss_irq_handler - Interrupt handler for CSI-2
+ * @irq: IRQ number
+ * @data: Pointer to device state
+ *
+ * In the interrupt handler, a list of event counters are updated for
+ * corresponding interrupts. This is useful to get status / debug.
+ *
+ * Return: IRQ_HANDLED after handling interrupts
+ */
+static irqreturn_t xcsi2rxss_irq_handler(int irq, void *data)
+{
+ struct xcsi2rxss_state *state = (struct xcsi2rxss_state *)data;
+ struct device *dev = state->dev;
+ u32 status;
+
+ status = xcsi2rxss_read(state, XCSI_ISR_OFFSET) & XCSI_ISR_ALLINTR_MASK;
+ xcsi2rxss_write(state, XCSI_ISR_OFFSET, status);
+
+ /* Received a short packet */
+ if (status & XCSI_ISR_SPFIFONE) {
+ u32 count = 0;
+
+ /*
+ * Drain generic short packet FIFO by reading max 31
+ * (fifo depth) short packets from fifo or till fifo is empty.
+ */
+ for (count = 0; count < XCSI_SPKT_FIFO_DEPTH; ++count) {
+ u32 spfifostat, spkt;
+
+ spkt = xcsi2rxss_read(state, XCSI_SPKTR_OFFSET);
+ dev_dbg(dev, "Short packet = 0x%08x\n", spkt);
+ spfifostat = xcsi2rxss_read(state, XCSI_ISR_OFFSET);
+ spfifostat &= XCSI_ISR_SPFIFONE;
+ if (!spfifostat)
+ break;
+ xcsi2rxss_write(state, XCSI_ISR_OFFSET, spfifostat);
+ }
+ }
+
+ /* Short packet FIFO overflow */
+ if (status & XCSI_ISR_SPFIFOF)
+ dev_dbg_ratelimited(dev, "Short packet FIFO overflowed\n");
+
+ /*
+ * Stream line buffer full
+ * This means there is a backpressure from downstream IP
+ */
+ if (status & XCSI_ISR_SLBF) {
+ dev_alert_ratelimited(dev, "Stream Line Buffer Full!\n");
+
+ /* disable interrupts */
+ xcsi2rxss_clr(state, XCSI_IER_OFFSET, XCSI_IER_INTR_MASK);
+ xcsi2rxss_clr(state, XCSI_GIER_OFFSET, XCSI_GIER_GIE);
+
+ /* disable core */
+ xcsi2rxss_clr(state, XCSI_CCR_OFFSET, XCSI_CCR_ENABLE);
+
+ /*
+ * The IP needs to be hard reset before it can be used now.
+ * This will be done in streamoff.
+ */
+
+ /*
+ * TODO: Notify the whole pipeline with v4l2_subdev_notify() to
+ * inform userspace.
+ */
+ }
+
+ /* Increment event counters */
+ if (status & XCSI_ISR_ALLINTR_MASK) {
+ unsigned int i;
+
+ for (i = 0; i < XCSI_NUM_EVENTS; i++) {
+ if (!(status & xcsi2rxss_events[i].mask))
+ continue;
+ state->events[i]++;
+ dev_dbg_ratelimited(dev, "%s: %u\n",
+ xcsi2rxss_events[i].name,
+ state->events[i]);
+ }
+
+ if (status & XCSI_ISR_VCXFE && state->en_vcx) {
+ u32 vcxstatus;
+
+ vcxstatus = xcsi2rxss_read(state, XCSI_VCXR_OFFSET);
+ vcxstatus &= XCSI_VCXR_VCERR;
+ for (i = 0; i < XCSI_VCX_NUM_EVENTS; i++) {
+ if (!(vcxstatus & BIT(i)))
+ continue;
+ state->vcx_events[i]++;
+ }
+ xcsi2rxss_write(state, XCSI_VCXR_OFFSET, vcxstatus);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+/**
+ * xcsi2rxss_s_stream - It is used to start/stop the streaming.
+ * @sd: V4L2 Sub device
+ * @enable: Flag (True / False)
+ *
+ * This function controls the start or stop of streaming for the
+ * Xilinx MIPI CSI-2 Rx Subsystem.
+ *
+ * Return: 0 on success, errors otherwise
+ */
+static int xcsi2rxss_s_stream(struct v4l2_subdev *sd, int enable)
+{
+ struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);
+ int ret = 0;
+
+ mutex_lock(&xcsi2rxss->lock);
+
+ if (enable == xcsi2rxss->streaming)
+ goto stream_done;
+
+ if (enable) {
+ xcsi2rxss_reset_event_counters(xcsi2rxss);
+ ret = xcsi2rxss_start_stream(xcsi2rxss);
+ } else {
+ xcsi2rxss_stop_stream(xcsi2rxss);
+ xcsi2rxss_hard_reset(xcsi2rxss);
+ }
+
+stream_done:
+ mutex_unlock(&xcsi2rxss->lock);
+ return ret;
+}
+
+static struct v4l2_mbus_framefmt *
+__xcsi2rxss_get_pad_format(struct xcsi2rxss_state *xcsi2rxss,
+ struct v4l2_subdev_pad_config *cfg,
+ unsigned int pad, u32 which)
+{
+ switch (which) {
+ case V4L2_SUBDEV_FORMAT_TRY:
+ return v4l2_subdev_get_try_format(&xcsi2rxss->subdev, cfg, pad);
+ case V4L2_SUBDEV_FORMAT_ACTIVE:
+ return &xcsi2rxss->format;
+ default:
+ return NULL;
+ }
+}
+
+/**
+ * xcsi2rxss_init_cfg - Initialise the pad format config to default
+ * @sd: Pointer to V4L2 Sub device structure
+ * @cfg: Pointer to sub device pad information structure
+ *
+ * This function is used to initialize the pad format with the default
+ * values.
+ *
+ * Return: 0 on success
+ */
+static int xcsi2rxss_init_cfg(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg)
+{
+ struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);
+ struct v4l2_mbus_framefmt *format;
+ unsigned int i;
+
+ mutex_lock(&xcsi2rxss->lock);
+ for (i = 0; i < XCSI_MEDIA_PADS; i++) {
+ format = v4l2_subdev_get_try_format(sd, cfg, i);
+ *format = xcsi2rxss->default_format;
+ }
+ mutex_unlock(&xcsi2rxss->lock);
+
+ return 0;
+}
+
+/**
+ * xcsi2rxss_get_format - Get the pad format
+ * @sd: Pointer to V4L2 Sub device structure
+ * @cfg: Pointer to sub device pad information structure
+ * @fmt: Pointer to pad level media bus format
+ *
+ * This function is used to get the pad format information.
+ *
+ * Return: 0 on success
+ */
+static int xcsi2rxss_get_format(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
+{
+ struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);
+
+ mutex_lock(&xcsi2rxss->lock);
+ fmt->format = *__xcsi2rxss_get_pad_format(xcsi2rxss, cfg, fmt->pad,
+ fmt->which);
+ mutex_unlock(&xcsi2rxss->lock);
+
+ return 0;
+}
+
+/**
+ * xcsi2rxss_set_format - This is used to set the pad format
+ * @sd: Pointer to V4L2 Sub device structure
+ * @cfg: Pointer to sub device pad information structure
+ * @fmt: Pointer to pad level media bus format
+ *
+ * This function is used to set the pad format. Since the pad format is fixed
+ * in hardware, it can't be modified on run time. So when a format set is
+ * requested by application, all parameters except the format type is saved
+ * for the pad and the original pad format is sent back to the application.
+ *
+ * Return: 0 on success
+ */
+static int xcsi2rxss_set_format(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *fmt)
+{
+ struct xcsi2rxss_state *xcsi2rxss = to_xcsi2rxssstate(sd);
+ struct v4l2_mbus_framefmt *__format;
+ u32 dt;
+
+ mutex_lock(&xcsi2rxss->lock);
+
+ /*
+ * Only the format->code parameter matters for CSI as the
+ * CSI format cannot be changed at runtime.
+ * Ensure that format to set is copied to over to CSI pad format
+ */
+ __format = __xcsi2rxss_get_pad_format(xcsi2rxss, cfg,
+ fmt->pad, fmt->which);
+
+ /* only sink pad format can be updated */
+ if (fmt->pad == XVIP_PAD_SOURCE) {
+ fmt->format = *__format;
+ mutex_unlock(&xcsi2rxss->lock);
+ return 0;
+ }
+
+ /*
+ * RAW8 is supported in all datatypes. So if requested media bus format
+ * is of RAW8 type, then allow to be set. In case core is configured to
+ * other RAW, YUV422 8/10 or RGB888, set appropriate media bus format.
+ */
+ dt = xcsi2rxss_get_dt(fmt->format.code);
+ if (dt != xcsi2rxss->datatype && dt != XCSI_DT_RAW8) {
+ dev_dbg(xcsi2rxss->dev, "Unsupported media bus format");
+ /* set the default format for the data type */
+ fmt->format.code = xcsi2rxss_get_nth_mbus(xcsi2rxss->datatype,
+ 0);
+ }
+
+ *__format = fmt->format;
+ mutex_unlock(&xcsi2rxss->lock);
+
+ return 0;
+}
+
+/*
+ * xcsi2rxss_enum_mbus_code - Handle pixel format enumeration
+ * @sd: pointer to v4l2 subdev structure
+ * @cfg: V4L2 subdev pad configuration
+ * @code: pointer to v4l2_subdev_mbus_code_enum structure
+ *
+ * Return: -EINVAL or zero on success
+ */
+static int xcsi2rxss_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ struct xcsi2rxss_state *state = to_xcsi2rxssstate(sd);
+ u32 dt, n;
+ int ret = 0;
+
+ /* RAW8 dt packets are available in all DT configurations */
+ if (code->index < 4) {
+ n = code->index;
+ dt = XCSI_DT_RAW8;
+ } else if (state->datatype != XCSI_DT_RAW8) {
+ n = code->index - 4;
+ dt = state->datatype;
+ } else {
+ return -EINVAL;
+ }
+
+ code->code = xcsi2rxss_get_nth_mbus(dt, n);
+ if (!code->code)
+ ret = -EINVAL;
+
+ return ret;
+}
+
+/* -----------------------------------------------------------------------------
+ * Media Operations
+ */
+
+static const struct media_entity_operations xcsi2rxss_media_ops = {
+ .link_validate = v4l2_subdev_link_validate
+};
+
+static const struct v4l2_subdev_core_ops xcsi2rxss_core_ops = {
+ .log_status = xcsi2rxss_log_status,
+};
+
+static const struct v4l2_subdev_video_ops xcsi2rxss_video_ops = {
+ .s_stream = xcsi2rxss_s_stream
+};
+
+static const struct v4l2_subdev_pad_ops xcsi2rxss_pad_ops = {
+ .init_cfg = xcsi2rxss_init_cfg,
+ .get_fmt = xcsi2rxss_get_format,
+ .set_fmt = xcsi2rxss_set_format,
+ .enum_mbus_code = xcsi2rxss_enum_mbus_code,
+ .link_validate = v4l2_subdev_link_validate_default,
+};
+
+static const struct v4l2_subdev_ops xcsi2rxss_ops = {
+ .core = &xcsi2rxss_core_ops,
+ .video = &xcsi2rxss_video_ops,
+ .pad = &xcsi2rxss_pad_ops
+};
+
+static int xcsi2rxss_parse_of(struct xcsi2rxss_state *xcsi2rxss)
+{
+ struct device *dev = xcsi2rxss->dev;
+ struct device_node *node = dev->of_node;
+
+ struct fwnode_handle *ep;
+ struct v4l2_fwnode_endpoint vep = {
+ .bus_type = V4L2_MBUS_CSI2_DPHY
+ };
+ bool en_csi_v20, vfb;
+ int ret;
+
+ en_csi_v20 = of_property_read_bool(node, "xlnx,en-csi-v2-0");
+ if (en_csi_v20)
+ xcsi2rxss->en_vcx = of_property_read_bool(node, "xlnx,en-vcx");
+
+ xcsi2rxss->enable_active_lanes =
+ of_property_read_bool(node, "xlnx,en-active-lanes");
+
+ ret = of_property_read_u32(node, "xlnx,csi-pxl-format",
+ &xcsi2rxss->datatype);
+ if (ret < 0) {
+ dev_err(dev, "missing xlnx,csi-pxl-format property\n");
+ return ret;
+ }
+
+ switch (xcsi2rxss->datatype) {
+ case XCSI_DT_YUV4228B:
+ case XCSI_DT_RGB444:
+ case XCSI_DT_RGB555:
+ case XCSI_DT_RGB565:
+ case XCSI_DT_RGB666:
+ case XCSI_DT_RGB888:
+ case XCSI_DT_RAW6:
+ case XCSI_DT_RAW7:
+ case XCSI_DT_RAW8:
+ case XCSI_DT_RAW10:
+ case XCSI_DT_RAW12:
+ case XCSI_DT_RAW14:
+ break;
+ case XCSI_DT_YUV42210B:
+ case XCSI_DT_RAW16:
+ case XCSI_DT_RAW20:
+ if (!en_csi_v20) {
+ ret = -EINVAL;
+ dev_dbg(dev, "enable csi v2 for this pixel format");
+ }
+ break;
+ default:
+ ret = -EINVAL;
+ }
+ if (ret < 0) {
+ dev_err(dev, "invalid csi-pxl-format property!\n");
+ return ret;
+ }
+
+ vfb = of_property_read_bool(node, "xlnx,vfb");
+ if (!vfb) {
+ dev_err(dev, "operation without VFB is not supported\n");
+ return -EINVAL;
+ }
+
+ ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
+ XVIP_PAD_SINK, 0,
+ FWNODE_GRAPH_ENDPOINT_NEXT);
+ if (!ep) {
+ dev_err(dev, "no sink port found");
+ return -EINVAL;
+ }
+
+ ret = v4l2_fwnode_endpoint_parse(ep, &vep);
+ fwnode_handle_put(ep);
+ if (ret) {
+ dev_err(dev, "error parsing sink port");
+ return ret;
+ }
+
+ dev_dbg(dev, "mipi number lanes = %d\n",
+ vep.bus.mipi_csi2.num_data_lanes);
+
+ xcsi2rxss->max_num_lanes = vep.bus.mipi_csi2.num_data_lanes;
+
+ ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),
+ XVIP_PAD_SOURCE, 0,
+ FWNODE_GRAPH_ENDPOINT_NEXT);
+ if (!ep) {
+ dev_err(dev, "no source port found");
+ return -EINVAL;
+ }
+
+ fwnode_handle_put(ep);
+
+ dev_dbg(dev, "vcx %s, %u data lanes (%s), data type 0x%02x\n",
+ xcsi2rxss->en_vcx ? "enabled" : "disabled",
+ xcsi2rxss->max_num_lanes,
+ xcsi2rxss->enable_active_lanes ? "dynamic" : "static",
+ xcsi2rxss->datatype);
+
+ return 0;
+}
+
+static int xcsi2rxss_probe(struct platform_device *pdev)
+{
+ struct v4l2_subdev *subdev;
+ struct xcsi2rxss_state *xcsi2rxss;
+ int num_clks = ARRAY_SIZE(xcsi2rxss_clks);
+ struct device *dev = &pdev->dev;
+ int irq, ret;
+
+ xcsi2rxss = devm_kzalloc(dev, sizeof(*xcsi2rxss), GFP_KERNEL);
+ if (!xcsi2rxss)
+ return -ENOMEM;
+
+ xcsi2rxss->dev = dev;
+
+ xcsi2rxss->clks = devm_kmemdup(dev, xcsi2rxss_clks,
+ sizeof(xcsi2rxss_clks), GFP_KERNEL);
+ if (!xcsi2rxss->clks)
+ return -ENOMEM;
+
+ /* Reset GPIO */
+ xcsi2rxss->rst_gpio = devm_gpiod_get_optional(dev, "video-reset",
+ GPIOD_OUT_HIGH);
+ if (IS_ERR(xcsi2rxss->rst_gpio)) {
+ if (PTR_ERR(xcsi2rxss->rst_gpio) != -EPROBE_DEFER)
+ dev_err(dev, "Video Reset GPIO not setup in DT");
+ return PTR_ERR(xcsi2rxss->rst_gpio);
+ }
+
+ ret = xcsi2rxss_parse_of(xcsi2rxss);
+ if (ret < 0)
+ return ret;
+
+ xcsi2rxss->iomem = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(xcsi2rxss->iomem))
+ return PTR_ERR(xcsi2rxss->iomem);
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+
+ ret = devm_request_threaded_irq(dev, irq, NULL,
+ xcsi2rxss_irq_handler, IRQF_ONESHOT,
+ dev_name(dev), xcsi2rxss);
+ if (ret) {
+ dev_err(dev, "Err = %d Interrupt handler reg failed!\n", ret);
+ return ret;
+ }
+
+ ret = clk_bulk_get(dev, num_clks, xcsi2rxss->clks);
+ if (ret)
+ return ret;
+
+ /* TODO: Enable/disable clocks at stream on/off time. */
+ ret = clk_bulk_prepare_enable(num_clks, xcsi2rxss->clks);
+ if (ret)
+ goto err_clk_put;
+
+ mutex_init(&xcsi2rxss->lock);
+
+ xcsi2rxss_hard_reset(xcsi2rxss);
+ xcsi2rxss_soft_reset(xcsi2rxss);
+
+ /* Initialize V4L2 subdevice and media entity */
+ xcsi2rxss->pads[XVIP_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
+ xcsi2rxss->pads[XVIP_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
+
+ /* Initialize the default format */
+ xcsi2rxss->default_format.code =
+ xcsi2rxss_get_nth_mbus(xcsi2rxss->datatype, 0);
+ xcsi2rxss->default_format.field = V4L2_FIELD_NONE;
+ xcsi2rxss->default_format.colorspace = V4L2_COLORSPACE_SRGB;
+ xcsi2rxss->default_format.width = XCSI_DEFAULT_WIDTH;
+ xcsi2rxss->default_format.height = XCSI_DEFAULT_HEIGHT;
+ xcsi2rxss->format = xcsi2rxss->default_format;
+
+ /* Initialize V4L2 subdevice and media entity */
+ subdev = &xcsi2rxss->subdev;
+ v4l2_subdev_init(subdev, &xcsi2rxss_ops);
+ subdev->dev = dev;
+ strscpy(subdev->name, dev_name(dev), sizeof(subdev->name));
+ subdev->flags |= V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_HAS_DEVNODE;
+ subdev->entity.ops = &xcsi2rxss_media_ops;
+ v4l2_set_subdevdata(subdev, xcsi2rxss);
+
+ ret = media_entity_pads_init(&subdev->entity, XCSI_MEDIA_PADS,
+ xcsi2rxss->pads);
+ if (ret < 0)
+ goto error;
+
+ platform_set_drvdata(pdev, xcsi2rxss);
+
+ ret = v4l2_async_register_subdev(subdev);
+ if (ret < 0) {
+ dev_err(dev, "failed to register subdev\n");
+ goto error;
+ }
+
+ return 0;
+error:
+ media_entity_cleanup(&subdev->entity);
+ mutex_destroy(&xcsi2rxss->lock);
+ clk_bulk_disable_unprepare(num_clks, xcsi2rxss->clks);
+err_clk_put:
+ clk_bulk_put(num_clks, xcsi2rxss->clks);
+ return ret;
+}
+
+static int xcsi2rxss_remove(struct platform_device *pdev)
+{
+ struct xcsi2rxss_state *xcsi2rxss = platform_get_drvdata(pdev);
+ struct v4l2_subdev *subdev = &xcsi2rxss->subdev;
+ int num_clks = ARRAY_SIZE(xcsi2rxss_clks);
+
+ v4l2_async_unregister_subdev(subdev);
+ media_entity_cleanup(&subdev->entity);
+ mutex_destroy(&xcsi2rxss->lock);
+ clk_bulk_disable_unprepare(num_clks, xcsi2rxss->clks);
+ clk_bulk_put(num_clks, xcsi2rxss->clks);
+
+ return 0;
+}
+
+static const struct of_device_id xcsi2rxss_of_id_table[] = {
+ { .compatible = "xlnx,mipi-csi2-rx-subsystem-5.0", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, xcsi2rxss_of_id_table);
+
+static struct platform_driver xcsi2rxss_driver = {
+ .driver = {
+ .name = "xilinx-csi2rxss",
+ .of_match_table = xcsi2rxss_of_id_table,
+ },
+ .probe = xcsi2rxss_probe,
+ .remove = xcsi2rxss_remove,
+};
+
+module_platform_driver(xcsi2rxss_driver);
+
+MODULE_AUTHOR("Vishal Sagar <vsagar@xilinx.com>");
+MODULE_DESCRIPTION("Xilinx MIPI CSI-2 Rx Subsystem Driver");
+MODULE_LICENSE("GPL v2");
--
2.1.1
^ permalink raw reply related
* Re: [PATCH v4 10/11] i2c: designware: Move reg-space remapping into a dedicated function
From: Andy Shevchenko @ 2020-05-27 13:58 UTC (permalink / raw)
To: Serge Semin
Cc: Jarkko Nikula, Wolfram Sang, Mika Westerberg, Serge Semin,
Alexey Malahov, Thomas Bogendoerfer, Rob Herring, linux-mips,
devicetree, linux-i2c, linux-kernel
In-Reply-To: <20200527120111.5781-11-Sergey.Semin@baikalelectronics.ru>
On Wed, May 27, 2020 at 03:01:10PM +0300, Serge Semin wrote:
> This is a preparation patch before adding a quirk with custom registers
> map creation required for the Baikal-T1 System I2C support.
Looks good. Though one nit below.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
>
> ---
>
> Changelog v3:
> - This is a new patch, which has been created due to declining the
> glue-layer approach.
>
> Changelog v4:
> - Use PTR_ERR_OR_ZERO() helper in the bt1_i2c_request_regs() method.
> - Discard devm_platform_get_and_ioremap_resource() utilization.
> ---
> drivers/i2c/busses/i2c-designware-platdrv.c | 18 +++++++++++++-----
> 1 file changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
> index ad292de2d260..061c8d506c7c 100644
> --- a/drivers/i2c/busses/i2c-designware-platdrv.c
> +++ b/drivers/i2c/busses/i2c-designware-platdrv.c
> @@ -108,6 +108,15 @@ static void dw_i2c_plat_pm_cleanup(struct dw_i2c_dev *dev)
> pm_runtime_put_noidle(dev->dev);
> }
>
> +static int dw_i2c_plat_request_regs(struct dw_i2c_dev *dev)
> +{
> + struct platform_device *pdev = to_platform_device(dev->dev);
> +
> + dev->base = devm_platform_ioremap_resource(pdev, 0);
> +
> + return PTR_ERR_OR_ZERO(dev->base);
> +}
> +
> static int dw_i2c_plat_probe(struct platform_device *pdev)
> {
> struct dw_i2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
> @@ -125,15 +134,14 @@ static int dw_i2c_plat_probe(struct platform_device *pdev)
> return -ENOMEM;
>
> dev->flags |= (uintptr_t)device_get_match_data(&pdev->dev);
It's related to previous patch, but I just realized that '|' is not needed
here. Care to amend in the previous patch?
> -
> - dev->base = devm_platform_ioremap_resource(pdev, 0);
> - if (IS_ERR(dev->base))
> - return PTR_ERR(dev->base);
> -
> dev->dev = &pdev->dev;
> dev->irq = irq;
> platform_set_drvdata(pdev, dev);
>
> + ret = dw_i2c_plat_request_regs(dev);
> + if (ret)
> + return ret;
> +
> dev->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
> if (IS_ERR(dev->rst))
> return PTR_ERR(dev->rst);
> --
> 2.26.2
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* [PATCH v14 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem
From: Vishal Sagar @ 2020-05-27 13:57 UTC (permalink / raw)
To: Hyun Kwon, laurent.pinchart, mchehab, robh+dt, mark.rutland,
Michal Simek, linux-media, devicetree, hans.verkuil,
linux-arm-kernel, linux-kernel, Dinesh Kumar, Sandip Kothari,
Luca Ceresoli, Jacopo Mondi
Cc: Vishal Sagar
In-Reply-To: <1590587839-129558-1-git-send-email-vishal.sagar@xilinx.com>
Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.
The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a
D-PHY in Rx mode and a Video Format Bridge.
Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Luca Ceresoli <luca@lucaceresoli.net>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
v14
- Removed xlnx,csi-pxl-format from required properties
- Added dependency of xlnx,csi-pxl-format on xlnx,vfb
- End the yaml file with ...
- Added Reviewed by Laurent
v13
- Based on Laurent's suggestions
- Fixed the datatypes values as minimum and maximum
- condition added for en-vcx property
v12
- Moved to yaml format
- Update CSI-2 and D-PHY
- Mention that bindings for D-PHY not here
- reset -> video-reset
v11
- Modify compatible string from 4.0 to 5.0
v10
- No changes
v9
- Fix xlnx,vfb description.
- s/Optional/Required endpoint property.
- Move data-lanes description from Ports to endpoint property section.
v8
- Added reset-gpios optional property to assert video_aresetn
v7
- Removed the control name from dt bindings
- Updated the example dt node name to csi2rx
v6
- Added "control" after V4L2_CID_XILINX_MIPICSISS_ACT_LANES as suggested by Luca
- Added reviewed by Rob Herring
v5
- Incorporated comments by Luca Cersoli
- Removed DPHY clock from description and example
- Removed bayer pattern from device tree MIPI CSI IP
doesn't deal with bayer pattern.
v4
- Added reviewed by Hyun Kwon
v3
- removed interrupt parent as suggested by Rob
- removed dphy clock
- moved vfb to optional properties
- Added required and optional port properties section
- Added endpoint property section
v2
- updated the compatible string to latest version supported
- removed DPHY related parameters
- added CSI v2.0 related property (including VCX for supporting upto 16
virtual channels).
- modified csi-pxl-format from string to unsigned int type where the value
is as per the CSI specification
- Defined port 0 and port 1 as sink and source ports.
- Removed max-lanes property as suggested by Rob and Sakari
.../bindings/media/xilinx/xlnx,csi2rxss.yaml | 237 +++++++++++++++++++++
1 file changed, 237 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
new file mode 100644
index 0000000..2282231
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
@@ -0,0 +1,237 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/xilinx/xlnx,csi2rxss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx MIPI CSI-2 Receiver Subsystem
+
+maintainers:
+ - Vishal Sagar <vishal.sagar@xilinx.com>
+
+description: |
+ The Xilinx MIPI CSI-2 Receiver Subsystem is used to capture MIPI CSI-2
+ traffic from compliant camera sensors and send the output as AXI4 Stream
+ video data for image processing.
+ The subsystem consists of a MIPI D-PHY in slave mode which captures the
+ data packets. This is passed along the MIPI CSI-2 Rx IP which extracts the
+ packet data. The optional Video Format Bridge (VFB) converts this data to
+ AXI4 Stream video data.
+ For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
+ Please note that this bindings includes only the MIPI CSI-2 Rx controller
+ and Video Format Bridge and not D-PHY.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - xlnx,mipi-csi2-rx-subsystem-5.0
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ description: List of clock specifiers
+ items:
+ - description: AXI Lite clock
+ - description: Video clock
+
+ clock-names:
+ items:
+ - const: lite_aclk
+ - const: video_aclk
+
+ xlnx,csi-pxl-format:
+ description: |
+ This denotes the CSI Data type selected in hw design.
+ Packets other than this data type (except for RAW8 and
+ User defined data types) will be filtered out.
+ Possible values are as below -
+ 0x1e - YUV4228B
+ 0x1f - YUV42210B
+ 0x20 - RGB444
+ 0x21 - RGB555
+ 0x22 - RGB565
+ 0x23 - RGB666
+ 0x24 - RGB888
+ 0x28 - RAW6
+ 0x29 - RAW7
+ 0x2a - RAW8
+ 0x2b - RAW10
+ 0x2c - RAW12
+ 0x2d - RAW14
+ 0x2e - RAW16
+ 0x2f - RAW20
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - anyOf:
+ - minimum: 0x1e
+ - maximum: 0x24
+ - minimum: 0x28
+ - maximum: 0x2f
+
+ xlnx,vfb:
+ type: boolean
+ description: Present when Video Format Bridge is enabled in IP configuration
+
+ xlnx,en-csi-v2-0:
+ type: boolean
+ description: Present if CSI v2 is enabled in IP configuration.
+
+ xlnx,en-vcx:
+ type: boolean
+ description: |
+ When present, there are maximum 16 virtual channels, else only 4.
+
+ xlnx,en-active-lanes:
+ type: boolean
+ description: |
+ Present if the number of active lanes can be re-configured at
+ runtime in the Protocol Configuration Register. Otherwise all lanes,
+ as set in IP configuration, are always active.
+
+ video-reset-gpios:
+ description: Optional specifier for a GPIO that asserts video_aresetn.
+ maxItems: 1
+
+ ports:
+ type: object
+
+ properties:
+ port@0:
+ type: object
+ description: |
+ Input / sink port node, single endpoint describing the
+ CSI-2 transmitter.
+
+ properties:
+ reg:
+ const: 0
+
+ endpoint:
+ type: object
+
+ properties:
+
+ data-lanes:
+ description: |
+ This is required only in the sink port 0 endpoint which
+ connects to MIPI CSI-2 source like sensor.
+ The possible values are -
+ 1 - For 1 lane enabled in IP.
+ 1 2 - For 2 lanes enabled in IP.
+ 1 2 3 - For 3 lanes enabled in IP.
+ 1 2 3 4 - For 4 lanes enabled in IP.
+ items:
+ - const: 1
+ - const: 2
+ - const: 3
+ - const: 4
+
+ remote-endpoint: true
+
+ required:
+ - data-lanes
+ - remote-endpoint
+
+ additionalProperties: false
+
+ additionalProperties: false
+
+ port@1:
+ type: object
+ description: |
+ Output / source port node, endpoint describing modules
+ connected the CSI-2 receiver.
+
+ properties:
+
+ reg:
+ const: 1
+
+ endpoint:
+ type: object
+
+ properties:
+
+ remote-endpoint: true
+
+ required:
+ - remote-endpoint
+
+ additionalProperties: false
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - ports
+
+allOf:
+ - if:
+ required:
+ - xlnx,vfb
+ then:
+ required:
+ - xlnx,csi-pxl-format
+ else:
+ properties:
+ xlnx,csi-pxl-format: false
+
+ - if:
+ not:
+ required:
+ - xlnx,en-csi-v2-0
+ then:
+ properties:
+ xlnx,en-vcx: false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ xcsi2rxss_1: csi2rx@a0020000 {
+ compatible = "xlnx,mipi-csi2-rx-subsystem-5.0";
+ reg = <0x0 0xa0020000 0x0 0x10000>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 95 4>;
+ xlnx,csi-pxl-format = <0x2a>;
+ xlnx,vfb;
+ xlnx,en-active-lanes;
+ xlnx,en-csi-v2-0;
+ xlnx,en-vcx;
+ clock-names = "lite_aclk", "video_aclk";
+ clocks = <&misc_clk_0>, <&misc_clk_1>;
+ video-reset-gpios = <&gpio 86 GPIO_ACTIVE_LOW>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ /* Sink port */
+ reg = <0>;
+ csiss_in: endpoint {
+ data-lanes = <1 2 3 4>;
+ /* MIPI CSI-2 Camera handle */
+ remote-endpoint = <&camera_out>;
+ };
+ };
+ port@1 {
+ /* Source port */
+ reg = <1>;
+ csiss_out: endpoint {
+ remote-endpoint = <&vproc_in>;
+ };
+ };
+ };
+ };
+...
--
2.1.1
^ permalink raw reply related
* [PATCH v14 0/2] Add support for Xilinx CSI2 Receiver Subsystem
From: Vishal Sagar @ 2020-05-27 13:57 UTC (permalink / raw)
To: Hyun Kwon, laurent.pinchart, mchehab, robh+dt, mark.rutland,
Michal Simek, linux-media, devicetree, hans.verkuil,
linux-arm-kernel, linux-kernel, Dinesh Kumar, Sandip Kothari,
Luca Ceresoli, Jacopo Mondi
Cc: Vishal Sagar
Xilinx MIPI CSI-2 Receiver Subsystem
------------------------------------
The Xilinx MIPI CSI-2 Receiver Subsystem Soft IP consists of a D-PHY which
gets the data, a CSI-2 Receiver controller which parses the data and
converts it into AXIS data.
This stream output maybe connected to a Xilinx Video Format Bridge.
The maximum number of lanes supported is fixed in the design.
The pixel format set in design acts as a filter allowing only the selected
data type or RAW8 data packets. The D-PHY register access can be gated in
the design.
The device driver registers the MIPI CSI-2 Rx Subsystem as a V4L2 sub device
having 2 pads. The sink pad is connected to the MIPI camera sensor and
output pad is connected to the video node.
Refer to xlnx,csi2rxss.yaml for device tree node details.
This driver helps enable the core, setting and handling interrupts.
It logs the number of events occurring according to their type between
streaming ON and OFF.
The Xilinx CSI-2 Rx Subsystem outputs an AXI4 Stream data which can be
used for image processing. This data follows the video formats mentioned
in Xilinx UG934 when the Video Format Bridge is enabled.
v14
- 1/2
- Removed xlnx,csi-pxl-format from required properties
- Added dependency of xlnx,csi-pxl-format on xlnx,vfb
- End the yaml file with ...
- Added Reviewed by Laurent
- 2/2
- Fixed condition to check ret in xcsi2rxss_start_stream
- Use BIT(i) instead of (1 << i)
- Moved "only sink pad format can be updated" in xcsi2rxss_set_format
- Added Reviewed by Luca Ceresoli
- Replace "tr" and "fa" to "true" and "false" in xcsi2rxss_log_status
- Remove setting streaming state to false in SLBF case. The app should
stop the streaming in case of SLBF.
- Made xcsi2rxss_enum_mbus_code() static as reported by kbuild bot
- Added Reviewed by Laurent
v13
- 1/2
- Based on Laurent's suggestions
- Fixed the datatypes values as minimum and maximum
- condition added for en-vcx property
- 2/2
- Based on Laurent's suggestions
- Removed unnecessary debug statement for vep
- Added TODO for clock to enable disable at streamon/off
- Fix for index to start from 0 for get_nth_mbus_format
- Removed macro XCSI_TIMEOUT_VAL
- Remove ndelay from hard reset
- Remove hard reset from irq handler
- Fix short packet fifo clear
- Add TODO for v4l2_subdev_notify for SLBF error
- Fix the enable condition in s_stream
- Fix condition in xcsi2rxss_set_format
- Fix enum_mbus_code for double enumeration of RAW8 Data type
- Removed core struct
- Added reviewed by Laurent
v12
- 1/2
- Moved to yaml format
- 2/2
- Changes done as suggested by Laurent Pinchart and Luca Ceresoli
- Removed unused macros
- No local storage of supported formats
- Dropped init mbus fmts and removed xcsi2rxss_init_mbus_fmts()
- XCSI_GET_BITSET_STR removed
- Add data type and mbus LUT
- Added xcsi2rxss_get_nth_mbus() and xcsi2rxss_get_dt()
- Replaced all core->dev with dev in dev_dbg() and related debug prints
- Replaced xcsi2rxss_log_ipconfig() with single line
- Removed small functions to enable/disable interrupts and core
- Now save remote subdev in state struct before streaming on
- Made xcsi2rxss_reset as soft_reset()
- Added hard reset using video-reset gpio
- 2 modes one with delay and another sleep
- Instead of reset-gpios it is not video-reset-gpios
- In irq handler
- Moved clearing of ISR up
- Dump / empty short packet fifo
- Irq handler is now threaded
- Added init_cfg pad ops and removed open()
- Updated xcsi2rxss_set_format(), xcsi2rxss_enum_mbus_code() to use the dt mbus lut
- xcsi2rxss_set_default_format() updated
- Moved mutex_init()
- Updated graph handling
- Removed unnecessary prints
- devm_platform_ioremap_resource() and platform_get_irq()
v11
- 1/2
- Modified the compatible string to 5.0 from 4.0
- 2/2
- Fixed changes as suggested by Sakari Ailus
- Removed VIDEO_XILINX from KConfig
- Minor formatting
- Start / Stop upstream sub-device in xcsi2rxss_start_stream()
and xcsi2rxss_stop_stream()
- Added v4l2_subdev_link_validate_default() in v4l2_subdev_pad_ops()
- Use fwnode_graph_get_endpoint_by_id() instead of parsing by self
- Set bus type as V4L2_MBUS_CSI2_DPHY in struct v4l2_fwnode_endpoint
- Remove num_clks from core. Instead use ARRAY_SIZE()
- Fixed SPDX header to GPL-2.0
- Update copyright year to 2020
v10
- 1/2
- No changes
- 2/2
- Removed all V4L2 controls and events.
- Now stop_stream() before toggling rst_gpio
- Updated init_mbus() to throw error on array out of bound access
- Added XADD_MBUS macro
- Make events and vcx_events as counters instead of structures
- Minor fixes in set_format() enum_mbus_code() as suggested by Sakari
v9
- 1/2
- Fix xlnx,vfb description.
- s/Optional/Required endpoint property.
- Move data-lanes description from Ports to endpoint property section.
- 2/2
- Moved all controls and events to xilinx-csi2rxss.h
- Updated name and description of controls and events
- Get control base address from v4l2-controls.h (0x10c0)
- Fix KConfig for dependency on VIDEO_XILINX
- Added enum_mbus_code() support
- Added default format to be returned on open()
- Mark variables are const
- Remove references to short packet in comments
- Add check for streaming before setting active lanes control
- strlcpy -> strscpy
- Fix xcsi2rxss_set_format()
v8
- 1/2
- Added reset-gpios optional property
- 2/2
- Use clk_bulk* APIs
- Add gpio reset for asserting video_aresetn when stream line buffer occurs
- Removed short packet related events and irq handling
- V4L2_EVENT_XLNXCSIRX_SPKT and V4L2_EVENT_XLNXCSIRX_SPKT_OVF removed
- Removed frame counter control V4L2_CID_XILINX_MIPICSISS_FRAME_COUNTER
and xcsi2rxss_g_volatile_ctrl()
- Minor formatting fixes
v7
- 1/2
- Removed the name of control from en-active-lanes as suggested by Sakari
- Updated the dt node name to csi2rx
- 2/2
- No change
v6
- 1/2
- Added minor comment by Luca
- Added Reviewed by Rob Herring
- 2/2
- No change
v5
- 1/2
- Removed the DPHY clock description and dt node.
- removed bayer pattern as CSI doesn't deal with it.
- 2/2
- removed bayer pattern as CSI doesn't deal with it.
- add YUV422 10bpc media bus format.
v4
- 1/2
- Added reviewed by Hyun Kwon
- 2/2
- Removed irq member from core structure
- Consolidated IP config prints in xcsi2rxss_log_ipconfig()
- Return -EINVAL in case of invalid ioctl
- Code formatting
- Added reviewed by Hyun Kwon
v3
- 1/2
- removed interrupt parent as suggested by Rob
- removed dphy clock
- moved vfb to optional properties
- Added required and optional port properties section
- Added endpoint property section
- 2/2
- Fixed comments given by Hyun.
- Removed DPHY 200 MHz clock. This will be controlled by DPHY driver
- Minor code formatting
- en_csi_v20 and vfb members removed from struct and made local to dt parsing
- lock description updated
- changed to ratelimited type for all dev prints in irq handler
- Removed YUV 422 10bpc media format
v2
- 1/2
- updated the compatible string to latest version supported
- removed DPHY related parameters
- added CSI v2.0 related property (including VCX for supporting upto 16
virtual channels).
- modified csi-pxl-format from string to unsigned int type where the value
is as per the CSI specification
- Defined port 0 and port 1 as sink and source ports.
- Removed max-lanes property as suggested by Rob and Sakari
- 2/2
- Fixed comments given by Hyun and Sakari.
- Made all bitmask using BIT() and GENMASK()
- Removed unused definitions
- Removed DPHY access. This will be done by separate DPHY PHY driver.
- Added support for CSI v2.0 for YUV 422 10bpc, RAW16, RAW20 and extra
virtual channels
- Fixed the ports as sink and source
- Now use the v4l2fwnode API to get number of data-lanes
- Added clock framework support
- Removed the close() function
- updated the set format function
- Support only VFB enabled config
Vishal Sagar (2):
media: dt-bindings: media: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem
media: v4l: xilinx: Add Xilinx MIPI CSI-2 Rx Subsystem driver
.../bindings/media/xilinx/xlnx,csi2rxss.yaml | 237 +++++
drivers/media/platform/xilinx/Kconfig | 7 +
drivers/media/platform/xilinx/Makefile | 1 +
drivers/media/platform/xilinx/xilinx-csi2rxss.c | 1111 ++++++++++++++++++++
4 files changed, 1356 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.yaml
create mode 100644 drivers/media/platform/xilinx/xilinx-csi2rxss.c
--
2.1.1
^ permalink raw reply
* Re: [PATCH v4 09/11] i2c: designware: Retrieve quirk flags as early as possible
From: Andy Shevchenko @ 2020-05-27 13:51 UTC (permalink / raw)
To: Serge Semin
Cc: Jarkko Nikula, Wolfram Sang, Mika Westerberg, Serge Semin,
Alexey Malahov, Thomas Bogendoerfer, Rob Herring, linux-mips,
devicetree, linux-i2c, linux-kernel
In-Reply-To: <20200527120111.5781-10-Sergey.Semin@baikalelectronics.ru>
On Wed, May 27, 2020 at 03:01:09PM +0300, Serge Semin wrote:
> Some platforms might need to activate the driver quirks at a very early
> probe stage. For instance, Baikal-T1 System I2C doesn't need to map the
> registers space as ones belong to the system controller. Instead it will
> request the syscon regmap from the parental DT node. In order to be able
> to do so let's retrieve the model flags right after the DW I2C private
> data is created.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: linux-mips@vger.kernel.org
> Cc: devicetree@vger.kernel.org
>
> ---
>
> Changelog v3:
> - This is a new patch, which has been created due to declining the
> glue-layer approach.
> ---
> drivers/i2c/busses/i2c-designware-platdrv.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-designware-platdrv.c b/drivers/i2c/busses/i2c-designware-platdrv.c
> index ca057aa9eac4..ad292de2d260 100644
> --- a/drivers/i2c/busses/i2c-designware-platdrv.c
> +++ b/drivers/i2c/busses/i2c-designware-platdrv.c
> @@ -124,6 +124,8 @@ static int dw_i2c_plat_probe(struct platform_device *pdev)
> if (!dev)
> return -ENOMEM;
>
> + dev->flags |= (uintptr_t)device_get_match_data(&pdev->dev);
> +
> dev->base = devm_platform_ioremap_resource(pdev, 0);
> if (IS_ERR(dev->base))
> return PTR_ERR(dev->base);
> @@ -146,8 +148,6 @@ static int dw_i2c_plat_probe(struct platform_device *pdev)
>
> i2c_dw_acpi_adjust_bus_speed(&pdev->dev);
>
> - dev->flags |= (uintptr_t)device_get_match_data(&pdev->dev);
> -
> if (pdev->dev.of_node)
> dw_i2c_of_configure(pdev);
>
> --
> 2.26.2
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH v4 08/11] i2c: designware: Convert driver to using regmap API
From: Andy Shevchenko @ 2020-05-27 13:50 UTC (permalink / raw)
To: Serge Semin
Cc: Jarkko Nikula, Wolfram Sang, Mika Westerberg, Serge Semin,
Alexey Malahov, Thomas Bogendoerfer, Rob Herring, devicetree,
linux-mips, linux-i2c, linux-kernel
In-Reply-To: <20200527120111.5781-9-Sergey.Semin@baikalelectronics.ru>
On Wed, May 27, 2020 at 03:01:08PM +0300, Serge Semin wrote:
> Seeing the DW I2C driver is using flags-based accessors with two
> conditional clauses it would be better to replace them with the regmap
> API IO methods and to initialize the regmap object with read/write
> callbacks specific to the controller registers map implementation. This
> will be also handy for the drivers with non-standard registers mapping
> (like an embedded into the Baikal-T1 System Controller DW I2C block, which
> glue-driver is a part of this series).
>
> As before the driver tries to detect the mapping setup at probe stage and
> creates a regmap object accordingly, which will be used by the rest of the
> code to correctly access the controller registers. In two places it was
> appropriate to convert the hand-written read-modify-write and
> read-poll-loop design patterns to the corresponding regmap API
> ready-to-use methods.
>
> Note the regmap IO methods return value is checked only at the probe
> stage. The rest of the code won't do this because basically we have
> MMIO-based regmap so non of the read/write methods can fail (this also
> won't be needed for the Baikal-T1-specific I2C controller).
Thanks! My comments below.
...
> #include <linux/export.h>
> #include <linux/i2c.h>
> #include <linux/interrupt.h>
> +#include <linux/regmap.h>
> #include <linux/io.h>
> #include <linux/kernel.h>
> #include <linux/module.h>
Please, keep ordered.
...
> +static int dw_reg_write_word(void *context, unsigned int reg, unsigned int val)
> +{
> + struct dw_i2c_dev *dev = context;
> +
> + writew_relaxed((u16)val, dev->base + reg);
> + writew_relaxed((u16)(val >> 16), dev->base + reg + 2);
What does explicit casting here help to?
I think you may drop it.
> + return 0;
> }
...
> #include <linux/errno.h>
> #include <linux/i2c.h>
> #include <linux/interrupt.h>
> +#include <linux/regmap.h>
> #include <linux/io.h>
> #include <linux/module.h>
> #include <linux/pm_runtime.h>
Order?
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: pinctrl: Add bindings for mscc,ocelot-sgpio
From: Linus Walleij @ 2020-05-27 13:45 UTC (permalink / raw)
To: Lars Povlsen
Cc: SoC Team, Rob Herring, Microchip Linux Driver Support,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:GPIO SUBSYSTEM, Linux ARM, linux-kernel@vger.kernel.org,
Alexandre Belloni
In-Reply-To: <87pnappzun.fsf@soft-dev15.microsemi.net>
On Wed, May 27, 2020 at 10:05 AM Lars Povlsen
<lars.povlsen@microchip.com> wrote:
> The only issue is that the gpios on the same "port" have restrictions on
> their status - they can only be enabled "all" or "none" for gpios that
> map to the same port. F.ex. gpio0, gpio32, gpio64 and gpio96 must all be
> enabled or disabled because at the hardware level you control the
> _port_.
This is fairly common. For example that an entire port/block share
a clock.
> But as I noted earlier, that could just be the driver enforcing
> this.
Yeps.
Yours,
Linus Walleij
^ permalink raw reply
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