* Re: [PATCH v3 4/5] regulator: qcom: Add labibb driver
From: Bjorn Andersson @ 2020-05-29 2:04 UTC (permalink / raw)
To: Sumit Semwal
Cc: agross, lgirdwood, broonie, robh+dt, nishakumari, linux-arm-msm,
linux-kernel, devicetree, kgunda, rnayak
In-Reply-To: <20200528154625.17742-5-sumit.semwal@linaro.org>
On Thu 28 May 08:46 PDT 2020, Sumit Semwal wrote:
> From: Nisha Kumari <nishakumari@codeaurora.org>
>
> Qualcomm platforms have LAB(LCD AMOLED Boost)/IBB(Inverting Buck Boost)
> regulators, labibb for short, which are used as power supply for
> LCD Mode displays.
>
> This patch adds labibb regulator driver for pmi8998 PMIC, found on
> SDM845 platforms.
>
> Signed-off-by: Nisha Kumari <nishakumari@codeaurora.org>
> Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
>
> --
> v2: sumits: reworked the driver for more common code, and addressed
> review comments from v1
> v3: sumits: addressed review comments from v2; moved to use core
> regulator features like enable_time, off_on_delay, and the newly
> added poll_enabled_time. Moved the check_enabled functionality
> to core framework via poll_enabled_time.
>
> ---
> drivers/regulator/Kconfig | 10 +
> drivers/regulator/Makefile | 1 +
> drivers/regulator/qcom-labibb-regulator.c | 224 ++++++++++++++++++++++
> 3 files changed, 235 insertions(+)
> create mode 100644 drivers/regulator/qcom-labibb-regulator.c
>
> diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
> index f4b72cb098ef..58704a9fd05d 100644
> --- a/drivers/regulator/Kconfig
> +++ b/drivers/regulator/Kconfig
> @@ -1167,5 +1167,15 @@ config REGULATOR_WM8994
> This driver provides support for the voltage regulators on the
> WM8994 CODEC.
>
> +config REGULATOR_QCOM_LABIBB
> + tristate "QCOM LAB/IBB regulator support"
> + depends on SPMI || COMPILE_TEST
> + help
> + This driver supports Qualcomm's LAB/IBB regulators present on the
> + Qualcomm's PMIC chip pmi8998. QCOM LAB and IBB are SPMI
> + based PMIC implementations. LAB can be used as positive
> + boost regulator and IBB can be used as a negative boost regulator
> + for LCD display panel.
> +
> endif
>
> diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
> index 6610ee001d9a..5b313786c0e8 100644
> --- a/drivers/regulator/Makefile
> +++ b/drivers/regulator/Makefile
> @@ -87,6 +87,7 @@ obj-$(CONFIG_REGULATOR_MT6323) += mt6323-regulator.o
> obj-$(CONFIG_REGULATOR_MT6358) += mt6358-regulator.o
> obj-$(CONFIG_REGULATOR_MT6380) += mt6380-regulator.o
> obj-$(CONFIG_REGULATOR_MT6397) += mt6397-regulator.o
> +obj-$(CONFIG_REGULATOR_QCOM_LABIBB) += qcom-labibb-regulator.o
> obj-$(CONFIG_REGULATOR_QCOM_RPM) += qcom_rpm-regulator.o
> obj-$(CONFIG_REGULATOR_QCOM_RPMH) += qcom-rpmh-regulator.o
> obj-$(CONFIG_REGULATOR_QCOM_SMD_RPM) += qcom_smd-regulator.o
> diff --git a/drivers/regulator/qcom-labibb-regulator.c b/drivers/regulator/qcom-labibb-regulator.c
> new file mode 100644
> index 000000000000..634d08461c6e
> --- /dev/null
> +++ b/drivers/regulator/qcom-labibb-regulator.c
> @@ -0,0 +1,225 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +// Copyright (c) 2020, The Linux Foundation. All rights reserved.
> +
> +#include <linux/module.h>
> +#include <linux/of_irq.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/regulator/driver.h>
> +#include <linux/regulator/of_regulator.h>
> +
> +#define REG_PERPH_TYPE 0x04
> +#define QCOM_LAB_TYPE 0x24
> +#define QCOM_IBB_TYPE 0x20
> +
> +#define REG_LABIBB_STATUS1 0x08
> +#define REG_LABIBB_ENABLE_CTL 0x46
> +#define LABIBB_STATUS1_VREG_OK_BIT BIT(7)
> +#define LABIBB_CONTROL_ENABLE BIT(7)
> +
> +#define LAB_ENABLE_CTL_MASK BIT(7)
> +#define IBB_ENABLE_CTL_MASK (BIT(7) | BIT(6))
> +
> +#define LABIBB_ENABLE_TIME 1000
> +#define LAB_POLL_ENABLED_TIME (LABIBB_ENABLE_TIME * 2)
> +#define IBB_POLL_ENABLED_TIME (LABIBB_ENABLE_TIME * 10)
> +#define LABIBB_OFF_ON_DELAY (8200)
> +
> +struct labibb_regulator {
> + struct regulator_desc desc;
> + struct device *dev;
> + struct regmap *regmap;
> + struct regulator_dev *rdev;
> + u16 base;
> + u8 type;
> +};
> +
> +struct labibb_regulator_data {
> + u16 base;
> + const char *name;
> + u8 type;
> + unsigned int poll_enabled_time;
> +};
> +
> +static int qcom_labibb_regulator_is_enabled(struct regulator_dev *rdev)
> +{
> + int ret;
> + unsigned int val;
> + struct labibb_regulator *reg = rdev_get_drvdata(rdev);
> +
> + ret = regmap_read(reg->regmap, reg->base + REG_LABIBB_STATUS1, &val);
> + if (ret < 0) {
> + dev_err(reg->dev, "Read register failed ret = %d\n", ret);
> + return ret;
> + }
> + return !!(val & LABIBB_STATUS1_VREG_OK_BIT);
> +}
> +
> +static int qcom_labibb_regulator_enable(struct regulator_dev *rdev)
> +{
> + int ret;
> + struct labibb_regulator *reg = rdev_get_drvdata(rdev);
> +
> + ret = regulator_enable_regmap(rdev);
> + if (ret < 0)
> + dev_err(reg->dev, "Write failed: enable %s regulator\n",
> + reg->desc.name);
If you return a negative value the various callers of
_regulator_do_enable() and _regulator_do_disable() will print an error
message for you.
As such you don't need these wrappers and should be able to just specify
regulator_enable_regmap and regulator_disable_regmap as you enable and
disable functions in qcom_labibb_ops directly.
> +
> + return ret;
> +}
> +
> +static int qcom_labibb_regulator_disable(struct regulator_dev *rdev)
> +{
> + int ret = 0;
> + struct labibb_regulator *reg = rdev_get_drvdata(rdev);
> +
> + ret = regulator_disable_regmap(rdev);
> + if (ret < 0)
> + dev_err(reg->dev, "Disable failed: disable %s\n",
> + reg->desc.name);
> +
> + return ret;
> +}
> +
> +static struct regulator_ops qcom_labibb_ops = {
> + .enable = qcom_labibb_regulator_enable,
> + .disable = qcom_labibb_regulator_disable,
> + .is_enabled = qcom_labibb_regulator_is_enabled,
> +};
> +
> +static int register_labibb_regulator(struct labibb_regulator *reg,
> + const struct labibb_regulator_data *reg_data,
> + struct device_node *of_node)
> +{
> + struct regulator_config cfg = {};
> +
> + reg->base = reg_data->base;
> + reg->type = reg_data->type;
> + reg->desc.enable_reg = reg->base + REG_LABIBB_ENABLE_CTL;
> + reg->desc.enable_val = LABIBB_CONTROL_ENABLE;
> + reg->desc.of_match = reg_data->name;
> + reg->desc.name = reg_data->name;
> + reg->desc.owner = THIS_MODULE;
> + reg->desc.type = REGULATOR_VOLTAGE;
> + reg->desc.ops = &qcom_labibb_ops;
> +
> + reg->desc.enable_time = LABIBB_ENABLE_TIME;
> + reg->desc.poll_enabled_time = reg_data->poll_enabled_time;
> + reg->desc.off_on_delay = LABIBB_OFF_ON_DELAY;
> +
> + cfg.dev = reg->dev;
> + cfg.driver_data = reg;
> + cfg.regmap = reg->regmap;
> + cfg.of_node = of_node;
> +
> + reg->rdev = devm_regulator_register(reg->dev, ®->desc, &cfg);
> + return PTR_ERR_OR_ZERO(reg->rdev);
If you change the return type to struct regulator_dev *, you can clean
this up by just:
return devm_regulator_register()
And then if (IS_ERR()) that in the caller.
> +}
> +
> +static const struct labibb_regulator_data pmi8998_labibb_data[] = {
> + {0xde00, "lab", QCOM_LAB_TYPE, LAB_POLL_ENABLED_TIME},
> + {0xdc00, "ibb", QCOM_IBB_TYPE, IBB_POLL_ENABLED_TIME},
> + { },
> +};
> +
> +static const struct of_device_id qcom_labibb_match[] = {
> + { .compatible = "qcom,pmi8998-lab-ibb", .data = &pmi8998_labibb_data},
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, qcom_labibb_match);
> +
> +static int qcom_labibb_regulator_probe(struct platform_device *pdev)
> +{
> + struct labibb_regulator *labibb_reg;
> + struct device *dev;
> + struct device_node *child;
> + const struct of_device_id *match;
> + const struct labibb_regulator_data *reg_data;
> + struct regmap *reg_regmap;
> + unsigned int type;
> + int ret;
> +
> + reg_regmap = dev_get_regmap(pdev->dev.parent, NULL);
> + if (!reg_regmap) {
> + dev_err(&pdev->dev, "Couldn't get parent's regmap\n");
> + return -ENODEV;
> + }
> +
> + dev = &pdev->dev;
Do this as you declare "dev" above.
> +
> + match = of_match_device(qcom_labibb_match, &pdev->dev);
> + if (!match)
> + return -ENODEV;
> +
> + for (reg_data = match->data; reg_data->name; reg_data++) {
> + child = of_get_child_by_name(pdev->dev.of_node, reg_data->name);
> +
> + /* TODO: This validates if the type of regulator is indeed
> + * what's mentioned in DT.
> + * I'm not sure if this is needed, but we'll keep it for now.
> + */
> + ret = regmap_read(reg_regmap, reg_data->base + REG_PERPH_TYPE,
> + &type);
> + if (ret < 0) {
> + dev_err(dev,
> + "Peripheral type read failed ret=%d\n",
> + ret);
> + return -EINVAL;
> + }
> +
> + if ((type != QCOM_LAB_TYPE) && (type != QCOM_IBB_TYPE)) {
Given that you don't actually validate the information in DT, but rather
just check that the data in the pmi8998_labibb_data is accurate this is
merely a sanity check during development. So I think you should reduce
this to:
if (WARN_ON(type != reg_data->type))
return -EINVAL;
You can thereby remove the TODO comment above as well.
What you should do though is check that "child" is not NULL - to catch
the case where the DT doesn't specify both lab and ibb.
> + dev_err(dev,
> + "qcom_labibb: unknown peripheral type\n");
> + return -EINVAL;
> + } else if (type != reg_data->type) {
> + dev_err(dev,
> + "qcom_labibb: type %x doesn't match DT %x\n",
> + type, reg_data->type);
> + return -EINVAL;
> + }
> +
> + labibb_reg = devm_kzalloc(&pdev->dev, sizeof(*labibb_reg),
> + GFP_KERNEL);
> + if (!labibb_reg)
> + return -ENOMEM;
> +
> + labibb_reg->regmap = reg_regmap;
> + labibb_reg->dev = dev;
> +
> + switch (reg_data->type) {
> + case QCOM_LAB_TYPE:
> + labibb_reg->desc.enable_mask = LAB_ENABLE_CTL_MASK;
All other parts of labibb_reg->desc are filled out inside
register_labibb_regulator(), pass the mask as an argument instead to
consolidate the setup.
> + break;
> +
> + case QCOM_IBB_TYPE:
> + labibb_reg->desc.enable_mask = IBB_ENABLE_CTL_MASK;
> + break;
> + }
> +
> + dev_info(dev, "Registering %s regulator\n", child->full_name);
> +
> + ret = register_labibb_regulator(labibb_reg, reg_data, child);
> + if (ret < 0) {
> + dev_err(dev,
> + "qcom_labibb: error registering %s : %d\n",
> + child->full_name, ret);
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static struct platform_driver qcom_labibb_regulator_driver = {
> + .driver = {
> + .name = "qcom-lab-ibb-regulator",
> + .of_match_table = qcom_labibb_match,
> + },
> + .probe = qcom_labibb_regulator_probe,
> +};
I think you should drop the tabs before the various = in this
definition.
Regards,
Bjorn
> +module_platform_driver(qcom_labibb_regulator_driver);
> +
> +MODULE_DESCRIPTION("Qualcomm labibb driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.26.2
>
^ permalink raw reply
* [PATCH V2] dt-bindings: regulator: Convert anatop regulator to json-schema
From: Anson Huang @ 2020-05-29 1:59 UTC (permalink / raw)
To: lgirdwood, broonie, robh+dt, paul.liu, linux-kernel, devicetree; +Cc: Linux-imx
Convert the anatop regulator binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
Changes since V1:
- remove definition of "regulator-name" which is a standrad property;
- add "unevaluatedProperties: false".
---
.../bindings/regulator/anatop-regulator.txt | 40 ---------
.../bindings/regulator/anatop-regulator.yaml | 94 ++++++++++++++++++++++
2 files changed, 94 insertions(+), 40 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/regulator/anatop-regulator.txt
create mode 100644 Documentation/devicetree/bindings/regulator/anatop-regulator.yaml
diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
deleted file mode 100644
index a3106c7..0000000
--- a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-Anatop Voltage regulators
-
-Required properties:
-- compatible: Must be "fsl,anatop-regulator"
-- regulator-name: A string used as a descriptive name for regulator outputs
-- anatop-reg-offset: Anatop MFD register offset
-- anatop-vol-bit-shift: Bit shift for the register
-- anatop-vol-bit-width: Number of bits used in the register
-- anatop-min-bit-val: Minimum value of this register
-- anatop-min-voltage: Minimum voltage of this regulator
-- anatop-max-voltage: Maximum voltage of this regulator
-
-Optional properties:
-- anatop-delay-reg-offset: Anatop MFD step time register offset
-- anatop-delay-bit-shift: Bit shift for the step time register
-- anatop-delay-bit-width: Number of bits used in the step time register
-- vin-supply: The supply for this regulator
-- anatop-enable-bit: Regulator enable bit offset
-
-Any property defined as part of the core regulator
-binding, defined in regulator.txt, can also be used.
-
-Example:
-
- regulator-vddpu {
- compatible = "fsl,anatop-regulator";
- regulator-name = "vddpu";
- regulator-min-microvolt = <725000>;
- regulator-max-microvolt = <1300000>;
- regulator-always-on;
- anatop-reg-offset = <0x140>;
- anatop-vol-bit-shift = <9>;
- anatop-vol-bit-width = <5>;
- anatop-delay-reg-offset = <0x170>;
- anatop-delay-bit-shift = <24>;
- anatop-delay-bit-width = <2>;
- anatop-min-bit-val = <1>;
- anatop-min-voltage = <725000>;
- anatop-max-voltage = <1300000>;
- };
diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.yaml b/Documentation/devicetree/bindings/regulator/anatop-regulator.yaml
new file mode 100644
index 0000000..e7b3abe
--- /dev/null
+++ b/Documentation/devicetree/bindings/regulator/anatop-regulator.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/regulator/anatop-regulator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Anatop Voltage Regulators
+
+maintainers:
+ - Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
+
+allOf:
+ - $ref: "regulator.yaml#"
+
+properties:
+ compatible:
+ const: fsl,anatop-regulator
+
+ regulator-name: true
+
+ anatop-reg-offset:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: u32 value representing the anatop MFD register offset.
+
+ anatop-vol-bit-shift:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: u32 value representing the bit shift for the register.
+
+ anatop-vol-bit-width:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: u32 value representing the number of bits used in the register.
+
+ anatop-min-bit-val:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: u32 value representing the minimum value of this register.
+
+ anatop-min-voltage:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: u32 value representing the minimum voltage of this regulator.
+
+ anatop-max-voltage:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: u32 value representing the maximum voltage of this regulator.
+
+ anatop-delay-reg-offset:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: u32 value representing the anatop MFD step time register offset.
+
+ anatop-delay-bit-shift:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: u32 value representing the bit shift for the step time register.
+
+ anatop-delay-bit-width:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: u32 value representing the number of bits used in the step time register.
+
+ anatop-enable-bit:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description: u32 value representing regulator enable bit offset.
+
+ vin-supply:
+ $ref: '/schemas/types.yaml#/definitions/phandle'
+ description: input supply phandle.
+
+required:
+ - compatible
+ - regulator-name
+ - anatop-reg-offset
+ - anatop-vol-bit-shift
+ - anatop-vol-bit-width
+ - anatop-min-bit-val
+ - anatop-min-voltage
+ - anatop-max-voltage
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ regulator-vddpu {
+ compatible = "fsl,anatop-regulator";
+ regulator-name = "vddpu";
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-always-on;
+ anatop-reg-offset = <0x140>;
+ anatop-vol-bit-shift = <9>;
+ anatop-vol-bit-width = <5>;
+ anatop-delay-reg-offset = <0x170>;
+ anatop-delay-bit-shift = <24>;
+ anatop-delay-bit-width = <2>;
+ anatop-min-bit-val = <1>;
+ anatop-min-voltage = <725000>;
+ anatop-max-voltage = <1300000>;
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH V3] dt-bindings: timer: Convert i.MX GPT to json-schema
From: Anson Huang @ 2020-05-29 2:04 UTC (permalink / raw)
To: daniel.lezcano, tglx, robh+dt, shawnguo, s.hauer, kernel,
festevam, linux-kernel, devicetree, linux-arm-kernel
Cc: Linux-imx
Convert the i.MX GPT binding to DT schema format using json-schema.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
Changes since V2:
- in compatible properties, group all the ones with the same
fallback to a single 'items' list using enum for the first entry.
---
.../devicetree/bindings/timer/fsl,imxgpt.txt | 45 --------------
.../devicetree/bindings/timer/fsl,imxgpt.yaml | 72 ++++++++++++++++++++++
2 files changed, 72 insertions(+), 45 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/timer/fsl,imxgpt.txt
create mode 100644 Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml
diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt b/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt
deleted file mode 100644
index 5d8fd5b..0000000
--- a/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-Freescale i.MX General Purpose Timer (GPT)
-
-Required properties:
-
-- compatible : should be one of following:
- for i.MX1:
- - "fsl,imx1-gpt";
- for i.MX21:
- - "fsl,imx21-gpt";
- for i.MX27:
- - "fsl,imx27-gpt", "fsl,imx21-gpt";
- for i.MX31:
- - "fsl,imx31-gpt";
- for i.MX25:
- - "fsl,imx25-gpt", "fsl,imx31-gpt";
- for i.MX50:
- - "fsl,imx50-gpt", "fsl,imx31-gpt";
- for i.MX51:
- - "fsl,imx51-gpt", "fsl,imx31-gpt";
- for i.MX53:
- - "fsl,imx53-gpt", "fsl,imx31-gpt";
- for i.MX6Q:
- - "fsl,imx6q-gpt", "fsl,imx31-gpt";
- for i.MX6DL:
- - "fsl,imx6dl-gpt";
- for i.MX6SL:
- - "fsl,imx6sl-gpt", "fsl,imx6dl-gpt";
- for i.MX6SX:
- - "fsl,imx6sx-gpt", "fsl,imx6dl-gpt";
-- reg : specifies base physical address and size of the registers.
-- interrupts : should be the gpt interrupt.
-- clocks : the clocks provided by the SoC to drive the timer, must contain
- an entry for each entry in clock-names.
-- clock-names : must include "ipg" entry first, then "per" entry.
-
-Example:
-
-gpt1: timer@10003000 {
- compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
- reg = <0x10003000 0x1000>;
- interrupts = <26>;
- clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
- <&clks IMX27_CLK_PER1_GATE>;
- clock-names = "ipg", "per";
-};
diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml
new file mode 100644
index 0000000..883f7f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/fsl,imxgpt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX General Purpose Timer (GPT)
+
+maintainers:
+ - Sascha Hauer <s.hauer@pengutronix.de>
+
+properties:
+ compatible:
+ oneOf:
+ - const: fsl,imx1-gpt
+ - const: fsl,imx21-gpt
+ - items:
+ - const: fsl,imx27-gpt
+ - const: fsl,imx21-gpt
+ - const: fsl,imx31-gpt
+ - items:
+ - enum:
+ - fsl,imx25-gpt
+ - fsl,imx50-gpt
+ - fsl,imx51-gpt
+ - fsl,imx53-gpt
+ - fsl,imx6q-gpt
+ - const: fsl,imx31-gpt
+ - const: fsl,imx6dl-gpt
+ - items:
+ - enum:
+ - fsl,imx6sl-gpt
+ - fsl,imx6sx-gpt
+ - const: fsl,imx6dl-gpt
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: SoC GPT ipg clock
+ - description: SoC GPT per clock
+
+ clock-names:
+ items:
+ - const: ipg
+ - const: per
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx27-clock.h>
+
+ timer@10003000 {
+ compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
+ reg = <0x10003000 0x1000>;
+ interrupts = <26>;
+ clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
+ <&clks IMX27_CLK_PER1_GATE>;
+ clock-names = "ipg", "per";
+ };
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v3 5/5] regulator: qcom: labibb: Add SC interrupt handling
From: Bjorn Andersson @ 2020-05-29 2:28 UTC (permalink / raw)
To: Sumit Semwal
Cc: agross, lgirdwood, broonie, robh+dt, nishakumari, linux-arm-msm,
linux-kernel, devicetree, kgunda, rnayak
In-Reply-To: <20200528154625.17742-6-sumit.semwal@linaro.org>
On Thu 28 May 08:46 PDT 2020, Sumit Semwal wrote:
> From: Nisha Kumari <nishakumari@codeaurora.org>
>
> Add Short circuit interrupt handling and recovery for the lab and
> ibb regulators on qcom platforms.
>
> The client panel drivers need to register for REGULATOR_EVENT_OVER_CURRENT
> notification which will be triggered on short circuit. They should
> try to enable the regulator once, and if it doesn't get enabled,
> handle shutting down the panel accordingly.
>
> Signed-off-by: Nisha Kumari <nishakumari@codeaurora.org>
It would be nice to see a short summary of your changes from the
original patch here, like:
[sumit: Changed this and that]
> Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
>
> --
> v2: sumits: reworked handling to user regmap_read_poll_timeout, and handle it
> per-regulator instead of clearing both lab and ibb errors on either irq
> triggering. Also added REGULATOR_EVENT_OVER_CURRENT handling and
> notification to clients.
> v3: sumits: updated as per review comments of v2: removed spurious check for
> irq in handler and some unused variables; inlined some of the code,
> omitted IRQF_TRIGGER_RISING as it's coming from DT.
>
> ---
> drivers/regulator/qcom-labibb-regulator.c | 92 +++++++++++++++++++++++
> 1 file changed, 92 insertions(+)
>
> diff --git a/drivers/regulator/qcom-labibb-regulator.c b/drivers/regulator/qcom-labibb-regulator.c
> index 634d08461c6e..695ffac71e81 100644
> --- a/drivers/regulator/qcom-labibb-regulator.c
> +++ b/drivers/regulator/qcom-labibb-regulator.c
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0-only
> // Copyright (c) 2020, The Linux Foundation. All rights reserved.
>
> +#include <linux/interrupt.h>
> #include <linux/module.h>
> #include <linux/of_irq.h>
> #include <linux/of.h>
> @@ -18,6 +19,7 @@
> #define REG_LABIBB_ENABLE_CTL 0x46
> #define LABIBB_STATUS1_VREG_OK_BIT BIT(7)
> #define LABIBB_CONTROL_ENABLE BIT(7)
> +#define LABIBB_STATUS1_SC_DETECT_BIT BIT(6)
>
> #define LAB_ENABLE_CTL_MASK BIT(7)
> #define IBB_ENABLE_CTL_MASK (BIT(7) | BIT(6))
> @@ -27,12 +29,17 @@
> #define IBB_POLL_ENABLED_TIME (LABIBB_ENABLE_TIME * 10)
> #define LABIBB_OFF_ON_DELAY (8200)
>
> +#define POLLING_SCP_DONE_INTERVAL_US 5000
> +#define POLLING_SCP_TIMEOUT 16000
> +
> struct labibb_regulator {
> struct regulator_desc desc;
> struct device *dev;
> struct regmap *regmap;
> struct regulator_dev *rdev;
> u16 base;
> + int sc_irq;
This is now a local variable in register_labibb_regulator().
> + int vreg_enabled;
bool is a better representation of this (and the vreg_ prefix doesn't
really add value).
> u8 type;
> };
>
> @@ -65,6 +72,8 @@ static int qcom_labibb_regulator_enable(struct regulator_dev *rdev)
> if (ret < 0)
> dev_err(reg->dev, "Write failed: enable %s regulator\n",
> reg->desc.name);
> + else
> + reg->vreg_enabled = 1;
No I see why you add these wrappers around the regmap in the previous
patch.
My request to not print an error message on enable/disable errors
remains.
>
> return ret;
> }
> @@ -78,6 +87,8 @@ static int qcom_labibb_regulator_disable(struct regulator_dev *rdev)
> if (ret < 0)
> dev_err(reg->dev, "Disable failed: disable %s\n",
> reg->desc.name);
> + else
> + reg->vreg_enabled = 0;
>
> return ret;
> }
> @@ -88,11 +99,70 @@ static struct regulator_ops qcom_labibb_ops = {
> .is_enabled = qcom_labibb_regulator_is_enabled,
> };
>
> +static irqreturn_t labibb_sc_err_handler(int irq, void *_reg)
> +{
> + int ret;
> + u16 reg;
> + unsigned int val;
> + struct labibb_regulator *labibb_reg = _reg;
> + bool in_sc_err, scp_done = false;
> +
> + ret = regmap_read(labibb_reg->regmap,
> + labibb_reg->base + REG_LABIBB_STATUS1, &val);
> + if (ret < 0) {
> + dev_err(labibb_reg->dev, "sc_err_irq: Read failed, ret=%d\n",
> + ret);
> + return IRQ_HANDLED;
> + }
> +
> + dev_dbg(labibb_reg->dev, "%s SC error triggered! STATUS1 = %d\n",
> + labibb_reg->desc.name, val);
> +
> + in_sc_err = !!(val & LABIBB_STATUS1_SC_DETECT_BIT);
> +
> + /*
> + * The SC(short circuit) fault would trigger PBS(Portable Batch
> + * System) to disable regulators for protection. This would
> + * cause the SC_DETECT status being cleared so that it's not
> + * able to get the SC fault status.
> + * Check if the regulator is enabled in the driver but
> + * disabled in hardware, this means a SC fault had happened
> + * and SCP handling is completed by PBS.
> + */
> + if (!in_sc_err) {
> +
Empty line
Regards,
Bjorn
> + reg = labibb_reg->base + REG_LABIBB_ENABLE_CTL;
> +
> + ret = regmap_read_poll_timeout(labibb_reg->regmap,
> + reg, val,
> + !(val & LABIBB_CONTROL_ENABLE),
> + POLLING_SCP_DONE_INTERVAL_US,
> + POLLING_SCP_TIMEOUT);
> +
> + if (!ret && labibb_reg->vreg_enabled) {
> + dev_dbg(labibb_reg->dev,
> + "%s has been disabled by SCP\n",
> + labibb_reg->desc.name);
> + scp_done = true;
> + }
> + }
> +
> + if (in_sc_err || scp_done) {
> + regulator_lock(labibb_reg->rdev);
> + regulator_notifier_call_chain(labibb_reg->rdev,
> + REGULATOR_EVENT_OVER_CURRENT,
> + NULL);
> + regulator_unlock(labibb_reg->rdev);
> + }
> + return IRQ_HANDLED;
> +}
> +
> static int register_labibb_regulator(struct labibb_regulator *reg,
> const struct labibb_regulator_data *reg_data,
> struct device_node *of_node)
> {
> struct regulator_config cfg = {};
> + int ret;
>
> reg->base = reg_data->base;
> reg->type = reg_data->type;
> @@ -108,6 +178,28 @@ static int register_labibb_regulator(struct labibb_regulator *reg,
> reg->desc.poll_enabled_time = reg_data->poll_enabled_time;
> reg->desc.off_on_delay = LABIBB_OFF_ON_DELAY;
>
> + reg->sc_irq = -EINVAL;
> + ret = of_irq_get_byname(of_node, "sc-err");
> + if (ret < 0) {
> + dev_err(reg->dev, "Unable to get sc-err, ret = %d\n",
> + ret);
> + return ret;
> + } else
> + reg->sc_irq = ret;
> +
> + if (reg->sc_irq > 0) {
> + ret = devm_request_threaded_irq(reg->dev,
> + reg->sc_irq,
> + NULL, labibb_sc_err_handler,
> + IRQF_ONESHOT,
> + "sc-err", reg);
> + if (ret) {
> + dev_err(reg->dev, "Failed to register sc-err irq ret=%d\n",
> + ret);
> + return ret;
> + }
> + }
> +
> cfg.dev = reg->dev;
> cfg.driver_data = reg;
> cfg.regmap = reg->regmap;
> --
> 2.26.2
>
^ permalink raw reply
* Question about "xxx,yyy" style property
From: Kuninori Morimoto @ 2020-05-29 2:41 UTC (permalink / raw)
To: Rob Herring
Cc: Liam Girdwood, Mark Brown, Mark Rutland, devicetree, alsa-devel,
linux-kernel
In-Reply-To: <20200528223916.GA804926@bogus>
The Subject was "Re: [PATCH] ASoC: dt-bindings: simple-card: care missing address #address-cells"
Hi Rob
I'm trying to create v2 of simple-card patch,
And got issue which I can't solve by myself.
I think "xxx,yyy" (= which has "," at the property name)
needs special care, but it is very un-understandable...
Now, I'm give up.
So, can I ask you 2 things about Yaml Doc "xxx,yyy" type property ?
========================
1) reference own definitions from "xxx,yyy"
========================
I guess "xxx,yyy" naming property needs to has "description", right ?
But, it is OK if it references "/schemas/xxxx"
--- OK ------
xxx,yyy:
description: xxx
$ref: /schemas/types.yaml#/definitions/phandle-array
-------------
but, will be error if it references own definitions
--- NG ------
xxx,yyy:
description: xxx
$ref: "#/definitions/mydef"
-------------
This is the related error
-- error(?) --
xxx.yaml: properties:xxx,yyy:\
$ref: '#/definitions/mydef' does not match 'types.yaml#[/]{0,1}definitions/.*'
--------------
# but, there is no problem if it was defined as "patternProperties"
Q. The "xxx,yyy" property can't references own definitions,
or needs some magical extra settings ??
========================
2) phandle for "xxx,yyy"
========================
I noticed that it seems "xxx,yyy" property can't be referenced.
Here, "xxx,yyy" has "type: object" and "additionalProperties: false"
(below didn't happen if it doesn't have "additionalProperties: false")
If "xxx,yyy" has phandle, but not referenced,
This is not a problem.
--- OK ---
...
foo = <&bar>;
...
xxx_yyy: xxx,yyy {
...
};
--------------
But will be error if it is referenced.
--- NG ---
foo = <&xxx_yyy>;
...
xxx_yyy: xxx,yyy {
...
};
------------
The error is
-- error ---
xxx.yaml: xxx.yyy: \
Additional properties are not allowed ('phandle' was unexpected)
------------
Q. The "xxx,yyy" needs magical settings to be referenced, or can't be ?
^ permalink raw reply
* Re: [PATCH 1/9] dt-bindings: clock: Convert i.MX5 clock to json-schema
From: Rob Herring @ 2020-05-29 2:45 UTC (permalink / raw)
To: Anson Huang
Cc: linux-arm-kernel, kernel, shawnguo, shc_work, devicetree,
mturquette, sboyd, festevam, linux-clk, linux-kernel, robh+dt,
Linux-imx, s.trumtrar, s.hauer
In-Reply-To: <1590650879-18288-2-git-send-email-Anson.Huang@nxp.com>
On Thu, 28 May 2020 15:27:51 +0800, Anson Huang wrote:
> Convert the i.MX5 clock binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> .../devicetree/bindings/clock/imx5-clock.txt | 28 ----------
> .../devicetree/bindings/clock/imx5-clock.yaml | 63 ++++++++++++++++++++++
> 2 files changed, 63 insertions(+), 28 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/imx5-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/imx5-clock.yaml
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH 2/9] dt-bindings: clock: Convert i.MX35 clock to json-schema
From: Rob Herring @ 2020-05-29 2:48 UTC (permalink / raw)
To: Anson Huang
Cc: shc_work, linux-arm-kernel, sboyd, s.hauer, Linux-imx, robh+dt,
linux-clk, linux-kernel, devicetree, s.trumtrar, kernel, shawnguo,
festevam, mturquette
In-Reply-To: <1590650879-18288-3-git-send-email-Anson.Huang@nxp.com>
On Thu, 28 May 2020 15:27:52 +0800, Anson Huang wrote:
> Convert the i.MX35 clock binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> .../devicetree/bindings/clock/imx35-clock.txt | 114 -----------------
> .../devicetree/bindings/clock/imx35-clock.yaml | 137 +++++++++++++++++++++
> 2 files changed, 137 insertions(+), 114 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/imx35-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/imx35-clock.yaml
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH 3/9] dt-bindings: clock: Convert i.MX31 clock to json-schema
From: Rob Herring @ 2020-05-29 2:48 UTC (permalink / raw)
To: Anson Huang
Cc: linux-arm-kernel, linux-kernel, shc_work, s.hauer, shawnguo,
devicetree, robh+dt, festevam, linux-clk, kernel, Linux-imx,
s.trumtrar, mturquette, sboyd
In-Reply-To: <1590650879-18288-4-git-send-email-Anson.Huang@nxp.com>
On Thu, 28 May 2020 15:27:53 +0800, Anson Huang wrote:
> Convert the i.MX31 clock binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> .../devicetree/bindings/clock/imx31-clock.txt | 90 ----------------
> .../devicetree/bindings/clock/imx31-clock.yaml | 118 +++++++++++++++++++++
> 2 files changed, 118 insertions(+), 90 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/imx31-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/imx31-clock.yaml
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH 3/4] mailbox: qcom: Add ipq6018 apcs compatible
From: kbuild test robot @ 2020-05-29 2:41 UTC (permalink / raw)
To: Sivaprakash Murugesan, agross, bjorn.andersson, robh+dt,
jassisinghbrar, linux-arm-msm, devicetree, linux-kernel
Cc: kbuild-all, clang-built-linux, Sivaprakash Murugesan
In-Reply-To: <1590583092-24290-4-git-send-email-sivaprak@codeaurora.org>
[-- Attachment #1: Type: text/plain, Size: 2169 bytes --]
Hi Sivaprakash,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on linus/master v5.7-rc7 next-20200528]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Sivaprakash-Murugesan/Add-ipq6018-apcs-mailbox-driver/20200527-204025
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: x86_64-randconfig-a004-20200528 (attached as .config)
compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project 2d068e534f1671459e1b135852c1b3c10502e929)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp@intel.com>
All warnings (new ones prefixed by >>, old ones prefixed by <<):
>> drivers/mailbox/qcom-apcs-ipc-mailbox.c:48:34: warning: unused variable 'apcs_clk_match_table' [-Wunused-const-variable]
static const struct of_device_id apcs_clk_match_table[] = {
^
1 warning generated.
vim +/apcs_clk_match_table +48 drivers/mailbox/qcom-apcs-ipc-mailbox.c
47
> 48 static const struct of_device_id apcs_clk_match_table[] = {
49 { .compatible = "qcom,ipq6018-apcs-apps-global", .data = "qcom,apss-ipq6018-clk", },
50 { .compatible = "qcom,msm8916-apcs-kpss-global", .data = "qcom-apcs-msm8916-clk", },
51 { .compatible = "qcom,qcs404-apcs-apps-global", .data = "qcom-apcs-msm8916-clk", },
52 {}
53 };
54
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 41054 bytes --]
^ permalink raw reply
* Re: [PATCH 2/6] arm64: dts: qcom: sm8250: add apps_smmu node
From: Bjorn Andersson @ 2020-05-29 2:48 UTC (permalink / raw)
To: Jonathan Marek
Cc: Sai Prakash Ranjan, linux-arm-msm, Andy Gross, Rob Herring,
devicetree, linux-kernel, linux-arm-msm-owner
In-Reply-To: <8f9a5750-7909-4be7-6780-198d8c242af3@marek.ca>
On Mon 25 May 04:53 PDT 2020, Jonathan Marek wrote:
[..]
> I guess the commit message is ambiguous, that's not what I meant. Is "Now
> that the kernel initializes the iommu, the bypass mappings set by the
> bootloader are cleared. Adding the iommus property is required so that new
> mappings are created for UFS." better?
>
This looks better, but it's actually not a bypass mapping that we
inherit from the bootloader, it's the stream mapping pointing to a
disabled (~ARM_SMMU_SCTLR_M) context bank. So when we wipe the stream
mappings we will fault on the unmatched stream - which secure world
"handles" for us...
As such, I think you should replace "bypass" with "stream".
Regards,
Bjorn
^ permalink raw reply
* Re: [PATCH 4/9] dt-bindings: clock: Convert i.MX28 clock to json-schema
From: Rob Herring @ 2020-05-29 2:51 UTC (permalink / raw)
To: Anson Huang
Cc: mturquette, Linux-imx, robh+dt, shawnguo, shc_work, s.trumtrar,
devicetree, s.hauer, kernel, linux-clk, linux-arm-kernel,
linux-kernel, festevam, sboyd
In-Reply-To: <1590650879-18288-5-git-send-email-Anson.Huang@nxp.com>
On Thu, 28 May 2020 15:27:54 +0800, Anson Huang wrote:
> Convert the i.MX28 clock binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> .../devicetree/bindings/clock/imx28-clock.txt | 93 -----------------
> .../devicetree/bindings/clock/imx28-clock.yaml | 113 +++++++++++++++++++++
> 2 files changed, 113 insertions(+), 93 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/imx28-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/imx28-clock.yaml
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH 5/9] dt-bindings: clock: Convert i.MX23 clock to json-schema
From: Rob Herring @ 2020-05-29 2:51 UTC (permalink / raw)
To: Anson Huang
Cc: s.hauer, mturquette, robh+dt, shc_work, linux-kernel, kernel,
linux-arm-kernel, festevam, linux-clk, Linux-imx, sboyd,
devicetree, s.trumtrar, shawnguo
In-Reply-To: <1590650879-18288-6-git-send-email-Anson.Huang@nxp.com>
On Thu, 28 May 2020 15:27:55 +0800, Anson Huang wrote:
> Convert the i.MX23 clock binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> .../devicetree/bindings/clock/imx23-clock.txt | 70 -----------------
> .../devicetree/bindings/clock/imx23-clock.yaml | 90 ++++++++++++++++++++++
> 2 files changed, 90 insertions(+), 70 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/imx23-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/imx23-clock.yaml
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH 6/9] dt-bindings: clock: Convert i.MX27 clock to json-schema
From: Rob Herring @ 2020-05-29 2:52 UTC (permalink / raw)
To: Anson Huang
Cc: linux-arm-kernel, devicetree, festevam, robh+dt, sboyd, shawnguo,
Linux-imx, linux-clk, linux-kernel, s.trumtrar, kernel, shc_work,
mturquette, s.hauer
In-Reply-To: <1590650879-18288-7-git-send-email-Anson.Huang@nxp.com>
On Thu, 28 May 2020 15:27:56 +0800, Anson Huang wrote:
> Convert the i.MX27 clock binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> .../devicetree/bindings/clock/imx27-clock.txt | 27 -----------
> .../devicetree/bindings/clock/imx27-clock.yaml | 53 ++++++++++++++++++++++
> 2 files changed, 53 insertions(+), 27 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/imx27-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/imx27-clock.yaml
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH 7/9] dt-bindings: clock: Convert i.MX25 clock to json-schema
From: Rob Herring @ 2020-05-29 2:53 UTC (permalink / raw)
To: Anson Huang
Cc: kernel, linux-clk, s.hauer, mturquette, devicetree, linux-kernel,
sboyd, s.trumtrar, linux-arm-kernel, festevam, robh+dt, Linux-imx,
shawnguo, shc_work
In-Reply-To: <1590650879-18288-8-git-send-email-Anson.Huang@nxp.com>
On Thu, 28 May 2020 15:27:57 +0800, Anson Huang wrote:
> Convert the i.MX25 clock binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> .../devicetree/bindings/clock/imx25-clock.txt | 160 ------------------
> .../devicetree/bindings/clock/imx25-clock.yaml | 184 +++++++++++++++++++++
> 2 files changed, 184 insertions(+), 160 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/imx25-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/imx25-clock.yaml
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH 8/9] dt-bindings: clock: Convert i.MX21 clock to json-schema
From: Rob Herring @ 2020-05-29 2:53 UTC (permalink / raw)
To: Anson Huang
Cc: s.trumtrar, linux-kernel, sboyd, shawnguo, festevam, linux-clk,
robh+dt, devicetree, Linux-imx, kernel, mturquette, s.hauer,
shc_work, linux-arm-kernel
In-Reply-To: <1590650879-18288-9-git-send-email-Anson.Huang@nxp.com>
On Thu, 28 May 2020 15:27:58 +0800, Anson Huang wrote:
> Convert the i.MX21 clock binding to DT schema format using json-schema,
> can NOT find any CCM interrupt info from reference manual and DT file,
> so interrupts property is removed from original binding doc.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> .../devicetree/bindings/clock/imx21-clock.txt | 27 ------------
> .../devicetree/bindings/clock/imx21-clock.yaml | 49 ++++++++++++++++++++++
> 2 files changed, 49 insertions(+), 27 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/imx21-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/imx21-clock.yaml
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH 1/6] arm64: dts: qcom: sm8150: add apps_smmu node
From: Bjorn Andersson @ 2020-05-29 2:52 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20200524023815.21789-2-jonathan@marek.ca>
On Sat 23 May 19:38 PDT 2020, Jonathan Marek wrote:
> Add the apps_smmu node for sm8150. Note that adding the iommus field for
> UFS is required because initializing the iommu removes the bypass mapping
> that created by the bootloader.
>
Unrelated to the patch itself; how do you disable the splash screen on
8150? "fastboot oem select-display-panel none" doesn't seem to work for
me on the MTP - and hence this would prevent my device from booting.
Thanks,
Bjorn
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 91 ++++++++++++++++++++++++++++
> 1 file changed, 91 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> index a36512d1f6a1..acb839427b12 100644
> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> @@ -442,6 +442,8 @@ ufs_mem_hc: ufshc@1d84000 {
> resets = <&gcc GCC_UFS_PHY_BCR>;
> reset-names = "rst";
>
> + iommus = <&apps_smmu 0x300 0>;
> +
> clock-names =
> "core_clk",
> "bus_aggr_clk",
> @@ -706,6 +708,7 @@ usb_1_dwc3: dwc3@a600000 {
> compatible = "snps,dwc3";
> reg = <0 0x0a600000 0 0xcd00>;
> interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> + iommus = <&apps_smmu 0x140 0>;
> snps,dis_u2_susphy_quirk;
> snps,dis_enblslpm_quirk;
> phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
> @@ -742,6 +745,94 @@ spmi_bus: spmi@c440000 {
> cell-index = <0>;
> };
>
> + apps_smmu: iommu@15000000 {
> + compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
> + reg = <0 0x15000000 0 0x100000>;
> + #iommu-cells = <2>;
> + #global-interrupts = <1>;
> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> remoteproc_adsp: remoteproc@17300000 {
> compatible = "qcom,sm8150-adsp-pas";
> reg = <0x0 0x17300000 0x0 0x4040>;
> --
> 2.26.1
>
^ permalink raw reply
* Re: [PATCH 9/9] dt-bindings: clock: Convert i.MX1 clock to json-schema
From: Rob Herring @ 2020-05-29 2:54 UTC (permalink / raw)
To: Anson Huang
Cc: shawnguo, kernel, festevam, s.trumtrar, s.hauer, mturquette,
shc_work, linux-kernel, robh+dt, linux-arm-kernel, Linux-imx,
devicetree, sboyd, linux-clk
In-Reply-To: <1590650879-18288-10-git-send-email-Anson.Huang@nxp.com>
On Thu, 28 May 2020 15:27:59 +0800, Anson Huang wrote:
> Convert the i.MX1 clock binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> .../devicetree/bindings/clock/imx1-clock.txt | 26 ------------
> .../devicetree/bindings/clock/imx1-clock.yaml | 49 ++++++++++++++++++++++
> 2 files changed, 49 insertions(+), 26 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/clock/imx1-clock.txt
> create mode 100644 Documentation/devicetree/bindings/clock/imx1-clock.yaml
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH v2] of/fdt: Remove redundant kbasename function call
From: Rob Herring @ 2020-05-29 2:57 UTC (permalink / raw)
To: Qi Zheng; +Cc: devicetree, frowand.list, robh+dt, linux-kernel
In-Reply-To: <20200528132541.463300-1-arch0.zheng@gmail.com>
On Thu, 28 May 2020 21:25:41 +0800, Qi Zheng wrote:
> For version 1 to 3 of the device tree, this is the node full
> path as a zero terminated string, starting with "/". The
> following equation will not hold, since the node name has
> been processed in the fdt_get_name().
>
> *pathp == '/'
>
> For version 16 and later, this is the node unit name only
> (or an empty string for the root node). So the above
> equation will still not hold.
>
> So the kbasename() is redundant, just remove it.
>
> Signed-off-by: Qi Zheng <arch0.zheng@gmail.com>
> ---
>
> Change in v2:
> remove another kbasename() also.
>
> drivers/of/fdt.c | 4 ----
> 1 file changed, 4 deletions(-)
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH] dt-bindings: timer: renesas: mtu2: Convert to json-schema
From: Rob Herring @ 2020-05-29 2:57 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Thomas Gleixner, devicetree, Rob Herring, Daniel Lezcano,
linux-kernel, linux-renesas-soc, Laurent Pinchart
In-Reply-To: <20200528133033.4191-1-geert+renesas@glider.be>
On Thu, 28 May 2020 15:30:33 +0200, Geert Uytterhoeven wrote:
> Convert the Renesas Multi-Function Timer Pulse Unit 2 (MTU2) Device Tree
> binding documentation to json-schema.
>
> Add missing properties.
> Update the example to match reality.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> .../bindings/timer/renesas,mtu2.txt | 42 ----------
> .../bindings/timer/renesas,mtu2.yaml | 76 +++++++++++++++++++
> 2 files changed, 76 insertions(+), 42 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/timer/renesas,mtu2.txt
> create mode 100644 Documentation/devicetree/bindings/timer/renesas,mtu2.yaml
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH] dt-bindings: sound: tlv320adcx140: Fix dt-binding-check issue
From: Rob Herring @ 2020-05-29 2:58 UTC (permalink / raw)
To: Dan Murphy
Cc: lgirdwood, broonie, perex, tiwai, alsa-devel, linux-kernel,
devicetree
In-Reply-To: <20200528144711.18065-1-dmurphy@ti.com>
On Thu, May 28, 2020 at 09:47:11AM -0500, Dan Murphy wrote:
> Fix dt-binding-check issue
>
> ti,gpi-config:0:0: 4 is greater than the maximum of 1
> ti,gpi-config:0:1: 5 is greater than the maximum of 1
> ti,gpi-config:0:2: 6 is greater than the maximum of 1
> ti,gpi-config:0:3: 7 is greater than the maximum of 1
>
> Reported-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Dan Murphy <dmurphy@ti.com>
> ---
> Documentation/devicetree/bindings/sound/tlv320adcx140.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Thanks for the quick fix.
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v3 0/2] CH7322 CEC controller driver
From: Jeff Chase @ 2020-05-29 3:00 UTC (permalink / raw)
To: linux-media; +Cc: mchehab, hverkuil-cisco, robh+dt, devicetree, Jeff Chase
Add device driver and device tree bindings for a Chrontel CEC
conroller. This is an I2C device that can send and receive CEC
messages.
Changes from v2:
- fix formatting errors
- mask and unmask interrupt in cec adapter enable
Changes from v1:
- fix formatpatch.pl --strict errors
- additional comments
- enable and program logical address register
- add flags to aid interpreting transmit done status
- move ch7322 out of devicetree trivial devices
Jeff Chase (2):
dt-bindings: Add ch7322 media i2c device
media: cec: i2c: ch7322: Add ch7322 CEC controller driver
.../bindings/media/i2c/chrontel,ch7322.yaml | 65 +++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 8 +
drivers/media/cec/Kconfig | 1 +
drivers/media/cec/Makefile | 2 +-
drivers/media/cec/i2c/Kconfig | 14 +
drivers/media/cec/i2c/Makefile | 5 +
drivers/media/cec/i2c/ch7322.c | 523 ++++++++++++++++++
8 files changed, 619 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/media/i2c/chrontel,ch7322.yaml
create mode 100644 drivers/media/cec/i2c/Kconfig
create mode 100644 drivers/media/cec/i2c/Makefile
create mode 100644 drivers/media/cec/i2c/ch7322.c
--
2.27.0.rc0.183.gde8f92d652-goog
^ permalink raw reply
* [PATCH v3 2/2] media: cec: i2c: ch7322: Add ch7322 CEC controller driver
From: Jeff Chase @ 2020-05-29 3:00 UTC (permalink / raw)
To: linux-media; +Cc: mchehab, hverkuil-cisco, robh+dt, devicetree, Jeff Chase
In-Reply-To: <20200529030012.254592-1-jnchase@google.com>
Add a CEC device driver for the Chrontel ch7322 CEC conroller.
This is an I2C device capable of sending and receiving CEC messages.
Signed-off-by: Jeff Chase <jnchase@google.com>
---
MAINTAINERS | 1 +
drivers/media/cec/Kconfig | 1 +
drivers/media/cec/Makefile | 2 +-
drivers/media/cec/i2c/Kconfig | 14 +
drivers/media/cec/i2c/Makefile | 5 +
drivers/media/cec/i2c/ch7322.c | 523 +++++++++++++++++++++++++++++++++
6 files changed, 545 insertions(+), 1 deletion(-)
create mode 100644 drivers/media/cec/i2c/Kconfig
create mode 100644 drivers/media/cec/i2c/Makefile
create mode 100644 drivers/media/cec/i2c/ch7322.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 34c6d30e61e5..43e876395686 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4053,6 +4053,7 @@ L: linux-media@vger.kernel.org
S: Maintained
T: git git://linuxtv.org/media_tree.git
F: Documentation/devicetree/bindings/media/i2c/chontel,ch7322.yaml
+F: drivers/media/cec/i2c/ch7322.c
CIRRUS LOGIC AUDIO CODEC DRIVERS
M: James Schulman <james.schulman@cirrus.com>
diff --git a/drivers/media/cec/Kconfig b/drivers/media/cec/Kconfig
index eea74b7cfa8c..3e934aa239ab 100644
--- a/drivers/media/cec/Kconfig
+++ b/drivers/media/cec/Kconfig
@@ -33,6 +33,7 @@ menuconfig MEDIA_CEC_SUPPORT
adapter that supports HDMI CEC.
if MEDIA_CEC_SUPPORT
+source "drivers/media/cec/i2c/Kconfig"
source "drivers/media/cec/platform/Kconfig"
source "drivers/media/cec/usb/Kconfig"
endif
diff --git a/drivers/media/cec/Makefile b/drivers/media/cec/Makefile
index 74e80e1b3571..23539339bc81 100644
--- a/drivers/media/cec/Makefile
+++ b/drivers/media/cec/Makefile
@@ -1,2 +1,2 @@
# SPDX-License-Identifier: GPL-2.0
-obj-y += core/ platform/ usb/
+obj-y += core/ i2c/ platform/ usb/
diff --git a/drivers/media/cec/i2c/Kconfig b/drivers/media/cec/i2c/Kconfig
new file mode 100644
index 000000000000..e445ca2110b3
--- /dev/null
+++ b/drivers/media/cec/i2c/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# I2C drivers
+
+config CEC_CH7322
+ tristate "Chrontel CH7322 CEC controller"
+ select I2C
+ select REGMAP_I2C
+ select CEC_CORE
+ help
+ This is a driver for the Chrontel CH7322 CEC controller. It uses the
+ generic CEC framework interface.
+ CEC bus is present in the HDMI connector and enables communication
+ between compatible devices.
diff --git a/drivers/media/cec/i2c/Makefile b/drivers/media/cec/i2c/Makefile
new file mode 100644
index 000000000000..d7496dfd0fa4
--- /dev/null
+++ b/drivers/media/cec/i2c/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the CEC I2C device drivers.
+#
+obj-$(CONFIG_CEC_CH7322) += ch7322.o
diff --git a/drivers/media/cec/i2c/ch7322.c b/drivers/media/cec/i2c/ch7322.c
new file mode 100644
index 000000000000..dd54df61a522
--- /dev/null
+++ b/drivers/media/cec/i2c/ch7322.c
@@ -0,0 +1,523 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for the Chrontel CH7322 CEC Controller
+ *
+ * Copyright 2020 Google LLC.
+ */
+
+/*
+ * Notes
+ *
+ * - This device powers on in Auto Mode which has limited functionality. This
+ * driver disables Auto Mode when it attaches.
+ *
+ */
+
+#include <linux/cec.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/regmap.h>
+#include <media/cec.h>
+
+#define CH7322_WRITE 0x00
+#define CH7322_WRITE_MSENT 0x80
+#define CH7322_WRITE_BOK 0x40
+#define CH7322_WRITE_NMASK 0x0f
+
+/* Write buffer is 0x01-0x10 */
+#define CH7322_WRBUF 0x01
+#define CH7322_WRBUF_LEN 0x10
+
+#define CH7322_READ 0x40
+#define CH7322_READ_NRDT 0x80
+#define CH7322_READ_MSENT 0x20
+#define CH7322_READ_NMASK 0x0f
+
+/* Read buffer is 0x41-0x50 */
+#define CH7322_RDBUF 0x41
+#define CH7322_RDBUF_LEN 0x10
+
+#define CH7322_MODE 0x11
+#define CH7322_MODE_AUTO 0x78
+#define CH7322_MODE_SW 0xb5
+
+#define CH7322_RESET 0x12
+#define CH7322_RESET_RST 0x00
+
+#define CH7322_POWER 0x13
+#define CH7322_POWER_FPD 0x04
+
+#define CH7322_CFG0 0x17
+#define CH7322_CFG0_EOBEN 0x40
+#define CH7322_CFG0_PEOB 0x20
+#define CH7322_CFG0_CLRSPP 0x10
+#define CH7322_CFG0_FLOW 0x08
+
+#define CH7322_CFG1 0x1a
+#define CH7322_CFG1_STDBYO 0x04
+#define CH7322_CFG1_HPBP 0x02
+#define CH7322_CFG1_PIO 0x01
+
+#define CH7322_INTCTL 0x1b
+#define CH7322_INTCTL_INTPB 0x80
+#define CH7322_INTCTL_STDBY 0x40
+#define CH7322_INTCTL_HPDFALL 0x20
+#define CH7322_INTCTL_HPDRISE 0x10
+#define CH7322_INTCTL_RXMSG 0x08
+#define CH7322_INTCTL_TXMSG 0x04
+#define CH7322_INTCTL_NEWPHA 0x02
+#define CH7322_INTCTL_ERROR 0x01
+
+#define CH7322_DVCLKFNH 0x1d
+#define CH7322_DVCLKFNL 0x1e
+
+#define CH7322_CTL 0x31
+#define CH7322_CTL_FSTDBY 0x80
+#define CH7322_CTL_PLSEN 0x40
+#define CH7322_CTL_PLSPB 0x20
+#define CH7322_CTL_SPADL 0x10
+#define CH7322_CTL_HINIT 0x08
+#define CH7322_CTL_WPHYA 0x04
+#define CH7322_CTL_H1T 0x02
+#define CH7322_CTL_S1T 0x01
+
+#define CH7322_PAWH 0x32
+#define CH7322_PAWL 0x33
+
+#define CH7322_ADDLW 0x34
+#define CH7322_ADDLW_MASK 0xf0
+
+#define CH7322_ADDLR 0x3d
+#define CH7322_ADDLR_HPD 0x80
+#define CH7322_ADDLR_MASK 0x0f
+
+#define CH7322_INTDATA 0x3e
+#define CH7322_INTDATA_MODE 0x80
+#define CH7322_INTDATA_STDBY 0x40
+#define CH7322_INTDATA_HPDFALL 0x20
+#define CH7322_INTDATA_HPDRISE 0x10
+#define CH7322_INTDATA_RXMSG 0x08
+#define CH7322_INTDATA_TXMSG 0x04
+#define CH7322_INTDATA_NEWPHA 0x02
+#define CH7322_INTDATA_ERROR 0x01
+
+#define CH7322_EVENT 0x3F
+#define CH7322_EVENT_TXERR 0x80
+#define CH7322_EVENT_HRST 0x40
+#define CH7322_EVENT_HFST 0x20
+#define CH7322_EVENT_PHACHG 0x10
+#define CH7322_EVENT_ACTST 0x08
+#define CH7322_EVENT_PHARDY 0x04
+#define CH7322_EVENT_BSOK 0x02
+#define CH7322_EVENT_ERRADCF 0x01
+
+#define CH7322_DID 0x51
+#define CH7322_DID_CH7322 0x5b
+#define CH7322_DID_CH7323 0x5f
+
+#define CH7322_REVISIONID 0x52
+
+#define CH7322_PARH 0x53
+#define CH7322_PARL 0x54
+
+#define CH7322_IOCFG2 0x75
+#define CH7322_IOCFG_CIO 0x80
+#define CH7322_IOCFG_IOCFGMASK 0x78
+#define CH7322_IOCFG_AUDIO 0x04
+#define CH7322_IOCFG_SPAMST 0x02
+#define CH7322_IOCFG_SPAMSP 0x01
+
+#define CH7322_CTL3 0x7b
+#define CH7322_CTL3_SWENA 0x80
+#define CH7322_CTL3_FC_INIT 0x40
+#define CH7322_CTL3_SML_FL 0x20
+#define CH7322_CTL3_SM_RDST 0x10
+#define CH7322_CTL3_SPP_CIAH 0x08
+#define CH7322_CTL3_SPP_CIAL 0x04
+#define CH7322_CTL3_SPP_ACTH 0x02
+#define CH7322_CTL3_SPP_ACTL 0x01
+
+/* BOK status means NACK */
+#define CH7322_TX_FLAG_NACK BIT(0)
+/* Device will retry automatically */
+#define CH7322_TX_FLAG_RETRY BIT(1)
+
+struct ch7322 {
+ struct i2c_client *i2c;
+ struct regmap *regmap;
+ struct cec_adapter *cec;
+ struct mutex mutex; /* device access mutex */
+ u8 tx_flags;
+};
+
+static const struct regmap_config ch7322_regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = 0x7f,
+ .disable_locking = true,
+};
+
+static int ch7322_unmask_interrupt(struct ch7322 *ch7322)
+{
+ int ret;
+
+ mutex_lock(&ch7322->mutex);
+ ret = regmap_write(ch7322->regmap, CH7322_INTCTL, 0xff);
+ mutex_unlock(&ch7322->mutex);
+
+ return ret;
+}
+
+static int ch7322_mask_interrupt(struct ch7322 *ch7322)
+{
+ int ret;
+
+ mutex_lock(&ch7322->mutex);
+ ret = regmap_write(ch7322->regmap, CH7322_INTCTL, CH7322_INTCTL_INTPB);
+ mutex_unlock(&ch7322->mutex);
+
+ return ret;
+}
+
+static int ch7322_send_message(struct ch7322 *ch7322, const struct cec_msg *msg)
+{
+ unsigned int val;
+ unsigned int len = msg->len;
+ int ret;
+ int i;
+
+ WARN_ON(!mutex_is_locked(&ch7322->mutex));
+
+ if (len > CH7322_WRBUF_LEN || len < 1)
+ return -EINVAL;
+
+ ret = regmap_read(ch7322->regmap, CH7322_WRITE, &val);
+ if (ret)
+ return ret;
+
+ /* Buffer not ready */
+ if (!(val & CH7322_WRITE_MSENT))
+ return -EBUSY;
+
+ if (cec_msg_opcode(msg) == -1 &&
+ cec_msg_initiator(msg) == cec_msg_destination(msg)) {
+ ch7322->tx_flags = CH7322_TX_FLAG_NACK | CH7322_TX_FLAG_RETRY;
+ } else if (cec_msg_is_broadcast(msg)) {
+ ch7322->tx_flags = CH7322_TX_FLAG_NACK;
+ } else {
+ ch7322->tx_flags = CH7322_TX_FLAG_RETRY;
+ }
+
+ ret = regmap_write(ch7322->regmap, CH7322_WRITE, len - 1);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < len; i++) {
+ ret = regmap_write(ch7322->regmap,
+ CH7322_WRBUF + i, msg->msg[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ch7322_receive_message(struct ch7322 *ch7322, struct cec_msg *msg)
+{
+ unsigned int val;
+ int ret = 0;
+ int i;
+
+ WARN_ON(!mutex_is_locked(&ch7322->mutex));
+
+ ret = regmap_read(ch7322->regmap, CH7322_READ, &val);
+ if (ret)
+ return ret;
+
+ /* Message not ready */
+ if (!(val & CH7322_READ_NRDT))
+ return -EIO;
+
+ msg->len = (val & CH7322_READ_NMASK) + 1;
+
+ /* Read entire RDBUF to clear state */
+ for (i = 0; i < CH7322_RDBUF_LEN; i++) {
+ ret = regmap_read(ch7322->regmap, CH7322_RDBUF + i, &val);
+ if (ret)
+ return ret;
+ msg->msg[i] = (u8)val;
+ }
+
+ return 0;
+}
+
+static void ch7322_tx_done(struct ch7322 *ch7322)
+{
+ int ret;
+ unsigned int val;
+ u8 status, flags;
+
+ mutex_lock(&ch7322->mutex);
+ ret = regmap_read(ch7322->regmap, CH7322_WRITE, &val);
+ flags = ch7322->tx_flags;
+ mutex_unlock(&ch7322->mutex);
+
+ /*
+ * The device returns a one-bit OK status which usually means ACK but
+ * actually means NACK when sending a logical address query or a
+ * broadcast.
+ */
+ if (ret)
+ status = CEC_TX_STATUS_ERROR;
+ else if ((val & CH7322_WRITE_BOK) && (flags & CH7322_TX_FLAG_NACK))
+ status = CEC_TX_STATUS_NACK;
+ else if (val & CH7322_WRITE_BOK)
+ status = CEC_TX_STATUS_OK;
+ else if (flags & CH7322_TX_FLAG_NACK)
+ status = CEC_TX_STATUS_OK;
+ else
+ status = CEC_TX_STATUS_NACK;
+
+ if (status == CEC_TX_STATUS_NACK && (flags & CH7322_TX_FLAG_RETRY))
+ status |= CEC_TX_STATUS_MAX_RETRIES;
+
+ cec_transmit_attempt_done(ch7322->cec, status);
+}
+
+static void ch7322_rx_done(struct ch7322 *ch7322)
+{
+ struct cec_msg msg;
+ int ret;
+
+ mutex_lock(&ch7322->mutex);
+ ret = ch7322_receive_message(ch7322, &msg);
+ mutex_unlock(&ch7322->mutex);
+
+ if (ret)
+ dev_err(&ch7322->i2c->dev, "cec receive error: %d\n", ret);
+ else
+ cec_received_msg(ch7322->cec, &msg);
+}
+
+/*
+ * This device can either monitor the DDC lines to obtain the physical address
+ * or it can allow the host to program it. This driver lets the device obtain
+ * it.
+ */
+static void ch7322_phys_addr(struct ch7322 *ch7322)
+{
+ unsigned int pah, pal;
+ int ret = 0;
+
+ mutex_lock(&ch7322->mutex);
+ ret |= regmap_read(ch7322->regmap, CH7322_PARH, &pah);
+ ret |= regmap_read(ch7322->regmap, CH7322_PARL, &pal);
+ mutex_unlock(&ch7322->mutex);
+
+ if (ret)
+ dev_err(&ch7322->i2c->dev, "phys addr error\n");
+ else
+ cec_s_phys_addr(ch7322->cec, pal | (pah << 8), false);
+}
+
+static void ch7322_handle_events(struct ch7322 *ch7322)
+{
+ unsigned int data = 0;
+
+ mutex_lock(&ch7322->mutex);
+ regmap_read(ch7322->regmap, CH7322_INTDATA, &data);
+ regmap_write(ch7322->regmap, CH7322_INTDATA, data);
+ mutex_unlock(&ch7322->mutex);
+
+ if (data & CH7322_INTDATA_HPDFALL)
+ cec_phys_addr_invalidate(ch7322->cec);
+
+ if (data & CH7322_INTDATA_TXMSG)
+ ch7322_tx_done(ch7322);
+
+ if (data & CH7322_INTDATA_RXMSG)
+ ch7322_rx_done(ch7322);
+
+ if (data & CH7322_INTDATA_NEWPHA)
+ ch7322_phys_addr(ch7322);
+
+ if (data & CH7322_INTDATA_ERROR)
+ dev_dbg(&ch7322->i2c->dev, "unknown error\n");
+}
+
+static irqreturn_t ch7322_irq(int irq, void *dev)
+{
+ struct ch7322 *ch7322 = dev;
+
+ ch7322_handle_events(ch7322);
+
+ return IRQ_HANDLED;
+}
+
+static int ch7322_cec_adap_enable(struct cec_adapter *adap, bool enable)
+{
+ struct ch7322 *ch7322 = cec_get_drvdata(adap);
+ int ret;
+
+ if (enable)
+ ret = ch7322_unmask_interrupt(ch7322);
+ else
+ ret = ch7322_mask_interrupt(ch7322);
+
+ return ret;
+}
+
+static int ch7322_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
+{
+ struct ch7322 *ch7322 = cec_get_drvdata(adap);
+ int ret;
+
+ mutex_lock(&ch7322->mutex);
+ ret = regmap_update_bits(ch7322->regmap, CH7322_ADDLW,
+ CH7322_ADDLW_MASK, log_addr << 4);
+ mutex_unlock(&ch7322->mutex);
+
+ return ret;
+}
+
+static int ch7322_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
+ u32 signal_free_time, struct cec_msg *msg)
+{
+ struct ch7322 *ch7322 = cec_get_drvdata(adap);
+ int ret;
+
+ mutex_lock(&ch7322->mutex);
+ ret = ch7322_send_message(ch7322, msg);
+ mutex_unlock(&ch7322->mutex);
+
+ return ret;
+}
+
+static const struct cec_adap_ops ch7322_cec_adap_ops = {
+ .adap_enable = ch7322_cec_adap_enable,
+ .adap_log_addr = ch7322_cec_adap_log_addr,
+ .adap_transmit = ch7322_cec_adap_transmit,
+};
+
+static int ch7322_probe(struct i2c_client *client)
+{
+ struct ch7322 *ch7322;
+ int ret;
+ unsigned int val;
+
+ ch7322 = devm_kzalloc(&client->dev, sizeof(*ch7322), GFP_KERNEL);
+ if (!ch7322)
+ return -ENOMEM;
+
+ ch7322->regmap = devm_regmap_init_i2c(client, &ch7322_regmap);
+ if (IS_ERR(ch7322->regmap))
+ return PTR_ERR(ch7322->regmap);
+
+ ret = regmap_read(ch7322->regmap, CH7322_DID, &val);
+ if (ret)
+ return ret;
+
+ if (val != CH7322_DID_CH7322)
+ return -ENOTSUPP;
+
+ mutex_init(&ch7322->mutex);
+ ch7322->i2c = client;
+ ch7322->tx_flags = 0;
+
+ i2c_set_clientdata(client, ch7322);
+
+ /* Disable auto mode */
+ ret = regmap_write(ch7322->regmap, CH7322_MODE, CH7322_MODE_SW);
+ if (ret)
+ goto err_mutex;
+
+ ret = ch7322_mask_interrupt(ch7322);
+ if (ret)
+ goto err_mutex;
+
+ /* Configure HPDO pin as interrupt */
+ ret = regmap_write(ch7322->regmap, CH7322_CFG1, 0);
+ if (ret)
+ goto err_mutex;
+
+ /* Enable logical address register */
+ ret = regmap_update_bits(ch7322->regmap, CH7322_CTL,
+ CH7322_CTL_SPADL, CH7322_CTL_SPADL);
+ if (ret)
+ goto err_mutex;
+
+ ch7322->cec = cec_allocate_adapter(&ch7322_cec_adap_ops, ch7322,
+ dev_name(&client->dev),
+ CEC_CAP_DEFAULTS, 1);
+
+ if (IS_ERR(ch7322->cec)) {
+ ret = PTR_ERR(ch7322->cec);
+ goto err_mutex;
+ }
+
+ ret = cec_register_adapter(ch7322->cec, &client->dev);
+ if (ret) {
+ cec_delete_adapter(ch7322->cec);
+ goto err_mutex;
+ }
+
+ ret = devm_request_threaded_irq(&client->dev, client->irq, NULL,
+ ch7322_irq,
+ IRQF_ONESHOT | IRQF_TRIGGER_RISING,
+ client->name, ch7322);
+ if (ret)
+ goto err_cec;
+
+ ch7322_handle_events(ch7322);
+
+ dev_info(&client->dev, "device registered\n");
+
+ return 0;
+
+err_cec:
+ cec_unregister_adapter(ch7322->cec);
+
+err_mutex:
+ mutex_destroy(&ch7322->mutex);
+ return ret;
+}
+
+static int ch7322_remove(struct i2c_client *client)
+{
+ struct ch7322 *ch7322 = i2c_get_clientdata(client);
+
+ /* Mask interrupt */
+ mutex_lock(&ch7322->mutex);
+ regmap_write(ch7322->regmap, CH7322_INTCTL, CH7322_INTCTL_INTPB);
+ mutex_unlock(&ch7322->mutex);
+
+ cec_unregister_adapter(ch7322->cec);
+ mutex_destroy(&ch7322->mutex);
+
+ dev_info(&client->dev, "device unregistered\n");
+
+ return 0;
+}
+
+static const struct of_device_id ch7322_of_match[] = {
+ { .compatible = "chrontel,ch7322", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ch7322_of_match);
+
+static struct i2c_driver ch7322_i2c_driver = {
+ .driver = {
+ .name = "ch7322",
+ .of_match_table = of_match_ptr(ch7322_of_match),
+ },
+ .probe_new = ch7322_probe,
+ .remove = ch7322_remove,
+};
+
+module_i2c_driver(ch7322_i2c_driver);
+
+MODULE_DESCRIPTION("Chrontel CH7322 CEC Controller Driver");
+MODULE_AUTHOR("Jeff Chase <jnchase@google.com>");
+MODULE_LICENSE("GPL");
--
2.27.0.rc0.183.gde8f92d652-goog
^ permalink raw reply related
* [PATCH v3 1/2] dt-bindings: Add ch7322 media i2c device
From: Jeff Chase @ 2020-05-29 3:00 UTC (permalink / raw)
To: linux-media; +Cc: mchehab, hverkuil-cisco, robh+dt, devicetree, Jeff Chase
In-Reply-To: <20200529030012.254592-1-jnchase@google.com>
The ch7322 is a Chrontel CEC controller.
Signed-off-by: Jeff Chase <jnchase@google.com>
---
.../bindings/media/i2c/chrontel,ch7322.yaml | 65 +++++++++++++++++++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 7 ++
3 files changed, 74 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/i2c/chrontel,ch7322.yaml
diff --git a/Documentation/devicetree/bindings/media/i2c/chrontel,ch7322.yaml b/Documentation/devicetree/bindings/media/i2c/chrontel,ch7322.yaml
new file mode 100644
index 000000000000..d5706e08164c
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/chrontel,ch7322.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/media/i2c/chrontel,ch7322.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Chrontel HDMI-CEC Controller
+
+maintainers:
+ - Jeff Chase <jnchase@google.com>
+
+description: |-
+ The Chrontel CH7322 is a discrete HDMI-CEC controller. It is
+ programmable through I2C and drives a single CEC line.
+
+properties:
+ compatible:
+ const: chrontel,ch7322
+
+ reg:
+ description: I2C device address
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ reset-gpios:
+ description: |-
+ Reference to the GPIO connected to the RESET pin, if any. This
+ pin is active-low.
+
+ standby-gpios:
+ description: |-
+ Reference to the GPIO connected to the OE pin, if any. When low
+ the device will respond to power status requests with "standby"
+ if in auto mode.
+
+ # see ../cec.txt
+ hdmi-phandle:
+ description: phandle to the HDMI controller
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ch7322@75 {
+ compatible = "chrontel,ch7322";
+ reg = <0x75>;
+ interrupts = <47 IRQ_TYPE_EDGE_RISING>;
+ standby-gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+ hdmi-phandle = <&hdmi>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index d3891386d671..7794ffccd325 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -187,6 +187,8 @@ patternProperties:
description: ChipOne
"^chipspark,.*":
description: ChipSPARK
+ "^chrontel,.*":
+ description: Chrontel, Inc.
"^chrp,.*":
description: Common Hardware Reference Platform
"^chunghwa,.*":
diff --git a/MAINTAINERS b/MAINTAINERS
index d633a131dcd7..34c6d30e61e5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4047,6 +4047,13 @@ F: drivers/power/supply/cros_usbpd-charger.c
N: cros_ec
N: cros-ec
+CHRONTEL CH7322 CEC DRIVER
+M: Jeff Chase <jnchase@google.com>
+L: linux-media@vger.kernel.org
+S: Maintained
+T: git git://linuxtv.org/media_tree.git
+F: Documentation/devicetree/bindings/media/i2c/chontel,ch7322.yaml
+
CIRRUS LOGIC AUDIO CODEC DRIVERS
M: James Schulman <james.schulman@cirrus.com>
M: David Rhodes <david.rhodes@cirrus.com>
--
2.27.0.rc0.183.gde8f92d652-goog
^ permalink raw reply related
* Re: [PATCH v3 2/5] dt-bindings: regulator: Add labibb regulator
From: Rob Herring @ 2020-05-29 3:01 UTC (permalink / raw)
To: Sumit Semwal
Cc: kgunda, nishakumari, agross, linux-kernel, devicetree,
bjorn.andersson, robh+dt, rnayak, lgirdwood, broonie,
linux-arm-msm
In-Reply-To: <20200528154625.17742-3-sumit.semwal@linaro.org>
On Thu, 28 May 2020 21:16:22 +0530, Sumit Semwal wrote:
> From: Nisha Kumari <nishakumari@codeaurora.org>
>
> Adding the devicetree binding for labibb regulator.
>
> Signed-off-by: Nisha Kumari <nishakumari@codeaurora.org>
> Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
>
> --
> v2: updated for better compatible string and names.
> v3: moved to yaml
>
> ---
> .../regulator/qcom-labibb-regulator.yaml | 63 +++++++++++++++++++
> 1 file changed, 63 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/regulator/qcom-labibb-regulator.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
Documentation/devicetree/bindings/regulator/qcom-labibb-regulator.yaml: while scanning for the next token
found character that cannot start any token
in "<unicode string>", line 48, column 1
Documentation/devicetree/bindings/Makefile:12: recipe for target 'Documentation/devicetree/bindings/regulator/qcom-labibb-regulator.example.dts' failed
make[1]: *** [Documentation/devicetree/bindings/regulator/qcom-labibb-regulator.example.dts] Error 1
make[1]: *** Waiting for unfinished jobs....
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/regulator/qcom-labibb-regulator.yaml: ignoring, error parsing file
warning: no schema found in file: ./Documentation/devicetree/bindings/regulator/qcom-labibb-regulator.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/regulator/qcom-labibb-regulator.yaml: ignoring, error parsing file
warning: no schema found in file: ./Documentation/devicetree/bindings/regulator/qcom-labibb-regulator.yaml
Makefile:1300: recipe for target 'dt_binding_check' failed
make: *** [dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1299916
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:
pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
Please check and re-submit.
^ permalink raw reply
* Re: [PATCH 1/6] arm64: dts: qcom: sm8150: add apps_smmu node
From: Jonathan Marek @ 2020-05-29 3:02 UTC (permalink / raw)
To: Bjorn Andersson
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20200529025246.GV279327@builder.lan>
On 5/28/20 10:52 PM, Bjorn Andersson wrote:
> On Sat 23 May 19:38 PDT 2020, Jonathan Marek wrote:
>
>> Add the apps_smmu node for sm8150. Note that adding the iommus field for
>> UFS is required because initializing the iommu removes the bypass mapping
>> that created by the bootloader.
>>
>
> Unrelated to the patch itself; how do you disable the splash screen on
> 8150? "fastboot oem select-display-panel none" doesn't seem to work for
> me on the MTP - and hence this would prevent my device from booting.
>
> Thanks,
> Bjorn
>
I don't have a MTP, but on HDK855, "fastboot oem select-display-panel
none" combined with setting the physical switch to HDMI mode (which
switches off the 1440x2560 panel) gets it to not setup the display at
all (just the fastboot command isn't enough).
With HDK865 though that doesn't work and I have a hack to work around it
(writing 0 to INTF_TIMING_ENGINE_EN early on in boot will stop video
mode scanout and it won't crash).
>> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
>> ---
>> arch/arm64/boot/dts/qcom/sm8150.dtsi | 91 ++++++++++++++++++++++++++++
>> 1 file changed, 91 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
>> index a36512d1f6a1..acb839427b12 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
>> @@ -442,6 +442,8 @@ ufs_mem_hc: ufshc@1d84000 {
>> resets = <&gcc GCC_UFS_PHY_BCR>;
>> reset-names = "rst";
>>
>> + iommus = <&apps_smmu 0x300 0>;
>> +
>> clock-names =
>> "core_clk",
>> "bus_aggr_clk",
>> @@ -706,6 +708,7 @@ usb_1_dwc3: dwc3@a600000 {
>> compatible = "snps,dwc3";
>> reg = <0 0x0a600000 0 0xcd00>;
>> interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>> + iommus = <&apps_smmu 0x140 0>;
>> snps,dis_u2_susphy_quirk;
>> snps,dis_enblslpm_quirk;
>> phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
>> @@ -742,6 +745,94 @@ spmi_bus: spmi@c440000 {
>> cell-index = <0>;
>> };
>>
>> + apps_smmu: iommu@15000000 {
>> + compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
>> + reg = <0 0x15000000 0 0x100000>;
>> + #iommu-cells = <2>;
>> + #global-interrupts = <1>;
>> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> remoteproc_adsp: remoteproc@17300000 {
>> compatible = "qcom,sm8150-adsp-pas";
>> reg = <0x0 0x17300000 0x0 0x4040>;
>> --
>> 2.26.1
>>
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox