* Re: [PATCH v2] of/fdt: Remove redundant kbasename function call
From: Rob Herring @ 2020-05-29 2:57 UTC (permalink / raw)
To: Qi Zheng; +Cc: devicetree, frowand.list, robh+dt, linux-kernel
In-Reply-To: <20200528132541.463300-1-arch0.zheng@gmail.com>
On Thu, 28 May 2020 21:25:41 +0800, Qi Zheng wrote:
> For version 1 to 3 of the device tree, this is the node full
> path as a zero terminated string, starting with "/". The
> following equation will not hold, since the node name has
> been processed in the fdt_get_name().
>
> *pathp == '/'
>
> For version 16 and later, this is the node unit name only
> (or an empty string for the root node). So the above
> equation will still not hold.
>
> So the kbasename() is redundant, just remove it.
>
> Signed-off-by: Qi Zheng <arch0.zheng@gmail.com>
> ---
>
> Change in v2:
> remove another kbasename() also.
>
> drivers/of/fdt.c | 4 ----
> 1 file changed, 4 deletions(-)
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH] dt-bindings: timer: renesas: mtu2: Convert to json-schema
From: Rob Herring @ 2020-05-29 2:57 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Thomas Gleixner, devicetree, Rob Herring, Daniel Lezcano,
linux-kernel, linux-renesas-soc, Laurent Pinchart
In-Reply-To: <20200528133033.4191-1-geert+renesas@glider.be>
On Thu, 28 May 2020 15:30:33 +0200, Geert Uytterhoeven wrote:
> Convert the Renesas Multi-Function Timer Pulse Unit 2 (MTU2) Device Tree
> binding documentation to json-schema.
>
> Add missing properties.
> Update the example to match reality.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
> .../bindings/timer/renesas,mtu2.txt | 42 ----------
> .../bindings/timer/renesas,mtu2.yaml | 76 +++++++++++++++++++
> 2 files changed, 76 insertions(+), 42 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/timer/renesas,mtu2.txt
> create mode 100644 Documentation/devicetree/bindings/timer/renesas,mtu2.yaml
>
Applied, thanks!
^ permalink raw reply
* Re: [PATCH] dt-bindings: sound: tlv320adcx140: Fix dt-binding-check issue
From: Rob Herring @ 2020-05-29 2:58 UTC (permalink / raw)
To: Dan Murphy
Cc: lgirdwood, broonie, perex, tiwai, alsa-devel, linux-kernel,
devicetree
In-Reply-To: <20200528144711.18065-1-dmurphy@ti.com>
On Thu, May 28, 2020 at 09:47:11AM -0500, Dan Murphy wrote:
> Fix dt-binding-check issue
>
> ti,gpi-config:0:0: 4 is greater than the maximum of 1
> ti,gpi-config:0:1: 5 is greater than the maximum of 1
> ti,gpi-config:0:2: 6 is greater than the maximum of 1
> ti,gpi-config:0:3: 7 is greater than the maximum of 1
>
> Reported-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Dan Murphy <dmurphy@ti.com>
> ---
> Documentation/devicetree/bindings/sound/tlv320adcx140.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Thanks for the quick fix.
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v3 0/2] CH7322 CEC controller driver
From: Jeff Chase @ 2020-05-29 3:00 UTC (permalink / raw)
To: linux-media; +Cc: mchehab, hverkuil-cisco, robh+dt, devicetree, Jeff Chase
Add device driver and device tree bindings for a Chrontel CEC
conroller. This is an I2C device that can send and receive CEC
messages.
Changes from v2:
- fix formatting errors
- mask and unmask interrupt in cec adapter enable
Changes from v1:
- fix formatpatch.pl --strict errors
- additional comments
- enable and program logical address register
- add flags to aid interpreting transmit done status
- move ch7322 out of devicetree trivial devices
Jeff Chase (2):
dt-bindings: Add ch7322 media i2c device
media: cec: i2c: ch7322: Add ch7322 CEC controller driver
.../bindings/media/i2c/chrontel,ch7322.yaml | 65 +++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 8 +
drivers/media/cec/Kconfig | 1 +
drivers/media/cec/Makefile | 2 +-
drivers/media/cec/i2c/Kconfig | 14 +
drivers/media/cec/i2c/Makefile | 5 +
drivers/media/cec/i2c/ch7322.c | 523 ++++++++++++++++++
8 files changed, 619 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/media/i2c/chrontel,ch7322.yaml
create mode 100644 drivers/media/cec/i2c/Kconfig
create mode 100644 drivers/media/cec/i2c/Makefile
create mode 100644 drivers/media/cec/i2c/ch7322.c
--
2.27.0.rc0.183.gde8f92d652-goog
^ permalink raw reply
* [PATCH v3 2/2] media: cec: i2c: ch7322: Add ch7322 CEC controller driver
From: Jeff Chase @ 2020-05-29 3:00 UTC (permalink / raw)
To: linux-media; +Cc: mchehab, hverkuil-cisco, robh+dt, devicetree, Jeff Chase
In-Reply-To: <20200529030012.254592-1-jnchase@google.com>
Add a CEC device driver for the Chrontel ch7322 CEC conroller.
This is an I2C device capable of sending and receiving CEC messages.
Signed-off-by: Jeff Chase <jnchase@google.com>
---
MAINTAINERS | 1 +
drivers/media/cec/Kconfig | 1 +
drivers/media/cec/Makefile | 2 +-
drivers/media/cec/i2c/Kconfig | 14 +
drivers/media/cec/i2c/Makefile | 5 +
drivers/media/cec/i2c/ch7322.c | 523 +++++++++++++++++++++++++++++++++
6 files changed, 545 insertions(+), 1 deletion(-)
create mode 100644 drivers/media/cec/i2c/Kconfig
create mode 100644 drivers/media/cec/i2c/Makefile
create mode 100644 drivers/media/cec/i2c/ch7322.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 34c6d30e61e5..43e876395686 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4053,6 +4053,7 @@ L: linux-media@vger.kernel.org
S: Maintained
T: git git://linuxtv.org/media_tree.git
F: Documentation/devicetree/bindings/media/i2c/chontel,ch7322.yaml
+F: drivers/media/cec/i2c/ch7322.c
CIRRUS LOGIC AUDIO CODEC DRIVERS
M: James Schulman <james.schulman@cirrus.com>
diff --git a/drivers/media/cec/Kconfig b/drivers/media/cec/Kconfig
index eea74b7cfa8c..3e934aa239ab 100644
--- a/drivers/media/cec/Kconfig
+++ b/drivers/media/cec/Kconfig
@@ -33,6 +33,7 @@ menuconfig MEDIA_CEC_SUPPORT
adapter that supports HDMI CEC.
if MEDIA_CEC_SUPPORT
+source "drivers/media/cec/i2c/Kconfig"
source "drivers/media/cec/platform/Kconfig"
source "drivers/media/cec/usb/Kconfig"
endif
diff --git a/drivers/media/cec/Makefile b/drivers/media/cec/Makefile
index 74e80e1b3571..23539339bc81 100644
--- a/drivers/media/cec/Makefile
+++ b/drivers/media/cec/Makefile
@@ -1,2 +1,2 @@
# SPDX-License-Identifier: GPL-2.0
-obj-y += core/ platform/ usb/
+obj-y += core/ i2c/ platform/ usb/
diff --git a/drivers/media/cec/i2c/Kconfig b/drivers/media/cec/i2c/Kconfig
new file mode 100644
index 000000000000..e445ca2110b3
--- /dev/null
+++ b/drivers/media/cec/i2c/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# I2C drivers
+
+config CEC_CH7322
+ tristate "Chrontel CH7322 CEC controller"
+ select I2C
+ select REGMAP_I2C
+ select CEC_CORE
+ help
+ This is a driver for the Chrontel CH7322 CEC controller. It uses the
+ generic CEC framework interface.
+ CEC bus is present in the HDMI connector and enables communication
+ between compatible devices.
diff --git a/drivers/media/cec/i2c/Makefile b/drivers/media/cec/i2c/Makefile
new file mode 100644
index 000000000000..d7496dfd0fa4
--- /dev/null
+++ b/drivers/media/cec/i2c/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for the CEC I2C device drivers.
+#
+obj-$(CONFIG_CEC_CH7322) += ch7322.o
diff --git a/drivers/media/cec/i2c/ch7322.c b/drivers/media/cec/i2c/ch7322.c
new file mode 100644
index 000000000000..dd54df61a522
--- /dev/null
+++ b/drivers/media/cec/i2c/ch7322.c
@@ -0,0 +1,523 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Driver for the Chrontel CH7322 CEC Controller
+ *
+ * Copyright 2020 Google LLC.
+ */
+
+/*
+ * Notes
+ *
+ * - This device powers on in Auto Mode which has limited functionality. This
+ * driver disables Auto Mode when it attaches.
+ *
+ */
+
+#include <linux/cec.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/regmap.h>
+#include <media/cec.h>
+
+#define CH7322_WRITE 0x00
+#define CH7322_WRITE_MSENT 0x80
+#define CH7322_WRITE_BOK 0x40
+#define CH7322_WRITE_NMASK 0x0f
+
+/* Write buffer is 0x01-0x10 */
+#define CH7322_WRBUF 0x01
+#define CH7322_WRBUF_LEN 0x10
+
+#define CH7322_READ 0x40
+#define CH7322_READ_NRDT 0x80
+#define CH7322_READ_MSENT 0x20
+#define CH7322_READ_NMASK 0x0f
+
+/* Read buffer is 0x41-0x50 */
+#define CH7322_RDBUF 0x41
+#define CH7322_RDBUF_LEN 0x10
+
+#define CH7322_MODE 0x11
+#define CH7322_MODE_AUTO 0x78
+#define CH7322_MODE_SW 0xb5
+
+#define CH7322_RESET 0x12
+#define CH7322_RESET_RST 0x00
+
+#define CH7322_POWER 0x13
+#define CH7322_POWER_FPD 0x04
+
+#define CH7322_CFG0 0x17
+#define CH7322_CFG0_EOBEN 0x40
+#define CH7322_CFG0_PEOB 0x20
+#define CH7322_CFG0_CLRSPP 0x10
+#define CH7322_CFG0_FLOW 0x08
+
+#define CH7322_CFG1 0x1a
+#define CH7322_CFG1_STDBYO 0x04
+#define CH7322_CFG1_HPBP 0x02
+#define CH7322_CFG1_PIO 0x01
+
+#define CH7322_INTCTL 0x1b
+#define CH7322_INTCTL_INTPB 0x80
+#define CH7322_INTCTL_STDBY 0x40
+#define CH7322_INTCTL_HPDFALL 0x20
+#define CH7322_INTCTL_HPDRISE 0x10
+#define CH7322_INTCTL_RXMSG 0x08
+#define CH7322_INTCTL_TXMSG 0x04
+#define CH7322_INTCTL_NEWPHA 0x02
+#define CH7322_INTCTL_ERROR 0x01
+
+#define CH7322_DVCLKFNH 0x1d
+#define CH7322_DVCLKFNL 0x1e
+
+#define CH7322_CTL 0x31
+#define CH7322_CTL_FSTDBY 0x80
+#define CH7322_CTL_PLSEN 0x40
+#define CH7322_CTL_PLSPB 0x20
+#define CH7322_CTL_SPADL 0x10
+#define CH7322_CTL_HINIT 0x08
+#define CH7322_CTL_WPHYA 0x04
+#define CH7322_CTL_H1T 0x02
+#define CH7322_CTL_S1T 0x01
+
+#define CH7322_PAWH 0x32
+#define CH7322_PAWL 0x33
+
+#define CH7322_ADDLW 0x34
+#define CH7322_ADDLW_MASK 0xf0
+
+#define CH7322_ADDLR 0x3d
+#define CH7322_ADDLR_HPD 0x80
+#define CH7322_ADDLR_MASK 0x0f
+
+#define CH7322_INTDATA 0x3e
+#define CH7322_INTDATA_MODE 0x80
+#define CH7322_INTDATA_STDBY 0x40
+#define CH7322_INTDATA_HPDFALL 0x20
+#define CH7322_INTDATA_HPDRISE 0x10
+#define CH7322_INTDATA_RXMSG 0x08
+#define CH7322_INTDATA_TXMSG 0x04
+#define CH7322_INTDATA_NEWPHA 0x02
+#define CH7322_INTDATA_ERROR 0x01
+
+#define CH7322_EVENT 0x3F
+#define CH7322_EVENT_TXERR 0x80
+#define CH7322_EVENT_HRST 0x40
+#define CH7322_EVENT_HFST 0x20
+#define CH7322_EVENT_PHACHG 0x10
+#define CH7322_EVENT_ACTST 0x08
+#define CH7322_EVENT_PHARDY 0x04
+#define CH7322_EVENT_BSOK 0x02
+#define CH7322_EVENT_ERRADCF 0x01
+
+#define CH7322_DID 0x51
+#define CH7322_DID_CH7322 0x5b
+#define CH7322_DID_CH7323 0x5f
+
+#define CH7322_REVISIONID 0x52
+
+#define CH7322_PARH 0x53
+#define CH7322_PARL 0x54
+
+#define CH7322_IOCFG2 0x75
+#define CH7322_IOCFG_CIO 0x80
+#define CH7322_IOCFG_IOCFGMASK 0x78
+#define CH7322_IOCFG_AUDIO 0x04
+#define CH7322_IOCFG_SPAMST 0x02
+#define CH7322_IOCFG_SPAMSP 0x01
+
+#define CH7322_CTL3 0x7b
+#define CH7322_CTL3_SWENA 0x80
+#define CH7322_CTL3_FC_INIT 0x40
+#define CH7322_CTL3_SML_FL 0x20
+#define CH7322_CTL3_SM_RDST 0x10
+#define CH7322_CTL3_SPP_CIAH 0x08
+#define CH7322_CTL3_SPP_CIAL 0x04
+#define CH7322_CTL3_SPP_ACTH 0x02
+#define CH7322_CTL3_SPP_ACTL 0x01
+
+/* BOK status means NACK */
+#define CH7322_TX_FLAG_NACK BIT(0)
+/* Device will retry automatically */
+#define CH7322_TX_FLAG_RETRY BIT(1)
+
+struct ch7322 {
+ struct i2c_client *i2c;
+ struct regmap *regmap;
+ struct cec_adapter *cec;
+ struct mutex mutex; /* device access mutex */
+ u8 tx_flags;
+};
+
+static const struct regmap_config ch7322_regmap = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = 0x7f,
+ .disable_locking = true,
+};
+
+static int ch7322_unmask_interrupt(struct ch7322 *ch7322)
+{
+ int ret;
+
+ mutex_lock(&ch7322->mutex);
+ ret = regmap_write(ch7322->regmap, CH7322_INTCTL, 0xff);
+ mutex_unlock(&ch7322->mutex);
+
+ return ret;
+}
+
+static int ch7322_mask_interrupt(struct ch7322 *ch7322)
+{
+ int ret;
+
+ mutex_lock(&ch7322->mutex);
+ ret = regmap_write(ch7322->regmap, CH7322_INTCTL, CH7322_INTCTL_INTPB);
+ mutex_unlock(&ch7322->mutex);
+
+ return ret;
+}
+
+static int ch7322_send_message(struct ch7322 *ch7322, const struct cec_msg *msg)
+{
+ unsigned int val;
+ unsigned int len = msg->len;
+ int ret;
+ int i;
+
+ WARN_ON(!mutex_is_locked(&ch7322->mutex));
+
+ if (len > CH7322_WRBUF_LEN || len < 1)
+ return -EINVAL;
+
+ ret = regmap_read(ch7322->regmap, CH7322_WRITE, &val);
+ if (ret)
+ return ret;
+
+ /* Buffer not ready */
+ if (!(val & CH7322_WRITE_MSENT))
+ return -EBUSY;
+
+ if (cec_msg_opcode(msg) == -1 &&
+ cec_msg_initiator(msg) == cec_msg_destination(msg)) {
+ ch7322->tx_flags = CH7322_TX_FLAG_NACK | CH7322_TX_FLAG_RETRY;
+ } else if (cec_msg_is_broadcast(msg)) {
+ ch7322->tx_flags = CH7322_TX_FLAG_NACK;
+ } else {
+ ch7322->tx_flags = CH7322_TX_FLAG_RETRY;
+ }
+
+ ret = regmap_write(ch7322->regmap, CH7322_WRITE, len - 1);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < len; i++) {
+ ret = regmap_write(ch7322->regmap,
+ CH7322_WRBUF + i, msg->msg[i]);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ch7322_receive_message(struct ch7322 *ch7322, struct cec_msg *msg)
+{
+ unsigned int val;
+ int ret = 0;
+ int i;
+
+ WARN_ON(!mutex_is_locked(&ch7322->mutex));
+
+ ret = regmap_read(ch7322->regmap, CH7322_READ, &val);
+ if (ret)
+ return ret;
+
+ /* Message not ready */
+ if (!(val & CH7322_READ_NRDT))
+ return -EIO;
+
+ msg->len = (val & CH7322_READ_NMASK) + 1;
+
+ /* Read entire RDBUF to clear state */
+ for (i = 0; i < CH7322_RDBUF_LEN; i++) {
+ ret = regmap_read(ch7322->regmap, CH7322_RDBUF + i, &val);
+ if (ret)
+ return ret;
+ msg->msg[i] = (u8)val;
+ }
+
+ return 0;
+}
+
+static void ch7322_tx_done(struct ch7322 *ch7322)
+{
+ int ret;
+ unsigned int val;
+ u8 status, flags;
+
+ mutex_lock(&ch7322->mutex);
+ ret = regmap_read(ch7322->regmap, CH7322_WRITE, &val);
+ flags = ch7322->tx_flags;
+ mutex_unlock(&ch7322->mutex);
+
+ /*
+ * The device returns a one-bit OK status which usually means ACK but
+ * actually means NACK when sending a logical address query or a
+ * broadcast.
+ */
+ if (ret)
+ status = CEC_TX_STATUS_ERROR;
+ else if ((val & CH7322_WRITE_BOK) && (flags & CH7322_TX_FLAG_NACK))
+ status = CEC_TX_STATUS_NACK;
+ else if (val & CH7322_WRITE_BOK)
+ status = CEC_TX_STATUS_OK;
+ else if (flags & CH7322_TX_FLAG_NACK)
+ status = CEC_TX_STATUS_OK;
+ else
+ status = CEC_TX_STATUS_NACK;
+
+ if (status == CEC_TX_STATUS_NACK && (flags & CH7322_TX_FLAG_RETRY))
+ status |= CEC_TX_STATUS_MAX_RETRIES;
+
+ cec_transmit_attempt_done(ch7322->cec, status);
+}
+
+static void ch7322_rx_done(struct ch7322 *ch7322)
+{
+ struct cec_msg msg;
+ int ret;
+
+ mutex_lock(&ch7322->mutex);
+ ret = ch7322_receive_message(ch7322, &msg);
+ mutex_unlock(&ch7322->mutex);
+
+ if (ret)
+ dev_err(&ch7322->i2c->dev, "cec receive error: %d\n", ret);
+ else
+ cec_received_msg(ch7322->cec, &msg);
+}
+
+/*
+ * This device can either monitor the DDC lines to obtain the physical address
+ * or it can allow the host to program it. This driver lets the device obtain
+ * it.
+ */
+static void ch7322_phys_addr(struct ch7322 *ch7322)
+{
+ unsigned int pah, pal;
+ int ret = 0;
+
+ mutex_lock(&ch7322->mutex);
+ ret |= regmap_read(ch7322->regmap, CH7322_PARH, &pah);
+ ret |= regmap_read(ch7322->regmap, CH7322_PARL, &pal);
+ mutex_unlock(&ch7322->mutex);
+
+ if (ret)
+ dev_err(&ch7322->i2c->dev, "phys addr error\n");
+ else
+ cec_s_phys_addr(ch7322->cec, pal | (pah << 8), false);
+}
+
+static void ch7322_handle_events(struct ch7322 *ch7322)
+{
+ unsigned int data = 0;
+
+ mutex_lock(&ch7322->mutex);
+ regmap_read(ch7322->regmap, CH7322_INTDATA, &data);
+ regmap_write(ch7322->regmap, CH7322_INTDATA, data);
+ mutex_unlock(&ch7322->mutex);
+
+ if (data & CH7322_INTDATA_HPDFALL)
+ cec_phys_addr_invalidate(ch7322->cec);
+
+ if (data & CH7322_INTDATA_TXMSG)
+ ch7322_tx_done(ch7322);
+
+ if (data & CH7322_INTDATA_RXMSG)
+ ch7322_rx_done(ch7322);
+
+ if (data & CH7322_INTDATA_NEWPHA)
+ ch7322_phys_addr(ch7322);
+
+ if (data & CH7322_INTDATA_ERROR)
+ dev_dbg(&ch7322->i2c->dev, "unknown error\n");
+}
+
+static irqreturn_t ch7322_irq(int irq, void *dev)
+{
+ struct ch7322 *ch7322 = dev;
+
+ ch7322_handle_events(ch7322);
+
+ return IRQ_HANDLED;
+}
+
+static int ch7322_cec_adap_enable(struct cec_adapter *adap, bool enable)
+{
+ struct ch7322 *ch7322 = cec_get_drvdata(adap);
+ int ret;
+
+ if (enable)
+ ret = ch7322_unmask_interrupt(ch7322);
+ else
+ ret = ch7322_mask_interrupt(ch7322);
+
+ return ret;
+}
+
+static int ch7322_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
+{
+ struct ch7322 *ch7322 = cec_get_drvdata(adap);
+ int ret;
+
+ mutex_lock(&ch7322->mutex);
+ ret = regmap_update_bits(ch7322->regmap, CH7322_ADDLW,
+ CH7322_ADDLW_MASK, log_addr << 4);
+ mutex_unlock(&ch7322->mutex);
+
+ return ret;
+}
+
+static int ch7322_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
+ u32 signal_free_time, struct cec_msg *msg)
+{
+ struct ch7322 *ch7322 = cec_get_drvdata(adap);
+ int ret;
+
+ mutex_lock(&ch7322->mutex);
+ ret = ch7322_send_message(ch7322, msg);
+ mutex_unlock(&ch7322->mutex);
+
+ return ret;
+}
+
+static const struct cec_adap_ops ch7322_cec_adap_ops = {
+ .adap_enable = ch7322_cec_adap_enable,
+ .adap_log_addr = ch7322_cec_adap_log_addr,
+ .adap_transmit = ch7322_cec_adap_transmit,
+};
+
+static int ch7322_probe(struct i2c_client *client)
+{
+ struct ch7322 *ch7322;
+ int ret;
+ unsigned int val;
+
+ ch7322 = devm_kzalloc(&client->dev, sizeof(*ch7322), GFP_KERNEL);
+ if (!ch7322)
+ return -ENOMEM;
+
+ ch7322->regmap = devm_regmap_init_i2c(client, &ch7322_regmap);
+ if (IS_ERR(ch7322->regmap))
+ return PTR_ERR(ch7322->regmap);
+
+ ret = regmap_read(ch7322->regmap, CH7322_DID, &val);
+ if (ret)
+ return ret;
+
+ if (val != CH7322_DID_CH7322)
+ return -ENOTSUPP;
+
+ mutex_init(&ch7322->mutex);
+ ch7322->i2c = client;
+ ch7322->tx_flags = 0;
+
+ i2c_set_clientdata(client, ch7322);
+
+ /* Disable auto mode */
+ ret = regmap_write(ch7322->regmap, CH7322_MODE, CH7322_MODE_SW);
+ if (ret)
+ goto err_mutex;
+
+ ret = ch7322_mask_interrupt(ch7322);
+ if (ret)
+ goto err_mutex;
+
+ /* Configure HPDO pin as interrupt */
+ ret = regmap_write(ch7322->regmap, CH7322_CFG1, 0);
+ if (ret)
+ goto err_mutex;
+
+ /* Enable logical address register */
+ ret = regmap_update_bits(ch7322->regmap, CH7322_CTL,
+ CH7322_CTL_SPADL, CH7322_CTL_SPADL);
+ if (ret)
+ goto err_mutex;
+
+ ch7322->cec = cec_allocate_adapter(&ch7322_cec_adap_ops, ch7322,
+ dev_name(&client->dev),
+ CEC_CAP_DEFAULTS, 1);
+
+ if (IS_ERR(ch7322->cec)) {
+ ret = PTR_ERR(ch7322->cec);
+ goto err_mutex;
+ }
+
+ ret = cec_register_adapter(ch7322->cec, &client->dev);
+ if (ret) {
+ cec_delete_adapter(ch7322->cec);
+ goto err_mutex;
+ }
+
+ ret = devm_request_threaded_irq(&client->dev, client->irq, NULL,
+ ch7322_irq,
+ IRQF_ONESHOT | IRQF_TRIGGER_RISING,
+ client->name, ch7322);
+ if (ret)
+ goto err_cec;
+
+ ch7322_handle_events(ch7322);
+
+ dev_info(&client->dev, "device registered\n");
+
+ return 0;
+
+err_cec:
+ cec_unregister_adapter(ch7322->cec);
+
+err_mutex:
+ mutex_destroy(&ch7322->mutex);
+ return ret;
+}
+
+static int ch7322_remove(struct i2c_client *client)
+{
+ struct ch7322 *ch7322 = i2c_get_clientdata(client);
+
+ /* Mask interrupt */
+ mutex_lock(&ch7322->mutex);
+ regmap_write(ch7322->regmap, CH7322_INTCTL, CH7322_INTCTL_INTPB);
+ mutex_unlock(&ch7322->mutex);
+
+ cec_unregister_adapter(ch7322->cec);
+ mutex_destroy(&ch7322->mutex);
+
+ dev_info(&client->dev, "device unregistered\n");
+
+ return 0;
+}
+
+static const struct of_device_id ch7322_of_match[] = {
+ { .compatible = "chrontel,ch7322", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ch7322_of_match);
+
+static struct i2c_driver ch7322_i2c_driver = {
+ .driver = {
+ .name = "ch7322",
+ .of_match_table = of_match_ptr(ch7322_of_match),
+ },
+ .probe_new = ch7322_probe,
+ .remove = ch7322_remove,
+};
+
+module_i2c_driver(ch7322_i2c_driver);
+
+MODULE_DESCRIPTION("Chrontel CH7322 CEC Controller Driver");
+MODULE_AUTHOR("Jeff Chase <jnchase@google.com>");
+MODULE_LICENSE("GPL");
--
2.27.0.rc0.183.gde8f92d652-goog
^ permalink raw reply related
* [PATCH v3 1/2] dt-bindings: Add ch7322 media i2c device
From: Jeff Chase @ 2020-05-29 3:00 UTC (permalink / raw)
To: linux-media; +Cc: mchehab, hverkuil-cisco, robh+dt, devicetree, Jeff Chase
In-Reply-To: <20200529030012.254592-1-jnchase@google.com>
The ch7322 is a Chrontel CEC controller.
Signed-off-by: Jeff Chase <jnchase@google.com>
---
.../bindings/media/i2c/chrontel,ch7322.yaml | 65 +++++++++++++++++++
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
MAINTAINERS | 7 ++
3 files changed, 74 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/i2c/chrontel,ch7322.yaml
diff --git a/Documentation/devicetree/bindings/media/i2c/chrontel,ch7322.yaml b/Documentation/devicetree/bindings/media/i2c/chrontel,ch7322.yaml
new file mode 100644
index 000000000000..d5706e08164c
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/chrontel,ch7322.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/media/i2c/chrontel,ch7322.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Chrontel HDMI-CEC Controller
+
+maintainers:
+ - Jeff Chase <jnchase@google.com>
+
+description: |-
+ The Chrontel CH7322 is a discrete HDMI-CEC controller. It is
+ programmable through I2C and drives a single CEC line.
+
+properties:
+ compatible:
+ const: chrontel,ch7322
+
+ reg:
+ description: I2C device address
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ reset-gpios:
+ description: |-
+ Reference to the GPIO connected to the RESET pin, if any. This
+ pin is active-low.
+
+ standby-gpios:
+ description: |-
+ Reference to the GPIO connected to the OE pin, if any. When low
+ the device will respond to power status requests with "standby"
+ if in auto mode.
+
+ # see ../cec.txt
+ hdmi-phandle:
+ description: phandle to the HDMI controller
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ch7322@75 {
+ compatible = "chrontel,ch7322";
+ reg = <0x75>;
+ interrupts = <47 IRQ_TYPE_EDGE_RISING>;
+ standby-gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
+ reset-gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
+ hdmi-phandle = <&hdmi>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index d3891386d671..7794ffccd325 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -187,6 +187,8 @@ patternProperties:
description: ChipOne
"^chipspark,.*":
description: ChipSPARK
+ "^chrontel,.*":
+ description: Chrontel, Inc.
"^chrp,.*":
description: Common Hardware Reference Platform
"^chunghwa,.*":
diff --git a/MAINTAINERS b/MAINTAINERS
index d633a131dcd7..34c6d30e61e5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4047,6 +4047,13 @@ F: drivers/power/supply/cros_usbpd-charger.c
N: cros_ec
N: cros-ec
+CHRONTEL CH7322 CEC DRIVER
+M: Jeff Chase <jnchase@google.com>
+L: linux-media@vger.kernel.org
+S: Maintained
+T: git git://linuxtv.org/media_tree.git
+F: Documentation/devicetree/bindings/media/i2c/chontel,ch7322.yaml
+
CIRRUS LOGIC AUDIO CODEC DRIVERS
M: James Schulman <james.schulman@cirrus.com>
M: David Rhodes <david.rhodes@cirrus.com>
--
2.27.0.rc0.183.gde8f92d652-goog
^ permalink raw reply related
* Re: [PATCH v3 2/5] dt-bindings: regulator: Add labibb regulator
From: Rob Herring @ 2020-05-29 3:01 UTC (permalink / raw)
To: Sumit Semwal
Cc: kgunda, nishakumari, agross, linux-kernel, devicetree,
bjorn.andersson, robh+dt, rnayak, lgirdwood, broonie,
linux-arm-msm
In-Reply-To: <20200528154625.17742-3-sumit.semwal@linaro.org>
On Thu, 28 May 2020 21:16:22 +0530, Sumit Semwal wrote:
> From: Nisha Kumari <nishakumari@codeaurora.org>
>
> Adding the devicetree binding for labibb regulator.
>
> Signed-off-by: Nisha Kumari <nishakumari@codeaurora.org>
> Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
>
> --
> v2: updated for better compatible string and names.
> v3: moved to yaml
>
> ---
> .../regulator/qcom-labibb-regulator.yaml | 63 +++++++++++++++++++
> 1 file changed, 63 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/regulator/qcom-labibb-regulator.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
Documentation/devicetree/bindings/regulator/qcom-labibb-regulator.yaml: while scanning for the next token
found character that cannot start any token
in "<unicode string>", line 48, column 1
Documentation/devicetree/bindings/Makefile:12: recipe for target 'Documentation/devicetree/bindings/regulator/qcom-labibb-regulator.example.dts' failed
make[1]: *** [Documentation/devicetree/bindings/regulator/qcom-labibb-regulator.example.dts] Error 1
make[1]: *** Waiting for unfinished jobs....
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/regulator/qcom-labibb-regulator.yaml: ignoring, error parsing file
warning: no schema found in file: ./Documentation/devicetree/bindings/regulator/qcom-labibb-regulator.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/regulator/qcom-labibb-regulator.yaml: ignoring, error parsing file
warning: no schema found in file: ./Documentation/devicetree/bindings/regulator/qcom-labibb-regulator.yaml
Makefile:1300: recipe for target 'dt_binding_check' failed
make: *** [dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1299916
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:
pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
Please check and re-submit.
^ permalink raw reply
* Re: [PATCH 1/6] arm64: dts: qcom: sm8150: add apps_smmu node
From: Jonathan Marek @ 2020-05-29 3:02 UTC (permalink / raw)
To: Bjorn Andersson
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20200529025246.GV279327@builder.lan>
On 5/28/20 10:52 PM, Bjorn Andersson wrote:
> On Sat 23 May 19:38 PDT 2020, Jonathan Marek wrote:
>
>> Add the apps_smmu node for sm8150. Note that adding the iommus field for
>> UFS is required because initializing the iommu removes the bypass mapping
>> that created by the bootloader.
>>
>
> Unrelated to the patch itself; how do you disable the splash screen on
> 8150? "fastboot oem select-display-panel none" doesn't seem to work for
> me on the MTP - and hence this would prevent my device from booting.
>
> Thanks,
> Bjorn
>
I don't have a MTP, but on HDK855, "fastboot oem select-display-panel
none" combined with setting the physical switch to HDMI mode (which
switches off the 1440x2560 panel) gets it to not setup the display at
all (just the fastboot command isn't enough).
With HDK865 though that doesn't work and I have a hack to work around it
(writing 0 to INTF_TIMING_ENGINE_EN early on in boot will stop video
mode scanout and it won't crash).
>> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
>> ---
>> arch/arm64/boot/dts/qcom/sm8150.dtsi | 91 ++++++++++++++++++++++++++++
>> 1 file changed, 91 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
>> index a36512d1f6a1..acb839427b12 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
>> @@ -442,6 +442,8 @@ ufs_mem_hc: ufshc@1d84000 {
>> resets = <&gcc GCC_UFS_PHY_BCR>;
>> reset-names = "rst";
>>
>> + iommus = <&apps_smmu 0x300 0>;
>> +
>> clock-names =
>> "core_clk",
>> "bus_aggr_clk",
>> @@ -706,6 +708,7 @@ usb_1_dwc3: dwc3@a600000 {
>> compatible = "snps,dwc3";
>> reg = <0 0x0a600000 0 0xcd00>;
>> interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>> + iommus = <&apps_smmu 0x140 0>;
>> snps,dis_u2_susphy_quirk;
>> snps,dis_enblslpm_quirk;
>> phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
>> @@ -742,6 +745,94 @@ spmi_bus: spmi@c440000 {
>> cell-index = <0>;
>> };
>>
>> + apps_smmu: iommu@15000000 {
>> + compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
>> + reg = <0 0x15000000 0 0x100000>;
>> + #iommu-cells = <2>;
>> + #global-interrupts = <1>;
>> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> remoteproc_adsp: remoteproc@17300000 {
>> compatible = "qcom,sm8150-adsp-pas";
>> reg = <0x0 0x17300000 0x0 0x4040>;
>> --
>> 2.26.1
>>
^ permalink raw reply
* Re: [PATCH 5/6] arm64: dts: qcom: add sm8150 hdk dts
From: Bjorn Andersson @ 2020-05-29 3:01 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20200524023815.21789-6-jonathan@marek.ca>
On Sat 23 May 19:38 PDT 2020, Jonathan Marek wrote:
> Add initial HDK855 dts, based on sm8150-mtp, with a few changes.
>
Happy to see this on the list Jonathan, just some minor things on the
remoteproc nodes below.
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 461 ++++++++++++++++++++++++
> 2 files changed, 462 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sm8150-hdk.dts
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index cc103f7020fd..e5dbd8b63951 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -22,6 +22,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
> diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts
[..]
> +/ {
> + model = "Qualcomm Technologies, Inc. SM8150 HDK";
> + compatible = "qcom,sm8150-hdk";
> +
> + aliases {
> + serial0 = &uart2;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + vph_pwr: vph-pwr-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vph_pwr";
> + regulator-min-microvolt = <3700000>;
> + regulator-max-microvolt = <3700000>;
> + };
> +
> + /*
> + * Apparently RPMh does not provide support for PM8150 S4 because it
> + * is always-on; model it as a fixed regulator.
> + */
One day we should stop being surprised by this and drop the "Apparently"
from this comment ;)
> + vreg_s4a_1p8: pm8150-s4 {
> + compatible = "regulator-fixed";
> + regulator-name = "vreg_s4a_1p8";
> +
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +
> + regulator-always-on;
> + regulator-boot-on;
> +
> + vin-supply = <&vph_pwr>;
> + };
[..]
> +&remoteproc_adsp {
> + status = "okay";
It would be nice to see a
firmware-name = "qcom/sm8150/adsp.mbn";
here. Because if we ever end up pushing firmware to linux-firmware this
DTB would continue to work.
Use https://github.com/andersson/pil-squasher to get mbn files out of
the mdt+bXX files for your testing (or just rename/symlink the mdt to
mbn for now).
> +};
> +
> +&remoteproc_cdsp {
> + status = "okay";
firmware-name = "qcom/sm8150/cdsp.mbn";
> +};
> +
> +&remoteproc_slpi {
> + status = "okay";
firmware-name = "qcom/sm8150/slpi.mbn";
Regards,
Bjorn
> +};
> +
> +&tlmm {
> + gpio-reserved-ranges = <0 4>, <126 4>;
> +};
> +
> +&uart2 {
> + status = "okay";
> +};
> +
> +&ufs_mem_hc {
> + status = "okay";
> +
> + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
> +
> + vcc-supply = <&vreg_l10a_2p5>;
> + vcc-max-microamp = <750000>;
> + vccq-supply = <&vreg_l9a_1p2>;
> + vccq-max-microamp = <700000>;
> + vccq2-supply = <&vreg_s4a_1p8>;
> + vccq2-max-microamp = <750000>;
> +};
> +
> +&ufs_mem_phy {
> + status = "okay";
> +
> + vdda-phy-supply = <&vdda_ufs_2ln_core_1>;
> + vdda-max-microamp = <90200>;
> + vdda-pll-supply = <&vreg_l3c_1p2>;
> + vdda-pll-max-microamp = <19000>;
> +};
> +
> +&usb_1_hsphy {
> + status = "okay";
> + vdda-pll-supply = <&vdd_usb_hs_core>;
> + vdda33-supply = <&vdda_usb_hs_3p1>;
> + vdda18-supply = <&vdda_usb_hs_1p8>;
> +};
> +
> +&usb_2_hsphy {
> + status = "okay";
> + vdda-pll-supply = <&vdd_usb_hs_core>;
> + vdda33-supply = <&vdda_usb_hs_3p1>;
> + vdda18-supply = <&vdda_usb_hs_1p8>;
> +};
> +
> +&usb_1_qmpphy {
> + status = "okay";
> + vdda-phy-supply = <&vreg_l3c_1p2>;
> + vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
> +};
> +
> +&usb_2_qmpphy {
> + status = "okay";
> + vdda-phy-supply = <&vreg_l3c_1p2>;
> + vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
> +};
> +
> +&usb_1 {
> + status = "okay";
> +};
> +
> +&usb_2 {
> + status = "okay";
> +};
> +
> +&usb_1_dwc3 {
> + dr_mode = "peripheral";
> +};
> +
> +&usb_2_dwc3 {
> + dr_mode = "host";
> +};
> --
> 2.26.1
>
^ permalink raw reply
* Re: [PATCH 6/6] arm64: dts: qcom: add sm8250 hdk dts
From: Bjorn Andersson @ 2020-05-29 3:03 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20200524023815.21789-7-jonathan@marek.ca>
On Sat 23 May 19:38 PDT 2020, Jonathan Marek wrote:
> Add initial HDK865 dts, based on sm8250-mtp, with a few changes.
> Notably, regulator configs are changed a bit.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 454 ++++++++++++++++++++++++
> 2 files changed, 455 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sm8250-hdk.dts
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index e5dbd8b63951..4649e8bc5034 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -24,6 +24,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
> diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
> new file mode 100644
> index 000000000000..d35014bf4f81
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
> @@ -0,0 +1,454 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include "sm8250.dtsi"
> +#include "pm8150.dtsi"
> +#include "pm8150b.dtsi"
> +#include "pm8150l.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. SM8250 HDK";
> + compatible = "qcom,sm8250-hdk";
compatible = "qcom,sm8250-hdk", "qcom,sm8250";
Apart from that this looks good!
Thanks,
Bjorn
^ permalink raw reply
* Re: [PATCH 0/6] arm64: dts: qcom: smmu/USB nodes and HDK855/HDK865 dts
From: Bjorn Andersson @ 2020-05-29 3:05 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, Andy Gross,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Rob Herring
In-Reply-To: <20200524023815.21789-1-jonathan@marek.ca>
On Sat 23 May 19:38 PDT 2020, Jonathan Marek wrote:
> Add dts nodes for apps_smmu and USB for both sm8150 and sm8250.
>
> Also add initial dts files for HDK855 and HDK865, based on mtp dts, with a
> few changes. Notably, the HDK865 dts has regulator config changed a bit based
> on downstream (I think sm8250-mtp.dts is wrong and copied too much from sm8150).
Can you please elaborate on this discrepancy? I do remember seeing
something odd when looking at this, but it seems like I didn't document
it anywhere...
Thanks,
Bjorn
>
> Jonathan Marek (6):
> arm64: dts: qcom: sm8150: add apps_smmu node
> arm64: dts: qcom: sm8250: add apps_smmu node
> arm64: dts: qcom: sm8150: Add secondary USB and PHY nodes
> arm64: dts: qcom: sm8250: Add USB and PHY device nodes
> arm64: dts: qcom: add sm8150 hdk dts
> arm64: dts: qcom: add sm8250 hdk dts
>
> arch/arm64/boot/dts/qcom/Makefile | 2 +
> arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 461 ++++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 180 +++++++++
> arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 454 +++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 287 +++++++++++++++
> 5 files changed, 1384 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sm8150-hdk.dts
> create mode 100644 arch/arm64/boot/dts/qcom/sm8250-hdk.dts
>
> --
> 2.26.1
>
^ permalink raw reply
* Re: [PATCH v2 0/4] Spilt PCIe node to comply with hardware design
From: Ryder Lee @ 2020-05-29 3:05 UTC (permalink / raw)
To: chuanjia.liu
Cc: robh+dt, matthias.bgg, lorenzo.pieralisi, amurray, linux-pci,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
bhelgaas, jianjun.wang, yong.wu, srv_heupstream
In-Reply-To: <20200528061648.32078-1-chuanjia.liu@mediatek.com>
On Thu, 2020-05-28 at 14:16 +0800, chuanjia.liu@mediatek.com wrote:
> There are two independent PCIe controllers in MT2712/MT7622 platform,
> and each of them should contain an independent MSI domain.
>
> In current architecture, MSI domain will be inherited from the root
> bridge, and all of the devices will share the same MSI domain.
> Hence that, the PCIe devices will not work properly if the irq number
> which required is more than 32.
>
> Split the PCIe node for MT2712/MT7622 platform to fix MSI issue and
> comply with the hardware design.
>
> change note:
> v2: change the allocation of mt2712 PCIe MMIO space due to the allcation
> size is not right in v1.
>
> chuanjia.liu (4):
> dt-bindings: PCI: Mediatek: Update PCIe binding
> PCI: mediatek: Use regmap to get shared pcie-cfg base
> arm64: dts: mediatek: Split PCIe node for MT2712/MT7622
> ARM: dts: mediatek: Update mt7629 PCIe node
>
> .../bindings/pci/mediatek-pcie-cfg.yaml | 38 +++++
> .../devicetree/bindings/pci/mediatek-pcie.txt | 144 +++++++++++-------
> arch/arm/boot/dts/mt7629-rfb.dts | 3 +-
> arch/arm/boot/dts/mt7629.dtsi | 23 +--
> arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 75 +++++----
> .../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 16 +-
> arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 6 +-
> arch/arm64/boot/dts/mediatek/mt7622.dtsi | 68 ++++++---
> drivers/pci/controller/pcie-mediatek.c | 25 ++-
> 9 files changed, 258 insertions(+), 140 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml
>
> --
> 2.18.0
>
>
For the series:
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
^ permalink raw reply
* Re: [PATCH 3/4] mailbox: qcom: Add ipq6018 apcs compatible
From: Bjorn Andersson @ 2020-05-29 3:11 UTC (permalink / raw)
To: Sivaprakash Murugesan
Cc: agross, robh+dt, jassisinghbrar, linux-arm-msm, devicetree,
linux-kernel
In-Reply-To: <1590583092-24290-4-git-send-email-sivaprak@codeaurora.org>
On Wed 27 May 05:38 PDT 2020, Sivaprakash Murugesan wrote:
> The Qualcomm ipq6018 has apcs block, add compatible for the same.
> Also, the apcs provides a clock controller functionality similar
> to msm8916 but the clock driver is different.
>
> Create a child platform device based on the apcs compatible for the
> clock controller functionality.
>
> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
> ---
> drivers/mailbox/qcom-apcs-ipc-mailbox.c | 23 ++++++++++++++---------
> 1 file changed, 14 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> index eeebafd..db3f9518 100644
> --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> @@ -45,6 +45,13 @@ static const struct mbox_chan_ops qcom_apcs_ipc_ops = {
> .send_data = qcom_apcs_ipc_send_data,
> };
>
> +static const struct of_device_id apcs_clk_match_table[] = {
> + { .compatible = "qcom,ipq6018-apcs-apps-global", .data = "qcom,apss-ipq6018-clk", },
> + { .compatible = "qcom,msm8916-apcs-kpss-global", .data = "qcom-apcs-msm8916-clk", },
> + { .compatible = "qcom,qcs404-apcs-apps-global", .data = "qcom-apcs-msm8916-clk", },
> + {}
> +};
> +
> static int qcom_apcs_ipc_probe(struct platform_device *pdev)
> {
> struct qcom_apcs_ipc *apcs;
> @@ -54,11 +61,7 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
> void __iomem *base;
> unsigned long i;
> int ret;
> - const struct of_device_id apcs_clk_match_table[] = {
> - { .compatible = "qcom,msm8916-apcs-kpss-global", },
> - { .compatible = "qcom,qcs404-apcs-apps-global", },
> - {}
> - };
> + const struct of_device_id *clk_device;
>
> apcs = devm_kzalloc(&pdev->dev, sizeof(*apcs), GFP_KERNEL);
> if (!apcs)
> @@ -93,11 +96,12 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
> return ret;
> }
>
> - if (of_match_device(apcs_clk_match_table, &pdev->dev)) {
> + clk_device = of_match_device(apcs_clk_match_table, &pdev->dev);
I think you should replace the direct integer in qcom_apcs_ipc_of_match
with a small struct containing offset and the clock device's name -
allowing the latter to be omitted.
That avoids the apcs_clk_match_table being unreferenced when this is
compiled without CONFIG_OF and it removes the need for two of_device_id
arrays.
Regards,
Bjorn
> + if (clk_device) {
> apcs->clk = platform_device_register_data(&pdev->dev,
> - "qcom-apcs-msm8916-clk",
> - PLATFORM_DEVID_NONE,
> - NULL, 0);
> + clk_device->data,
> + PLATFORM_DEVID_NONE,
> + NULL, 0);
> if (IS_ERR(apcs->clk))
> dev_err(&pdev->dev, "failed to register APCS clk\n");
> }
> @@ -126,6 +130,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = {
> { .compatible = "qcom,sc7180-apss-shared", .data = (void *)12 },
> { .compatible = "qcom,sdm845-apss-shared", .data = (void *)12 },
> { .compatible = "qcom,sm8150-apss-shared", .data = (void *)12 },
> + { .compatible = "qcom,ipq6018-apcs-apps-global", .data = (void *)8 },
> { .compatible = "qcom,ipq8074-apcs-apps-global", .data = (void *)8 },
> {}
> };
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH 0/6] arm64: dts: qcom: smmu/USB nodes and HDK855/HDK865 dts
From: Jonathan Marek @ 2020-05-29 3:15 UTC (permalink / raw)
To: Bjorn Andersson
Cc: linux-arm-msm, Andy Gross,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Rob Herring
In-Reply-To: <20200529030505.GY279327@builder.lan>
On 5/28/20 11:05 PM, Bjorn Andersson wrote:
> On Sat 23 May 19:38 PDT 2020, Jonathan Marek wrote:
>
>> Add dts nodes for apps_smmu and USB for both sm8150 and sm8250.
>>
>> Also add initial dts files for HDK855 and HDK865, based on mtp dts, with a
>> few changes. Notably, the HDK865 dts has regulator config changed a bit based
>> on downstream (I think sm8250-mtp.dts is wrong and copied too much from sm8150).
>
> Can you please elaborate on this discrepancy? I do remember seeing
> something odd when looking at this, but it seems like I didn't document
> it anywhere...
>
> Thanks,
> Bjorn
>
Mainly there's a few regulators with different min/max voltage values.
For example with l16a, downstream has min/max 3024000/3304000 but
upstream sm8250-mtp has 2704000/2960000. I also added l18a.
>>
>> Jonathan Marek (6):
>> arm64: dts: qcom: sm8150: add apps_smmu node
>> arm64: dts: qcom: sm8250: add apps_smmu node
>> arm64: dts: qcom: sm8150: Add secondary USB and PHY nodes
>> arm64: dts: qcom: sm8250: Add USB and PHY device nodes
>> arm64: dts: qcom: add sm8150 hdk dts
>> arm64: dts: qcom: add sm8250 hdk dts
>>
>> arch/arm64/boot/dts/qcom/Makefile | 2 +
>> arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 461 ++++++++++++++++++++++++
>> arch/arm64/boot/dts/qcom/sm8150.dtsi | 180 +++++++++
>> arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 454 +++++++++++++++++++++++
>> arch/arm64/boot/dts/qcom/sm8250.dtsi | 287 +++++++++++++++
>> 5 files changed, 1384 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/sm8150-hdk.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/sm8250-hdk.dts
>>
>> --
>> 2.26.1
>>
^ permalink raw reply
* Re: [PATCH 1/6] arm64: dts: qcom: sm8150: add apps_smmu node
From: Bjorn Andersson @ 2020-05-29 3:15 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <d0908f34-a698-3449-35b9-7a98e9641295@marek.ca>
On Thu 28 May 20:02 PDT 2020, Jonathan Marek wrote:
>
>
> On 5/28/20 10:52 PM, Bjorn Andersson wrote:
> > On Sat 23 May 19:38 PDT 2020, Jonathan Marek wrote:
> >
> > > Add the apps_smmu node for sm8150. Note that adding the iommus field for
> > > UFS is required because initializing the iommu removes the bypass mapping
> > > that created by the bootloader.
> > >
> >
> > Unrelated to the patch itself; how do you disable the splash screen on
> > 8150? "fastboot oem select-display-panel none" doesn't seem to work for
> > me on the MTP - and hence this would prevent my device from booting.
> >
> > Thanks,
> > Bjorn
> >
>
> I don't have a MTP, but on HDK855, "fastboot oem select-display-panel none"
> combined with setting the physical switch to HDMI mode (which switches off
> the 1440x2560 panel) gets it to not setup the display at all (just the
> fastboot command isn't enough).
>
Okay, I don't think we have anything equivalent on the MTP, but good to
know.
> With HDK865 though that doesn't work and I have a hack to work around it
> (writing 0 to INTF_TIMING_ENGINE_EN early on in boot will stop video mode
> scanout and it won't crash).
>
Then we need to sort this out in the arm-smmu driver before we can
enable the apps_smmu node on 8250. I did receive some guidance from Will
on the subject and have started looking into this.
Thanks,
Bjorn
> > > Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> > > ---
> > > arch/arm64/boot/dts/qcom/sm8150.dtsi | 91 ++++++++++++++++++++++++++++
> > > 1 file changed, 91 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > > index a36512d1f6a1..acb839427b12 100644
> > > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > > @@ -442,6 +442,8 @@ ufs_mem_hc: ufshc@1d84000 {
> > > resets = <&gcc GCC_UFS_PHY_BCR>;
> > > reset-names = "rst";
> > > + iommus = <&apps_smmu 0x300 0>;
> > > +
> > > clock-names =
> > > "core_clk",
> > > "bus_aggr_clk",
> > > @@ -706,6 +708,7 @@ usb_1_dwc3: dwc3@a600000 {
> > > compatible = "snps,dwc3";
> > > reg = <0 0x0a600000 0 0xcd00>;
> > > interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> > > + iommus = <&apps_smmu 0x140 0>;
> > > snps,dis_u2_susphy_quirk;
> > > snps,dis_enblslpm_quirk;
> > > phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
> > > @@ -742,6 +745,94 @@ spmi_bus: spmi@c440000 {
> > > cell-index = <0>;
> > > };
> > > + apps_smmu: iommu@15000000 {
> > > + compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
> > > + reg = <0 0x15000000 0 0x100000>;
> > > + #iommu-cells = <2>;
> > > + #global-interrupts = <1>;
> > > + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
> > > + };
> > > +
> > > remoteproc_adsp: remoteproc@17300000 {
> > > compatible = "qcom,sm8150-adsp-pas";
> > > reg = <0x0 0x17300000 0x0 0x4040>;
> > > --
> > > 2.26.1
> > >
^ permalink raw reply
* Re: [PATCH 3/3] ARM: dts: qcom: Add MikroTik RB3011
From: Bjorn Andersson @ 2020-05-29 3:20 UTC (permalink / raw)
To: Jonathan McDowell; +Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <75390e66c9e6e36ddd42dc7f54cac28dfd7a24b9.1589824955.git.noodles@earth.li>
On Mon 18 May 11:10 PDT 2020, Jonathan McDowell wrote:
> This patch adds a DTS file for the MikroTik RouterBoard 3011, which is a
> 1U rackmount router based on the IPQ8064, supporting the serial UART,
> dual QCA8337 Gigabit ethernet switches, boot loader NOR and user LED
> device.
>
> Signed-off-by: Jonathan McDowell <noodles@earth.li>
Patch 2 and 3 picked up for 5.9
Thanks,
Bjorn
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 308 ++++++++++++++++++++++
> 2 files changed, 309 insertions(+)
> create mode 100644 arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index e8dd99201397..e697a4bd7426 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -884,6 +884,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
> qcom-ipq4019-ap.dk07.1-c1.dtb \
> qcom-ipq4019-ap.dk07.1-c2.dtb \
> qcom-ipq8064-ap148.dtb \
> + qcom-ipq8064-rb3011.dtb \
> qcom-msm8660-surf.dtb \
> qcom-msm8960-cdp.dtb \
> qcom-msm8974-fairphone-fp2.dtb \
> diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
> new file mode 100644
> index 000000000000..282b89ce3d45
> --- /dev/null
> +++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
> @@ -0,0 +1,308 @@
> +// SPDX-License-Identifier: GPL-2.0
> +#include "qcom-ipq8064.dtsi"
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> + model = "MikroTik RB3011UiAS-RM";
> + compatible = "mikrotik,rb3011";
> +
> + aliases {
> + serial0 = &gsbi7_serial;
> + ethernet0 = &gmac0;
> + ethernet1 = &gmac3;
> + mdio-gpio0 = &mdio0;
> + mdio-gpio1 = &mdio1;
> + };
> +
> + chosen {
> + bootargs = "loglevel=8 console=ttyMSM0,115200";
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory@0 {
> + reg = <0x42000000 0x3e000000>;
> + device_type = "memory";
> + };
> +
> + mdio0: mdio@0 {
> + status = "okay";
> + compatible = "virtual,mdio-gpio";
> + gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
> + <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pinctrl-0 = <&mdio0_pins>;
> + pinctrl-names = "default";
> +
> + switch0: switch@10 {
> + compatible = "qca,qca8337";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dsa,member = <0 0>;
> +
> + pinctrl-0 = <&sw0_reset_pin>;
> + pinctrl-names = "default";
> +
> + reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
> + reg = <0x10>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + switch0cpu: port@0 {
> + reg = <0>;
> + label = "cpu";
> + ethernet = <&gmac0>;
> + phy-mode = "rgmii-id";
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + label = "sw1";
> + };
> +
> + port@2 {
> + reg = <2>;
> + label = "sw2";
> + };
> +
> + port@3 {
> + reg = <3>;
> + label = "sw3";
> + };
> +
> + port@4 {
> + reg = <4>;
> + label = "sw4";
> + };
> +
> + port@5 {
> + reg = <5>;
> + label = "sw5";
> + };
> + };
> + };
> + };
> +
> + mdio1: mdio@1 {
> + status = "okay";
> + compatible = "virtual,mdio-gpio";
> + gpios = <&qcom_pinmux 11 GPIO_ACTIVE_HIGH>,
> + <&qcom_pinmux 10 GPIO_ACTIVE_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pinctrl-0 = <&mdio1_pins>;
> + pinctrl-names = "default";
> +
> + switch1: switch@14 {
> + compatible = "qca,qca8337";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dsa,member = <1 0>;
> +
> + pinctrl-0 = <&sw1_reset_pin>;
> + pinctrl-names = "default";
> +
> + reset-gpios = <&qcom_pinmux 17 GPIO_ACTIVE_LOW>;
> + reg = <0x10>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + switch1cpu: port@0 {
> + reg = <0>;
> + label = "cpu";
> + ethernet = <&gmac3>;
> + phy-mode = "sgmii";
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + label = "sw6";
> + };
> +
> + port@2 {
> + reg = <2>;
> + label = "sw7";
> + };
> +
> + port@3 {
> + reg = <3>;
> + label = "sw8";
> + };
> +
> + port@4 {
> + reg = <4>;
> + label = "sw9";
> + };
> +
> + port@5 {
> + reg = <5>;
> + label = "sw10";
> + };
> + };
> + };
> + };
> +
> + soc {
> + gsbi5: gsbi@1a200000 {
> + qcom,mode = <GSBI_PROT_SPI>;
> + status = "okay";
> +
> + spi4: spi@1a280000 {
> + status = "okay";
> + spi-max-frequency = <50000000>;
> +
> + pinctrl-0 = <&spi_pins>;
> + pinctrl-names = "default";
> +
> + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
> +
> + norflash: s25fl016k@0 {
> + compatible = "jedec,spi-nor";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + spi-max-frequency = <50000000>;
> + reg = <0>;
> +
> + partition@0 {
> + label = "RouterBoot";
> + reg = <0x0 0x40000>;
> + };
> + };
> + };
> + };
> +
> + gpio_keys {
> + compatible = "gpio-keys";
> + pinctrl-0 = <&buttons_pins>;
> + pinctrl-names = "default";
> +
> + button@1 {
> + label = "reset";
> + linux,code = <KEY_RESTART>;
> + gpios = <&qcom_pinmux 66 GPIO_ACTIVE_LOW>;
> + linux,input-type = <1>;
> + debounce-interval = <60>;
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + pinctrl-0 = <&leds_pins>;
> + pinctrl-names = "default";
> +
> + led@7 {
> + label = "rb3011:green:user";
> + gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> + };
> +
> + };
> +};
> +
> +&gmac0 {
> + status = "okay";
> +
> + phy-mode = "rgmii";
> + qcom,id = <0>;
> + phy-handle = <&switch0cpu>;
> +
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> +};
> +
> +&gmac3 {
> + status = "okay";
> +
> + phy-mode = "sgmii";
> + qcom,id = <3>;
> + phy-handle = <&switch1cpu>;
> +
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> +};
> +
> +&gsbi7 {
> + status = "okay";
> + qcom,mode = <GSBI_PROT_I2C_UART>;
> +};
> +
> +&gsbi7_serial {
> + status = "okay";
> +};
> +
> +&qcom_pinmux {
> + buttons_pins: buttons_pins {
> + mux {
> + pins = "gpio66";
> + drive-strength = <16>;
> + bias-disable;
> + };
> + };
> +
> + leds_pins: leds_pins {
> + mux {
> + pins = "gpio33";
> + drive-strength = <16>;
> + bias-disable;
> + };
> + };
> +
> + mdio0_pins: mdio0_pins {
> + mux {
> + pins = "gpio0", "gpio1";
> + function = "gpio";
> + drive-strength = <8>;
> + bias-disable;
> + };
> + };
> +
> + mdio1_pins: mdio1_pins {
> + mux {
> + pins = "gpio10", "gpio11";
> + function = "gpio";
> + drive-strength = <8>;
> + bias-disable;
> + };
> + };
> +
> + sw0_reset_pin: sw0_reset_pin {
> + mux {
> + pins = "gpio16";
> + drive-strength = <16>;
> + function = "gpio";
> + bias-disable;
> + input-disable;
> + };
> + };
> +
> + sw1_reset_pin: sw1_reset_pin {
> + mux {
> + pins = "gpio17";
> + drive-strength = <16>;
> + function = "gpio";
> + bias-disable;
> + input-disable;
> + };
> + };
> +};
> --
> 2.20.1
>
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: sm8250: use dt-bindings defines for clocks
From: Bjorn Andersson @ 2020-05-29 3:22 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20200523131213.18653-1-jonathan@marek.ca>
On Sat 23 May 06:12 PDT 2020, Jonathan Marek wrote:
> Use the dt-bindings defines for qupv3_id_1 node's clocks.
>
Applied
Thanks,
Bjorn
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index 9c210fbac65e..04c9c215ffcd 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -292,7 +292,8 @@ qupv3_id_1: geniqup@ac0000 {
> compatible = "qcom,geni-se-qup";
> reg = <0x0 0x00ac0000 0x0 0x6000>;
> clock-names = "m-ahb", "s-ahb";
> - clocks = <&gcc 133>, <&gcc 134>;
> + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
> + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> #address-cells = <2>;
> #size-cells = <2>;
> ranges;
> @@ -302,7 +303,7 @@ uart2: serial@a90000 {
> compatible = "qcom,geni-debug-uart";
> reg = <0x0 0x00a90000 0x0 0x4000>;
> clock-names = "se";
> - clocks = <&gcc 113>;
> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
> interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
> --
> 2.26.1
>
^ permalink raw reply
* Re: [PATCH v6 3/5] remoteproc: qcom: Update PIL relocation info on load
From: kbuild test robot @ 2020-05-29 3:06 UTC (permalink / raw)
To: Bjorn Andersson, Andy Gross, Ohad Ben-Cohen
Cc: kbuild-all, Rob Herring, linux-arm-msm, linux-remoteproc,
devicetree, linux-kernel, Vinod Koul
In-Reply-To: <20200527054850.2067032-4-bjorn.andersson@linaro.org>
[-- Attachment #1: Type: text/plain, Size: 5788 bytes --]
Hi Bjorn,
I love your patch! Perhaps something to improve:
[auto build test WARNING on next-20200526]
[also build test WARNING on v5.7-rc7]
[cannot apply to robh/for-next linus/master agross-msm/qcom/for-next remoteproc/for-next rpmsg/for-next hwspinlock/for-next v5.7-rc7 v5.7-rc6 v5.7-rc5]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Bjorn-Andersson/remoteproc-qcom-PIL-info-support/20200527-135911
base: b0523c7b1c9d0edcd6c0fe6d2cb558a9ad5c60a8
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp@intel.com>
All warnings (new ones prefixed by >>, old ones prefixed by <<):
>> drivers/remoteproc/qcom_pil_info.c:69:5: warning: no previous prototype for 'qcom_pil_info_store' [-Wmissing-prototypes]
69 | int qcom_pil_info_store(const char *image, phys_addr_t base, size_t size)
| ^~~~~~~~~~~~~~~~~~~
vim +/qcom_pil_info_store +69 drivers/remoteproc/qcom_pil_info.c
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 60
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 61 /**
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 62 * qcom_pil_info_store() - store PIL information of image in IMEM
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 63 * @image: name of the image
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 64 * @base: base address of the loaded image
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 65 * @size: size of the loaded image
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 66 *
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 67 * Return: 0 on success, negative errno on failure
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 68 */
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 @69 int qcom_pil_info_store(const char *image, phys_addr_t base, size_t size)
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 70 {
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 71 char buf[PIL_RELOC_NAME_LEN];
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 72 void __iomem *entry;
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 73 int ret;
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 74 int i;
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 75
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 76 mutex_lock(&reloc_mutex);
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 77 ret = qcom_pil_info_init();
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 78 if (ret < 0) {
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 79 mutex_unlock(&reloc_mutex);
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 80 return ret;
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 81 }
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 82
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 83 for (i = 0; i < _reloc.num_entries; i++) {
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 84 entry = _reloc.base + i * sizeof(struct pil_reloc_entry);
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 85
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 86 memcpy_fromio(buf, entry, PIL_RELOC_NAME_LEN);
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 87
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 88 /*
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 89 * An empty record means we didn't find it, given that the
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 90 * records are packed.
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 91 */
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 92 if (!buf[0])
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 93 goto found_unused;
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 94
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 95 if (!strncmp(buf, image, PIL_RELOC_NAME_LEN))
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 96 goto found_existing;
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 97 }
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 98
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 99 pr_warn("insufficient PIL info slots\n");
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 100 mutex_unlock(&reloc_mutex);
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 101 return -ENOMEM;
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 102
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 103 found_unused:
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 104 memcpy_toio(entry, image, PIL_RELOC_NAME_LEN);
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 105 found_existing:
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 106 writel(base, entry + offsetof(struct pil_reloc_entry, base));
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 107 writel(size, entry + offsetof(struct pil_reloc_entry, size));
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 108 mutex_unlock(&reloc_mutex);
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 109
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 110 return 0;
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 111 }
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 112 EXPORT_SYMBOL_GPL(qcom_pil_info_store);
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 113
:::::: The code at line 69 was first introduced by commit
:::::: 41d96cc2fee2c1143685357ad2929be0a7cf5d0f remoteproc: qcom: Introduce helper to store pil info in IMEM
:::::: TO: Bjorn Andersson <bjorn.andersson@linaro.org>
:::::: CC: 0day robot <lkp@intel.com>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 72793 bytes --]
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: sm8250: rename spmi node to spmi_bus
From: Bjorn Andersson @ 2020-05-29 3:26 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20200523132104.31046-1-jonathan@marek.ca>
On Sat 23 May 06:21 PDT 2020, Jonathan Marek wrote:
> The pm8150 dtsi files refer to it as spmi_bus, so change it.
>
Applied. Also removed "qcom," from the node name while we're poking at
the line.
Thanks,
Bjorn
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index 04c9c215ffcd..a273b99bf1e6 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -578,7 +578,7 @@ pdc: interrupt-controller@b220000 {
> interrupt-controller;
> };
>
> - spmi: qcom,spmi@c440000 {
> + spmi_bus: qcom,spmi@c440000 {
> compatible = "qcom,spmi-pmic-arb";
> reg = <0x0 0x0c440000 0x0 0x0001100>,
> <0x0 0x0c600000 0x0 0x2000000>,
> --
> 2.26.1
>
^ permalink raw reply
* Re: [PATCH 1/6] arm64: dts: qcom: sm8150: add apps_smmu node
From: Jonathan Marek @ 2020-05-29 3:34 UTC (permalink / raw)
To: Bjorn Andersson
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20200529031520.GA1799770@builder.lan>
On 5/28/20 11:15 PM, Bjorn Andersson wrote:
> On Thu 28 May 20:02 PDT 2020, Jonathan Marek wrote:
>
>>
>>
>> On 5/28/20 10:52 PM, Bjorn Andersson wrote:
>>> On Sat 23 May 19:38 PDT 2020, Jonathan Marek wrote:
>>>
>>>> Add the apps_smmu node for sm8150. Note that adding the iommus field for
>>>> UFS is required because initializing the iommu removes the bypass mapping
>>>> that created by the bootloader.
>>>>
>>>
>>> Unrelated to the patch itself; how do you disable the splash screen on
>>> 8150? "fastboot oem select-display-panel none" doesn't seem to work for
>>> me on the MTP - and hence this would prevent my device from booting.
>>>
>>> Thanks,
>>> Bjorn
>>>
>>
>> I don't have a MTP, but on HDK855, "fastboot oem select-display-panel none"
>> combined with setting the physical switch to HDMI mode (which switches off
>> the 1440x2560 panel) gets it to not setup the display at all (just the
>> fastboot command isn't enough).
>>
>
> Okay, I don't think we have anything equivalent on the MTP, but good to
> know.
>
>> With HDK865 though that doesn't work and I have a hack to work around it
>> (writing 0 to INTF_TIMING_ENGINE_EN early on in boot will stop video mode
>> scanout and it won't crash).
>>
>
> Then we need to sort this out in the arm-smmu driver before we can
> enable the apps_smmu node on 8250. I did receive some guidance from Will
> on the subject and have started looking into this.
>
That's annoying because a lot depends on apps_mmu. GPU is an exception
with its own MMU but pretty much everything else uses apps_smmu (does it
make sense to add USB nodes if it won't work without apps_smmu?) Is this
something that will get resolved soon?
FWIW, I have another sm8250 board which does not need the workaround
(its bootloader does not set up the display). AFAIK modifying the
bootloader to not set up any display is a trivial modification (assuming
that's an option).
> Thanks,
> Bjorn
>
>>>> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/sm8150.dtsi | 91 ++++++++++++++++++++++++++++
>>>> 1 file changed, 91 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
>>>> index a36512d1f6a1..acb839427b12 100644
>>>> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
>>>> @@ -442,6 +442,8 @@ ufs_mem_hc: ufshc@1d84000 {
>>>> resets = <&gcc GCC_UFS_PHY_BCR>;
>>>> reset-names = "rst";
>>>> + iommus = <&apps_smmu 0x300 0>;
>>>> +
>>>> clock-names =
>>>> "core_clk",
>>>> "bus_aggr_clk",
>>>> @@ -706,6 +708,7 @@ usb_1_dwc3: dwc3@a600000 {
>>>> compatible = "snps,dwc3";
>>>> reg = <0 0x0a600000 0 0xcd00>;
>>>> interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>>>> + iommus = <&apps_smmu 0x140 0>;
>>>> snps,dis_u2_susphy_quirk;
>>>> snps,dis_enblslpm_quirk;
>>>> phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
>>>> @@ -742,6 +745,94 @@ spmi_bus: spmi@c440000 {
>>>> cell-index = <0>;
>>>> };
>>>> + apps_smmu: iommu@15000000 {
>>>> + compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
>>>> + reg = <0 0x15000000 0 0x100000>;
>>>> + #iommu-cells = <2>;
>>>> + #global-interrupts = <1>;
>>>> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
>>>> + };
>>>> +
>>>> remoteproc_adsp: remoteproc@17300000 {
>>>> compatible = "qcom,sm8150-adsp-pas";
>>>> reg = <0x0 0x17300000 0x0 0x4040>;
>>>> --
>>>> 2.26.1
>>>>
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: sm8250: sort nodes by physical address
From: Bjorn Andersson @ 2020-05-29 3:37 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20200523132223.31108-1-jonathan@marek.ca>
On Sat 23 May 06:22 PDT 2020, Jonathan Marek wrote:
> Other dts have nodes sorted by physical address, be consistent with that.
>
This didn't apply cleanly, because we haven't yet migrated the hwlock to
the yet to be approved binding and I don't have a usb node.
I resolved it and applied the patch.
Thanks,
Bjorn
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 176 +++++++++++++--------------
> 1 file changed, 88 insertions(+), 88 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index a273b99bf1e6..bc8a14df60e5 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -379,6 +379,12 @@ ufs_mem_phy_lanes: lanes@1d87400 {
> };
> };
>
> + tcsr_mutex: hwlock@1f40000 {
> + compatible = "qcom,tcsr-mutex";
> + reg = <0x0 0x01f40000 0x0 0x40000>;
> + #hwlock-cells = <1>;
> + };
> +
> usb_1_hsphy: phy@88e3000 {
> compatible = "qcom,sm8250-usb-hs-phy",
> "qcom,usb-snps-hs-7nm-phy";
> @@ -559,15 +565,6 @@ usb_2_dwc3: dwc3@a800000 {
> };
> };
>
> - intc: interrupt-controller@17a00000 {
> - compatible = "arm,gic-v3";
> - #interrupt-cells = <3>;
> - interrupt-controller;
> - reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
> - <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
> - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> - };
> -
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,sm8250-pdc", "qcom,pdc";
> reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
> @@ -596,85 +593,6 @@ spmi_bus: qcom,spmi@c440000 {
> #interrupt-cells = <4>;
> };
>
> - apps_rsc: rsc@18200000 {
> - label = "apps_rsc";
> - compatible = "qcom,rpmh-rsc";
> - reg = <0x0 0x18200000 0x0 0x10000>,
> - <0x0 0x18210000 0x0 0x10000>,
> - <0x0 0x18220000 0x0 0x10000>;
> - reg-names = "drv-0", "drv-1", "drv-2";
> - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> - qcom,tcs-offset = <0xd00>;
> - qcom,drv-id = <2>;
> - qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
> - <WAKE_TCS 3>, <CONTROL_TCS 1>;
> -
> - rpmhcc: clock-controller {
> - compatible = "qcom,sm8250-rpmh-clk";
> - #clock-cells = <1>;
> - clock-names = "xo";
> - clocks = <&xo_board>;
> - };
> -
> - rpmhpd: power-controller {
> - compatible = "qcom,sm8250-rpmhpd";
> - #power-domain-cells = <1>;
> - operating-points-v2 = <&rpmhpd_opp_table>;
> -
> - rpmhpd_opp_table: opp-table {
> - compatible = "operating-points-v2";
> -
> - rpmhpd_opp_ret: opp1 {
> - opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
> - };
> -
> - rpmhpd_opp_min_svs: opp2 {
> - opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> - };
> -
> - rpmhpd_opp_low_svs: opp3 {
> - opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> - };
> -
> - rpmhpd_opp_svs: opp4 {
> - opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> - };
> -
> - rpmhpd_opp_svs_l1: opp5 {
> - opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> - };
> -
> - rpmhpd_opp_nom: opp6 {
> - opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> - };
> -
> - rpmhpd_opp_nom_l1: opp7 {
> - opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> - };
> -
> - rpmhpd_opp_nom_l2: opp8 {
> - opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
> - };
> -
> - rpmhpd_opp_turbo: opp9 {
> - opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> - };
> -
> - rpmhpd_opp_turbo_l1: opp10 {
> - opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> - };
> - };
> - };
> - };
> -
> - tcsr_mutex: hwlock@1f40000 {
> - compatible = "qcom,tcsr-mutex";
> - reg = <0x0 0x01f40000 0x0 0x40000>;
> - #hwlock-cells = <1>;
> - };
> -
> tlmm: pinctrl@f100000 {
> compatible = "qcom,sm8250-pinctrl";
> reg = <0 0x0f100000 0 0x300000>,
> @@ -690,6 +608,15 @@ tlmm: pinctrl@f100000 {
> wakeup-parent = <&pdc>;
> };
>
> + intc: interrupt-controller@17a00000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
> + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> timer@17c20000 {
> #address-cells = <2>;
> #size-cells = <2>;
> @@ -749,6 +676,79 @@ frame@17c2d000 {
> };
> };
>
> + apps_rsc: rsc@18200000 {
> + label = "apps_rsc";
> + compatible = "qcom,rpmh-rsc";
> + reg = <0x0 0x18200000 0x0 0x10000>,
> + <0x0 0x18210000 0x0 0x10000>,
> + <0x0 0x18220000 0x0 0x10000>;
> + reg-names = "drv-0", "drv-1", "drv-2";
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + qcom,tcs-offset = <0xd00>;
> + qcom,drv-id = <2>;
> + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
> + <WAKE_TCS 3>, <CONTROL_TCS 1>;
> +
> + rpmhcc: clock-controller {
> + compatible = "qcom,sm8250-rpmh-clk";
> + #clock-cells = <1>;
> + clock-names = "xo";
> + clocks = <&xo_board>;
> + };
> +
> + rpmhpd: power-controller {
> + compatible = "qcom,sm8250-rpmhpd";
> + #power-domain-cells = <1>;
> + operating-points-v2 = <&rpmhpd_opp_table>;
> +
> + rpmhpd_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + rpmhpd_opp_ret: opp1 {
> + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
> + };
> +
> + rpmhpd_opp_min_svs: opp2 {
> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> + };
> +
> + rpmhpd_opp_low_svs: opp3 {
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + };
> +
> + rpmhpd_opp_svs: opp4 {
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> + };
> +
> + rpmhpd_opp_svs_l1: opp5 {
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> + };
> +
> + rpmhpd_opp_nom: opp6 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> + };
> +
> + rpmhpd_opp_nom_l1: opp7 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> + };
> +
> + rpmhpd_opp_nom_l2: opp8 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
> + };
> +
> + rpmhpd_opp_turbo: opp9 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> + };
> +
> + rpmhpd_opp_turbo_l1: opp10 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> + };
> + };
> + };
> + };
> +
> cpufreq_hw: cpufreq@18591000 {
> compatible = "qcom,cpufreq-hw";
> reg = <0 0x18591000 0 0x1000>,
> --
> 2.26.1
>
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: sm8250: change ufs node name to ufshc
From: Bjorn Andersson @ 2020-05-29 3:40 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20200523175232.13721-1-jonathan@marek.ca>
On Sat 23 May 10:52 PDT 2020, Jonathan Marek wrote:
> The ufs-qcom driver checks that the name matches the androidboot.bootdevice
> parameter provided by the bootloader, which uses the name ufshc. Without
> this change UFS fails to probe.
>
Seems I only tested with UFS built as module, thanks for spotting this.
> I think this is broken behavior from the ufs-qcom driver, but using the
> name ufshc is consistent with dts for sdm845/sm8150/etc.
>
I agree. Patch applied...
Thanks,
Bjorn
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index e0344d3ba159..3bdce658c08a 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -309,7 +309,7 @@ uart2: serial@a90000 {
> };
> };
>
> - ufs_mem_hc: ufs@1d84000 {
> + ufs_mem_hc: ufshc@1d84000 {
> compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
> "jedec,ufs-2.0";
> reg = <0 0x01d84000 0 0x3000>;
> --
> 2.26.1
>
^ permalink raw reply
* Re: [PATCH 1/6] arm64: dts: qcom: sm8150: add apps_smmu node
From: Bjorn Andersson @ 2020-05-29 3:42 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <00b8f010-1ae1-45b2-8dd0-a1b582861a2e@marek.ca>
On Thu 28 May 20:34 PDT 2020, Jonathan Marek wrote:
> On 5/28/20 11:15 PM, Bjorn Andersson wrote:
> > On Thu 28 May 20:02 PDT 2020, Jonathan Marek wrote:
> >
> > >
> > >
> > > On 5/28/20 10:52 PM, Bjorn Andersson wrote:
> > > > On Sat 23 May 19:38 PDT 2020, Jonathan Marek wrote:
> > > >
> > > > > Add the apps_smmu node for sm8150. Note that adding the iommus field for
> > > > > UFS is required because initializing the iommu removes the bypass mapping
> > > > > that created by the bootloader.
> > > > >
> > > >
> > > > Unrelated to the patch itself; how do you disable the splash screen on
> > > > 8150? "fastboot oem select-display-panel none" doesn't seem to work for
> > > > me on the MTP - and hence this would prevent my device from booting.
> > > >
> > > > Thanks,
> > > > Bjorn
> > > >
> > >
> > > I don't have a MTP, but on HDK855, "fastboot oem select-display-panel none"
> > > combined with setting the physical switch to HDMI mode (which switches off
> > > the 1440x2560 panel) gets it to not setup the display at all (just the
> > > fastboot command isn't enough).
> > >
> >
> > Okay, I don't think we have anything equivalent on the MTP, but good to
> > know.
> >
> > > With HDK865 though that doesn't work and I have a hack to work around it
> > > (writing 0 to INTF_TIMING_ENGINE_EN early on in boot will stop video mode
> > > scanout and it won't crash).
> > >
> >
> > Then we need to sort this out in the arm-smmu driver before we can
> > enable the apps_smmu node on 8250. I did receive some guidance from Will
> > on the subject and have started looking into this.
> >
>
> That's annoying because a lot depends on apps_mmu. GPU is an exception with
> its own MMU but pretty much everything else uses apps_smmu (does it make
> sense to add USB nodes if it won't work without apps_smmu?) Is this
> something that will get resolved soon?
>
We have a number of boards where this is becoming a critical issue, so
we better find an acceptable solution to this very soon.
Regards,
Bjorn
> FWIW, I have another sm8250 board which does not need the workaround (its
> bootloader does not set up the display). AFAIK modifying the bootloader to
> not set up any display is a trivial modification (assuming that's an
> option).
>
> > Thanks,
> > Bjorn
> >
> > > > > Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> > > > > ---
> > > > > arch/arm64/boot/dts/qcom/sm8150.dtsi | 91 ++++++++++++++++++++++++++++
> > > > > 1 file changed, 91 insertions(+)
> > > > >
> > > > > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > > > > index a36512d1f6a1..acb839427b12 100644
> > > > > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > > > > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > > > > @@ -442,6 +442,8 @@ ufs_mem_hc: ufshc@1d84000 {
> > > > > resets = <&gcc GCC_UFS_PHY_BCR>;
> > > > > reset-names = "rst";
> > > > > + iommus = <&apps_smmu 0x300 0>;
> > > > > +
> > > > > clock-names =
> > > > > "core_clk",
> > > > > "bus_aggr_clk",
> > > > > @@ -706,6 +708,7 @@ usb_1_dwc3: dwc3@a600000 {
> > > > > compatible = "snps,dwc3";
> > > > > reg = <0 0x0a600000 0 0xcd00>;
> > > > > interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> > > > > + iommus = <&apps_smmu 0x140 0>;
> > > > > snps,dis_u2_susphy_quirk;
> > > > > snps,dis_enblslpm_quirk;
> > > > > phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
> > > > > @@ -742,6 +745,94 @@ spmi_bus: spmi@c440000 {
> > > > > cell-index = <0>;
> > > > > };
> > > > > + apps_smmu: iommu@15000000 {
> > > > > + compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
> > > > > + reg = <0 0x15000000 0 0x100000>;
> > > > > + #iommu-cells = <2>;
> > > > > + #global-interrupts = <1>;
> > > > > + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
> > > > > + };
> > > > > +
> > > > > remoteproc_adsp: remoteproc@17300000 {
> > > > > compatible = "qcom,sm8150-adsp-pas";
> > > > > reg = <0x0 0x17300000 0x0 0x4040>;
> > > > > --
> > > > > 2.26.1
> > > > >
^ permalink raw reply
* [PATCH 0/3] MIPS: Loongson64: Initial LS7A PCH support
From: Jiaxun Yang @ 2020-05-29 3:43 UTC (permalink / raw)
To: maz
Cc: Jiaxun Yang, Thomas Bogendoerfer, Rob Herring, Huacai Chen,
linux-mips, devicetree, linux-kernel
With this series, LS7A and Loongson-3A4000 is finally supported
note that this series should depend on irqchip support[1], which
is likely to get merged soon.
Thanks.
[1]: https://lkml.org/lkml/2020/5/16/72
Jiaxun Yang (3):
dt-bindings: mips: Document two Loongson generic boards
MIPS: Loongson64: DeviceTree for LS7A PCH
MIPS: Loongson64:Load LS7A dtbs
.../bindings/mips/loongson/devices.yaml | 8 +
arch/mips/boot/dts/loongson/Makefile | 5 +-
.../dts/loongson/loongson3-r4-package.dtsi | 74 +++++++
.../dts/loongson/loongson3_4core_ls7a.dts | 25 +++
.../boot/dts/loongson/loongson3_r4_ls7a.dts | 10 +
arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 185 ++++++++++++++++++
.../asm/mach-loongson64/builtin_dtbs.h | 2 +
arch/mips/loongson64/env.c | 56 +++---
8 files changed, 342 insertions(+), 23 deletions(-)
create mode 100644 arch/mips/boot/dts/loongson/loongson3-r4-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_ls7a.dts
create mode 100644 arch/mips/boot/dts/loongson/loongson3_r4_ls7a.dts
create mode 100644 arch/mips/boot/dts/loongson/ls7a-pch.dtsi
--
2.27.0.rc0
^ permalink raw reply
* [PATCH 1/3] dt-bindings: mips: Document two Loongson generic boards
From: Jiaxun Yang @ 2020-05-29 3:43 UTC (permalink / raw)
To: maz
Cc: Jiaxun Yang, Thomas Bogendoerfer, Rob Herring, Huacai Chen,
linux-mips, devicetree, linux-kernel
In-Reply-To: <20200529034338.1137776-1-jiaxun.yang@flygoat.com>
Document loongson3-8core-ls7a and loongson3-r4-ls7a, with
two boards LS7A PCH.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
.../devicetree/bindings/mips/loongson/devices.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
index 74ed4e397a78..6164b0fcb493 100644
--- a/Documentation/devicetree/bindings/mips/loongson/devices.yaml
+++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
@@ -24,4 +24,12 @@ properties:
- description: Generic Loongson3 Octa Core + RS780E
items:
- const: loongson,loongson3-8core-rs780e
+
+ - description: Generic Loongson3 Quad Core + LS7A
+ items:
+ - const: loongson,loongson3-8core-ls7a
+
+ - description: Generic Loongson3 Release 4 + LS7A
+ items:
+ - const: loongson,loongson3-r4-ls7a
...
--
2.27.0.rc0
^ permalink raw reply related
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