* [PATCH v5 15/16] spi: dw: Use regset32 DebugFS method to create regdump file
From: Serge Semin @ 2020-05-29 3:59 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Serge Semin, Andy Shevchenko, Georgy Vlasov,
Ramil Zaripov, Alexey Malahov, Thomas Bogendoerfer, Arnd Bergmann,
Feng Tang, Rob Herring, linux-mips, devicetree, linux-spi,
linux-kernel
In-Reply-To: <20200529035915.20790-1-Sergey.Semin@baikalelectronics.ru>
DebugFS kernel interface provides a dedicated method to create the
registers dump file. Use it instead of creating a generic DebugFS
file with manually written read callback function.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Feng Tang <feng.tang@intel.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
Changelog v3:
- Add commas in the debugfs_reg32 structure initializer and after the last
item of the array dw_spi_dbgfs_regs.
---
drivers/spi/spi-dw-core.c | 86 ++++++++++++---------------------------
drivers/spi/spi-dw.h | 2 +
2 files changed, 28 insertions(+), 60 deletions(-)
diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
index 4d1849699a12..323c66c5db50 100644
--- a/drivers/spi/spi-dw-core.c
+++ b/drivers/spi/spi-dw-core.c
@@ -29,66 +29,29 @@ struct chip_data {
};
#ifdef CONFIG_DEBUG_FS
-#define SPI_REGS_BUFSIZE 1024
-static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
- size_t count, loff_t *ppos)
-{
- struct dw_spi *dws = file->private_data;
- char *buf;
- u32 len = 0;
- ssize_t ret;
-
- buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
- if (!buf)
- return 0;
-
- len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
- "%s registers:\n", dev_name(&dws->master->dev));
- len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
- "=================================\n");
- len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
- "CTRLR0: \t0x%08x\n", dw_readl(dws, DW_SPI_CTRLR0));
- len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
- "CTRLR1: \t0x%08x\n", dw_readl(dws, DW_SPI_CTRLR1));
- len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
- "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
- len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
- "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
- len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
- "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
- len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
- "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFTLR));
- len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
- "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFTLR));
- len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
- "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
- len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
- "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
- len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
- "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
- len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
- "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
- len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
- "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
- len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
- "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
- len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
- "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
- len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
- "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
- len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
- "=================================\n");
-
- ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
- kfree(buf);
- return ret;
+
+#define DW_SPI_DBGFS_REG(_name, _off) \
+{ \
+ .name = _name, \
+ .offset = _off, \
}
-static const struct file_operations dw_spi_regs_ops = {
- .owner = THIS_MODULE,
- .open = simple_open,
- .read = dw_spi_show_regs,
- .llseek = default_llseek,
+static const struct debugfs_reg32 dw_spi_dbgfs_regs[] = {
+ DW_SPI_DBGFS_REG("CTRLR0", DW_SPI_CTRLR0),
+ DW_SPI_DBGFS_REG("CTRLR1", DW_SPI_CTRLR1),
+ DW_SPI_DBGFS_REG("SSIENR", DW_SPI_SSIENR),
+ DW_SPI_DBGFS_REG("SER", DW_SPI_SER),
+ DW_SPI_DBGFS_REG("BAUDR", DW_SPI_BAUDR),
+ DW_SPI_DBGFS_REG("TXFTLR", DW_SPI_TXFTLR),
+ DW_SPI_DBGFS_REG("RXFTLR", DW_SPI_RXFTLR),
+ DW_SPI_DBGFS_REG("TXFLR", DW_SPI_TXFLR),
+ DW_SPI_DBGFS_REG("RXFLR", DW_SPI_RXFLR),
+ DW_SPI_DBGFS_REG("SR", DW_SPI_SR),
+ DW_SPI_DBGFS_REG("IMR", DW_SPI_IMR),
+ DW_SPI_DBGFS_REG("ISR", DW_SPI_ISR),
+ DW_SPI_DBGFS_REG("DMACR", DW_SPI_DMACR),
+ DW_SPI_DBGFS_REG("DMATDLR", DW_SPI_DMATDLR),
+ DW_SPI_DBGFS_REG("DMARDLR", DW_SPI_DMARDLR),
};
static int dw_spi_debugfs_init(struct dw_spi *dws)
@@ -100,8 +63,11 @@ static int dw_spi_debugfs_init(struct dw_spi *dws)
if (!dws->debugfs)
return -ENOMEM;
- debugfs_create_file("registers", S_IFREG | S_IRUGO,
- dws->debugfs, (void *)dws, &dw_spi_regs_ops);
+ dws->regset.regs = dw_spi_dbgfs_regs;
+ dws->regset.nregs = ARRAY_SIZE(dw_spi_dbgfs_regs);
+ dws->regset.base = dws->regs;
+ debugfs_create_regset32("registers", 0400, dws->debugfs, &dws->regset);
+
return 0;
}
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 0b2cd7994513..151ba316619e 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -3,6 +3,7 @@
#define DW_SPI_HEADER_H
#include <linux/completion.h>
+#include <linux/debugfs.h>
#include <linux/irqreturn.h>
#include <linux/io.h>
#include <linux/scatterlist.h>
@@ -152,6 +153,7 @@ struct dw_spi {
#ifdef CONFIG_DEBUG_FS
struct dentry *debugfs;
+ struct debugfs_regset32 regset;
#endif
};
--
2.26.2
^ permalink raw reply related
* [PATCH v5 11/16] spi: dw: Remove DW DMA code dependency from DW_DMAC_PCI
From: Serge Semin @ 2020-05-29 3:59 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Serge Semin, Georgy Vlasov, Ramil Zaripov,
Andy Shevchenko, Alexey Malahov, Thomas Bogendoerfer,
Arnd Bergmann, Feng Tang, Rob Herring, linux-mips, devicetree,
linux-spi, linux-kernel
In-Reply-To: <20200529035915.20790-1-Sergey.Semin@baikalelectronics.ru>
Since there is a generic method available to initialize the DW SPI DMA
interface on any DT and ACPI-based platforms, which in general can be
designed with not only DW DMAC but with any DMA engine on board, we can
freely remove the CONFIG_DW_DMAC_PCI config from dependency list of
CONFIG_SPI_DW_DMA. Especially seeing that we don't use anything DW DMAC
specific in the new driver.
Co-developed-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Signed-off-by: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Co-developed-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Feng Tang <feng.tang@intel.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
drivers/spi/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 03b061975f70..6a84f3dad35c 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -228,7 +228,7 @@ config SPI_DESIGNWARE
config SPI_DW_DMA
bool "DMA support for DW SPI controller"
- depends on SPI_DESIGNWARE && DW_DMAC_PCI
+ depends on SPI_DESIGNWARE
config SPI_DW_PCI
tristate "PCI interface driver for DW SPI core"
--
2.26.2
^ permalink raw reply related
* [PATCH v5 07/16] spi: dw: Use DMA max burst to set the request thresholds
From: Serge Semin @ 2020-05-29 3:59 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Serge Semin, Andy Shevchenko, Alexey Malahov,
Thomas Bogendoerfer, Arnd Bergmann, Feng Tang, Rob Herring,
linux-mips, devicetree, linux-spi, linux-kernel
In-Reply-To: <20200529035915.20790-1-Sergey.Semin@baikalelectronics.ru>
Each channel of DMA controller may have a limited length of burst
transaction (number of IO operations performed at ones in a single
DMA client request). This parameter can be used to setup the most
optimal DMA Tx/Rx data level values. In order to avoid the Tx buffer
overrun we can set the DMA Tx level to be of FIFO depth minus the
maximum burst transactions length. To prevent the Rx buffer underflow
the DMA Rx level should be set to the maximum burst transactions length.
This commit setups the DMA channels and the DW SPI DMA Tx/Rx levels
in accordance with these rules.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Feng Tang <feng.tang@intel.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
Changelog v3:
- Use min() method to calculate the optimal burst values.
---
drivers/spi/spi-dw-mid.c | 37 +++++++++++++++++++++++++++++++++----
drivers/spi/spi-dw.h | 2 ++
2 files changed, 35 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index 93463bdba0f8..ff79b4239d68 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -36,6 +36,31 @@ static bool mid_spi_dma_chan_filter(struct dma_chan *chan, void *param)
return true;
}
+static void mid_spi_maxburst_init(struct dw_spi *dws)
+{
+ struct dma_slave_caps caps;
+ u32 max_burst, def_burst;
+ int ret;
+
+ def_burst = dws->fifo_len / 2;
+
+ ret = dma_get_slave_caps(dws->rxchan, &caps);
+ if (!ret && caps.max_burst)
+ max_burst = caps.max_burst;
+ else
+ max_burst = RX_BURST_LEVEL;
+
+ dws->rxburst = min(max_burst, def_burst);
+
+ ret = dma_get_slave_caps(dws->txchan, &caps);
+ if (!ret && caps.max_burst)
+ max_burst = caps.max_burst;
+ else
+ max_burst = TX_BURST_LEVEL;
+
+ dws->txburst = min(max_burst, def_burst);
+}
+
static int mid_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws)
{
struct dw_dma_slave slave = {
@@ -73,6 +98,8 @@ static int mid_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws)
init_completion(&dws->dma_completion);
+ mid_spi_maxburst_init(dws);
+
return 0;
free_rxchan:
@@ -100,6 +127,8 @@ static int mid_spi_dma_init_generic(struct device *dev, struct dw_spi *dws)
init_completion(&dws->dma_completion);
+ mid_spi_maxburst_init(dws);
+
return 0;
}
@@ -229,7 +258,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_tx(struct dw_spi *dws,
memset(&txconf, 0, sizeof(txconf));
txconf.direction = DMA_MEM_TO_DEV;
txconf.dst_addr = dws->dma_addr;
- txconf.dst_maxburst = TX_BURST_LEVEL;
+ txconf.dst_maxburst = dws->txburst;
txconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
txconf.dst_addr_width = convert_dma_width(dws->n_bytes);
txconf.device_fc = false;
@@ -321,7 +350,7 @@ static struct dma_async_tx_descriptor *dw_spi_dma_prepare_rx(struct dw_spi *dws,
memset(&rxconf, 0, sizeof(rxconf));
rxconf.direction = DMA_DEV_TO_MEM;
rxconf.src_addr = dws->dma_addr;
- rxconf.src_maxburst = RX_BURST_LEVEL;
+ rxconf.src_maxburst = dws->rxburst;
rxconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
rxconf.src_addr_width = convert_dma_width(dws->n_bytes);
rxconf.device_fc = false;
@@ -346,8 +375,8 @@ static int mid_spi_dma_setup(struct dw_spi *dws, struct spi_transfer *xfer)
{
u16 imr = 0, dma_ctrl = 0;
- dw_writel(dws, DW_SPI_DMARDLR, RX_BURST_LEVEL - 1);
- dw_writel(dws, DW_SPI_DMATDLR, TX_BURST_LEVEL);
+ dw_writel(dws, DW_SPI_DMARDLR, dws->rxburst - 1);
+ dw_writel(dws, DW_SPI_DMATDLR, dws->fifo_len - dws->txburst);
if (xfer->tx_buf) {
dma_ctrl |= SPI_DMA_TDMAE;
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 9585d0c83a6d..9247670fcdfb 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -142,7 +142,9 @@ struct dw_spi {
/* DMA info */
struct dma_chan *txchan;
+ u32 txburst;
struct dma_chan *rxchan;
+ u32 rxburst;
unsigned long dma_chan_busy;
dma_addr_t dma_addr; /* phy address of the Data register */
const struct dw_spi_dma_ops *dma_ops;
--
2.26.2
^ permalink raw reply related
* [PATCH v5 09/16] spi: dw: Add core suffix to the DW APB SSI core source file
From: Serge Semin @ 2020-05-29 3:59 UTC (permalink / raw)
To: Mark Brown
Cc: Serge Semin, Serge Semin, Andy Shevchenko, Georgy Vlasov,
Ramil Zaripov, Alexey Malahov, Thomas Bogendoerfer, Feng Tang,
Rob Herring, Arnd Bergmann, linux-mips, devicetree, linux-spi,
linux-kernel
In-Reply-To: <20200529035915.20790-1-Sergey.Semin@baikalelectronics.ru>
Generic DMA support is going to be part of the DW APB SSI core object.
In order to preserve the kernel loadable module name as spi-dw.ko, let's
add the "-core" suffix to the object with generic DW APB SSI code and
build it into the target spi-dw.ko driver.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Feng Tang <feng.tang@intel.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
---
Changelog v3:
- This is a new patch added as a result of the discussion with Andy
Shevchenko.
---
drivers/spi/Makefile | 1 +
drivers/spi/{spi-dw.c => spi-dw-core.c} | 0
2 files changed, 1 insertion(+)
rename drivers/spi/{spi-dw.c => spi-dw-core.c} (100%)
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 28f601327f8c..70ebc2a62e5f 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -36,6 +36,7 @@ obj-$(CONFIG_SPI_COLDFIRE_QSPI) += spi-coldfire-qspi.o
obj-$(CONFIG_SPI_DAVINCI) += spi-davinci.o
obj-$(CONFIG_SPI_DLN2) += spi-dln2.o
obj-$(CONFIG_SPI_DESIGNWARE) += spi-dw.o
+spi-dw-y := spi-dw-core.o
obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o
obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o
spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw-core.c
similarity index 100%
rename from drivers/spi/spi-dw.c
rename to drivers/spi/spi-dw-core.c
--
2.26.2
^ permalink raw reply related
* Re: [PATCH v4 2/6] dt-bindings: interrupt-controller: Add Loongson HTVEC
From: Jiaxun Yang @ 2020-05-29 3:51 UTC (permalink / raw)
To: Marc Zyngier
Cc: Rob Herring, Thomas Gleixner, Jason Cooper, Huacai Chen,
linux-kernel, devicetree, linux-mips
In-Reply-To: <98643a72747e4896b78cd4d583d2d3f9@kernel.org>
On Tue, 26 May 2020 10:53:15 +0100
Marc Zyngier <maz@kernel.org> wrote:
> On 2020-05-26 10:26, Jiaxun Yang wrote:
> > On Mon, 25 May 2020 11:12:26 +0100
> > Marc Zyngier <maz@kernel.org> wrote:
> >
> >> On Sat, 16 May 2020 09:29:02 +0100,
> >> Jiaxun Yang <jiaxun.yang@flygoat.com> wrote:
> >> >
> >> > Add binding for Loongson-3 HyperTransport Interrupt Vector
> >> > Controller.
> >> >
> >> > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> >> > --
> >> > v4: Drop ref, '|', add additionalProperties, fix example
> >>
> >> Rob, do you have any input on this?
> >
> > Oops, looks like I was in-reply into wrong patch topic for this
> > patch, should I resend this series into correct thread?
>
> No, this series is fine as it is. TBH, your practice of sending
> a series in reply to the previous version is not that useful
> (I personally find it very annoying).
>
> It would also be a big improvement if you sent a cover letter
> with your patches (using --cover-letter when generating the patches).
>
> I'll wait for Rob to comment on this patch as well as patch #4.
Hi Marc,
I have send out patches for DeviceTree[1] utilizing these drivers.
If this series looks fine for you could you please Ack this series
so it can all go through MIPS tree together with DeviceTree changes?
Thanks.
[1]: https://patchwork.kernel.org/project/linux-mips/list/?series=295413
>
> Thanks,
>
> M.
^ permalink raw reply
* [PATCH 3/3] MIPS: Loongson64:Load LS7A dtbs
From: Jiaxun Yang @ 2020-05-29 3:43 UTC (permalink / raw)
To: maz
Cc: Jiaxun Yang, Thomas Bogendoerfer, Rob Herring, Huacai Chen,
linux-mips, devicetree, linux-kernel
In-Reply-To: <20200529034338.1137776-1-jiaxun.yang@flygoat.com>
Load correct devicetree according to PRID and PCH type.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/loongson64/env.c | 56 +++++++++++++++++++++++---------------
1 file changed, 34 insertions(+), 22 deletions(-)
diff --git a/arch/mips/loongson64/env.c b/arch/mips/loongson64/env.c
index d11bc346bbca..9b56f4a80b62 100644
--- a/arch/mips/loongson64/env.c
+++ b/arch/mips/loongson64/env.c
@@ -126,28 +126,6 @@ void __init prom_init_env(void)
loongson_sysconf.cores_per_node - 1) /
loongson_sysconf.cores_per_node;
- if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) {
- switch (read_c0_prid() & PRID_REV_MASK) {
- case PRID_REV_LOONGSON3A_R1:
- case PRID_REV_LOONGSON3A_R2_0:
- case PRID_REV_LOONGSON3A_R2_1:
- case PRID_REV_LOONGSON3A_R3_0:
- case PRID_REV_LOONGSON3A_R3_1:
- loongson_fdt_blob = __dtb_loongson3_4core_rs780e_begin;
- break;
- case PRID_REV_LOONGSON3B_R1:
- case PRID_REV_LOONGSON3B_R2:
- loongson_fdt_blob = __dtb_loongson3_8core_rs780e_begin;
- break;
- default:
- break;
- }
- }
-
-
- if (!loongson_fdt_blob)
- pr_err("Failed to determine built-in Loongson64 dtb\n");
-
loongson_sysconf.pci_mem_start_addr = eirq_source->pci_mem_start_addr;
loongson_sysconf.pci_mem_end_addr = eirq_source->pci_mem_end_addr;
loongson_sysconf.pci_io_base = eirq_source->pci_io_start_addr;
@@ -198,4 +176,38 @@ void __init prom_init_env(void)
loongson_sysconf.bridgetype = RS780E;
loongson_sysconf.early_config = rs780e_early_config;
}
+
+ if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C) {
+ switch (read_c0_prid() & PRID_REV_MASK) {
+ case PRID_REV_LOONGSON3A_R1:
+ case PRID_REV_LOONGSON3A_R2_0:
+ case PRID_REV_LOONGSON3A_R2_1:
+ case PRID_REV_LOONGSON3A_R3_0:
+ case PRID_REV_LOONGSON3A_R3_1:
+ switch (loongson_sysconf.bridgetype) {
+ case RS780E:
+ loongson_fdt_blob = __dtb_loongson3_4core_rs780e_begin;
+ break;
+ case LS7A:
+ loongson_fdt_blob = __dtb_loongson3_4core_ls7a_begin;
+ break;
+ default:
+ break;
+ }
+ break;
+ case PRID_REV_LOONGSON3B_R1:
+ case PRID_REV_LOONGSON3B_R2:
+ if (loongson_sysconf.bridgetype == RS780E)
+ loongson_fdt_blob = __dtb_loongson3_8core_rs780e_begin;
+ break;
+ default:
+ break;
+ }
+ } else if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64G) {
+ if (loongson_sysconf.bridgetype == LS7A)
+ loongson_fdt_blob = __dtb_loongson3_r4_ls7a_begin;
+ }
+
+ if (!loongson_fdt_blob)
+ pr_err("Failed to determine built-in Loongson64 dtb\n");
}
--
2.27.0.rc0
^ permalink raw reply related
* [PATCH 2/3] MIPS: Loongson64: DeviceTree for LS7A PCH
From: Jiaxun Yang @ 2020-05-29 3:43 UTC (permalink / raw)
To: maz
Cc: Jiaxun Yang, Thomas Bogendoerfer, Rob Herring, Huacai Chen,
linux-mips, devicetree, linux-kernel
In-Reply-To: <20200529034338.1137776-1-jiaxun.yang@flygoat.com>
DeviceTree for Loongson-3 Quad core + LS7A boards
and Loongson-3 Release 4 + LS7A boards.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/boot/dts/loongson/Makefile | 5 +-
.../dts/loongson/loongson3-r4-package.dtsi | 74 +++++++
.../dts/loongson/loongson3_4core_ls7a.dts | 25 +++
.../boot/dts/loongson/loongson3_r4_ls7a.dts | 10 +
arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 185 ++++++++++++++++++
.../asm/mach-loongson64/builtin_dtbs.h | 2 +
6 files changed, 300 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/boot/dts/loongson/loongson3-r4-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_ls7a.dts
create mode 100644 arch/mips/boot/dts/loongson/loongson3_r4_ls7a.dts
create mode 100644 arch/mips/boot/dts/loongson/ls7a-pch.dtsi
diff --git a/arch/mips/boot/dts/loongson/Makefile b/arch/mips/boot/dts/loongson/Makefile
index 56d379471262..8f94fcb5d32e 100644
--- a/arch/mips/boot/dts/loongson/Makefile
+++ b/arch/mips/boot/dts/loongson/Makefile
@@ -1,4 +1,7 @@
# SPDX_License_Identifier: GPL_2.0
-dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_4core_rs780e.dtb loongson3_8core_rs780e.dtb
+dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_4core_rs780e.dtb
+dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_8core_rs780e.dtb
+dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_4core_ls7a.dtb
+dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_r4_ls7a.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/loongson/loongson3-r4-package.dtsi b/arch/mips/boot/dts/loongson/loongson3-r4-package.dtsi
new file mode 100644
index 000000000000..e3d33f31e2b6
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson3-r4-package.dtsi
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpuintc: interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ package0: bus@1fe00000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
+ 0 0x3ff00000 0 0x3ff00000 0x100000
+ 0xefd 0xfb000000 0xefd 0xfb000000 0x10000000>;
+
+ liointc: interrupt-controller@3ff01400 {
+ compatible = "loongson,liointc-1.0";
+ reg = <0 0x3ff01400 0x64>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>, <3>;
+ interrupt-names = "int0", "int1";
+
+ loongson,parent_int_map = <0xf0ffffff>, /* int0 */
+ <0x0f000000>, /* int1 */
+ <0x00000000>, /* int2 */
+ <0x00000000>; /* int3 */
+
+ };
+
+ cpu_uart0: serial@1fe001e0 {
+ compatible = "ns16550a";
+ reg = <0 0x1fe00100 0x10>;
+ clock-frequency = <100000000>;
+ interrupt-parent = <&liointc>;
+ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
+ no-loopback-test;
+ };
+
+ cpu_uart1: serial@1fe001e8 {
+ status = "disabled";
+ compatible = "ns16550a";
+ reg = <0 0x1fe00110 0x10>;
+ clock-frequency = <100000000>;
+ interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&liointc>;
+ no-loopback-test;
+ };
+
+ htvec: interrupt-controller@efdfb000080 {
+ compatible = "loongson,htvec-1.0";
+ reg = <0xefd 0xfb000080 0x40>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&liointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/loongson3_4core_ls7a.dts b/arch/mips/boot/dts/loongson/loongson3_4core_ls7a.dts
new file mode 100644
index 000000000000..4eadcf99423d
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson3_4core_ls7a.dts
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "loongson3-package.dtsi"
+#include "ls7a-pch.dtsi"
+
+/ {
+ compatible = "loongson,loongson3-4core-ls7a";
+};
+
+&package0 {
+ htvec: interrupt-controller@efdfb000080 {
+ compatible = "loongson,htvec-1.0";
+ reg = <0xefd 0xfb000080 0x40>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&liointc>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
+ <25 IRQ_TYPE_LEVEL_HIGH>,
+ <26 IRQ_TYPE_LEVEL_HIGH>,
+ <27 IRQ_TYPE_LEVEL_HIGH>;
+ };
+};
diff --git a/arch/mips/boot/dts/loongson/loongson3_r4_ls7a.dts b/arch/mips/boot/dts/loongson/loongson3_r4_ls7a.dts
new file mode 100644
index 000000000000..d171f3a1a0ef
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/loongson3_r4_ls7a.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+
+#include "loongson3-r4-package.dtsi"
+#include "ls7a-pch.dtsi"
+
+/ {
+ compatible = "loongson,loongson3-r4-ls7a";
+};
diff --git a/arch/mips/boot/dts/loongson/ls7a-pch.dtsi b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
new file mode 100644
index 000000000000..9c124601fe4c
--- /dev/null
+++ b/arch/mips/boot/dts/loongson/ls7a-pch.dtsi
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ bus@10000000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0x00000000 0 0x00000000 0 0x00040000 /* PIO */
+ 0 0x10000000 0 0x10000000 0 0xf000000 /* CONF & APB */
+ 0 0x20000000 0 0x20000000 0 0x10000000
+ 0 0x40000000 0 0x40000000 0 0x40000000 /* PCI MEM */
+ 0xe00 0x00000000 0xe00 0x00000000 0x100 0x0000000>;
+
+ pic: interrupt-controller@10000000 {
+ compatible = "loongson,pch-pic-1.0";
+ reg = <0 0x10000000 0 0x400>;
+ interrupt-controller;
+ interrupt-parent = <&htvec>;
+ loongson,pic-base-vec = <64>;
+ #interrupt-cells = <2>;
+ };
+
+ pci@1a000000 {
+ compatible = "loongson,ls7a-pci";
+ device_type = "pci";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <2>;
+ msi-parent = <&msi>;
+
+ reg = <0 0x1a000000 0 0x02000000>,
+ <0xefe 0x00000000 0 0x20000000>;
+
+ ranges = <0x01000000 0x0 0x00020000 0x0 0x00020000 0x0 0x00020000>,
+ <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
+
+ ohci@4,0 {
+ compatible = "pci0014,7a24.0",
+ "pci0014,7a24",
+ "pciclass0c0310",
+ "pciclass0c03";
+
+ reg = <0x2000 0x0 0x0 0x0 0x0>;
+ interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ };
+
+ ehci@4,1 {
+ compatible = "pci0014,7a14.0",
+ "pci0014,7a14",
+ "pciclass0c0320",
+ "pciclass0c03";
+
+ reg = <0x2100 0x0 0x0 0x0 0x0>;
+ interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ };
+
+ ohci@5,0 {
+ compatible = "pci0014,7a24.0",
+ "pci0014,7a24",
+ "pciclass0c0310",
+ "pciclass0c03";
+
+ reg = <0x2800 0x0 0x0 0x0 0x0>;
+ interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ };
+
+ ehci@5,1 {
+ compatible = "pci0014,7a14.0",
+ "pci0014,7a14",
+ "pciclass0c0320",
+ "pciclass0c03";
+
+ reg = <0x2900 0x0 0x0 0x0 0x0>;
+ interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ };
+
+ sata@8,0 {
+ compatible = "pci0014,7a08.0",
+ "pci0014,7a08",
+ "pciclass010601",
+ "pciclass0106";
+
+ reg = <0x4000 0x0 0x0 0x0 0x0>;
+ interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ };
+
+ sata@8,1 {
+ compatible = "pci0014,7a08.0",
+ "pci0014,7a08",
+ "pciclass010601",
+ "pciclass0106";
+
+ reg = <0x4100 0x0 0x0 0x0 0x0>;
+ interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ };
+
+ sata@8,2 {
+ compatible = "pci0014,7a08.0",
+ "pci0014,7a08",
+ "pciclass010601",
+ "pciclass0106";
+
+ reg = <0x4200 0x0 0x0 0x0 0x0>;
+ interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+ };
+
+ pci_bridge@9,0 {
+ compatible = "pci0014,7a19.0",
+ "pci0014,7a19",
+ "pciclass060400",
+ "pciclass0604";
+
+ reg = <0x4800 0x0 0x0 0x0 0x0>;
+ interrupts = <32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &pic 32 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pci_bridge@b,0 {
+ compatible = "pci0014,7a09.0",
+ "pci0014,7a09",
+ "pciclass060400",
+ "pciclass0604";
+
+ reg = <0x5800 0x0 0x0 0x0 0x0>;
+ interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &pic 34 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pci_bridge@d,0 {
+ compatible = "pci0014,7a19.0",
+ "pci0014,7a19",
+ "pciclass060400",
+ "pciclass0604";
+
+ reg = <0x6800 0x0 0x0 0x0 0x0>;
+ interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &pic 36 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ pci_bridge@11,0 {
+ compatible = "pci0014,7a29.0",
+ "pci0014,7a29",
+ "pciclass060400",
+ "pciclass0604";
+
+ reg = <0x8800 0x0 0x0 0x0 0x0>;
+ interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&pic>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &pic 42 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
+
+ msi: msi-controller@2ff00000 {
+ compatible = "loongson,pch-msi-1.0";
+ reg = <0 0x2ff00000 0 0x8>;
+ interrupt-controller;
+ msi-controller;
+ loongson,msi-base-vec = <0>;
+ loongson,msi-num-vecs = <64>;
+ interrupt-parent = <&htvec>;
+ };
+ };
+};
diff --git a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
index 853c6d80887b..cf563fafc0ea 100644
--- a/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
+++ b/arch/mips/include/asm/mach-loongson64/builtin_dtbs.h
@@ -10,4 +10,6 @@
extern u32 __dtb_loongson3_4core_rs780e_begin[];
extern u32 __dtb_loongson3_8core_rs780e_begin[];
+extern u32 __dtb_loongson3_4core_ls7a_begin[];
+extern u32 __dtb_loongson3_r4_ls7a_begin[];
#endif
--
2.27.0.rc0
^ permalink raw reply related
* [PATCH 1/3] dt-bindings: mips: Document two Loongson generic boards
From: Jiaxun Yang @ 2020-05-29 3:43 UTC (permalink / raw)
To: maz
Cc: Jiaxun Yang, Thomas Bogendoerfer, Rob Herring, Huacai Chen,
linux-mips, devicetree, linux-kernel
In-Reply-To: <20200529034338.1137776-1-jiaxun.yang@flygoat.com>
Document loongson3-8core-ls7a and loongson3-r4-ls7a, with
two boards LS7A PCH.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
.../devicetree/bindings/mips/loongson/devices.yaml | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/Documentation/devicetree/bindings/mips/loongson/devices.yaml b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
index 74ed4e397a78..6164b0fcb493 100644
--- a/Documentation/devicetree/bindings/mips/loongson/devices.yaml
+++ b/Documentation/devicetree/bindings/mips/loongson/devices.yaml
@@ -24,4 +24,12 @@ properties:
- description: Generic Loongson3 Octa Core + RS780E
items:
- const: loongson,loongson3-8core-rs780e
+
+ - description: Generic Loongson3 Quad Core + LS7A
+ items:
+ - const: loongson,loongson3-8core-ls7a
+
+ - description: Generic Loongson3 Release 4 + LS7A
+ items:
+ - const: loongson,loongson3-r4-ls7a
...
--
2.27.0.rc0
^ permalink raw reply related
* [PATCH 0/3] MIPS: Loongson64: Initial LS7A PCH support
From: Jiaxun Yang @ 2020-05-29 3:43 UTC (permalink / raw)
To: maz
Cc: Jiaxun Yang, Thomas Bogendoerfer, Rob Herring, Huacai Chen,
linux-mips, devicetree, linux-kernel
With this series, LS7A and Loongson-3A4000 is finally supported
note that this series should depend on irqchip support[1], which
is likely to get merged soon.
Thanks.
[1]: https://lkml.org/lkml/2020/5/16/72
Jiaxun Yang (3):
dt-bindings: mips: Document two Loongson generic boards
MIPS: Loongson64: DeviceTree for LS7A PCH
MIPS: Loongson64:Load LS7A dtbs
.../bindings/mips/loongson/devices.yaml | 8 +
arch/mips/boot/dts/loongson/Makefile | 5 +-
.../dts/loongson/loongson3-r4-package.dtsi | 74 +++++++
.../dts/loongson/loongson3_4core_ls7a.dts | 25 +++
.../boot/dts/loongson/loongson3_r4_ls7a.dts | 10 +
arch/mips/boot/dts/loongson/ls7a-pch.dtsi | 185 ++++++++++++++++++
.../asm/mach-loongson64/builtin_dtbs.h | 2 +
arch/mips/loongson64/env.c | 56 +++---
8 files changed, 342 insertions(+), 23 deletions(-)
create mode 100644 arch/mips/boot/dts/loongson/loongson3-r4-package.dtsi
create mode 100644 arch/mips/boot/dts/loongson/loongson3_4core_ls7a.dts
create mode 100644 arch/mips/boot/dts/loongson/loongson3_r4_ls7a.dts
create mode 100644 arch/mips/boot/dts/loongson/ls7a-pch.dtsi
--
2.27.0.rc0
^ permalink raw reply
* Re: [PATCH 1/6] arm64: dts: qcom: sm8150: add apps_smmu node
From: Bjorn Andersson @ 2020-05-29 3:42 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <00b8f010-1ae1-45b2-8dd0-a1b582861a2e@marek.ca>
On Thu 28 May 20:34 PDT 2020, Jonathan Marek wrote:
> On 5/28/20 11:15 PM, Bjorn Andersson wrote:
> > On Thu 28 May 20:02 PDT 2020, Jonathan Marek wrote:
> >
> > >
> > >
> > > On 5/28/20 10:52 PM, Bjorn Andersson wrote:
> > > > On Sat 23 May 19:38 PDT 2020, Jonathan Marek wrote:
> > > >
> > > > > Add the apps_smmu node for sm8150. Note that adding the iommus field for
> > > > > UFS is required because initializing the iommu removes the bypass mapping
> > > > > that created by the bootloader.
> > > > >
> > > >
> > > > Unrelated to the patch itself; how do you disable the splash screen on
> > > > 8150? "fastboot oem select-display-panel none" doesn't seem to work for
> > > > me on the MTP - and hence this would prevent my device from booting.
> > > >
> > > > Thanks,
> > > > Bjorn
> > > >
> > >
> > > I don't have a MTP, but on HDK855, "fastboot oem select-display-panel none"
> > > combined with setting the physical switch to HDMI mode (which switches off
> > > the 1440x2560 panel) gets it to not setup the display at all (just the
> > > fastboot command isn't enough).
> > >
> >
> > Okay, I don't think we have anything equivalent on the MTP, but good to
> > know.
> >
> > > With HDK865 though that doesn't work and I have a hack to work around it
> > > (writing 0 to INTF_TIMING_ENGINE_EN early on in boot will stop video mode
> > > scanout and it won't crash).
> > >
> >
> > Then we need to sort this out in the arm-smmu driver before we can
> > enable the apps_smmu node on 8250. I did receive some guidance from Will
> > on the subject and have started looking into this.
> >
>
> That's annoying because a lot depends on apps_mmu. GPU is an exception with
> its own MMU but pretty much everything else uses apps_smmu (does it make
> sense to add USB nodes if it won't work without apps_smmu?) Is this
> something that will get resolved soon?
>
We have a number of boards where this is becoming a critical issue, so
we better find an acceptable solution to this very soon.
Regards,
Bjorn
> FWIW, I have another sm8250 board which does not need the workaround (its
> bootloader does not set up the display). AFAIK modifying the bootloader to
> not set up any display is a trivial modification (assuming that's an
> option).
>
> > Thanks,
> > Bjorn
> >
> > > > > Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> > > > > ---
> > > > > arch/arm64/boot/dts/qcom/sm8150.dtsi | 91 ++++++++++++++++++++++++++++
> > > > > 1 file changed, 91 insertions(+)
> > > > >
> > > > > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > > > > index a36512d1f6a1..acb839427b12 100644
> > > > > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > > > > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > > > > @@ -442,6 +442,8 @@ ufs_mem_hc: ufshc@1d84000 {
> > > > > resets = <&gcc GCC_UFS_PHY_BCR>;
> > > > > reset-names = "rst";
> > > > > + iommus = <&apps_smmu 0x300 0>;
> > > > > +
> > > > > clock-names =
> > > > > "core_clk",
> > > > > "bus_aggr_clk",
> > > > > @@ -706,6 +708,7 @@ usb_1_dwc3: dwc3@a600000 {
> > > > > compatible = "snps,dwc3";
> > > > > reg = <0 0x0a600000 0 0xcd00>;
> > > > > interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> > > > > + iommus = <&apps_smmu 0x140 0>;
> > > > > snps,dis_u2_susphy_quirk;
> > > > > snps,dis_enblslpm_quirk;
> > > > > phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
> > > > > @@ -742,6 +745,94 @@ spmi_bus: spmi@c440000 {
> > > > > cell-index = <0>;
> > > > > };
> > > > > + apps_smmu: iommu@15000000 {
> > > > > + compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
> > > > > + reg = <0 0x15000000 0 0x100000>;
> > > > > + #iommu-cells = <2>;
> > > > > + #global-interrupts = <1>;
> > > > > + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
> > > > > + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
> > > > > + };
> > > > > +
> > > > > remoteproc_adsp: remoteproc@17300000 {
> > > > > compatible = "qcom,sm8150-adsp-pas";
> > > > > reg = <0x0 0x17300000 0x0 0x4040>;
> > > > > --
> > > > > 2.26.1
> > > > >
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: sm8250: change ufs node name to ufshc
From: Bjorn Andersson @ 2020-05-29 3:40 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20200523175232.13721-1-jonathan@marek.ca>
On Sat 23 May 10:52 PDT 2020, Jonathan Marek wrote:
> The ufs-qcom driver checks that the name matches the androidboot.bootdevice
> parameter provided by the bootloader, which uses the name ufshc. Without
> this change UFS fails to probe.
>
Seems I only tested with UFS built as module, thanks for spotting this.
> I think this is broken behavior from the ufs-qcom driver, but using the
> name ufshc is consistent with dts for sdm845/sm8150/etc.
>
I agree. Patch applied...
Thanks,
Bjorn
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index e0344d3ba159..3bdce658c08a 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -309,7 +309,7 @@ uart2: serial@a90000 {
> };
> };
>
> - ufs_mem_hc: ufs@1d84000 {
> + ufs_mem_hc: ufshc@1d84000 {
> compatible = "qcom,sm8250-ufshc", "qcom,ufshc",
> "jedec,ufs-2.0";
> reg = <0 0x01d84000 0 0x3000>;
> --
> 2.26.1
>
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: sm8250: sort nodes by physical address
From: Bjorn Andersson @ 2020-05-29 3:37 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20200523132223.31108-1-jonathan@marek.ca>
On Sat 23 May 06:22 PDT 2020, Jonathan Marek wrote:
> Other dts have nodes sorted by physical address, be consistent with that.
>
This didn't apply cleanly, because we haven't yet migrated the hwlock to
the yet to be approved binding and I don't have a usb node.
I resolved it and applied the patch.
Thanks,
Bjorn
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 176 +++++++++++++--------------
> 1 file changed, 88 insertions(+), 88 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index a273b99bf1e6..bc8a14df60e5 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -379,6 +379,12 @@ ufs_mem_phy_lanes: lanes@1d87400 {
> };
> };
>
> + tcsr_mutex: hwlock@1f40000 {
> + compatible = "qcom,tcsr-mutex";
> + reg = <0x0 0x01f40000 0x0 0x40000>;
> + #hwlock-cells = <1>;
> + };
> +
> usb_1_hsphy: phy@88e3000 {
> compatible = "qcom,sm8250-usb-hs-phy",
> "qcom,usb-snps-hs-7nm-phy";
> @@ -559,15 +565,6 @@ usb_2_dwc3: dwc3@a800000 {
> };
> };
>
> - intc: interrupt-controller@17a00000 {
> - compatible = "arm,gic-v3";
> - #interrupt-cells = <3>;
> - interrupt-controller;
> - reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
> - <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
> - interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> - };
> -
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,sm8250-pdc", "qcom,pdc";
> reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>;
> @@ -596,85 +593,6 @@ spmi_bus: qcom,spmi@c440000 {
> #interrupt-cells = <4>;
> };
>
> - apps_rsc: rsc@18200000 {
> - label = "apps_rsc";
> - compatible = "qcom,rpmh-rsc";
> - reg = <0x0 0x18200000 0x0 0x10000>,
> - <0x0 0x18210000 0x0 0x10000>,
> - <0x0 0x18220000 0x0 0x10000>;
> - reg-names = "drv-0", "drv-1", "drv-2";
> - interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> - qcom,tcs-offset = <0xd00>;
> - qcom,drv-id = <2>;
> - qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
> - <WAKE_TCS 3>, <CONTROL_TCS 1>;
> -
> - rpmhcc: clock-controller {
> - compatible = "qcom,sm8250-rpmh-clk";
> - #clock-cells = <1>;
> - clock-names = "xo";
> - clocks = <&xo_board>;
> - };
> -
> - rpmhpd: power-controller {
> - compatible = "qcom,sm8250-rpmhpd";
> - #power-domain-cells = <1>;
> - operating-points-v2 = <&rpmhpd_opp_table>;
> -
> - rpmhpd_opp_table: opp-table {
> - compatible = "operating-points-v2";
> -
> - rpmhpd_opp_ret: opp1 {
> - opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
> - };
> -
> - rpmhpd_opp_min_svs: opp2 {
> - opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> - };
> -
> - rpmhpd_opp_low_svs: opp3 {
> - opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> - };
> -
> - rpmhpd_opp_svs: opp4 {
> - opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> - };
> -
> - rpmhpd_opp_svs_l1: opp5 {
> - opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> - };
> -
> - rpmhpd_opp_nom: opp6 {
> - opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> - };
> -
> - rpmhpd_opp_nom_l1: opp7 {
> - opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> - };
> -
> - rpmhpd_opp_nom_l2: opp8 {
> - opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
> - };
> -
> - rpmhpd_opp_turbo: opp9 {
> - opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> - };
> -
> - rpmhpd_opp_turbo_l1: opp10 {
> - opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> - };
> - };
> - };
> - };
> -
> - tcsr_mutex: hwlock@1f40000 {
> - compatible = "qcom,tcsr-mutex";
> - reg = <0x0 0x01f40000 0x0 0x40000>;
> - #hwlock-cells = <1>;
> - };
> -
> tlmm: pinctrl@f100000 {
> compatible = "qcom,sm8250-pinctrl";
> reg = <0 0x0f100000 0 0x300000>,
> @@ -690,6 +608,15 @@ tlmm: pinctrl@f100000 {
> wakeup-parent = <&pdc>;
> };
>
> + intc: interrupt-controller@17a00000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
> + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> timer@17c20000 {
> #address-cells = <2>;
> #size-cells = <2>;
> @@ -749,6 +676,79 @@ frame@17c2d000 {
> };
> };
>
> + apps_rsc: rsc@18200000 {
> + label = "apps_rsc";
> + compatible = "qcom,rpmh-rsc";
> + reg = <0x0 0x18200000 0x0 0x10000>,
> + <0x0 0x18210000 0x0 0x10000>,
> + <0x0 0x18220000 0x0 0x10000>;
> + reg-names = "drv-0", "drv-1", "drv-2";
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + qcom,tcs-offset = <0xd00>;
> + qcom,drv-id = <2>;
> + qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
> + <WAKE_TCS 3>, <CONTROL_TCS 1>;
> +
> + rpmhcc: clock-controller {
> + compatible = "qcom,sm8250-rpmh-clk";
> + #clock-cells = <1>;
> + clock-names = "xo";
> + clocks = <&xo_board>;
> + };
> +
> + rpmhpd: power-controller {
> + compatible = "qcom,sm8250-rpmhpd";
> + #power-domain-cells = <1>;
> + operating-points-v2 = <&rpmhpd_opp_table>;
> +
> + rpmhpd_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + rpmhpd_opp_ret: opp1 {
> + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
> + };
> +
> + rpmhpd_opp_min_svs: opp2 {
> + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
> + };
> +
> + rpmhpd_opp_low_svs: opp3 {
> + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> + };
> +
> + rpmhpd_opp_svs: opp4 {
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> + };
> +
> + rpmhpd_opp_svs_l1: opp5 {
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> + };
> +
> + rpmhpd_opp_nom: opp6 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> + };
> +
> + rpmhpd_opp_nom_l1: opp7 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> + };
> +
> + rpmhpd_opp_nom_l2: opp8 {
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
> + };
> +
> + rpmhpd_opp_turbo: opp9 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> + };
> +
> + rpmhpd_opp_turbo_l1: opp10 {
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> + };
> + };
> + };
> + };
> +
> cpufreq_hw: cpufreq@18591000 {
> compatible = "qcom,cpufreq-hw";
> reg = <0 0x18591000 0 0x1000>,
> --
> 2.26.1
>
^ permalink raw reply
* Re: [PATCH 1/6] arm64: dts: qcom: sm8150: add apps_smmu node
From: Jonathan Marek @ 2020-05-29 3:34 UTC (permalink / raw)
To: Bjorn Andersson
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20200529031520.GA1799770@builder.lan>
On 5/28/20 11:15 PM, Bjorn Andersson wrote:
> On Thu 28 May 20:02 PDT 2020, Jonathan Marek wrote:
>
>>
>>
>> On 5/28/20 10:52 PM, Bjorn Andersson wrote:
>>> On Sat 23 May 19:38 PDT 2020, Jonathan Marek wrote:
>>>
>>>> Add the apps_smmu node for sm8150. Note that adding the iommus field for
>>>> UFS is required because initializing the iommu removes the bypass mapping
>>>> that created by the bootloader.
>>>>
>>>
>>> Unrelated to the patch itself; how do you disable the splash screen on
>>> 8150? "fastboot oem select-display-panel none" doesn't seem to work for
>>> me on the MTP - and hence this would prevent my device from booting.
>>>
>>> Thanks,
>>> Bjorn
>>>
>>
>> I don't have a MTP, but on HDK855, "fastboot oem select-display-panel none"
>> combined with setting the physical switch to HDMI mode (which switches off
>> the 1440x2560 panel) gets it to not setup the display at all (just the
>> fastboot command isn't enough).
>>
>
> Okay, I don't think we have anything equivalent on the MTP, but good to
> know.
>
>> With HDK865 though that doesn't work and I have a hack to work around it
>> (writing 0 to INTF_TIMING_ENGINE_EN early on in boot will stop video mode
>> scanout and it won't crash).
>>
>
> Then we need to sort this out in the arm-smmu driver before we can
> enable the apps_smmu node on 8250. I did receive some guidance from Will
> on the subject and have started looking into this.
>
That's annoying because a lot depends on apps_mmu. GPU is an exception
with its own MMU but pretty much everything else uses apps_smmu (does it
make sense to add USB nodes if it won't work without apps_smmu?) Is this
something that will get resolved soon?
FWIW, I have another sm8250 board which does not need the workaround
(its bootloader does not set up the display). AFAIK modifying the
bootloader to not set up any display is a trivial modification (assuming
that's an option).
> Thanks,
> Bjorn
>
>>>> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
>>>> ---
>>>> arch/arm64/boot/dts/qcom/sm8150.dtsi | 91 ++++++++++++++++++++++++++++
>>>> 1 file changed, 91 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
>>>> index a36512d1f6a1..acb839427b12 100644
>>>> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
>>>> @@ -442,6 +442,8 @@ ufs_mem_hc: ufshc@1d84000 {
>>>> resets = <&gcc GCC_UFS_PHY_BCR>;
>>>> reset-names = "rst";
>>>> + iommus = <&apps_smmu 0x300 0>;
>>>> +
>>>> clock-names =
>>>> "core_clk",
>>>> "bus_aggr_clk",
>>>> @@ -706,6 +708,7 @@ usb_1_dwc3: dwc3@a600000 {
>>>> compatible = "snps,dwc3";
>>>> reg = <0 0x0a600000 0 0xcd00>;
>>>> interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>>>> + iommus = <&apps_smmu 0x140 0>;
>>>> snps,dis_u2_susphy_quirk;
>>>> snps,dis_enblslpm_quirk;
>>>> phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
>>>> @@ -742,6 +745,94 @@ spmi_bus: spmi@c440000 {
>>>> cell-index = <0>;
>>>> };
>>>> + apps_smmu: iommu@15000000 {
>>>> + compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
>>>> + reg = <0 0x15000000 0 0x100000>;
>>>> + #iommu-cells = <2>;
>>>> + #global-interrupts = <1>;
>>>> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
>>>> + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
>>>> + };
>>>> +
>>>> remoteproc_adsp: remoteproc@17300000 {
>>>> compatible = "qcom,sm8150-adsp-pas";
>>>> reg = <0x0 0x17300000 0x0 0x4040>;
>>>> --
>>>> 2.26.1
>>>>
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: sm8250: rename spmi node to spmi_bus
From: Bjorn Andersson @ 2020-05-29 3:26 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20200523132104.31046-1-jonathan@marek.ca>
On Sat 23 May 06:21 PDT 2020, Jonathan Marek wrote:
> The pm8150 dtsi files refer to it as spmi_bus, so change it.
>
Applied. Also removed "qcom," from the node name while we're poking at
the line.
Thanks,
Bjorn
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index 04c9c215ffcd..a273b99bf1e6 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -578,7 +578,7 @@ pdc: interrupt-controller@b220000 {
> interrupt-controller;
> };
>
> - spmi: qcom,spmi@c440000 {
> + spmi_bus: qcom,spmi@c440000 {
> compatible = "qcom,spmi-pmic-arb";
> reg = <0x0 0x0c440000 0x0 0x0001100>,
> <0x0 0x0c600000 0x0 0x2000000>,
> --
> 2.26.1
>
^ permalink raw reply
* Re: [PATCH v6 3/5] remoteproc: qcom: Update PIL relocation info on load
From: kbuild test robot @ 2020-05-29 3:06 UTC (permalink / raw)
To: Bjorn Andersson, Andy Gross, Ohad Ben-Cohen
Cc: kbuild-all, Rob Herring, linux-arm-msm, linux-remoteproc,
devicetree, linux-kernel, Vinod Koul
In-Reply-To: <20200527054850.2067032-4-bjorn.andersson@linaro.org>
[-- Attachment #1: Type: text/plain, Size: 5788 bytes --]
Hi Bjorn,
I love your patch! Perhaps something to improve:
[auto build test WARNING on next-20200526]
[also build test WARNING on v5.7-rc7]
[cannot apply to robh/for-next linus/master agross-msm/qcom/for-next remoteproc/for-next rpmsg/for-next hwspinlock/for-next v5.7-rc7 v5.7-rc6 v5.7-rc5]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Bjorn-Andersson/remoteproc-qcom-PIL-info-support/20200527-135911
base: b0523c7b1c9d0edcd6c0fe6d2cb558a9ad5c60a8
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp@intel.com>
All warnings (new ones prefixed by >>, old ones prefixed by <<):
>> drivers/remoteproc/qcom_pil_info.c:69:5: warning: no previous prototype for 'qcom_pil_info_store' [-Wmissing-prototypes]
69 | int qcom_pil_info_store(const char *image, phys_addr_t base, size_t size)
| ^~~~~~~~~~~~~~~~~~~
vim +/qcom_pil_info_store +69 drivers/remoteproc/qcom_pil_info.c
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 60
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 61 /**
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 62 * qcom_pil_info_store() - store PIL information of image in IMEM
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 63 * @image: name of the image
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 64 * @base: base address of the loaded image
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 65 * @size: size of the loaded image
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 66 *
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 67 * Return: 0 on success, negative errno on failure
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 68 */
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 @69 int qcom_pil_info_store(const char *image, phys_addr_t base, size_t size)
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 70 {
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 71 char buf[PIL_RELOC_NAME_LEN];
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 72 void __iomem *entry;
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 73 int ret;
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 74 int i;
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 75
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 76 mutex_lock(&reloc_mutex);
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 77 ret = qcom_pil_info_init();
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 78 if (ret < 0) {
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 79 mutex_unlock(&reloc_mutex);
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 80 return ret;
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 81 }
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 82
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 83 for (i = 0; i < _reloc.num_entries; i++) {
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 84 entry = _reloc.base + i * sizeof(struct pil_reloc_entry);
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 85
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 86 memcpy_fromio(buf, entry, PIL_RELOC_NAME_LEN);
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 87
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 88 /*
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 89 * An empty record means we didn't find it, given that the
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 90 * records are packed.
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 91 */
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 92 if (!buf[0])
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 93 goto found_unused;
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 94
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 95 if (!strncmp(buf, image, PIL_RELOC_NAME_LEN))
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 96 goto found_existing;
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 97 }
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 98
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 99 pr_warn("insufficient PIL info slots\n");
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 100 mutex_unlock(&reloc_mutex);
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 101 return -ENOMEM;
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 102
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 103 found_unused:
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 104 memcpy_toio(entry, image, PIL_RELOC_NAME_LEN);
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 105 found_existing:
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 106 writel(base, entry + offsetof(struct pil_reloc_entry, base));
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 107 writel(size, entry + offsetof(struct pil_reloc_entry, size));
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 108 mutex_unlock(&reloc_mutex);
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 109
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 110 return 0;
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 111 }
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 112 EXPORT_SYMBOL_GPL(qcom_pil_info_store);
41d96cc2fee2c1 Bjorn Andersson 2020-05-26 113
:::::: The code at line 69 was first introduced by commit
:::::: 41d96cc2fee2c1143685357ad2929be0a7cf5d0f remoteproc: qcom: Introduce helper to store pil info in IMEM
:::::: TO: Bjorn Andersson <bjorn.andersson@linaro.org>
:::::: CC: 0day robot <lkp@intel.com>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 72793 bytes --]
^ permalink raw reply
* Re: [PATCH] arm64: dts: qcom: sm8250: use dt-bindings defines for clocks
From: Bjorn Andersson @ 2020-05-29 3:22 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20200523131213.18653-1-jonathan@marek.ca>
On Sat 23 May 06:12 PDT 2020, Jonathan Marek wrote:
> Use the dt-bindings defines for qupv3_id_1 node's clocks.
>
Applied
Thanks,
Bjorn
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index 9c210fbac65e..04c9c215ffcd 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -292,7 +292,8 @@ qupv3_id_1: geniqup@ac0000 {
> compatible = "qcom,geni-se-qup";
> reg = <0x0 0x00ac0000 0x0 0x6000>;
> clock-names = "m-ahb", "s-ahb";
> - clocks = <&gcc 133>, <&gcc 134>;
> + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
> + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
> #address-cells = <2>;
> #size-cells = <2>;
> ranges;
> @@ -302,7 +303,7 @@ uart2: serial@a90000 {
> compatible = "qcom,geni-debug-uart";
> reg = <0x0 0x00a90000 0x0 0x4000>;
> clock-names = "se";
> - clocks = <&gcc 113>;
> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
> interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
> };
> --
> 2.26.1
>
^ permalink raw reply
* Re: [PATCH 3/3] ARM: dts: qcom: Add MikroTik RB3011
From: Bjorn Andersson @ 2020-05-29 3:20 UTC (permalink / raw)
To: Jonathan McDowell; +Cc: linux-arm-msm, devicetree, linux-kernel
In-Reply-To: <75390e66c9e6e36ddd42dc7f54cac28dfd7a24b9.1589824955.git.noodles@earth.li>
On Mon 18 May 11:10 PDT 2020, Jonathan McDowell wrote:
> This patch adds a DTS file for the MikroTik RouterBoard 3011, which is a
> 1U rackmount router based on the IPQ8064, supporting the serial UART,
> dual QCA8337 Gigabit ethernet switches, boot loader NOR and user LED
> device.
>
> Signed-off-by: Jonathan McDowell <noodles@earth.li>
Patch 2 and 3 picked up for 5.9
Thanks,
Bjorn
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/qcom-ipq8064-rb3011.dts | 308 ++++++++++++++++++++++
> 2 files changed, 309 insertions(+)
> create mode 100644 arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index e8dd99201397..e697a4bd7426 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -884,6 +884,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
> qcom-ipq4019-ap.dk07.1-c1.dtb \
> qcom-ipq4019-ap.dk07.1-c2.dtb \
> qcom-ipq8064-ap148.dtb \
> + qcom-ipq8064-rb3011.dtb \
> qcom-msm8660-surf.dtb \
> qcom-msm8960-cdp.dtb \
> qcom-msm8974-fairphone-fp2.dtb \
> diff --git a/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
> new file mode 100644
> index 000000000000..282b89ce3d45
> --- /dev/null
> +++ b/arch/arm/boot/dts/qcom-ipq8064-rb3011.dts
> @@ -0,0 +1,308 @@
> +// SPDX-License-Identifier: GPL-2.0
> +#include "qcom-ipq8064.dtsi"
> +#include <dt-bindings/input/input.h>
> +
> +/ {
> + model = "MikroTik RB3011UiAS-RM";
> + compatible = "mikrotik,rb3011";
> +
> + aliases {
> + serial0 = &gsbi7_serial;
> + ethernet0 = &gmac0;
> + ethernet1 = &gmac3;
> + mdio-gpio0 = &mdio0;
> + mdio-gpio1 = &mdio1;
> + };
> +
> + chosen {
> + bootargs = "loglevel=8 console=ttyMSM0,115200";
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory@0 {
> + reg = <0x42000000 0x3e000000>;
> + device_type = "memory";
> + };
> +
> + mdio0: mdio@0 {
> + status = "okay";
> + compatible = "virtual,mdio-gpio";
> + gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
> + <&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pinctrl-0 = <&mdio0_pins>;
> + pinctrl-names = "default";
> +
> + switch0: switch@10 {
> + compatible = "qca,qca8337";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dsa,member = <0 0>;
> +
> + pinctrl-0 = <&sw0_reset_pin>;
> + pinctrl-names = "default";
> +
> + reset-gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
> + reg = <0x10>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + switch0cpu: port@0 {
> + reg = <0>;
> + label = "cpu";
> + ethernet = <&gmac0>;
> + phy-mode = "rgmii-id";
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + label = "sw1";
> + };
> +
> + port@2 {
> + reg = <2>;
> + label = "sw2";
> + };
> +
> + port@3 {
> + reg = <3>;
> + label = "sw3";
> + };
> +
> + port@4 {
> + reg = <4>;
> + label = "sw4";
> + };
> +
> + port@5 {
> + reg = <5>;
> + label = "sw5";
> + };
> + };
> + };
> + };
> +
> + mdio1: mdio@1 {
> + status = "okay";
> + compatible = "virtual,mdio-gpio";
> + gpios = <&qcom_pinmux 11 GPIO_ACTIVE_HIGH>,
> + <&qcom_pinmux 10 GPIO_ACTIVE_HIGH>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pinctrl-0 = <&mdio1_pins>;
> + pinctrl-names = "default";
> +
> + switch1: switch@14 {
> + compatible = "qca,qca8337";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + dsa,member = <1 0>;
> +
> + pinctrl-0 = <&sw1_reset_pin>;
> + pinctrl-names = "default";
> +
> + reset-gpios = <&qcom_pinmux 17 GPIO_ACTIVE_LOW>;
> + reg = <0x10>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + switch1cpu: port@0 {
> + reg = <0>;
> + label = "cpu";
> + ethernet = <&gmac3>;
> + phy-mode = "sgmii";
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + label = "sw6";
> + };
> +
> + port@2 {
> + reg = <2>;
> + label = "sw7";
> + };
> +
> + port@3 {
> + reg = <3>;
> + label = "sw8";
> + };
> +
> + port@4 {
> + reg = <4>;
> + label = "sw9";
> + };
> +
> + port@5 {
> + reg = <5>;
> + label = "sw10";
> + };
> + };
> + };
> + };
> +
> + soc {
> + gsbi5: gsbi@1a200000 {
> + qcom,mode = <GSBI_PROT_SPI>;
> + status = "okay";
> +
> + spi4: spi@1a280000 {
> + status = "okay";
> + spi-max-frequency = <50000000>;
> +
> + pinctrl-0 = <&spi_pins>;
> + pinctrl-names = "default";
> +
> + cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_HIGH>;
> +
> + norflash: s25fl016k@0 {
> + compatible = "jedec,spi-nor";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + spi-max-frequency = <50000000>;
> + reg = <0>;
> +
> + partition@0 {
> + label = "RouterBoot";
> + reg = <0x0 0x40000>;
> + };
> + };
> + };
> + };
> +
> + gpio_keys {
> + compatible = "gpio-keys";
> + pinctrl-0 = <&buttons_pins>;
> + pinctrl-names = "default";
> +
> + button@1 {
> + label = "reset";
> + linux,code = <KEY_RESTART>;
> + gpios = <&qcom_pinmux 66 GPIO_ACTIVE_LOW>;
> + linux,input-type = <1>;
> + debounce-interval = <60>;
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + pinctrl-0 = <&leds_pins>;
> + pinctrl-names = "default";
> +
> + led@7 {
> + label = "rb3011:green:user";
> + gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>;
> + default-state = "off";
> + };
> + };
> +
> + };
> +};
> +
> +&gmac0 {
> + status = "okay";
> +
> + phy-mode = "rgmii";
> + qcom,id = <0>;
> + phy-handle = <&switch0cpu>;
> +
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> +};
> +
> +&gmac3 {
> + status = "okay";
> +
> + phy-mode = "sgmii";
> + qcom,id = <3>;
> + phy-handle = <&switch1cpu>;
> +
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> +};
> +
> +&gsbi7 {
> + status = "okay";
> + qcom,mode = <GSBI_PROT_I2C_UART>;
> +};
> +
> +&gsbi7_serial {
> + status = "okay";
> +};
> +
> +&qcom_pinmux {
> + buttons_pins: buttons_pins {
> + mux {
> + pins = "gpio66";
> + drive-strength = <16>;
> + bias-disable;
> + };
> + };
> +
> + leds_pins: leds_pins {
> + mux {
> + pins = "gpio33";
> + drive-strength = <16>;
> + bias-disable;
> + };
> + };
> +
> + mdio0_pins: mdio0_pins {
> + mux {
> + pins = "gpio0", "gpio1";
> + function = "gpio";
> + drive-strength = <8>;
> + bias-disable;
> + };
> + };
> +
> + mdio1_pins: mdio1_pins {
> + mux {
> + pins = "gpio10", "gpio11";
> + function = "gpio";
> + drive-strength = <8>;
> + bias-disable;
> + };
> + };
> +
> + sw0_reset_pin: sw0_reset_pin {
> + mux {
> + pins = "gpio16";
> + drive-strength = <16>;
> + function = "gpio";
> + bias-disable;
> + input-disable;
> + };
> + };
> +
> + sw1_reset_pin: sw1_reset_pin {
> + mux {
> + pins = "gpio17";
> + drive-strength = <16>;
> + function = "gpio";
> + bias-disable;
> + input-disable;
> + };
> + };
> +};
> --
> 2.20.1
>
^ permalink raw reply
* Re: [PATCH 1/6] arm64: dts: qcom: sm8150: add apps_smmu node
From: Bjorn Andersson @ 2020-05-29 3:15 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <d0908f34-a698-3449-35b9-7a98e9641295@marek.ca>
On Thu 28 May 20:02 PDT 2020, Jonathan Marek wrote:
>
>
> On 5/28/20 10:52 PM, Bjorn Andersson wrote:
> > On Sat 23 May 19:38 PDT 2020, Jonathan Marek wrote:
> >
> > > Add the apps_smmu node for sm8150. Note that adding the iommus field for
> > > UFS is required because initializing the iommu removes the bypass mapping
> > > that created by the bootloader.
> > >
> >
> > Unrelated to the patch itself; how do you disable the splash screen on
> > 8150? "fastboot oem select-display-panel none" doesn't seem to work for
> > me on the MTP - and hence this would prevent my device from booting.
> >
> > Thanks,
> > Bjorn
> >
>
> I don't have a MTP, but on HDK855, "fastboot oem select-display-panel none"
> combined with setting the physical switch to HDMI mode (which switches off
> the 1440x2560 panel) gets it to not setup the display at all (just the
> fastboot command isn't enough).
>
Okay, I don't think we have anything equivalent on the MTP, but good to
know.
> With HDK865 though that doesn't work and I have a hack to work around it
> (writing 0 to INTF_TIMING_ENGINE_EN early on in boot will stop video mode
> scanout and it won't crash).
>
Then we need to sort this out in the arm-smmu driver before we can
enable the apps_smmu node on 8250. I did receive some guidance from Will
on the subject and have started looking into this.
Thanks,
Bjorn
> > > Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> > > ---
> > > arch/arm64/boot/dts/qcom/sm8150.dtsi | 91 ++++++++++++++++++++++++++++
> > > 1 file changed, 91 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > > index a36512d1f6a1..acb839427b12 100644
> > > --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > > +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
> > > @@ -442,6 +442,8 @@ ufs_mem_hc: ufshc@1d84000 {
> > > resets = <&gcc GCC_UFS_PHY_BCR>;
> > > reset-names = "rst";
> > > + iommus = <&apps_smmu 0x300 0>;
> > > +
> > > clock-names =
> > > "core_clk",
> > > "bus_aggr_clk",
> > > @@ -706,6 +708,7 @@ usb_1_dwc3: dwc3@a600000 {
> > > compatible = "snps,dwc3";
> > > reg = <0 0x0a600000 0 0xcd00>;
> > > interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
> > > + iommus = <&apps_smmu 0x140 0>;
> > > snps,dis_u2_susphy_quirk;
> > > snps,dis_enblslpm_quirk;
> > > phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
> > > @@ -742,6 +745,94 @@ spmi_bus: spmi@c440000 {
> > > cell-index = <0>;
> > > };
> > > + apps_smmu: iommu@15000000 {
> > > + compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
> > > + reg = <0 0x15000000 0 0x100000>;
> > > + #iommu-cells = <2>;
> > > + #global-interrupts = <1>;
> > > + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
> > > + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
> > > + };
> > > +
> > > remoteproc_adsp: remoteproc@17300000 {
> > > compatible = "qcom,sm8150-adsp-pas";
> > > reg = <0x0 0x17300000 0x0 0x4040>;
> > > --
> > > 2.26.1
> > >
^ permalink raw reply
* Re: [PATCH 0/6] arm64: dts: qcom: smmu/USB nodes and HDK855/HDK865 dts
From: Jonathan Marek @ 2020-05-29 3:15 UTC (permalink / raw)
To: Bjorn Andersson
Cc: linux-arm-msm, Andy Gross,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Rob Herring
In-Reply-To: <20200529030505.GY279327@builder.lan>
On 5/28/20 11:05 PM, Bjorn Andersson wrote:
> On Sat 23 May 19:38 PDT 2020, Jonathan Marek wrote:
>
>> Add dts nodes for apps_smmu and USB for both sm8150 and sm8250.
>>
>> Also add initial dts files for HDK855 and HDK865, based on mtp dts, with a
>> few changes. Notably, the HDK865 dts has regulator config changed a bit based
>> on downstream (I think sm8250-mtp.dts is wrong and copied too much from sm8150).
>
> Can you please elaborate on this discrepancy? I do remember seeing
> something odd when looking at this, but it seems like I didn't document
> it anywhere...
>
> Thanks,
> Bjorn
>
Mainly there's a few regulators with different min/max voltage values.
For example with l16a, downstream has min/max 3024000/3304000 but
upstream sm8250-mtp has 2704000/2960000. I also added l18a.
>>
>> Jonathan Marek (6):
>> arm64: dts: qcom: sm8150: add apps_smmu node
>> arm64: dts: qcom: sm8250: add apps_smmu node
>> arm64: dts: qcom: sm8150: Add secondary USB and PHY nodes
>> arm64: dts: qcom: sm8250: Add USB and PHY device nodes
>> arm64: dts: qcom: add sm8150 hdk dts
>> arm64: dts: qcom: add sm8250 hdk dts
>>
>> arch/arm64/boot/dts/qcom/Makefile | 2 +
>> arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 461 ++++++++++++++++++++++++
>> arch/arm64/boot/dts/qcom/sm8150.dtsi | 180 +++++++++
>> arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 454 +++++++++++++++++++++++
>> arch/arm64/boot/dts/qcom/sm8250.dtsi | 287 +++++++++++++++
>> 5 files changed, 1384 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/sm8150-hdk.dts
>> create mode 100644 arch/arm64/boot/dts/qcom/sm8250-hdk.dts
>>
>> --
>> 2.26.1
>>
^ permalink raw reply
* Re: [PATCH 3/4] mailbox: qcom: Add ipq6018 apcs compatible
From: Bjorn Andersson @ 2020-05-29 3:11 UTC (permalink / raw)
To: Sivaprakash Murugesan
Cc: agross, robh+dt, jassisinghbrar, linux-arm-msm, devicetree,
linux-kernel
In-Reply-To: <1590583092-24290-4-git-send-email-sivaprak@codeaurora.org>
On Wed 27 May 05:38 PDT 2020, Sivaprakash Murugesan wrote:
> The Qualcomm ipq6018 has apcs block, add compatible for the same.
> Also, the apcs provides a clock controller functionality similar
> to msm8916 but the clock driver is different.
>
> Create a child platform device based on the apcs compatible for the
> clock controller functionality.
>
> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
> ---
> drivers/mailbox/qcom-apcs-ipc-mailbox.c | 23 ++++++++++++++---------
> 1 file changed, 14 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/mailbox/qcom-apcs-ipc-mailbox.c b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> index eeebafd..db3f9518 100644
> --- a/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> +++ b/drivers/mailbox/qcom-apcs-ipc-mailbox.c
> @@ -45,6 +45,13 @@ static const struct mbox_chan_ops qcom_apcs_ipc_ops = {
> .send_data = qcom_apcs_ipc_send_data,
> };
>
> +static const struct of_device_id apcs_clk_match_table[] = {
> + { .compatible = "qcom,ipq6018-apcs-apps-global", .data = "qcom,apss-ipq6018-clk", },
> + { .compatible = "qcom,msm8916-apcs-kpss-global", .data = "qcom-apcs-msm8916-clk", },
> + { .compatible = "qcom,qcs404-apcs-apps-global", .data = "qcom-apcs-msm8916-clk", },
> + {}
> +};
> +
> static int qcom_apcs_ipc_probe(struct platform_device *pdev)
> {
> struct qcom_apcs_ipc *apcs;
> @@ -54,11 +61,7 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
> void __iomem *base;
> unsigned long i;
> int ret;
> - const struct of_device_id apcs_clk_match_table[] = {
> - { .compatible = "qcom,msm8916-apcs-kpss-global", },
> - { .compatible = "qcom,qcs404-apcs-apps-global", },
> - {}
> - };
> + const struct of_device_id *clk_device;
>
> apcs = devm_kzalloc(&pdev->dev, sizeof(*apcs), GFP_KERNEL);
> if (!apcs)
> @@ -93,11 +96,12 @@ static int qcom_apcs_ipc_probe(struct platform_device *pdev)
> return ret;
> }
>
> - if (of_match_device(apcs_clk_match_table, &pdev->dev)) {
> + clk_device = of_match_device(apcs_clk_match_table, &pdev->dev);
I think you should replace the direct integer in qcom_apcs_ipc_of_match
with a small struct containing offset and the clock device's name -
allowing the latter to be omitted.
That avoids the apcs_clk_match_table being unreferenced when this is
compiled without CONFIG_OF and it removes the need for two of_device_id
arrays.
Regards,
Bjorn
> + if (clk_device) {
> apcs->clk = platform_device_register_data(&pdev->dev,
> - "qcom-apcs-msm8916-clk",
> - PLATFORM_DEVID_NONE,
> - NULL, 0);
> + clk_device->data,
> + PLATFORM_DEVID_NONE,
> + NULL, 0);
> if (IS_ERR(apcs->clk))
> dev_err(&pdev->dev, "failed to register APCS clk\n");
> }
> @@ -126,6 +130,7 @@ static const struct of_device_id qcom_apcs_ipc_of_match[] = {
> { .compatible = "qcom,sc7180-apss-shared", .data = (void *)12 },
> { .compatible = "qcom,sdm845-apss-shared", .data = (void *)12 },
> { .compatible = "qcom,sm8150-apss-shared", .data = (void *)12 },
> + { .compatible = "qcom,ipq6018-apcs-apps-global", .data = (void *)8 },
> { .compatible = "qcom,ipq8074-apcs-apps-global", .data = (void *)8 },
> {}
> };
> --
> 2.7.4
>
^ permalink raw reply
* Re: [PATCH v2 0/4] Spilt PCIe node to comply with hardware design
From: Ryder Lee @ 2020-05-29 3:05 UTC (permalink / raw)
To: chuanjia.liu
Cc: robh+dt, matthias.bgg, lorenzo.pieralisi, amurray, linux-pci,
linux-mediatek, devicetree, linux-kernel, linux-arm-kernel,
bhelgaas, jianjun.wang, yong.wu, srv_heupstream
In-Reply-To: <20200528061648.32078-1-chuanjia.liu@mediatek.com>
On Thu, 2020-05-28 at 14:16 +0800, chuanjia.liu@mediatek.com wrote:
> There are two independent PCIe controllers in MT2712/MT7622 platform,
> and each of them should contain an independent MSI domain.
>
> In current architecture, MSI domain will be inherited from the root
> bridge, and all of the devices will share the same MSI domain.
> Hence that, the PCIe devices will not work properly if the irq number
> which required is more than 32.
>
> Split the PCIe node for MT2712/MT7622 platform to fix MSI issue and
> comply with the hardware design.
>
> change note:
> v2: change the allocation of mt2712 PCIe MMIO space due to the allcation
> size is not right in v1.
>
> chuanjia.liu (4):
> dt-bindings: PCI: Mediatek: Update PCIe binding
> PCI: mediatek: Use regmap to get shared pcie-cfg base
> arm64: dts: mediatek: Split PCIe node for MT2712/MT7622
> ARM: dts: mediatek: Update mt7629 PCIe node
>
> .../bindings/pci/mediatek-pcie-cfg.yaml | 38 +++++
> .../devicetree/bindings/pci/mediatek-pcie.txt | 144 +++++++++++-------
> arch/arm/boot/dts/mt7629-rfb.dts | 3 +-
> arch/arm/boot/dts/mt7629.dtsi | 23 +--
> arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 75 +++++----
> .../dts/mediatek/mt7622-bananapi-bpi-r64.dts | 16 +-
> arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 6 +-
> arch/arm64/boot/dts/mediatek/mt7622.dtsi | 68 ++++++---
> drivers/pci/controller/pcie-mediatek.c | 25 ++-
> 9 files changed, 258 insertions(+), 140 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie-cfg.yaml
>
> --
> 2.18.0
>
>
For the series:
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
^ permalink raw reply
* Re: [PATCH 0/6] arm64: dts: qcom: smmu/USB nodes and HDK855/HDK865 dts
From: Bjorn Andersson @ 2020-05-29 3:05 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, Andy Gross,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Rob Herring
In-Reply-To: <20200524023815.21789-1-jonathan@marek.ca>
On Sat 23 May 19:38 PDT 2020, Jonathan Marek wrote:
> Add dts nodes for apps_smmu and USB for both sm8150 and sm8250.
>
> Also add initial dts files for HDK855 and HDK865, based on mtp dts, with a
> few changes. Notably, the HDK865 dts has regulator config changed a bit based
> on downstream (I think sm8250-mtp.dts is wrong and copied too much from sm8150).
Can you please elaborate on this discrepancy? I do remember seeing
something odd when looking at this, but it seems like I didn't document
it anywhere...
Thanks,
Bjorn
>
> Jonathan Marek (6):
> arm64: dts: qcom: sm8150: add apps_smmu node
> arm64: dts: qcom: sm8250: add apps_smmu node
> arm64: dts: qcom: sm8150: Add secondary USB and PHY nodes
> arm64: dts: qcom: sm8250: Add USB and PHY device nodes
> arm64: dts: qcom: add sm8150 hdk dts
> arm64: dts: qcom: add sm8250 hdk dts
>
> arch/arm64/boot/dts/qcom/Makefile | 2 +
> arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 461 ++++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/sm8150.dtsi | 180 +++++++++
> arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 454 +++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 287 +++++++++++++++
> 5 files changed, 1384 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sm8150-hdk.dts
> create mode 100644 arch/arm64/boot/dts/qcom/sm8250-hdk.dts
>
> --
> 2.26.1
>
^ permalink raw reply
* Re: [PATCH 6/6] arm64: dts: qcom: add sm8250 hdk dts
From: Bjorn Andersson @ 2020-05-29 3:03 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20200524023815.21789-7-jonathan@marek.ca>
On Sat 23 May 19:38 PDT 2020, Jonathan Marek wrote:
> Add initial HDK865 dts, based on sm8250-mtp, with a few changes.
> Notably, regulator configs are changed a bit.
>
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 454 ++++++++++++++++++++++++
> 2 files changed, 455 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sm8250-hdk.dts
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index e5dbd8b63951..4649e8bc5034 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -24,6 +24,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sm8250-hdk.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
> diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
> new file mode 100644
> index 000000000000..d35014bf4f81
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
> @@ -0,0 +1,454 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2020, The Linux Foundation. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include "sm8250.dtsi"
> +#include "pm8150.dtsi"
> +#include "pm8150b.dtsi"
> +#include "pm8150l.dtsi"
> +
> +/ {
> + model = "Qualcomm Technologies, Inc. SM8250 HDK";
> + compatible = "qcom,sm8250-hdk";
compatible = "qcom,sm8250-hdk", "qcom,sm8250";
Apart from that this looks good!
Thanks,
Bjorn
^ permalink raw reply
* Re: [PATCH 5/6] arm64: dts: qcom: add sm8150 hdk dts
From: Bjorn Andersson @ 2020-05-29 3:01 UTC (permalink / raw)
To: Jonathan Marek
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20200524023815.21789-6-jonathan@marek.ca>
On Sat 23 May 19:38 PDT 2020, Jonathan Marek wrote:
> Add initial HDK855 dts, based on sm8150-mtp, with a few changes.
>
Happy to see this on the list Jonathan, just some minor things on the
remoteproc nodes below.
> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 1 +
> arch/arm64/boot/dts/qcom/sm8150-hdk.dts | 461 ++++++++++++++++++++++++
> 2 files changed, 462 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sm8150-hdk.dts
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index cc103f7020fd..e5dbd8b63951 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -22,6 +22,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r3.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += sm8250-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
> diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts
[..]
> +/ {
> + model = "Qualcomm Technologies, Inc. SM8150 HDK";
> + compatible = "qcom,sm8150-hdk";
> +
> + aliases {
> + serial0 = &uart2;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + vph_pwr: vph-pwr-regulator {
> + compatible = "regulator-fixed";
> + regulator-name = "vph_pwr";
> + regulator-min-microvolt = <3700000>;
> + regulator-max-microvolt = <3700000>;
> + };
> +
> + /*
> + * Apparently RPMh does not provide support for PM8150 S4 because it
> + * is always-on; model it as a fixed regulator.
> + */
One day we should stop being surprised by this and drop the "Apparently"
from this comment ;)
> + vreg_s4a_1p8: pm8150-s4 {
> + compatible = "regulator-fixed";
> + regulator-name = "vreg_s4a_1p8";
> +
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +
> + regulator-always-on;
> + regulator-boot-on;
> +
> + vin-supply = <&vph_pwr>;
> + };
[..]
> +&remoteproc_adsp {
> + status = "okay";
It would be nice to see a
firmware-name = "qcom/sm8150/adsp.mbn";
here. Because if we ever end up pushing firmware to linux-firmware this
DTB would continue to work.
Use https://github.com/andersson/pil-squasher to get mbn files out of
the mdt+bXX files for your testing (or just rename/symlink the mdt to
mbn for now).
> +};
> +
> +&remoteproc_cdsp {
> + status = "okay";
firmware-name = "qcom/sm8150/cdsp.mbn";
> +};
> +
> +&remoteproc_slpi {
> + status = "okay";
firmware-name = "qcom/sm8150/slpi.mbn";
Regards,
Bjorn
> +};
> +
> +&tlmm {
> + gpio-reserved-ranges = <0 4>, <126 4>;
> +};
> +
> +&uart2 {
> + status = "okay";
> +};
> +
> +&ufs_mem_hc {
> + status = "okay";
> +
> + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>;
> +
> + vcc-supply = <&vreg_l10a_2p5>;
> + vcc-max-microamp = <750000>;
> + vccq-supply = <&vreg_l9a_1p2>;
> + vccq-max-microamp = <700000>;
> + vccq2-supply = <&vreg_s4a_1p8>;
> + vccq2-max-microamp = <750000>;
> +};
> +
> +&ufs_mem_phy {
> + status = "okay";
> +
> + vdda-phy-supply = <&vdda_ufs_2ln_core_1>;
> + vdda-max-microamp = <90200>;
> + vdda-pll-supply = <&vreg_l3c_1p2>;
> + vdda-pll-max-microamp = <19000>;
> +};
> +
> +&usb_1_hsphy {
> + status = "okay";
> + vdda-pll-supply = <&vdd_usb_hs_core>;
> + vdda33-supply = <&vdda_usb_hs_3p1>;
> + vdda18-supply = <&vdda_usb_hs_1p8>;
> +};
> +
> +&usb_2_hsphy {
> + status = "okay";
> + vdda-pll-supply = <&vdd_usb_hs_core>;
> + vdda33-supply = <&vdda_usb_hs_3p1>;
> + vdda18-supply = <&vdda_usb_hs_1p8>;
> +};
> +
> +&usb_1_qmpphy {
> + status = "okay";
> + vdda-phy-supply = <&vreg_l3c_1p2>;
> + vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
> +};
> +
> +&usb_2_qmpphy {
> + status = "okay";
> + vdda-phy-supply = <&vreg_l3c_1p2>;
> + vdda-pll-supply = <&vdda_usb_ss_dp_core_1>;
> +};
> +
> +&usb_1 {
> + status = "okay";
> +};
> +
> +&usb_2 {
> + status = "okay";
> +};
> +
> +&usb_1_dwc3 {
> + dr_mode = "peripheral";
> +};
> +
> +&usb_2_dwc3 {
> + dr_mode = "host";
> +};
> --
> 2.26.1
>
^ permalink raw reply
* Re: [PATCH 1/6] arm64: dts: qcom: sm8150: add apps_smmu node
From: Jonathan Marek @ 2020-05-29 3:02 UTC (permalink / raw)
To: Bjorn Andersson
Cc: linux-arm-msm, Andy Gross, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list
In-Reply-To: <20200529025246.GV279327@builder.lan>
On 5/28/20 10:52 PM, Bjorn Andersson wrote:
> On Sat 23 May 19:38 PDT 2020, Jonathan Marek wrote:
>
>> Add the apps_smmu node for sm8150. Note that adding the iommus field for
>> UFS is required because initializing the iommu removes the bypass mapping
>> that created by the bootloader.
>>
>
> Unrelated to the patch itself; how do you disable the splash screen on
> 8150? "fastboot oem select-display-panel none" doesn't seem to work for
> me on the MTP - and hence this would prevent my device from booting.
>
> Thanks,
> Bjorn
>
I don't have a MTP, but on HDK855, "fastboot oem select-display-panel
none" combined with setting the physical switch to HDMI mode (which
switches off the 1440x2560 panel) gets it to not setup the display at
all (just the fastboot command isn't enough).
With HDK865 though that doesn't work and I have a hack to work around it
(writing 0 to INTF_TIMING_ENGINE_EN early on in boot will stop video
mode scanout and it won't crash).
>> Signed-off-by: Jonathan Marek <jonathan@marek.ca>
>> ---
>> arch/arm64/boot/dts/qcom/sm8150.dtsi | 91 ++++++++++++++++++++++++++++
>> 1 file changed, 91 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
>> index a36512d1f6a1..acb839427b12 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
>> @@ -442,6 +442,8 @@ ufs_mem_hc: ufshc@1d84000 {
>> resets = <&gcc GCC_UFS_PHY_BCR>;
>> reset-names = "rst";
>>
>> + iommus = <&apps_smmu 0x300 0>;
>> +
>> clock-names =
>> "core_clk",
>> "bus_aggr_clk",
>> @@ -706,6 +708,7 @@ usb_1_dwc3: dwc3@a600000 {
>> compatible = "snps,dwc3";
>> reg = <0 0x0a600000 0 0xcd00>;
>> interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
>> + iommus = <&apps_smmu 0x140 0>;
>> snps,dis_u2_susphy_quirk;
>> snps,dis_enblslpm_quirk;
>> phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
>> @@ -742,6 +745,94 @@ spmi_bus: spmi@c440000 {
>> cell-index = <0>;
>> };
>>
>> + apps_smmu: iommu@15000000 {
>> + compatible = "qcom,sdm845-smmu-500", "arm,mmu-500";
>> + reg = <0 0x15000000 0 0x100000>;
>> + #iommu-cells = <2>;
>> + #global-interrupts = <1>;
>> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
>> + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
>> + };
>> +
>> remoteproc_adsp: remoteproc@17300000 {
>> compatible = "qcom,sm8150-adsp-pas";
>> reg = <0x0 0x17300000 0x0 0x4040>;
>> --
>> 2.26.1
>>
^ permalink raw reply
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